DECODER CIRCUIT

Abstract: A decoder circuit comprises a plurality of signal conductors (X₀ - X₇ , DL), first potential setting units (Tpc) for setting a potential of the signal conductors (X₀ - X₇ , DL) to a first potential, second potential setting units (Cs) for maintaining a potential of one signal conductor (X₀ - X₇) at the first potential and bringing a potential of the remaining signal conductors (X₀ - X₇ , DL) to a second potential, and a respective transfer transistor (T₀ - T₇) provided for each signal conductor (X₀ - X₇). A gate electrode of each transfer transistor (T₀ - T₇) is connected to its respective signal conductor (X₀ - X₇), a source electrode thereof is connected to another signal conductor (X₁ - X₇ , DL), and one transfer transistor (T₀ - T₇) is switched ON and a decoded output signal is output when a gate potential of that transfer transistor (T₀ - T₇) is maintained at the first potential and a source potential thereof is brought to the second potential. Therefore, only one output signal conductor (X₀ - X₇) is selected during a decoder operation without using a discharge detecting circuit of a nonselected output signal conductor and a timing signal, and thus an operation speed of the decoder circuit is much higher and the decoding circuit has a simpler construction and is suitable as a large scale integration circuit.

Description: The present invention relates to a decoder circuit, more particularly, to an output portion or a buffer portion of a dynamic type decoder circuit used for selecting a memory cell of a memory device. In the prior art, a decoder circuit is used for decoding an input signal, and selecting and outputting a signal on one of a plurality of signal conductors. A decoder circuit is used for various purposes, but in the example given below, the decoder circuit is used for selecting a memory cell of a memory such as a ROM (Read Only Memory) or PLA (Programmable Logic Array), and the like. For example, one type of decoder circuit comprises a decoder portion, a buffer portion, and a control portion. The decoder portion includes input signal conductors and output signal conductors, the input signal conductors being complemental signal conductors and the output signal conductors being provided so as to cross the input signal conductors. A cell transistor is provided for each crossed portion of the input signal conductors and the output signal conductors, and one of the output signal conductors is selected in accordance with a decoded logic of the contents of the input signals. Output portions of the output signal conductors are provided, for example, with NAND circuits, and the input terminal of each of the NAND circuits is connected to one of the output signal conductors and the other input terminal thereof is supplied with a timing signal. This timing signal is input to the other input terminals thereof after changing a potential of the output signal conductors, except one selected output signal conductor, to a low level. Namely, the timing signal is used to avoid a selection error, and this timing signal is output from a control portion in the decoder circuit. The control portion comprises, for example, an inverter having an input supplied with a potential of a dummy signal conductor wired in the same manner as the output signal conductors, a NAND circuit, and an inverter. The above type of decoder circuit has problems in that the timing signal should be applied to the NAND circuit, and the word lines should be driven by the timing signal through the NAND circuit in the output portions of the output signal conductors. Namely, the timing signal should be generated after all unselected output signal conductors have been fully discharged. Therefore, an output timing of the timing signal must include a time margin, taking into consideration a discharge time for fully discharging an electrical charge in each of the output signal conductors, whereby a drive timing of the word line corresponding to the selected output signal conductor is delayed and thus hinders a high speed operation of the decoder circuit. Further, the NAND circuits in the output portions of the output signal conductors and the control portions must be provided, and thus the construction of the decoder circuit becomes complicated. According to the present invention, there is provided a decoder circuit including a plurality of signal conductors, a first potential setting means connected to said signal conductors and operable to set a potential of said signal conductors at a first potential, and a second potential setting means connected to said signal conductors and operable to maintain a potential of one of said signal conductors at said first potential and to reduce a potential of remaining said signal conductors to a second potential, characterized in that said decoder circuit comprises: a respective transfer transistor provided for each signal conductor, a gate electrode of each transfer transistor being connected to the corresponding signal conductor, a source electrode thereof being connected to another signal conductor, whereby in use, one of said transfer transistors is switched ON and a decoded output signal output when a gate potential of that transfer transistor is maintained at said first potential and a source potential thereof is brought to said second potential. An embodiment of the present invention may provide a decoder circuit having a simple configuration, a high speed operation and stable operation, and suitable for application to a large scale integration circuit. Reference will now be made, by way of example, to the accompanying drawings in which: Figure 1 is a block diagram showing one example of a decoder circuit applied to a read only memory; Fig. 2 is a circuit diagram showing one example of the decoder circuit shown in Fig. 1; Fig. 3 is a timing chart explaining an operation of the decoder circuit shown in Fig. 2; Fig. 4 is a block diagram showing one embodiment of a decoder circuit according to the present invention; Fig. 5 is a circuit diagram showing one embodiment of the decoder circuit as shown in Fig. 4; Fig. 6 is a circuit diagram showing a modification of the embodiment of the decoder circuit as shown in Fig. 5; Fig. 7 is a circuit diagram showing another modification of the embodiment of the decoder circuit as shown in Fig. 5; and, Fig. 8 is a timing chart explaining an operation of the circuit shown in Fig. 5. A decoder circuit is used for decoding input signals, and selecting and outputting one of a plurality of signal conductors. The decoder circuit is used for various purposes, but in the given below example, the decoder circuit is used for selecting a memory cell of a memory such as a ROM (Read Only Memory), and the like. First, an existing decoder circuit applied to a read only memory is explained with reference to Figs. 1, 2, and 3. Figure 1 is a block diagram showing one example of an existing decoder circuit applied to a read only memory. As shown in Fig. 1, the decoder circuit 101 comprises a decoder portion 111, i.e., an AND-term portion, a buffer portion 112, and a control portion 113. The decoder circuit 101 is connected to a bit block 102, i.e., an OR-term portion, and selects one word line of the OR-term portion in accordance with an address signal of an input signal A₀ - A₂ , so that a bit data of an output signal is output from the bit block 102. Figure 2 is a circuit diagram showing one example of the decoder circuit as shown in Fig. 1. This decoder circuit 101 is a dynamic type circuit wherein input signal conductors Y₀ - Y₂ are constructed by complemental signal conductors such as a pair of Y₀ and Y₀ , a pair of Y₁ and Y₁ , and a pair of Y₂ and Y₂ . Output signal conductors X₀ - X₇ are provided so as to cross the input signal conductors Y₀ - Y₂ . A cell transistor Cs is provided for each crossed portion of the input signal conductors Y₀ - Y₂ and the output signal conductors X₀ - X₇ , and one of the output signal conductors is selected in accordance with a decoded logic of the contents of the input signals A₀ - A₂. Note, each cell transistor Cs is formed by an N-channel MIS transistor. In the decoder portion 111, input portions of the input signal conductors Y₀ - Y₂ are provided with NAND circuits NY₀ - NY₂′ to which input signals A₀ - A₂ , inverted signals A₀ - A₂ , of the input signals A₀ - A₂ , and a clock signal  are applied. Namely, one input terminal of the NAND circuits NY₀ , NY₁ , and NY₂ is supplied with the input signals A₀ , A₁ , and A₂ , respectively, one input terminal of the NAND circuits NY₀′, NY₁′ and NY₂′ is supplied with the inverted input signals A₀ , A₁ , and A₂ inverted by inverter circuits INV₀ , INV₁ , and INV₂ respectively, and the other input terminals of the all of the NAND circuits NY₀ - NY₂′ are supplied with the clock signal . An output terminal of each of the NAND circuits NY₀ - NY₂′ is connected to the corresponding input signal conductors Y₀ - Y₂ through each of drive transistors D IN which are P-channel type MIS transistors, respectively. In the buffer portion 112, output portions of the output signal conductors X₀ - X₇ are provided with NAND circuits NX₀- NX₇ , and one input terminal of each of the NAND circuits NX₀ - NX₇ is connected to one of the output signal conductors X₀ - X₇. The other input terminal of each of the NAND circuits NX₀ - NX₇ is supplied with a timing signal Tc after changing a potential of the output signal conductors, except one selected output signal conductor, to a low level. Namely, the timing signal Tc is used to avoid a selection error, and this timing signal is output from a control circuit 113 in the decoder circuit 101. The control circuit 113 comprises an inverter INV₃ having an input supplied with a potential of a dummy signal conductor DL wired in the same manner as the output signal conductance X₀ - X₇ , a NAND circuit N, and an inverter INV₄. The other sides of the input signal conductors Y₀ - Y₂ are provided with discharge transistors T DC which are switched ON while the clock signal  is at a low level. These transistors are N-channel type MIS transistors, and gate electrodes thereof are supplied with an inverted clock signal  by an inverter IV₅. The other sides of the output signal conductors X₀ - X₇ are provided with precharge transistors Tpc which are driven by the clock signal . The precharge transistors Tpc, which are P-channel type MIS transistors, are switched ON when the clock signal  is at a high level, and the output signal conductors X₀ - X₇ and the dummy signal conductor DL are precharged to a power source potential V DD . The output terminals of the NAND circuits NX₀ - NX₇ are connected to gate electrodes of the output transistors TR₀ - TR₇ (P-channel type MIS transistors), respectively. Note, the drain electrodes of the output transistors TR₀ - TR₇ serve as output terminals O₀ - O₇ in this decoder circuit 101, and are connected, for example, to a cell array of the ROM 102 through word lines WD₀ - WD₇. The above described decoder circuit is formed by a C-MIS circuit, as shown in Fig. 2, wherein transistors shown by a thick line are P-channel type MIS (P-MIS) transistors and a transistor shown by a normal line is an N-channel type MIS (N-MIS) transistor, Note, an N-MIS transistor is switched ON when an input signal thereof is at a high level, and a P-MIS transistor is switched ON when an input signal thereof is at a low level. Next, the operation of the above circuit is explained with reference to Fig. 3. A period during which the clock signal  is at a low level corresponds to a reset period of the decoder circuit 101, and a period during which the clock signal  is at a high level corresponds to an active period of the decoder circuit 101. First, in the period during which the clock signal  is at a low level, the precharge transistors Tpc and the discharge transistors T DC are switched ON, all of the input signal conductors Y₀ - Y₂ are discharged, and all of the output signal conductors X₀ - X₇ are precharged. In this case, all output signals of the NAND circuits NY₀ - NY₂′ are at a high level, and thus all of the input transistors D IN are switched OFF. When the clock signal  goes from the low level to a high level, all of the precharge transistors Tpc and all of the discharge transistors T DC are switched OFF, and the input signal conductors Y₀ - Y₂ are at a high level or a low level in accordance with address signals (input signals) A₀ , A₁ , and A₂. As a result, one of the output signal conductors X₀ - X₇ is maintained at the precharged level, and the other output signal conductors are discharged through the cell transistors Cs. For example, when the input signal A₀ is at a low level, A₁ is at a low level and A₂ is at a high level, the input signal conductors Y₀ , Y₁ , and Y₂ are brought to a low level, and the other signal conductors are brought to a high level. Consequently, only one output signal conductor X₄ is selected by the above potential relationship of the input signals A₀ , A₁ and A₂ and a connection relationship of the cell transistors Cs. In this case, a potential of the selected output signal conductor X₄ is maintained at the high level, and the other output signal conductors X₀ - X₃ and X₅ - X₇ are discharged and brought to a low level by each corresponding cell transistor Cs. Next, the timing signal Tc (high level) is input to the NAND circuits NX₀ - NX₇ , after all of the unselected output signal conductors X₀ - X₃ and X₅ - X₇ are discharged, and thus an input of only the NAND circuit NX₄ corresponding to the selected output signal conductor X₄ is brought to a high level and a low level signal is output to an output transistor TR₄. Consequently, only the output transistor TR₄ is switched ON, and a word line WL₄ is driven. The timing for generating the timing signal Tc is determined by a discharge time of the dummy signal conductor DL. Namely, the dummy signal conductor DL has the longest discharge time (or longer than the longest discharge time) among the output signal conductors X₀ - X₇. Note, the dummy signal conductor DL is not selected (i.e., is always discharged) regardless of the address signals A₀ - A₂. As a result a potential of the dummy signal conductor DL is always changed to a low level in a decoding operation, when an output signal conductor is selected. In the control portion 113, this signal of the dummy signal conductor DL is applied to an input of the inverter IV₃ , and when the other input of a NAND circuit N is supplied with a high level enable signal EN from another circuit (not shown in the drawing) a high level timing signal Tc is output from an inverter IV₄. As described above, the timing signal Tc must be output after it is confirmed that all of the unselected output signal conductors X₀ - X₃ and X₅ - X₇ are fully discharged, since an error may be generated such that a plurality of output signal conductors are selected when the timing signal Tc is applied before the discharge operation described above is completed. As described above, this type of decoder circuit 101 has problems in that the timing signal Tc should be applied to the NAND circuits and the word lines must be driven by the timing signal Tc through the NAND circuits NX₀ - NX₇. Namely, as understood from Fig. 3, the timing signal Tc must be generated after the all of the nonselected output signal conductors X₀ - X₃ and X₅ - X₇ are fully discharged. Therefore, an output timing of the timing signal Tc must include a time margin, taking into consideration a discharge time for fully discharging an electrical charge in each of the output signal conductors X₀ - X₇ , and thus the drive timing of the word line WL₄ corresponding to the selected output signal conductor X₄ is delayed and hinders a high speed operation of the decoder circuit. Further, in the decoder circuit 101, the NAND circuits NX₀ - NX₇ of the buffer portion 112 and the control portion 113 including the inverter INV₃ , the NAND circuit N, and the inverter INV₄ must be provided and thus the construction of the decoder circuit becomes complicated. Furthermore, when C-MIS transistors are used, a NAND circuit is formed by four transistors, and thus a problem arises in a pattern layout of the decoder circuit, when the decoder circuit is used by a large scale integration circuit. Namely, when the four transistors of the NAND circuit are provided in parallel with the input signal conductors, a large space is occupied by these four transistors, but if the four transistors of the NAND circuit are provided in series, the wiring process for connecting these four transistors must be carried out. Therefore, a problem arises whenever a large a number of transistors is used for the NAND circuit. For example, when used as an address decoder of a ROM, the scale of the decoder circuit as a peripheral circuit is too large to realize the purpose of making a memory cell small, and thus it is difficult to insert the buffer portion in a small space between two adjacent signal conductors or between each pitch of neighboring word lines. The present invention may provide a decoder circuit having a simple configuration, a high speed and stable operation, and suitable for application to a large scale integration circuit. Below, an embodiment of the present invention will be explained with reference to the drawings. Figure 4 is a block diagram showing one embodiment of a decoder circuit according to the present invention. As shown in Fig. 4, the decoder circuit 1 comprises a decoder portion 11, i.e., an AND-term portion, and a buffer portion 12. Namely, the control portion of the existing type decoder circuit is not needed for the present embodiment. The decoder circuit 1 is connected to a bit block 2, i.e., an OR-term portion, and selects one word line of the OR-term portion in accordance with an address signal of an input signal A₀ - A₂ , whereby bit data of an output signal is output from the bit block 2. A circuit diagram of the embodiment according to the present invention is shown in Fig. 5. In this embodiment, the same portions as shown in the existing type decoder circuit of Fig. 2 are indicated by the same references. In this decoder circuit 1, input signal conductors Y₀ - Y₂ are complemental signal conductors such as a pair of Y₀ and Y₀ , a pair of Y₁ and Y₁ , and a pair of Y₂ and Y₂ . Output signal conductors X₀ - X₇ are provided so as to cross the input signal conductors Y₀ - Y₂ . A cell transistor Cs is provided for each crossed portion of the input signal conductors Y₀ - Y₂ and the output signal conductors X₀ - X₇ , and one of the output signal conductors is selected in accordance with a decoded logic of the contents of the input signals A₀ - A₂. Note, each cell transistor Cs is formed by an N-channel MIS transistor. In the decoder portion 11, input portions of the input signal conductors Y₀ - Y₂ are provided with NAND circuits NY₀ - NY₂′ to which input signals A₀ - A₂ , inverted signals A₀ - A₂ of the input signals A₀ - A₂ , and a clock signal  are applied. Namely, each input terminal of the NAND circuits NY₀ , NY₁ and NY₂ is supplied with the input signals A₀ , A₁ , and A₂ , each input terminal of the NAND circuits NY₀′, NY₁′ and NY₂′ is supplied with the inverted input signals A₀ , A₁ and A₂ inverted by inverter circuits INV₀ , INV₁ and INV₂ , and the other input terminals of all of the NAND circuits NY₀ - NY₂′ are supplied with the clock signal . An output terminal of each of the NAND circuits NY₀ - NY₂′ is connected to the corresponding input signal conductors Y₀ - Y₂ through each of drive transistors D IN which are P-channel type MIS transistors, respectively. In the above description, the decoder portion 11 of the decoder circuit 1 of the present embodiment has the same configuration as the existing circuit, but in the present embodiment, the configuration of the buffer portion 12 is simpler than that of the existing buffer portion, the present decoder circuit has a high speed and stable operation, and the present embodiment does not need the control portion necessary in the existing decoder circuit. As shown in Fig. 5, in the buffer portion 12, an output end of each of the output signal conductors X₀ - X₇ is connected to a gate electrode of a corresponding transfer transistor T₀ - T₇ provided for each of the output signal conductors X₀ - X₇ , and a source electrode of each of the transfer transistors T₀ - T₇ is connected to a neighboring output signal conductor thereof. For example, in a transfer transistor T₀ , a gate electrode of the transfer transistor T₀ is connected to a corresponding output signal conductor X₀ , and a source electrode thereof is connected to a neighboring output signal conductor X₁. Similarly, in a transfer transistor T₁ , a gate electrode of the transfer transistor T₁ is connected to a corresponding output signal conductor X₁ , and a source electrode thereof is connected to a neighboring output signal conductor X₂. Note, a dummy signal conductor DL is discharged to a low level regardless of the address signals A₀ - A₂ , during a decoder operation, and thus the dummy signal conductor DL can be connected to a source electrode of a transfer transistor T₇. A drain electrode of each of the transfer transistors T₀ - T₇ is connected to a gate electrode of each corresponding output transistor TR₀ - TR₇ and a drain electrode of each corresponding preset transistor PRT₀ - PRT₇ , respectively. Namely, a drain electrode of the transfer transistor T₀ is connected to a gate electrode of a output transistor TR₀ and a drain electrode of a preset transistor PRT₀ , and a drain electrode of the transfer transistor T₁ is connected to a gate electrode of a output transistor TR₁ and a drain electrode of a preset transistor PRT₁. A source electrode of each preset transistor PRT₀ - PRT₇ and a source electrode of each output transistor TR₀ - TR₇ are supplied with a power supply potential V DD . A drain electrode of each output transistor TR₀ - TR₇ is connected to each corresponding output terminal O₀ - O₇. Note, in the buffer portion 12 of the decoder circuit 1, only three transistors, i.e., a transfer transistor T₀ - T₇ , a preset transistor PRT₀ - PRT₇ and an output transistor TR₀ - TR₇ , are needed, and thus these three transistors can be provided in a small space between two adjacent signal conductors. Namely, a space between two adjacent signal conductors or each pitch of neighboring word lines is made smaller. Note, the transfer transistors T₀ - T₇ are N-channel type MIS transistors, and the preset transistors PRT₀ - PRT₇ and the output transistors TR₀ - TR₇ are P-channel type MIS transistors. Further, the output terminals O₀ - O₇ are connected to word lines WL₀ - WL₇ of the bit block 2. The bit block 2 is, for example, a read only memory having a plurality of word lines (WL₁ - WL₇), a plurality of bit lines and a plurality of memory cells. The other sides of the input signal conductors Y₀ - Y₂ are provided with discharge transistors T DC which are switched ON while the clock signal  is at a low level. These transistors are N-channel type MIS transistors, and the gate electrodes thereof are supplied with an inverted clock signal  by an inverter IV₅. The other sides of the output signal conductors X₀ - X₇ are provided with precharge transistors Tpc driven by the clock signal . The precharge transistors Tpc, which are P-channel type MIS transistors, are switched ON when the clock signal  is at a low level, and the output signal conductors X₀ - X₇ and the dummy signal conductor DL are precharged at a high level. Figures 6 and 7 are circuit diagrams showing modifications of the embodiment of the decoder circuit shown in Fig. 5. In these decoder circuits, the dummy signal conductor DL can be omitted. As shown in Fig. 6, in one modification of the decoder circuit, output signal conductors X₀ - X₇ are divided into pairs of two adjacent output signal conductors, a gate electrode of one transfer transistor of each pair is connected to one output signal conductor and a gate electrode of the other transfer transistor is connected to the other output signal conductor, and a source electrode of one transfer transistor is connected to the other output signal conductor and a source electrode of the other transfer transistor is connected to one output signal conductor, respectively. For example, in a pair of two adjacent output signal conductors X₀ and X₁ , a gate electrode of a transfer transistor T₀ is connected to the output signal conductors X₀ and a source electrode of the transfer transistor T₀ is connected to the output signal conductors X₁, and a gate electrode of a transfer transistor T₁ is connected to the output signal conductors X₁ and a source electrode of the transfer transistor T₁ is connected to the output signal conductors X₀. Similarly, for example, in a pair of two adjacent output signal conductors X₂ and X₃ , a gate electrode of a transfer transistor T₂ is connected to the output signal conductors X₂ and a source electrode of the transfer transistor T₂ is connected to the output signal conductors X₃ , and a gate electrode of a transfer transistor T₃ is connected to the output signal conductors X₃ and a source electrode of the transfer transistor T₃ is connected to the output signal conductors X₂. In another modification of the decoder circuit shown in Fig. 7, each of the output signal conductors X₀ - X₇ is connected to a gate electrode of each corresponding transfer transistor T₀ - T₇ , a source electrode of each transfer transistor T₀ - T₆ , except a last transfer transistor T₇ , is connected to an adjacent output signal conductor X₁ - X₇ , except a first signal conductor X₀. A source electrode of the last transfer transistor T₇ is connected to the first output signal conductor X₀. As described above, in these modifications of the decoder circuit, the dummy signal conductor DL can be omitted. Furthermore, a source electrode of each of the transfer transistors T₀ - T₇ is not only connected to an djacent output signal conductor X₁ - X₇ and DL, which are connected to the gate electrode of the each of the transfer transistors T₀ - T₇ , but also the source electrode of each of the transfer transistors T₀ - T₇ can be connected to any one of the other signal conductors X₀ - X₇ and DL without connecting to a gate electrode thereof. Namely, for example, in a transfer transistor T₀ , a gate electrode of the transfer transistor T₀ is connected to a corresponding output signal conductor X₀ , and a source electrode thereof can be connected to another signal conductor X₁, X₂ , X₃ , X₄ , X₅ , X₆ , X₇ or DL. Similarly, in a transfer transistor T₁ , a gate electrode of the transfer transistor T₁ is connected to a corresponding output signal conductor X₁ , and a source electrode thereof can be connected to another signal conductor X₀ , X₂ , X₃ , X₄ , X₅ , X₆ , X₇ or DL. The above described decoder circuits are formed by a C-MIS circuit, and as shown in Figs. 5, 6, and 7, transistors drawn by a thick line are P-channel type MIS (P-MIS) transistors and a transistor shown by a normal line is an N-channel type MIS (N-MIS) transistor. Next, an operation of the embodiment of the decoder circuit as shown in Fig. 5 is explained with reference to Fig. 8. In this embodiment, only one transfer transistor (one of the select transistors T₀ - T₇) having a gate electrode connected to the selected output signal conductor, which is at a high level, is switched ON. The other transfer transistors having gate electrodes connected to the other non selected signal conductors are not switched ON, since both the gate electrodes and source electrodes thereof are at a low level. The above operations are a principle of the present embodiment, and detailed explanation of these operations is given below. First, in a decoder circuit, each node thereof is set to a specific potential in synchronization with a clock signal , when the clock signal  is at a low level. Namely, when the clock signal  is at a low level, a gate electrode of each of the present transistors PRT₀ - PRT₇ , which are P-channel type MIS transistors, is at a low level, and then all of the preset transistors PRT₀ - PRT₇ are switched ON, whereby a gate potential of each of the output transistors TR₀ -PR₇ is precharged to a high level state. Further, at the same time, all of the precharge transistors Tpc and the discharge transistors T DC are switched ON, each input signal conductor Y₀ - Y₂ is discharged to a low level, and each output signal conductor X₀ - X₇ is precharged to a high level. When the clock signal  is made high level and address signals A₀ - A₃ are supplied will be explained. To simplify the explanation, the logical states of the address signals A₀ , A₁ and A₃ are assumed to be the same as in Fig. 3, i.e., the address signals A₀ is at a low level, A₁ is at a low level, and A₃ is at a high level. In this state of the address signals A₀ - A₃ , similar to the example in Fig. 2, an output signal conductor X₄ is selected by NAND circuits NY₀ - NY₂ , inverter circuits INV₀ - INV₂ , drive transistors D IN , and a cell transistor Cs. In this case, a potential of the output signal conductor X₄ is maintained at a high level, since all of the cell transistors connected to the output signal conductor X₄ are kept OFF. The potential levels of the other non selected output signal conductors X₀ - X₃ and X₅ - X₇ are made low level. Note, a potential level of the dummy signal conductor is also made low level. As a result, a gate potential of the transfer transistor T₄ is kept at a high level, a source potential thereof is made low level, and the only one transfer transistor T₄ is switched ON, since a voltage between the gate electrode and the source electrode is higher than a threshold voltage thereof. On the other hand, a transfer transistor T₃ is kept OFF, since a source potential thereof is at a high level, a gate potential thereof is made low level, and a reverse bias is applied between the gate electrode and the source electrode thereof. The other transfer transistors T₀ , T₁, T₂ , T₅ , T₆ and T₇ are kept OFF, since both a gate potential and a source potential thereof are made low level. Note, in the other transfer transistors T₀ , T₁ , T₂ , T₅ , T₆ and T₇ , the gate potential thereof is made the same as the source potential thereof. Namely, when the transfer transistor T₄ is switched ON and the other transfer transistors T₀ - T₃ and T₅ - T₇ are switched OFF, the relationship between a gate potential and a source potential of each of the other transfer transistors T₀ - T₃ and T₅ - T₇ is such that the gate potential is gradually made low level, and at the same time, the source potential is made low level. Even if an environmental condition of the decoder circuit such as an ambient temperature is changed, the gate potential and the source potential of each transfer transistor T₀ , T₁ , T₂ , T₅ , T₆ and T₇ are made equivalent to each other, and thus each transfer transistors T₀ , T₁ , T₂ , T₅ , T₆ and T₇ is made OFF, respectively. Consequently, the gate potential is not higher than the source potential, and thus an OFF state is maintained and a selection error can not be made. When the transfer transistor T₄ is switched ON, a gate electric charge of the output transistor TR₄ is discharged by a source electrode of the transfer transistor T₄ connected to an adjacent output signal conductor X₅ , whereby a gate potential of the output transistor TR₄ is made low level. Therefore, the output transistor TR₄ is switched ON, and the word line WL₄ is made high level. Note, in the present invention, the transistors of the decoder circuit can have a reverse polarity to those of the above embodiment. In this case, a P-channel MIS transistor is replaced by an N-channel MIS transistor, an N-channel MIS transistor is replaced by a P-channel MIS transistor, a logical value is reversed, an operation of each preset transistor PRT₀ - PRT is used for discharging, and an operation of each transfer transistor T₀ - T₇ is used for charging. As described above, in accordance with the present invention, only one output signal conductor is selected during a period of decode operation in which a timing signal is not used a control circuit for outputting the timing signal is not required. Therefore, unnecessary delay is avoided and operation errors do not occur. Furthermore, since NAND circuits are not needed for the buffer portion of the present invention, the circuit is simpler and thus suitable for a large scale integration circuit. Many widely different embodiments of the present invention may be constructed without departing from the scope of the present invention, and it should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.

Claims: A decoder circuit including a plurality of signal conductors (X₀ - X₇ , DL), a first potential setting means (Tpc) connected to said signal conductors (X₀ - X₇ , DL) and operable to set a potential of said signal conductors (X₀ - X₇ , DL) at a first potential, and a second potential setting means (Cs) connected to said signal conductors (X₀ - X₇ , DL) and operable to maintain a potential of one of said signal conductors (X₀ - X₇) at said first potential and to reduce a potential of remaining said signal conductors (X₀ - X₇ , DL) to a second potential, characterized in that said decoder circuit comprises: a respective transfer transistor (T₀ -T₇) provided for each signal conductor (X₁ - X₇), a gate electrode of each transfer transistor (T₀ - T₇) being connected to the corresponding signal conductor (X₀ - X₇), a source electrode thereof being connected to another signal conductor (X1 - X₇ , DL), whereby in use, one of said transfer transistors (T₀ - T₇) is switched ON and a decoded output signal is output when a gate potential of that transfer transistor (T₀ - T₇) is maintained at said first potential and a source potential thereof is brought to said second potential. A decoder circuit according to claim 1, wherein said plurality of signal conductors (X₀ - X₇ , DL) comprises a plurality of output signal conductors (X₀ - X₇) and a dummy signal conductor (DL). A decoder circuit according to claim 1 or 2, wherein said first potential setting means (Tpc) comprises a plurality of precharge transistors, each precharge transistor (Tpc) being connected to a respective said signal conductor (X₀ - X₇ , DL). A decoder circuit according to claim 3, wherein a source electrode of each precharge transistor (Tpc) is supplied with a first power supply potential (V DD ), a gate electrode thereof is supplied with a clock signal (), and a drain electrode thereof is connected to the respective said signal conductor (X₀ - X₇ , DL). A decoder circuit according to claim 1, 2, 3 or 4, wherein said second potential setting means (Cs) comprises a plurality of cell transistors, each cell transistor (Cs) being connected to a respective said signal conductor (X₀ - X₇ , DL) and operable to select that signal conductor (X₀ - X₇) in accordance with input signals (A₀ - A₃). A decoder circuit according to claim 5, wherein a source electrode of each cell transistor (Cs) is connected to one of said signal conductors (X₀ - X₇ , DL), a gate electrode thereof is connected to one of a plurality of input signal conductors (Y₀ - Y₂ ), and a drain electrode thereof is arranged to be supplied with a second power supply potential (GND), wherein, in use, a potential of one signal conductor (X₀ - X₇) is maintained at said first potential and a potential of the remaining signal conductors (X₀ - X₇ , DL) is brought to said second potential through said cell transistors (Cs). A decoder circuit according to claim 6, wherein one end of each input signal conductor (Y₀ - Y₂ ) is connected to a respective drive transistor (D IN ), and the other end of each input signal conductor (Y₀ - Y₂ ) is connected to a respective discharge transistor (T DC ), said drive transistors (D IN ) being controlled by said input signals (A₀ - A₃) and said clock signal () through corresponding NAND-gate circuits (NY₀ - NY₂′) and inverter circuits (INV0 - INV2), and said discharge transistors (T DC ) being controlled by said clock signal through an inverter circuit (INV₅). A decoder circuit according to any preceding claim, wherein the source electrode of each transfer transistor (T₀ -T₇) is connected to a said signal conductor (X₂ - X₇ , DL) adjacent to a said signal conductor (X₀ - X₇) connected to the gate electrode of that transfer transistor (T₀ - T₇). A decoder circuit according to claim 8, wherein the source electrode of a last transfer transistor (T₇) is connected to said dummy signal conductor (DL). A decoder circuit according to claim 8, wherein the source electrode of a last transfer transistor (T₇) is connected to the first signal conductor (X₀). A decoder circuit according to claim 8, wherein said signal conductors (X₀ - X₇) are divided into pairs of first and second adjacent output signal conductors (X₀ , X₁; X₂ , X₃; X₄ , X₅; X₆ , X₇), connected to gate electrodes of first and second transfer transistors (T₀ , T₁; T₂ , T₃; T₄ , T₅; T₆ , T₇), a source of the first transfer transistor (T₀; T₂; T₄; T₆) is connected to said second output signal conductor (X₁; X₃; X₅; X₇), and a source of the second transfer transistor (T₁; T₃; T₅; T₇) is connected to said first output signal conductor (X₀; X₂; X₄; X₆), respectively. A decoder circuit according to any preceding claim, wherein a drain electrode of each transfer transistor (T₀ - T₇) is connected to a drain electrode of a respective preset transistor (PRT₀ - PRT₇) and to a gate electrode of a respective output transistor (TR₀ - TR₇), a source electrode of each preset transistor (PRT₀ - PRT₇) is supplied with said first power supply potential (V DD ) and a gate electrode of each preset transistor (PRT₀ - PRT₇) is supplied with said clock signal (), and a source electrode of each output transistor (TR₀ - TR₇) is supplied with said first power supply potential (V DD ) and a drain electrode of each output transistor (TR₀ - TR₇) is connected to a respective output terminal (O₀ - O₇). A decoder circuit according to claim 12, wherein each transfer transistor (T₀ - T₇), preset transistor (PRT₀ - PRT₇) and output transistor (TR₀ - TR₇) is disposed in a space between adjacent ones of said signal conductors (X₀ - X₇ , DL). A decoder circuit according to any preceding claim, wherein all of said transistors are MIS type transistors. A decoder circuit according to claim 14, wherein said first potential setting means (Tpc) comprises a plurality of P-channel type MIS precharge transistors, wherein said second potential setting means comprises a plurality of N-channel type MIS cell transistors, and wherein each transfer transistor (T₀ - T₇) is an N-channel type MIS transistor. A read only memory device comprising a decoder circuit according to any preceding claim.

Inventors: IWAZAKI, TOMONOBU
Applicants: FUJITSU LIMITED
Application year: 1989
Main classification: G11C8
IPC codes: H03M7, G11C8