Highly integrated multi-port semiconductor storage

Abstract: For a multi-port SRAM, a write-byte scheme is proposed which allows the selection of a single byte for a fast write or write-through operation. The cell matrix is divided into i blocks of kx8 or kx9 columns each (k = 1, 2, 3, ...), and to every block a column of AND gates (A) is added which link the block word lines (WLW) to the respective write word lines (WL), depending on the state of a unique write byte control signal (WBi). This concept allows the removal of the write byte gate (WB) from the multi-port cell, saving one or two devices per write port (single- or double-ended write). The cell can then be written through a single NFET rather than a series connection of two, thus achieving a better performance/density trade-off. The write performance of the multi-port cell is further enhanced by using an asymmetrical CMOS flip-flop (FF) with weak feedback. The first flip-flop inverter is designed to drive the attached inverter buffer or preamplifier. The second flip-flop inverter contains a minimal-width and long-channel NFET to reduce the countereffect when writing a high-level through the write port NFET. With this write-byte scheme the critical path delay can be minimized.

Description: The invention relates to a highly integrated multi-port semiconductor storage according to the preamble of claim 1. Storages permitting the parallel reading of two stored words or the simultaneous reading of a particular stored word and the writing of another word into another storage location are known in principle. A semiconductor storage permitting two or more word lines to be simultaneously addressed is described in DE-OS 2,327,062. However, this storage has the disadvantage that the words read are not simultaneously available at the storage output but are combined in the storage to form a logical product. The simultaneous writing of a word into other storage locations is not possible. Known from US Patent 3,675,218 is furthermore a storage arrangement, wherein information can be written into any random part, while information is read from another part different from the first one. Although this solution is technically elaborate, it only permits writing one word and simultaneously reading another. In IBM TDB, Vol. 19, No. 7, December 1976, a storage organization is described permitting the parallel reading of two stored words. From IEEE 1977, "International Solid State Circuit Conference", February 16, 1977, pp. 72 and 73, a 32 x 9 ECL dual address register is known permitting two separate parallel read operations of stored words. Beside the apparent access port restrictions the technical means required in the prior art for sensing and selection as well as writing are relatively elaborate and do not permit optimum integration. The previously described storages which are addressable in parallel have the common disadvantage that, unless additional registers or storages are provided, they are not suited for use as high-speed storages in advanced processors. Up-to-date processors comprise, as a rule, high-speed registers, the operation of which is partly concealed and which are partly available to the programmer. With many instructions, two operands are to be read from two different registers and to be fed to the arithmetic unit for processing; the result of this arithmetic operation is stored in one of the registers. In such a known processor, an instruction is executed as follows: 1. Reading two operands from different registers, 2. executing an arithmetical operation, such as an addition, subtraction or multiplication, and 3. feeding the result to one of the registers, i.e., the result is written into one of the registers. In addition, it is frequently necessary to find a time gap in which other new information, for example from the main storage, can be written into one of the registers. With the storages known so far, which permit addressing only for reading two words, such operations can only be performed in series or partly in parallel. As a result, storage times accumulate which essentially influence the speed at which an instruction can be executed. To speed up operation, it would be desirable to have a storage whose ports to the individual registers can be used in parallel, i.e., in the present case to have at least three ports, one read port for each operand and one write port for the result. For addressing these ports to the registers, each of them is provided with an independent address decoder. As described, register banks with two ports are known from the above-mentioned literature (IEEE 1977). In highly integrated semiconductor technology it is relatively difficult and expensive to manage with only one storage cell per bit. In accordance with the two address systems, two cells are generally used for each bit, but these cells must always contain the same information. Care must be taken that information written by an address system into one cell of the pair also reaches the other cell of the pair. In the above-mentioned prior art citation, this is accomplished by coupling the cell pairs in the standby state, i.e., it is only after a cell has been written and is about to assume the standby state, that the coupling impresses the same information into the other cell of the pair. This storage has no third port. US Patent 4,412,312 describes a storage where the storage locations are made up of at least two storage elements which, via coupling elements, are connected to associated but different bit lines as well as to separate word lines, and which have at least three independently selectable ports. The coupling elements respond to different polarities of changes in the reference potential of the storage elements. A memory cell adapted for different combinations of simultaneous read and write operations is described in IBM Tech. Disc. Bul., Vol. 23, No.1, 6/80, pp. 180-186. Another multi-port array cell is described in IBM Tech. Disc. Bul., Vol. 22, No.10, 3/80, pp. 4553-4554, and a multi-port asymmetrical memory cell is described in IBM Tech. Disc. Bul., Vol. 23, No.7A, 12/80, p.2822. A semiconductor memory device provided with an improved precharge scheme for bit lines is known from EP-A-0 237 813. A plurality of bit lines are divided into a plurality of bit line group and a precharge control signal is applied only to precharge transistors in a selected bit line group. EP-A-0 145 497 discloses a master slice type LSI which is constructed as a three port memory circuit in which respective cells exclusively utilized as memory circuits constituting respective memory regions can be accessed simultaneously. Each cell exclusively used as a memory circuit is constituted by a flip-flop circuit including two inverters which are connected in parallel opposition, a single write data input line and two read out data output lines which are connected to the flip-flop circuit through transfer gate circuits respectively and at least three word lines respectively and at least three word lines along which independent word signals are transmitted. The three transfer gate circuits are independently enabled and disabled based on the word signals transmitted over the word lines. The teaching of this document forms the preamble to claim 1. The prior art cells do not meet the density and performance requirements, particularly of a fast byte-writable multi-port static random access memory. It is therefore the object of the invention to provide a multi-port highly integrated static semiconductor storage which improves both the density and the write performance to allow a single byte select for a fast write or write-through operation. The solution is described in the characterizing part of claim 1. Further improvements are described in claims 2 - 7. To improve both the density and the write performance of the byte-writeable multi-port SRAM described above, it is suggested to use a multi-port cell with an asymmetrical flip-flop and a single device per write port, and to implement a write-byte control in the word line common to all attached cells. Instead of integrating the write-byte device(s) into each memory cell, an extra AND circuit is provided which gates all write devices of a group of kx9 cells in a row (k=1, 2, 3, ...). The AND gate is only selected if both input signals, the main write word line signal WL and the unique write byte signal WBi, are activated. This approach is more area efficient and allows to optimize the cell design for a fast write performance without being limited too much by the cell size. Provided that the multi-port cell contains inverter buffers in the read ports, the single-ended write can be accelerated significantly by an asymmetrical flip-flop with a weak feedback as storage element. Such a flip-flop is realized by a cross-coupled inverter pair. The first inverter uses devices slightly larger than minimum, adjusted to the size of the attached inverter buffers. The second inverter contains a minimum-width and long-channel NFET to reduce the countereffect when pulling up the flip-flop node 1 by the write NFET. This concept ensures that the written signal propagates rapidly to the read port. To summarize, the proposed write-byte scheme for a CMOS static random access memory (SRAM) of the invention has the following major features and advantages: Fully static multi-port memory cell with asymmetric flip-flop sufficient driveability of first inverter (driving the preamplifier) reduced countereffect (flip-flop with weak feedback) Byte write control outside memory cell - all write port devices of a cell group within a row controlled by a common AND gate, selected by the main WL and the byte write control This leads to the following advantages over the circuitry of the prior art: Better write performance - 44% shorter write time with single write NFET and asymmetrical flip-flop Higher array density by saving FETs. In conclusion, the proposed write-byte scheme provides an optimal trade-off between density and performance. By using an asymmetrical flip-flop in conjunction with a single write port device and the byte-controlled section word line, the critical path delay through the fully static multi-port memory cell can be minimized for a fast write-through operation. The invention will be described in detail below with reference to drawings which illustrate embodiments, in which Fig. 1 shows a typical circuit schematic of the multi-port cell within a storage matrix; Fig. 1a shows a more detailed circuit of Fig. 1; Fig. 2 shows a block diagram of the write circuitry for a row of a multi-port SRAM; Fig. 3 shows a timing chart of the SRAM of Figs. 1 and 2; Fig. 4 shows a particularly favorable circuit diagram of the multi-port SRAM cell. Referring to the circuitry of Fig. 1, the block diagram of Fig. 2 and the timing diagram in Fig. 3, the fast write operation or the write-through operation of the byte-writeable multi-port cell scheme is as follows: It is assumed that a logical '0' is stored in the memory cell and that the bit lines are at a low level due to preceding write and/or read '0' operations. At the beginning of the write operation the write address is set up. The write word decoder WD selects one of the main word lines, e. g., main word line WL goes to a high level after the last change of address Aw. To selectively store data only into a particular block i of the cell array, the byte write clock WBi is activated. This signal is fed into a column of AND gates located at the edge of the block of cells. As soon as clock signal WBi goes high, one of these AND gates connected to the selected main word line WL is enabled to perform the final decoding, after which the associated block word line WLw rises, gating all write devices of the attached byte-organized group of cells. Assuming that a logical '1' is to be stored in a selected cell, the respective data input and hence the write bit line BLw must be set to a high level (Fig. 1a). With the write-port NFET T1 being turned on, the cell node 1 is first charged towards a voltage of only VDD-VTn, i.e. a threshold voltage VTn below the power supply voltage VDD (Fig. 1a). This is sufficient to switch the high-gain flip-flop inverter T2/T3. As soon as the output of this inverter, i.e. cell node 2, has dropped below VDD-VTP (VTP = threshold voltage of PFET), the small load PFET T4 of the low-gain inverter T4/T5 turns on and starts charging node 1 to the full power supply voltage VDD. Thus, the final pull-up is achieved by the feedback effect. The high level obtained at node 1 propagates quickly through the flip-flop inverter T2/T3 and the attached inverting buffers T6/T7. This completes the write operation. Provided the cell is also selected for a read operation, one or more read ports can be opened, depending on the status of the read address bits. This operation mode where the read address is the same as the write address is called WRITE-THROUGH operation. If a read-port is selected by the respective read word line, the new cell data is transmitted to the read bit line. To give an example: When the read word line WLR1 rises, the read port NFET T8 turns on and the read bit line BLR1 adopts the high voltage level from the inverting buffer T6/T7. Thus the data received from the input can quickly be written through the memory cell to the data output. If a stored '1' were to be overwritten by a '0', the cell node 1 would be quickly discharged from VDD to ground via the write port NFET T1. In Fig. 4 the write-port T1 is realized with a p-device. This step is advisable if the "write word line" is to drive a high load. In this case a high speed selection via the word driver is possible as the word line can be quickly discharged from VDD to 0. In that case, the flip-flop is set asymmetrically in a precisely inverted mode, i.e. T4 is of small dimensions, so that the writing of a '0' that is affected owing to the P device in the write port is accelerated.

Claims: Highly integrated multi-port static random access memory (SRAM) comprising asymmetrical CMOS flip-flops (FF) as storage cells, further comprising a plurality of intersection bit and word lines forming crosspoints therebetween, a plurality of storage locations provided at the crosspoints and connected to the respective bit and word lines for selecting a single bit group, particularly a single byte for a fast write or write-through operation, whereby a cross-coupled inverter pair (T2, T3; T4, T5) forms the asymmetrical CMOS flip-flop (FF), where the first flip-flop inventer (T2, T3) is designed to drive an output, and the second flip-flop inverter (T4, T5) contains a minimum-width and long-channel N field effect transistor (NFET) to reduce the countereffect when writing a high-level through the write port; characterized by inverter buffers or preamplifiers (T6, T7) being attached to the output of the assymetrical CMOS flip-flop and driving the bit lines; by dividing the cell matrix in i blocks of k bit columns each, k = 1, 2, ...; and by a column of AND gates (A) connected to every block, the AND gates linking the block word lines (WLw) to the respective main write word lines (WL) depending on the state of a unique write byte control signal (WBi). Multi-port static random access memory (SRAM) as set forth in claim 1, characterized by activating a byte-write clock signal (WBi) which is fed into a column of the AND gates (A) located at the edge of the block of cells, where one of these AND gates connected to the selected main word line (WL) is enabled to perform the final decoding as soon as the write clock signal (WBi) goes to the signal high level; by gating all write devices of the attached group of cells; by raising the potential on the associated block word line (WLw). Multi-port static random access memory (SRAM), as set forth in claim 1 or 2, characterized by using a multi-port cell with the asymmetrical flip-flop (FF) and a single device per write port, and by implementing a write-bit group control in the write word line (WL) common to all attached multi-port cells. Multi-port static random access memory (SRAM) as set forth in any one of claims 1 to 3, characterized in that each multi-port cell contains the inverter buffers in the read ports, and in that the single-ended write is accelerated significantly by an asymmetrical flip-flop (FF) with a weak feedback. Multi-port static random access memory (SRAM) with asymmetrical flip-flops as cells of claims 1 or 4 characterized in that the first inverter (T2, T3) contains devices slightly larger than minimum and adjusted to the device of the attached inverter buffer (T6, T7), and that the second (feedback) inverter contains a minimum-width and long-channel N-channel field effect transistor (T4) to prevent the countereffect when pulling up the flip-flop node (1) by the write N-channel field effect transistor (T1). Multi-port static random access memory (SRAM), as set forth in any one of claims 1 - 5, characterized in that the bit groups consist of half bytes, bytes or multi-bytes. Multi-port static random access memory (SRAM) as set forth in any one of the claims 1 to 6, characterized in that the field effect transistors (FETs) of the write ports are P-channel devices.

Inventors: CLEMEN RAINER DIPL-ING, LOEHLEIN WOLFDIETER, CLEMEN, RAINER, DIPL.-ING., LOEHLEIN, WOLFDIETER
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: G11C8
IPC codes: G11C11, G11C8