Sequence controller for controlling next operating state with a short delay

Abstract: A sequence controller for designating an operating state to be performed currently is disclosed. This controller includes a set of terminals from which first data for designating a current operating state is derived, a state designation circuit producing a second data for designating a next operating state in response to said first data, a latch circuit coupled between the state designation circuit and the set of terminals for latching and outputting the second data as the first data in response to a strobe signal, and a signal generator supplied with a clock signal and producing the strobe signal in synchronism with the clock signal when a response signal to the current operating state is returned to the controller.

Description: BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to a sequence controller for controlling a sequence of operating states of a data processor and, more particularly, to a controller for designating a next operating state by a response signal to a current operating state. Description of the Related Arts: Such a sequence controller is employed in, for example, an instruction decoder unit of a microprocessor. More specifically, the microprocessor includes a bus control unit for controlling a bus coupled to a memory to write or read data into or from the memory, an instruction prefetch unit coupled to the bus control unit for prefetching instructions from the memory by use of the bus control unit, an effective address generator coupled to the bus control unit for supplying an effective address used for a memory access operation, an execution unit executing each instruction, and an instruction decoder unit coupled to the prefetch unit, the effective address generator and the execution unit. The decoder unit requests the prefetch unit to output the instruction therefrom. If the prefetch unit has the prefetched instruction, it returns a prefetch ready signal to the decoder unit and concurrently supplies the instruction to the decoder unit. The decoder unit responds to the prefetch ready signal and receives the instruction from the prefetch unit to decode them. In general, the instruction has an operation code field for designating an operation to be executed by the execution unit and at least one operand addressing field for designating the addressing of an operand data to be processed. The decoded output of the operation code field is therefore supplied to the execution unit. On the other hand, in case where the operand addressing field is decoded to designate the memory addressing, the decoder unit requests to the effective address generator to calculate the effective address of the operand data. If the effective address generator is free, it returns an address calculation ready signal to the decoder unit and starts to calculate the effective address of the operand data. The calculated effective address is supplied to the bus control unit. In response to the address calculation ready signal, on the other hand, the decoder units changes to an initial operating state to request the prefetch unit to output a next instruction. Thus, the instruction decoder unit operates in a predetermined state sequence. In order to control the operating sequence of the decoder unit, a sequence controller is provided, which includes a state designation circuit for designating the operating state to be performed currently. It should be noted, however, that the current operating state has to be maintained until the response signal to the current operating state, i.e. the prefetch ready signal or the address calculation ready signal, is returned to the sequence controller. For this purpose, according to prior art, the output of the state designation circuit is latched by a latch circuit in synchronism with a first clock signal, the output of the latch circuit being used for designating the current operating state, and the response signal to the current operating state is sampled in synchronism with a second clock signal having a phase opposite to that of the first clock signal. The sampled result is supplied to the state designation circuit together with the output of the latch circuit. When the response signal is not returned, the state designation circuit designates the same operating state, so that the output of the latch circuit is not changed. However, the sampling of the response signal is carried out in synchronism with the second clock signal, i.e., in synchronism with the end of a half clock of the first clock signal. It is very difficult to synchronize the operations of the prefetch unit and the effective address unit, because they operate at a very high speed to return the ready signal to the decoder unit within the period corresponding to the half clock of the first clock signal. In fact, they return the ready signal to the decoder unit after the half clock of the first clock signal. For this reason, the same operating state is designated during at least two clock periods of the first clock signal even when the prefetch unit and the effective address generator return the ready signal to the decoder unit in response immediately to the request from the decoder unit. As a result, the data processing speed of the microprocessor cannot be made quick. The prior art document WO 82/02 784 shows a system having latches and different states. It uses the gating of timing pulses of different phases during a standard two phase clock cycle to achieve processing during otherwise unused time. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an improved sequence controller. Another object of the present invention is to provide a sequence controller which can shift an operating state to be designated in a short clock period of a predetermined clock signal. Still another object of the present invention is to provide a microprocessor including an instruction decoder unit equipped with a sequence controller which can enhance a processing speed of the microprocessor. A sequence controller according to the present invention as claimed comprises a set of output terminals from which first data designating a current operating state is derived, a state designation circuit coupled to the set of output terminals to receive the first data and generating second data designating a next operating state, a latch circuit coupled between the state designation circuit and the set of output terminals for latching the second data from the state designation circuit in response to a strobe signal and for supplying the latched data to the set of the output terminals as the first data, and a strobe signal generator receiving a clock signal to generate the strobe signal in synchronism with the clock signal when a response signal to the current operating state is supplied thereto. The state designation circuit designates the next operation state irrespective of the response signal to the current operating state, and the latch circuit latches the output from the state designation circuit in response to the strobe signal which is generated in synchronism with the clock signal when the response signal to the current operating state is returned thereto. The designation to the next operating state is thereby determined by whether or not the response signal is returned within a period corresponding to one clock, not a half clock, of the clock signal. Accordingly, even when the response signal is returned after a half clock of the clock signal, the operating state to be designated can be shifted in one clock. If the response signal is not returned, the strobe signal is not generated, so that the data latched in the latch circuit is not changed. The same operating state thereby continues to be designated unit the response signal is returned. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram representative of a microprocessor; Fig. 2 is a block diagram representative of an instruction decoder unit shown in Fig. 1; Fig. 3 is a circuit diagram representative of a normal sequential control circuit according to an embodiment of the present invention; Fig. 4 is a state shifting diagram of the sequential control circuit shown in Fig. 3; Fig. 5 is a timing chart representative of an operation of the sequential control circuit shown in Fig. 3; Fig. 6 is a circuit diagram representative of a main sequential control circuit according to another embodiment of the present invention; Fig. 7 is a state shifting diagram of the sequential control circuit shown in Fig. 6; Fig. 8 is a timing chart representative of an operation of the sequential control circuits shown in Figs. 3 and 6; and Fig. 9A is a format representative of a first type instruction and Fig. 9B is a format representative of a second type instruction. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to facilitate the understanding of the present invention, description will be made on a case where a sequence controller according to the present invention is applied to an instruction decoder unit of a microprocessor. Referring to Fig. 1, a microprocessor 1000 includes a bus control unit (BCU) 1001, an instruction prefetch unit (PFU) 1002, an instruction decoder unit (IDU) 1003, an effect address generator (EAG) 1004, and an execution unit (EXU) 1005. The BCU 1001 controls a system bus 1006 to write or read data into or from a memory 1007 coupled to the bus 1006. Further coupled to the bus 1006 are a plurality of peripheral control units (not show). The PFU 1002 prefetches instructions from the memory 1007 by use of the BCU 1001 when the bus 1006 is free from a data access operation. Turning to Fig. 9, there are shown two type instructions, the first type of which is a one-operand instruction (Fig. 9A) and the second type of which is a two-operand instruction (Fig. 9B) Each of the first and second type instructions includes an operation code field 901 of one byte for designating an operation to be performed and a first operand addressing field 902 of one byte. Only the second type instruction further includes a second operand addressing field 903 of one byte. Each of the addressing fields 902 and 903 has base mode information representing that an operand to be processed is stored in the memory 1007 or register mode information representing that an operand to be processed is stored in a register provided in the EXU 1005. Turning back to Fig. 1, the PFU 1002 supplies the instruction to the IDU 1003 in response to a request therefrom. In case where the operand addressing field 902 (903) has the base mode information, the IDU 1003 supplies the EAG with information necessary to calculate an effective address of the operand data. On the other hand, the operand addressing field 902 (903) has the register mode information, the IDU 1003 supplied that information to the EXU 1005. The IDU 1003 further supplies the EXU 1005 with information responsive to the operation code field 901 to designate an operation to be performed by the EXU 1005. The EAG 1004 calculates the effective address of the operand data in response to the information from the IDU 1003 and supplies the calculated effective address to the BCU 1001 to request a memory access. The BCU 1001 make access to the memory 1007 by use of the effective address and supplies the operand data to the EXU 1005. When the EXU 1005 is prepared with all the operand data necessary to perform the designated operation, it starts to execute the instruction. Thus, the IDU 1003 is required to operate in a predetermined sequence responsive to the type of the instructions. For this purpose, the IDU 1003 includes a sequence controller 1103, as shown in Fig. 2. The IDU 1003 further includes an operation code decoder 1101 and an addressing field decoder 1102. When the sequence controller 1103 is activated by, for example, the EXU 1005, it generates and supplies an instruction read request (IRQ) signal to the PFU 1002 to request two-byte code. If the PFU 1002 has already prefetched the instruction, it returns an instruction ready (IQRDY) signal to the sequence controller 1103 and concurrently transfers the prefetched instruction to the IDU 1003 via an instruction bus 1104. Otherwise, the IDU 1003 continues to supply the IRQ signal until the IQRDY signal is returned thereto. The decoder 1101 receives the operation code field 901 of the instruction and the decoder 1102 receives the operand addressing field 902 thereof. In response to the operation code field, the decoder 1101 supplies an instruction type designation (SOPD) signal to the controller 1103 to inform it of the type of the instruction. In this description, the SOPD signal of logic "1" indicates the one-operand instruction shown in Fig. 9A, whereas the SOPD signal of logic "0" indicates the two-operand instruction shown in Fig. 9B. The decoded output of the operation code is supplied to the EXU 1105 via an internal bus 1106. In response to the operand addressing field, the decoder 1102 supplies an address node type designation (AFTYP) signal to the controller to inform it of the type of the address mode. In this description, the AFTYP signal of logic "1" indicates the base addressing mode, whereas the AFTYP signal of logic "0" indicates the register addressing mode. In response to the AFTYP signal of logic "1", the sequence controller generates and supplies an address calculation request signal (STEA) to the EAG 1004 and controls the decoder 1102 to supply the EAG 1004 via an internal bus 1105 with the information ACD necessary to calculate an effective address of the operand data. When the EAG 1004 is not busy, it returns an address calculation ready (EARDY) signal to the sequence controller 1103. Otherwise, the IDU 1003 continues to supply the STEA signal and information ACD until the EARDY signal is returned thereto. In response to the EARDY signal, the sequence controller 1103 changes the operating state of IDU 1003 to an initial state to generate the IRQ signal. On the other, hand in case of logic "0" of AFTYP signal, i.e., in case of the register addressing mode, the sequence controller 1103 controls the decoder 1102 to supply the decoded output to the EXU 1005 via a bus 1107, and then changes the operating state to the initial state. When the SOPD signal is logic "0", the IDU 1003 generates the IRQ signal to request one-byte code from the PFU 1002. The second operand addressing field 903 of the second type instruction (Fig. 9B) is thereby outputted from the PFU 1002 and then supplied to the decoder 1102. On the other hand, in case where the SOPD signal is logic "1", the IDU 1003 requests two-byte code from the PFU 1002, so that a next first type instruction (Fig. 9A) is read out of the PFU 1002. Thus, the sequence controller 1103 includes a main sequential control circuit for controlling the operating state of the IDU 1003 in response to the number of the operand addressing fields in one instruction and a normal sequential control circuit for controlling the operating state of the IDU 1003 in response to the addressing mode designated by the operand addressing field. Turning to Fig. 3, the above normal sequential control circuit is denoted by reference numeral 100 and shown as an embodiment of the prevent invention. This control circuit 100 generates three operating state signals QN1, QN2 and QN3. The operating state of the IDU 1003 is shifted in accordance with the signals QN1, QN2 and QN3, as shown in Fig. 4. The state signal QN1 designates an operating state QNS1 in which the IDU 1003 generates the IRQ signal to request two-byte or one-byte code from the PFU 1002 and waits for the IQRDY signal. When the PFU 1002 generates the IQRDY signal, i.e. when the IQRDY signal takes logic "1", the state signal QN2 is generated to designate an operating state QNS2, during which the decoding operation of the decoders 1101 and 1102 is completed. The state signal QN3 is thereafter generated to designate an operating state QNS3. In this state, when the operand addressing field 902 (903) designates the base mode (AFTYP = "1"), the IDU 1003 generates the STEA signal and waits for the EARDY signal. When the EARDY signal is generated from the EAG 1004 to take logic "1", the signal QN1 is generated, so that the operating state is turned to the state QNS1. On the other hand, when the operand addressing field 902 (903) designates the register mode, the operating state is changed from QNS3 to QNS1 without waiting for the EARDY signal. The operating state signals QN1 to QN3 are supplied to a state designation circuit 101. This circuit 101 is constructed by a programmable logic array (PLA) well-known in the art and generates next operating state signals QN1′, QN2′ and QN3′ in response to the current operating state signal QN1 to QN3, as shown in the following TABLE-1. The circuit 101 further generates a signal ENS′ which is outputted simultaneously with the state signal QNS′ as shown in TABLE-1 and represents the end of one sequence in the normal sequential control circuit 100. These signals QN1′, QN2′, QN3′ and ENS are stored respectively into D-FFs 103, 104, 105 and 106 in synchronism with the leading edge of a second clock signal PHI2 which has a phase opposite to that of the first clock signal PHI1. The outputs of the D-FFs 103 to 106 are supplied to a latch circuit 102 which receives a strobe signal STPNS as a latch-enable clock. That is, the latch circuit 102 latches the outputs of the D-FFs 103 to 106 in synchronism with the leading edge of the strobe signal STPNS, and the data latched in the circuit 102 are outputted as the current operating state signals QN1 to QN3 and the one-sequence end signal ENS. The strobe signal STPNS is produced by an AND gate 120 having a first input supplied with the first clock signal PHI1 and a second input supplied with the output STEN of an AND gate 119. This gate 119 receives the outputs of two OR gates 115 and 118. The OR gate 115 has a first input supplied with the IQRDY signal from the PFU 1002 and a second input supplied via an inverter 114 with an instruction ready check (IQRDYCQ) signal. This IQRDYCQ signal is generated by a D-FF 121 storing the state signal QN1 in synchronism with the leading edge of the second clock signal PHI2 and is thus used for waiting for the IQRDY signal in the state QNS1. The OR gate 118 has a first input supplied with the EARDY signal from the FAG 1004 and a second input supplied via an inverter 116 with an address calculation ready check (EARDYCQ) signal. This EARDYCQ signal is produced by a D-FF 122 having a data input supplied with the output AND gate 124 and a clock input supplied with the second clock signal PHI2. The AND gate 124 supplied with the state signal QN3 and the output of a D-FF 123 having a data input supplied with the AFTYP signal and a clock input supplied with the first clock signal PHI1. Therefore, when the base mode is designated (AFTYP = "1") the EARDYCQ signal is used for waiting for the EARDY signal in the state QNSY. When the register mode is designated (AFTYP = "0"), the EARDYCQ signal is held at the logic "0" to invalid the EARDY signal. The operation of the normal sequential control circuit 100 will be described below with reference to the timing chart shown in Fig. 5. When the IDU 1003 is activated by the power-on or the request from the EXU 1005, the latch circuit 102 is preset in synchronism with the leading edge of the first clock signal PHI1 to output the state signal QN1 at a timing T1. The state QNST is thereby designated to request two-byte or one-byte code from the PFU 1002. Assuming that the PFU 1002 has already prefetched the instruction, it returns the the IQRDY signal to the IDU 1003. However, as already mentioned hereinbefore, the PFU 1002 cannot return the IQRDY signal during a half clock period of the first clock signal PHI1, but returns it at a timing T2 after the half clock period. On the other hand, the state designation circuit 101 generates the state signal QN2′ in response to the current state signal QN1, and the signal QN2′ is stored in the D-FF 104 in response to the second clock signal PHI2. By the IQRDY signal, the OR gate 115 produces the logic "1", and at this time, the OR gate 118 also produces the logic "1" due to the logic "0" of the EARDYCQ signal. The output STEN of the AND gate 119 thereby takes logic "1". As a result, the strobe signal STPNS is generated in synchronism with the next leading edge of the first clock signal PHI1 (time T3). The state signal QN1 thereby disappears and the state signal QN2 is in turn generated to designate the state QNS2. Thus, the state QNS1 is completed during one clock period of PHI1, when the PFU 1002 returns the IQRDY signal to the IDU 1003 in response immediately to the request therefrom. In the state QNS2, the code from the PFU 1002 is decoded by the decrders 1101 and 1102. In response to the signal QN2, the circuit generates the state signal QN3′ and the one-sequence end signal ENS′ which are in turn stored in the D-FFs 105 and 106 by the second clock PHI2. Assuming that the base addressing mode is designated, the AFTYP is changed to logic "1". At a timing T₄, the state signal QN3′ is latched by the latch circuit 102 to designate the state QNS3 as a current state. Accordingly, the IDU 1003 produce the STEA signal to request the effect address calculation from the EAG 1004. Assuming that the EAG 1004 is not busy, it returns the EARDY signal to the IDU 1003. As also mentioned hereinbefore, however, the EAG 1004 cannot return the EARDY signal within a half clock period of the first clock signal PHI, but returns it at a timing T₅. By the EARDT signal, the OR gate 118 produces the logic "1", and the OR gate 115 already produces the logic "1". On the other hand, the circuit 101 generate the state signal QN1′ in response to the current state signal QN3. Therefore, the latch circuit 102 latches the signal QN1′ at a timing T₆, so that the state signal QN3 disappears and the state signal QN1 is in turn generated. Thus, the state QNS3 is completed during one clock period of PHI1, if the EAG 1004 is not busy. Since the state QNS1 is designated at a timing T₆, the IDU 1003 requests another two-byte or one-byte code from the PFU 1002 and waits for the IQRDY signal. In response to the generation of the IQRDY signal at a timing T₇, the state signal QN2 is generated to designate the state QNS2 at a timing T₈. Assuming that the register addressing mode is designated, the AFTYP signal is changed to logic "0". At a timing T₉, the state QNS3 is designated. Since the AFTYP signal is logic "0", the EARDYCQ signal is held at the logic "0". The EARDY signal is thereby ignored, so that the operating state of the IDU 1003 is changed to the state QNS1 at a timing T₁₀. Thus, the normal sequential control circuit 100 can shift the operating state of the IDU in one clock cycle of the first clock signal PHI1 when the PFU 1002 has already prefetched the instructions and the EAG 1004 is not busy, and moreover can continue to designate the current operating state until the response signal, IQRDY or EARDY, to the current operating state is returned to the IDU 1003. In Fig. 3, when the state designation circuit 101 is constructed by a static type PLA, the D-FFs 103 to 106 may be omitted. On the other hand, in case of employ a dynamic type PLA circuit 101, the circuit 101 is precharged during the high level period of the second clock signal PHI2 and generates the state signal during the high level period of the first clock signal PHI1, and therefore the D-FFs 103 to 106 are required. Turning to Fig. 6, the above-described main sequential control circuit employed in the sequence controller 1103 is denoted by the reference numeral 500 and shown as another embodiment of the present invention. This control circuit 500 generates two main state signals QM1 and QM2 which designates operating states QMS1 and QMS2, respectively, as shown in Fig. 7. The state QMS1 controls the normal sequential control circuit 500 such that the circuit 500 performs the sequential control of two-byte code. As long as the SOPD signal is at logic "1", the state QMS1 is designated. When the SOPD signal is changed to logic "0", the state QMS2 is designated to control the circuit 500 such that it performs the sequential control of one-byte code. Turning back to Fig. 6, the state signals QM1 and QM2 are supplied to a main state designation circuit 501 which also receives the output of D-FF 505 having a data input supplied with the SOPD signal and a clock input supplied with the first clock signal PHI1. The circuit 501 is also constructed by a PLA circuit and generates next state signals QM1′ and QM2′ in response to the current state signals QM1 and QM2 and the SOPD signal, as shown in TABLE-2 below. The state signals QM1′ and QM2′ are stored respectively in D-FFs 503 and 504 in synchronism with the leading edge of the second clock PHI2. The outputs of the D-FFs 503 and 504 are latched in a latch circuit 502 in response to the lead edge of a strobe signal STPMS. The output of the batch circuit 102 is outputted as the current state signal QM. The strobe signal STPMS is produced by an AND gate 510 having a first input supplied with the first clock PHI1 and a second input supplied with the output STENM of an AND gate 509. This gate 509 has a first input supplied with the output of D-FF 514 delaying the one-sequence end signal ENS from the normal sequential circuit 500 and a second input supplied with an output of the OR gate 508. The first input of the OR gate 508 is supplied with the EARDY signal from the EAG 1004 and the second input thereof is supplied with the EARDYCQ signal via an inverter 513. When the IDU 1003 is activated by the power-on or the request from the EXU 1005, the latch circuit 502 is also preset to produce the state signal QM1 in synchronism with the leading edge of the first clock PHI1 at a timing 20, as shown in Fig. 8. Accordingly, two state signals QM1 and QN1 are generated at the timing T₂₀. In response to these signals QM1 and QN1, the IDU 1003 request two-byte code from the PFU 1002. The state QNS1 by the signal QN1 is continued until the IQRDY signal is returned from the PFU 1002, and thereafter the state signal QN2 is generated to designate the state QNS2 at a timing T₂₁. In this state QNS2, the two-byte code is decoded by the decoders 1101 and 1102. Assuming that the instruction to be executed has two operand addressing fields 902 and 903 and the first operand addressing field 902 designates the base mode, the SOPD signal is changed to logic "0" and the AFTYP signal is changed to logic "1". In response to logic "1" of the AFTYP signal, the state QM3 is generated at a timing T₂₂. On the other hand, the main state designation circuit 501 generates the state signal QM2′, but this signal QM2′ is not latched in the latch circuit 502 since the strobe signal STPMS is held at logic "0". In the state QN3, the IDU 1003 generates the STEA signal to request the address calculation from the EAG 1004 and waits for the EARDY signal. When the EARDY signal is returned to the IDU 1003, the OR gates 115 and 508 both produce logic "1". At this time, both of the output of the OR gate 118 and the one-sequence end signal ENS are at logic "1", so that the strobe signals STPNS and STPMS are generated at a timing T₂₃. As a result, the state signal QN1 is generated again and the state signal QM2 is generated in place of the signal QM2. In response these signals QN1 and QM2, the IDU 1003 requests one-byte code, i.e. the second operand addressing field 903, from the PFU 1002. The IDU 1003 waits for the IQRDY signal from the PFU 1002 in the state QNS1, and thereafter the state signal QN2 is generated at a timing T₂₄. Assuming that the second operand addressing field 903 designates the register mode, the AFTYP signal is changed to logic "0", so that the EARDYCQ signal is changed to and held at logic "0". At a timing T₂₅, the state QN3 starts. However, since the EARDYCQ signal is logic "0", the strobe signals STPNS and STPMS are generated at a timing T₂₅. At this time, the main designation circuit 501 produces the state signal QM1′ in response to the current state signal QM2. Therefore, the state signals QM1 and QN1 are produced at the timing T₂₅. In Fig. 6, in case of employing a static type PLA circuit 501, the D-FFs 503 and 504 may be omitted. The present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope of the claims. The present invention is also able to be applied to a sequence controller used in a data processor other than a microprocessor.

Claims: A sequence controller comprising: a) a first terminal (QN1) for outputting a first state signal designating a first operating state of said sequence controller; b) a state control circuit (101) responsive to said first state signal for generating a second state signal designating a second operating signal of said sequence controller during a period corresponding to said first operating state; and c) a first latch circuit (102) for latching and outputting said second state signal in response to a latch control signal (STPNS), characterized in that, d) said sequence controller (1103) outputs a control signal to a data processing unit (1002) associated therewith in response to said first state signal during said period and waits for a response signal representing a completion of data processing in said data processor and further comprising: e) a clock control circuit (119, 114, 115, 120) responsive to said first state signal for inhibiting a first clock signal (PHI1) from being supplied to said first latch circuit as said latch control signal and thereafter permitting said first clock signal to be supplied to said first latch circuit as said latch control signal in response to said response signal from said data processing unit irrespective of said first state signal. A controller according to claim 1, further comprising a second latch circuit (104) inserted between said state control circuit and said first latch circuit for latching and providing said second state signal to said first latch circuit in response to a second clock signal having a phase opposite to said first clock signal, wherein said clock control circuit is also responsive to said second clock signal and inhibits said first clock signal from being supplied to said first latch circuit as said latch control signal in response to said second clock signal, said first latch circuit thereby being inhibited from latching said second state signal after said second latch circuit latching said second state signal.

Inventors: SUZUKI NARIKO, SUZUKI, NARIKO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: G06F9
IPC codes: G06F9