Analog macro embedded in a digital gate array

Abstract: A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

Description: Field of the Invention The present invention relates to logic gate array chips, also termed master slices, and more particularly concerns such chips adapted to provide analog functions and digital functions from respective areas of the same chip. Background of the Invention As chips become larger in size and greater in circuit density and approach the complexity of computer systems, the need arises to incorporate both analog and digital functions on the same chip. In a straightforward approach, each of the required analog circuits and digital circuits can be designed separately, without regard to the other. However, such an approach does not permit any exploitation of pre-existing chip designs of exclusively one functional kind to incorporate the other functional kind, e.g. to add analog functions to a pre-existing digital function gate array. IBM Technical Disclosure Bulletin, Vol. 29, N° 7, December 1986, pages 3009-3011, New York, US; "Phase-locked loop clock recovery circuit" discloses the implementation of a voltage controlled oscillator (VCO) by means of a ring of gates. US-A-4 227 158 discloses a piezo-electric crystal vibrating in several nodes which controls several frequencies generated by voltage controlled oscillators simultaneously. The output of each voltage controlled oscillator is fed to a summing amplifier which drives the crystal. The output of the crystal is fed to individual phase detectors; each phase detector is also supplied with the output of a voltage proportional to the phase difference between the voltage controlled oscillator and the crystal output for correcting the out put frequency of each oscillator. Summary of the Invention The object of the present invention is to provide in an efficient way different frequency oscillators and logic functions on the same gate array chip using the same basic gate design. These and other objects are achieved, in accordance with a preferred embodiment of the present invention, by the features claimed in claim 1. The invention comprises: a plurality of logic cells, with each logic cell having a power supply line; a main power bus for providing electrical power to the power supply lines of said cells; a first recirculating loop formed by connection of a first set of said cells, said first recirculating loop oscillating at a first frequency; a second recirculating loop formed by connection of a second set of said cells, said second recirculating loop oscillating at a second frequency; means for disconnecting said main power bus from a first plurality of the cells in said first set of cells and from a second plurality of said cells in said second set of cells; means for providing a reference frequency signal; a first phase/frequency-locked loop including first means for generating a third signal that is indicative of said first frequency signal; first means for comparing said third frequency signal to said reference frequency signal and for generating a first control signal indicative of the frequency difference therebetween; and first means for providing said first control signal to the power supply lines of said first plurality of cells of said first set of cells to provide a controlled amount of power thereto in order to control the frequency of oscillation of said first recirculating loop; and a second phase/frequency-locked loop including second means for generating a fourth signal that is indicative of said second frequency signal; second means for comparing said fourth frequency signal to said reference frequency signal and generating a second control signal indicative of the frequency difference therebetween; and second means for providing said second control signal to the power supply lines of said second plurality of cells of said second set of cells to provide a controlled amount of power thereto in order to control the frequency of oscillation of said second recirculating loop; wherein said cells associated with said logic functions are high powered relative to said cells associated with said frequency generation functions. The amount of delay introduced by each oscillator loop cell is a function of its applied power supply voltage. Accordingly, the chip power line buss is connected to all of the cells of the array except for the oscillator loop cells which instead are powered by the control voltage output of a respective phase comparator. The comparator provides a control voltage determined by the difference in frequencies of its two input signals. One input signal is a desired reference signal. The other of the input signals is obtained from the loop-connected oscillator cells, either directly, or after a frequency division or multiplication operation has been performed. If more than one oscillator frequency is desired then a separate generation circuit may be used for each frequency, with a different frequency division or multiplication operation performed on each oscillator loop output prior to application of the signal to its respective comparator. The same reference signal, however, is used for all phase comparators. Brief Description of the Drawings For a more complete understanding of the present invention, reference should be made to the following detailed description and drawings of which Fig. 1 is a simplified chip layout diagram illustrating the relative positioning of the reference signal oscillator, loop-connected oscillators and logic gate array of a preferred embodiment of the present invention; Fig. 2 is a block diagram of each phase-locked loop oscillator of Fig. 1. Fig. 3 is a block diagram of the loop-connected oscillator cells of Fig. 2; and Fig. 4 is a representative metallization pattern for the loop-connected oscillator portion of Fig. 1. Description of the Preferred Embodiment Referring to Fig. 1, the preferred embodiment exemplifies the introduction of two clock oscillators e.g., operating at the respective frequencies of 40 Mhz and 32 Mhz, on a single, pre-existing gate array chip 1. The oscillators are located within region 2 conveniently positioned along the accessible perimeter of chip 1. Region 2, along with region 3 of chip 1, is uniformly provided with the same gate array cells in accordance with gate array or masterslice design technology. The array cells in region 2, however, are connected together to form a pair of oscillator signal sources. Additionally, as further described later, some of the cells of region 2 are disconnected from the chip busses that otherwise power the cells of the entire chip. For enhanced stability, the oscillators of region 2 may be crystal controlled. For this purpose, a single off-chip crystal 4 is connected to a single on-chip reference oscillator 5 (shown in Fig. 2) also located within region 2. In past designs, reference clock oscillator frequencies have been generated by respective crystal oscillator units, one crystal unit used per frequency. In accordance with one feature of the present invention, however, the individual units are replaced by the single off-chip crystal 4 of Fig. 2, a single on-chip reference oscillator 5 and a plurality of phase-frequency locked loops 6 and 7 to generate a desired pair of reference clock frequencies. By integrating the reference oscillator and the phase locked loops onto a single chip, a substantial cost savings can be realized over separate crystal oscillator units. A further cost savings is available, in accordance with another feature of the present invention, by implementing the on-chip oscillator units using the cells of a pre-existing gate array or masterslice design originally created to implement logic circuits. Fig. 2 illustrates the manner in which the frequency from off-chip crystal 4 stabilizes a respective oscillator 8 in the phase lock loop 6 and a respective oscillator 9 in the phase lock loop 7. In the phase lock loop 6 configuration illustrated in Fig. 2, the signal from oscillator 8 is applied via a frequency divider 10 to one input of a phase/frequency comparator 11. The second input of the comparator 11 is obtained from crystal controlled reference oscillator 5. In this embodiment an output control voltage containing a direct component representing the frequency difference between the two inputs is provided by comparator 11. The direct component of the control voltage is extracted by a filter 12 and applied as a powering voltage to oscillator 8. In conventional servo-feedback fashion, the divided-down frequency of oscillator 8, available at the output of divider 10, is constrained to be substantially equal to the frequency of reference oscillator 5. Thus, the harmonically related frequency of oscillator 8 (where divider 10 introduces a whole integer quotient) is likewise closely frequency stabilized. Fully analogous operation may be achieved by utilizing a signal frequency multiplier instead of a signal frequency divider, in which case the respective loop-connected oscillator would be driven to operate at a subharmonic of the frequency of reference oscillator 5. The apparatus and operation of loop 7 corresponds to the above-described loop 6, the only difference being that oscillator 9 operates at a frequency determined by the quotient of frequency divider 13 rather than by the quotient of frequency divider 10. The present invention is not restricted to any one specific circuit design or technology. Suitable implementation for both loop 6 and loop 7 is described, for example, in U.S. Patent No. 4,594,563 issued on June 10, 1986 to Marshall Williams. Many specific circuit designs are available to those skilled in the art, depending upon the basic cell design and technology of the gate array chip employed, e.g., bipolar or FET technology. Fig. 3 illustrates a design configuration for oscillators 8, 9 using AND-INVERT (AI) array cells connected in a loop design. It will be noted from Fig. 3 that each oscillator loop comprises an odd-number of AND-INVERT cells such as 14, 15, 16, 17 and 18. In operation, a "one" present at the input (node 19) of, for example, cell 16 remains as a "one" at that mode until the "one" travels fully around the inverter loop, with the odd number of cummulative inversions and delays introduced by the cells, causing a "zero" to arrive at the node 19. The change from "one" to "zero" at output node 19 occurs at one half the repetition rate of the loop oscillator. Node 19 then remains at a "zero" value for five stage delays, (in this example) until the "zero" has propagated through the loop and been inverted at node 19 by the odd number of inverter cells. The oscillator repetition rate can be varied by changing the time delay experienced by the propagating pulse in traversing each of the cells 17, 18, 14, 15 and 16. It has been found that control of the propagational delay can be realized in response to changes in circuit powering potential. It has also been found that a T2L circuit implementation of the basic AND-INVERT cells is especially advantageous for obtaining delay control of the loop oscillator repetition rate, particularly where the loop cells are low-powered, relative to the higher performance powering of the cells used in the logic portion of the gate array chip. Relatively low or high powering of the cells can be readily accomplished simply by controlling the value of the AND-INVERT cell load resistors. This load resistor area may be determined by the area of the impurity implantation or diffusion mask used in forming the load resistors. In order to control the propagational delay of each loop cell, a control voltage is applied via power line 20 to cells 14, 15, 16, 17 and 18 in Fig. 3. The control voltage is derived from the output of the respective loop filter, such as filter 12 of loop 6 of Figure 2 and will typically vary from 1.4 to 2.2 volts. However, all of the cells of chip 1 are ordinarily powered by the same power buses. Accordingly, it becomes necessary, when adding the loop-connected oscillators to a pre-existing gate array, to isolate the loop cells from said power busses. Figure 4 shows oscillator loops 8 and 9 disconnected at respective points A & B from the normal chip power distribution busses 21 and 22. The isolated cell power lines 23 and 24 are connected instead to the output lines from the respective loop filters such as filter 12 of loop 6 and filter 52 of loop 7 of Figure 2, as previously explained. The required disconnections and the required connections between the loop filters and the isolated cell power lines can be readily accomplished by customizing a metal patterning mask for region 2 of gate array chip 1 of Fig. 1. The correspondence of the AI cells 14 - 18 in Fig. 3 are shown in Fig. 4 for the lower AI loop in the Figure. While the present invention has been particularly shown and described with reference to preferred embodiments therefor, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the scope of the present invention, as defined in the appended claims.

Claims: A single semiconductor chip for performing both logic and frequency generation functions, comprising: a plurality of logic cells, with each logic cell having a power supply line; a main power bus for providing electrical power to the power supply lines of said cells; a first recirculating loop (8) formed by connection of a first set of said cells, said first recirculating loop oscillating at a first frequency; a second recirculating loop (9) formed by connection of a second set of said cells, said second recirculating loop oscillating at a second frequency; means (5) for disconnecting said main power bus from a first plurality of the cells in said first set of cells and from a second plurality (14-18) of said cells in said second set of cells; means for providing a reference frequency signal; a first phase/frequency-locked loop (6) including first means (10) for generating a third signal that is indicative of said first frequency signal; first means (11) for comparing said third frequency signal to said reference frequency signal and for generating a first control signal indicative of the frequency difference therebetween; and first means for providing said first control signal to the power supply lines of said first plurality of cells of said first set of cells to provide a controlled amount of power thereto in order to control the frequency of oscillation of said first recirculating loop (8); and a second phase/frequency-locked loop (7) including second means for generating a fourth signal that is indicative of said second frequency signal; second means for comparing said fourth frequency signal to said reference frequency signal and generating a second control signal indicative of the frequency difference therebetween; and second means (23) for providing said second control signal to the power supply lines (20) of said second plurality (14-18) of cells of said second set of cells to provide a controlled amount of power thereto in order to control the frequency of oscillation of said second recirculating loop (9); wherein said cells associated with said logic functions are high powered relative to said cells associated with said frequency generation functions. A gate array circuit according to claim 1, wherein said cells are transistor-transistor-logic cells. A gate array circuit according to claim 2 wherein said first means (10) for generating a third signal and said second means (13) for generating a fourth signal are either signal frequency dividers or signal frequency multipliers.

Inventors: CULICAN EDWARD FRANCIS SR, DAVIS JOHN DONALD, EWEN JOHN FARLEY, MCCABE SCOTT ALLAN, MOSLEY JOSEPH MICHAEL, MULLGRAV ALLAN LESLIE JR, NOTO PHILIP KRANKIE, PETERSON CLARENCE IVAN JR, PRITZLAFF PHILIPP EDWARD JR, CULICAN, EDWARD FRANCIS, SR., DAVIS, JOHN DONALD, EWEN, JOHN FARLEY, MCCABE, SCOTT ALLAN, MOSLEY, JOSEPH MICHAEL, MULLGRAV ALLAN LESLIE, JR., NOTO, PHILIP KRANKIE, PETERSON, CLARENCE IVAN, JR., PRITZLAFF, PHILIPP EDWARD, JR.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: H03L7
IPC codes: H01L21, H01L27, H03L7, H03K19