Memory system having predictive module selection

Abstract: Memory system comprising a plurality of memory modules, wherein the selection of one among the memory modules is performed in preselection as to the memory activation for a memory access operation , on the basis of the previously performed selection of the same module for a preceding memory access operation and wherein, in case the performed preselection is not the appropriate one, the appropriate selection is first performed and then the memory access operation is "retried".

Description: The present invention relates to a memory system having predictive module selection. It is known that semiconductor working memories, used in data processing systems, are built up with a plurality of memory modules, to increase their capacity. For such memories the problem of a fast and efficacious module selection arises. The selection operation implies a time waste which, if at all possible, must be avoided. Conceptually a memory address, expressed in binary code, comprises a bit field which references an addressable location or "entry" in each of a plurality of modules and a bit field which references one among the several modules which form the memory. This field must be decoded by a decoding circuit to provide a selection signal of one module, with exclusion of the other. The time loss resulting from this decoding operation is made worst in system where virtual memory addressing is used and the memories are structured for the immediate addressing of "rows" and the subsequent addressing of "columns". In these systems the address generated by a processor requiring a memory operation is of logical type and comprises an "offset" field and a logical page address field. The "offset" field coincides with a corresponding "offset" field of the physical address, but the logical page address field must be converted, for its use, in a physical page address. This conversion is performed by an address management unit or MMU. When this address structure is used it is possible to immediately start a memory operation by providing the memory system with the "offset" field, and subsequently forwarding the physical page address. The physical page address substantially comprises a field corresponding to a column address and a field which identifies a module (which module field must be decoded). In order to avoid time losses involved in decoding and further, in case of logical addresses, due to the delay in the availability of the field to be decoded, it has been resorted, so far, to an approach which provides the simultaneous activation of all the memory modules, the selection being performed at output level by enabling the output of the selected module only. This enabling may be performed at the end of the memory cycle, when the address information required for selection is already available. This approach, however effective has heavy trade off. The activation of all memory modules results in remarkable power consumption and requires power supplies sized for the maximum foreseen memory capacity. Further, in case write operation of the "off line" type are performed, (i.e. the write operation, once started is completed by the memory system without any form of control by the processor), it becomes impossible to exert a timely control on the operation result. The write operation may reference an entry which exceeds the installed memory capacity. In fact it is clear that the presence or absence of a selected memory module may be verified only when the logical address has been converted into a physical address and only when the physical address has been decoded to produce a module selection signal, with circuits and methods an example of which is provided by US patent 4,592,011. The resulting "overmemory" signal becomes available too late for consideration. Thus, or the protection is given up, or the off line write operation are given up or complex expedients have to be provided. It has also been proposed to provide for a "predictive" memory module selection based on a previous module selection. This approach is disclosed in EP-A-0025801. Accordingly to this disclosure, a memory module is selected by decoding a physical address portion and storing the physical address in a register. In the next following memory access, the physical address portion stored in the register is again decoded and used for memory module selection, without waiting for the availability of the new physical address. The module selection already performed is validated by comparison of the physical address portion stored in the register with the new physical address, in case they match, if not a new memory address cycle is started using the new address. This approach is effective only at the extent, the memory is referenced by addresses which follows a locality criterium as, it results from the use of sequential address. However, the locality or sequentiality criterion is followed only by information of the same cathegory (instruction or data) and not by information of differing category. Thus if an instruction is to be fetched from memory and thereafter a data is to be fetched, it is unlikely that they are latched from the same memory module. In this case the advantages provided by EP-A-0025801 are lost and an overhead due to repetition of a memory access results. The invention is based on the fact that the physical memory addressing, for each of differing cathegories or classes, of information (instructions, data) and for each of differing operations (read, write) is mostly sequential and even in case of branches the information follows a prevailing locality criterion in its allocation within the memory space. GB-A-2193017 (SUN) follows such an approach. Here several registers are provided, one for each memory module. This requires classes of information to be bound to memory modules, whereby one class per module is the constraint to achieve better prediction results. Thus this solution reduces flexibility of module usage. The memory system as set out in Claim 1 with predictive module selection of the presents invention overcomes these trade offs. Therefore, if for a certain operation the selection of a predetermined module is required, it is very likely that the following operation of the same type will require the selection of the same memory module. Thus the module selection may be based on the previously occurred module selection signal, related to the same cathegory or class of information, latched in a suitable register, one per cathegory without waiting for the completion of decoding operations. The features and the advantages of the invention will appear more clearly from the following description of a preferred form of embodiment and from the enclosed drawings where: Figure 1 is a block diagram of a first simplified form of embodiment of the memory system according to the prior art Figure 2 is a block diagram of a second simplified form of embodiment of the memory system according to the prior art Figure 3 is a block diagram of an embodiment of the memory system of the invention. Figure 1 shows in block diagram a first embodiment according to the prior art in the context of a data processing system. The system comprises a central processing unit CPU 1, for instance a microprocessor 68020 of the US firm MOTOROLA, a memory address management unit MMU2 and a working memory 3 having parallelism of 4 bytes (double word). Working memory 3 comprises a plurality of banks or modules, up to a maximum, for instance of 16 modules, respectively referenced as MOD1...MOD16, a timing unit 4 and interface registers 5,6. CPU 1 communicates with the working memory, with other system units such as coprocessors and input/output units, through a system bus, comprising an address channel LADD, a control channel COM and a bidirectional data channel DBUS. To perform a memory access operation (or an access to other system units), CPU 1 puts a logical address LA0-31 on the address channel. The logical address is received by MMU 2 and converted in a physical address PADD. Together with the physical address, MMU2 produces a signal MSTART for selection and activation of the memory (if the memory is the destination unit). The physical address PADD comprises a certain number of bits PAD0-25, of which bits of weight 0-1 indicates the position of the requested information (byte) within a double word and bits having weight from 2 to 25 are effectively used for memory addressing. Assumption is made that each of the memory modules has a capacity, expressed in addressable locations, of 1 M locations, each defined by a column address of 10 bits and by a row address of 10 bits. The address bits PAD2-21 identify a location within each module. The four address bits PAD22-25 identify one among the 16 possible modules. Memory 3 receives signal MSTART and the address bits PAD2-25. Signal MSTART activates the timing unit 4, which generates a suitable sequence of control signals EN1,RAS,CAS,EN2. Register 5 is loaded by signal EN1 with address bits PAD 2-21, which are forwarded, as row address (bits PAD2-11) and column address (bits PAD12-12) to all the memory modules. Register 6 is loaded by signal EN2, at the end of a memory cycle, with address bits PAD22-25. The outputs of register 6 are connected to the inputs of a decoder 7 which generates as output, in a mutually exclusive way, one of 16 selection signals SEL1,...SEL16, each of which selects a corresponding memory module. By selection it is meant both the enabling of a module, if such module is composed of integrated circuits having a CE (chip enable) control input, both the selective inputing of signals RAS,CAS, controlled by the selection signals through suitable logic gates. By way of preferred embodiment example, figure 1 shows that module MOD1 is controlled by signal SEL1 input to control input CE1 and module MOD16 is controlled by signal SEL16 input to control input CE16. The data Inputs/Outputs of the several modules, of tristate type, are enabled only if the corresponding module is active and are all connected to the data channel DBUS. Signal R/W, issued by CPU1 on control channel COM and received by memory 3 defines the data transfer direction. Memory 3 comprises further a comparator 12 having a first input set connected to the inputs of register 6 and a second input set connected to the outputs of register 6. Comparator 12 is enabled by signal EN1 which causes the loading of register 5. The operation of the memory system is very symple. The first time the memory is activated the contents of register 6 are random or, if an initialization reset had been provided, are all zeroes. As a consequence a module is randomly selected even before a memory cycle is activated. However, as soon as the memory cycle starts, by enabling comparator 12 it is possible to verify if the module to be selected is the one already selected or a differing one. If the module is the same, the memory operation is successfully and normally concluded. If the module is a differing one, comparator 12 asserts an error/stop signal (BERR-HALT) at level 0. Such signal is forwarded to CPU1. Owing to such signal, CPU1 performs a "retry" operation, that is it controls a repeating of the previous operation. In practice, it maintains on address channel LADD the previous address, so that the address PADD and control signal MSTART are maintained unchanged at the output of MMU2. At the end of the first memory cycle signal EN2 caused the loading of register 6 with the appropriate module selection code. As a consequence the appropriate memory module is selected and the next following memory operation can be successfully concluded. The module preselection enables to recover all the delays intrinsic to the used selection logic and ultimately enables to increase the operating speed of the memory. It is clear that as long as the memory addresses are in a field which selects the same module, all the memory access operations are successfully performed without need to "retry" them. It is only in case the memory access requires the selection of a module differing from the one previously used that a "retry" operation is required. Suitable protection circuits are provided to avoid that a write operation, performed in a module other than the appropriate one, may alter the contents of a memory location. To this purpose signal R/W issued by CPU1, received by memory 3 and defining, when at level 0 a write operation, is transferred to the several modules through an OR gate 13. OR gate 13 receives at a second input the signal in output from comparator 12, through an inverter 14. Thus in case of unsuccessful comparison the write command R/W=0 is converted into a read command R/W=1 and the information erroneously selected is not changed. Since at each memory operation one and only one module is selected, the power consuption of the memory is greatly reduced if compared with the one of memories where, in order to increase the operative speed, all the memory modules are concurrently activated. Further such consumption is substantially independent on the number of modules, which may be increased at will, without impacts on the powering devices. Figure 2 shows an embodiment similar to the one of figure 1, where the advantages are further enhanced. The embodiment of figure 2 differs from the one of figure 1 only for the fact that the memory activation is advanced as to effective availability of the physical addresses. In this case CPU 1 generates a logical address comprising three parts: an "Offset", which coincides with a portion of the physical address and may be used as a row address ROWADD for the several memory modules, a space code SPCODE, which defines if the addressed space is a memory space or a space of some other resource (register space, peripheral unit space and so on) and a page code LPA which, subject to conversion in a physical page address by the MMU2, may be used in part as a column address COLADD, in part as a module selection code MCOD. The space code SPCODE is input to a decoder 15, which outpus resource selection commands and, among them, signal MSTART. Timinig unit 4, on receipt of MSTART generates a sequence of control signals EN1,RAS,EN2,CAS,EN3. Control signal EN1 is used to load the row address (offset) already present as logical address, in a register 5A. Control signal EN2 is used to load column address COLADD, output from MMU2, in a register 5B. Control signal EN3, at the end of the memory cycle, is used to load the module selection code, output from MMU2, in register 6. Control signal EN2 is further used to enable comparator 12. In the system of figure 2 the memory activation is controlled as soon as the logical address is available, the module preselection being determined by the code previously loaded in register 6. This results in a further reduction of the delay occurring between the instant at which CPU1 requires a memory access operation and the completion of the same operation. A part from this consideration the system of figure 2 operates the same way as the one of figure 1. Figure 3 shows an improvement to the system of Figure 1 (and by analogy to the system of Figure 2) according to the invention. It is know that the memory addressing, in view of the way by which information is organized, follows the sequentiality and locality criteria, separately for data and instructions, and further in case of data, separately for data which may be defined as global and data which may be defined as local or stack data. A further distinction can be made for write operations as to read operations. Therefore in order to reduce to a minimum the "retry" operations which may result from the circumstance that in the execution of a process an instruction read operation may be followed by a data read operation (the instruction and the data being stored in differing modules), register 6 of Figure 1 is replicated in a plurality of registers, each devoted to store a module selection code specific to operation type or nature of the requested information. Thus CPU1 provides MMU with a logical address and MMU2 outputs a physical address PADD and a control signal MSTART, which is forwarded to the timing unit 4. Timing unit 4 generates the sequence of control signals EN1,RAS, CAS,EN2. The address bits PAD2-21 are loaded in register 5 by control signals EN1. The address bits PAD22-25 (the module selection code) are loaded, owing to control signal EN2, in one of a plurality of register 6A,6B,6C,6D. Selection of one, among registers 6A,6B,6C,6D, is performed as follows: Among the several control signals generated by CPU 1, a function code FC is generated, which for sake of clearness may be considered as a single bit. When FC=1 the information requested in a read operation is an instruction. When FC=0 the requested information is a data. In case of a write operation, the information to be written is always considered as a data. The logical address bit LA26, say the most significant bit of the logical address (bits LA27-31 constitutes a field which identify the system space and, within such space, memory 3 as one of the destinations), characterizes a data as a global data if at logical level 0, as a local or stack data if at logical level 1. This distinction, however arbitrary, is in practice used for classifying and organizing data in two classes. Signals FC, LA26 and R/W are input to a decoding network 16 which outputs one of four signals SELA,SELB,SELC,SELD, respectively having the following meaning: SEL A: instruction read operation SEL B: global data read operation SEL C: write operation SEL D: stack data read operation. Each of these signals, in logical AND with signal EN2, enables the loading of one among register 6A,6B,6C,6D. These signals, further input to the control inputs of a multiplexer 18 (or a functionally equivalent logical circuit), enable the selective and mutually exclusive connection of one of the register 6A,6B,6C,6D to a common collector 19. Comparator 12, enabled by signal EN1, receives at an input set the selection code present on collector 19 and, at another input set, the selection code in output from MMU2. The selection code present on collector 19 is further input to a selection logic circuit 20, which decodes it in a module selection signal SEL1,...SEL16. The operation of the system of Figure 3 is similar to the one of the system of Figure 1. The only difference consists in that a memory access is performed by activation of a memory module on the basis, not of the immediately preceding memory module selection, but of the preceding module selection used for the same class of operation and information. In figure 3, decoder 7 of figure 1 is substituted with a selection logic 20 to put in evidence a further advantage of the invention. The selection logic 20 may be for instance of the kind described in US PAT 4,571,676. It provides, in addition to a module selection signal, also an "overmemory" signal OVM if the memory address exceeds the effectively installed or usable memory capacity. In case of a memory write operation "off line", CPU 1 put the logical address on the address channel and the data to be written on the data channel. This information is latched at the beginning of a memory cycle in address register 5 and data register 21 respectively. Once the memory cycle is started, the CPU 1 relinquishes the memory and starts the execution of internal operations. However, before this occurs, it is required to be sure that the write operation can be effectively and successfully concluded. Therefore an "overmemory" signal must be generated, in case of "overmemory" in the shortest possible time. From this point in view a CPU 1 has very stringent requirements. For instance, if the CPU 1 consists in a 68020 microprocessor, operating at the clock rate of 25 MHz, a memory write operation develops on the time span of 6 CPU states, S0,...S5 each having a duration of 20 nsec. During state S0 CPU 1 puts the logical address code on address channel and the required control signals on control channel. During state S2 the data code is put on data bus. Address and control signal are stable at the beginning of state S1 and data is stable at the beginning of state S3. If the write operation cannot be performed, because an overmemory occurs, CPU 1 must receive a BERR error signal, not later than 10 ns prior to the end of state S4. On the other hand, the memory start may occurr only after conversion of the logical address into a physical address by MMU2. This conversion requires about 50 nsec. The memory activation, say the generation of MSTART signal occurs roughly in the middle of state S3. Therefore only 20 nsec are available for checking of the address, the detection of the overmemory occurrence and the generation of the error signal. This time margin is critical or insufficing. By the adoption of the memory system with predictive module selection of the invention, on the contrary, even the overmemory signal has a predictive nature and is generated by logic 20 on the basis of a previously used selection code. This code is made available by multiplexer 18 (even considering the propagation delay of decoder 16 and multiplexer 18) at a time which is roughly within state S1. Therefore a broader time margin is available to logic 20 for generation of the overmemory signal. The overmemory signal OVM i transferred to CPU 1 through logical gate 22, enabled by signal MSTART and can be received within the required time limit. In the preceding description reference has been made to a memory system with predictive module selection, where, in case of wrong prediction a "retry" occurs, that is the repetition of the memory operation is performed with the appropriate module selection. It is however clear that rather than performing a "retry" it is possible to perform a time lengthtening of the memory cycle by providing a time unit 4 having modifiable timing , as described for instance in US Pat N. 4,249,253. In this way, once a memory cycle has been started by control signal MSTART, if in the course of the operation the comparator 12, enabled by signal EN1 (EN2 in Figure 2) generates an error indication, this indication, sent to timing unit 4 through the path indicated by dotted line in figures 1,2,3 and referenced as 30, may change the timing sequence of timing unit 4. For instance, signal EN2 (EN3 in figure 2) may be generated in advance of signals RAS,CAS, so as to load the updated physical address in register 6 and have available, through decoder 7 (or 20 in figure 3), the appropriate module selection signal. By reverse signals RAS,CAS may be suitably delayed.

Claims: Memory system with predictive module selection for a memory comprising a plurality of modules, the selection of one of the memory modules being performed by a selection command obtained by decoding a memory address field, comprising at least a register (6) for latching said memory address field in the course of a current memory access operation, the outputs of said register being connected to the inputs of a decoding network (7,20) for generating said command, the contents of said register (7,20) being used for generating said selection command in the course of a subsequent memory access operation and a comparator (12) having inputs connected to the inputs and outputs of said register (6) for comparing the contents of said register (6) with an address field in input to said register and for providing an error and invalidation signal of the memory access operation in case of unequality, characterised in that said latching register (6) consists in a plurality of registers (6A,6B,6C,6D), each being devoted to the latching of an address field related to a predetermined class of information, said system comprising further selection means (12), controlled by control signals provided in addition to the memory address (SELA, SELB, SELC, SELD) indicative of the differing classes of information to select one among said register (6A,6B,6C,6D), to enable the selected one register to transfer the information stored therein to the inputs of said decoding network (7,20) and to load said selected one register with said address field present at the inputs of said plurality of registers. Memory system as in claim 1 comprising further logic means, enabled by said error signal, for converting a memory write command into a memory read command and thus suppressing the write command.

Inventors: PORRO ENRICO, ZULIAN FERRUCCIO, PORRO, ENRICO, ZULIAN, FERRUCCIO
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS ITALIA S.P.A.
Application year: 1989
Main classification: G06F12
IPC codes: G06F12