Input protection circuit for MOS device

Abstract: An input protection circuit for MOS devices includes a first resistor (12) and a first parasitic bipolar transistor (13) connected between an input pad (11) and an input buffer circuit (14) of a MOS device. The input protection circuit for MOS devices further includes a second resistor (16) and a second parasitic bipolar transistor (17) connected at a preceding stage of the input buffer circuit (14) so that the gate oxide film of the input buffer circuit (14) can be protected from being damaged by static charges or a voltage which is accidentally generated, without increasing the pattern size of the first parasitic bipolar transistor (13).

Description: This invention relates to an input protection circuit for MOS devices. In an ordinary MOS device, the gate thereof is isolated from the remaining portion thereof by a gate oxide film (SiO 2 film) which forms the dielectric layer between the gate and substrate. Since the gate oxide film is very thin, it may be destroyed in the same manner as other dielectric materials if an excessively high voltage is applied to the gate. As a result, the gate and substrate may be short-circuited and the device will be destroyed permanently. Therefore, special care must be taken so as not to accidentally apply excessive charges to the gate. Fig. 2 shows an input protection circuit serving as a protection device for the conventional MOS device. Input pad 1 is connected to one end of resistor (R) 2 formed of a diffusion layer or polysilicon layer and the other end of the resistor is connected to the emitter of parasitic bipolar transistor 3. The collector and base of parasitic bipolar transistor 3 are respectively connected to power source terminal Vss (ground potential) and power source terminal VBB (substrate potential). The other end of resistor 2 is connected to the gate in input buffer circuit 4. In Fig. 2, 5 denotes a parasitic capacitor, (C). The conventional circuit of the above construction may be insufficient in its ability to protect the gate oxide film of the MOS device from being damaged by static charges or a voltage which is accidentally applied to the gate. For example, in Fig. 2, resistor 2 is formed near input pad 1 and the wiring distance between resistor 2 and input buffer circuit 4 is long. Accordingly, the capacitance of parasitic capacitor (C) 5 is large, therefore the resistance of resistor (R) 2 cannot be large from the viewpoint of wave formation (that is, the waveform will become deformed due to RC). As a result, it is necessary to increase the pattern size of parasitic bipolar transistor 3. From Electronics, volume 59, No. 31, September 1986, pages 78 to 81, New York, US; "TI's BLAZING-FAST CMOS LOGIC TAKES ON SCHOTTKY BIPOLAR" a circuit for protecting the input of MOS devices is known which includes a diffused transistor connected at its connector and emitter between the input line of the MOS device and a supply voltage terminal. Moreover, a resistor is provided in the input line. From patent abstract of Japan, volume 10, 125 (E-402) [2182], 10th May, 1986 a protection circuit for MOS devices is known which protects the input of the MOS device against excessive input voltages by means of a network including resistors and diodes. The resistor network serves to divide the input current flowing due to the excessive input voltage such that each diode of the network has to handle a fraction of the flowing current only. As described above, in order to enhance the ability to protect the gate oxide film of the MOS device from being damaged by static charges or a voltage which is accidentally applied to the gate, it is necessary to increase the pattern size of the parasitic bipolar transistor. An object of this invention is to provide an input protection circuit for MOS devices in which the gate oxide film can be protected from being damaged by static charges or a voltage which is accidentally applied to the gate, without increasing the pattern size of the clamp element (for example parasitic bipolar transistor) and without causing deformation of an input signal waveform. The above object can be attained by an input protection circuit for MOS devices, comprising: An input protection circuit for MOS devices, comprising: an input pad ; an input buffer circuit of said MOS device; a first resistor connected at its one terminal to said input pad; a first transistor connected at its emitter with the other terminal of said first resistor, its base and collector, respectively, being connected with a substrate terminal and a power source terminal, respectively; characteterized by a second resistor connected between said emitter of said first transistor and said input buffer circuit ; and a second transistor connected at its emitter with said input buffer circuit, its base and collector, respectively, being connected with said substrate terminal and said power source terminal, respectively; said first transistor being a parasitic transistor formed near said input pad and said second transistor being a parasitic transistor formed near said input buffer circuit; the resistance of said second resistor being higher than that of said first resistor; a capacitance of a parasitic capacitor of a wiring from said second transistor to said input buffer circuit being lower than a capacitance of a parasitic capacitor of a wiring from said first transistor to said second transistor. With this circuit the gate oxide film of the input buffer circuit can be protected from being damaged by static charges or a voltage which is accidentally applied to the gate, without increasing the pattern size of the first clamp element. Fig. 1 is a circuit diagram of an input protection circuit for MOS devices according to one embodiment of this invention; and Fig. 2 is a circuit diagram of the conventional input protection circuit for MOS devices. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows an input protection circuit for MOS devices according to one embodiment of this invention. Input pad 11 is connected to one end of first resistor (R1) 12 with a resistance of, for example, 100 Ω, formed of a diffusion layer, polysilicon or wiring material, and the other end of first resistor 12 is connected to a clamp element, such as the emitter of first parasitic bipolar transistor 13 formed of an NPN bipolar transistor. The collector and base of first parasitic bipolar transistor 13 are respectively connected to power source terminal Vss (ground potential) and power source terminal VBB (substrate potential). The other end of first resistor 12 is connected to one end of second resistor (R2) 16 with a resistance of 1 KΩ, for example, formed of a diffusion layer, polysilicon or wiring material, and the other end of second resistor 16 is connected to a second clamp element, such as the emitter second parasitic bipolar transistor 17 formed of an NPN bipolar transistor. The collector and base of second parasitic bipolar transistor 17 are respectively connected to power source terminals Vss and VBB. The other end of second resistor 16 is also connected to the gate of input buffer circuit 14 having at least one MOS device. In Fig. 1, 15 denotes a parasitic capacitor (C1) of the wiring having a capacitance of 2 pF, for example, and 18 denotes a parasitic capacitor (C2) of the wiring having a capacitance of 200 fF, for example. An object of this invention is to enhance the ability to protect the gate oxide film of the input buffer circuit formed of a MOS device from being damaged by a voltage which is accidentally generated and causes stress, without increasing the pattern size of first parasitic bipolar transistor 13. To this end, in this embodiment, second resistor (R2) 16 with a resistance of 1 KΩ, for example, formed of a diffusion layer, polysilicon or wiring material, and second parasitic bipolar transistor 17 are connected at a stage immediately before input buffer circuit 14. In order to introduce second parasitic bipolar transistor 17 into the circuit, second resistor 16 is used. The capacitance (C2) of parasitic capacitor 18 of the wiring, which is 200 fF, is less than that (C1) of parasitic capacitor 15 of the wiring, which is 2 pF. Thus, the resistance (R2) of second resistor 16 can be increased to 1 KΩ, without causing the deformation of the waveform. Hence, the current flowing in second parasitic bipolar transistor 17 is small, and transistor 17 requires only a small pattern area. As described above, according to this invention, the second resistor and the second parasitic bipolar transistor, having a small pattern size, are connected at a stage immediately before the input buffer circuit having a MOS device so that the ability to protect the gate oxide film of the first parasitic bipolar transistor from being damaged can be enhanced without increasing the pattern size of the first parasitic bipolar transistor. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: An input protection circuit for MOS devices, comprising: an input pad (11); an input buffer circuit (14) of said MOS device; a first resistor (12) connected at its one terminal to said input pad (11); a first transistor (13) connected at its emitter with the other terminal of said first resistor (12), its base and collector, respectively, being connected with a substrate terminal (V BB ) and a power source terminal (V SS ), respectively; characterized by a second resistor (16) connected between said emitter of said first transistor (13) and said input buffer circuit (14); and a second transistor connected at its emitter with said input buffer circuit (14), its base and collector, respectively, being connected with said substrate terminal (V BB ) and said power source terminal (V SS ), respectively; said first transistor (3) being a parasitic transistor formed near said input pad (11) and said second transistor (17) being a parasitic transistor formed near said input buffer circuit; the resistance of said second resistor (16) being higher than that of said first resistor (12); a capacitance (C2) of a parasitic capacitor (18) of a wiring from said second transistor (17) to said input buffer circuit (14) being lower than a capacitance (C1) of a parasitic capacitor (15) of a wiring from said first transistor (13) to said second transistor (17).

Inventors: IMADA SADAO, OKADA YOSHIO, SHIMIZU MITSURU, IMADA, SADAO, OKADA, YOSHIO, SHIMIZU, MITSURU, IMADA, SADAO C/O INTELLECTUAL PROPERTY DIVISION, OKADA, YOSHIO C/O INTELLECTUAL PROPERTY DIVISION, SHIMIZU, MITSURU C/OINTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1989
Main classification: H03K17
IPC codes: H03K19, H03K17, H01L29, H01L27