Microwave integrated circuit

Abstract: In a microwave integrated circuit, a series circuit of an inductive element (6) and a variable capacitance element (7) is inserted between a source of a field effect transistor (5) of an initial stage circuit and ground. The capacitance of the variable capacitance element (7) is controlled by an input signal applied to an external terminal (10) so that an input impedance of the initial stage circuit is properly changed by the input signal applied to the external terminal (10). Thus, it is possible to set a system to an input matching characteristic which has both a noise matching characteristic and a gain matching characteristic which fit to a system specification.

Description: Background of the Invention (Field of the Invention) The present invention relates to a low noise amplification microwave integrated circuit (hereinafter MIC) for use in a satellite broadcasting receiving converter or microwave communication, and more particularly to an improvement in an input matching characteristic thereof. (Related Background Art) One of prior art low noise amplification MICs uses a monolithic MIC (hereinafter MMIC) which uses a field effect transistor such as a GaAs FET. A general circuit configuration of the MMIC is shown in Fig. 1 in which a source of a FET 21 is grounded, an input matching circuit 22 is connected to an input terminal of MMIC and an output matching circuit 23 is connected to an output terminal of MMIC. In an input matching characteristic of an initial stage amplifier in a multi-stage amplification MMIC circuit, either a noise matching characteristic which requires a low noise characteristic is important or a gain matching characteristic which requires a high gain characteristic is important, depending on an application of the circuit. Constants of elements in the input matching circuit 22 are set in accordance with the characteristic. In the prior art MMIC, the matching characteristic of the initial stage amplifier has been designed by taking primary consideration of only one of the noise matching characteristic and the gain matching characteristic, depending on the application. The circuit designed primarily for the noise matching characteristic can provide a minimum noise figure (hereinafter NF) but a gain of the initial stage amplifier is low and an input voltage standing wave ratio (hereinafter VSWR) is high. In the circuit designed primarily for the gain matching characteristic, the gain of the initial stage is high and the input VSWR is low, but the NF is high. An example for a high frequency amplifyer can be found in DE-A-3 327 107. Summary of the Invention The present invention as defined in the appended claims intends to solve the problems mentioned above. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention. Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the scope of the invention as defined by claims will become apparent to those skilled in the art from this detailed description. Brief Description of the Drawings Fig. 1 is a block diagram of a prior art circuit configuration, Fig. 2 is a block diagram of one embodiment of the present invention, and Fig. 3 is a Smith chart for a signal source impedance Z opt and an input reflection coefficient S₁₁* in the embodiment. Description of the preferred Embodiments The present invention is now explained in detail with reference to the drawings. Fig. 2 shows one embodiment of an initial amplification circuit of MMIC of the present invention. As shown in Fig. 2, a microwave signal is applied through a signal input terminal 1 to the initial stage amplification circuit, a capacitor 2 blocks a DC component of an input signal, a microstrip 3 is connected in series to the capacitor 2. Another microstrip 4 has one end thereof connected to a junction of the capacitor 2 and the microstrip 3. The microstrips 3 and 4 form an input matching circuit. A field effect transistor 5 (hereinafter FET) such as GaAs MESFET or HEMT has a gate thereof connected to the microstrip 3. An inductor 6 is constructed by a microstrip having one end thereof connected to a source of the FET 5. A variable capacitance diode 7 has an anode thereof connected to one end of the inductor 6 and a cathode thereof grounded and a microstrip 8 has one end thereof connected to a junction of the inductor 6 and the variable capacitance diode 7. A resistor 9 has one end thereof connected to the other end of the microstrip 8, and an external terminal 10 is connected to the other end of the resistor 9. Microstrips 11 and 12 are connected in series to a drain of the FET 5, and a microstrip 13 has one end thereof connected to a junction of the microstrip 11 and 12 and the other end thereof grounded. Those microstrips 11, 12 and 13 constitute an interstage matching circuit in the multi-stage circuit. A DC blocking capacitor 14 is connected to the microstrip 12, and an output terminal 15 is connected to a succeeding stage circuit. In the present circuit, a combined impedance Z is given by Z = jωL + 1/jωC = jω(L - 1/ω²C) where L is an inductance of the inductor 6, and C is a capacitance of the variable capacitance diode 7. The constants are selected such that L > 1/ω²C is met, where ω is an operating frequency band, and the capacitance C of the variable capacitance diode 7 is changed in accordance with the signal applied to the external terminal 10 so that the combined impedance Z is changed as a combined inductance L s . By changing the combined impedance Z, that is, by changing the combined inductance L s of the inductance 6 and the variable capacitance diode 7, Z opt (a signal source impedance which causes a minimum NF) and S₁₁* (a complex conjugate number of the input reflection coefficient) are controlled such that Z opt and S₁₁* change on the Smith chart shown in Fig. 3 in a manner shown by arrows. The reason therefore is explained below. The input impedance Z in of the FET 5(which corresponds to S₁₁ in the Smith chart) is given by: Z in = R G +R in +R s +G m ·L s /C gs +1/(j·ω·C gs ) where R G : gate resistance of the FET 5 R in :channel resistance R s : source resistance C gs : gate-source capacitance G m : transfer conductance Z opt is represented by: Z opt = R opt + j (X opt - ω/L s ) where R opt * real part of the signal source impedance which causes a minimum NF by the FET 5 alone. X opt : imaginary part thereof As seen from the formula (2), the real part of the input impedance Z in changes in accordance with the combined impedance L s . As the combined impedance L s is increased by the signal applied to the external terminal 10, the complex conjugate number S₁₁* of S₁₁ changes as shown by the arrow on the Smith chart of Fig. 3. Namely, it changes along a constant reactance line in a direction to increase the resistance. The imaginary part of the signal source impedance Z opt changes in accordance with the combined impedance L s . As the combined impedance L s increases, Z opt changes as shown by the arrow on the Smith chart. Namely, it changes along a constant resistance circle in a direction to reduce the reactance. Accordingly, by properly selecting the combined impedance L s (Z) by the input signal applied to the external 10, S₁₁* and Z opt approach to each other on the Smith chart so that the trade-off between the noise matching characteristic and the gain matching characteristic is optimized. While the initial stage amplification circuit of the MMIC has been described in the present embodiment, the present invention is applicable to a multi-stage amplification type MMIC in which a plurality of the initial stage amplification circuits are connected in series. While the MMIC has been described in the present embodiment, the present invention is also applicable to a hybrid MIC and a discrete component circuit with a similar advantage. From the invention thus described, it will be obvious that the invention may be varied in many ways. Such variations are not to be regarded as a departure from the scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims: A microwave integrated circuit having a plurality of circuit components integrated therein, comprising: initial stage amplification means having a field effect transistor (5); series circuit means (6, 7) having an inductive element (6) connected in series with a variable capacitance element (7), said inductive element (6) consisting of a microstrip line provided in the circuit, one end of said series circuit means being connected to a source of said field effect transistor (5) and the other end being connected to ground, and control means (8, 9) including a circuit with a micro-strip (8) and a resistor (9) which are serially connected for controlling the capacitance of said variable capacitance element (7) by an external signal, one end of said control means (8, 9) being connected to a junction of said variable capacitance element (7) and said inductive element (6), and said external signal being applied to the other end of said control means (8, 9). A microwave integrated circuit according to claim 1, wherein a gate of said field effect transistor (5) is electrically connected to an input terminal (1) of said microwave integrated circuit. A microwave integrated circuit according to claim 1 or 2, wherein said variable capacitance element comprises a variable capacitance diode (7). A method of controlling a microwave integrated circuit according to any preceding claim, characterized by changing the capacitance of said variable capacitance element (7) in a range which meets L > 1/ω²C where L is an inductance of said inductive element and ω is an operating frequency band.

Inventors: SHIGA NOBUO C O YOKOHAMA WORKS, SHIGA, NOBUO C/O YOKOHAMA WORKS OF SUMITOMO
Applicants: SUMITOMO ELECTRIC INDUSTRIES, SUMITOMO ELECTRIC INDUSTRIES, LTD.
Application year: 1989
Main classification: H03F3
IPC codes: H01P5, H01L21, H03H7, H03H11, H01L29, H03F3