Data processing unit having a bypass circuit

Abstract: In a data processing unit which includes first and second buses, and an arithmetic and logic unit (21), there are provided a register file (22) connected between the first and second buses, for storing data on the second bus, the register file including a plurality of register portions (22a, 22b, 22c) having a capacity equal to or exceeding a minimum data length of data processed in the ALU (21), and a bypass circuit (23) connected between the first and second buses for bypassing data on the second bus to output the data to the first bus per a unit of the minimum data length, the bypass circuit including a plurality of bypass lines (23a, 23b, 23c) each having the minimum data length. A control circuit (24, 25) controls data read and data write for the register file per a unit of the minimum data length and controlling the bypass circuit so as to bypass the data on the second bus to the first bus per a unit of the minimum data length.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to a data processing unit having a bypass circuit, and in particular to a data processing unit having a bypass circuit which can cope with a bypass control for various data having different data length (word length) with high flexibility. Generally, data processing in a data processing unit such as a computer and a microprocessor is carried out with respect to a register file. By using a register file, high-speed data processing can be done without being limited by the access speed of an external memory. However, a delay may occur in data processing even with the register file, because it takes a time to renew or rewrite data in the register file. Referring to FIGS.1 and 2, a processing block 1 subjects input data Din to a predetermined data processing, and produces output data Dout in a processing cycle 1 ○. The output data Dout is then written into a register file 2 ○. Thereby, the content of the register file is renewed with the output data Dout during a processing cycle 2 shown in FIG.2. Thereafter, when the next data processing step using the just written data (hatched data) is required, necessary data including the hatched data are read out from the register file 2 in a processing cycle 3 ○, and the desired data processing is carried out. It can be seen from the above-mentioned description that the data processing which uses the just written (renewed) data cannot be performed immediately after the processing cycle 2 ○, or in other words, must be kept waiting during the processing cycle 2 ○. This causes a delay of data processing. In order to overcome the above-mentioned problem, a bypass control has been proposed. FIG.3 shows the basic arrangement for a conventional bypass control. As shown, a bypass circuit 3, which is arranged between data buses, functions to pass the processed data Dout derived from the processing block 1 and supply the processing block 1 with the bypassed data Din as it is. When the register file 2 is renewed with the processed data Dout supplied from the processing block 1, which is to be used in the next data processing, the processed data Dout is passed through the bypass circuit 3 and is supplied, as the input data Din, to the processing block 1. Then, the processing block 1 carries out the next data processing by referring to the bypassed input data. In this manner, the bypass circuit 3 enables it to be possible to perform both the next data processing and renewal of the register file 2 at the same time. Such a data processing unit having a bypass circuit is known from document "IBM TECHNICAL DISCLOSURE BULLETIN", vol. 19, no. 1, June 1976, New York, US, page 265, L.C. Eggebrecht: 'Microprocessor high speed ALU input buffer with data save and restore capability'. This document discloses a data processing unit with first and second buses, processing means, register file means comprising a plurality of register portions and bypass means including a plurality of bypass lines. Furthermore, control means for controlling data read and data write are described. FIG.4 illustrates a procedure of the above-mentioned data processing. It can be seen from FIG.4 that the first data processing operation and the following data processing operation can be carried out in successive processing cycles 1 ○ and 2 ○. However, in the conventional bypass control, the register file 2 and the bypass circuit 3 are designed so as to be in conformity with a large-scale computer designed to process data having a specific (fixed) word length. For this reason, the structure of FIG.3 is not suitable for a small-scale computer where word length of data is not fixed but variable. FIG.5 is a view illustrating the above-mentioned problem. It is assumed that a data processing is subjected to low-order bytes of word length data D1 and D2 stored in the register file 2, and the low-order byte of a word length data in the register file 2 is reversed with a resultant data R, and that a revised word-length data D3 including the data R is used in the next data processing. In this case, only the data R is allowed to pass through the bypass circuit 3, while the high-order byte of the data D3 is still placed in the register file 2. Therefore, at this time, the processing block 1 cannot refer to the word length of data. For this reason, in practical use, after the renewal of the the register file 2 ends, the word-length data having the revised low-order byte R in the register file 2 is read out therefrom and used in the next data processing step. This means the loss of the advantages provided by the bypass control. As a result, a delay of data processing cannot be effectively overcome even when the bypass control is employed. SUMMARY OF THE INVENTION It is therefore a general object of the present invention as claimed to provide a data processing unit having a bypass circuit in which the above-mentioned disadvantages are eliminated. A more specific object of the present invention as claimed is to provide a data processing unit having a bypass circuit which is capable of coping with variable data length data with an increased data processing speed. The above objects of the present invention as claimed can be achieved by a data processing unit having a bypass circuit which includes first and second buses ; processing means for subjecting input data supplied from the first bus to a predetermined operation, thereby supplying the second bus with output data; register file means connected between the first and second buses, for storing data on the second bus, the register file means including a plurality of register portions having a capacity equal to or exceeding a minimum data length of data processed in the processing means; bypass means connected between the first and second buses, for bypassing data on the second bus to output the data to the first bus per a unit of the minimum data length, the bypass means including a plurality of bypass lines each having the minimum data length; and control means for controlling data read and data write for the register file means per a unit of the minimum data length and controlling the bypass means so as to bypass the data on the second bus to the first bus per a unit of the minimum data length. Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a block diagram of the conventional data processing unit having no bypass circuit; FIG.2 is a view illustrating the flow of data in the data processing unit of FIG.1; FIG.3 is a block diagram of the conventional data processing unit having a bypass circuit; FIG.4 is a view illustrating the flow of data in the data processing unit of FIG.3; FIG.5 is a view illustrating the problem presented in the data processing unit of FIG.3; FIG.6 is a block diagram of the basic structure of a preferred embodiment of the present invention; FIG.7 is a view illustrating operation of the embodiment; FIG.8 is a timing chart illustrating the operation of the embodiment; FIG.9 is a block diagram illustrating the detailed structure of the embodiment; FIG.10 is a block diagram of an example of a register file used in the structure of FIG.9 FIG.11 is a circuit diagram of registers used in the structure of FIG.10; FIG.12 is a circuit diagram of an example of a memory cell provided in the register file shown in FIG.11; FIG.13 is a circuit diagram of an example of a data transmit controlling circuit used in the structure of FIG.9; FIG.14 is a block diagram of an example of a bypass circuit used in the structure of FIG.9; FIG.15 is a timing chart showing read/write operation with respect to the register file shown in FIG.10; and FIG.16 is a timing chart showing operation of the embodiment when the bypass operation is required. DESCRIPTION OF THE PREFERRED EMBODIMENTS A description is given of a preferred embodiment of the present invention. FIG.6 shows the basic structure of a preferred embodiment of the present invention. A data processing unit 11 of the embodiment includes a processing block 12, a register file 13, and a bypass circuit 14, which are connected to a first bus 15 and a second bus 16. The number of lines included in each of the first and second buses 15 and 16 corresponds to a maximum word length which the processing block 12 can handle, 4n bits (n is an integer), for example. The processing block 12 is an arithmetic and logic unit, for example, and carries out a predetermined operation such as numerical operation and logical operation to data which are input therein through the first bus 15. The result of the predetermined operation is supplied to the second bus 16. The numerical operation executed in the process block 12 includes addition, subtraction, multiplication, division and the like. The logical operation executed in the processing block 12 includes logical add, logical product and the like. The above-mentioned operations can be achieved by an adder for a predetermined number of bits. That is, the word length of data to be processed depends on the number of bits which can be handled by the addition circuit (or arithmetic and logic circuit). For example, it is assumed that the processing block 12 is designed to process data having a data length of 1 byte (8 bits = n bits), 2 bytes (2n bits) or 4 bytes (4n bits). In this case, a data length of 1 byte is a minimum word length consisting of n bits, and an adder for use in 1 byte is employed. In place of such an adder, an adder for a half-byte (n/2 bits) may be used. In this case, a half-byte is the minimum word length. The register file 13 includes a group of registers each capable of reading and writing data at a high speed. Each register in the register group consists of the number of bits (n), which corresponds to the minimum word length, and is coupled with the first bus 15 through n number of signal lines. The bypass circuit 14 is connected to the second bus 16 on the side of input terminals thereof, and is connected to the first bus 15 on the side of output terminals thereof through four groups of signal lines, in which each group of signal lines consists of n number of signal lines. The bypass circuit 14 connects 4n signal lines of the second bus 16 to the first bus 15 per a unit of n number of signal lines. The following are now assumed with reference to FIG.7. (I) A logical operation is carried out for two-byte length data [A] stored in the register file 13 and reference data [RA] of 1 byte. Then, the low-order byte data [AL] stored in the register file 13 is revised with an operation result [AL′]. (II) Next, a high-order byte [AU] of the data [A] stored in the register file 13 and the operation result [AL′] are referred to, and a desired logical operation is carried out for two-byte length data of [AU] + [AL′]. It is noted that according to the conventional method, the above-described procedure (II) cannot be done until renewal of the register file 13 is completed. On the other hand, according to the present embodiment, the processed low-order byte data [AL′] is sent to the first bus 15 through the bypass circuit, and at the same time, a register in the register group which stores the high-order byte [AU], is made opened so that the byte data [AU] on the first bus 15 is output. Thereby, data consisting of bytes [AU] + [AL′] are available on the first bus 15. As a result, it becomes possible to execute the above-mentioned procedure (II) at the same time as the register file 13 is renewed, so that the delay of data processing can be prevented. FIG.8 is a view showing processing cycles of the above-mentioned data processing. In a processing cycle 1 ○ the register file 13 starts to be renewed with the processed low-order byte data [AL′], which is also bypassed through the bypass circuit 14. In a processing cycle 2 ○ subsequent to the processing cycle 1 ○ the bypassed low-order byte data [AL′] and the high-order byte data [AU] stored in the register file 13 becomes available on the first bus 15. As a result, the processing cycles 1 ○ and 2 ○ can be successively executed, so that no delay occurs. FIG.9 is a block diagram showing an example of the detailed structure for the data processing unit 11 of FIG.9. A data processing unit 20 includes a processing block 21, a register file 22, a bypass circuit 23, a data transmit controlling circuit 24, a controller 25, first and second buses 26 and 27, an input buffer 30, an output buffer 31, a microsequencer 32 and an instruction decoder 33. The processing block 21 corresponds to the processing block 12 shown in FIG.6, and, as necessary, subjects data having a data length of any of 1 byte to 4 bytes to a desired operation. The register file 22 corresponds to the register file 13 shown in FIG.6, and is composed of three registers 22a, 22b and 22c. The bypass circuit 23 corresponds to the bypass circuit 14, and is made up of three bypass lines 23a, 23b and 23c. The data transmit controlling circuit 24 controls the register file 22 and the bypass circuit 23. The controller 25 controls the register file 22 and the data transmit controlling circuit 24. For this purpose, the controller 25 generates various control information, which will be described later. Each of the first and second buses 26 and 27 includes 32 signal lines which correspond to 4 bytes and are numbered as [31 - 0]. The input buffer 30 is interposed between the first bus 26 and an external bus 28, to which an external memory 29 is coupled, for example. The input buffer 30 inputs data supplied from an external circuit such as the external memory 29 through the external bus 28, and sends the same on the first bus 26. The output buffer 31 is interposed between the external bus 28 and the second bus 27, and sends data on the second bus 27 to the external circuit such as the external memory 29. The instruction decoder 33 decodes an instruction supplied from an external circuit such as a central processing unit (not shown). The microsequencer 32 controls the controller 25 and the processing block 21 such as an arithmetic and logic circuit in accordance with the decoded instruction supplied from the instruction decoder 33. The first and second buses 26 and 27 are connected to the processing block 21, the register file 22 and the bypass circuit 23. The processing block 21 are connected to the first and second buses 26 and 27 through signal lines [31 - 0] provided on sides of input and output terminals thereof. The first and second buses 26 and 27, and the register file 22 are mutually connected as follows. The registers 22c, 22b and 22a are respectively provided with bits [31 -16], [15 - 8] and [7 - 0] of data on the second bus 27. The outputs of the registers 22a, 22b and 22c are connected to the first bus 26 through signal lines which transmit bits [31 -16], [15 - 8] and [7 - 0], respectively. In the same manner, and the bypass circuit 23 which consists of three bypass lines 23a, 23b and 23c, are connected to the first and second buses 26 and 27. Table 1 shows data to be sent through the bypass circuit 23 to the first bus 26, based on combinations of the renewal size for the register file 22 and a size of data to be processed in the next data processing step (defined as a reference size) which corresponds to procedure (II) shown in FIG.7. Table 2 shows data read out from the register file 22 to the first bus 26, based on combinations of the renewal size for the register file 22 and the reference size. In Tables 1 and 2, a mark 'o' indicates data to be sent on the first bus 26. It can be seen from Tables 1 and 2 that even when the combination of the renewal size and the reference size relates to any one of word, half-word and byte, necessary data is available on the first bus 26, so that the necessary data can be supplied to the processing block 21. It follows that the present invention can cope with variable length data with high flexibility, which results in an increased data processing speed. A description is given of the detailed structure of the register file 22 shown in FIG.9 by referring to FIG.10. A data latch circuit 41 temporarily stores data consisting of bits numbered as [31 - 0] supplied from the second data bus 27. A register 42 consists of 16 registers #0 - #15, each of which consists of 32 bits. FIG.11 is a circuit diagram of the register 42. Referring to FIG.11, WD31 - WD0 indicate write word lines, and RD31 - RD0 indicate read data lines. Each of the word data lines WD31 - WD0 is connected to a terminal T3 of corresponding memory cells 42c arranged in each of the registers #0 - #15. The word data lines WD31 - WD0 are also connected to corresponding inverters 42b, which are connected to terminals T4 of the corresponding memory cells 42c provided in each of the registers #0 - #15. The read data line RD15 - RD0 are connected to terminals T5 of corresponding memory cells 42c provided in each of the registers #0 - #15. The read data line RD31 - RD0 are connected to corresponding inverters 42d, and are pulled up to a positive potential Vcc through corresponding registers R connected at input terminals of the inverters 42d. A write word line 43 is provided for each of the registers #0 - #15. The write word line 43 consists of first, second and third write word lines 43a, 43b and 43c, respectively. The first, second and third write word lines 43a, 43b and 43c are connected to AND gates 39a, 39b and 39c, respectively. The AND gates 39a, 39b and 39c relating to the registers #1, #2,..., #15 are provided with decoded write selection codes WR-SEL0, WR - SEL1,..., WR-SEL15, respectively, which are derived from a write decoder 49 (FIG.10) by decoding a write selection code WR-SEL supplied from the controller 25. The AND gates 39a, 39b and 39c are also supplied with a write timing signal  W supplied from the controller 25 (FIG.9). An output terminal of the AND gate 39a provided for each register is connected to terminals T1 of the memory cells 42c connected to the write data lines WD7 - WD0. An output terminal of the AND gate 39b provided for each register is connected to terminals T1 of the memory cells 42c connected to the write data lines WD15 - WD8. An output terminal of the AND gate 39c provided for each register is connected to terminals T1 of the memory cells 42c connected to the write data lines WD31 - WD16. The first, second and third word lines 43a, 43b and 43c are connected to output terminals of AND gates 45a, 45b and 45c shown in FIG.10, respectively. An input terminal of each AND gate 45a, 45b and 45c is supplied to a write enable signal WR, and the other input terminal thereof is connected to a write size decoder 46. A write size code RW-SIZE is derived from the controller 25 shown in FIG.9, and is supplied to the write size decoder 46. The write size decoder 46 decodes the write size code WR-SIZE, and generates a write word code which consists of three bits. A binary value "1" is always output on the first write word line 43a. Bits W2 0 and W2 1 are output on the second and third write word lines 43b and 43c, respectively. A read word line 44 provided for each of the registers #0 - #15 is connected to terminals T2 of all the memory cells 42c. Decoded read selection codes RD-SEL0, RD-SEL1,..., RD-SEL15 derived from a read decoder 47 (FIG.10) are transferred on the corresponding read word lines 44. The read decoder 47 is supplied with a read selection code RD-SEL, which is supplied from the controller 25 shown in FIG.9. FIG.12 is a circuit diagram of each memory cell 42c. The memory cell 42c includes three metal oxide semiconductor (hereafter simply referred to as MOS) transistors Tr1, Tr2 and Tr3, and inverters INV1 and INV2, which are connected as shown in FIG.12. The read data lines RD7 - RD0 are connected to a tri-state buffer 48a, and the read data lines RD15 - RD8 are connected to a tri-state buffer 48b. The read data lines RD31 - RD16 are connected to a tri-state buffer 48c. The tri-state buffers 48a, 48b and 48c are supplied, through control lines 50a, 50b and 50c, with read instruction signals RD-INS1, RD-INS2 and RD-INS3, respectively. As will be described in detail later, the read instruction signals RD-INS1, RD-INS2 and RD-INS3 are generated by the data transmit controlling circuit 24. FIG.13 is a circuit diagram of the data transmit controlling circuit 24. A read signal RD derived from the controller 25 is supplied to an AND gate 67, which is also supplied with a read timing signal  R generated by the controller 25. An output of the AND gate 67 is connected to AND gates 52 through 57. A comparator 51 compares the content of the read selection code RD-SEL with the content of the write selection code WR-SEL, when the write enable signal WR is supplied from the controller 25. As described previously, the read and write selection codes RD-SEL and WR-SEL are also supplied from the controller 25. When the content of the read selection code RD-SEL coincides with the content of the write selection code WR-SEL, the comparator 51 outputs a binary value of "1" (high level). The output signal of the comparator 51 is fed to AND gates 58, 59 and 60. AND gates 61 and 62 are supplied with bits W2 0 and W2 1 of the decoded write size code, respectively, which is generated, by a decoder 66, from the write size code WR-SIZE supplied from the controller 25. The bits W2 0 and W2 1 are identical to those to be supplied to the AND gates 39b and 39c shown in FIG.11. The AND gates 61 and 62 are also supplied with bits R2 0 and R2 1 of a decoded read size code, respectively, which is generated, by the decoder 66, from a read size code RD-SIZE supplied from the controller 25. The AND gate 58 is always supplied with a binary value of "1" from the decoder 66. As described previously, the present embodiment can process data of the size of byte, half-word and word. Table 3 shows the relationship between the write size and values of the write size code WR-SIZE. Table 4 shows the relationship between the read size and values of the read size code RD-SIZE. Output signals of the AND gates 61 and 62 are supplied to the AND gates 59 and 60, respectively. The output terminal of the AND gate 58 is connected directly to the AND gate 55, and also the AND gate 52 through an inverter 65. The output terminals of the AND gates 59 and 60 are connected to inverters 63 and 64, and also the AND gates 56 and 57, respectively. The output terminals of the inverters 63 and 64 are connected to the AND gates 53 and 54. The AND gates 53 and 54 are supplied with bits R2 0 and R2 1 of the read selection code RD-SEL. Output signals of the AND gates 52, 53 and 54 are supplied, as read instruction signals RD-INS1, RD-INS2 and RD-INS3, to the tri-state buffers 48a, 48b and 48c through the control lines 50a, 50b and 50c, respectively. Output signals of the AND gates 55, 56 and 57 are control signals BY-CONT1, BY-CONT2 and BY-CONT3, respectively, and are supplied to the bypass circuit 23. FIG.14 is a block diagram of the bypass circuit 23. The bypass circuit comprises latch circuits 71, 72 and 73, and tri-state buffers 74a, 74b and 74c. The latch circuits 71, 72 and 73 are supplied with data bits [7 - 0], [15 - 8] and [31 - 16], respectively. The tri-state buffers 74a, 74b and 74c are connected to the latch circuits 71, 72, and 73, respectively, and are controlled by the control signals BY-CONT1, BY-CONT2 and BY-CONT3, respectively. A description is given of read/write operation with respect to the register 42 when no bypass operation is performed, with reference to FIG.15. At the commencement of write operation, data on the second bus 27 is input in the data latch circuit 41. At this time, the write enable signal WR is kept at the high level, the write selection code WR-SEL and the write size code WR-SIZE are supplied to the write decoder 49 and the write size decoder 46, respectively. The write size code WR-SIZE is decoded by the write size decoder 46, and in a clock phase T2, the decoded write size code consisting of bits 1, W2 0 , W2 1 is supplied to the register 42 through the AND gates 45a, 45b and 45c. In the clock phase T2, the decoded write selection codes WR-SEL0 to WR-SEL15 are supplied to the registers #0 to #15, respectively. Thereafter, in a clock phase T2, the write clock  W is switched to the high level, and thereby the data latched in the data latch circuit 41 is written into memory cells 42c of the register which is designated by the decoded write selection code and the decoded write size code. In a clock phase T3, the read selection code RD-SEL is supplied to the read decoder 47 (FIG.10), and the read size signal RD-SIZE is supplied to the read size decoder 66 (FIG.13). The read instruction signals RD-INS1 to RD-INS3, and the control signals BY-CONT1 to BY-CONT3 has corresponding levels based on the combination of the decoded write size code and the decoded read size code. When there exists no requirement for the bypass operation, the write selection code WR-SEL and the read selection code RD-SEL do not coincide with each other. Therefore, the comparator 51 outputs no signal, or in other words, is kept at a low level. As a result, the AND gates 58, 59 and 60 are kept in the closed state, so that the control signal BY-CONT1 to BY-CONT3 are kept at the low level, and thereby the tri-state buffers 48a, 48b and 48c (FIG.10) are kept closed. Then in a clock phase T2 in the second cycle, a read timing signal  R is switched to the high level, and thereby the data designated by the read size code RD-SIZE and the read selection code RD-SEL is read out and output to the first bus 26. A description is given of the bypass operation with reference to FIG.16. The data on the second bus 27 is latched in the data latch circuit 41. The write selection code WR-SEL and the write size code WR-SIZE are supplied to the write decoder 49 and the write size decoder 46 (FIG.10), respectively. It is now assumed that the write size code WR-SIZE represents "byte". In clock phase T2, the write timing signal  W is switched to the high level, and thereby bits [7 - 0] of the latched data are written to the corresponding register in the register file 47. On the other hand, the controller 25 is already outputting the read selection code RD-SEL and the read size code RD-SIZE. It is now assumed that the read size code RD-SIZE indicates "word". The write selection code WR-SEL and the read selection code RD-SEL are supplied to the comparator 51 (FIG.13), which compares them with each other when the write enable signal WR is supplied thereto. When the bypass operation is required, the write selection code WR-SEL and the read selection code RD-SEL coincide with each other. Therefore, the comparator 51 produces the comparison result of the high level, which is supplied to the AND gates 58 - 60 (FIG.13). Bits W2 0 and W2 1 of the decoded write size code WR-SIZE derived from the decoder 66 are supplied to the AND gates 61 and 62 (FIG.13), respectively. At this time, the write size code WR-SIZE supplied to the decoder 66 is the same as the write size code WR-SIZE supplied to the write size decoder 46 (FIG.10). Bits R2 0 and R 1 of the decoded read size code RD-SIZE derived from the decoder 66 are supplied to the AND gates 61 and 62, respectively. In the present example, the designated write size is "byte". Therefore, both the bits W2 0 and W2 1 are 0. As a result, the control signal BY-CONT1 is 1, and the control signals BY-CONT2 and BY-CONT2 are 0. On the other hand, the designated read size is "word". Therefore, both the bits R2 0 and R 1 are 1. As a result, the read instruction signal RD-INS1 is 0 and the read instruction signals RD-INS2 and RD-INS2 are 1. During the one cycle of the bypass operation, the read signal RD (not shown in FIG.16) is kept at the high level, and the read timing signal  R is switched to the high level at the start of the clock phase 2. Therefore, the AND gates 52 to 57 (FIG.13) are made open. As a result, only the tri-state buffer 74a (FIG.14) is made open and is allowed to pass through bits [7 -0] latched in the latch circuit 71, and on the other hand, the tri-state buffers 48b and 48c (FIG.10) are made open, and are allowed to pass through bits [31 - 8] output from the register 42. In the alternative, it is possible to provide the controller 25 with the comparator 51 and the decoder 66 without providing the data transmit controlling circuit 24 with those parts. The present invention is not limited to the embodiments, and variations and modification may be made without departing from the scope of the present invention.

Claims: A data processing unit comprising a) first and second buses (26, 27); b) processing means (21) for subjecting input data supplied from said first bus (26) to a predetermined operation and sending output data of the result of said operation to said second bus (27); c) register file means (22) connected between said first and second buses (26, 27) for storing data on said second bus (27), said register file means including a plurality of register portions (22a, 22b, 22c) having a capacity equal to or exceeding a minimum data length of data processed in said processing means (21); d) bypass means (23) connected between said first and second buses (26, 27) for bypassing data on said second bus (27) to output said data to said first bus (26) with said minimum data length or a multiple thereof, said bypass means including a plurality of bypass lines (23a, 23b, 23c), each having said minimum data length; and e) control means (24, 25) for controlling data read and data write for said register file means (22) with said minimum data length or a multiple thereof and for controlling said bypass means (23) so as to bypass said data on said second bus (27) to said first bus (26) with said minimum data length or a multiple thereof, characterized in that said second control means (24, 25) designates bypass portions through which data on said second bus (27) is sent to said first bus (26) on the basis of a write size which indicates a data length of data to be written into said register file means (22) and a read size which indicates a data length of data to be read out from said register file means (22); and said bypass means (23) bypasses said data on said second bus (27) to said first bus (26) when data write and data read are carried out for the same register among said registers. A data processing unit as claimed in claim 1, characterized in that said control means comprises first control means (25) for designating at least one of said register portions (22a, 22b, 22c) in which said data on said second bus is to be written, and second control means (24) for designating at least one of said register portions (22a, 22b, 22c) from which data is to be read out and to be supplied to said first bus (26) and for designating at least one of said bypass lines (23a, 23b, 23c) through which said data on said second bus (27) is sent to said first bus (26). A data processing unit as claimed in any of claims 1 and 2, characterized in that said first means (25) designates said register portions in which said data on said second bus (27) is to be written, on the basis of a write size which indicates a data length of data to be written into said register file means (22). A data processing unit as claimed in any of claims 1 to 3, characterized in that said second means (24) designates register portions from which data is read out, on the basis of a read size which indicates a data length of data to be read out from said register file means (22). A data processing unit as claimed in any of claims 1 to 4, characterized in that said register file means (22) comprises data latch means (41) for latching said data on said second bus (27), a plurality of registers (42, #0 - #15) for storing data supplied from said latch means, and selector means (48a, 48b, 48c) for selecting data which is to be read out from one of said plurality of registers and is to be sent to said first bus (26). A data processing unit as claimed in any of claims 1 to 5, characterized in that when said processing means (21) is capable of handling data of 1 byte to 4 bytes, said register file means (22) includes three register portions (22a, 22b, 22c), and each of two of said register portions (22b, 22c) consists of 8 bits, and the remaining register portion (22a) consists of 16 bits. A data processing unit as claimed in any of claims 1 to 6, characterized in that said bypass means (23) comprises a plurality of latch means (71, 72, and 73) for latching said data on said second bus (27), and selector means (74a, 74b, 74c) for selecting at least one of said latch means to connect the selected register to said first bus (26). A data processing unit as claimed in any of claims 1 to 7, characterized in that said processing means (21) comprises an arithmetic and logic unit. A data processing unit as claimed in any of claims 1 to 8, characterized by further comprising instruction decoder means (32) for decoding an instruction code supplied from an external circuit, and microsequencer means (33) for controlling said control means (24, 25) based on a decoded instruction code supplied from said instruction decoder means (32). A data processing unit as claimed in any of claims 1 to 9, characterized by further comprising input buffer means for sending said first bus (26) data supplied from an external circuit (29), and output buffer means for sending said external circuit (29 ) data on said second bus (27).

Inventors: KANAMARU KOUJI, SATO TAIZO, KANAMARU, KOUJI, SATO, TAIZO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: G06F9
IPC codes: G06F9, G06F7