Device for generating a reference voltage for a switching circuit including a capacitive bootstrap circuit

Abstract: This device for generating a reference voltage for a capacitive bootstrap circuit of an output stage can be easily integrated. The output stage comprises a driving block (1), a capacitive bootstrap circuit (3) and a reference voltage generating block (2) generating a floating reference voltage which is referred to the output voltage signal and switches in accordance thereto.

Description: The present invention relates to a device for generating a reference voltage for a switching circuit including a driving block controlled by an input switching signal and a capacitive bootstrap circuit, in particular for an output stage. As is known, transistors implemented in MOS technology are often used to manufacture output stage circuits. Such output stages comprise N-channel MOS transistors which are driven by a high supply voltage, the drain of said transistors being connected to a positive supply line. It is also known that a problem which occurs with such output stages is that of ensuring a correct driving voltage for the gate electrode of the MOS transistors, so as to ensure the operation of the device as a low-resistance switch (with a gate-source voltage V GS above 10 V). To this end, a capacitive bootstrap circuit is provided. An example of a prior art circuit applied to a half-bridge is shown in figure 1. A similar circuit is disclosed in document GB-A-1 180 422. Such a circuit comprises capacitive bootstrap circuitry and output stage circuitry, the output stage being driven so as to generate a periodic wave-form signal V OUT which oscillates between a low voltage, which is about O V in the example being considered, and a high voltage substantially equal to a first supply voltage V CC . In particular, two output transistors T₁ and T₂ are provided in order to generate the periodic wave-form signal and are driven by two driving elements DR. According to the input signal V IN , said two transistors T₁ and T₂ are alternately switched in the ON and OFF state so that the output signal switches between the low voltage of O V and the high voltage V CC . The bootstrap circuitry substantially comprises two elements, i.e. the bootstrap capacitor C B and the bootstrap diode D B . When the transistor T₁ is off and the transistor T₂ is on, V OUT is connected to the ground and therefore is in the LOW state. In this condition, the bootstrap capacitor C B is charged through the bootstrap diode D B at a voltage equal to the difference between a second supply voltage, for example 12 V, and the voltage drop across the bootstrap diode D B . In the reverse condition, i.e. with the transistor T₁ in the ON state and the transistor T₂ in the OFF state, the potential of the source electrode of the transistor T₁ rises toward the value of the first reference voltage V CC , and the bootstrap capacitor maintains the supply to the driving elements DR at about V CC + 12V. As can be seen, in this stage the bootstrap diode is reverse biased, and its reverse biasing voltage is equal to the first supply voltage (V CC ), thus decoupling the bootstrap capacitor from the second supply voltage. The problem which arises in the above descibed circuit is that of satisfying two contrasting requirements. In fact, an output signal having a good dynamic behavior (i.e. considerable amplitude) is required on one hand, while on the other hand it must be possible to integrate the bootstrap capacitor. In order to satisfy the first of the above mentioned requirements, the bootstrap diode D B must have a high breakdown voltage, since, as said, when the output voltage V OUT is high, the diode D B has applied thereto a reverse biasing voltage which is equal to the first reference voltage V CC . This condition is troublesome (in view of the required integration) when the required breakdown voltage of the diode is in the range of hundreds of volts. On the other hand , in the direct biasing state, the bootstrap diode must have low losses toward the substrate. This is a problem when the diode is implemented by a base to collector junction in order to have high breakdown: in fact in this case the diode is associated with a parasitic vertical PNP transistor. Therefore the problem arises that it is difficult to integrate a small size diode with a high breakdown and low current losses toward the substrate, and this problem becomes the bigger, the higher is the supply voltage V CC . Therefore, the aim of the present invention is to provide a device for generating a reference voltage for a bootstrap circuit, in particular for an output stage, which allows said output stage to generate and supply at the output a high-amplitude voltage signal. Within this aim, a particular object of the present invention is to provide a device which can be easily integrated and can be manufactured with conventional technologies, i.e. bipolar or MOS technology. Another object of the present invention is to provide a device for generating a reference voltage for the bootstrap circuit which is able to eliminate the problems associated with a high breakdown voltage and affecting the prior art. Not least object of the present invention is to provide an integrated device producible with conventional methods, as mentioned above, can be obtained at a cost which is relatively low and in any case comparable to that of known similar circuits. The above described aim and objects, as well as others which may become apparent hereinafter, are achieved by a device for generating a reference voltage for a bootstrap circuit having the features of the characterizing part of claim 1. The characteristics and advantages of the invention will become apparent from the following detailed description of a preferred but not exclusive embodiment of the present invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a circuit diagram of an output stage with a prior art bootstrap circuit; figure 2 is a block diagram of the output stage and of the bootstrap circuit according to the teachings of the present invention; and figure 3 is a circuit diagram of an embodiment of the present invention, implemented in MOS technology. With specific reference to figure 2, the output stage comprises a driving block 1, a reference voltage generating block 2 and a bootstrap circuit 3. In particular, the driving block 1 has an input IN receiving a switching input signal V IN , having for example a square wave-form, and an output OUT supplying output voltage V OUT . Said input switching signal is sent to the input of a driving element DR2 and the same switching signal is also sent to a further driving element DR1 after being inverted by an inverter element indicated at N. The outputs of the driving elements are applied to the gate electrodes of a first switching transistor M1 and a second switching transistor M2; more specifically, the output of the driving element DR2 is applied to the gate electrode of the switching transistor M2 while the output of the driving element DR1 is applied to the gate electrode of the first switching transistor M1. As is apparent, the switching transistors illustrated in figure 1 are manufactured with MOS technology, but this must not be regarded as a limitation, since said transistors may naturally be manufactured according to any other conventional technology. As can be seen, the source electrode of the first transistor M1 is connected to the drain electrode of the second transistor M2 so as to supply said output OUT, while the source electrode of the second transistor M2 is connected to the ground and the drain electrode of the transistor M1 is connected to a first supply voltage indicated at V CC . The output signal V OUT is feedback to said reference voltage block 2 and said bootstrap circuit 3; said reference voltage block 2 is also connected to the first supply voltage line V CC and feeds a reference voltage V FL to the bootstrap diode D BOOT and to be bootstrap capacitor C BOOT . According to the invention, reference voltage V FL is floating and referred to the output voltage V OUT , and more precisely V FL follows the output voltage V OUT so as to have a convenient charging level for the bootstrap capacitor C BOOT when the output is low (near O V) and to have a high level (about V CC ) when the output is high. Therefore, when the output is low, the bootstrap capacitor can be charged at the desired level, while when the output is high, the voltage drop across the bootstrap diode D BOOT is low. Therefore, this diode may be easily integrated with low losses (e.g. by the emitter to base junction), while allowing the output stage to supply an output signal having high dynamics. Figures 3 illustrates in detail a possible implementation of the reference voltage generating block 2. As illustrated, said block comprises two Zener diodes, more specifically a first Zener diode DZ₁ and a second Zener diode DZ₂, having respective Zener voltages V Z1 and V Z2 ; said Zener diodes are mutually connected in series, with the anode of the diode second Zener diode DZ₂ being connected to the output OUT and the cathode thereof being connected to the anode of the first Zener diode DZ₁. Said circuit furthermore comprises a third transistor M3 preferably of the MOS type, the drain electrode whereof is connected to the first supply voltage line V CC ; its gate electrode is connected to the cathode of the first Zener diode DZ₁ and its source electrode is connected to the output OUT through a resistor R₂. As can be seen, a further resistor R₁ is interposed between the gate electrode of the third transistor M3 and the first supply voltage line V CC . The source electrode S of the transistor M3 is also connected to the anode of the bootstrap diode D BOOT , to supply the floating reference voltage V FL , which , as said, is referred to the output. In fact, when the input signal V IN causes the second transistor M2 to switch on, the first transistor M1 is off. The output voltage V OUT is low, since the point OUT is connected to the ground, and the bootstrap capacitor C BOOT is charged, through the bootstrap diode, to the voltage level of the source electrode of the third transistor M3, i.e. to the value V FL which is now equal to V Z1 + V Z2 - V GS (V GS being the gate-source voltage of the third transistor M3 which is on in this operating mode). By appropriately selecting the Zener diodes, the voltage V FL may be in the range of 12 V, like the second supply voltage, as is known in the art. Thus, the bootstrap capacitor charges at a voltage which is equal to the floating voltage V FL . Vice versa, when the input signal V IN causes the second transistor M2 to switch off and teh first transistor M1 on, the potential of the output OUT starts to rise toward the value of the first reference voltage line V CC , and the bootstrap capacitor maintains a constant voltage equal to the previous value of the floating voltage V FL so as to increase the supply of the driving elements. Since the floating voltage V FL is always related to the output voltage V OUT , until said output voltage V OUT remains lower than the first reference voltage V CC , the bootstrap diode is directly biased, and the problem of breakdown cannot therefore occur. Vice versa, when the output voltage V OUT reaches a value proximate to that of the reference voltage V CC , the third transistor M3 switches off, since the voltage across its drain and source electrodes becomes substantially equal to O V. In this condition, the anode of the bootstrap diode is connected through R₂ to the output voltage V OUT and is thus reversely biased; but the reverse voltage across said diode is now equal to 12 V, thus avoiding the problems due to the high breakdown voltage which are characteristic of the prior art. As is evident from the preceding description, the invention fully achieves the intended aim and objects. A circuit structure has in fact been provided which has, on one hand, no problems in integration, since the voltage between the anode and the cathode of the bootstrap diode during the diode reverse-biasing is low, and has, on the other hand, an output voltage with a high maximum or peak value, since said value is equal to the first supply voltage V CC . Therefore, the diode is not required to have a high breakdown voltage and thus may be implemented by the emitter-base junction, which has no vertical PNP parasitic transistors associated therewith. The invention as defined in the Claims is susceptible to numerous modifications and variations. In particular, the fact is stressed that though the described circuit structure has been implemented in MOS technology, the MOS transistors may naturally be replaced with bipolar transistors, for example of the NPN type. The described resistors may also be replaced with controlled current sources. In addition, all the details may be replaced with other technically equivalent ones, in sofar as such replacements are formally consistent with the definition of the invention according to the Claims. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly, such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: An output stage, comprising a driving block (1) interposed between a first reference potential line (V CC ) and a second reference potential line (GND), said driving block (1) having a signal input (IN) receiving an input switching signal (V IN ), a reference input connected to a further reference potential line (V FL ), and an output (OUT) generating an output switching signal (V OUT ), and a capacitive bootstrap circuit (3) connected between said output of said driving block and said further reference potential line, characterized in that it comprises means (2) for generating a floating reference voltage (V FL ) connected to said further reference potential line, said floating reference voltage switching in accordance with said output switching signal (V OUT ). Output stage, according to claim 1, characterized in that said means for generating a floating reference voltage comprises Zener diode means (D Z1 , D Z2 ) having its anode connected to said output (OUT) of said driving block (1), and its cathode connected to the gate electrode (G) of a transistor (M3) and to a reference potential line (V CC ) through first resistor means, control means (R₂) being interposed between the source electrode (S) of said transistor (M3) and said output (OUT) of said driving block, said control means being adapted to control said transistor (M3). Output stage according to claim 2, characterized in that said control means for said transistor comprise resistor means (R₂). Output stage according to claim 2, characterized in that said control means for said transistor comprise current source means. Output stage according to claim 1, characterized in that said output switching signal (V OUT ) switches between a low level (0 V) and a high level (V CC ), and in that, when said output switching signal switches to said low level, said floating reference voltage (V FL ) switches to a low state (12 V), higher than said low level of said switching output voltage signal for charging said capacitive bootstrap circuit (3), and when said switching output voltage signal switches to said high level, said floating reference voltage switches to a high state (V CC ), near to said high level. Output stage according to claim 2, 3 or 4, characterized in that said capacitive bootstrap circuit (3) comprises a feedback connection interposed between the source electrode (S) of said transistor (M3) and said output (OUT) of said driving block (1), said bootstrap circuit comprising a diode (D BOOT ), the anode whereof is connected to said source electrode of said transistor, and the cathode whereof is connected to the output of said driving block through bootstrap capacitor means (C BOOT ). Output stage according to claim 2, 3, 4 or 6, characterized in that said transistor (M3) comprises a MOS transistor. Output stage according to claim 2, 3, 4, 6 or 7, characterized in that said transistor (M3) comprises an NPN-type bipolar transistor. Output stage according to claim 2, 3, 4, 6, 7 or 8, characterized in that said Zener diode means comprise a plurality of Zener diodes (D Z1 ,D Z2 ) connected in series.

Inventors: BARSANTI ANDREA, DIAZZI CLAUDIO, VIO FABIO, BARSANTI, ANDREA, DIAZZI, CLAUDIO, VIO, FABIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1989
Main classification: H03K17
IPC codes: G01R29, H03K17, H03K5