DROP/INSERT CHANNEL SELECTING SYSTEM

Abstract: Disclosed is a drop/insert selecting system in an optical transmission system. To decrease the circuit scale, the system comprises a switching unit (4, 4') having a plurality of input terminals for receiving a plurality of input channels and a plurality of output terminals, each of the input channels conveying a frame synchronization signal and a channel number; at least one drop/insert unit (51, 52, 51', 52') for sequentially generating channel preselection signals until a frame synchronization is established, and for dropping or inserting necessary signals from or into a corresponding one of the necessary channels incorporated into the drop/insert units when a frame synchronization is established; and a channel selecting unit (6, 6a, 6b) for generating a plurality of channel selecting signals in response to each of the channel preselection signals, each of the channel selecting signals functioning to connect each of the output terminals to one of the plurality of input terminals; the remaining output terminals of the switching unit being connected to through-channels to which no drop/insert means is connected.

Description: DESCRIPTION TITLE OF THE INVENTION Drop/Insert Channel Selecting System TECHNICAL FIELD The present invention relates to a drop/insert channel selecting system in an optical transmission system in which an orderwire signal or a supervisory and control signal is dropped or inserted. BACKGROUND ART In an optical transmission system, to transmit an orderwire signal or a supervisory and control signal , it is advantageous, in view of effective utilization of an optical fiber, to superimpose these subsignals on a main signal passing through the optical fiber. These subsignals are usually transmitted to or received from a line terminating equipment. In recent years, however, accompanied by the developments in large capacity optical .transmission systems, requirements have increased to drop or insert the subsignals at any desired repeater such as in a regenerator or, in other words, an intermediate repeater arranged between line terminal equipments. Such an intermediate repeater having a drop/insert function is referred to in this specification as a D/I repeater. When a D/I repeater is provided, then, between these D/I repeaters, or between the line terminal equipment and the D/I repeater, subsignals such as the orderwire signal or the supervisory and control signal can be transmitted and received through two or more specified channels. These subsignals are required to be dropped or inserted at a desired D/I repeater. In the conventional intermediate repeaters, drop/insert units for dropping or inserting necessary signals are provided for all channels regardless of whether or not the signals on the channels need not be dropped or inserted. In the intermediate repeaters, however, there are signals such as communication data which need not be dropped or inserted from or into channels. Herinafter these signals which need not be dropped or inserted are referrred to as through- channel signals. Therefore, there is a problem in that the number of the drop/insert units in a conventional intermediate repeater is so large that the circuit scale of the conventional intermediate repeater is large. In particular, for a high-speed data, since it is difficult to directly drop or insert subsignals from or into a high-speed data, the high-speed data is usually converted into a plurality of low-speed data channels of for example 400 Mb/s by a serial-parallel conversion, and the subsignals are dropped or inserted from or into one of the parallel channels. In this case, a suitable channel selecting circuit has to be developped. If a limited number of dro /insert units are provided to correspond to only the necessary channels other than the through-channels, the circuit for selecting the through- channels must be as simple as possible. However, conventional circuits for selecting these thro ugh- channels are very complex. Namely, these circuits are formed by a random logic circuit constructed of 20 to 30 integrated circuits ( IC's) so that the circuit scale becomes large and is opposite to the requirement to construct a D/I repeater as simple as possible. From another point of view, if the intermediate repeater has the dro /insert function, the constitution thereof becomes similar to that of the line terminal equipment so that these repeaters can be manufactured with the same design. Conventionally, however, the line terminal equipment and the intermediate repeater are manufactured with different system designs. The different system designs cause disadvantages in high manufacturing cost, in complex control of the repeaters, and in preparing different kinds of spare repeaters for accidental faults. DISCLOSURE OF THE INVENTION The present invention is created in view of these circumstances and has an object to provide a D/I repeater in which the number of drop/insert units is reduced . Another object of the present invention is to provide a D/I repeater which has a very simple channel selecting circuit for selecting through- channel signals. Still another object of the present invention is to provide a D/I repeater which has a similar circuit configuration to a line terminal equipment. To attain the above objects, there is provided, according to the present invention, a drop/insert selecting system for dropping or inserting necessary signals from or into necessary channels. The system comprises a switching unit having a plurality of input terminals for receiving a plurality of input channels and a plurality of output terminals. Each of the input channels conveys a frame synchronization signal and a channel number. At least one drop/insert unit is provided, each operatively connected to one of the output terminals of the switching unit, for sequentially generating channel preselection signals until a frame synchronization is established, and for dropping or inserting necessary signals from or into a corresponding one of the necessary channels incorporated into the drop/insert unit when a frame synchronization is established. A channel selecting unit is further provided, operatively connected to the switching unit and to the at least one drop/insert unit, for generating a plurality of channel selecting signals in response to each of the channel preselection signals, each of the channel selecting signals functioning to connect each of the output terminals to one of the plurality of input terminals . The remaining output terminals of the switching unit are connected to through-channels to which no drop/ insert unit is connected. According to one aspect of the present invention, the plurality of input terminals comprise a first , a second, a third and a fourth input terminals . The plurality of output terminals comprise a first, a second, a third and a fourth output terminals . The at least one drop/insert unit comprises a first and a second drop/ insert units , operatively connected to the first and the second output terminals , respectively. The through- channels comprises a first and a second through-channels , operatively connected to the third and the fourth output terminals , respectively . Each of the drop/insert units comprises a f rame synchronization detecting unit , operatively connected t o a corresponding one of the output terminals , for detecting an out of frame synchronization in the channel output from the corresponding output terminal; a comparing unit , operatively connected to corresponding one of the output terminals, for detecting a non-coincidence between the channel number in the channel output from said corresponding output terminal and a previouly stored channel number indicating the channel from which or into which signals are to be dropped or to be inserted; and a preselecting signal generating unit, operatively connected to the frame synchronization detecting unit and the comparing unit, for generating a two-bit presel ecting signal f or selecting one of the input terminals to be connected to the output terminal connected to the drop/insert unit under consideration, the two-bit preselecting signal being changed with a predetermined period until both of the out of f rame and the non-coincidence signals disappear. The system further comprises an out of frame protection circuit, operatively connected to the frame synchronization detecting unit, for effecting a front and a reat protection on the out of frame signal from the frame synchronization detecting unit; a non- coincidence signal protection circuit, operatively connected to the comparig unit, for effecting a front and a rear protection of the non-coincidence signal from the comparing unit; and a reframe protection circuit, operatively connected between the outputs of the out of frame protection circuit and the switching unit, and between the output of the non-coincidence protection circuit and the switching unit, for effecting a rear protection of the signal output from the out of frame protection circuit or the non- coincidence protection circuit. The preselecting signal generating unit comprises: a clock signal generating unit for generating a clock signal; and a frequency dividing unit, operatively connected to the clock signal generating unit, to the frame synchronization detecting unit, and to the comparing unit, for generating the two-bit preselecting signal in response to the clock signal until both of the out of frame signal and the non- coincidence signal disappear. The system further comprises: a counter unit, operatively connected to the frequency dividing unit, for counting at least the maximum average refraining time from the detection of an out of frame state. According to still another aspect of the present invention, the channel selecting unit comprises: two pair of lines, operatively connected to the first and the second drop/insert units, for directly passing the two channel preselection signals output from the first and the second drop/insert units, to the switching unit, as a first and a second channel selecting signals for selecting one of the input terminals to be- connected to the first output terminal and another one of the input terminals to be connected to the second output terminal, respectively; a first NOT gate for inverting the first bit in the first channel preselection signal to output a first bit of a third channel selecting signal for selecting one of the input terminals to be connected to the third output terminal; a second NOT gate for inverting the second bit in the first channel preselection signal to output a second bit of a fourth channel selecting signal for selecting one of the input terminals to be connected to the fourth output terminal; a third NOT gate for inverting the first bit in the second channel preselection signal to output a first bit of the fourth channel selecting signal for selecting one of the input terminals to be connected to the fourth output terminal; and a fourth NOT gate for inverting the second bit in the second channel preselection signal to output a second bit of the third channel selecting signal for selecting one of the input terminals to be connected to the third output terminal. According to a further aspect of the present invention, the plurality of input terminals comprise a first, a second, a third and a fourth input terminals; the plurality of output terminals comprise a first, a second, a third and a fourth output terminals; the at least one drop/insert unit comprise a first, a second, a third, and a fourth drop/insert units, operatively connected to the first, the second, the third, and the fourth output terminals, respectively; the third and the fourth drop/insert units being optionally plugged in the drop/insert system; and the third and the fourth drop/insert units providing detecting signals (DT) , indicating that the third and the fourth drop /insert units are plugged in, to the channel selecting unit when plugged into the drop/insert system. According to still further aspect of the present invention, the plurality of input terminals comprise a first, a second, a third and a fourth input terminals; the plurality of output terminals comprise a first, a second, a third and a fourth output terminals; the at least one drop/insert unit comprise a first, a second, a third, and a fourth drop/insert units, optionally plugged in the drop/insert system, and operatively connected to the first, the second, the third, and the fourth output terminals, respectively when plugged into the drop/ insert unit; the first, the second, the third and the fourth drop/insert units providing detecting signals to the channel selecting unit when plugged into the drop/insert system. According to still further aspect of the present invention, the channel selecting unit comprises: a first NOT gate for inverting the first bit in the first channel preselection signal; a second NOT gate for inverting the second bit in the first channel preselection signal; a third NOT gate for inverting the first bit in the second channel preselection signal; a fourth NOT gate for inverting the second bit in the second channel preselection signal; a f if th» OT gate for inverting the first bit in the third channel preselection signal; a sixth NOT gate for inverting the second bit in the third channel preselection signal; a seventh NOT gate for inverting the first bit in the fourth channel preselection signal; an eighth NOT gate for inverting the second bit in the fourth channel preselection signal; a first gate circuit having a first input connected to the output of the first NOT gate and a second input connected to a first bit in the third channel preselection signal, for outputting, as a first bit in the third channel selection signals, either the first bit in the third channel preselection signal or the output of the first NOT gate, depending on whether the third drop/insert unit is plugged in or is not plugged in the drop/insert system respectively; a second gate circuit having a first input connected to the output of the fourth NOT gate and a second input connected to a second bit in the third channel preselection signal, for outputting, as a second bit in the third channel selection signal , either the second bit in the third channel preselection signal or the output of the fourth NOT gate, depending on whether the third drop/insert unit is plugged in or is not plugged in the drop/insert system respectively; a third gate circuit having a first input connected to the output of the third NOT gate and a second input connected to a first bit in the fourth channel preselection signal , for outputting , as ' a first bit in the fourth channel selection signal , either the first bit in the fourth channel preselection signal or the output of the third NOT gate , depending on whether the fourth drop/insert unit is plugged in or is not plugged in the drop /insert system respectively; a fourth gate circuit having a first input connected to the output of the second NOT gate and a second input connected to a second bit in the fourth channel preselection signal , for outputting, as a second bit in the fourth channel selection signal , e i the r th e s e c ond b i t in the f o urth channe l preselection signal or the output of the second NOT gate, depending on whether the fourth drop/insert unit is plugged in or is not plugged in the drop/insert system respectively; a fifth gate circuit having a first input connected to the output of the fifth NOT gate and a second input connected to a first bit in the first channel preselection signal, for outputting, as a first bit in the first channel selection signal , either the first bit in the first channel preselection signal or the output of the fifth NOT gate , depending on whether the first drop/insert unit is plugged in or is not plugged in the drop/insert system respectively; a sixth gate circuit having a first input connected to the output of the sixth NOT gate and a second input connected to a second bit in the first channel preselection signal, for outputting, as a second bit in the first channel selection signal , either the second bit in the first channel preselection signal or the output of the sixth NOT gate, depending on whether the second drop/insert unit is plugged in or is not plugged in the drop/insert system respectively; a seventh gate circuit having a first input connected to the output of the seventh NOT gate and a second input connected to a first bit in the second channel preselection signal , for outputting , as a first bit in the s econd channel selection signal , either the first bit in the second channel pres e l ecti on signal or the output of the s eventh NOT gate , depending on whether the thi rd drop/insert unit is plugged in or is not plugged in the drop/insert system respectively; an eighth gate circuit having a first input connected to the output of the sixth NOT gate and a second input connected to a second bit in the second channel presel ection signal , for outputting , as a second bit in the second channel selection signal , either the second bit in the second channel preselection signal or the output of the sixth NOT gate, depending on whether the fourth drop/insert unit is plugged in or is not plugged in the drop/insert system respectively; the outputs of the fifth and the sixth gate circuits being the first channel selecting signal for selecting one of the input terminals of the switching unit to be connected to the first output terminal of the switching unit; the outputs of the seventh and the eighth gate circuits being the second channel selecting signal for selecting one of the input terminals of the switching unit to be connected to the s econd output terminal of the switching unit; the outputs of the first and the second gate circuits being the third channel selecting signal for selecting one of the input terminal s of the switching unit to b e connected to the third output terminal of the switching unit; the outputs of the third and the fourth gate circuits being a fourth channel selecting signal for selecting one of the input terminals of the switching unit to be connected to the fourth output terminal of the switching unit. According to still further aspect of the present invention, the switching unit comprises a first, a second, a third, and a fourth switching parts arranged to correspond to the first drop/insert unit, the second drop/insert unit, the first through- channel , and the second through-channel, respectively; each of the switching parts having the plurality of input terminals and one of the output terminals connected to the corresponding one of the first drop/insert unit, the second drop/insert unit, the first through-channel, and the second through- channel; the third switching part and the fourth switching part having unit to fix, when the first or the second drop/insert unit is in an out of frame, their switching positions as the through channels. In this aspect, the third drop/insert unit and the fourth drop/insert unit are unplugged; the switching unit comprises a first, a second, a third, and a fourth switching parts arranged to correspond to the first drop/insert unit, the second drop/insert unit, the first through-channel, and the second through- channel, respectively; each of the switching parts having the plurality of input terminals and one of the output terminals connected to the corresponding one of the first drop/insert unit, the second drop/insert unit, the first through-channel, and the second through- channel; the third switching part and the fourth switching part having unit to fix, when the first or the second drop/ insert unit is in an out of frame, their switching positions as the through channels . BRIEF DESCRIPTION OF DRAWINGS The above objects and features of the present invention will be more apparent from the follwing description of the preferred embodiments with reference to the accompanying drawings, wherein: Figure 1 is a block diagram showing an optical transmission system for explaining the background of the present invention; Fig. 2 is a block diagram showing a conventional optical transmission system; Fig. 3 is a block diagram showing a general construction of one of drop/insert circuits D/I shown in Fig. 2; Fig. 4 is a block diagram showing an intermediate repeater according to an embodiment of the present invention; Fig. 5 is a block diagram showing the optical transmission system employing the intermediate repeater shown in Fig. 4 according to an embodiment of the present invention; Fig. 6 is a block diagram showing an example of the constitution of a channel selecting circuit in each of the D/I units shown in Fig. 5; Fig. 7 is a diagram for explaining the channel selecting operation in response to the channel selecting signal shown in Fig. 6 ; Fig. δ is a diagram showing the combinations of the channel selecting signals output from the D/I units shown in Fig. 6; Fig. 9 is a circuit diagram of an example of the channel selecting circuit shown in Fig. 6, according to an embodiment of the present invention; Fig. 10 is a circuit diagram of another example of the channel selecting circuit shown in Fig. 6, according to an embodiment of the present invention; Fig. 11 is a diagram showing a still another example of the channel selecting circuit shown in Fig. 6, according to an embodiment of the present invention; Fig. 12 is a block diagram showing another example of the* constitution of a D/I unit shown in Fig. 6, according to an embodiment of the present invention; Fig. 13 is a circuit diagram showing another example of the construction of the matrix switch and the channel selecting circuit shown in Fig. 6, according to another embodiment of the present invention; Fig. 14 is a timechart for explaining an operation from an out of frame to a channel selection in the circuit shown in Fig. 12, according to an embodiment of the present invention; and Fig. 15 is a timechart for explaining a reframe operation in the circuit shown in Fig. 12, according to an embodiment of the present inveniton. BEST MODE FOR CARRYING OUT THE INVENTION Throughout the specification and the accompanying drawings, the same reference numerals or the same reference symbols represent the same or corresponding parts. Figure 1 is a block diagram showing an optical transmission system as a background of the present invention. In the optical transmission system shown in Fig. 1, there are a plurality of regenerators (REG) R between line terminating equipments (LTE) T and T' . The regenerators are referred to in this specification as intermediate repeaters. Each of the intermediate repeaters also has a drop/insert function. Therefore, the intermediate repeaters are also referred to as D/I repeaters. Between these D/I repeaters, or between the line terminal equipment T or T' and a D/I repeater, orderwire signals or supervisory and control signals are transmitted and received. The general construction of the conventional line terminal equipments T and T ! and the conventional intermediate repeater R are shown in Fig. 2. In the figure, the transmitting line terminal equipment T includes a plurality of multiplexers MUX each for multiplexing three 150 Mb/s signals into a 450 Mb/s signal, and a parallel-serial converter P/S for converting the four 450 Mb/s parallel signals into a 1.8 Gb/s serial signal. The intermediate repeater R includes a serial-parallel converter S/P for converting the 1.8Gb/s parallel signal into four channels CHI to CH4 of 450 Mb/s parallel signals, a plurality of D/I units for dropping or inserting necessary subsignals, and a parallel-serial converter P/S for converting the four channels of 450 Mb/s parallel signals into a 1.8 Gb/s serial signal. The line terminal equipment T' includes a serial-parallel converter S/P for converting the 1.8 Gb/s serial signal into four channels CHI to CH 4 of 450 Mb/s parallel signals and a plurality of demultiplexers DMUX for demultiplexing the 450 Mb/s signal into three 150 Mb/s signals. In the transmitting line terminal equipment T, subsignals are also multiplexed with the 150 Mb/s main signals. In the receiving line terminal equipment T', subsignals are demultiplexed by the demultiplexers DMUX. The above-mentioned number of channels and the bit rates of the signals are of course only an example. The general construction of each D/I unit in the intermediate repeater R is shown in Fig. 3. In the figure, the D/I unit includes a demultiplexer (DMUX) 300, a multiplexer (MUX) 301, and a control circuit (CO 302. A part of the demulti lexed signals from the demultiplexer (DMUX) 300 are dropped into the control circuit (CO 302, while the remaining signals from the demultiplexer (DMUX) 300 are passed through and directly input to the multiplexer (MUX) 301. From the control circuit (CO 302, inserting signals are input to the multiplexer 301. For example, the input signal input to the demultiplexer (DMUX) 300 is a 1.8 Gb/s signal in which four channels of signals of 450 Mb/s are multiplexed. In the 1.8Gb/s signal, subsignals are superimposed on the respective channels of 450 Mb/s signals. In such a system, subsignals passing through two or more specified channels are required to be dropped or inserted at the D/I units corresponding to the specified channels . On the other hand, there are through- channel signals such as communication data which need not be dropped or inserted at any D/I unit. However, as shown in Fig. 2, conventionally, the D/I units are provided on the respective channels regardless of whether or not the signals are the through- channel signals. Therefore, for the through-channel signals, the D/I units connected to the channels are wasted. Further, the circiut for selecting the thro ugh- channel signals must be as simple as possible. However, conventional circuits for selecting these through- channel signals are formed by a random logic circuit constructed of 20 to 30 integrated circuits ( ICs) so that the circuit scale becomes large and is opposite to the requirement to construct by a simple D/I repeater. Figure 4 is a block diagram showing an intermediate repeater for explaining the principle of the present invention. In the figure, the intermediate repeater includes an input unit 1, i.e., an optical receiving unit, two drop/insert units (D/I) 51 and 52, and an output unit 7. The input unit 1 includes an opto-electric converter (O/E) 2, a serial -parallel converter (S/P) 3 for converting a 1.8 Gb/s serial signal into four 450 Mb/s parallel signals, and a matrix switch 4 for switching the input channels in response to channel selecting signals SELl to SEL4. The drop/insert unit (D/I) 5 has a demultiplexer and a multiplexer arranged back to back as shown in Fig. 3. The channel selecting circuit 6 receives channel preselecting signals (al, bl) and (a2,b2) for preselecting channels to be dropped or inserted from or into the drop/insert unit (D/I) 5. Each of the channel preselecting signals is formed by a combination of two bits, i.e., al and bl or a2 and b2. In response to the channel preselecting signals, the channel selecting circuit 6 outputs, to the matrix switch 4, the channel selecting signals SELl = (al,bl) and SEL2 = (a2,b2) for selecting the channels through which signals to be dropped or inserted are transmitted and, in addition, channel selecting signals SEL3 = (al,b2) and SEL4 = (a2,bl) for selecting the channels through which no signal is to be dropped or inserted. Herinafter, the channels through which signals to be dropped or inserted are transmitted are referred to as drop/insert channels, and the channels through which no signal is to be dropped or inserted are referred to as through- channels. It should be noted that each of the through- channel selecting signal SEL3 or SEL4 is formed by an inverted bit of the first bit of one of the preselecting signals and an inverted bit of the second bit of another one of the preselecting signals. This is important for selecting the through-channels by means of a simple circuit. The output unit 7 includes a parallel-serial converter (P/S) 8 for converting the four 450 Mb/s parallel signals into a 1.8 Gb/s serial signal, and an electro-optic converter (E/O) 9 . In operation, the signals through the drop/insert channels CHI and CH2 are input from the input unit 1 to the drop/insert units 51 and 52 and are dropped therefrom. The signals to be inserted are input from a control circuit (not shown in Fig. 4) into the drop/insert units 51 and 52 and inserted into the channels CHI and CH2. On the other hand, the signals passing through the through-channels CH3 and CH4 are transmitted directly to the output unit 7 without passing through the drop/ insert unit 51 or 52. The selection of the drop/insert channels CHI and CH2 or the through-channels CH3 and CH4 is carried out by the channel selection circuit 6. Namely, in response to the channel preselecting signals (al,bl) and (a2,b2) for preselecting the drop/insert channels, the channel selecting signals SELl to SEL4 are output from the channel selecting circuit 6 to the matrix switch 4 so as to control the through- channels CH3 and CH4. In other words, when the channel preselecting signals from the drop/insert unit 5 are (al,bl) and (a2, b2), the channel selecting circuit 6 generates the channel selecting signals SEL3 ( a3 ' , b3 ' ) = (al,b2) and SEL4(a4' ,b4' ) = (a2,bl) for selecting the through- channels . Figure 5 is a block diagram showing an optical transmission system including the D/I repeater according to an embodiment of the present invention. In the figure, a transmitting line terminal equipment T and a D/I repeater R are connected through an optical fiber F. Also, the D/I repeater R and a receiving side line terminal equipment T' are connected through another optical fiber F. The transmitting line terminal equipment T includes a plurality of multiplexers 10 each for multiplexing three lines of 45 Mb/s to a 150 Mb/s, four multiplexers 11 each for multiplexing three lines of 150 Mb/s to a 450 Mb/s, a serial to parallel converter (P/S) 12 for converting the four parallel 450 Mb/s signals into a 1.8 Gb/s signal, and an electro-optic converter (O/E) 13 for converting the 1.8 Gb/s signal into an optical signal . The construction of the D/I repeater R is substantially the same as that shown in Fig. 4. In Fig. 5, the D/I repeater R includes a central control unit (CO 53 which is connected to a personal computer (PC) 54 to which a data terminal 55, a telephone terminal 56 , a printer 57 and the like are connected. The drop/insert units 51 and 52 each has a multiplexer and a demultiplexer arranged back to back as shown in Fig. 3. From the D/I units 51 and 52, channel preselecting signals (al,bl) and (a2,b2) for preselecting the dro /insert channels are output to the channel selecting circuit 6. The receiving line terminal equipment T' includes an opto-electric converter (O/E) 14 for converting the 1.8 Gb/s optical signal from the intermediate repeater R into a 1.8 Gb/s electric signal, a matrix switch 16, demulti lexe s 171 and 172 including four demultiplexers 1711, 1712, 1721, and 1722 each for demultiplexing a 450 Mb/s signal into three 150 Mb/s, a channel selecting circuit 18, and a plurality of demultiplexers 19 each for demultiplexing the 150 Mb/s signal into 45 Mb/s signals. Fig. 6 is a block diagram showing the construction of the D/I units 51 and 52 in the intermediate repeater R shown in Fig. 5. In the figure, the D/I units 51 and 52 respectively include frame synchroniztion detecting parts 51a and 52a, channel number comparing parts 51a and 51b for comparing channel numbers previously set from setting terminals 51c and 52c with channel numbers in the received channels from the matrix switch 4, OR gates 51d and 52d for gating the outputs of the frame synchronization detecting parts 51a and 52a and the comparing parts 51b and 52b, oscillators 51e and 52e, NAND gates 51f and 52f , and one-fourth frequency dividing circuits 51g and 52g. The frame synchronization detecting part 51a previously outputs an Out Of Frame signal OOF when it can not find a frame synchronizing signal FR in the channel received from the matrix switch 4. The channel number comparing part 51b outputs a discord signal when the channel number in the received channel does not. coincide with the previously stored channel number, when at least one of the Out Of Frame signal OOF and the non-coincide signal NC is output, it is gated through the OR gate 51d to be output as an alarm signal ALM. While the alarm signal ALM is being generated, the output of the oscillator 51e is gated through the NAND gate 51 . The clock-signal oscillator 51e outputs a clock signal of about several KHz to the NAND gate 51f . The frequency of the oscillator 51e is determined by the maximum time required to detect a frame. The maximum time for detecting the frame is referred to as a Maximum Average Reframing Time MART, and in this example, it is about 70 # seconds. The output of the NAND gate 51f is input to the one-fourth frequency dividing circuit 51g. The frequency dividing circuit 51g includes two dividing stages. From the two dividing stages, a 2-bit channel preselecting signal (al,bl) is output for selecting a channel to be dropped or to be inserted. The circuit construction of the D/I unit 52 is the same as the D/I unit 51 described above. The parts corresponding to the parts 51a to 51g are denoted by 52a to 52g. From the two stages in the frequency divider 52g, a 2-bit channel preselecting signal (a2,b2) is output for selecting a channel to be dropped cr to be inserted. The channel selecting circuit 6 receives, from the D/I units 51 and 52, the channel preselecting signals (al,bl) and (a2,b2) for preselecting the channels to be dropped and to be inserted, and generates the same channel selecting signals SELl (al ' ,bl ' ) = (al,bl) and SEL2(a2 r ,b2' ) = (a2,b2) for selecting the input channels to be dropped and to be inserted, and also generates the other channel selecting signals SEL3(a3',b ' 3') = (al,b2) and SEL4(a4 ! ,b4' ) = (a2,bl) for selecting the channels not to be dropped and to be inserted. These selecting signals SELl to SEL4 are applied to the matrix switch 4. Figure 7 is a diagram showing an example of an operation of the D/I unit 51 shown in Fig. 6. In Fig. 7. the matrix switch 4 has four input terminals #1 to #4 and four output terminals #1' to #4'. It is assumed that the first output terminal #1' is at first connected to the first input terminal #1 ' to which the input channel of the channel number #1 is connected in response to the channel selecting signal (al',bl') = (0,0). It is also assumed that the channel number #2 is previously stored in the channel number comparing part 51b. Then, when the power of the D/I repeater R is turned ON, since the channel number #1 does not coincide with the previously stored channel number #2, an alarm signal ALM indicating an out of frame synchronization is output from the NAND gate 51f. In response to the alarm signal ALM, the one-fourth frequency divider 51d generates a cahnnel preselecting signal (al,bl). The signal bl has one-half the frequency of the clock signal CL. The signal al has one-fourth the frequency of the clock signal CL. The channel selecting signal is at first turned from (0,0) to (1,1). In response to this channel selecting signal (1,1), the output of the matrix switch 4 is connected to the input channel of the channel number #4. The channel number #4 also does not coincide with the previously stored channel number #2. Therefore, the alarm signal ALM does not disappear. The channel selecting signal is then turned from (1,1) to (1,0) so that the output of the matrix switch 4 is connected to the input channel of the channel number #3. The channel number #3 also does not coincide with the previously stored cahnnel number #2. Therefore, the alarm signal also does not disappear. When the channel selecting signal then becomes (al,bl) = (0,1) so that the output cf the matrix switch 4 is connected to the input channel of the channel number #2, the channel number #2 coincides with the previously stored channel number #2, and therefore, the alarm signal ALM disappears. When the alarm signal ALM disappears, the signal on the channel of the channel number #2 is input to the D/I unit 51. Similarly to the second, third, and fourth output terminals #2',#3 ! , and #4', the input channels #1 to #4 are connected sequentially in response to the channel selecting signals (al' ,bl' ), (a2',b2' ), (a3',b3'), and (a4',b4'). The operation of another D/I unit 52 is quite similar to that of the D/I unit 51 described above, and the description thereof is omitted here. Figure 8 is a diagram showing all combinations of the channel s-electing signals SEL( al ' ,bl ' ) , (a2 ? ,b2 f ), (a3',b3'), and (a4',b4 ! ). As will be seen from Fig. 8, when (al',bl ! ) = (0,0), then (a2',b2 ! ) may be (0,0), (0,1), (1,0), or (1,1); 3',b3') may be (1,1), (1,0), (1,1), or (1,1); and (a4',b4') may be (1,1), (1,1), (0,1), or (0,1), respectively. The channel selecting signals (0,0), (0,1), (1,0), and (1,1) respectively select the input channels #1, #2, #3, and #4 to be connected to the output terminals of the matrix switch 4. For the channel selecting signal (al,bl) = (0,1), (1,0), or (1,1), there are also four combinations of each of the other channel selecting signals (a2,b2), (a3,b3), and (a4,b4) . Note that, for the combinations of the channel selecting signals marked b -& , there are the same channel selecting signals for the different channels . This means that the same input channel is connected to different output channels in the matrix switch 4. This causes an indefinite operation of the D/I units and abnormal operation with respect to the through-channels. These indefinite or abnormal operations, however, also occur even when the other channels selecting system is employed. Such an indefinite or abnormal operation can be detected at a line terminal equipment and the like by detecting an out of frame signal OOF. Therefore, the combinations of the channel selecting signals marked by > *• do not cause any problem. Figure 9 is a circuit diagram showing an example of the channel selecting circuit wherein the output channels CH3 and CH4 are fixed to be through- channels. In the figure, the channel selecting circuit 6 includes four signal lines for directly passing the prechannel selecting signals (al,bl) and (a2,b2) for selecting the input channels #1 and #2 to be dropped or to be inserted to output the selecting signals SELKal', bl') and SEL2(a2' ,b2' ) , and four NOT circuits 61 to 64 for inverting the codes of the signals on the respective signal lines. By this construction, the channel selecting signal SEL3(a3 ' ,b3' ) is determined as (al,b2) and the channel selecting signal SEL4 (a4 ' ,b4 ' ) is determined as (a2,bl). Namely, the first bit al in the cahnnel preselecting signal (al,bl) is inverted by the NOT circuit 61 to output the first bit a3 ' in the third channel selecting signal SEL3(a3',b3' ; the second bit bl in the channel preselecting signal (al,bl) is inverted by the NOT circuit 62 to output the second bit b4 ' in the fourth channel selecting signal SEL ( a3 ' , b3 * ) ; the first bit a2 in the channel preselecting signal (a2,b2) is inverted by the NOT circuit 63 to output the first bit a4' in the fourth channel selecting signal SEL4(a4' ,b4 f ) ; and the second bit b2 in the channel preselecting signal (a2,b2) is inverted by the NOT circuit 64 to output the second bit b3' in the third channel selecting signal SEL3(a3' ,b3' ) . Since the channel selecting signals for selecting the through -channels can be determined by the use of only the channel selecting signals for selecting the drop/insert cahnnels, the channel selecting circuit 6 can be formed by a small scale circuit of only two or three ICs . Figure 10 is a circuit diagram of a channel selecting circuit according to another embodiment of the present invention in which a part of the channels are selectively used as through-channels or drop/insert channels. In the figure, a channel selecting circuit 6a includes four gate circuits 65 to 68 each consisting of three NAND gates and a NOT gate 69, in addition to the two pair of signal lines for directly passing the channel selecting signals (al,bl) and (a2,b2) as the channel selecting signals SEL(al r ,bl') and SEL2(a2', b2') and the four NOT circuits 61 to 64 in the circuit shown in Fig. 9. A D/I unit detecting signal DT representing whether or not D/I units corresponding to the channels CH3 and CH4 is mounted on the D/I repeater R. When no D/I unit corresponding to the channels CH3 and CH4 is mounted, the detecting signal DT is at a high level H, and when the D/I units corresponding to the channels CH3 and CH4 is mounted, the detecting signal DT is at a low level L. When the detecting signal DT is at the high level H, the gate circuit 65 selects the output of the NOT circuit 61, i.e., al, as the first bit a3' of the channel selecting signal SEL3; the gate circuit 66 selects the output of the NOT circuit 64, i.e., b2, as the second bit b3 ' of the channel selecting signal SEL3; the gate circuit 67 selects the output of the NOT circuit 66 i.e., a2, as the first bit a3' of the channel selecting signal SEL4; and the gate circuit 68 selects the output of the NOT circuit 62 i.e., bl, as the second bit b4' of the channel selecting signal SEL4. As a result, in this case, the channel selecting signals SEL3 and the SEL4 are the same as those in the channel selecting circuit shown in Fig. 9. When the detecting signal DT is at the low level L, the gate circuits 65 and 66 select the channel selecting signal (a3, b3) from the additional D/I units; and the gate circuits 67 and 68 select the channel selecting signal (a4, b4) from the additional D/I units. The additional D/I units are used in a repeater which has no through-channel. The switching NOT gate 69 and the gate circuits 65 to 68 are provided for selecting the channel selecting signals SEL3 and SEL4 to be (al,b2) and (a2,bl) or (a3,b3) and (a4,b4) as described above. Namely, in the repeater which has no through-channel , there may be further provided two drop/insert units corresponding to the two output channels CH3 and CH4 of the matrix switch 4 so that all of the channels are dropped and inserted. Each of the additional D/I units has the same constructions as the D/I unit 51 or 52 except for the previously stored channel number. A channel selecting signal SEL3(a3' ,b3' ) is the output of one of the additional D/I unit (not shown in Fig. 10 but may be connected to the output channel CH3 of the matrix switch 4) . A channel selecting signal SEL4(a4' ,b4' ) is the output of another one of the additional D/I unit (not shown in Fig. 10 but may be connected to the output CH4 of the matrix switch 4) . When the additional D/I units are plugged into the system, the detecting signal DT becomes the low level L. In contrast, when the additional D/I units are not plugged into the system, a detecting signal DT becomes the high level H. Whereby, when the above mentioned additional D/I units are not plugged into the system, the gate circuits 65 to 68 select the through-channel selecting signals SEL3 ( a3 ' ,b3 ' ) = (al,b2) and SEL4(a4' ,b4 f ) = (a2,bl) which are obtained by inverting the channel selecting signals (al,bl) and (a2,b2) by the NOT gates 61 to 64; whereas when the above mentioned additional D/I units are plugged into the system, the gate circuits 65 to 68 select the channel selecting signals SEL3(a3' ,b3' ) = (a3,b3) and SEL4(a4' ,b4' ) = (a4 b4 ) which are obtained directly from the additional D/I units or the demultiplexers. Fiure 11 is a circuit diagram showing a general purpose channel selecting circuit according to still another embodiment of the present invention. In the above-described embodiments, the through-channels in the intermediate repeater are fixed to be the channels CH3 and CH4. The through-channels, however, may alternatively be any of the channels CHI, CH2, CH3, and CH4. The channel selecting circuit in this case is as shown in Fig . 11. In Fig. II, the general purpose channel selecting circuit 6b includes NOT circuits 61A to 64A and 61B to 64B for inverting the signal codes of the channel selecting signals (al,bl), (a2,b2), (a3,b3), and (a4,b4) from the corresponding D/I units, gate circuits 65A to 68A and 65B to 68B each consisting of three NAND gates, and switching NOT gates 69 A-1, 69A-2, 69B-1, and 69B-2. There are three modes regarding whether or not the drop/insert units corresponding to the channels CHI to CH4 are plugged into the system. Namely, in the first mode, all of the drop /insert units are plugged in; in the second mode, only the drop/insert units corresponding to the output channels CHI and CH2 are plugged in and the drop/insert units corresponding to the output channels CH3 and CH4 are not plugged in; and in the third mode, only the drop/insert units corresponding to the output channels CH3 and CH4 are plugged in and the drop/insert units corresponding to the channels CHl and CH2 are not plugged in. In the first mode, the detecting signals DTA and DTB are both at the L level and therefore the outputs of the NOT circuits 69 A-1 and 69B-1 are at the H level, so that the gate circuits 65A to 68A select the signals al, bl, a2, and b2 as the channel selecting signals SELKal * ,bl' ) and SEL2(a2' ,b2' ) , and the gate circuits 65B to 68B select the signals a3,b3,a4 and b4 as the channel selecting signals SEL3(a3' ,b3' ) and SEL4(a4 ' ,b4 ' ) . As a result, the channel selecting signals SELl to SEL4 in this case are (al, bl), (a2,b2), (a3,b3), and (a4, b4) from the D/I units, respectively. In the second mode, the output of the NOT circuit 69A-1 and the output of the NOT circit 69A-2 are at the H level so that the gate circuits 65A to 6δA select the signals al, bl, a2, and b2 as the channel selecting signals SELKal ' ,bl ' ) and SEL2(a2 f ,b2' ) , and the gate circuits 65B to 68B select the signals al,b2,a2, and bl as the signals SEL3 ( a3 ' ,b3 ' ) and SEL4(a4 ' ,b4 ' ) , respectively. As a result, the channel selecting signals SELl to SEL4 in this case are (al, bl), (a2,b2), (al,b2), and (a2, bl), respectively. The above- mentioned first and second modes are the same as the previously described embodiment. In the third mode, the output of the NOT circuit 69A-2 and the output of the NOT circit 69B-1 are at the H level so that the gate circuits 65A to 6δA select the signals a3, b4, a4, and b3 as the channel - selecting signals SELKal ' ,bl ' ) and SEL2(a2' ,b2' ) , and the gate circuits 65B to 68B select the signals a3, b3,a4, and b4 as the channel selecting signals SEL3(a3' ,b3' ) and SEL4(a4' ,b4 ' ) , respectively. As a result, the channel selecting signals SELl to SEL4 in this case are (a3, b4), ( a4, b3), (a3, b3), and (a4, b4), respectively. The above-described embodiments of the channel selecting circuits shown in Figs. 10 and 11 can be applied not only to the intermediate repeater but also to the receiving line terminal equipment T' . Therefore, both the receiving line terminal equipment and the intermediate repeater can employ the same channel selecting circuit. Note, however, that, in the receiving line terminal equipment T', demultiplexers are used in place of the D/I units in the intermediate repeater R. The D/I units and the demultiplexers are common in ' their multiplexing function. Since the channel selecting circuit in the receiving line terminal equipment and in the intermediate repeater can be manufactured as the same circuit configuration with the same design specification, the cost for implementing an optical transmission system can be reduced in, for example, the design cost or in the manufacturing cost of the repeaters. Further, when the channel selecting circuits are made the same, the number of kinds of standby units of the repeaters can be reduced so that the management becomes easy. In the above-described embodiment with reference to Fig. 11, the through-channel may be any one of the output channels CHl to CH4. As a result, the insert/drop operation between the line terminal equipment and the intermediate repeater can be effected flexibl , providing a great advantage in decreasing the design cost, the manufacturing cost, managing cost, and the like. In the above described embodiments, after the drop/insert channels and the through-channels are determined, if one or more of the channels received by the intermediate repeater or by the receiving line terminal equipment enters a state of out of frame synchronization r - or in other words an out of frame, due to a fault in the transmitting repeater or the transmittig line, external noises and the like so that the intermediate repeater R or the receiving repeater T' receives an incorrect channel, the intermediate repeater R or the receiving line terminal equipment T' serches the desired channel from all of the input channels. To this end, the intermediate repeater R or the receiving line terminal equipment T* carries out a switching operation for all the channels. By the switching operation, however, the correctly selected channels such as through-cahnnels are also switched. As a result, even when a single input channel includes a fault, all of the channels in the whole system become isconnected. Therefore, the above-described embodiments still have a low system reliability. In the following, a still further embodiment of the present invention is described. An object of this embodiment of the present invention is to prevent the disconnected states of the all channels even when a single channel has a fault and to raise the system reliability. To attain this object, according to this embodiment, briefly, when a channel is not correctly received by an intermediate repeater or a receiving line terminal equipment, the channel is switched to another channel in the matrix switch, while the through- channels are fixed so as not to be switched . Figure 12 is a block diagram showing a D/I unit in an intermediate repeater according to this embodiment of the present invention. In the figure, the same parts as in the D/I unit 51 shown in Fig. 6 are denoted by the same reference symbols, and the parts corresponding to the parts shown in Fig. 6 are denoted by the same reference numbers with primes. Namely, 51' is a D/I unit according to this embodiment. 510 is a demultiplexer for demultiplexing the signals passing through the channel CHI output from the matrix switch 4 into a plurality of main signals. The demultiplexer 510 also detects an out of frame synchronization signal OOF and a 2-bit channel number in the channel CHI . 511 is an. out of frame protecting circuit for effecting a front and rear protection of the out of frame synchronization signal OOF detected by the demultiplexer 510, 512 is a comparing circuit for detecting whether or not the received channel number from the demultiplexer 510 coincides with the previously stored 2-bit channel selection number, and 513 is a non-coincidence signal protection circuit for effecting a front and rear protection of the signal , representing that the received channel number does not coincide with the previously set channel selection number, detected by the comparing circuit 512. 51d is an OR circuit for obtaining a logical sum of the output signal of the out of frame protection circuit 511 and the output signal cf the non-coincidence protecting circit 513 to be output as an out of frame synchronization signal OOF, and 515 is a reframe protection circuit for effecting a rear protection of the output signal from the OR circuit 51d and for outputting the out of frame synchronization signal OOF to the matrix switch 4' . 51e is a clock-signal oscillator. 51g is a frequency divider which is reset by the out of frame synchronization signal OOF from the OR circuit 51d. 518 Q is a counter for counting the maximum average reframining time MART multiplied by two after the reset and generates a 2-bit channel selecting signal . The 2- bit channel selecting signal applied to the counter 518 is output from the counter 518 after counting the MART 5 and is applied to a channel selecting circuit 6'. The demultiplexer 510 in Fig. 12 includes the frame synchronization detecting circuit 51a in the D/I unit 51 shown in Fig. 6. The constitution and the function of the comparing circuit 512 is the same as 0 those of the comparing circuit 51b shown in Fig. 6. The other D/I units 52', 53' and 54' have similar constitution as the D/I. unit 51'. When the D/I unit is inserted into the system, a detecting signal DTA of the L level is input to the 5 channel selecting circuit 6'. Figure 13 is a block diagram showing the detailed construction of the matrix switch 4' and the channel selecting circuit 6' in the intermediate repeater R. In the figure, 471 to 474 are switching 0 parts constituting the matrix switch 4* . The construction of the channel selecting circuit 6' is substantially the same as that shown in Fig. 11. Namely. 475 to 478 are channel selectors in the channel selecting circuit 6'. The channel selector 475 is 5 formed by the logic circuits 65A and 66A shovm in Fig. 11. Similarly, " the channel selectors 476 to 478 are formed by the logic circuits 67A and 68A, 65B and 66B, and 67B and 68B, respectively. To the channel selectors 475 to 478, the inverting circuits 61B to 64B and 61A to 64A are connected in the same way as in Fig. 11. The out of frame synchronization signal OOF from the reframe protection unit 515 in the D/I unit 51 'is applied to the switching parts 473 and 474 corresponding to the through-channels. Similarly, the signal OOF from the D/I unit 52' is also applied to the switching parts 473 and 474 corresponding to the through-channels. DT is a detection signal representing whether or not the corresponding D/I unit is mounted in the system. MAIN SIG is a main signal in the selected channel from the matrix switch 4'. Each of the switching parts 471 to 474 selects one of the four input channels input from the serial-parallel converter 3 and output it in accordance with the corresponding one of the selecting signals from the selecting parts 475 to 478. In addition, according to this embodiment of the present invention, when an out of frame synchronization signal OOF from the D/I unit 51' or 52' is received, the switching parts 473 and 474 corresponding to the through-channels fix their switching positions so as to continuously select the channels which are being selected, regardless of the channel selecting signals from the selecting parts 477 and 478. In the matrix switch 4' , the selection of the channel numbers of the through- channel at a normal state is carried out in the same way as in the before- described embodiment with reference to Fig. 11. Namely, in this case, no out of frame signal OOF is generated so that the switching parts 471 to 474 operate to select the channels in accordance with the channel selecting signals in the same way as described before. B contrast, when a out of frame synchronization signal OOF is generated from either one of the D/I units 51' and 52' due to some hard error or soft error, the channel selection in the switching parts 473 and 474 corresponding to the through-channels are inhibited to sequentially select the channels but their output channels are fixed to the channels being selected at the time the signal OOF is applied, while the other switching parts 471 and 472 which do not correspond to the through-channels continue to select the input channels until the signal OOF disappears. Assuming that a fault occurs in the multiplexer 11 ( see Fig. 5) in the the optical line terminal equipment T so that the channel CHl enters a fault state, and that the D/I unit 51* in the optical intermediate repeater R expects the channel CHl as a drop cr insert channel, as a result, the D/I unit 51' cannot receive the channel CHl in a normally synchronized state. Namely, the D/I unit 51' cannot detect the frame signal in the channel CHl or cannot detect the channel number of the channel CHl. In this situation, the D/I unit 51' outputs the out of frame synchronization signal OOF after a predetermined protection time formed by the OOF protection circuit 511. The signal OOF is applied to the switching parts 473 and 474 whereby the operations thereof are inhibited. Then the D/I unit 51' outputs a channel preselecting signal (al,bl) to the channel selecting circuit 6' so as to receive other channels for searching the desired channel CHl. In response to the channel preselecting signal, the matrix switch 4' switches the output channels. An operation of the device shown in Figs. 12 and 13 is described in more detail with reference to Figs. 14 and 15. Figure 14 is a diagram for explaining the output timing of the channel selecting signal and the out of frame synchronization signal OOF. In the figure, before a time tl, the channel CHl is in a normal state so that the OOF signal at the output of the demultiplexer 510 is at the low level L- When a fault occurs in the channel CHl at a time tl, an OOF signal is applied from the demultiplexer 510 to the OOF protection circuit 511. The OOF protection circuit 511 is provided because there is a possiblity that the OFF signal will disappear within a short time. If the OFF signal disappears within a short time and the normal state returns soon, the channel selection is not necessary. Therefore, to avoid the unnecessary selection of the channels, the OOF signal is output from the OOF protection circuit 511 at a time t2 after a predetermined front protection time pi from the time tl. Here, the front protection means the ensurance time of the beginning of the OOF signal. At the same time tl, the comparing circuit 512 also detects that the channel number in the received channel does not coincide with the previouly stored channel, number. The non- coincidence protection circuit 513 also performs the front protection of the non-coincidence signal. As a result, at a time t3 after a predetermined protection time p2, the non-coincidence protection circuit 513 outputs a high level signal indicating that the channel number in the received channel is uncertain. The period pi is selected to be shorter than the period p2 because the front protection of the non-coincidence usually requires a longer time. As a result, the OR circuit 51d outputs, at the time t2, the OOF signal which is then applied as a reset signal to the frequency divider 51e. The frequency divider 51e then counts to two times the MART by the use of the clock signal generator 51e. The output of the OR circuit 51e is also sent through the reframe protection circuit 515 to the matrix switch 4. The channel selecting signal is changed after the two times of the MART after the time t2. Here, the worst average reframing time MART is the average time from the time when the received signal anothers the out of frame synchronization state due to a bit error or external noises on a transmission line and the like during a normal state, to the time when a synchronized state is again recovered. Namely, the out of frame synchronization signal OOF from the OR circuit 51d drives the frequency divider 51g so that the frequency of the clock signal from the clock-signal oscillator 51e is divided- The divided frequency signal is sent to the counter 518- The counter 518 outputs a channel selecting signal (al,bl) to the channel selecting citcuit 6' after counting the worst average reframe time by the use of the input clock signals. In the matrix switch 4', the out of frame synchronization signal OOF is input to the switching parts 473 and 474, whereby the frames being selected by these switching parts 473 and 474 are fixed not to be switched. To the selecting parts 475 and 476, the channel selecting signals (al,bl) and (a2,b2) are input at a time t4 after the the MART has passed twice from the time t2 when the signal OOF is applied from the OR circuit 51d to the frequency divider 51g so as to change the channel selecting signals at the output of the selecting parts 475 and 476, whereby, the switching parts 471 and 472 select the other channels and send them to the D/I units 51' and 52 * . The switching parts 473 and 474 fix their outputs as the through-channels so that the channel selecting is not carried out. Next, an explanation of the operation of the optical intermediate repeater R is given for the case when the channel CHl is reframed or recovered from its fault state. Figure 15 is a time chart for explaining the reframe process from the out of frame state. In Fig. 15, when the channel CHl becomes normal at a time tl, the demultiplexer 510 detects the frame synchronization signal FR in the received channel CHl so as to output a frame detection signal which is the L level of the out of frame synchronization signal OOF to the- out of frame protection circuit 511 which then turns the signal OOF at its output at a time t2 after a predetermined rear protection time p3 has passed. Here, the rear protection time pi means the ensuring time of the fall of the signal OOF. Similary, at the time tl , the comparing circuit 512 detects a coincidence of the channel number of the channel CHl with the previoulsy stored channel number so as to drive the coincidence protection circuit 513 which then stops, at a time t3, to provide its output signal after a predetermined rear protection time p4 has passed. Therefore, the out of frame synchronization signal OOF output from the OR circuit 514 is turned off only after both of the out ut signals from the frame synchronization protection circuit 51 and the non- coincidence protection circuit 513 are turned off. In the case of Fig. 15, it is the time t3. Further, the reframe protection circuit 515 turns off the out of frame synchronization signal OOF output to the matrix switch 4' only after a predetermined reframe protection time p5 has further passed. The above-mentioned reframe protection time p5 is provided because the non-coincidence signal cannot correctly be obtained until the frame synchronization is stably established. Therefore, as shown in the lower portion in Fig. 15, the channel identification coincidence signal may be indefinite even after the frame synchronization protection time p3 has passed. This indefinite coincedence/non-coincidence signal may cause a disturbance of the operation of the matrix switch 4' . To avoid the disturbance, the reframe protection time p5 is further provided as shown in Fig. 15- Various modifications are possible in implementing the present invention. For example, the present invention is not restricted to the optical communication system as in the above-described embodiments but may be applied to other communication systems. Further, the present invention may be applied not only to an intermediate repeater but also to a receiving line terminal equipment. When the present invention is applied to a receiving line terminal equipment, demultiplexing units should be used in place of the D/I units in the intermediate repeater. Still further, the present invention may employ, as the multiplexing system, a frequency divided multiplexing system, a wave length- dividing multiplexing system, and the like. INDUSTRIAL APPLICABILITY As described in detail above, in the drop/insert cahnnel selecting system accorcing to the present invention, the channel selecting signal is expressed by a 2-bit signal (a,b) . When subsignals on two specific channels are to be dropped or to be inserted in an intermediate repeater, the channel selecting signals for selecting the channels to be dropped or to be inserted are assumed to be (al,bl) and (a2,b2), then the channel selecting signals for selecting the channels which are not to be dropped or inserted are calculated as (a2,bl) and (al,b2) . Accordingly, the conventional random logic circuit constructed by 20 to 30 ICs is net necessary, and through-channels can be selected by a small scale circuit with only 2 to 3 ICs . Further , according to the present invention, in a multiplexing transmission device, even when one line becomes faulty, all lines do not become faulty. Namely, as described above, since the channel selecting signals are switched after a sufficient protection time from the detection of the out of frame signal, and since the selecting parts corresponding to the through-chanels are fixed so as not to change the channels, the main signals passing through the through -channels are not cut even when a signal OOF is detected in the other channels.

Claims: CLAIMS 1. A drop/insert selecting system for dropping or inserting necessary signals from or into necessary channels comprising: s itching means (4,4' ) ha ing a plurality of input terminals for receiving a plurality of input channels and a plurality of output terminals, each cf said input channels conveying a frame synchronization signal and a channel number; at least one dro /insert means (51 ,52,51 ' ,52' ) , each operatively connected to one of said output terminals of said, switching means, for sequentially generating channel preselection signals until a frame synchronization is established, and for dropping or inserting necessary signals from or into a corresponding one of said necessary channels incorporated into said drop/insert means when a frame synchronization is established; and channel selecting means (6, 6a, 6b), operatively connected to said switching means and to said at least one drop/insert means, for generating a plurality of channel selecting signals in response to each of said channel preselection signals, each of said channel selecting signals functioning to connect each of said output terminals to one of said plurality of input terminals; the remaining output terminals of said switching means being connected to through-channels to which no drop/insert means is connected. 2. A drop/insert selecting system as claimed in claim 1, wherein: said plurality of input terminals comprise a first, a second, a third and a fourth input terminals; said plurality of output terminals comprise a first, a second, a third and a fourth output tεrminals; said at least one drop/insert means comprise a first and a second drop/insert units, operatively connected to said first and said second output terminals, respecti e ; and said through- channels comprises a first and a second through-channels, operatively connected to said third and said fourth output terminals, respectively. 3. A drop/insert selecting system as claimed in claim 2, wherein each of said drop/insert units comprises: frame synchronization detecting means (51a), operatively connected to a corresponding one of said output terminals, for detecting an out of frame synchronization in the channel output from said corresponding output terminal; comparing means (51b) , operatively connected to corresponding one of said output terminals, for detecting a non-coincidence between the channel number in the channel output from said corresponding output terminal and a previouly stored channel number indicating the channel from which cr into which signals are to be dropped or to be inserted; and preselecting signal generating means (51d,51e, 51f, 51g), operatively connected to said frame synchronization detecting means and said comparing means, for generating a two-bit preselecting signal (al, bl) or (a2,b2) for selecting one of said input terminals to be connected to the output terminal connected to the drop/insert unit under consideration, said two-bit preselecting signal being changed with a predetermined period until both of said out of frame and said non- coincidence signals disappear. 4. A dro /insert selecting system as claimed in claim 3, further comprising: an out of frame protection circuit (511), operatively connected to said frame synchronization detecting means (51a), for effecting a front and a reat protection, of the out of frame signal from said frame synchronization detecting means; a non-coincidence signal protection circuit (513), operatively connected to said comparig means (51b), for effecting a front and a rear protection of the non-coincidence signal from said comparing means; and a reframe protection circuit (515), operatively connected between the outputs of said out of frame protection circuit and said switching means, and between the output of said ncn-coincidence protection circuit and said switching means, for effecting a rear protection of the signal output from said out of frame protection circuit or said non-coincidence protection circuit. 5. A drop/insert selecting system as claimed in claim 3, wherein said preselecting signal generating means comprises: clock signal generating means (51e) for generating a clock signal; and frequency dividing means (51g) , operatively connected, to said clock signal, generating means, to said frame synchronization detecting means, and to said comparing means, for generating said two-bit preselecting signal in response to said clock signal until both of said out of frame signal and said non- coincidence signal disappear. 6. A drop/insert selecting system as claimed in claim 5, further comprising: counter means ( 518 ) , operatively connected to said frequency dividing means, for counting at least the maximum average reframing time from the detection of an out of frame state. 7. A drop/insert selecting system as claimed in claim 2, wherein said channel selecting means (6) comprises : two pair of lines, operatively connected to said first and said second drop/insert units, for directly passing said two channel preselection signals ( (al,bl) and (a2,b2) ) output from said first and said second drop/insert units, to said switching means, as a first and a second channel selecting signals (SELl and SEL2) for selecting one of said input terminals to be connected to said first output terminal and another one of said input terminals to be connected to said second output terminal, respectively; - a first NOT gate (61) for inverting the first bit (al) in said first channel preselection signal (al,bl) to output a first bit (a3 ! ) of a third channel selecting signal (SEL3) for selecting one of said input terminals to Jbe connected to said third output terminal; a second NOT gate (62) for inverting the second bit (bl) in said first channel preselection signal (al,bl) to output a second bit (b4 ! ) of a fourth channel selecting signal (SEL4) for selecting one of said input terminals to be connected to said fourth output terminal; a third NOT gate (63) for inverting the first bit Ca2) in said second channel preselection signal (a2,b2) to output a first bit (a4') of said fourth channel selecting signal (SEL4) for selecting one of said input terminals to be connected to said fourth output terminal; and a fourth NOT gate (64) for inverting the second bit (b2) in said second channel preselection signal (a2,b2) to output a second bit Cb3') of said third channel selecting signal (SEL3) for selecting one of said input terminals to be connected to said third output terminal. 8 . A drop/insert selecting system as claimed in c laim 7 , wherein each of said drop/ ins ert units comprises: frame synchronization detecting means (51a), operatively connected to a corresponding one of said output terminals, for detecting an out of frame synchronization in the channel output from said corresponding output terminal; comparing means (51b), operatively connected to a corresponding one of said output terminals, for detecting a non-coincidence between the channel number in the channel output from said corresponding output terminal and a previouly stored channel number indicating the channel from which or into said signals are to be dropped or to be inserted; and preselecting signal generating means (51d,51e, 51f, 51g), operatively connected to said frame synchronization detecting means and said comparing means, for generating a two-bit preselecting signal (al, bl ) or (a2,b2) for selecting one of said input terminals to be connected to the output terminal connected to the drop/insert unit under consideration, said two-bit preselecting signal being changed with a predetermined period until said out of frame or said non-coincidence signal disappers. 9. A drop/insert selecting system as claimed in claim 8, further comprising: an out of frame protection circuit (511), operatively connected to said frame synchronization detecting means (51a), for effecting a front and a reat protection on the out of frame signal from said frame synchronization detecting means; a non-coincidence signal protection circuit (513), operatively connected to said comparig means (51b), for effecting a front and a rear protection of the non-coincidence signal from said comparing means; and; a reframe protection circuit (515), operatively connected between the outputs of said out of fra e protection circuit and said switching means, and between the output of said non-coincidence protection circuit and said switching means, for effecting a front protection and a rear protection of the signal output from said out of frame protection circuit or said non- coincidence protection circuit. 10. A drop/insert selecting system as claimed in claim 8, wherein said preselecting signal generating means comprises: clock signal generating means (51e) for generating a clock ^ signal; and frequency dividing means (51g), operatively connected to said clock signal generating means, to said frame synchronization detecting means, and to said comparing means, for generating said two-bit preselecting signal in response to said clock signal, to said out of frame signal and to said non-coincidence signal. 11. A drop/insert selecting system as claimed in claim 10, further comprising: counter means ( 518 ),operatively connected to said frequency dividing means, for counting at least the maximum average reframing time from the detection of an out of frame state. 12. A drop/insert selecting system as claimed in claim 1, wherein: said plurality of input terminals comprise a first, a second, a third and a fourth input terminals; said plurality of output terminals comprise a first, a second, a third and a fourth output terminals; said at least one drop/insert means compris e a first , a second , a third , and a fourth drop/insert units , operativel y connected to said first, said second , said third , and said fourth output terminals , respectively; said third and said fourth drop/insert units being optionally plugged in said drop/insert system; and said third and said fourth drop/insert units providing detecting signals (DT) , indicating that said third and said fourth drop/insert units are plugged in, to said channel selecting means when plugged into said drop/insert system. 13. A drop/insert selecting system as claimed in claim 12, wherein said channel selecting means (6a) comprises: two pair of lines, operatively connected to said first and said second drop/insert units, for directly passing said two channel preselection signals ( (al,bl) and (a2,b2) ) , output from said first and said second drop/ insert units, to said switching means, as a first and a second channel selecting signals (SELl and SEL2) for selecting one of said input terminals to be connected to said first output terminal and one of said input terminals to be connected to said second output terminal , respectively; a first NOT gate (61) for inverting the first bit (al) in said first channel preselection signal (al,bl); a second NOT gate (62) for inverting the second bit (bl) in said first channel preselection signal (al,bl); a third NOT gate (63) for inverting the first bit (a2) in said second channel preselection signal (a2,b2); a fourth NOT gate (64) for inverting the second bit (b2) in said second channel preselection signal (a2,b2); a first gate circuit (65) having a first input connected to the output of said first NOT gate (61) and a second input connected to a first bit (a3) in said third channel preselection signal (a3,b3), for outputting, as a first bit (a3') in the third channel selecting signal (SEL3), either said first bit in said third channel preselection signal (a3,b3) or the output of said first NOT gate (64), depending on whether said third drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; a second gate circuit (66) having a first input connected to the output of said fourth NOT gate (64) and a second input connected to a second bit (b3) in said third channel preselection signal, for outputting, as a second bit (b3') in said third channel selecting signal (SEL3), either said second bit in said third channel preselection signal or the output of said fourth NOT gate (64), depending on whether said third drop/insert unit is plugged in cr is not plugged in said drop/insert system respectively; a third gate circuit (67) having a first input connected to the output of said third NOT gate (63) and a second input connected to a first bit (a4) in said fourth channel preselection signal (a4,b4), for outputting, as a first bit (a4' ) in said fourth channel selecting signal (SEL4), either said first bit in said fourth channel preselection signal or the output of said third NOT gate (63), depending on whether said fourth drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; and a fourth gate circuit (68) having a first input connected to the output of said second NOT gate (62) and a second input connected to a second bit (b4) in said fourth channel preselection signal (a4,b4) , for outputting, as a second bit (b4 ! ) in said fourth channel selection signal (SEL4) , either said second bit in said fourth channel preselection signal or the output of said second NOT gate (62), depending on whether said fourth drop/insert unit is plugged in cr is not plugged in said drop/insert system respectively; the outputs of said first and said second gate circuits (65,66) being a third channel selecting signal (SEL3) for selecting one of said input terminals of said switching means to be connected to said third output terminal of said switching means; the outputs of said third and said fourth gate circuits (67,68) being a fourth channel selecting signal (SEL4) for selecting one of said input terminals of said switching means to be connected to said fourth output terminal of said switching means . 14. A drop/insert selecting system as claimed in claim 13, wherein each cf said dro /insert units comprises : frame synchronization detecting means (51a), operatively connected to a corresponding one of said output terminals, for detecting an out of frame synchronization in the channel output from said corresponding output terminal; comparing means (51b), operatively connected to a corresponding one of said output terminals, for detecting a non-coincidence between the channel number in the channel output from said corresponding output terminal and a previouly stored channel number indicating the channel from which or into which signals are to be dropped or to be inserted; and preselecting signal generating means (51d,51e, 51f, 51g), operatively connected to said frame synchronization detecting means and said comparing means, for generating a two-bit preselecting signal (al, bl) or (a2,b2) for selecting one of said input terminals to be connected to the output terminal connected to the drop/insert unit under consideration, said two-bit preselecting signal being changed with a predetermined period until both cf said out of frame and said non-coincidence signals disappear. 15. A drop/insert selecting system as claimed in claim 14, further comprising: an out of frame protection circuit (511), operatively connected to said frame synchronization detecting means (51a), for effecting a front and a reat protection on the out of frame signal from said frame synchronization detecting means; a non-coincidence signal protection circuit (513), operatively connected to said comparig means (51b), for effecting a front and a rear protection of the non-coincidence signal from said comparing means ; and a reframe protection circuit (515), operatively connected, between the outputs of said out of frame protection circuit and said switching means, and between the output of said non-coincidence protection circuit and said switching means, for effecting a front protection and a rear protection of the signal output from said out of frame protection circuit or said non- coincidence protection circuit. 16. A drop/insert selecting system as claimed in claim 14, wherein said preselecting signal generating means comprises: clock signal generating means (51e) for generating a clock signal; and frequency dividing means (51g), operatively connected to said clock signal generating means, to said frame synchronization detecting means, and to said comparing means, for generating said two-bit preselecting signal in response to said clock signal until both of said out of frame signal and said non- coincidence signal disappear. 17. A drop/insert selecting system as claimed in claim 16, further comprising: counter means ( 518 ), operatively connected to said frequency dividing means, for counting at least the maximum average reframing time from the detection of an out of frame state. 18. A drop/insert selecting system as claimed in claim 1, wherein: said plurality of input terminals comprise a first, a second, a third and a fourth input terminals; said plurality of output terminals comprise a first, a second, a third and a fourth output terminals; said at least one drop/insert means comprise a first, a second, a third, and a fourth drop/insert units, optionally plugged in said drop/insert system, and operatively connected to said first, said second, said third, and said fourth output terminals, respectively when plugged into said drop/insert unit; said first, said second, said third and said fourth drop/insert units providing detecting signals to said channel selecting means when plugged into said drop /insert system. 19. A drop/insert selecting system as claimed in claim 18, wherein each of said drop/insert units comprises: frame synchronization detecting means (51a), operatively connected to corresponding one of said output terminals, for detecting an out of frame synchronization in the channel output from said corresponding output terminal; comparing means (51b) , operatively connected to corresponding one of said output terminals, for detecting a non-coincidence between the channel number in the channel output from said corresponding output terminal and a previouly stored channel number indicating the channel from which or into which signals are to be dropped or to be inserted; and preselecting signal generating means ' (51d, 51e, 51f, 51g), operatively connected to said frame synchronization detecting means and said comparing means, for generating a two-bit preselecting signal (al,bl) or (a2,b2) for selecting one of said input terminals to be connected to the output terminal connected to the drop/ insert unit under consideration, said two-bit preselecting signal being changed with a predetermined period until both of said out of frame and said non-coincidence signal disapper. 20 . A drop/insert selecting system as claimed in claim 19, further comprising: an out of frame protection circuit (511) , operatively connected to said frame synchronization detecting means ( 51a) , for effecting a front and a reat protection on the out of frame signa l from said frame synchronization detecting means; a non-coincidence signal protection circuit ( 513) , operatively connected to said comparig means (51b) , for effecting a front and a rear protection of the non-coincidence signal from said comparing means; and a reframe protection circuit ( 515 ) , operatively connected between the outputs of said out cf frame protection circuit and said switching means , and between the output of said non-coincidence protection circuit and said switching means, for effecting a front protection and a rear protection of the signal output from said out of frame protection circuit or said non- coincidence protection circuit . 21. A drop/insert selecting system as claimed in claim 19 , wherein said preselecting signal generating means comprises : clock signal generating means (51e) for generating a clock signal; and frequency divid ing means ( 51g ) , operatively connected to said clock signal generating means , to said frame synchronization detecting means, and to said comparing means, for generating said two-bit preselecting signal in response to said clock signal unti l both of said out cf frame signal and said non- coincidence signal disappear . 22. A drop/insert selecting system as claimed in claim 21, further comprising: counter means ( 518), operatively connected to said frequency dividing means, for counting at least the maximum average reframing time from the detection of an out of frame state. 23. A drop/insert selecting system as claimed in claim 18, wherein said channel, selecting means (6b) comprises: a first NOT gate (61A) for inverting the first bit (al ) in said first channel preselection signal (al,bl); a second NOT gate (62A) for inverting the second bit (bl) in said first channel preselection signal (al,bl); a third NOT gate (63A) for inverting the first bit (a2) in said second channel preselection signal (a2,b2); a fourth NOT gate (64A) for inverting the second bit (b2) in said second channel preselection signal (a2,b2); a fifth NOT gate (61B) for inverting the first bit (a3) in said third channel preselection signal (a3,b3); a sixth NOT gate (62B) for inverting the second bit (b3) in said third channel preselection signal (a3,b3); a seventh NOT gate (63B) for inverting the first bit (a4) in said fourth channel preselection signal (a4,b4); an eighth NOT gate (64B) for inverting the second bit (b4) in said fourth channel preselection signal (a4,b4); a first gate circuit (65B) having a first input connected to the output of said first NOT gate (61A) and a second input connected to a first bit (a3 ) in said third channel preselection signal, for cutputting, as a first bit (a3 ! ) in said third channel selection signals (SEL3), either said first bit (a3) in said third channel preselection signal or the output of said first NOT gate (64A), depending on whether said third drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; a second gate circuit (66B) having a first input connected to the output of said fourth NOT gate (64A) and a second input connected to a second bit (b3) in said third channel preselection signal, for outputting, as a second bit (b3') in said third channel selection signal (SEL3) , either said second bit in said third channel preselection signal or the output of said fourth NOT gate (64A), depending on whether said third drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; a third gate circuit (67B) having a first input connected to the output of said third NOT gate (63A) and a second input connected to a first bit (a4) in said fourth channel preselection signal, for outputting, as a first bit (a4') in said fourth channel selection signal (SEL4), either said first bit in said fourth channel preselection signal or the output of said third NOT gate (63A), depending on whether said fourth drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; a fourth gate circuit (68B) having a first input connected to the output of said second NOT gate (62A) and a second input connected to a second bit (b4) in said fourth channel preselection signal, for outputting, as a second bit Cb4') in said fourth channel selection signal (SEL4) , either said second bit in said fourth channel preselection signal cr the output of said second NOT gate (62A) , depending on whether said fourth drop/insert unit is plugged in or is net plugged in said drop/insert system respectively; a fifth gate circuit (65A) having a first input connected to the output of said fifth NOT gate (61B) and a second input connected to a first bit (al) in said first channel preselection signal, for outputting, as a first bit (al') in said first channel selection signal (SELl), either said first bit (al) in said first channel preselection signal or the output of said, fifth NOT gate (61B), depending on whether said first drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; a sixth gate circuit (66A) having a first input connected to the output of said sixth NOT gate (64B) and a second input connected to a second bit (bl) in said first channel preselection signal, for outputting, as a second bit (bl') in said first channel selection signal. (SELl), either said second bit in said first channel preselection signal or the output of said sixth NOT gate (64B), depending on whether said second drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; a seventh gate circuit (67A) having a first input connected to the output of said seventh NOT gate (63B) and a second input connected to a first bit (a2) in said second channel preselection signal, for outputting, as a first bit (a2') in said second channel selection signal (SEL2), either said first bit in said second channel preselection signal or the output of said seventh NOT gate (63B), depending on whether said third drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; an eighth gate circuit (68A) having a first input connected to the output of said sixth NOT gate (62B) and a second input connected to a second bit (b2) in said second channel preselection signal, for outputting, as a second bit (b2' ) in said second channel selection signal (SEL2) , either said second bit in said second channel preselection signal or the output of said sixth NOT gate (62B), depending on whether said fcurth drop/insert unit is plugged in or is not plugged in said drop/insert system respectively; the outputs of said fifth and said sixth gate circuits (65A and 66A) being said first channel selecting signal (SELl) for selecting one of said input terminals of said switching means to be connected to said first output terminal of said switching means; the outputs of said seventh and said eighth gate circuits (67A and 68A) being said second channel selecting signal (SEL2) for selecting one of said input terminals of said switching means to be connected to said second output terminal of said switching means; the outputs of said first and said second gate circuits (65B and 66B) being said third channel selecting signal (SEL3) for selecting one of said input terminals of said switching means to be connected to said third output terminal of said switching means; the outputs of said third and said fourth gate circuits (67B and 68B) being a fourth channel selecting signal (SEL4) for selecting one of said input terminals of said switching means to be connected to said fourth output terminal of said switching means. 24. A drop/insert selecting system as claimed in claim 2, wherein: said switching means (4') comprises a first, a second, a third, and a fourth switching parts (471,472,473, and 474) arranged to correspond to said first drop/insert unit, said second drop/insert unit, said first through-channel, and said second through- channel , respectively; each of said switching parts having said plurality of input terminals and one of said output terminals connected to the corresponding one of said first drop/insert unit, said second drop/insert unit. said first through-channel , and said second through- channel; said third switching part ( 473) and said fourth switching part ( 474) having means to fix, when said first or said second drop/insert unit is in an out cf f rame , thei r switching pos iti ons as the through channels . 25- A drop/insert selecting system as claimed in claim 24, wherein: said third drop/insert unit and said fourth drop/insert unit being unplugged; said switching means (4') comprises a first, a second, a third, and a fourth switching parts (471,472,473, and 474 ) arranged to correspond to said first drop/insert unit, said second drop/insert unit, said first through-channel, and said second through- channel , respectively; each of said switching parts having said plurality of input terminals and one of said output terminals connected to the corresponding one of said first drop/insert unit, said second drop/insert unit, said first through-channel, and said second through- channel; said third switching part (473) and said fourth switching part (474) having means to fix, when said first or said second drop/insert unit is in an out of frame, their switching positions as the through channels.

Inventors: ARAI MASANORI, FUJIMOTO NAONOBU, MORI MASAKAZU, TAKATSU KAZUO, YAMAGUCHI NOBUHIDE, ARAI, MASANORI, FUJIMOTO, NAONOBU, MORI, MASAKAZU, TAKATSU, KAZUO, YAMAGUCHI, NOBUHIDE
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H04J3
IPC codes: H04J3