NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF PRODUCING THE SAME

Abstract: A nonvolatile semiconductor memory having nonvolatile memory cells that electrically erase and write data. Each memory cell has a floating gate and a control gate formed on the channel region on the surface of a semiconductor substrate. The floating gate covers only part of the channel region. In the memory cell, therefore, a floating gate transistor and an enhancement transistor are connected in parallel. The floating gate transistor is deviated toward one side in the direction of width of the channel region or covers only the central portion of the channel region in the direction of width. Further, a plurality of memory cells are connected in series to constitute a basic block. The neighboring basic blocks are separated by the enhancement MOS transistor. In this memory, the memory cell (floating gate) and the enhancement MOS transistor (gate) are formed using the same mask in a self-aligned manner. In this memory, furthermore, the control gate and the floating gate are formed using the same mask in the self-aligned manner.

Description: The present invention relates to a non-volatile semiconductor memory according to the preamble of claim 1, which is known from JP-A-58 190 069, and to a method of manufacturing and operating the same. A ROM, the storage contents of memory cells of which can be electrically erased and changed, is known as an EEPROM (electrically erasable programmable ROM). When compared with an EPROM, EEPROM can be used more easily since data are erased with electric signals while being mounted on a circuit board, so that demand for use with various control circuits, memory cards or the like are rapidly increasing. A large scale EEPROM in particular which is used when changing date in a floppy disk has been recently desired. Figs. 1A to 1C show the structure of the memory array of a conventional NAND type EEPROM suitable for large scale integration. Fig. 1A is a plane view of the pattern, Fig. 1B is a cross section along line A-A′ of Fig. 1A, and Fig. 1C is a cross section along line B-B′ of Fig. 1A. Referring to Fig. 1A, a portion enclosed by a broken line and indicated at 10 represents one NAND basis block. As understood from Fig. 1B, this NAND basic block 10 is partitioned from other NAND basic blocks disposed in the right/left direction as viewed in Fig. 1B by field oxide films 12, 12, ... The vertical cross section of the NAND basic block 10 is as shown in Fig. 1C. Specifically, referring to Fig. 1C in particular, reference numeral 11 represents a p-type silicon semiconductor substrate, 13 a common source region made of an n⁺ diffusion layer and shared by respective basic blocks 10, 14 a drain region of the NAND basic block 10 which region is also made of an n⁺ diffusion layer, 15, 15, ... source/drain regions of memory cells within the NAND basic block 10 which regions are made of n⁺ diffusion layers, 16, 16, ... floating gates made of a first polysilicon layer, 17, 17, ... control gates made of a second polysilicon layer, 18 a first select gate constructed by electrically connecting together the first and second polysilicon layers, 19 a second select gate constructed by electrically connecting together the first and second polysilicon layers, 20 a data line, 21 a contact connecting the drain region 14 and the data line 20, 22 a gate oxide film formed between the floating gate 16 and the substrate 11 and having a thickness of, e.g., about 100 Å (10nm), 23 a gate insulating film formed between the floating gate 16 and the control gate 17 for which the film has a thickness of about 300 Å (30nm) and three-layered structure of, e.g., ONO (oxide-nitride-oxide), 24 an insulating oxide film, and 25 and 26 gate oxide films formed between the substrate 11 and the first and second select gates 18 and 19, respectively, and having a thickness of, e.g., about 400 Å (40nm). This gate oxide film 25 may be of the ONO three-layered structure which is formed at the time of forming the gate oxide film 23. In this case, the select gate transistors 18 and 19 are made of only the second polysilicon layer without using the first polysilicon layer. As seen from Fig. 1C in particular, each NAND basic block 10 is formed with ten transistors (memory cells and select gate transistors) 31 to 40 which will be described later in detail. The transistors 31 to 40 are turned on and off by means of gates 17 to 19 of respective channels. The on/off of the transistors 32 to 39, however, is controlled in dependence upon whether each floating gate 16 has electrons or holes. Each floating gate 16 stores "1" or "0" in dependence on whether it has electrons or holes. The number of control gates 17, 17, ... provided for each NAND basic block 10 is, for example, eight. Each control gate is formed continuously to cover a plurality of floating gates 16, 16, ... positioned under the control gate. Namely, as seen from Figs. 1A and 1B in particular, the width (width in the up/down direction as viewed in Fig. 1A) of each floating gate 16, 16, ... is the same as that of each control gate 17, 17, ..., and the length (length in the right/left direction as viewed in Fig. 1A) of each floating gate 16, 16, ... is formed shorter than the width of each NAND basic block. The memory cell array is constructed by disposing the NAND basic blocks 10 in matrix in the up/down right/left directions as viewed in Fig. 1A. The equivalent circuit of the NAND basic block 10 is shown in Fig. 2. In Fig. 2, two NAND basic blocks 10 and 10 disposed right and left are shown. As seen from Fig. 2, the equivalent circuit of each NAND basic block 10 is constructed such that between the source 13 and the data line 20 (DL1, DL2), the select gate transistor 31, eight memory cells 32 to 39, and select gate transistor 40 are serially connected. The transistors 31 and 40 are inputted with select gate signals SG1 and SG2, respectively, and word lines WL1 to WL8 are connected to the control gates 17 of the memory cells 32 to 39. The data erase/write operation of eight memory cells 32 to 39 each made of a floating gate transistor will be described hereinbelow. As understood from Fig. 3A, data are erased by applying a high voltage, e.g., 15 V to the control gate 17 and connecting the source 15 and drain 15 to a 0 V ground potential. By applying a high voltage to the control gate 17, the control gate 17 and the floating gate 16 are electrostatically coupled so that the potential of the floating gate 16 rises and electrons are injected from the source 15 or drain 15 into the floating gate 16 via the gate oxide film 22. This is called an erase state, and the stored data at this state is defined as a "1" level. The threshold voltage of the memory cell at this state becomes about 2 to 3 V as shown in the characteristic curves of Fig. 4. As understood from Fig. 3B, data are written by setting the control gate 17 at 0 V, making the source 15 in an open state, and applying a high voltage to the drain 15. In this case, electrons are emitted to the drain 15 from the floating gate 16, and the threshold voltage of the memory cell becomes about -5 V as shown in the characteristic curves of Fig. 4. The stored data at this state are defined as a "0" level. The operation of the NAND basic block 10 show in Figs. 2 and 1A will be described with reference to Table 1. Data are erased by setting the data line DL1, DL2 to 0 V, SG1 to 5 V, SG2 to 15 V, and word lines WL1 to WL8 to 15 V. In this state, all the drains and sources of the memory cells 32 to 39 become 0 V so that all the data in the memory cells 32 to 39 are erased collectively. Data are written sequentially and selectively starting from the memory cell 32 (cell 1) nearest to the select gate transistor 31. First, in order to write data in the cell 32, SG1 is set to 0 V, data line DL1 to 20 V, DL2 to 10 V, and SG2 to 20 V. Next, word line WL1 is set to 0 V, and all the other word lines WL2 to WL8 to 20 V so that the memory cell 32 is selected and data are written therein. The threshold voltage of the memory cell whose data have been erased is about 3 V, whereas that of the memory cells 33 to 39 (cell 2 to cell 8) with a high voltage being applied in a write state is about 5 V while taking the substrate effect into consideration. As a result, the drain of the memory cell 32 is applied with (gate voltage of the memory cell 33) - (threshold voltage of the erased memory cell) = (20 V - 5 V) = 15 V, so that electrons are emitted from the floating gate to the drain via the gate oxide film (indicated at 22 in Fig. 1B) having a thickness of 100 Å (10 nm), in other words, data are written in the memory cell 32. In writing data in the next memory cell 33, word lines WL1 and WL2 are set to 0 V, and all the other word lines WL3 to WL8 are set to 20 V. In a similar manner, data writing is sequentially performed up to the memory cell 39 with voltages being set as shown in Table 1. If data are not written in a selected memory cell, i.e., if the "1" level data are remained unchanged, data line DL1 is applied with 0 V or 10 V instead of 20 V. In this case, a voltage is not applied between the floating gate and the drain, or an applied voltage is small, so that data are not written. As described above, data writing is sequentially performed for eight memory cells starting from the memory cell 32 on the source side. The reason for this is that if data are written into a cell without using this data writing order, a high voltage (20 V) is applied to the word lines of the other cells already written, and 0 V is applied to the drain, to thereby produce an erase state and erase the data in the other cells. By using the above-described data writing order, it is possible to prevent the written data from being erased. Furthermore, while a data erase/write operation is carried out for the block 10 on the data line DL1 side, the other data line DL2 is applied with about 10 V which is an intermediate voltage between the write and erase operations. This is carried out for preventing erroneous data erase/write relative to the memory cells connected to the data line DL2. Furthermore, while one NAND basic block is selected and data are written, in the other NAND basic blocks connected to the block vertically (in the up/down direction as viewed in Fig. 1A), SG2 is set to 0V and the word lines WL1 to WL8 are set to 0 V so as to prevent erroneous data erase/write. The data read operation from the NAND basic block is carried out in the following manner. For example, in Fig. 2, consider the case wherein data are read by selecting the memory cell 32 in the NAND basic block connected to the data lines DL1. In this case, as shown in Table 1, DL1 is set to 1 V, SG1 and SG2 to 5 V, the selected word line WL1 to 0 V, and the other word lines WL2 to WL8 to 5 V. The non-selected data line DL2 becomes a floating state, and takes approximately 0 V. If the stored data in the selected memory cell 32 are of the "1" level (threshold voltage of +3 V), the control gate voltage is 0 V so that it takes an off-state. As a result, in the selected NAND basic block 10, current will not flow between the data line DL1 and the ground potential so that the "1" level data are sensed with a sense amplifier (not shown) connected to the data line DL1. On the other hand, if the stored data in the selected memory cell 32 is of "0" level (threshold voltage of -5 V), the memory cell 32 takes an on-state even if the control gate voltage is 0 V. In this case, the control gate voltages of the other memory cells 33 to 39 are 5 V and these memory cells 33 to 39 take an on-state irrespective of the stored data. Therefore, in this basic block, current flows between the data line DL1 and the ground potential so that the "0" level data are sensed with the sense amplifier. In a conventional memory having NAND basic blocks described above, memory cells can be disposed at the pitch of the word lines (control gates 17), and only a single contact 21 is used for a plurality (e.g., eight) of memory cells, allowing a larger number of memory cells per unit area and providing a structure suitable for miniaturizing a large capacity memory. Such a conventional memory, however, has the following problems. A first problem is as follows. Since a NAND basic block has a NAND type cell structure with a plurality of memory cells connected in series, it is necessary for reading data from a selected memory cell to turn on other non-selected and erased memory cells. It becomes necessary to therefore turn them on by using a 5 V gate voltage and to maintain the threshold voltage smaller than or equal to about 3 V (at least smaller than or equal to 5 V). Similarly, it is also necessary to maintain the threshold voltage of the selected and erased memory cell larger than or equal to about 1 V (at least larger than or equal to 0 V). It is difficult however, to uniformly erase all memory cells of a large capacity memory of large scale such as 1 M bits or 4 M bits as variation will necessarily occur. If such variation causes the threshold voltage of even one erased memory cell to move out of the range from 0 V to 3 V, then the memory becomes a defective one. It is very difficult to design and manufacture a memory capable of uniformly and reliably erase the data of all memory cells. Apart from the above, in order to speed up the data read speed, it is necessary to make a larger current flow in a NAND basic block which includes a memory cell storing "0" level data. Also in this case, if the threshold voltage of a non-selected memory cell whose gate is applied with 5 V, is 3 V, it is not possible to make an on-current sufficiently large. For instance, in a NAND basic block designed on the basis of a 1 µm rule, a cell current only in the order of several µA flows during data reading, which is not suitable from the standpoint of increased speed A second problem of such a conventional memory is the necessity of high voltage withstanding. During data writing into the memory cell 32 for example, the threshold voltage of the memory cells 33 to 39 is about 5 V so that a high voltage of 20 V becomes necessary to efficiently write data in the memory cell 32. For this reason, a sufficiently high voltage withstand is required for peripheral circuits, while posing another problem of lowering the reliability due to voltage stress applied to memory cells. The JP-A-62 54962 discloses a transistor comprising one conductive type semiconductor substrate, a source region and a drain region having a conductive type reversed to said semiconductor substrate provided on said semiconductor substrate, a gate insulating film provided on a channel region between said source region and said drain region, a floating gate electrode which extends over and between said source region and said drain region and which is provided so as to cover a part of said gate insulating film, and a control gate electrode provided on said floating gate electrode and said channel region not covered with said floating gate electrode through an insulating film, wherein said floating gate electrode is provided so that a threshold voltage of said channel region not covered with said floating gate electrode and having no memory function is higher than a threshold voltage after writing a low level of said channel region covered with said floating gate electrode and having a memory function but lower than a threshold voltage after writing a high level. Since the channel region having a memory function is connected in parallel with the channel region of the threshold voltage of approximately 1 V having no memory function, the threshold voltage after writing in the whole transistor does not exceed 1 V irrespective of the amount of electrons injected into the floating gate electrode. That is, the threshold voltage after writing is determined by the control of the threshold voltage of the channel region having no memory function under the control gate electrode instead of the amount of electrons injected into the floating gate electrode. However, the transistor structure disclosed in the JP-A-62 549 62 may be affected by mask alignment if used in a plurality of basic blocks of a non-volatile semiconductor each having a plurality of those transistors connected in series. The JP-A-58 190069 discloses a non-volatile memory device comprising a semiconductor substrate, drain and source regions formed at required intervals on said semiconductor substrate, a floating gate on the region sandwiched between said drain and ssource regions, at least one side thereof being formed within the width of each region through an insulating layer so as to extend over the regions, and a control gate, or said floating gate, formed through a insulating layer so as to extend over the regions in the region sandwiched between said drain and source regions, wherein a thickness of an insulating corresponding portion between the control gate and the substrate at a portion where only the control gate is present is made larger than a thickness of an insulating layer corresponding portion between the floating gate and the substrate at a portion where said control gate and said floating gate are present. Accordingly, although the width of the floating gate is maller than that between source and drain, the presence of the transistor between source and drain where no floating gate is present, need not to be taken into account at the time of readout, whereas at the time of writing all transistors between source and drain are turned on. SUMMARY OF THE INVENTION It is an object of the present application to provide a non-volatile semiconductor memory which has a high operation speed, can collectively and uniformly erase all memory cells reliably, allows the use of a low-voltage during data-writing, and is insensitive to all small displacement in mask alignment during the manufacturing process, and a corresponding manufacturing method. This object is achieved by a memory of the initially defined type having the characterizing features of claim 1, and by a method of claim 10. Preferred embodiments are listed in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a plan view showing a pattern according to the background art; Fig. 1B is a cross-section along line A-A′ of Fig. 1A; Fig. 1C is a cross-section along line B-B′ of Fig. 1A; Fig. 2 is an equivalent circuit for Fig. 1A; Figs. 3A and 3B are views illustrating the erase/write operation of a floating gate transistor; Fig. 4 shows the characteristic curves of the threshold voltage of a floating gate transistor in an erase state and in a write state; Fig. 5A is a plan view of a pattern showing a first embodiment leading to the present invention; Fig. 5B is a cross section along line A-A′ of Fig. 5A; Fig. 6 is an equivalent circuit for Fig. 5A; Fig. 7 shows the characteristic curves of the threshold voltage for Fig. 5A; Fig. 8 is a plan view showing a second embodiment leading to the present invention; Fig. 9 is an equivalent circuit for Fig. 8; Fig. 10A is a plan view of a pattern showing a third embodiment leading to the present invention; Fig. 10B is a cross section along line A-A′ of Fig. 10A; Fig. 11 is an equivalent circuit for Fig. 10A; Fig. 12A is a plan view of a pattern showing a fourth embodiment according to the present invention; Fig. 12B is a cross section along line A-A′ of Fig. 15A; Fig. 13A is a plan view of a pattern showing a fifth embodiment according to the present invention; Fig. 14A is a plan view of a pattern showing an sixth embodiment according to the present invention; Fig. 13B and 14B are cross sections along line A-A′ respectively of Figs. 13A and 14B; Figs. 15 and 16 are cross sections showing a seventh embodiment; Figs. 17A to 17D and Figs. 18A to 18D are cross sections showing manufacturing steps of the seventh embodiment; Fig. 19 is a plan view of a pattern showing a eighth embodiment; Fig. 20 is a cross section along line a-a′ of Fig. 19; Fig. 21 is a cross section along line b-b′ of Fig. 19; Figs. 22A to 22G are cross sections showing manufacturing steps of a first manufacturing method of the eighth embodiment; and Figs. 23A to 28C are cross sections showing manufacturing steps of a second manufacturing method of the eighth embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figs. 5A and 5B show the memory array of a NAND type EEPROM leading to the present invention, wherein Fig. 5A is a plan view of the pattern, and Fig. 5B is a cross section along line A-A′ of Fig. 5A. In Figs. 5A and 5B, similar constitutional elements to those shown in Figs. 1A to 5B are represented by using identical reference numerals shown in Figs. 1A to 1C. The device shown in Figs. 5A and 5B is applied with the same voltages shown in Table 1 (although a write voltage value is small and an erase voltage value is large) to perform erase, write and read operations. The different point of the embodiment shown in Figs. 5A and 5B from the memory cell shown in Figs. 1A to 1C is that, as understood from Fig. 5A in particular, each floating gate 16 is displaced left in the extending direction of a control gate 17. With such displacement arrangement, each floating gate 16 covers not all the area of each memory cell (32 to 39) but a partial area thereof. Consider the channel region of a memory cell (39) for example. At the partial area of the channel region, the floating gate 16 overlaps the control gate 17 to form a floating gate transistor (39a), whereas at the remaining area, only the control gate 17 is present to fcrm an enhancement type transistor (39b). Each memory cell is therefore constructed of a parallel connection of the above-described two types of transistors. The equivalent circuit of each NAND basic block 10 shown in Fig. 5A is therefore represented as shown in Fig. 6. Next, the operation of eight memory cells 32 to 39 each constructed of a parallel connection of the floating gate transistor and enhancement type transistor as shown in Fig. 6, will be described with reference to the characteristic curves shown in Fig. 7. The curve (b) shown in Fig. 7 indicates the characteristic of a memory cell in an erase state. In the erase state, the threshold voltage of a floating transistor, e.g., transistor 32a shown in Fig. 6, is as high as about 5 V as shown by the curve (a) in Fig. 7. However, the threshold voltage of the enhancement type transistor 32b connected in parallel with the transistor 32a is 1 V as seen from the curve (b). As a result, the characteristic of the enhancement type transistor 32b becomes dominant as the characteristic of the memory cell 32, thus presenting the threshold voltage of 1 V. Similarly, as the characteristics of the other memory cells 33 to 39, the enhancement type transistors 33b to 39b become dominant. The curve (c) shown in Fig. 7 represents the characteristic of a memory cell in a write state. In this case the threshold voltage becomes about -5 V. Namely, although the threshold voltage of an enhancement type transistor (e.g., 32b) in the write state remains 1 V which is the same as the case of the erase state, the threshold voltage of a floating gate transistor (e.g., 32a) becomes about -5 V. As a result, the characteristic of a floating gate transistor becomes dominant as the characteristic of the memory cell, thereby presenting the threshold voltage of about -5 V. In a memory cell constructed of a parallel connection of such two transistors, the threshold voltage in the erase state is determined by the enhancement type transistor. It is easy to design and manufacture enhancement type transistors having a threshold voltage of 1 V. In addition, the threshold voltage of floating gate transistors may take any value larger than or equal to 1 V (at least larger than or equal to 0 V), so that if data are erased sufficiently while considering threshold voltage variation, a large cell current can flow to thereby realize a stable characteristic. The erase, write and read operations of the NAND basic block is the same as that described with Table 1. It is necessary for a conventional memory to set the threshold voltage within the range from 1 V to 3 V in the erase state. Therefore, too high a voltage cannot be applied to the word line. For this reason, a relatively low voltage 15 V is applied to slowly erase data and carefully move to a desired threshold voltage. In contrast, in the memory of this embodiment, the threshold voltage in the erase state is determined by the enhancement type transistor so that it is not necessary to consider to what degree the threshold voltage of the floating gate transistor moves in the erase state. A voltage higher than conventional, e.g. in the order of 17 V can therefore be applied to the word line to sufficiently erase data. Furthermore, in writing data in a conventional memory, the threshold voltage of an erased memory cell rises to about 5 V so that it is necessary to apply a high voltage 20 V to the control gate of a non-selected memory cell in order to apply 15 V to the drain of a selected memory cell. In contrast, in the case of this embodiment, the threshold voltage in the erase state is as low as 1 V, or about 2 V if the substrate effect is considered, so that a voltage about 17 V lower than conventionally applied, can be applied to the control gate of a non-selected memory cell in order to obtain a voltage 15 V as conventionally obtained at the drain of a selected memory cell. Fig. 8 is a plan view of the pattern showing the second embodiment of the memory array leading to the present invention. The size, in the lateral direction in Fig. 1C, of each memory cell according to the related background art is determined by the pitch between floating gates. In the case of the embodiment memory shown in Fig. 5A, the size is determined by the pitch between drain regions 14 formed with the contact 21. The size in the lateral direction of the embodiment memory shown in Fig. 5A becomes smaller than that of the memory shown in Fig. 1C according to the related background art. However, the size of the memory shown in Fig. 5A is determined by the contact 21 so that it is not possible to make the size sufficiently small. In view of this, the embodiment shown in Fig. 8 aims at making the size in the lateral direction smaller. Specifically, instead of the select gate 19 shown in Fig. 5A, two select gates 26 and 27 are provided as shown in Fig. 8. The right and left, two NAND basic blocks are connected in common to a single data line (not shown) via a single contact 21. In the two NAND basic blocks, the region 28a of the select gate 26 and the region 28b of the select gate 27 are formed, for example, by depletion type transistors or n⁺ type buried regions, and the regions 28a and 28b are made always on-state. The regions 29a and 29b are formed as enhancement type transistors. With the above arrangement, the right and left, two NAND basic blocks can commonly use the single contact 21. As a result, the distance, in the lateral direction in Fig. 8, between basic blocks is determined by the distance between n⁺ diffusion layers (source or drain region 15) of a memory cell. The distance can be made smaller than that of the memory shown in Fig. 5A. Fig. 9 is an equivalent circuit of the two NAND basic blocks in the memory array shown in Fig. 8. In Fig. 9, reference numerals 61 and 62 represent enhancement type transistors constructed of the regions 29a and 29b of the select gates 27 and 26. The transistors 61 and 62 are controlled by select gate signals SG4 and SG3, respectively. In Fig. 9, reference numerals 52 to 59 represent memory cells, 52F to 59F floating gate transistors, and 52E to 59E enhancement type transistors. Figs. 10A and 10B show the structure of the memory array according to the third embodiment leading to this invention. Fig. 10A is a plan view of the pattern, and Fig. 10B is a cross section along line A-A′ of Fig. 10A. The different point of the embodiment shown in Fig. 10A from the embodiment shown in Fig. 8 is that an erase gate 72 is provided as seen particularly from Fig. 10B. Namely, as seen from Figs. 10A and 10B, above a floating gate 16 made of a first polysilicon layer, there is formed the erase gate 72 made of a second polysilicon layer with an erase gate oxide film 71 interposed therebetween. There is further formed a control gate 17 made of a third polysilicon layer on the gate 72 with a gate insulating film 73 interposed therebetween. The equivalent circuit of two NAND basic blocks of the memory array constructed as above is shown in Fig. 11. The different point of Fig. 11 from Fig. 9 is that the erase gate 72 is positioned between the floating gate 16 and the control gate 17. These erase gates 72 are connected to erase gate lines EGL1 and EGL2 via which erase gate line signals EG1 and EG2 are applied. In the memory constructed as above, data are erased by setting WL1 to WL8 all to 0 V, and EG1 (or EG2) to 20 V. Electrons as Fowler-Nordheim's tunnel current are therefore emitted from the floating gates 16 of the memory cells 52 to 59 connected to the gate line EGL1 (or EGL2), to the erase gate 72 to thereby erase data. Writing data is performed in the following manner. It is assumed that a selected word line is WL1 for example. The word line WL1 is set to 12 V, data line DL to 10 V, select gate signals SG1, SG3 and SG4 to 20 V, and non-selected word lines WL2 to WL8 to 20 V. Electrons are therefore injected into the memory cell 52 by means of the hot electron effect, to thereby write data. In writing data into the memory cell 53, word line WL2 is set to 12 V while setting other word lines WL1, WL3 to WL8 to 20 V. In a similar manner, up to the memory cell 59 data can be sequentially written. The reason why the voltage of the non-selected word line is set as high as 20 V, is that each memory cell is caused to operate as a triode to suppress the generation of hot electrons and hence prevent writing erroneous data. In the embodiment shown in Fig. 10A, electron emission from the floating gate 16 is carried out not to the substrate but to the erase gate 72. As a result, it is possible to make the gate oxide film 22 formed between the floating gate 16 and the substrate 11 thick, e.g., in the order of 300 Å. The reliability of the gate oxide film 22 is thereby improved to the degree that high reliability similar to an ultraviolet ray erasure type EPROM can be obtained. Figs. 12 A and 12B show the fourth embodiment of this invention. Fig. 12A is a plan view of the pattern, and Fig. 12B is a cross section along line A-A′ of Fig. 12A. The different point of the memory of this embodiment from that shown in Figs. 5A and 5B is that each floating gate 16 is positioned generally at the center of the channel region of each memory cell in the widthwise direction. In the memory of this embodiment, the channel width of the floating gate transistor of each memory cell is determined by a length F indicated in Fig. 12B, and the channel width of the enhancement type transistor is determined by a length (E1 + E2). Even if the floating gates 16 are displaced in the right/left direction as viewed in Fig. 12B due to an occurrence of mask displacement in the right/left direction at the time of forming the floating gates 16, the length F and length (E1 + E2) are maintained constant. It is unnecessary to make uniform the thickness of the gate oxide film 22 between the semiconductor substrate 11 and the floating gate 16. As shown in Fig. 13B (fifth embodiment) and Fig. 14B (sixth embodiment), the upper position of the channel may be made thicker (t2), and only the tunnel portions 42 and 43 for passing tunnel current may be made partially thinner (t1, where t1 < t2). More specifically, as understood from Fig. 13B which is a cross section along line A-A′ of Fig. 13A, and from Fig. 14B which is a cross section along line A-A′ of Fig. 14A, the tunnel portions 42 and 43 are formed at the upper left corners of the floating gates 16 displaced right as viewed in the figures. More specifically, the tunnel portion 42 shown in Figs. 13A and 13B is formed in the following manner. Namely, the oxide film 22 on the substrate 11 is first removed using an opening 44 as a mask. Next, using the opening as a mask, ions such as N⁺ are injected so that a diffusion region 15a is formed on the substrate 11 under the opening 44. This region 15a is integrally connected to the source/drain region 15 to be formed thereafter. Then, an oxide film 22a is thinly formed (t1) on the substrate 11. This oxide film 22a becomes in unison with the originally formed oxide film. Thereafter, there are formed on the oxide films 22 and 22a, the floating gate 16, oxide film 23, and control gate 17. The tunnel portion 43 shown in Figs. 14A and 14B is formed in substantially the same manner as in Figs. 13A and 13B. In this case, in forming the tunnel portion 43, ion injection is performed through an opening 45, and the oxide film 22a is formed through an opening 46. Figs. 15 and 16 are cross sections of the seventh embodiment. Fig. 15 corresponds to Fig. 5B. Fig. 16 corresponds to a cross section along line B-B′ of Fig. 5A. The sixth embodiment shows the case where a silicon nitride film 47 is formed between the floating gate 16 and the control gate 17 of the first embodiment shown in Figs. 5A and 5B. The method of manufacturing a memory having the cross sections shown in Figs. 15 and 16, will be described with reference to Figs. 17A to 17D and Figs. 18A to 18D. Figs. 17A to 17D correspond to Figs. 15, and Figs. 18A to 18D correspond to Fig. 16. First, as seen from Figs. 17A and 18A, after forming an element separation insulating film 2 on a p-type Si substrate 1, there is formed a first gate insulating film 3₁ made of 300 to 400 Å (30 to 40 nm) thermal oxide film (Fig. 18A). The portion of the first gate insulating film 3₁ corresponding to the channel region of a memory cell, is removed with hydrofluoric acid solution or by means of a reactive ion etching, and thereafter there is formed at this portion a second gate insulating film 3₂ made of 50 to 200 Å (20 nm) thermal oxide film. Next, a first polycrystalline silicon film 4 of 500 to 4000 Å (50 to 400 nm) for forming the floating gate is deposited over the whole surface. On this first polycrystalline silicon film 4, there is formed a third gate insulating film 3₃ of 80 to 200 Å (8 to 20 nm) made of a thermal oxide film, and thereafter a silicon nitride film 5 of 80 to 200 Å (8 is 20 nm) is deposited by means of CVD. Next, as seen from Figs. 17B and 18B, the nitride film 5, third gate insulating film 3₃, and first polycrystalline silicon film 4 are selectively etched by means of reactive ion etching, to thereby form a slit separating floating gates between adjoining NAND cells. This slit is patterned so that it partially overlaps the element region and partially exposes an area above the channel region. At this stage, the first polycrystalline silicon film 4 is not yet separated between memory cells M₁ to M₄. Thereafter, there is formed above the channel region a fourth gate insulating film 3₄ of 300 to 400 Å (30 to 40 nm) by means of thermal oxidation (Figs. 17C and 18C). At the time, the surface of the nitride film 5 above the first polycrystalline silicon film 4 is oxidized, to thereby form a high voltage withstand interlayer insulating film of a three-layered structure made of oxide film, nitride film and oxide film. Since the oxidation speed on the nitride film 5 is slow, the thickness of the insulating film on the first polycrystalline silicon film 4 will not become unnecessarily thick. This is significant in that the capacitance ratio between gates are set at optimum values and the write characteristics is not deteriorated. Next, there is deposited a second polycrystalline silicon film 6 of 1000 to 4000 Å (100 to 400 nm) for forming control gates (Figs. 17C and 18C1). Next, cell control gates 6₁ to 6₄ and cell select gates 6₅ and 6₆ are formed by means of reactive ion etching (patterning) while using as a mask a resist R pattern. At this time, by using the same mask, patterning is carried out to the depth of the first polycrystalline silicon film 4 to thereby form floating gates 4₁ to 4₄ separately. Thereafter, by using these gate electrodes as a mask, ions are injected to form an n-type layer 7 which is a source/drain diffusion layer (Fig. 18C2). Next, the whole surface is covered with a CVD insulating film 8 to then open contact holes in the drain regions. Ions are again injected through the contact holes to form an n⁺ type layer 9 (Figs. 17D and 18D). Lastly, wirings such as bit lines are formed by means of Al vapor deposition and patterning, to thereby obtain a finished memory. Fig. 19 shows the eighth embodiment of this invention. Fig. 19 shows, in contrast with Fig. 12A, only the cell portion of the right and left, two NAND basic blocks 10. The cross section along line a-a′ of Fig. 19 is shown in Fig. 20, and the cross section along line b-b′ is shown in Fig. 21. As seen from Fig. 21, the structure shown in the cross section along line b-b′ is the same as Fig. 12A. The structure shown in the cross section along line a-a′, however, is different from Fig. 12A as seen from Fig. 20. Namely, the NAND basic blocks 10 and 10 are separated not by the field oxide film but by an enhancement type MOS transistor (separation transistor) 64 extending in the up/down direction as viewed in Fig. 19. That is, a field oxide film is not necessary. This separation transistor 64 is constructed by forming a gate electrode 66 on the semiconductor substrate (p type) 11 with a gate oxide film 65 interposed therebetween. The gate electrode 66 is set to the potential same as the substrate 11 in an ordinary use state to separate the blocks 10 and 10. The floating gate 16 is formed, similar to the case shown in Fig. 12A, at the position covering only the central portion of the channel (E3 + F3 + E3) with a thin gate oxide film interposed therebetween. Namely, the portion having the width F3 of the whole channel width (E3 + F3 + E3) is covered with the floating gate 16, to thus form a floating gate transistor having a channel width F3. The floating gate 16 and the gate electrode are formed at the same time using the same mask. Therefore, the relative distance between the floating gate 16 and the gate electrode 66 is constant. In other words, there occurs no mask displacement between the gates 16 and 66. It is not necessary, accordingly, to prepare some margin in the right/left direction as viewed in Figs. 22 and 23. In addition, it is not necessary to form a field oxide film as described above, to therefore make the overall size of the memory small. Next, the method of manufacturing the memory shown in Figs. 19 to 23 will be described with reference to Figs. 22A to 22G. Referring to Fig. 22A, a gate insulating film 82 for the separation transistor is grown on a semiconductor substrate 81 by thermal oxidation. Next, a resist 83 is deposited on the film 82 in order to form a thin oxide film 67 under the floating gate. Next, the insulating film 82a above the region where the floating gate transistor is to be formed, is removed by using the resist 83 as a mask. This is shown in Fig. 22B. Next, there is formed an oxide film 83 about 100 Å serving as the floating gate oxide film (Fig. 22C). Next, a polysilicon 84 is deposited in order to form the separation transistor gate and the floating gate. A resist 85 is applied on the polysilicon 84, the resist being patterned in the form of the separation transistor gate and the floating gate. The polysilicon 84 and the insulating film 82 are etched using the resist 85 as a mask. After etching, the resist is removed (Fig. 22E). Thereafter, an oxide film 86 is formed through oxidation (Fig. 22F). Next, there is deposited on the film 86 a polysilicon serving as the control gate (Fig. 22G). The polysilicon 87 is subjected to PEP (Photo Etching Process) to form a predetermined pattern by using a resist (Fig. 22G). Thereafter, N⁺ regions serving as the memory cell sources/drains are formed through ion implantation or the like by using as a mask the control gate and the separation transistor. With the above method, the distance between the floating gate and the separation transistor gate 66 shown in Fig. 19 can be determined without any error. In other words, self alignment can be achieved in the right/left direction as viewed in Fig. 19. The method of manufacturing the memory shown in Figs. 19 to 23 without displacement not only in the right/left direction but also in the up/down direction respectively as viewed in Fig. 19, will be described with reference to Figs. 23A to 28C. Figs. 23A and 23B, according to this method correspond to Fig. 22 of the above-described method. The cross section along line a-a′ of Fig. 23A is shown in Fig. 23B. This method is the same as the above-described method with respect to Figs. 23A and 23B. Next, as seen from Fig. 24A and Fig. 24B showing the cross section along a-a′ of Fig. 24A, a polysilicon 84 is deposited on the films 82 and 83 shown in Fig. 23A and 23B. A resist 85 is applied on the polysilicon 84. The resist 85 is patterned in a stripe shape to form resists 85a and 85b. As seen from Figs. 24A and 20, the resist 85a is arranged to have the width F3 of the floating gate 16, and the resist 85b is arranged to have the width I1 of the separation transistor gate 66. Next, as seen from Fig. 25A and Fig. 25B showing the cross section along line a-a′ of Fig. 25A, the polysilicon 84 and the films 82 and 83 are etched using the resists 85a and 85b as a mask. Thereafter, the polysilicon 84 and the substrate 11 are oxidized to form an oxide film 86. There is formed on this film 86 a polysilicon 87 in order to form the control gate. Next, as seen from Fig. 26A and it cross section along a-a′ (Fig. 26B) and its cross section along line b-b′ (Fig. 26C), the polysilicon 87 is oxidized to form an oxide film 91. A resist 92 is applied on the film 91. As particularly shown in Fig. 26A, the resist 92 is arranged to have a width W at the region where the control gate 16 (refer to Fig. 19) is to be formed. Next, oxide film 91, polysilicon 87 and oxide film 86 are etched using the resist 92 as a mask. The condition after this etching is shown in the cross section (Fig. 27B) along line a-a′ of Fig. 27A and in the cross section (Fig. 27C) along line b-b′ of Fig. 27A. Fig. 27B corresponds to Fig. 26B, and Fig. 27C corresponds to Fig. 26C. As seen from Figs. 27B and 26B, the portion under the resist 92 is not etched. However, as seen from Figs. 27C and 26C, the portion not covered with the resist 92 is etched to thereby expose the substrate 81 and the polysilicon 84. Next, as seen from Figs. 28A and its cross section along line a-a′ (Fig. 28B) and its cross section along line b-b′ (Fig. 28C), the resist 92 is removed. Next, another resist 93 is applied on the surface and patterned to leave the resist 93 only above the region where the separation transistor is to be formed. Next, etching is performed using the resist 93 and oxide film 91 as a mask. As a result, the polysilicon 84 shown at the center of Fig. 27A is removed at the portion extending outside of the oxide film 91, and remained as the floating gate 16 at the portion under the oxide film 91. Next, the resist 93 is removed, and N⁺ regions (refer to Fig. 21) serving as the memory cell source/drain regions 15 are formed through ion implantation or the like by using as a mask the control gate 87 (17) and separation transistor gate 84 (66). The succeeding processes are similar to the conventional processes. As described above, according to the manufacturing method illustrated in Figs. 23A to 28C, it is possible to form the floating gate 16 and enhancement type transistor of a memory cell by means of self alignment, thereby preventing the variation of characteristics to be caused by mask displacement. In addition, since the separation transistor 64 is used, it is not necessary to use a field oxide film. As a result, a memory cell can be formed at the pitch of polysilicon, to thereby make the cell size smaller when compared with the method which uses a field region for separation. In the above embodiments, the operation has been described with the definition that electrons are injected into the floating gate for the erase operation, and electrons withdrawn therefrom for the write operation. However, the operation may be described with the opposite definition that electrons are injected into the floating gate for the write operation, and electrons are withdrawn therefrom for the erase operation. Furthermore, although all memory cells are collectively erased in the above embodiments, they may be erased for each word line by selectively applying a voltage to a word line during the erase operation. The invention is not limited to the above embodiments, but various modifications may be possible which do not contradict the gist of this invention. For example, although the memory size becomes large to some degree, an independent E type transistor is provided in parallel with a conventional floating gate transistor, with the arrangement that the control gate is used commonly and the channel portion is separately formed. Furthermore, although a floating type non-volatile memory has been described, the gist of the present invention is not limited thereto, but a memory cell of a so-called MNOS (Metal-Nitride-Oxide-Semiconductor) type where electric charges are charged at the trap level is also included in this invention.

Claims: A non-volatile semiconductor memory comprising: a plurality of basic blocks (10) each having a plurality of non-volatile memory cells (32 - 39) connected in series; said memory cells (32 - 39) having a pair of source (13) and drain (14) regions formed on the surface area of a semiconductor substrate (11) and sandwiching a channel region therebetween, a floating gate (16) formed above said channel region and being capable of charging electric charges, and a control gate (17) formed above said floating gate (16) and channel region; said floating gate (16) covering a portion of said channel region such that a floating gate transistor (39a) is formed with said floating gate (16) and said control gate (17) being positioned above said channel region, and an enhancement type transistor (39b) is formed with only said control gate (17) being positioned above said channel region, said enhancement type transistor being located adjacent to the floating gate transistor in the direction of extent of said control gate (17), and said floating gate transistor (39a) and said enhancement type transistor (39b) being electrically connected in parallel with each other; and the width of said floating gate (16) being narrower than that of said channel region; and said floating gate (16) partially covers said channel region within its boundaries in the direction of extent of said control gate (17), said floating gate transistor being separated from said boundaries by predetermined lengths (E1, E2), the sum of said lengths (E1 + E2) constituting the channel width of said enhancement transistor such that displacements of said floating gate, which are smaller than said predetermined lengths (E1, E2) do not alter the channel width of said enhancement type transistor; and the threshold voltage of said floating gate transistor (39a) determines the characteristic of said memory cell in either the erase or write state, whereas the threshold voltage of said enhancement type transistor (39b) determines the characteristic of said memory cell in the other of said states; characterized in that - the threshold voltage of said floating gate transistor in the erase and write states is not lower than the threshold voltage of said enhancement type transistor. A memory according to claim 1, wherein said floating gate partially overlaps one of said source and drain regions and wherein a gap (t1) between the lower surface of said floating gate (16) and the upper surface of one of said source (13) and drain (14) regions is smaller than a gap (t2) between the lower surface of said floating gate (16) and the upper surface of said channel region. A memory according to claim 1, characterized by further comprising an erase gate (72) formed between said floating gate (16) and said control gate (17), wherein a current flows between said floating gate (16) and said erase gate (72) for erasing one of said memory cells (32 - 39). A memory according to claim 1, wherein said plurality of basic blocks (10) are connected in parallel in units of an optional number of basic blocks (10). A memory according to claim 1, wherein a silicon nitride film (47) is formed between said floating gate (16) and said control gate (17). A memory according to claim 1, wherein basic bocks (10) disposed adjacent each other in the direction of extent of said floating gate are separated by a field oxide film (12). A memory according to claim 1, wherein basic blocks (10) disposed adjacent each other are separated by an enhancement type MOS transistor (64) having said substrate (11) and a gate electrode (66) facing said substrate (11) with an insulator (65) interposed therebetween. A memory according to claim 8, wherein said enhancement type MOS transistor (64) has its gate (66) formed between said adjacently disposed basic blocks in the direction perpendicular to the direction of extent of said control gate of the basic block (10), said gate (66) of said enhancement type MOS transistor facing said substrate (11) with the gate oxide film (65) interposed therebetween. A method of operating a memory according to claim 1 comprising the steps of making said pair of source (13) and drain (14) regions and/or said substrate (11) higher in potential than that of said control gate (17) of each of said memory cells (32 - 39), so that electrons in said floating gate (16) are discharged into said source (13) and drain (14) regions and/or said substrate (11); and making said control gate higher in potential than said pair of source (13) and drain (14) regions and/or said substrate (11), so that electrons from said source (13) and drain (14) regions and/or said substrate (11) are injected to said floating gate (16). A method of manufacturing a non-volatile semiconductor memory according to one of the preceding claims 1-8 comprising: a first step of alternately forming stripe-shaped linear thin insulating films (83) and stripe-shaped and linear thick insulating films (82) on a semiconductor substrate (81), and depositing a first polysilicon (84) on said thin and thick insulating films (83, 82); a second step of patterning said first polysilicon to form a plurality of floating gates lines each of which with a plurality of floating gates (84) disposed at a predetermined pitch and to form stripe-shaped and linear separation transistor gates (84); a third step of depositing a second polysilicon (87) on said floating gates (84) and said separation transistor gates (84) with an insulating film (86) interposed therebetween; a fourth step of etching said second polysilicon (87) to from stripe-shaped and linear control gates (87) being perpendicular to said separation transistor gates (84) and covering said floating gates (84); a fifth step of forming source (13) and drain (14) regions of floating gate transistors using said separation transistor gates (84) and said control gates (87) as a first mask. A method of manufacturing a non-volatile semiconductor memory according to claim 10, wherein between said fourth step and said fifth step there is an additional step of etching said linear first polysilicon (84) by using a stripe-shaped second mask along said control gate (87) and a stripe-shaped third mask disposed along said separation transistor gates (84), to thereby form a plurality of floating gates (84) at said predetermined pitch between said separation transistor gates (84) along the longitudinal direction of said separation transistor gates. A method according to claim 11, wherein in said fourth step an oxide film (86) is formed on said second polysilicon (87), and an insulating film on said oxide film, said second polysilicon and said first polysilicon is etched by using said first mask, and in said additional step said second mask is said oxide film remaining on said control gates at said fourth step. A method according to claim 10, wherein said fifth step is a process of impurity ion injection and heat treatment. A method according to claim 12, wherein said fifth step is a process of impurity ion injection and heat treatment.

Inventors: ASANO MASAMICHI, ENDOH TETSURO - - - KIKUNA, INOUE SATOSHI SANO-SO F, IWAHASHI HIROSHI - SHIKIMIDAI, KIRISAWA RYOUHEI ISOGO-DAI- -R, MASUOKA FUJIO - - TAKEYAMA, NAKAYAMA RYOZO ISOGO-MARUYAMAD, SHIROTA RIICHIRO TOSHIBA-FURUK, ASANO, MASAMICHI, ENDOH TETSURO 6-13-31-106, KIKUNA, INOUE, SATOSHI SANO-SO 2F, IWAHASHI, HIROSHI 63-10, SHIKIMIDAI, KIRISAWA, RYOUHEI ISOGO-DAI-6-RYO, MASUOKA, FUJIO 1-14-6, TAKEYAMA, NAKAYAMA, RYOZO ISOGO-MARUYAMADAI-HEIGHTS 4-404, SHIROTA, RIICHIRO TOSHIBA-FURUKAWA APARTMENT 242
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1989
Main classification: H01L29
IPC codes: H01L27, H01L29, G11C16, H01L21