Amplifier circuit using feedback load

Abstract: An amplifier circuit of this invention includes a first-stage amplifier (5a,5b), an amplifier element (6a,6b) connected to the output terminal of the first-stage amplifier (5a,5b) as a feedback load, and a further amplifier element (12a,12b) connected between the output and input terminals of the amplifier element (6a,6b), and performs negative feedback through a load (RL1) of the first-stage amplifier (5a,5b). As the amplifier element (6a,6b), a transistor is used, and as the further amplifier element (12a,12b), an emitter-follower transistor is used.

Description: The present invention relates to an amplifier circuit using a feedback load. Fig. 1 is a circuit diagram showing a conventional wide-band feedback type differential amplifier circuit (H. Hillbrand, J. Gruber and P. Russer, "Computer Aided Design of a 1 GHz Band-width Monolithic Integrated Amplifier", ESSCI-RC, 1977, pp. 122 - 124). Referring to Fig. 1, reference numerals 1a and 1b denote input terminals for receiving input signals V in and V in ; 2a and 2b, output terminals for outputting output signals V out and V out ; 3, a high-potential power supply terminal for receiving a potential V CC ; 4, a low-potential power supply terminal for receiving a potential V EE ; 5a and 5b, a pair of input differential transistors as a first pair of differential transistors; 6a and 6b, a pair of output differential transistors as a second pair of differential transistors; 7a and 7b, and 8a and 8b, load resistors having resistances R L1 and R L2 , respectively; 9a and 9b, load capacitors having a capacitance C L ; and 10 and 11, first and second current supply circuits for supplying currents I 1 and I 2 . The circuit shown in Fig. 1 is constituted by the pair of input differential transistors 5a and 5b connected to the load resistors 7a and 8a, and 7b and 8b as loads, respectively, and the pair of output differential transistors 6a and 6b connected to the load resistors 8a and 8b as loads. As the characteristic feature of this circuit, the collectors of the transistors 6a and 6b are connected to their bases through the load resistors 7a and 7b, respectively. Collector signals of the transistors 6a and 6b are fed back to their bases in opposite phases through the load resistors 7a and 7b, in other words, feedback loads are used for the transistors 5a and 5b, thereby realizing a wide-band operation. If transconductances of the transistors 5a and 5b, and 6a and 6b are represented by gm1 and gm2, base resistances are represented by rb1 and rb2, input capacitances are presented by Cπ1 and Cπ2, and an angular frequency is represented by ω, a voltage gain A V of this conventional circuit is given by: A V = gm1·gm2·R L1 ·R L2 (1+gm2·R L2 )(1+jωa)(1+jωb)(1+jωc) where a is the time constant at the bases of the transistors 5a and 5b, b is the time constant at the bases of the transistors 6a and 6b, and c is the time constant at the collectors of the transistors 6a and 6b, and these constants are respectively given by: a = Cπ1·rb1 b = {Cπ2·(R L1 + R L2 + rb2)/ (1 + gm2·R L2 )}·{(1 + jωC L ·R L2 ) /(1 + jωc)} c = C L ·R L2 /(1 + gm2·R L2 ) The gain of the circuit shown in Fig. 1 in a low-frequency mode is approximated by gm1·R L1 from equation (1). The gain in a high-frequency mode is decreased as a frequency increases in accordance with the time constants a , b , and c . However, as can be seen from equations (3) and (4), since the time constants of the bases and collectors of the transistors 6a and 6b can be reduced to 1/(1+gm2·R L2 ) by a feedback effect, a wide-band operation is allowed as compared to a conventional differential amplifier circuit. The time constant b given by equation (3) has an imaginary number component. The imaginary number component is increased as the capacitances C L of the load capacitors 9a and 9b are increased, and operates to cause peaking in frequency characteristics. For this reason, the capacitances C L of the load capacitors 9a and 9b are optimized, thus achieving a wider-band operation. Fig. 2(a) is a graph showing simulation results of frequency characteristics of the circuit shown in Fig. 1. In Fig. 2(a), a frequency is plotted along the abscissa, and a gain is plotted along the ordinate. A plurality of characteristics 21, 22, 23, and 24 are obtained by changing the capacitance C L of the load capacitor to 0.2 pF, 0.1 pF, 0.05 pF, and 0. As can be seen from the graph, peaking characteristics can be provided by increasing the capacitance C L , and the capacitance C L is optimized to realize wide-band characteristics. For this reason, wide-band characteristics can be obtained by utilizing an input capacitance or wiring capacitance of the output-side circuit. Note that a bipolar transistor having a high-frequency cutoff frequency of 60 GHz was assumed for simulation. However, the circuit shown in Fig. 1 suffers from the following drawbacks. Since bias currents from two transistors, i.e., 5a and 6a, and 5b and 6b are flowed into the load resistors 8a and 8b, respectively, tradeoff (the relationship that when one is established, the other cannot be established) between two differential circuit design occurs, and it is not easy to optimize circuit constants. Since the gain of the circuit shown in Fig. 1 is determined by gm1·R L1 , as described above, when this circuit is applied to a variable gain amplifier circuit, it can be realized by controlling gm1 by changing a current value I 1 of the current source circuit. Thus when DC direct coupling is to be realized, DC potentials at the output terminals 2a and 2b are undesirably changed upon control of the current value I 1 . Furthermore, the amplitude of the output signal of the circuit shown in Fig. 1 is determined by R L1 ·I 1 , and may be applied to a limiter amplifier circuit. When the current I 1 of the current source circuit 10 is changed to allow adjustment of the amplitude of the output signal, the DC potentials at the output terminals 2a and 2b are varied in the same manner as in the variable gain amplifier circuit. Since R L1 and R L2 are directly coupled to each other, when a signal large enough to cause a switching operation (logic operation) is input to the input terminals 1a and 1b, the base-collector capacitance is largely changed due to a change in base-collector voltage of the transistors 6a and 6b. Thus, an output waveform S 2 is distorted, as shown in Fig. 2(b). For this reason, the circuit shown in Fig. 1 cannot be applied to a high-speed logic circuit. Note that S 1 denotes an input waveform. Furthermore, in monolithic amplifier circuits which will suffer from a variation in manufacturing, peaking characteristics tend to vary, and optimal frequency characteristics are not easy to obtain. It is, therefore, an object of the present invention to provide an improved amplifier circuit having a wider-band feedback load than in the conventional circuit described above and which is particularly adapted to form a tuned amplifier circuit. US-A-3399357 describes an amplifier circuit using a feedback load, comprising: a first amplifier including a 3-terminal first amplifier element having an input terminal and two output terminals; and a feedback load for said first amplifier; said input terminal of said first amplifier element being arranged to receive an input signal, and one output terminal of said first amplifier element is connected to a first potential; said feedback load comprises: 3-terminal second and third amplifier elements each having an input terminal and two output terminals, and first and second impedances, said input terminal of second amplifier element and one terminal of said first impedance are connected to the other output terminal of said first amplifier element, one output terminal of said second amplifier element is connected to a second potential, and the other output terminal of said second amplifier element is connected to a third potential through said second impedance, said input terminal of said third amplifier element is connected to said other output terminal of said second amplifier element, one output terminal of said third amplifier element is connected to a fourth potential, and the other output terminal of said third amplifier element is connected to the other terminal of said first impedance, and an output terminal is provided at a connecting node between said second impedance and said other output terminal of said second amplifier element or at a connecting node between said first impedance and said other output terminal of said third amplifier element. The present invention is characterized in that: said first impedance includes a tuning circuit consisting of a coil and a capacitor, whereby said amplifier circuit is a tuned amplifier circuit. US-A-3743863 describes certain transistorized differential circuits including a biasing system that substantially reduces the need for resistors in the base circuits of the transistors being biased. One example given of applications of this technique is to a tuned amplifier circuit. An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a conventional amplifier circuit having a feedback load; Fig. 2(a) is a graph showing gain-frequency characteristics of the conventional circuit; Fig. 2(b) is a graph showing input and output waveforms of the conventional circuit; Fig. 3 is a circuit diagram showing a differential amplifier circuit having a feedback load; Fig. 4 is a graph showing gain-frequency characteristics of the circuit of Fig. 3; Fig. 5 is a circuit diagram of another variable gain amplifier circuit; Fig. 6 is an I 1 -output voltage graph of Fig. 5; Fig. 7 is a circuit diagram of a limiter amplifier circuit which can perform output amplitude control; Fig. 8 is a graph showing input and output waveforms of the circuit shown in Fig. 7; Fig. 9 is a circuit diagram of a wide-band amplifier circuit which can change peaking characteristics; and tuned Fig. 10 is a circuit diagram showing a tuned amplifier circuit whose tuning characteristics are improved, according to an embodiment of the present invention; Figs. 3 to 9 relate to circuits outside the scope of the present invention but are helpful in understanding the invention. In those circuits, emitter-follower transistors are added to a feedback circuit portion, and have impedance and bias conditions of the feedback circuit portion different from those of the conventional circuit of Figs. 1 and 2. Referring to Fig. 3, reference numerals 1a and 1b denote input terminals for receiving input signals V in and V in ; 2a and 2b, output terminals for outputting output signals V out and V out ; 3, a high-potential power supply terminal for receiving a potential V CC ; 4, a low-potential power supply terminal for receiving a potential V EE ; 5a and 5b, a pair of input differential transistors as a first pair of differential transistors; 6a and 6b, a pair of output differential transistors as a second pair of differential transistors; 7a and 7b, and 8a and 8b, load resistors having resistances R L1 and R L2 , respectively; 9a and 9b, load capacitors having a capacitance C L ; 10 and 11, first and second current supply circuits for supplying currents I 1 and I 2 ; and 12a and 12b, feedback emitter-follower transistors. The transistors 12a and 12b and the load resistors 7a and 7b constitute a feedback means. In this circuit, the emitter-follower transistors 12a and 12b are added to the conventional circuit shown in Fig. 1, so that a wider-band operation than in the conventional circuit is achieved by the buffer effect of the transistors 12a and 12b. In addition, the circuit shown in Fig. 3 is arranged in a DC manner so that currents flowed through the transistors 5a and 5b are not flowed through the load resistors 8a and 8b, thus facilitating DC design of the circuit. If transconductances of the transistors 5a and 5b, and 6a and 6b are represented by gm1 and gm2, base resistances are represented by rb1 and rb2, input capacitances are presented by Cπ1 and Cπ2, and an angular frequency is represented by ω, a voltage gain A V of the circuit shown in Fig. 3 is given by: A V = gm1·gm2·R L1 ·R L2 (1+gm2·R L2 )(1+jωa)(1+jωb)(1+jωc) where a is the time constant at the bases of the transistors 5a and 5b, b is the time constant at the bases of the transistors 6a and 6b, and c is the time constant at the collectors of the transistors 6a and 6b, and these constants are respectively given by: a = Cπ1·rb1 b = {Cπ2·(R L1 + rb2)/(1+ gm2·R L2 )} ·{(1 + jωC L ·R L2 )/(1 + jωc)} c = C L ·R L2 /(1 + gm2·R L2 ) The gain of the circuit shown in Fig. 3 in a low-frequency mode is approximated by gm1·R L1 from equation (5) in the same manner in the conventional circuit. The gain in a high-frequency mode is decreased as a frequency increases in accordance with the time constants a , b , and c . As can be seen from equations (7) and (8), since the time constants of the bases and collectors of the transistors 6a and 6b can be reduced to 1/(1+gm2·R L2 ) due to the feedback effect, a wider-band operation can be realized as compared to a conventional differential amplifier circuit. Upon comparison between equation (3) of the conventional circuit shown in Fig. 1 and equation (7), since R L2 is eliminated in equation (7) in the circuit of this embodiment, wider-band characteristics than in the conventional circuit shown in Fig. 1 can be realized in principle. This advantage can be obtained by utilizing the fact that impedances from the emitters of the transistors 12a and 12b are low. Fig. 4 is a graph showing simulation results of frequency characteristics of the circuit of Fig. 3. In Fig. 4, a frequency is plotted along the abscissa, and a gain is plotted along the ordinate. A plurality of characteristics 31, 32, 33, and 34 are obtained by changing the capacitance C L of the load capacitor to 0.2 pF, 0.1 pF, 0.05 pF, and 0. In this simulation, the resistance R L1 of the resistors 7a and 7b = 500 Ω, the resistance R L2 of the resistors 8a and 8b = 500 Ω, I 1 = 3 mA, I 2 = 3 mA, and transistors used had a high-frequency cutoff frequency f T = 60 GHz and a current gain β = 50. Upon comparison with the frequency characteristics of the conventional circuit shown in Fig. 1 (Fig. 2(a)), a band-width can be improved by about 25% in the circuit of this embodiment. Like in the conventional circuit shown in Fig. 1, a band-width can be further increased by peaking due to the effect of the capacitance C L . For this reason, by utilizing an input capacitance or wiring capacitance of the output-side circuit, characteristics over a wider band can be obtained. Furthermore, the circuit of Fig. 3 has the following advantages in addition to the band characteristics as compared with the conventional circuit. (1) The current gain β of a bipolar transistor is normally 100 or more. For this reason, currents flowed in the bases of the transistors 12a and 12b are as small as 1/β the collector currents. The bias current of a differential pair consisting of the transistors 5a and 5b and the bias current of a differential pair consisting of the transistors 6a and 6b are separated by the transistors 12a and 12b. For this reason, bias design and gain design of the differential pairs can be independently made, thus allowing easier design than the conventional circuit. Note that in an ultra-high speed transistor, β may often be decreased to be equal to or smaller than 100 due to tradeoff with an operating speed. In principle, however, if β of 1 or more is provided, an effect of improving the conventional circuit can be obtained. (2) Since the transistors 12a and 12b are operated as the emitter-follower transistors, when signals are extracted from the emitters of the transistors 12a and 12b, a low output impedance advantageous for voltage amplification can be obtained. Like in the conventional circuit, output signals can be extracted from the collectors of the transistors 6a and 6b. (3) Fig. 5 shows a variable gain amplifier circuit. The circuit shown in Fig. 5 employs a variable current source circuit 13 in place of the first current source circuit in the circuit shown in Fig. 3. A current I 1 flowed through a differential pair consisting of transistors 5a and 5b is controlled to change the transconductance gm1 of the transistors 5a and 5b, thereby realizing a variable gain function. In this circuit, even if the current I 1 is changed, bias voltages at output terminals 2a and 2b will not be changed (characteristic curve P) due to the emitter follower effect of transistors 12a and 12b unlike in a conventional circuit (characteristic curve Q) shown in the graph of Fig. 6. For this reason, the circuit shown in Fig. 5 can be applied to a multi-stage amplifier circuit realized by DC direct coupling. The circuit arrangement shown in Fig. 5 is suitable for a monolithic IC with which a large-capacitance capacitor is difficult to realize. Note that reference numerals 9a' and 9b' denote load capacitors C L '. (4) Fig. 7 is a circuit diagram of a limiter amplifier circuit which can control an output amplitude. The circuit shown in Fig. 7 additionally employs resistors 14a and 14b having a resistance R E1 connected to the emitters of transistors 5a and 5b in the circuit shown in Fig. 3, and also employs a variable current source circuit 13 in place of the first current source circuit. The gain of the circuit shown in Fig. 7 is given by R L1 /R E1 due to the feedback effect of the resistors 14a and 14b, and its output amplitude is given by I 1 ·R L1 . For this reason, the circuit shown in Fig. 7 has a function of adjusting an output amplitude by controlling a current I 1 while the gain is kept constant. In this circuit, even if the current I 1 is changed, bias voltages at output terminals 2a and 2b will not be changed due to the emitter follower effect of transistors 12a and 12b as same as circuit shown in Fig. 5 unlike in the conventional circuit shown in Fig. 1. Therefore, the circuit shown in Fig. 7 can be applied to a multi-stage amplifier circuit realized by DC direct coupling. The circuit arrangement shown in Fig. 7 is suitable for a monolithic IC with which a large-capacitance capacitor is difficult to realize. Fig. 8 shows input and output waveforms S1 and S2 when the circuit shown in Fig. 7 is used. As can be seen from these input and output waveforms, even if an input signal is increased, an output waveform can be prevented from being distorted due to the effect of the transistors 12a and 12b. Since the base-emitter voltage of the transistors 12a and 12b is applied as a reverse-bias voltage of the base-collector junction of the transistors 6a and 6b, even if a signal large enough to cause a switching operation is input to the input terminals 1a and 1b, a change in base-collector capacitance of the transistors 6a and 6b is smaller than in the conventional circuit. (5) Fig. 9 shows, a wide-band amplifier circuit which can adjust a peaking amount. In the circuit shown in Fig. 9, the collectors of transistors 12a and 12b in the circuit shown in Fig. 3 are separated from the high-potential power supply terminal 3, and are connected to a control terminal 15, so that an arbitrary voltage can be independently applied. A voltage V PC applied to the control terminal 15 is controlled to adjust a junction capacitance as a load capacitance component between the bases and collectors of the transistors 12a and 12b, thereby adjusting a peaking amount. In the conventional circuit arrangement shown in Fig. 1, it is difficult to adjust the peaking amount. In addition, a monolithic amplifier circuit is assumed to suffer from a variation in the manufacture, and a circuit correction is not easy. Therefore, the circuit shown in Fig. 9 is effective for obtaining optimal band-width characteristics. Fig. 10 shows an embodiment of the present invention. In particular, when the present invention is applied to a tuning amplifier circuit, a coil 16a having an inductance L and a capacitor 17a having a capacitance C are connected in parallel with a load resistor 7a of a transistor 5a, and a coil 16b having an inductance L and a capacitor 17b having a capacitance C are connected in parallel with a load resistor 7b of a transistor 5b, thereby constituting parallel resonance circuits. With this arrangement, the circuit shown in Fig. 10 can have tuning characteristics. In this circuit arrangement, since the load resistors 8a and 7a, and 8b and 7b are separated by transistors 12a and 12b, respectively, degradation of Q due to the load resistors 8a and 8b in the tuning characteristics can be prevented. The present invention can be applied to amplifier circuits having various functions such as a high-frequency amplifier circuit in addition to a monolithic amplifier circuit, a hybrid amplifier circuit requiring wide-band characteristics, and the like. In a differential amplifier circuit according to the present invention, 3-terminal amplifier elements including PNP or FETs (including MIS FETs) may be used in place of NPN bipolar transistors. The present invention is not limited to a differential circuit but may also be applied to a single-end circuit, and the like. The circuit in this case is constituted by left-hand side circuit components (1a, 4, 5a, 6a, 7a, 8a, 10, 12a) of the differential pairs in the circuit shown in Fig. 10. As described above, since emitter-follower transistors are added as a feedback means, the buffer effect can be provided, and the following effects can be obtained. (1) Characteristics over a larger band-width can be obtained. (2) A bias current in a first-stage amplifier and a bias current in a transistor included in a feedback load can be separated, thus allowing easy gain design and bias design. (3) A bias voltage at an output terminal is not changed due to the emitter follower effect. If a current source circuit of a first-stage amplifier is replaced with a variable current source circuit, the present invention can be applied to a DC direct coupling type variable gain amplifier. (4) A bias voltage at an output terminal is not changed due to the emitter follower effect, and DC direct coupling is allowed. If an emitter resistor is added to a transistor in a first-stage amplifier and a current source circuit of the first-stage amplifier is replaced with a variable current source circuit, the present invention can be applied to a limiter amplifier which can adjust an output amplitude. (5) If a collector application potential of an emitter follower is designed to be controllable, a peaking amount can be adjusted upon control of a base-collector junction capacitance.

Claims: An amplifier circuit using a feedback load, comprising: a first amplifier including a 3-terminal first amplifier element (5a) having an input terminal (1a) and two output terminals; and a feedback load for said first amplifier; said input terminal (1a) of said first amplifier element (5a) being arranged to receive an input signal, and one output terminal of said first amplifier element is connected to a first potential (4); said feedback load comprises: 3-terminal second and third amplifier elements (6a,12a) each having an input terminal and two output terminals, and first and second impedances (7a,8a), said input terminal of said second amplifier element (6a) and one terminal of said first impedance (7a) are connected to the other output terminal of said first amplifier element (5a), one output terminal of said second amplifier element (6a) is connected to a second potential (4), and the other output terminal of said second amplifier element (6a) is connected to a third potential (3) through said second impedance (8a), said input terminal of said third amplifier element (12a) is connected to said other output terminal of said second amplifier element (6a), one output terminal of said third amplifier element (12a) is connected to a fourth potential (3), and the other output terminal of said third amplifier element (12a) is connected to the other terminal of said first impedance (7a), and an output terminal is provided at a connecting node between said second impedance (8a) and said other output terminal of said second amplifier element (6a) or at a connecting node between said first impedance (7a) and said other output terminal of said third amplifier element (12a); characterized in that: said first impedance (7a) includes a tuning circuit consisting of a coil (16a) and a capacitor (17a), whereby said amplifier circuit is a tuned amplifier circuit. An amplifier circuit according to Claim 1 characterized in that said first, second and third amplifier elements (5a,6a,12a) comprise transistors. An amplifier circuit according to Claim 1 or Claim 2 characterized in that said first impedance (7a) includes a resistor (7a) in parallel with said tuning circuit. An amplifier circuit according to any one of Claims 1 to 3 characterized in that a first current source (10) is connected between said one output terminal of said first amplifier element (5a) and said first potential (4), and a second current source (11) is connected between said one output terminal of said second amplifier element (6a) and said second potential (4). An amplifier circuit according to Claim 4 characterized in that said first current source (10) comprises a variable current source (13). An amplifier circuit according to Claim 5 characterized by a resistor (14a) connected between said variable current source (13) and said one output terminal of said first amplifier element (5a). An amplifier circuit according to any one of Claims 1 to 6 characterized in that said third and fourth potentials (3) are equal to each other. A differential amplifier circuit arrangement characterized by comprising first and second amplifier circuits each according to any one of Claims 1 to 7, wherein: said one output terminal of said first amplifier element (5a) of said first amplifier circuit and one output terminal of the first amplifier element (5b) of said second amplifier circuit are commonly connected to constitute a first differential pair commonly connected to said first potential (4), and said one output terminal of said second amplifier element (6a) of said first amplifier circuit and one output terminal of the second amplifier element (6b) of said second amplifier circuit are commonly connected to constitute a second differential pair commonly connected to said second potential (4).

Inventors: ICHIHARA NOBORU, ICHINO HARUHIKO, ICHIHARA, NOBORU, ICHINO, HARUHIKO
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1989
Main classification: H03F3
IPC codes: H03F3