Photonic-integrated-circuit fabrication process

Abstract: A process for etching corrugated patterns, for distributed feedback (DFB) or distributed Bragg reflector (DBR) devices, is disclosed. A masking layer is deposited over the area adjacent to the area where the corrugation is required. A corrugation-patterned mask is formed on the masking layer as well as on the area where the corrugation is required and etching is carried out to form corrugations (62) in the masking layer as well as the desired corrugations (61). The masking layer can then be removed. The material of the masking layer is chosen to etch at the same rate, and thus to deplete the concentration of the etchant by the same amount, as the material in which the corrugations are required. Thus, higher concentrations of etchant near the edge of the masking layer, and consequent over-etching, are avoided.

Description: Technical Field This invention involves photonic integrated circuits (PICs) and processes for fabricating such PICs. Background of the Invention The invention of the optical fiber, and subsequent developments which resulted in economical processes for manufacturing such fiber, has given birth to the field of optical communications. Currently, this field is essentially limited to transmission of information in optical form. However, the processing of information still proceeds by way of electrical devices and methods. Consequently, information signals must be processed in electrical form, transformed to optical form for transmission, and then retransformed to electrical form for further processing after the optical signals are received. Clearly, the economics of optical communications will drive the industry to develop optical devices capable of processing information in optical form. Such devices would include, for example, lasers, amplifiers, detectors, couplers, modulators, and regenerators, all coupled by appropriate optical waveguides. Such devices can be fabricated today, however, generally, they can only be manufactured in discreet form, and in order to be economically viable for optical communications systems, such devices would have to be manufactured in integrated form. However, to date, suggested processing techniques for fabricating PICs are not yet sufficiently effective or flexible to be economically viable for use in commerical optical communications. Summary of the Invention This invention is an improved process for fabricating Photonic Integrated Circuits (PICs) as set out in claim 1 Specific inventive processing steps are addressed to interconnecting passive waveguides, active devices, and grating filtering regions without the substantial optical discontinuities which appear in the prior art. Brief Description of the Drawing FIG. 1 is a schematic representation of a prior art device involving a selective area grating. FIG. 2 is a schematic representation of a base wafer used to fabricate the prior art device of FIG. 1. FIG. 3 is a schematic representation of a corrugated resist mask placed on the structure of FIG. 2 in order to etch a corrugation in the semiconductor surface. FIG. 4 is a schematic representation of a base wafer used in an embodiment of the inventive process. FIG. 5 is a schematic representation of the base wafer of FIG. 4 with a corrugated resist mask. FIG. 6 is a schematic representation of the structure of FIG. 5 subsequent to etching. FIG. 7 is a schematic representation of the structure of FIG. 6 in which the corrugated layer is removed and the structure is overgrown. Detailed Description Large numbers of photonic devices involve the use of gratings. For example, the distributed feedback laser (DFB) and other DFB devices, and the distributed Bragg reflector (DBR), and other DBR devices utilize grating regions as an integral part of the device. Often these devices will include optical waveguides, and in many such devices the grating portion of the device will be limited in physical extent. Fabrication of such limited grating areas using prior art techniques has often resulted in unacceptable waveguide or optical discontinuities. In other devices involving gratings, prior art fabrication techniques necessitate the deleterious removal of essential layers in the device in regions where the grating will not ultimately appear. The present invention permits the fabrication of selective area gratings without these deleterious effects. The ability of the technique to fabricate such areas will now be discussed in detail with reference to FIGS. 1 and 2. FIG. 1 is a schematic representation (not to scale) of a prior art device involving a selective area grating 11. In this FIG., 12 may be an exemplary active or gain layer in a laser or amplifying structure. 13 is a waveguiding layer intended to be largely continuous over some extended portion of the device. (In this and other of the schematic drawings portions of the device unnecessary for the immediate discussion at hand are not shown.) In the prior art, the device shown in FIG. 1 may be fabricated by first growing a number of epitaxial layers on a suitable substrate, followed by deposition of a suitable masking dielectric 23, as shown in FIG. 2. In this FIG., 22 is a layer, a portion of which will ultimately provide the gain area 12 as shown in FIG. 1. In FIG. 2, 21 is the layer which will ultimately form the waveguiding region 13 in FIG. 1. 23 is the dielectric masking layer. Using standard photolithography procedures, photoresist is deposited and patterned to leave a protective resist mask 24, as shown in FIG. 2, over the region where no grating is desired. The dielectric layer is then patterned with standard etching techniques to cover the limited region of the structure shown as 12 in FIG. 1. Layer 22 is then removed with suitable selective etchants over only the exposed portion of the device. This is followed by the application of a photoresist, holographic exposure, and developing to form a corrugated resist mask 31 suitable for etching a corrugation in the semiconductor surface as shown in FIG. 3. Due to the remaining dielectric layer, this corrugation will only be etched into the exposed region 11 in FIG. 1. Following the grating formation, the dielectric mask is removed and the structure is then overgrown with a suitable cladding layer 15 as shown in FIG. 1. In this prior art technique, it is found that an over-etched region, 14 in FIG. 1, appears which results in undesirable optical discontinuity in the waveguide layer, 13, as shown, and poor device performance. We believe that the reason for this over etching may be explained as follows. During the etching step, active etching will only take place in region 11 of FIG. 1 but not in region 12 where the dielectric will remain. Accordingly, the etchant over area 11 will slowly become at least somewhat depleted while the etchant over area 12 will remain substantially at full strength, since no etching takes place in area 12. Consequently, the region 14, which is closest to this undepleted etchant bath which appears over area 12, will be more strongly etched than other portions of region 11 over which there will be at least a somewhat depleted etchant bath. The present process avoids this over etching by eliminating the use of a dielectric mask during the corrugation etch, and providing instead a material over region 12 whose function will at least include providing material for the bath to etch so that the etchant bath will be approximately uniformly depleted along the entire length of the device. While this additional layer is being etched, it still provides protection, as the dielectric did in the prior art, for the underlying layers. We find that using this technique, the over etching phenomenon is eliminated to the extent of our observational capabilities. The resulting degree of optical continuity along the waveguide has led to substantial improvements in device performance as disclosed in greater detail in the discussion of the embodiment below. The inventive process is shown schematically in FIGS. 4-7. FIG. 4 shows the initial structure, analogous to FIG. 2, where a resist mask 44 has already been patterned with standard photolithographic techniques. In FIG. 4, layer 43 is now a material which will etch, during the corrugation etching step, at a rate comparable to the etch rate for layer 41, for example, an appropriate epitaxially grown semiconductor layer. Again referring to FIG. 4, using the resist mask, or any other suitable mask, layers 42 and 43 are removed in the exposed regions with suitable material selective etchants. Then, just as in the prior art, a corrugated resist mask is formed with holographic exposure, for example, to leave the configuration shown in FIG. 5. The corrugation is then uniformly transferred into the structure with a suitable etchant to form the structure of FIG. 6. It is at this step that the overetching at the boundary between the two regions is avoided. Corrugated layer 62 is then removed with a suitable material selective etchant, and the structure may then be overgrown to yield the final desired structure of FIG. 7. The removal of the corrugated layer 62 may not be required when the following overgrown layer will be of similar composition or optical properties. This discussion has been in terms of a device where the grating appears adjacent to a portion of the waveguide over which there are additional functioning layers, such as the region 12 in FIG. 1. In other applications, it may be desirable to juxtapose the grating adjacent to a portion of the waveguide over which there is no additional functioning layer. This can still be accomplished with the inventive processing technique by utilizing an additional, but photolithographic, exposure, following the holographic exposure to completely remove the resist grating mask over the region adjacent to the grating region. Therefore, during the grating etching step, this adjacent region is uniformly etched to leave a smooth surface with no corrugation.

Claims: A method of etching a first, patterned surface adjacent to a second surface, which second surface remains substantially unetched during the etching, comprising : forming a second surface masking material (43) over the second surface; forming a mask (FIG. 5) over both the first surface and the second surface masking material, so as to provide a corrugated pattern formed form ridges of masking material with interposed unmasked portions; and exposing both the first surface and the second surface masking material, through the corrugated pattern to an etchant, CHARACTERISED IN THAT the said first surface and second surface masking material are etched at substantially the same rate when exposed to the said etchant, whereby the said first surface is uniformly etched without there being any substantial non-uniformity in the amount of the etching in regions of the first surface adjacent to the second surface. The method of claim 1 wherein the surfaces are semiconductor materials. The method of claim 2 wherein said semiconductor materials are selected from the group consisting of III-V compound semiconductors. The method of claim 3 wherein the semiconductor material comprises InGaAsP. The method of any of the preceding claims wherein the second surface masking material is an epitaxially grown material. The method of claim 5 wherein the epitaxially grown material is a semiconductor. The method of claim 1 wherein the said first and second surfaces comprise InGaAsP and the second surface masking material comprises InP.

Inventors: KOCH THOMAS LAWSON, KOREN UZIEL, KOCH, THOMAS LAWSON, KOREN, UZIEL
Applicants: AT & T CORP, AT&T CORP.
Application year: 1989
Main classification: G02B6
IPC codes: G02B6, H01S5