Process for making a bipolar integrated circuit

Abstract: A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy (12,13,14) on top of a substrate (10). The first epitaxial layer (12) is of the same conductivity type as the substrate (10) and adds additional height to the substrate (10) surrounding the buried layer (11). The buried layer (11) serves as a collector and it is surrounded by an isolation area (24). The top two epitaxial layers (13,14) are of a conductivity type opposite to that of the substrate (10) with the upper most epitaxial layer (14) having a higher dopant density than does the middle epitaxial layer (13). A master mask is used to provide self-alignment between the isolation area (24), a collector plug (28) which makes contact to the buried layer (11), and a base region (29).

Description: This invention relates, in general, to a method for making semiconductor integrated circuits, and more particularly, to a process for making a high voltage bipolar transistor integrated circuit. The present technique for making high voltage (between 20 volts and 150 volts) bipolar transistors uses a low doped, thick silicon epitaxial layer. This thick silicon epitaxial layer causes some undesirable limitations. As an example, in order to create an isolation region for a transistor, long drive in times, at high temperatures, are necessary in order to drive in the dopants to create the isolation area. As a consequence, the lateral diffusion of the isolation area increases the minimum transistor size. Also such thermal cycles enhance the up diffusion of the buried layer thus reducing the active silicon layer under the bipolar transistor base. In this type of process the epitaxial layer must be thick in order to ensure an effective active layer underneath the base area. An example of such a device can be found in US-A-3,982,974, issued to Edel et al on September 28, 1976. The low dopant concentration necessary for the higher voltage bipolar transistors allows an increase in the expansion of the depletion spread between the base area and the isolation area. This results in requiring the spaces between these areas to be increased. Also the devices are extremely sensitive to the surface effects at the interface between the silicon epitaxial layer and a covering oxide layer. Often guard rings are required in order to eliminate the parasitic effects occurring near the surface. Therefore, it would be desirable to eliminate some of the negative effects of the thick epitaxial layer in order to increase the circuit density or the number of circuits per unit of silicon area. The document FR-A-2 445 022 shows a method for producing integrated semiconductor devices using two epitaxial layers formed on a substrate. The first epitaxial layer is of the same conductivity type as the substrate and the second epitaxial layer is of an opposite conductivity type. German Patent Application DE-A-3136364 discloses a similar method. Accordingly, it is an object of the present invention to provide an improved bipolar integrated circuit. Another object of the present invention is to provide a high voltage bipolar integrated circuit having a reduced size. Yet another object of the present invention is to provide a three layer epitaxial process with self-aligned isolation for highly dense and low cost high voltage bipolar integrated circuits. Yet a further object of the present invention is to provide a bipolar integrated circuit capable of handling a higher voltage yet consuming less silicon area. Summary of the Invention In accordance with a first aspect of the present invention there is provided a process for making a bipolar integrated circuit, comprising: providing a substrate of a first conductivity type and having a first major surface; selectively forming a buried layer of a second conductivity type in the substrate and extending from the first surface; providing a first epitaxial layer of the first conductivity type over the first surface; providing a second epitaxial layer of the second conductivity type over the first epitaxial layer; providing a third epitaxial layer of the second conductivity type over the second epitaxial layer and having a higher dopant concentration than the second epitaxial layer; selectively providing a dopant of the first conductivity type in the third epitaxial layer in a manner to surround the buried layer; selectively providing a dopant of the second conductivity type in the third epitaxial layer and positioned over a first portion of the buried layer; performing a diffusion to drive in the dopants selectively provided in the third epitaxial layer and simultaneously causing the buried layer to diffuse upwards through the first epitaxial layer (12) into the second epitaxial layer (13), wherein the selectively provided dopant of the first conductivity type extends to the first epitaxial layer to form an isolation region and the selectively provided dopant of the second conductivity type extends to the buried layer to form a collector contact plug; selectively providing a base region of the first conductivity type in the third epitaxial layer over a second portion of the buried layer; and providing and emitter region of the second conductivity type in the base region. In accordance with a second aspect of the present invention there is provided a bipolar integrated circuit comprising: a substrate of a first conductivity type; a first epitaxial layer of the first conductivity type covering the substrate; a second epitaxial layer of a second conductivity type covering the first epitaxial layer; a third epitaxial layer of the second conductivity type covering the second epitaxial layer and having a dopant concentration higher than that of the second epitaxial layer; a buried layer of the second conductivity type extending from the substrate through the first epitaxial layer and into the second epitaxial layer; an isolation region of the first conductivity type surrounding the buried layer and extending through the third and second epitaxial layers and at least into the first epitaxial layer; a collector contact plug of the second conductivity type extending through the third and second epitaxial layers and making contact with a first portion of the buried layer; a base area of the first conductivity type located in the third epitaxial layer above a second portion of the buried layer; and an emitter area of the second conductivity type located in the base area. Brief Description of the Drawings FIGS. 1-8 illustrate in outline form progressive steps in the method of practising the present invention; and FIG. 9 is a continuation of the process and illustrates in cross-sectional view a portion of an integrated circuit with one bipolar transistor near its completion stage. Detailed Description of the Invention A method of manufacturing an integrated circuit containing bipolar devices will now be described in conjunction with the figures. An understanding of the present invention can be obtained through the explanation of the manufacturing of a single bipolar device as illustrated in the drawings; however, it will be understood that an integrated circuit contains many such devices or other devices such as PNP transistors, diodes, capacitors, resistors, etc. with or without the NPN transistor illustrated. To simplify the explanation, conventional process steps will be described only briefly, while those steps relating to the novel aspects of the process will be described in greater detail. FIG. 1 illustrates a cross-sectional view of a small portion of a semiconductor substrate 10 having diffused dopants 11. Substrate 10 is of P conductivity type material having a top surface from which N+ conductivity type dopant extends to form a buried layer 11. FIG. 2 illustrates an epitaxial layer 12 grown over substrate 10 and covering buried layer 11. Epitaxial layer 12 is of lightly doped P conductivity type material. The resistivity of epitaxial layer 12 will be close to the resistivity of substrate 10. Epitaxial layer 12 serves as a capping layer to prevent auto doping during subsequent processing steps. As will be seen subsequently epitaxial layer 12 also provides additional height of P conductivity type substrate 10 around buried layer 11. FIG. 3 illustrates two additional epitaxial layers covering first epitaxial layer 12. Second epitaxial layer 13 is directly on top of epitaxial layer 12 and is of a lightly doped N conductivity type material. Third epitaxial layer 14 covers epitaxial layer 13 and is also of N conductivity type material which has a higher dopant concentration than does epitaxial layer 13. There are advantages resulting from the two step N conductivity type epitaxial layers which will be more apparent hereinafter. By way of example only and not as a limitation, in one embodiment, the dopant concentration of buried layer 11 is 5x10¹⁸ atoms per cubic centimeter, the dopant concentration of epitaxial layer 12 is 1x10¹⁵ atoms per cubic centimeter, the dopant concentration of epitaxial layer 13 is 1x10¹⁵ atoms per cubic centimeter, and the dopant concentration of epitaxial layer 14 is 2x10¹⁵ atoms per cubic centimeter. Typically, the dopant concentration of epitaxial layer 14 is twice that of epitaxial layer 13. The dopant concentration of epitaxial layer 14 can range from 1x10¹⁵ atoms per cubic centimeter to 5x10¹⁵ atoms per cubic centimeter depending upon the desired breakdown voltage characteristics of the resulting transistor. The higher the dopant concentration the lower the voltage. As an example, for a dopant concentration of 1x10¹⁵ for epitaxial layer 14 the resulting device will be a 120 volt transistor, and for a dopant concentration of 5X10¹⁵ the resulting device will be a 25 volt transistor with the appropriate epitaxy thickness. FIG. 4 illustrates the integrated circuit further along in its process. An oxide layer 16 has been grown over epitaxial layer 14. A dielectric layer 17 has been grown over oxide layer 16. Dielectric layer 17 can be any suitable material such as silicon nitride or the like. Dielectric layer 17 has been patterned by using well known techniques to provide openings 18, 19, 21, and 22. Openings 18 and 22 define the location for an isolation region, opening 19 defines the location for a collector plug, and opening 21 defines the location for a base region. By using dielectric layer 17 as a master mask, self-alignment results between the isolation region, the collector plug, and the base region. A master mask technique is described in U. S. Reissue Patent Re. 30,282, reissued on May 27, 1980 to Hunt et al. FIG. 5 shows a patterned layer of photoresist 23 covering the integrated circuit. Photoresist 23 is patterned to prevent covering openings 18 and 22. Using conventional techniques, the portion of oxide layer 16 existing in openings 18 and 22 has been suitably etched away to expose the top surface of epitaxial layer 14. This permits the placement of dopants through openings 18 and 22 to provide an isolation region. FIG. 6 illustrates these dopants as regions 24. In addition, FIG. 6 shows that photoresist 23 has been removed. Note that the dopants 24 are not completely diffused at this point in time, and form a continuous perimeter to completely surround the resulting bipolar device. FIG. 7 illustrates the integrated circuit having a new layer of patterned photoresist 26. Photoresist 26 has been patterned to expose opening 19. It can also be seen, in FIG. 7, that additional oxide has been grown and covers the portions of epitaxial layer 14 that were exposed in FIG. 6. At the same time additional oxide was grown in opening 21. After the growth of the additional oxide, photoresist 26 is applied and then oxide 16 that existed through opening 19 is etched away to expose epitaxial layer 14 through opening 19. An N type dopant is then introduced into epitaxial layer 14 through opening 19. Once this dopant is introduced into epitaxial layer 14 a diffusion step is performed to drive in that dopant along with the dopants 24. This diffusion step will produce isolation regions 24 and collector plug 28 illustrated in FIG. 8. Also note that buried layer 11 has diffused upward through epitaxial layer 12. Since epitaxial layer 12 has provided an additional height to substrate 10, isolation region 24 does not have to diffuse as deeply as it had to in prior art devices. As is well recognized, not only does the dopant provided for isolation region 24 diffuse downward but it also diffuses laterally and therefore by shortening the distance that the dopants must diffuse downwardly this also reduces the amount of lateral diffusion that occurs. Since the amount of lateral diffusion is reduced, the overall area provided for the bipolar device can be reduced also. It has been found that using the present invention results in approximately 50% reduction in the amount of silicon area required. FIG. 8 also illustrates that photoresist layer 26 has been removed and additional oxide grown in order to cover the portion of epitaxial layer 14 exposed through opening 19. Then a patterned layer of photoresist 27 is applied which has an opening to coincide with opening 21. The portion of oxide layer 16 existing in opening 21 is etched away to expose that portion of epitaxial layer 14 existing under opening 21. A P type dopant is then added through opening 21 to provide base area 29 (shown in FIG. 9). After base well or region 29 is formed photoresist 27, dielectric layers 17, and oxide layer 16 are all removed. As shown in FIG. 9, a new layer of oxide 32 is then grown over the integrated circuit and patterned to provide metal contact areas and to provide emitter area 31. Emitter area 31 is made from N type dopants. The metal layer provided to make contact through the openings in oxide layer 32 are not illustrated since these are well known to those skilled in the art. In a typical integrated circuit, multiple metal layers are generally required. In a typical device the dopant concentrations provided in base well or region 29 are 5x10¹⁸ atoms per cubic centimeter and are of P type while the dopant concentration in emitter area 31 are 1x10²¹ atoms per cubic centimeter. In one embodiment of the present invention, epitaxial layer 12 is approximately 4 microns thick, epitaxial layer 13 is approximately 10 microns thick, and epitaxial layer 14 is approximately 5 microns thick. The dopant concentration of isolation area 24 is 2x10¹⁹ atoms per cubic centimeter and the dopant concentration of collector plug 28 is 5x10¹⁹ atoms per cubic centimeter. These parameters will vary depending on the desired breakdown voltage. The preferred dopant to use in buried layer 11 is antimony because it exhibits less severe auto doping than does arsenic or phosphorus. Epitaxial layers 13 and 14 are doped with arsenic. Epitaxial layer 12 is doped with boron. Several advantages are achieved by having higher dopants in epitaxial layer 14 than exist in epitaxial layer 13. First the surface effects are reduced. As an example, the MOS field effect transistor action between base region 29 and isolation area 24 is decreased since the higher doped surface layer causes the threshold voltage of this parasitic MOS field effect transistor to be higher. The highly doped surface epitaxial layer 14 also helps to neutralize the charge in oxide layer 32. Thirdly the highly doped epitaxial layer 14 permits a shrinking of the spacing rules because base region 29 does not spread as far in the lateral direction through the highly doped epitaxial layer 14. A fourth benefit achieved by the dual epitaxial layers 13 and 14 is that the breakdown voltage of the bipolar transistor increases because of the lower dopants in epitaxial layer 13. By now it should be appreciated that there has been provided a new and improved bipolar integrated circuit which requires less silicon area. The number of critical process steps in making the integrated circuit is reduced by the use of a master mask.

Claims: A process for making a bipolar integrated circuit, comprising: providing a substrate (10) of a first conductivity type and having a first major surface; selectively forming a buried layer (11) of a second conductivity type in the substrate and extending from the first surface; providing a first epitaxial layer (12) of the first conductivity type over the first surface; providing a second epitaxial layer (13) of the second conductivity type over the first epitaxial layer; providing a third epitaxial layer (14) of the second conductivity type over the second epitaxial layer (13) and having a higher dopant concentration than the second epitaxial layer (13); selectively providing a dopant of the first conductivity type in the third epitaxial layer (14) in a manner to surround the buried layer (11); selectively providing a dopant of the second conductivity type in the third epitaxial layer (14) and positioned over a first portion of the buried layer (11); performing a diffusion to drive in the dopants selectively provided in the third epitaxial layer (14) and simultaneously causing the buried layer (11) to diffuse upwards through the first epitaxial layer (12) into the second epitaxial layer (13), wherein the selectively provided dopant of the first conductivity type extends to the first epitaxial layer (12) to form an isolation region (24) and the selectively provided dopant of the second conductivity type extends to the buried layer (11) to form a collector contact plug (28); selectively providing a base region (29) of the first conductivity type in the third epitaxial layer (14) over a second portion of the buried layer (11); and providing an emitter region (31) of the second conductivity type in the base region (29). The process of claim 1 wherein the dopant concentration in the third epitaxial layer (14) is approximately twice the dopant concentration in the second epitaxial layer (13). The process of claim 1 or 2 further comprising the steps of: providing a layer of oxide (16) over the third epitaxial layer (14) after providing the third epitaxial layer (14), providing a dielectric layer (17) over the layer of oxide (16), and using a master mask to selectively provide openings (18,22) in the dielectric layer (17) for the isolation region (24), the collector contact plug (19), and the base region (21); and wherein selectively providing the dopant of the first conductivity type in the third epitaxial layer (14) includes etching through the oxide in the opening provided for the isolation region (24), and providing a dopant of the first conductivity in the opening provided for the isolation region (24); and wherein selectively providing the dopant of the second conductivity type in the third epitaxial layer (14) includes masking over all the openings except the opening for the collector contact plug (19), etching through the oxide in the collector contact plug opening (19), and providing a dopant of the second conductivity type in the collector contact plug opening (19); and wherein performing the diffusion includes diffusing the dopants in the isolation region (24), in the collector contact plug opening (19), and in the buried layer (11); and wherein selectively providing the base region (29) includes masking over all the openings except for the base region opening (21), and forming the base region (29) of the first conductivity type through the base region opening (21). The process of claim 3 wherein the dielectric (17) is silicon nitride. The process of claim 3 or 4 wherein forming the base region (29) includes etching through the oxide in the base region opening (21) and implanting dopants and diffusing the dopants in the base region (29). The process of any preceding claim wherein the dopant concentration of the buried layer (11) is approximately 5x10¹⁸ atoms per cubic centimeter, the doping concentration of the third epitaxial layer (14) is nearly twice the doping concentration of the second epitaxial layer (13), the dopant concentration of the isolation region (24) is approximately 2x10¹⁹ atoms per cubic centimeter, the dopant concentration of the base region (29) is approximately 5x10¹⁸ atoms per cubic centimeter, and wherein the dopant concentration of the collector contact plug (28) is approximately 5x10¹⁹ atoms per cubic centimeter. A bipolar integrated circuit comprising: a substrate (10) of a first conductivity type; a first epitaxial layer (12) of the first conductivity type covering the substrate; a second epitaxial layer (13) of a second conductivity type covering the first epitaxial layer (12); a third epitaxial layer (14) of the second conductivity type covering the second epitaxial layer (13) and having a dopant concentration higher than that of the second epitaxial layer; a buried layer (11) of the second conductivity type extending from the substrate through the first epitaxial layer (12) and into the second epitaxial layer (13); an isolation region (24) of the first conductivity type surrounding the buried layer (11) and extending through the third (14) and second (13) epitaxial layers and at least into the first epitaxial layer (12); a collector contact plug (28) of the second conductivity type extending through the third (14) and second (13) epitaxial layers and making contact with a first portion of the buried layer (11); a base area (29) of the first conductivity type located in the third epitaxial layer (14) above a second portion of the buried layer (11); and an emitter area (31) of the second conductivity type located in the base area (29).

Inventors: CAMBOU BERTRAND F, CAMBOU, BERTRAND F.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1989
Main classification: H01L21
IPC codes: H01L21, H01L29, H01L27