Method and apparatus for encoding images

Abstract: There is disclosed an image encoding system in which a size of an image to be encoded is inputted, reference pixel positions or the number of reference pixels are determined in accordance with an input image size, and a noticed pixel is encoded by using reference pixels of the determined pixel positions or the determined number.

Description: The present invention relates to a method and apparatus for encoding an image based on image communication and an image data base. In a facsimile apparatus as a typical example of a conventional still image communication apparatus, an image is sequentially scanned in a raster direction, and the scanned data is encoded and transmitted. According to this scheme, in order to grasp the entire image, encoded data of the entire image must be transmitted to result in a long transmission time. It is therefore difficult to apply this scheme to image data base service and image communication service such as video telex service. In order to grasp the entire image at high speed, hierarchical encoding can be proposed. Fig. 1 shows a conventional hierarchical encoding scheme. An image is reduced into 1/2 by subsampling in both main scanning and subscanning directions to obtain a 1/2 reduced image. The 1/2 reduced image is further reduced to obtain a 1/4 reduced image. This operation is repeated to sequentially obtain low-resolution images. Encoding is started from low-resolution images, and the encoded images are sequentially transmitted, thereby allowing grasping of the entire image at the receiving side at high speed. In the example of Fig. 1, an image is reduced into 1/2, 1/4, and 1/8 in both the main scanning sand subscanning directions, and encoding is performed in an order of 1/8, 1/4, 1/2, and 1 (one-to-one size image or original image). The encoded data are then transmitted in the above order. Referring to Fig. 1, frame memories (FM1, FM1/2, FM1/4, and FM1/8) 101 to 104 store an original image, and 1/2, 1/4, and 1/8 reduced images, respectively. Reduction units (RDs) 105 to 107 generate 1/2, 1/4, and 1/8 reduced images. Encoders 108 to 111 encode the 1/8, 1/4, and 1/2 reduced images and the original image, respectively. In encoding of the 1/8 reduced image, the 1/8 reduced images stored in the frame memory 104 are sequentially scanned, and entropy coding such as arithmetic encoding is performed with reference to a noticed pixel and neighboring pixels. For the 1/4 reduced image, encoding efficiency can be increased by referring to the neighboring pixels of the noticed pixel and the neighboring pixels of the 1/8 reduced image. Similarly, the 1/2 reduced image is encoded with reference to the 1/4 reduced image, and the original image is encoded with reference to the 1/2 reduced image. As is apparent from the prior art shown in Fig. 1, reduction is performed in an order of 1/2, 1/4, and 1/8. Encoding is performed in an order of 1/8, 1/4, 1/2, and 1 from low-resolution images. Each frame memory is required for an image of each stage (reduction size). The number of reduction circuits must be the number of stages of the images. In the prior art, therefore, the capacity of a memory for storing images of the respective stages is inevitably increased, and the reduction units for generating reduced images are required in units of stages, thus resulting in a bulky apparatus. Conventional image encoding schemes include an MH scheme for encoding continuity (i.e., a run length) of a monochromatic image, an MR scheme, and an MMR scheme. When a halftone image obtained by a dither method or an error diffusion method is encoded by using such an encoding scheme, the data volume of the encoded image is larger than that of the original image since the halftone image has a short run length. In recent years, an arithmetic encoding scheme (C.C. Langdon and J.J. Rissanen "Compression of Black-White Images with Arithmetic Coding", IEEE Trans. Commun. COM-29, 1981) has received a great deal of attention. This scheme is known as a highly efficient encoding scheme whose encoding efficiency is determined by a probability of occurrence regardless of run lengths of white and black runs. In a conventionally known arithmetic encoding scheme, however, a probability of occurrence of minor symbols in an image to be encoded is required during encoding. For example, an image to be encoded is prescanned to obtain statistical data, and a probability of occurrence of minor symbols must be calculated in correspondence with each image. In a conventional dynamic arithmetic encoding scheme which does not require prescanning, images to be input are sequentially monitored to obtain minor symbols. According to this scheme, however, a predetermined number of pixels are referred to regardless of the size of an image to be encoded. When an image size is small, encoding efficiency is undesirably decreased. More specifically, when the number of reference pixels is large for an image of a small size, the possibility of occurrence of each state is decreased. As a result, encoding is completed before an initial value is converged into an optimal value, thus degrading the encoding efficiency. The present invention has been made in consideration of the above situation, and has as its object to provide a method and apparatus for encoding an image by highly efficient encoding in a simple arrangement. The present invention, as defined in the appended claims, provides a method and apparatus for encoding an image so as to perform encoding in a manner adapted to the size of an image to be encoded. In particular, embodiments of the present invention provide a method and apparatus for encoding an image so as to optimize reference pixels in predictive coding. Embodiments of the present invention provide an apparatus for encoding a hierarchical image in a simple arrangement. The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS : Fig. 1 is a block diagram showing a conventional arrangement for hierarchical encoding of images; Fig. 2 is a block diagram showing a novel arrangement for encoding hierarchical images; Fig. 3 is a block diagram of an image reduction unit; Fig. 4 is a table showing coefficients of a low-pass filter; Fig. 5 is a view for explaining subsampling; Fig. 6, consisting of Figs. 6A and 6B is a flow chart for explaining encoding; Fig. 7 is a flow chart for explaining encoding; Fig. 8 is a view for explaining a noticed pixel to be encoded and its neighboring pixels; Fig. 9 is a view for explaining a reduced pixel; Fig. 10 is a block diagram of an encoder; Fig. 11 is a block diagram showing an arrangement according to an embodiment of the present invention; Fig. 12 is a block diagram of an arrangement using a microprocessor according to the present invention; Fig. 13 is a flow chart for explaining an operation of the embodiment shown in Fig. 12; Fig. 14 is a view showing reference pixel positions; Fig. 15 is a flow chart for explaining dynamic arithmetic encoding processing; and Fig. 16 is a flow chart for renewing major symbol skew values. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS : Preferred embodiments of the present invention will be described with reference to the accompanying drawings. Fig. 2 shows an image encoding apparatus of novel form. This image encoding apparatus includes a frame memory 1 for storing one frame of an original image, an image reduction unit 2 for generating a reduced image, a demultiplexer 3 for distributing reduced images to line memories 4, 5, and 6 in units of rasters, a selector 7 for selecting two of data lines 11, 41, 51 and 61 and outputting the selected data to signal lines 71 and 72, and an encoder 8 for encoding each hierarchical image. The line memories 4, 5, and 6 store a few lines (three lines in this embodiment) of 1/2, 1/4, and 1/8 reduced images, respectively. One frame of an image (original image) to be encoded is input from an image input unit (not shown) to the frame memory 1 through a signal line 12. The original image is input from the frame memory 1 to the image reduction unit 2 through signal lines 13 and 22. At this time, a switch 14 is connected to the signal lines 13 and 22 (the A side in Fig. 2). The image reduction unit 2 is arranged, as shown in Fig. 3. That is, the image reduction unit 2 comprises line memories 21, 22, and 23 each capable of storing three lines of an image, a 3 x 3 low-pass filter 24 for smoothing outputs from the line memories 21, 22, and 23, a comparator 25 for binarizing an output from the low-pass filter 24, and a subsampling unit 26 for extracting a binary output at a predetermined timing. Conveniently, the three line memories 21, 22 and 23 may be incorporated as part of a random access memory under the control of the central processing unit 9. In this manner the different lengths of image lines of the full size and reduced size images may be accommodated using appropriate choices of start and end addresses. Other forms and structure of line memory, as also manner of operation, are not precluded. Fig. 4 shows coefficients of the 3 x 3 low-pass filter 24. The central pixel has a weighting coefficient C (C is a standard value, i.e., 4), and different weighting coefficients shown in Fig. 4 are assigned to the neighboring pixels. If the density of the central pixel is given as D ij (i = 1 to M; j = 1 to N where M and N are image sizes in the horizontal and vertical directions, respectively), an output density W of the filter is given as follows: W = (D i-1′j-1 + 2D i′j-1 + D i+1′j-1 + 2D i-1′j + CD i′j + 2D i+1′j + D i-1′j+1 + 2D i′j+1 + D i+1′j+1 ) The output W from the low-pass filter 24 is binarized with a threshold value T by the comparator 25 shown in Fig. 3. In this case, binary processing is performed as follows: If W > T, then output signal = 1 If W < T, then output signal = 0 The size of the binary output is reduced into 1/2 by the subsampling unit 26 in the vertical and horizontal directions. Fig. 5 is a view for explaining subsampling. Image data indicated by hatched lines are extracted every other line in the main scanning and subscanning directions, and a subsampled image having a 1/2 size (1/4 area) is formed. This can be easily performed by controlling latch timings of the image data. More specifically, as shown in Fig. 5, in order to reduce an image into 1/2 in the main scanning and subscanning directions, a three-line image a is filtered by the 3 x 3 low-pass filter, and a filter output is extracted at a 1/2 rate, thereby subsampling a1, a2, a3, a4,.... A three-line image b in Fig. 5 is filtered by the 3 x 3 low-pass filter, and the low-pass filter output is extracted at a 1/2 rate, thereby subsampling b1, b2, b3, b4,.... In this manner, the image on the same lines ℓ can be commonly used to obtain the outputs a1, a2, a3, a4... and b1, b2, b3, b4.... As described above, the 1/2 reduced image data (binary data) is distributed to the line memories 4, 5, and 6 through the signal line 21 in Fig. 2. When an original image is reduced into a 1/2 image, the resultant 1/2 reduced image is stored in the line memory 4. When a 1/2 reduced image is reduced into a 1/4 image, the resultant 1/4 reduced image is stored in the line memory 5. When a 1/4 reduced image is reduced into a 1/8 image, the resultant 1/8 reduced image is stored in the line memory 6. As described above, each line memory has three memory sections for storing three lines of the corresponding hierarchical image. A CPU 9 controls operations of the respective components in accordance with predetermined procedures. The encoding procedures under the control of the CPU 9 will be described in detail with reference to a flow chart in Fig. 6. Fig. 6 is a flow chart for encoding a 1/8 reduced image. The encoding procedures will be described with numerals indicated on the right-hand side of Fig. 6. 1 ○ Initialization is performed. That is, the line memories 4, 5, and 6 are cleared. 2 ○ The switch 14 is set on the A side. 3 ○ The original image is read out each line from the frame memory 1 to obtain a continuous three-line image. This three-line image is reduced into 1/2 in the vertical and horizontal directions to form a one-line image. This one-line image is written in one of the three memory sections of the line memory 4 through the demultiplexer 3. 4 ○ A second one-line image obtained by reducing an original image into 1/2 is formed as in step 3 ○ and is stored in the line memory 4. This image is written in one of the remaining two memory sections of this line memory 4. On the first pass through this routine following initialization this step is repeated and a third one-line image written into the remaining memory section of this line memory 4. At this point in the routine the line memory 4 now contains three successive lines of the 1/2 reduced image. 5 ○ The switch 14 is set on the B side. 6 ○ The three lines of the 1/2 reduced image stored in the line memory 4 are sequentially supplied to the reducing unit 2 through the selector 7, a signal line 73, and switch 14. The reduction unit 2 forms a one-line image (i.e. a 1/4 reduced image) obtained by reducing the three-line image into 1/2 in the vertical and horizontal directions. The 1/4 reduced image is stored in one of the three memory sections of the line memory 5 through the demultiplexer 3. The above step may be performed as follows: 1. A first-line image is entered from line memory 4 through switch 14 to line memory 23 and is stored therein. 2. A second-line image is entered from line memory 4 through switch 14 into line memory 23, and the first-line image is read out from line memory 23 and is entered into line memory 22. Thus, the second-line image is stored in line memory 23, and the first-line image is stored in line memory 22, respectively. 3. A third-line image is entered from line memory 4 through switch 14 into line memory 23, and the second-line image is entered from line memory 23 into line memory 22 and the first-line image is entered from line memory 22 into line memory 21. Thus, the third-line image is stored in line memory 23, the second-line image is stored in line memory 22, and the first-line image is stored in line memory 21, respectively. 4. The first-line image, the second-line image and the third-line, which are read out from line memories 21, 22 and 23, respectively, are simultaneously entered into low-pass filter 24 to obtain the one-line reduced image. 7 ○ On the first pass through this routine following initialization, steps 2 to 6 are repeated until a further two lines of the 1/4 reduced image are stored in the remaining sections of this line memory 5. On all subsequent passes through this routine, steps 2 ○ to 6 ○ are repeated until a further line of the 1/4 reduced image is stored in the line memory 5 (this 1/4 reduced image line together with the two previous reduced image lines entered constitute three successive lines of the 1/4 reduced image in the line memory 5). 8 ○ The three-line 1/4 reduced image data are read out and further reduced into 1/2 by the image reduction unit 2, thereby forming a 1/8 reduced image line. This 1/8 reduced image line is stored in one of the memory sections of the line memory 6 through the demultiplexer 3. 9 ○ Steps 2 ○ to 8 ○ are repeated until several reference lines required for encoding (two lines in this embodiment) of the 1/8 reduced image are written in the line memory 6. The two lines of the 1/8 reduced image stored in the line memory 6 are supplied to the encoder 8 through the selector 7 and the signal line 71 and are sequentially encoded by the encoder 8. The encoder 8 sequentially encodes the input data with reference to the noticed pixel and its neighboring pixels by an encoding method to be described later. Steps 2 ○ to are repeated until encoding of all lines of the 1/8 reduced image is completed. Encoding of the entire 1/8 reduced image is completed. The above description has been made for encoding of the 1/8 reduced image. Encoding of 1/4 and 1/2 reduced images and an original image will be described with reference to Fig. 7. Encoding of the 1/4 reduced image is started when a connector A ○ the flow chart of Fig. 6 is shifted to a flow chart of Fig. 7. Encoding of the 1/2 reduced image is started when a connector B ○ of the flow chart of Fig. 6 is shifted to the flow chart of Fig. 7. Encoding of the original image is started when a connector © of the flow chart of Fig. 6 is shifted to the flow chart of Fig. 7. In any of these cases, a noticed pixel of an image to be encoded is centered, and the encoder 8 encodes the input data with reference to two lines of the image to be encoded and one line (the same line as that including the noticed pixel) of the 1/2 reduced image of the image to be encoded. An encoding method will be described later. Encoding of the reduced images (1/2 and 1/4 reduced images) and the original image will be commonly described with reference to Fig. 7 by using numerals written on the right-hand side in Fig. 7. An image of a line including the noticed pixel of the image to be encoded and an image of the previous line are sequentially read out and supplied to the encoder 8 through the selector 7 and the signal line 71. The original image to be encoded is read out from the frame memory, whereas the 1/2 and 1/4 reduced images to be encoded are read out from the line memories 41 and 51, respectively. An image of one line (the same line as that including the noticed pixel to be encoded) of the 1/2 reduced image of the image to be encoded is read out from one of the 4, 5, and 6 and is supplied to the encoder 8 through the signal line 72. The encoder 8 encodes the input data with reference to the two lines including the noticed pixel to be encoded and one line (the same line as that including the noticed pixel) of the reduced image. Steps between the connector ® and step are repeated to terminate encoding of all pixels of the image to be encoded. The above description has been made for the flows of encoding of the original image, the 1/2 reduced image, and the 1/4 reduced image. Encoding performed by the encoder 8 shown in Fig. 2 will be described below. Arithmetic encoding is used as an encoding scheme in this embodiment. In this embodiment, a value of a noticed pixel is predicted from the neighboring pixels, a predicted pixel symbol is given as a major symbol, and other symbols are given as minor symbols. A probability of occurrence of the minor symbols is given as p , and encoding is performed on the basis of this probability. If binary arithmetic codes and auxiliary amounts for a code series s are defined as C(s) and A(s), respectively, they are given as: A(s1) = A(s).P(s) = A(s).2 -Q(s) A(s0) = A(s) - A(s1) C(s1) = C(s) + A(s0) C(s0) = C(s) for A(null) = 0.11...1 Encoding is performed by the above arithmetic calculations. p(s) = 2 -Q(s) is approximated to perform multiplications by only binary shifting. In the above equations, Q is called as a skew value. Major and minor symbols used for prediction, and the skew value Q must be predetermined for all reference pixels from a reference image. Decoding is based on a binary signal train s = s′xs″. When decoding is completed up to s′, C(s) is compared with C(s′)+A(s′0). If C(s) > (C(s′)+A(s′0), then x = 1. Otherwise, x = 0. Fig. 8 shows neighboring reference pixels 1 to 5 of a noticed pixel (*) to be encoded in this embodiment. The noticed pixel is predicted in accordance with states of these reference pixels. Fig. 9 shows pixel 6 obtained at the same position by reducing the pixels including the noticed pixel into 1/2. In encoding of the 1/8 reduced image, the noticed pixel is predicted by the five neighboring pixels (1 to 5), and encoding is performed by the arithmetic calculations described above. In encoding of the original image, the 1/2 reduced image, and the 1/4 reduced image, the noticed pixels are predicted by the neighboring pixels (1 to 5 in Fig. 8) of the noticed pixel to be encoded, the pixel (6 in Fig. 9) located at the same position as the noticed pixel to be encoded, and the positional relationship (four states determined by the positions of the noticed pixel in the dotted areas in Fig. 9) between the noticed pixel and the reduced pixel. Thereafter, encoding is performed by the arithmetic calculations described above. Fig. 10 shows a noticed pixel predicting circuit and an arithmetic encoding circuit. Line memories 910 and 920 store two-line images including the noticed pixel. A line memory 930 stores a one-line image obtained by reducing the image to be encoded. Signal lines 71 and 72 are the same as those in Fig. 2. A pixel clock 1 is a raster clock, and a clock 2 is a line clock. Latches 911, 912, 913, 914, 921, and 922 store neighboring pixels of a noticed pixel, and the noticed pixel, respectively. The reference numerals and symbols as in Fig. 7 denote the same parts in Fig. 10. Clocks 1/21 and 1/22 are raster and line clocks of the reduced image, respectively, and have a 1/2 clock speed of the clocks 1 and 2. A latch 931 stores a reduced pixel (Fig. 9) located at the same position as that of the noticed pixel. The numeral in the latch 931 corresponds to the numeral in Fig. 9. A look-up table (LUT) 940 trains a reference image or the like to store a skew value Q941 and a minor symbol ℓ 942 in each neighboring pixel state. Data of the latches 911, 912, 913, 914, and 921 for storing the neighboring pixels and data from the latch 931 for storing the reduced image are input to the LUT 940. Since the positional relationship between the' reduced pixel and the noticed pixel is determined by two bits, i.e., the clocks 1 and 2, this two-bit data is also input to the LUT 940. The LUT 940 outputs to an arithmetic encoding circuit 970 skew values Q941 and the minor symbols ℓ 942 which correspond to a plurality of neighboring pixel states defined by combinations of a plurality of inputs. In the case of the 1/8 reduced image, since a further reduced image (i.e., a 1/16 reduced image) is not present, the content of the latch 931 is set to be always zero. The LPS signal ℓ 942 from the LUT 940 and the noticed pixel 922 are exclusively ORed by an exclusive OR gate 960 to obtain an MPS/ LPS signal 961. The signal 961 represents that the major pixel is a major symbol when it is set at "1". However, when the signal 961 is set at "0", it represents a minor symbol. The arithmetic encoding circuit 970 performs the arithmetic operations given by equation (1) using the skew values Q941 and the MPS/ LPS signals 961. In this arrangement, the low-pass filter and subsampling are used to generate a reduced image. However, even if another reducing scheme is used, a similar arrangement can be used. Arithmetic encoding is used as an encoding scheme. However, a Markov code may be used in place of a Huffman code or the like to obtain the same effect as described above. As described above, reducing processing in hierarchical encoding can be commonly used for all stages, and the apparatus can be made compact. In addition, hierarchical encoding can be performed by using only line buffers each having a capacity of a few lines as hierarchical image memories. In the encoder 8 shown in Fig. 2, the pixels 1 to 5 at positions shown in Fig. 8 are always used as encoding reference pixels. Encoding efficiency can be improved when reference pixel positions and the number of reference pixels are changed in accordance with an image size as in an embodiment described below. Pixels necessary as the reference pixels are extracted from an image included in a line including a noticed pixel and two previous lines thereof. Fig. 11 is a block diagram of an image processing apparatus according to an embodiment of the present invention. In the image processing apparatus, an input unit 81 receives image data from a reader having an image sensor such as a CCD to photoelectrically read an original image. An image size input unit 82 receives a size (data volume) of an image on the basis of an operation of a size input key or an output from a size detection sensor. A reference pixel determination unit 83 determines the number of reference pixels by an image size value input from the image size input unit 82. A state discrimination unit 84 discriminates a state of an input image when the input image is assumed to be a Markov model. An arithmetic encoding unit 85 performs arithmetic encoding of image data. A memory 86 stores discrimination state data and encoded data. An output unit 87 outputs encoded data. Fig. 12 shows an arrangement wherein the reference pixel determination unit 83, the state discrimination unit 84, and the arithmetic encoding circuit 85 in Fig. 11 are realized by a microprocessor. An input unit 88 corresponds to the input unit 81 shown in Fig. 11. A ROM 89 stores an encoding program for image data. A CPU 90 includes a microprocessor as its major component and processes signals from the input unit 88 in accordance with the program stored in the ROM 89. A RAM 91 stores data processed by the CPU 90. An output unit 92 corresponds to the output unit 87 (Fig. 11) for outputting the data processed by the CPU 92 as encoded data. An input unit 93 corresponds to the input unit 82 shown in Fig. 11. Processing performed by the reference pixel determination unit 83, the state discrimination unit 84, and the arithmetic encoding unit 85 in Fig. 11 is performed by the CPU 90. Fig. 13 is a flow chart showing a control sequence of the CPU 90 shown in Fig. 12. When the program starts to run, data representing a size of an image to be encoded is input from the input unit 93 in step S1. The CPU 90 determines the number of reference pixels as in Table 1 in response to the input image size (the number of pixels) in step S2. For example, when the number of all pixels is 100,000, the number of reference pixels is seven. In this case, pixels numbered as 1 to 7 shown in Fig. 14 are referred to. A noticed pixel is represented by *. Image Size (Number of All Pixels) Number of Reference Pixels 64152 or less 4 pixels 64153 - 256608 7 pixels 256609 - 1026432 12 pixels 1026433 - 4105728 16 pixels In step S3, the major symbol (MPS) and the skew value (Q) of arithmetic encoding, a two-pixel counter CN, a minor symbol counter LCN, and a major interval counter CNL are initialized. For example, if seven pixels serve as reference pixels, the number of combinations of states of the seven pixels is 2 7 . Each of the number of major symbols and the number of skew values is 2 7 corresponding to the states. The 2 7 major symbols, the 2 7 skew values, the two-pixel counter, the minor symbol counter, and the major interval counter are defined as MPSt, Qt, CNt, LCNt, and CNLt (t = 0, 1,... 127), respectively. In step S4, image data is input from the input unit 88. In step S5, the states are classified into 128 (= 2 7 ) states with reference to the reference pixels already determined for a noticed pixel x(i,j). A method of classifying the states is performed on the basis of an assumption that a value of a dotted pixel value is given as 1, and a value of a nondotted pixel value is given as 0. A state St of the noticed pixel x(i,j) is represented by the following value: St = x(i-1,j) + 2 1 ·x(i, j-1) + 2 2 ·x(i+1,j-1) + 2 3 ·x(i-1,j-1) + 2 4 ·x(i-2,j-1) + 2 5 ·x(i-1,j-2) + 2 6 ·x(i+1,j-2) Similarly, if the number of reference pixels is 16, the following equation can be obtained: St = x(i-1,j) + 2·x(i,j-1) +... + 2 15 ·x(i-3,j-1) In step S6, the noticed pixel is arithmetically encoded using the data MPSt and Qt corresponding to the classified states, and the encoded data are stored in the RAM 91. If the data MPSt and Qt must be renewed, these values are renewed. In this manner, the input pixel data are sequentially encoded. The CPU 90 determines in step S7 that all image data (e.g., one-frame image data) are encoded. If NO in step S7, the next pixel is input to repeat the state classification and arithmetic encoding. If YES in step S7, the encoded data stored in the RAM 91 are output to the output unit 92, thereby completing the processing. At this time, if the data representing the number of reference pixels and the reference pixel positions are added as header data, the encoded data can be uniquely decoded. Fig. 15 is a detailed flow chart of a dynamic arithmetic encoding operation in step S6 of Fig. 13. In this embodiment, as described above, the value of the noticed pixel is predicted from the neighboring pixels determined in accordance with the image size. The predicted pixel symbol is given as the major symbol MPSt, and other symbols are defined as minor symbols. At the same time, the probability of occurrence of the minor symbols is given as Pt, and encoding is performed on the basis of this data. More specifically, if the binary arithmetic code and an auxiliary amount for a code series 5 are given as C(S) and A(S), respectively, A(S1) = A(S)·P(S) = A(S)·2 -Q(s) A(S0) = A(S) - A(S1) According to whether the noticed pixel is a major symbol, C(S1) = C(S) + A(S0) C(S0) = C(S) For A(null) = 0, 11...1. As described above, encoding is performed by arithmetic calculations. P(S) = 2 -Q(s) is approximated to perform multiplications by only binary shifting. The parameter Q is called a skew value. When this parameter is changed in accordance with states of reference pixels, arithmetic encoding can be dynamic. In step S11, equations (A) are set. The CPU 90 determines in step S12 whether the noticed pixel determined by the reference pixels has the same value as that of the major symbol MPSt. If YES in step S12, C(SO) ← C(S) is performed in step S13. If NO in step S12, i.e., when the noticed pixel is determined to represent a minor symbol, C(S1) ← C(S) + A(S0) is performed. In this case, the minor symbol counter LCNt is decremented by only one The CPU 90 determines in step S15 whether the count of the two-pixel counter CNt corresponding to the current pixel state is 2. If YES in step S15, MPSt and Qt corresponding to this pixel state are renewed in step S16. If CNt is 1, it is renewed to 2. Therefore, the skew value Qt and the major symbol MPSt corresponding to the pixel state t are dynamically updated on the basis of the previously encoded data every time the same pixel state is generated twice. Decoding of the encoded data is based on a binary signal train S = S′xS″. When decoding is completed up to S′, C(S) is compared with C(S′)+A(S′0). If C(S) > C(S′), then x = 1. Otherwise, x = 0. Fig. 16 is a detailed flow chart of renewal processing of MPSt and Qt in step S16 of Fig. 15. In step S21, when the same pixel state is generated twice and generation of a pixel corresponding to the minor symbol is zero times, the major interval counter CNLt representing the number of times of occurrence of only the major symbols is incremented by one in step S22. One is substituted into the minor symbol counter LCNt for subsequent calculations. If the number of times of occurrence of the minor symbol is one or two, the flow advances from step S26 to steps S27 and S28 to perform calculations CNLt ← [3·CNLT/4]+1 and CNLt ← [CNLt/2]+1 where symbol [] is a Gaussian symbol and represents a maximum integer equal to or smaller than numeric values within the Gaussian symbol. The calculation results are substituted in the counter CNLt. The CPU 90 determines in step S29 whether the CNLt is one. If YES in step S29, this indicates a boundary beyond which a probability of generating a minor symbol is higher than a probability of generating a major symbol in this pixel state t . In step S30, therefore, the MPSt corresponding to this pixel state t is inverted (i.e., if the state is "1", then it is inverted into "0"; and vice versa). In step S23, a calculation [-log 2 {LCNt/(2·(CNLt + 1))}] is performed using LCNt and CNLt to obtain a probability of occurrence of minor symbols in this pixel state. The resultant probability is substituted into Qt. When Qt exceeds one in steps S24 and S31; Qt is renewed to one. In step S25, the minor symbol counter LCNt is returned to zero, and the two-pixel counter CNt is reset to one. When dynamic encoding is performed as described above, a considerable number of symbols are required to converge the value of Qt. In this case, the number of reference pixels is determined in accordance with an image size, and therefore, the number of symbols classified into one state can be sufficiently increased, thereby improving encoding efficiency. As a method of performing dynamic encoding at high speed, the calculation (step S23 of Fig. 6) given as follows: [-log 2 {LCNt/(2·(CNLt+1))}] is performed in advance, and the calculation results are stored in the form of a table, thereby easily obtaining a hardware arrangement. The present invention is applicable not only to image data read by a reader but also to output data such as an image data base. In this case, since the image size is often included in the header data, the header data can be used for an image size input. In addition, when binary image attributes (e.g., data which discriminates a halftone image from a character image) are input, and pixel positions and the numbers of pixels which correspond to the respective attributes are referred to, encoding efficiency is improved. As described above, the reference pixel positions and the number of reference pixels are changed in accordance with different image sizes, and the number of symbols assigned to the respective states can be sufficiently increased. Therefore, the skew values Q can be satisfactorily converged in the respective states, and encoding efficiency can be improved. The present invention has been described with reference to the preferred embodiments. However, the present invention is not limited to these embodiments. Various changes and modifications may be made within the scope of the appended claims.

Claims: A method for encoding an image, comprising the steps of: inputting pixels of an image to be encoded; determining for each pixel of interest a set of reference pixels such that the number of reference pixels and/or their positions depend upon the size of the input image; predicting a status of each pixel of interest using the determined set of reference pixels; and encoding the pixel of interest by comparing an actual status of the pixel with the predicted status. A method according to claim 1, wherein said step of encoding the pixel of interest comprises the step of setting encoding parameters in accordance with states of the reference pixels in the image to be encoded. A method according to claim 1 or 2, wherein said step of predicting the status comprises the step of predicting a symbol of the pixel of interest. A method according to claim 1, 2 or 3, wherein said step of encoding the pixel of interest comprises the step of encoding the pixel by arithmetic encoding. A method according to any preceding claim, wherein the number of reference pixels and/or their positions further depends upon whether the image is a half-tone image or a character image. An apparatus for encoding an image, comprising: means for inputting pixels of an image to be encoded; means for determining for each pixel of interest a set of reference pixels such that the number of reference pixels and/or their positions depends upon the size of the image input from said inputting means; means for predicting a status of each pixel of interest using the determined set of reference pixels; and means for encoding the pixel of interest by comparing an actual status of the pixel with the status predicted by said predicting means. An apparatus according to claim 6, wherein said encoding means comprises means for setting encoding parameters in accordance with states of the reference pixels. An apparatus according to claim 6 or 7, wherein said predicting means predicts a symbol of the pixel of interest. An apparatus according to claim 6, 7 or 8, wherein said encoding means encodes the pixel of interest by arithmetic encoding. An apparatus according to claim 6, 7, 8 or 9, wherein the number of reference pixels and/or their positions further depend upon whether the image is a half-tone image or a character image.

Inventors: HIRABAYASHI YASUJI, KATAYAMA AKIHIRO, MAEDA MITSURU, YOSHIDA TADASHI, HIRABAYASHI, YASUJI, KATAYAMA, AKIHIRO, MAEDA, MITSURU, YOSHIDA, TADASHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1989
Main classification: H04N1
IPC codes: H04N1, G06T9