Electronically corrected electronic timepiece

Abstract: An electronically corrected electronic timepiece is provided which comprises a step motor, an external opera­ ting means, a correction signal forming circuit, and a control means for continuously correcting time-of-day, alarm setting time, setting time period of a timer, reference positions of hands (11,12,14,21,31,38,39), or the like in an electronical manner by actuating the external operating means (22-26). The correction signal forming circuit functions to increase or decrease a speed of driving the hands during the continuous correction. With the correction performed at the accelerated speed, the present timepiece has the capability of easy and quick electronic correc­ tion.

Description: BACKGROUND OF THE INVENTION The present invention relates to a technique for electronically correcting an electronic timepiece (watch and clock). As a conventional method of continuous electronic correction for electronically corrected electronic timepieces of the analog display type, hands or pointers have generally been driven at a constant speed by continuously actuating press button switches. However, because the hands are driven at a constant speed for correction, the conventional method of electronic correction has disadvantages that difficulty is experienced in stopping the hands at the intended positions exactly if the correction speed is set to be faster, and it takes a lot of time to drive the hands for correction when the intended positions of the hands are far from the start positions, if the correction speed is set to be slower. An electronically corrected electronic timepiece according to the prior art portion of claim 1 is disclosed in the document GB-A-2 079 012. This prior art includes a frequency divider comprising four divider stages dividing by 512, 4, 8 and 30, respectively. The frequency divider stages are connected in cascade to produce a 1/15 Hz signal, a 2 Hz signal, a 16 Hz signal and a 64 Hz signal. If the speed for moving the hands in the time correction mode is changed based on these signals, changing from 2 Hz to 16 Hz means increasing the speed of the hands by a factor of 8 and increasing from 16 Hz to 64 Hz means increasing the speed by a factor if 4, i.e. the speed of the hand increases quite rapidly. An analog timepiece having incorporated a digital display function is disclosed in the document US-A-4,444,513. The document EP-A-0 059 164 discloses a multifunction time-piece wherein the second hand can be used to display information other than the seconds. It is an object of the present invention to provide an electronically corrected electronic timepiece of the analog representation type allowing to stepwisely increase or decrease the speed of driving the hands in the process of continuous correction such as to achieve a smooth change of speed. This object is achieved with an electronic timepiece as claimed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of CMOS-IC20 for use in an electronically corrected electronic timepiece of the present invention: Fig. 2 is a sectional view of train wheels for the hour and minute indication of normal 12-hour time: Fig. 3 is a sectional view of train wheels for the second indication of normal 12-hour time: Fig. 4 is a sectional view of train wheels for the indication of chronograph second: Fig. 5 is a sectional view of train wheels for the minute indication of chronograph and timer second: Fig. 6 is a sectional view of train wheels for the indication of alarm setting time: Fig. 7 is an external appearance view of a completed electronic timepiece of the first embodiment; Fig. 8 is a circuit diagram of an embodiment of Fig. 9; Fig. 9 is a plan view showing the embodiment of the electronic timepiece of the present invention; Fig. 10 is a block diagram showing a practical configuration example of a chronograph circuit 211 in Fig. 1; Fig. 11 is a block diagram showing a practical configuration example of a motor hand-drive control circuit 212 in Fig. 1; Figs. 12, 13, 14 and 15 are timing charts of motor drive pulses Pa, Pb, Pc, Pd output from a 1st drive pulse forming circuit 221, a 2nd drive pulse forming circuit 222, a 3rd drive pulse forming circuit 223, and a 4th drive pulse forming circuit 224 in Fig. 11, respectively; Fig. 16 is a block diagram showing a practical configuration of motor clock control circuits 226, 227, 228 and 229 in Fig. 1; Fig. 17 is a block diagram showing a practical configuration of a hand-drive standard signal forming circuit 220 in Fig. 1; Fig. 18 is a flowchart for the indication of normal 12-hour time; Fig. 19 is a flowchart for a chronographic function; Fig. 20 is a flowchart for a timer function; Fig. 21 is a flowchart for an alarm setting function; Fig. 22 is a flowchart for a hand-drive process of the motor; Fig. 23 is a flowchart showing a 0-position corrector function of a CG 1/5 second hand; Figs. 24 is a table showing patterns for correction at an accelerated speed; Fig. 25 is a view of another embodiment showing those components added to the first embodiment; Fig. 26 is a graph showing the relationship between the correction time and the hand-drive speed in accelerated correction with forward drive according to the first embodiment; Fig. 27 is a block diagram showing an example in which the present invention is applied to an electronic analog timepiece; Fig. 28 is a time chart representing an switch input at K2 and an output signal at SA in a correction signal forming circuit 316 in Fig. 27; and Fig. 29 is a circuit diagram of the correction signal forming circuit. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Preferred embodiments of an electronically corrected electronical timepiece of the present invention will be described hereinafter. Fig. 9 is a plan view showing one embodiment of a electronically corrected electronic timepiece of the present invention. In this embodiment, the timepiece employs four step motors. Designated at reference numeral 1 is a main plate formed through resin molding, and 2 is a battery. 3 is a step motor A for giving the indication of normal 12-hour time (time-of-day). The step motor A comprises a coil core 3a of a high permeability material, a coil block 3b which is made up by a coil wound around the coil core 3a, a coil lead substrate having its opposite ends subjected to terminal processing for electric conduction and a coil frame, a stator 3c of a high permeability material, and a rotor 4 which is made up by a rotor magnet and a rotor pinion. 5, 6, 7, 8 are 5th, 4th, 3rd and 2nd wheels, respectively. Then, 9 is a minute wheel and 10 is an hour wheel. The 2nd wheel and the hour wheel are positioned at the center of a movement of the timepiece. With the above train wheel arrangement, the minute and hour indication of normal 12-hour time is given at the center of the movement. Fig. 2 is a sectional view showing the manner in which those train wheels for the hour and minute indication of normal 12-hour time are meshed with each other. As illustrated in Fig. 2, the rotor pinion 4a is in mesh with a 5th gear 5a and a 5th pinion 5b is in turn in mesh with a 4th gear 6a. A 4th pinion 6b is in mesh with a 3rd gear 7a and a 3rd pinion 7b is in turn in mesh a the 2nd gear 8a. The speed reducing ratio realized through the train wheels from the rotor pinion 4a to the 2nd gear 8a is selected to be 1/1800. Thus, when the rotor 4 is rotated to make half a turn per second, the second gear 8a is rotated once per 3600 seconds, i.e., 60 minutes, thereby enabling the minute indication of normal 12-hour time. 11 is a minute hand fitted over a distal end of the 2nd wheel 8 for the minute indication. Furthermore, a 2nd pinion 8b is in mesh with a minute gear 9a, and a minute pinion 9b is in turn in mesh with the hour wheel 10. The speed reducing ratio realized through the 2nd pinion 8b to the hour wheel 10 is selected to be 1/12 for enabling the hour indication of normal 12-hour time. 12 is an hour hand fitted over a distal end of the hour wheel 10 for the hour indication. In Fig. 9, 13 is a small second wheel disposed on a spindle located in the direction of 9 o'clock in the movement. With the train wheel arrangement of the rotor 4, the 5th wheel 5 and the small second wheel 13, the second indication of normal 12-hour time is given on the spindle located in the direction of 9 o'clock in the movement. Fig. 3 is a sectional view showing the manner in which those train wheels for the second indication of normal 12-hour time are meshed with each other. As illustrated in Fig. 3, the 5th pinion 5b is in mesh with a small second gear 13a. The speed reducing ratio realized through the train wheels from the rotor pinion 4a to the small second gear 13a is selected to be 1/30. Thus, when the rotor 4 is rotated through 180° per second, the small second wheel makes a full turn for every 60 seconds, i.e., it is rotated through 6° per one second, thereby enabling the second indication of normal 12-hour time. 14 is a small second hand fitted over a distal end of the small second wheel 13 for the second indication. In Fig. 9, designated at 15 is a step motor B for giving the indication of chronograph (CG) second. The step motor B comprises a coil core 15a of a high permeability material, a coil block 15b which is made up by a coil wound around the coil core 15a, a coil lead substrate having its opposite ends subjected to terminal processing for electric conduction and a coil frame, a stator 15c of a high permeability material, and a rotor 16 which is made up by a rotor magnet and a rotor pinion. 17, 18, 19 are a 1/5 second CG 1st intermediate wheel, a 1/5 second CG 2nd intermediate wheel, and a 1/5 second CG wheel, respectively. The 1/5 second CG wheel 19 is positioned at the center of the movement. With the above train wheel arrangement, the indication of chronograph second is given at the center of the movement. Fig. 4 is a sectional view showing the manner in which those train wheels for the indication of chronograph second are meshed with each other. As illustrated in Fig. 4, the rotor pinion 16a is in mesh with a 1/5 second CG 1st intermediate gear 17a and a 1/5 second CG 1st intermediate pinion 17b is in turn in mesh with a 1/5 second CG 2nd intermediate gear 18a. A 1/5 second CG 2nd intermediate pinion 18b is in mesh with a 1/5 second CG gear 19a. The speed reducing ratio realized through the train wheels from the rotor pinion 16a to the 1/5 second CG gear 19a is selected to be 1/150. An electric signal from CMOS-IC20 causes the rotor 16 to be rotated through 180° per 1/5 second. Therefore, the 1/5 second CG wheel 19 is rotated through 1.2° per 1/5 second, i.e., it makes a rotation of 1.2° x 5 steps per one second, thereby enabling the indication of chronograph second in units of 1/5 second. 21 is a 1/5 second CG hand fitted over a distal end of the 1/5 second CG wheel for the indication of chronograph second. The 1/5 second CG hand 21 serves as also a timer setter hand for setting a timer time. The timer operation will be explained later. Designated at 27 is a step motor C for giving the minute indication of chronograph and the second indication of the timer elapsed time. The step motor C comprises a coil core 27a of a high permeability material, a coil block 27b which is made up by a coil wound around the coil core 27a, a coil lead substrate having its opposite ends subjected to terminal processing for electric conduction and a coil frame, a stator 27c of a high permeability material, and a rotor 28 which is made up by a rotor magnet and a rotor pinion. 29, 30 are a minute CG intermediate gear and a minute CG wheel, respectively, the minute CG wheel 30 being disposed on a spindle located in the direction of 12 o'clock in the movement. With the above train wheel arrangement, both the minute indication of chronograph and the second indication of the timer elapsed time are given on the spindle located in the direction of 12 o'clock in the movement. Fig. 5 is a sectional view showing the manner in which those train wheels for the minute indication of chronograph and the second indication of the timer elapsed time are meshed with each other. As illustrated in Fig. 5, the rotor pinion 28a is in mesh with a minute CG intermediate gear 29a and a minute CG intermediate pinion 29b is in turn in mesh with a minute CG gear 30a. The speed reducing ratio realized through the train wheels from the rotor pinion 28a to the minute CG gear 30a is selected to be 1/30. In case of a chronograph mode, an electric signal from CMOS-IC20 causes the rotor 28 to be rotated through 360° per one minute, i.e., 180° x 2 steps. Therefore, the minute CG wheel 30 is rotated at a rate of 12° per one minute, i.e., it makes a rotation of 360° (12° x 30 steps) per 30 minutes, thereby enabling the minute indication of chronograph over 30 minutes. 31 is a minute CG hand fitted over a distal end of the minute CG wheel for the minute indication of chronograph. The combination of the minute CG hand 31 and the aforementioned 1/5 second CG hand 21 permits the chronograph indication in units of 1/5 second at minimum readout and over 30 minutes at maximum range. In case of a timer mode, an electric signal from CMOS-IC20 causes the rotor 28 to be rotated in the direction opposite to that in a chronograph mode. This rotation advances 180° x 1 step per one second so that the minute CG hand 31 is rotated counterclockwise in units of one second, thereby giving the second indication of the timer elapsed time on the basis of 60 seconds per one turn. At this time, an electric signal from CMOS-IC20 causes the rotor 16 to be rotated in the direction opposite to a chronograph mode through 180° x 5 steps per one minute. Therefore, the 1/5 second CG hand 21 is rotated counterclockwise at a rate of 6° per one minute, thereby giving the minute indication of the timer elapsed time. The timer setting time is adjusted as follows. In the state where a 2nd winding stem 23 in Fig. 9 is held at its 1st step, each push of a B switch 25 rotates the rotor 16 through 180° x 5 steps and the 1/5 second CG hand 21 in units of 6° (i.e., in units of one minute on the dial). Then, the timer setting time up to 60 minutes can be indicated at maximum. Designated at 32 in Fig. 9 is a step motor D for giving the indication of an alarm (AL) setting time. The step motor D comprises a coil core 32a of a high permeability material, a coil block 32b which is made up by a coil wound around the coil core 32a, a coil lead substrate having its opposite ends subjected to terminal processing for electric conduction and a coil frame, a stator 32c of a high permeability material, and a rotor 28 which is made up by a rotor magnet and a rotor pinion. 34, 35, 36, 37 are a an AL intermediate wheel, an AL center minute wheel, an AL minute wheel, and an AL hour wheel, respectively. The AL center minute wheel 35 and the AL hour wheel 37 are disposed on a spindle located in the direction of 6 o'clock in the movement. With the above train wheel arrangement, the indication of the alarm setting time is given on the spindle located in the direction of 6 o'clock in the movement. Fig. 6 is a sectional view showing the manner in which those train wheels for the indication of the alarm setting time are meshed with each other. As illustrated in Fig. 6, the rotor pinion 33a is in mesh with an AL intermediate gear 34a and an AL intermediate pinion 34b is in turn in mesh with an AL center minute gear 35a. An AL center minute pinion 35b is in mesh with an AL minute gear 36a and an AL minute pinion 36b is in turn in mesh with the AL hour wheel 37. The speed reducing ratio realized through the train wheels from the rotor pinion 33a to the AL center minute gear 35a is selected to be 1/30, while the speed reducing ratio realized through the train wheels from the AL center minute pinion 35b to the AL hour gear 37 is selected to be 1/12. Further, 38 is an AL minute hand fitted over a distal end of the AL center minute wheel 35, and 39 and is an AL hour hand fitted over a distal end of the AL hour wheel 37. Setting a 2nd winding stem 23 (Figs.7,9) to its 1st step brings about an alarm-on mode in which an electric signal from CMOS-IC20 causes the rotor 33 to be rotated through 180° for each push of a C switch 26 (Fig.8). Correspondingly, the AL minute hand 38 is rotated through 6° (one minute on the dial) and the AL hour hand 39 through 0.5°. Therefore, the alarm time can be set up to 12 hours at minimum in units of one minute. At this time, by continuing to push the C switch 26, the AL minute hand 38 and the AL hour hand 39 are allowed to continuously run at an accelerated speed, so that the alarm time may be set in a short time. Upon identity between the alarm setting time and the indicated normal 12-hour time, an alarm sound is produced. When the 2nd winding stem 23 is set to its 0th step, an alarm-off mode is set in which the AL minute hand 38 and the AL hour hand 39 indicate the normal 12-hour time. In this case, an electric signal from CMOS-IC20 causes the rotor 33 to be rotated through 180° per one minute. Accordingly, the AL minute hand 38 is driven in units of minute. Besides, in this embodiment, because the control means has no implement to know absolute positions of the hands, manual operation for moving the hands to their reference position (hereinafter referred to as 0-position correction) is required to return the CG 1/5 second hand 21 and the minute CG hand 31 to the 12 o'clock position when the chronograph and the timer are reset for instance after replacing the battery by new one. The 0-position correction of the CG 1/5 second hand 21 is carried out in the forward direction by the A switch 24 and in the backward direction by the B switch 25 with the 1st winding stem set to its 2nd step. The 0-position correction of the minute CG hand 31 in carried out in the forward direction by the A switch 24 and in the backward direction by the B switch 25 with the 1st winding stem set to its 1st step. Next, circuit configuration of the electronically corrected electronic timepiece of the present invention will be described. Fig. 8 shows a circuit diagram between CMOS-IC20 and other electric elements. In Fig. 8, designated at 2 is a silver oxide cell (SR927W), 3b is the coil block for the step motor A, 15b is the coil block for the step motor B, 24 is the A switch, 25 is the B switch, 26 is the C switch, 27b is the coil block for the step motor C, 32b is the coil block for the step motor D, 55 and 56 are elements for energizing a buzzer, i.e., 55 is a booster coil and 56 is a mini-molded transistor with a protector diode, 57 is a chip capacitor of 0.1 µ F for suppressing voltage fluctuations of a constant-voltage circuit built in CMOS-IC20, 58 is a microcrystal oscillator of the tuning fork type as a source for an oscillator circuit built in CMOS-IC20, 46a is a switch formed in a portion of a yoke 46, 59a is a switch formed in a portion of a 2nd setting lever, and 64 is a piezoelectric buzzer bonded to a back, though not shown in Fig. 9, of the timepiece case. Note that the switches 24, 25, 26 are all switches of the push button type that allow a user to apply an input therethrough only when they are pushed. The switch 46a is a switch in cooperation with the 1st winding stem 22, and arranged such that it closes an RA1 terminal with the 1st winding stem 22 set to its 1st step, closes an RA2 terminal with the stem 22 set to its 2nd step, and is opened with the stem 22 set at a normal position. Furthermore, the switch 59a is a switch in cooperation with the 2nd winding stem 23, and arranged such that it closes an RB1 terminal with the 2nd winding stem 23 set to its 1st step, closes an RB2 terminal with the stem 23 set to its 2nd step, and is opened with the stem 23 set at a normal position. Fig. 1 shows a block diagram of CMOS-IC20 employed in this embodiment. As illustrated in Fig. 1, CMOS-IC20 is a one-chip microcomputer for an analog electronic timepiece, in which a program memory, a data memory, four motor drivers, a motor drive control circuit, a sound generator, an interrupt control circuit, etc. are integrated on one chip with a core CPU at the center. The description will be made below in connection with Fig. 1. Designated at 201 is a core CPU which comprises an ALU, a register for operation, an address control register, a stack pointer, an instruction register, an instruction decoder, etc. The core CPU 201 is connected to peripheral circuits through address buses (adbus) and data buses (dbus) based on the memory mapped I/O technique. 202 is a program memory comprising a mask ROM of 2048 words x 12 bits configuration which stores therein a software for operating the IC. 203 is an address decoder for the program memory 202. 204 is a data memory comprising a RAM of 112 words x 4 bits configuration which is used such as a timer for various types of time counting and as a counter for storing therein positions of the respective hands. 205 is an address decoder for the data memory 204. 206 is an oscillator circuit which includes as a source a crystal oscillator of the tuning fork type connected to Xin and Xout terminals, and oscillates at the frequency of 32768 Hz. 207 is an oscillation stop detector circuit which detects the event that the oscillation of the oscillator circuit 206 has stopped, and then resets the system. 208 is a 1st frequency divider circuit which successively divides a signal  32K of 32768 Hz output from the oscillator circuit 206, and delivers a signal  16 of 16 Hz. 209 is a 2nd frequency divider circuit which successively divides the signal  16 of 16 Hz output from the 1st frequency divider circuit 208 into a signal  1 of 1 Hz. Note that the status of respective frequency divider stages in a range of from 8 Hz to 1 Hz can be read into the core CPU 201 under control of the software. Furthermore, in the IC of this embodiment, the signal  16 of 16 Hz, the signal  8 of 8 Hz and the signal  1 of 1 Hz are used as a time interrupt Tint for processing such as time counting. The time interrupt Tint occurs upon a falling edge of each signal. Read, resetting and masking of respective interrupt factors are all carried out under control of the software such that resetting and masking can individually be effected for each of the interrupt factors. 210 is a sound generator which forms a buzzer drive signal and outputs the latter to an AL terminal. The driver frequency, ON/OFF and sound patterns of the buzzer drive signal can be controlled by the software. 211 is a chronograph circuit which is practically constituted as shown in Fig. 10. A 1/100 second chronograph 211 is arranged using the hardware to control hand drive of a 1/100 second hand, which can greatly reduce the burden exerted on the software. In Fig. 10, 2111 is a clock forming circuit which generates from the signal  512 of 512 Hz both a signal  100 of 100 Hz as a reference clock for chronographic time counting and clock pulses Pfc of 100 Hz and 3.91 ms pulse width which are employed to form 1/100 second hand-drive pulses Pf. 2112 is a 1/50 based chronograph counter which counts the signal  100 having passed an AND gate 2119 and is reset by a chronograph reset signal Rcg output from a control signal forming circuit 2118. 2113 is a register which holds the content of the chronograph counter 2112 at the time the control signal forming circuit 2118 outputs a split indication command signal Sp. 2114 is a 1/50 based hand position counter which stores the indicated position of the 1/100 second hand by counting the 1/100 second hand-drive pulses Pf and is reset in response to a signal Rhnd output from the control signal forming circuit 2118 to store the 0-position of the 1/10 second hand. 2115 is an identity detector circuit which compares both the contents of the register 2113 and the hand position counter 2114 and then outputs an identity signal Dty when the identity is detected therebetween. 2116 is a 0-position detector circuit which outputs a 0 detection signal Dto upon detecting 0 in the hand position counter 2114. 2117 is a hand-drive control circuit for the 1/100 second hand which is arranged to pass the clock pulses Pfc when there exists an identity in the contents between the chronograph counter 2112 and the hand position counter 2114 during the operative state of the 1/100 second hand and time counting of the chronograph, pass the clock pulses Pfc when there exists no identity in the contents between the register 2113 and the hand position counter 2114 during split indication and outage of time counting, and pass the clock pulses Pfc when the content of the hand position counter 2125 is other than 0 during the inoperative state of the 1/100 second hand and time counting of the chronograph. 2118 is a control signal forming circuit which forms and outputs, in response to a command from the software, a start signal St for commanding start/stop of time counting of the chronograph, a split signal Sp for commanding on/off switching of the split indication, a chronograph reset signal Rcg for commanding to reset time counting of the chronograph, a 0-position signal Rhnd for storing the 0-position of the 1/100 second hand, and a signal Drv for commanding operative/-inoperative switching of the 1/100 second hand. Note that the 1/100 second hand can be driven by only the step motor C. Also, a carry signal  5 of 5 Hz output from the chronograph counter 2112 causes a chronograph interrupt CGint with which the software is able to advance the processing of time counting in excess of 1/5 second. 212 is a motor hand-drive control circuit which is practically constituted as shown in Fig. 11 and outputs motor drive pulses to respective motor drivers in response to commands from the software. Description of Fig. 11 will be made below in detail. 219 is a motor hand-drive mode control circuit which stores hand-drive modes of respective motors in response to commands from the software, and forms and then outputs respective control signals Sa for selecting forward drive I, Sb for selecting forward drive II, Sc for selecting backward drive I, Sd for selecting backward drive II, and Se for selecting forward correction drive. 220 is a hand-drive reference signal forming circuit which is practically constituted as shown in Fig. 17 and forms and then outputs hand-drive reference clock Cdrv in response to a command from the software. In Fig. 17, 2201 is a 3-bit register which stores the data for determining the frequency of the hand-drive reference clock Cdrv in response to a command from the software (i.e., an output signal from an address decoder 2202). 2203 is a 3-bit register which takes and stores the data stored in the register 2201 upon each falling edge of the hand-drive reference clock Cdrv output from a programmable frequency divider 2205. 2204 is a decoder which outputs the numbers of 2, 3, 4, 5, 6, 8, 10, 16 in the binary notation corresponding to the data stored in the register 2203. 2205 is a programmable frequency divider which divides the 256 Hz of the signal  256 output from the 1st frequency divider 208 into the 1/n frequency assuming that the numerical value output from the decoder 2204 is given by n. Accordingly, in response to commands from the software, the hand-drive reference signal forming circuit 220 can select as the frequency of the hand-drive reference clock Cdrv any one of eight values; i.e., 128 Hz, 85.3 Hz, 64 Hz, 51.2 Hz, 42.7 Hz, 32 Hz, 25.6 Hz and 16 Hz. Change in the frequency of the hand-drive reference clock Cdrv is made at the time of taking the data into the register 2203, and the data is taken into the register 2203 in synchronism with the hand-drive reference clock Cdrv. So, the interval of 1/fa has to be placed in changing the previous frequency fa to the subsequent frequency fb. Incidentally, when the forward drive I and the backward drive are carried out in succession, the frequency of the hand-drive reference clock Cdrv is limited to less than 64 Hz. 221 is a 1st drive pulse forming circuit which forms and outputs drive pulses Pa for the forward drive I as shown in Fig. 12. 222 is a 2nd drive pulse forming circuit which forms and outputs drive pulses Pb for the forward drive II as shown in Fig. 13. 223 is a 3rd drive pulse forming circuit which forms and outputs drive pulses Pc for the backward drive I as shown in Fig. 14. 224 is a 4th drive pulse forming circuit which forms and outputs drive pulses Pd for the backward drive II as shown in Fig. 15. 225 is a 5th drive pulse forming circuit which forms and outputs a group of drive pulses Pe for the compensation during the method for changing the pulse width in response to the load (i.e., normal drive pulses P1, correction drive pulses P2, pulses P3 upon detection of the AC magnetic field, AC magnetic field detecting pulses SP1, and rotation detecting pulses SP2 as disclosed in JP-A-60-250883.) 226, 227, 228, 229 are motor clock control circuits each of which is constituted as shown in Fig. 16 and controls the number of hand-drive pulses for the step motor A, B, C or D in response to a command from the software. In Fig. 16, 2261 is a 4-bit register which stores the number of hand-drive pulses commanded by the software. 2262 is a 4-bit up-counter which counts the hand-drive reference clock Cdrv having passed an AND gate 2274 and is reset by a control signal Sreset. 2263 is an identity detector which compares both the contents of the register 2261 and the up-counter 2262, and then outputs an identity signal Dy upon detecting the identity therebetween. 2264 is an all 1's detector circuit which outputs an all 1's detection signal D15 when the content of the register 2261 is all 1's in its bits. 2265 is a trigger signal generator circuit for forming motor drive pulses, which comprises NOT gates 2266 and 2267, a 3-input AND gate 2268, a 2-input AND gate 2269, and a 2-input OR gate 2270. It is so arranged that when all 1's (i.e., 15) is set into the register 2261, the motor pulses continue to be output repeatedly until setting of other data, and when other data than all 1's is set into the register 2261, the motor pulses are output as much as times corresponding to that data and then stopped until setting of the next data. 2271 is a bi-directional switch which is turned on upon issuance of a control signal Sread for placing the data stored in the up-counter 2262 onto data buses. 2227 is a control signal forming circuit which generates and outputs, in response to commands from the software, a signal Sset for setting the number of hand-drive pulses in the register 2261, a signal Sread for reading the data in the up-counter 2262, and a signal Sreset for resetting the register 2261 and the up-counter 2262. Incidentally, when the signal Sread is output, the combination of a NOT gate 2273 and an AND gate 2274 inhibits passage of the hand-drive reference clock Cdrv. In this case, it is required to generate the signal Sreset for resetting the register 2261 and the up-counter 2262 after reading. Also, upon the identity detector circuit 2263 for detecting the indentity (i.e., when the pulses in number set have all been delivered out), each motor generates a motor control interrupt (Mint). Where the motor control interrupt is generated, the software can read which interrupt has been generated, and then make reset after reading. 230, 231, 232, 233 are trigger forming circuits which pass trigger signals Tr from the respective motor clock control circuits as trigger signals Sat, Sbt, Act, Sdt, Set in response to the hand-drive mode control signals Sa, Sb, Sc, Sd, Se output from the motor hand-drive mode control circuit 219, respectively, thereby causing the 1st to 5th drive pulse control circuits to form respective motor drive pulses Pa, Pb, Pc, Pd, Pe. 234, 235, 236, 237 are motor drive pulse selector circuits which select and output those drive pulses necessary for the associated step motors among the motor drive pulses Pa, Pb, Pc, Pd, Pe output from the 1st to 5th drive pulse forming circuits in response to the drive mode control signals Sa, Sb, Sc, Sd, Se, respectively. The foregoing is a description of Fig. 11. Turning back to Fig. 1, 213, 214, 215, 216 are motor drivers each of which alternately outputs the motor drive pulse issued from the associated motor drive pulse selector circuit to two output terminals of its motor driver circuit for driving the associated step motor. 217 is an input control and reset circuit which carries out both processing of respective switch inputs applied through A, B, C, D, RA1, RA2, RB1, RB2 and processing of respective inputs applied through input terminals K, T, R. When an input is applied through either any one among the switches A, B, C, D or any one among the switches RA1, RA2, RB1, RB2, there occurs a switch interrupt Swint. At this time, interrupt factors are read and reset under control of the software. Note that each input terminal is normally pulled down to V SS, and sets data 0 when it is in the open state and data 1 when it is connected to V DD. The K terminal is a specification switching terminal which allows to select either one of two types of specifications dependent on the data applied to the K terminal. Incidentally, reading of data at the K terminal is executed under control of the software. The R terminal is a system reset terminal. When the R terminal is connected to V DD, the hardware forcibly initializes the core CPU, the frequency divider circuit and other peripheral circuits. The T terminal is a test mode conversion terminal. When the clock is input to the T terminal with the RA2 terminal kept connected to V DD, the peripheral circuits can be tested in any one of 16 test modes. As principal test modes, there are included a forward drive I verification mode, a forward drive II verification mode, a backward drive I verification mode, a backward drive II verification mode, a correction drive verification mode, a chronograph 1/100 second verification mode, etc. In these verification modes, the relevant motor drive pulses are automatically issued to the output terminals of the respective motor drive pulses. System reset can also be effected with simultaneous application of switch inputs other than the above methods of connecting the R terminal to V DD. The present IC is so arranged that system reset is forcibly implemented by the hardware upon simultaneous inputs through either one of A and C, B and RA2, as well as through any one of A, B and C, RA2 and RB2. There are also a frequency divider circuit reset and a peripheral circuit reset as reset functions which can be processed under control of the software. When the peripheral circuit reset is performed, the frequency divider circuits are also reset. 218 in Fig. 1 is an interrupt control circuit which processes priority setting of respective interrupts, storage until reading, and reset after reading with respect to switching interrupts, chronograph interrupts, and motor control interrupts. 200 is a constant-voltage circuit which forms a low constant-voltage of about 1.2 V from the battery voltage (about 1.58 V) applied between V DD and V SS and then outputs it to the V S 1 terminal. As fully described in the above, CMOS-IC20 has the following features in relation to a drive of a step motor and hence is very excellent and suitable as IC for a multi-functional analog electronic timepiece of the multi-hand type. 1 ○ It has the motor drivers 213, 214, 215, 216 and can drive four step motors at the same time. 2 ○ It has the motor hand-drive mode control circuit 219, the drive pulse forming circuits 221 - 225 and the motor drive pulse selector circuits 234 - 237, and can energize four step motors in any one of 3 forward drive modes and 2 backward drive modes separately under control of the software. 3 ○ It has the hand-drive reference signal forming circuit 220 and can freely change a hand-drive speed of each step motor. 4 ○ It has the motor clock forming circuits 226 - 229 corresponding to four step motors in one to one relation, and can freely set the number of hand-drive pulses for each step motor under control of the software. Fig. 7 is an external appearance view of the complete electronically corrected electronic timepiece of this embodiment. Specification and operation method of this embodiment will now be described briefly by referring to Figs. 7 and Figs. 24 to 28. In Fig. 7, designated at 40 is a bezel case, 41 a dial. On the dial, 42 is an area for the second indication of normal 12-hour time, 43 is an area for both the minute indication of chronograph and the second indication of timer elapsed time, and 44 is an area for the indication of alarm setting time. To begin with, normal 12-hour time is indicated by the use of the small second hand 14 driven in units of second, the minute hand 11 and the hour hand 12 as set forth above. Time adjustment can be made ready for by withdrawing the first winding stem 22 to its 2nd step. At this time, the 4-th wheel 6 is restricted by a train wheel setting lever 47 in engagement with the setting lever 45 and the yoke 46 shown in Fig. 9, so that the rotor 4 is stopped to suspend drive motion of the small second hand. By rotating the 1st winding stem 22 about its axis in this state, the torque is transmitted to the minute wheel 9 through a sliding pinion 48 and a setting wheel 50. Here, because the 2nd gear 8a is coupled to the 2nd pinion 8b while keeping certain sliding torque, the setting wheel 50, the minute wheel 9, the 2nd pinion 8b and the hour wheel 10 are all rotatable even with the 4-th wheel 6 restricted in its motion. Accordingly, the minute hand 11 and the hour hand 12 can be rotated, thereby allowing a user to set those hands to any desired time. Fig.18(a) and (b) show a flowchart for indicating normal 12-hour time. As will be seen from Fig. 18, upon input of an 1 Hz interrupt, the CPU reads as to whether the switch RA2 is turned off or on. If RA2 is off, then a forward compensation driving mode for the step motor A is set to the motor hand-drive mode control circuit 219, and the number of hand-drive pulses is set to 1 in the motor clock control circuit A 226. If the switch RA2 is on (i.e., time correction state), then the motor drive is stopped and, at the time RA2 is turned off, both the frequency divider circuits 208 and 209 are instantaneously reset so that the motor will start to be driven after one second. Fig.19(a) and (b) show a flowchart for a chronograph function. Note that "CG" found in Fig. 19 is an abbreviation of chronograph. Also, "CG start" represents the state in which the chronograph is under time counting and the split indication is released. With the 2nd winding stem 23 set at its normal position (i.e., when RB1 and RB2 are both turned off), the process flow enters a chronograph mode in which time counting of the chronographic is alternately started and stopped whenever the A switch input is applied. After onset of the chronograph time counting, the CG 1/5 second counter formed in a portion of the data memory 204 is incremented by +1 upon each CG interrupt so that the 1/5 CG hand 21 is driven in units of 1/5 second. Whenever the 1/5 second counter has counted one minute, the CG minute counter also formed in a portion of the data memory 204 is incremented by +1 so that the CG hand 31 is driven in units of minute. If the B switch input is applied after "CG start", then the process flow enters the split indication status. Furthermore, if the B switch is applied during the split indication, then the "CC start" is effected to fast-drive both the 1/5 second CG hand 21 and the minute CG hand 31 up to indicate the counted time. If the B switch input is applied during outage of the chronographic time counting, then the chronographic time counting is reset and the respective CG hands are fast-driven up to indicate the 0-position. Incidentally, the process for fast-driving the hands is shown in a flowchart of Fig. 22. Fig.20(a) and (b) is a flowchart for a timer function. The timer setting time is indicated by the 1/5 second CG hand 21. With the 2nd winding stem 23 set to its 1st step (i.e., when RB1 is turned on), there enters a timer mode. When the B switch input is applied during the timer set status, the timer setting time is incremented by one minute, and the 1/5 second CG hand 21 is driven in units of minute (or 5 steps). The graduation on the dial 41 that is indicated by the 1/5 second CG hand 21 represents the timer setting time. A timer setting time up to 60 minutes at maximum is possible. The timer is started and stopped by the A switch 24. After onset of the timer operation, the minute CG hand 31 is driven counterclockwise in units of second, and the 1/5 second CG hand 21 is driven counterclockwise in units of minute, thereby indicating the timer elapsed time. When the timer setting time is set to be one minute or when the timer remaining time has come into a range within the last one minute, the minute CG hand 31 is stopped and the 1/5 CG hand 21 is driven in units of second for countdown. The warning sound start to be produced from 3 seconds before the time-up, and when the countdown reaches 0 second, the time-up sound is produced and the timer operation is ended. Fig. 22 shows a flowchart for a hand-drive method of each motor. Fig. 22(a) represents a hand-drive method of the motor when the number of drive pulses is not larger than 14, while Figs. 22(b) and 22(c) represent a fast (128 Hz) hand-drive method of the motor in which the number of drive pulses is not less than 15. Note that "motor pulse register" found in Fig. 22 means the register 2261 in Fig. 16. Next, operation for setting the alarm time in this embodiment will be described below. As shown in Fig. 21(a), with the 2nd winding stem set to its 1st step (i.e., when the switch RB1 is turned on), if the C switch 26 continues to be pushed, then 16 Hz is set in the programmable frequency divider 2205 in the motor clock control circuit D 229 in response to a command from the CPU. Subsequently, the forward drive II is selected for the motor drive pulse selector circuit D 237 and finally 15 is set in the register of the trigger forming circuit D 233 (hereinafter referred to as motor pulse register). As mentioned above, where 15 is set in the motor pulse register, the motor pulses continue to be output until other data than 15 is set therein. Therefore, the alarm hour and minute hands driven by the motor driver D 216 are continuously rotated at a rate of 16 Hz until setting of the next reference clock. At the time 15 motor pulses are output, the trigger forming circuit D 233 produces a control interrupt. With the control interrupt produced, as shown in Fig. 21(b), if the reference clock does not yet reach 128 Hz, then the reference clock from the programmable frequency divider 2205 is increased in its frequency to 1-up stage in response to a command from the CPU, thereby enabling a unique correction hand-drive method in which the correction speed is stepwisely increased per 15 motor pulses (hereinafter referred to as accelerated correction), as shown in Fig. 24(a). Fig. 26 illustrates the relationship between the correction time and the frequency as established in this case. In this respect, the experiments conducted by the present inventors have proved that acceleration of the hand-drive speed can visually appear to a user in continuous fashion by once setting the hand-drive speed to one or two intermediate stages before doubling thereof so as to make every 15 motor pulses issued to the step motor at a constant speed, as shown in Fig. 24(a). Further, the alarm setting time is incremented by 15, since the alarm minute hand 38 has already been driven through 15 steps until occurrence of the control interrupt from the time when the correction has started or when the previous control interrupt has occurred. Such accelerated correction of the alarm setting time can be stopped as follows. By turning off the C switch 26, as shown in Fig. 21, the up-counter 2262 in the trigger forming circuit D 233 (hereinafter referred to as motor pulse up-counter) is read in response to a command from the CPU, whereby output of the motor pulses is stopped. At this time, since the alarm minute hand 38 has been advanced through those steps corresponding to the read value from the time when the previous control interrupt has occurred, that value is added to the alarm setting time for correction. After that, the motor pulse register and the motor pulse up-counter are reset. Besides, the foregoing embodiment in which the hand-drive speed is stepwisely increased per every 15 motor pulses provides a relatively fast feeling in acceleration of the hands. If the hand-drive speed is stepwisely increased per every 30 motor pulses, there can be obtained a relatively slow feeling in acceleration of the hands. In this case, acceleration of the hand-drive speed can also visually appear to a user in continuous fashion. The similar effect is obtainable even if the pattern of change in the hand-drive speed is modified with respect to the illustrated one. Next, operation of correcting the 0-position of the CG 1/5 second hand 21 in this embodiment will be described below. With the 1st winding stem set to its 2nd step (i.e., when the switch RA2 is turned on), as shown in Fig. 23(a), if either the A switch 24 or the B switch 25 is pushed, then either the forward drive II or the backward drive is selected in response to a command from the CPU. Subsequently, 16 Hz is set in the programmable frequency divider 2205 in the motor clock control circuit B 227. Finally, 15 is set in the motor pulse register of the trigger forming circuit B 231. As mentioned above, where 15 is set in the motor pulse register, the motor pulses continue to be output until other data than 15 is set therein. Therefore, the CG 1/5 second hand 21 driven by the motor driver B 214 is continuously rotated at a rate of 16 Hz until setting of the next reference clock. At the time 15 motor pulses are output, the trigger forming circuit B 231 produces a control interrupt. With the control interrupt produced, as shown in Fig. 23(b), if the reference clock does not yet reach 128 Hz for the forward drive or 64 Hz for the backward drive, then the reference clock from the programmable frequency divider 2205 is increased in its frequency to 1-up stage in response to a command from the CPU, thereby increasing the correction speed stepwisely per 15 motor pulses while allowing different patterns of the accelerated correction for the forward and backward drives, as shown in Figs. 24(a) (in the case of forward drive) and 24(b) (in the case of backward drive). Such accelerated correction can be stopped as follows. By turning off the A switch 24 or the B switch 25, as shown in Fig.23(a), the motor pulse up-counter in the trigger forming circuit B 233 is read in response to a command from the CPU, whereby output of the motor pulses is stopped. After that, the motor pulse register and the motor pulse up-counter are reset. In the foregoing embodiment, the hand-drive speed is changed in the direction to increase only. In correcting the alarm time, for example, if the correction speed is once lowered during continuous correction when the hands have reached the time about one hour earlier than the alarm time previously set, it becomes possible to easily set the alarm time again at such a time slightly earlier than the previous alarm time even with the correction actuatable only in the forward direction. Other practical configuration of the driver circuit for changing the hand-drive speed will now be described with reference to Figs. 27 to 29. Fig. 27 is a block diagram showing the case in which the present invention is applied to time correction for an electronic analog timepiece. With the illustrated embodiment, an oscillator circuit 311 can produce the original oscillation of 32768Hz. A frequency divider circuit 312 divides the original oscillation 16 times for providing a series of signals having frequencies ranging from the original frequency to 1 Hz. A mode selector circuit 317 is able to select either one of a time clock mode and a time correction mode in switching manner therebetween dependent on a switch input through K1. The mode selector circuit 317 enables a gate to output a signal of 1 Hz from the frequency divider circuit 312 to a waveform creating circuit 313 in a time clock mode. In a time correction mode a signal of 16 Hz is input into waveform creating circuit 313 under the control of mode selector circuit 317 controlling correction signal forming circuit 316. The correction signal forming circuit 316 also takes in other signals of 32 Hz, 64 Hz, 128 Hz, in addition to the signal of 16 Hz, from the frequency divider circuit, and then forms a single-shot correction signal and a fast-drive correction signal for outputting them to the waveform creating circuit 313. Based on the signals from the frequency divider circuit 312 and the correction signal forming circuit 316, the waveform creating circuit 313 generates a hand-drive signal on the order of 4 msec which is applied to a driver circuit 314 for driving a stepping motor 315. Fig. 28 is a time chart representing an switch input through K2 and an output signal from SA of the correction signal forming circuit 316 in Fig. 27. As will been seen from this time chart, actuating the push switch K2 outputs a single-shot correction signal from SA in a time correction mode. If the switch K2 continues to be held on for a period of time not shorter than one second, a fast-drive correction signal of 16 Hz is output from SA. Whenever every 16 shots (or drive pulses) are exceeded before reaching the intended amount to be corrected, the fast-drive correction signal is increased in its fast-drive correction speed stepwisely from 16 Hz to 32Hz, 64Hz and finally to 128 Hz. When reaching the maximum rate of 128 Hz, the correction speed is held at that rate. Upon the push switch K2 being turned off, the fast-drive correction is stopped. Fig. 29 is a circuit diagram for forming the fast-drive correction signal. A switch input through S2 is normally held at a high level, which keeps both a timer circuit 342 and a flip-flop 343 in the reset state. In this state, a signal input through the switch S2 passes both an AND gate 345 and a NOR gate 346 and then reaches SA. As a result, the single-shot correction signal is issued from SA. During the time the switch S2 is kept on, the timer circuit 342 counts a signal of 16 Hz. If the switch S2 continues to be held on for one second, the timer circuit 342 causes an overflow and then outputs a high level from Q4. Upon a C input terminal of the flip-flop 343 changing from a low level to a high level, Q and Q outputs thereof are changed from a low and high level to a high and low level, respectively, so that the AND gate 345 is closed. Meanwhile, another AND gate 344 is opened and an output of an OR gate 339 is delivered. Thus, the fast-drive reference signal is now allowed to pass the AND gate 344 and the NOR gate 346, and then output from SA. The fast-drive correction reference signal is formed by selecting any one of the signals of 16 Hz, 32 Hz, 64 Hz and 128 Hz. Designated at 331, 332, 333 and 334 are flip-flops for selecting the signals of 16 Hz, 32 Hz, 64 Hz and 128 Hz, respectively. Any one of the fast-drive reference signals 16 Hz, 32 Hz, 64 Hz and 128 Hz can be selected through AND gates 335 - 338 and the NOR gate 339. When the fast-drive correction is not selected by the flip-flop 343, the Q output of the flip-flop 343 holds a high level so that the flip-flops 332 - 334 are kept in the reset state and the flip-flop 331 is kept in the set state. If the switch input through S2 continues to be applied longer than a predetermined period of time, the fast-drive correction is selected and the Q output of the flip-flop 343 is changed from a high level to a low level, whereupon the flip-flop 331 and the flip-flops 332 - 334 are turned to the reset state and set state, respectively. The fast-drive reference signal output from the OR circuit 339 is applied to a counter circuit 341 after passing an AND gate 340 except for the case that the signal of 128 Hz is selected. The counter circuit 341 produces a carry output whenever 16 shots of the fast-drive reference signals are applied thereto, so that the cascaded flip-flops 331 - 334 are shifted by one bit. It is needless to say that the count number for delivering the carry output from the counter circuit 14 can be selected to be 15 as with the foregoing embodiment by way of example, and any other desired number may also be selected instead of 15. Immediately after onset of the fast-drive correction, the flip-flop 331 is in the set state and the reference signal of 16 Hz is selected. Whenever every 16 shots (or drive pulses) are exceeded within the amount of fast-drive correction, the correction speed is selected to be 16 Hz, 32Hz, 64Hz and 128 Hz stepwisely in an increasing order. When reaching the maximum rate of 128 Hz, the AND gate 340 prevents the fast-drive correction signal from being output to the counter circuit 341. Therefore, after the fast-drive reference signal has reached 128 Hz, the circuit continuously delivers the fast-drive correction signal of 128 Hz. Upon the switch S2 being turned off, the timer circuit 342 and the flip-flop 343 are reset so that the Q and Q outputs of the flip-flop 343 are turned to a low and high level, respectively. As a result, the fast-drive correction is stopped and the one-shot correction is enabled. Next, another embodiment of the present invention will be described below. In this embodiment, a liquid crystal driver and latch 3001 and a liquid crystal display 3002 as shown in Fig. 25 are added to the foregoing first embodiment. In response to commands of the software, the liquid crystal display 3002 indicates time-of-day, second time different from time-of-day, calendar date, alarm and timer setting time, mode, chronographic time, etc. in digital representation. According to the present invention as described above, since the drive speed of the hands is increased or decreased stepwisely by the correction signal forming circuit at the time of continuously correcting time-of-day, alarm setting time, setting time period of the timer, reference positions of the hands, etc., it becomes possible to realize an electronically corrected electronic timepiece of the analog display type which has the ability of easy and quick electronical correction. Facilitation of the correction method makes less frequent the chances of failing in and redoing the correction steps, and hence contributes to save the consumed current. This in turn reduces the degree of wear of the operating members and improves the reliability for a long term. Since the accelerated correction illustrated in the embodiments gives a user a natural feeling in operation, the user can feel satisfactory and the commercial value can be enhanced. Adaptable setting of correction pattern to the purpose of end use also contributes to improve an operation feeling and enhance the commercial value. Further, in case of setting the reference positions of the hands, for example, it becomes possible to easily set the reference positions and provide a still better operating feeling, by arranging the correction speed to be slow when the hands are passing near the reference positions, and to be fast when they are passing in an area far from the reference positions. In case of setting the alarm time, the correction speed can be reduced when the hands are passing near such time zones as set at relatively high frequency, thereby for facilitating the time setting in those zones. In case of unidirectional correction, even the backward correction of small amount can easily be performed by slowing down the hand-drive speed just before a full turn of the hands during the correction. In addition, although the correction speed can be changed selectively by manual operation, the present invention does not require any switch for changing the correction speed, and hence can be simplified in both arrangement and operation as compared with the case of manual switching.

Claims: An electronically corrected electronic timepiece, comprising a step motor (3b, 15b, 27b, 32b), an external operating means (22-26), a control circuit (20) for controlling said timepiece, a control circuit (212) for driving the step motor, and control means (220) for correcting the position of a hand (11, 12, 14, 21, 31, 38, 39) of the timepiece in an electronic manner in response to said external operating means being operated, wherein said control means is adapted to continuously correct position of hand while said operating means (22-26) is being operated, and the speed of driving said hand is increased during said continuous correction, characterized in that a progammable frequency divider (2205) is provided for frequency dividing a reference clock pulse (Φ256) and generating a drive pulse for said step motor, the frequency dividing ratio of said programmable frequency divider being set by means of a software command. A timepiece according to claim 1, adapted to correct the position of a hand (11, 12, 14, 21, 31, 38, 39) in both the forward and backward directions. A timepiece according to claim 1, wherein during continuous correction of the position of a hand (11, 12, 14, 21, 31, 38, 39), the hand-drive speed is changed through 3 or more stages. A timepiece according to claim 1, wherein during continuous correction of the position of a hand (11, 12, 14, 21, 31, 38, 39), the hand-drive speed is set to one or more intermediate stages before changing to double or half the starting speed. A timepiece according to claim 1, wherein during continuous correction of the position of a hand (11, 12, 14, 21, 31, 38, 39), the relationship between the hand-drive speed and the number of pulses delivered to a step motor (3b, 15b, 27b, 32b) at that hand-drive speed is controlled by said control means (220) so that changes in the hand-drive speed visually appear in continuous fashion. A timepiece according to claim 2, wherein during continuous correction of the positions of a hand (11, 12, 14, 21, 31, 38, 39), the patterns for changing the hand-drive speed are made different between forward drive and backward drive. A timepiece of the analog/digital display type according to claim 1, wherein the digital display function is incorporated. A timepiece according to claim 1, 2, 3, 4, 5, 6 or 7, wherein said hand points to the time of day, alarm setting time, setting time period of a timer or the like. A timepiece according to claim 1, further comprising a motor clock control circuit (226) for counting a certain number of pulses while the position of the hand is being corrected, wherein said motor clock control circuit (226) produces an interrupt signal (Mint) causing that the frequency divider ratio of said programmable frequency divider (2205) is increased by one step.

Inventors: KAWAGUCHI TAKASHI, KUBO HIROYUKI, MARUYAMA AKIHIKO, YABE HIROSHI, KAWAGUCHI, TAKASHI, KUBO, HIROYUKI, MARUYAMA, AKIHIKO, YABE, HIROSHI
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1989
Main classification: G04C9
IPC codes: G04C3, G04C23, G04C9