High side driver MOS circuit

Abstract: A MOS high side driver circuit switching a supply volt­ age by means of a power switching transistor (M1) driven by a driving circuit in function of a drive switching signal (C), utilizes a flip-flop (F) for driving the gate of the power switching transistor (M1). The inputs SET and RESET of the flip-flop (F) are respectively connected to the drain node of two, grounded source, input transistors (M2R, M2S) supplied from a (V GG ) rail maintained at a constant potential difference from the source (ouput) node of the power switching transistor (M1). Two pulse signals, respectively C R and C S and corre­ sponding to a rising and to a falling edge of the drive switching signal (C) from which they are derived by suitable circuit means, are respectively applied to the gates of the two input transistors (M2R, M2S). The driving circuit dissipates only during transitions in contrast to the driving circuits of the prior art.

Description: 1. Field of the invention The present invention relates to intergrated MOS circuits and particularly to a circuit for driving a power MOS transistor. 2. Description of the prior art The driving of a power MOS transistor under certain circumstances presents problems. This is the case for instance of a power MOS transistor of an output stage of a logic circuit utilized for switching a supply voltage across an externally connected load. In this situation, in order to ensure a complete turning-on (saturation) of the power transistor during an ON period, a relatively high voltage must be maintained between the gate and the source of the transistor (in the order of about 10 Volts). Should a normal bias configuration be used for the power transistor, an excessive voltage drop across the transistor itself would develop. In the instance, particular circuit techniques are used which permit the gate to reach absolute levels even higher than the drain voltage of the power transistor. A known practice is to use the so-called "bootstrap" circuit which is essentially a regenerative feedback circuit used for increasing the gate potential with respect to the source (output node) potential. An alternative circuit arrangement of the prior art contemplates the "release" of the gate potential from the drain potential of the output transistor by utilzing a constant voltage generator connected between the output node OUT (source of the power output transistor) and a V GG node and by supplying the driving device of the power transistor from these circuit nodes. In this way, the gate voltage of the power transistor may assume a value close to the voltage V GG , which may also be higher than the drain voltage V DD of the power transistor when the latter is conducting. An example of a driving circuit of this known type (high side driver in literature) is depicted in Figures 1, 2 and 3. The potential difference between the nodes V SS and V GG is maintained constant by means of a suitable voltage generator (a battery or a power supply) while the absolute value of the voltage of nodes V GG and V SS depends on the state (ON or OFF) of the power transistor M1, which switches a supply voltage V DD across the load Zc in function of a driving signal C which is applied to the gate of the driver transistor M2, which may be considered the input terminal IN of the driving circuit. Block 2 of Fig. 1 is essentially an amplifier A, as depicted in Figures 2 and 3. In both circuits, the switching OFF and ON of the input transistor M2 causes, by means of the amplifier A, the switching ON and the switching OFF of the power transistor M1. A limiting diode D is commonly added in order to protect the input of the amplifier A when the transistor M2 is ON by preventing the potential at the input of the amplifier A to become eccessively negative in respect to the voltage V SS . A current generator I (Fig. 2), or a resistor R p (Fig. 3) ensures the maintainance of the drain potential of the transistor M2 at a correct logic level (1) when the transistor is OFF. In general, the driving circuits in accordance with the prior art, have the disadvantage of dissipating energy during the periods when the transistor M2 is ON and the state of the output transistor M1 is tied to the state of the input transistor M2 of the driving circuit. OBJECTIVE AND SUMMARY OF THE INVENTION A main objective of the present invention is to provide a driving circuit for a high side driver circuit which dissipates energy only during a transition from one state to another state. This objective and related advantages are obtained by the driving circuit of the invention as defined in the annexed claims. The driving circuit of the invention as defined by claim 1 is based upon the use of a memory element, in practice a flip-flop, for driving the power transistor by driving the flip-flop, through the respective SET and RESET terminals, by means of two pulse signals derived from a drive switching signal C. The first of the pulse signals (C S ) is a pulse coinciding with a trailing edge of the drive switching signal C, while the second derived signal (C R ) is a pulse coinciding with a rise or front edge of the drive switching signal C. While the use of flip-flops for driving power transistors is per se known, e.g. from EDN, July 1986, pages 74-82,84, B.Travis: "High-voltage circuits use mixed processes, fulfill diverse roles", the driving circuit of the invention uses a flip-flop having different circuit connections BRIEF DESCRIPTION OF THE DRAWINGS The invention and its advantages in respect to the prior art will be more easily understood through the following description of an embodiment thereof and with reference to the accompanying drawings, wherein: Figure 1 is a circuit diagram of the driving circuit of a high side driver, in accordance with the prior art; Figure 2 is an embodiment of the driving circuit of Fig. 1, in accordance with the prior art; Figure 3 is another embodiment of the circuit of Fig. 1 in accordance with the prior art; Figure 4 depicts a driving MOS circuit for a high side driver made in accordance with the present invention; Figure 5 is a diagram showing the wave shape of the two pulse signals C R and C S derived from a drive switching signal C; Figure 6 shows a preferred embodiment of the block S of the circuit of Fig. 4; and Figure 7 is a diagram showing the wave shape of the respective signals of the circuit of Fig. 6. DESCRIPTION OF THE PREFERRED EMBODIMENT With reference to Fig. 4, the driving through the gate of the power switching transistor M1 is performed, in accordance with the present invention, by means of a memory element F, which is shown in Fig. 4. The memory element F may be constituted by a SET-RESET type flip-flop supplied from the nodes V GG and V SS of the circuit. The input SET (S) of the flip-flop is connected to the drain of a first, grounded source, input transistor M2S, and the RESET (R) input of the flip-flop is connected to the drain of a second, grounded source, input transistor M2R. A load element (R p1 , and R p2 ) is connected between the drain of each of the two input transistors, respectively, and the node V GG , in order to ensure that the drain potential of the two input transistors is kept at a level corresponding to a stationary logic state 1 when the two transistors are OFF. This load element may be, as shown in Fig. 4, a resistor (R p1 and R p2 , respectively) or a current generator. A diode (D1 and D2, respectively) is preferably connected between the node V SS (the source or output node of the power switching transistor M1) and the drain of each of the two input transistors M2S and M2R, in order to prevent the drain potential of the two transistors from becoming excessively negative in respect to the V SS when they are conducting. The two input transistors M2R and M2S are driven by two pulse signals, C R and C S , respectively, the first of which is a pulse which coincides with the rising edge of the drive switching signal C, while the second is a pulse which coincides with the falling edge of the drive switching signal C. The pulse signals C R and C S are derived from the switching signal C, which is applied to an input terminal IN of the driving circuit, by means of any suitable circuit means, indicated by the block S in Fig. 4, and which may be made in various forms as it is well known to a skilled technician. The respective wave shape of the signals C R and C S relative to a drive switching signal C having a certain "duty-cycle" are depicted in the diagram of Fig. 5. There are many methods and circuit arrangements for deriving such two positive pulse signals coinciding respectively with the rising edge and with the falling edge of a typical wave shape of a drive switching signal, for example derivating and rectifying circuits may be used. A preferred embodiment of such circuit means capable of deriving two positive pulse signals C R and C S from a drive switching signal C is depicted in Fig. 6 and is based on the utilization of the delay introduced by an inverting logic gate (an inverter). In the example shown in Fig. 6, essentially a NOT, an AND and a NOR gates are used. A drive switching signal C and the negate C thereof which is obtained at the output of the NOT (inverter) gate are applied to two inputs of each of the AND and NOR gates to obtain at the respective outputs two signals given by: C R = C Λ C and Since the inverted signal C obtained at the output of the inverter has in fact a certain delay in respect to the input signal C, the signals C R (at the output of the AND gate) and C S (at the output of the NOR gate) will have the desired characteristics, as graphically shown in the diagram of Fig. 7. Naturally, the same result may also be obtained through a different arrangement of logic gates and of a different kind of delay elements. Using the driving circuit of the invention a substantial dissipation (current drawing) by the driving circuit occurs only during transitions, thus fully achieving the objective. In certain circuit situations it may be useful to use a buffer stage between the output of the driving memory element F of the driving circuit and the gate of the power swtiching transistor M1. The driving memory element F, though being depicted in Fig. 4 as formed by two NAND gates, may also be formed with different logic gates or with any other bistable element having suitable characteristics.

Claims: A driver circuit for switching a supply voltage (V DD ) across a load (Zc) by means of a power switching transistor (M1), having a drain connected to said supply voltage (V DD ), a source connected, as a circuit node (V SS ), to a terminal of said load, the other terminal of which is connected to ground, said power switching transistor being driven by a driving circuit in function of a drive switching signal (C), said driving circuit dissipating power only during transitions, characterized by comprising input circuit means (S) having an input terminal (IN) to which said drive switching signal (C) is applied capable of producing at two output terminals thereof a first pulse signal (C S ) which is a positive pulse coinciding with a falling edge of said switching signal (C) and a second pulse signal (C R ) which is a positive pulse coinciding with a rising edge of said switching signal (C), respectively; a first, grounded source, transistor (M2S) driven by said first signal (C S ) and having a drain connected through a first load element, capable of maintaining the drain potential of the transistor at a stationary logic 1 level with respect to said circuit node (V SS ) when the transistor is OFF, to a supply node (V GG ) of the circuit; a second, grounded source, transistor (M2R), driven by said second pulse signal (C R ) and having a drain connected through a second load element capable of maintaining the drain potential of the transistor at a stationary logic 1 level with respect to said circuit node (V SS ) when the transistor is OFF to said supply node (V GG ) of the circuit; a SET-RESET type flip-flop (F) having its supply terminals connected to said supply node (V GG ) and said circuit node (V SS ), having a SET input terminal connected to the drain of said first transistor (M2S) and a RESET input terminal connected to the drain of said second transistor (M2R) and having an output terminal connected to the gate of said power switching transistor (M1); between said supply node (V GG ) of the circuit and said circuit node (V SS ) a constant potential difference being maintained by means of a voltage generator. The circuit according to claim 1, wherein said load of each the transistors (M2S, M2R) is a resistor (R p1 , R p2 ). The circuit according to claim 1, wherein said load of each the transistors (M2S, M2R) is a current generator. The circuit according to claim 1, wherein a limiting diode (D1, D2) is connected between the source of the power switching transistor (M1) and the drain of each of said two transistors (M2S and M2R), respectively. The circuit according to claim 1, wherein a buffer stage is present between the output terminal of said flip-flop (F) and the gate of said power switching transistor (M1). The circuit according to claim 1, wherein said circuit means (S) comprise a logic NOT gate, a logic AND gate and a logic NOR gate; said drive switching signal (C) being applied to an input of each of said logic gates, the output signal ( C ) of said NOT gate having a certain delay in respect to the input signal (C) and being applied to a second input of each of said other logic AND and NOR gates, thus obtaining at the respective output terminals of said latter gates said two pulse signals (C R , C S ).

Inventors: CHIELI DAVIDE, CHIELI, DAVIDE
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1989
Main classification: H03K17
IPC codes: H03K17, H03K19