Signal processing system

Abstract: A reception signal processing system in a communication system (e.g. a modem) for transmitting data under a predetermined baud-rate, including: a first unit (1,2) operated at a first frequency (fs) for receiving the reception signal (Xn) and for recovering loss components in the reception signal; a second unit (3) responsive to an output (Yn) of the first unit, for determining a first ideal reception signal (Rn) corresponding thereto based on a second frequency (fb) corresponding to the baud-rate, the first frequency (fs) being higher than the second frequency (fb); and a third unit (4) operatively connected to the first unit (1,2) and second unit (3), responsive to the first ideal reception signal (Rn) from the second unit (3) based on the second frequency (fb) and for generating and providing a second ideal reception signal (Sn) based on the first frequency (fs) to the first unit (1,2); the second ideal reception signal (Sn) being derived by processing the first ideal reception signal (Rn), and the first ideal reception signal corresponding to the data transmitted. The system is capable of suppressing high-frequency phase jitter in the reception signal (Xn).

Description: The present invention relates to a reception signal processing system in a communication system and to a digital signal processing system provided in a modulator/demodulator (below, modem) in a digital data transmission network. More particularly, it relates to a digital signal processing system for compensating a base band signal or pass band signal received in the modem using a predetermined sampling frequency. An output of the signal processing system is supplied to a personal computer, a facsimile apparatus and the like through the digital data transmission network. A digital signal processing technique is widely utilized in the field of information processing. In general, first, a digital signal is converted to a base band signal based on a Nyquist rate, second, the base band signal is wave-shaped by a filter and also converted to a pass band signal based on a modulation method in the modem, third, the pass band signal is transmitted to another modem through the analog or digital data transmission network, fourth, the pass band signal is converted to the original base band signal (demodulation), and last, the base band signal is recovered in the other modem. The modem mainly has two functions, i.e., the modulation and demodulation as explained above. Further, the type of the modem can be classified into high speed modems and low speed modems based on the processing speed. Low speed modems are mainly used for frequency shift keying (FSK) at a data transmission speed lower than 1200 bps (bit per second). While, high speed modems are mainly used for a phase shift keying (PSK) or a quadrature amplitude modulation (QAM) at a data transmission speed higher than 2400 bps. In the demodulation process, it is necessary to compensate phase jitter distortion contained in the pass band signal, particularly, in a low speed modem. One example of a digital signal processing system, "An automatic equalizing method and system" by Noriake Fujimura, is disclosed in U.S. Patent No. 4,097,807. This method is used for a suppressed carrier data transmission system for automatically compensating amplitude for static and dynamic variations in the phase, delay and frequency characteristics of a transmission channel in a high speed data transmission. As an another example, "Joint Equalization and Carrier Recovery Adaptation in Data Transmission Systems" by Falconer is disclosed in U.S. Patent No. 3,878,468. This prior art shows a pass band system and base band system. Both pass band and base band systems can be adapted to a low frequency system as mentioned above. NTC'77 conference Record, Los Angeles, Dec. 77, vol. 1, pages 11:1-1 / 11:1-9, IEEE, U.S.A.; by S. Qureshi et al "Performance and properties of a T/2 equalizer", discloses a digital signal processing system in accordance with the preamble of accompanying claim 1. In this system, the equalization means itself performs a frequency conversion by sampling an input signal at a predetermined sampling frequency and outputting an equalized signal at a lower baud-rate frequency. Subsequent decision and calculating circuits operate only with signals at the baud-rate frequency, so that a difference signal fed back to the equalization means is also at the baud-rate frequency. According to the present invention, there is provided a digital signal processing system in a modem, comprising: signal recovering means comprising at least an equalization means for compensating amplitude and delay distortion of a base band signal demodulated from a reception signal or pass band signal in the modem; a decision means operatively connected to said signal recovering means and operated at a predetermined baud-rate frequency for generating decision data from said base band signal; a calculation means operatively connected between said signal recovering means and said decision means for obtaining a difference signal, said difference signal being fed back to said signal recovering means so that said difference signal becomes zero; characterised in that said signal recovering means further comprises a carrier phase control means operatively connected to said equalization means and operated at said predetermined sampling frequency for correcting a phase shift of said base band signal; and in that the system further comprises a frequency conversion means operatively connected to said decision means for converting a sampling frequency of said decision data to said predetermined sampling frequency; whereby said difference signal represents the difference between an output of said frequency conversion means and an output of said carrier phase control means so that said equalization means compensates the amplitude and the delay distortion of said base band signal, and/or said carrier phase control means corrects the phase shift of said base band signal, by using said difference signal at the predetermined sampling frequency. An embodiment of the present invention may provide a digital signal processing system in a modem for enabling suppression of phase jitter at high frequencies contained in a base band signal or pass band signal when the received signal is processed in the modem by using a predetermined sampling frequency higher than the baud-rate frequency. In one embodiment of the present invention, the frequency conversion circuit comprises: a delay element for delaying the decision data and outputting delayed decision data, the decision data obtained from the base band signal demodulated from the reception signal having a roll-off rate of 100%; a second decision circuit for inputting the decision data and the delayed decision data, obtaining an intermediate point between present decision data and delayed decision data just before the present decision data, and outputting intermediate decision data; and a switching circuit for switching between the decision data and the intermediate decision data, and obtaining a signal of at least twice the baud-rate frequency used as a sampling signal having the predetermined sampling frequency. In another embodiment of the present invention, the frequency conversion circuit comprises an interpolator for generating a sampling signal having the predetermined sampling frequency based on the decision data. Reference is made, by way of example, to the accompanying drawings in which:- Fig. 1 is a schematic block diagram of a prior-proposed digital signal processing system provided in a modem; Fig. 2 is a basic block diagram of a digital signal processing system embodying the present invention; Fig. 3 is a schematic block diagram of a digital signal processing system according to an embodiment of the present invention; Fig. 4 is a view for explaining an intermediate point of an impulse response curve; Figs. 5 and 6 are curves for explaining a roll-off rate; Fig. 7 is a view for explaining a sampling frequency having a double baud-rate frequency; Fig. 8 is a schematic block diagram of a digital signal processing system according to another embodiment of the present invention; Fig. 9 is a view for explaining a difference signal output from a calculation circuit shown in Figs. 2, 3 and 8; Fig. 10 is a detail block diagram of an interpolator shown in Fig. 8; Fig. 11 is one example of a zero insertion circuit shown in Fig. 10; Fig. 12 is a view for explaining the relationship between decision data and a switch signal; Fig. 13 is one example of a roll-off filter shown in Fig. 10; Fig. 14 is a view for explaining a filtered signal In shown in Fig. 13; Fig. 15 is one example of an equalization circuit shown in Figs. 2, 3 and 8; Fig. 16 is one example of a carrier phase control circuit shown in Figs. 2, 3 and 8; and Fig. 17 is a one example of a decision circuit shown in Figs. 2, 3 and 8. Before describing the preferred embodiments, the explanations will be given of a prior-proposed digital signal processing system and problems thereof. Figure 1 is a schematic block diagram of a prior-proposed digital signal processing system provided in a modem. In Fig. 1, 11 denotes an equalization circuit (EQL), 12 a carrier phase control circuit (CAPC), 13 a decision circuit and 14 a calculation circuit. Further, Xn is a base band signal or pass band signal input into the equalization circuit 11. The equalization circuit 11 compensates an amplitude and a delay distortion of the base band signal or pass band signal Xn demodulated in the modem, and outputs an equalization signal Hn. One example of the equalization circuit 11 is shown in Fig. 15. The carrier phase control circuit 12 receives the equalization signal Hn and corrects a phase shift of the equalization signal Hn and outputs a correction signal Yn. One example of the carrier phase control circuit 12 is shown in Fig. 16. The decision circuit 13 receives the correction signal Yn, extracts the data from the correction signal Yn and outputs decision data Rn. The calculation circuit 14 receives the decision data Rn, and calculates a difference signal between a baud-rate frequency fb corresponding to the decision data Rn and the correction signal Yn. The difference signal Δ between the signal Rn and the signal Yn is fed back to the equalization circuit 11 and the carrier phase control circuit 12 so that the difference signal becomes zero. The digital signal processing system shown in Fig. 1 is generally operated in accordance with the baud-rate frequency fb input into the equalization circuit 11, the carrier phase control circuit 12, the decision circuit 13, and the calculation circuit 14. In a low speed modem, for example, the frequency 150 Hz is used as the band-rate frequency of the transmission in V.34 of the CCITT recommendation. Accordingly, when the sampling frequency for the base band signal Xn to the equalization circuit 11 and the carrier phase control circuit 12 is equal to the baud-rate frequency fb (for example, fb = 150 Hz), it is possible to only suppress the phase jitter generated under 75 Hz because the carrier phase control circuit 12 operates in accordance with the baud-rate frequency fb as the sampling frequency. While, in the high speed modem, it is possible to suppress the phase jitter at very high frequencies because the sampling frequency applied to the carrier phase control circuit 12 is very high. Phase jitter also occurs at double or three times of the frequency (100 Hz or 150 Hz) of a power source frequency (for example, 50 Hz) in the low speed modem. However, the phase jitter at the above frequencies cannot be suppressed because half of the sampling frequency is under 75 Hz. Figure 2 is a basic block diagram of a digital signal processing system embodying the present invention. In Fig. 2, reference number 1 denotes an equalization circuit, 2 a carrier phase control circuit, and 3 a decision circuit. Reference number 4 denotes a frequency conversion means according to the present invention for converting the sampling frequency of the decision data Rn to the higher frequency used as the sampling frequency. In this system, although the equalization circuit 1 and the carrier phase control circuit 2 are operated by (at) the sampling signal having the frequency fs, the decision circuit 3 is operated by the baud-rate frequency fb. Accordingly, it is necessary to convert the frequency of the decision data. Rn to the sampling frequency fs to obtain the difference signal Δ and feed back the difference signal Δ to the equalization circuit 1 and the carrier phase control circuit 2. The sampling frequency in this system can be converted to a frequency at least double the baud-rate frequency as explained hereinafter. Figure 3 is a schematic block diagram of a digital signal processing system according to an embodiment of the present invention. In Fig. 3, the frequency conversion means is constituted by a second decision circuit 41 for obtaining a frequency double the baud-rate frequency fb as the sampling frequency fs, a delay element (T) 42 having a register for delaying decision data Rn, and a switching device 43 for switching the decision data Rn and intermediate decision data Rd and obtaining the sampling signal having a frequency double the baud-rate frequency fb. In this case, the frequency conversion means 4 of this embodiment is applied to the base band signal Xn demodulated from the reception signal having a roll-off (ROF) rate of 100%. The operation of the digital signal processing system according to the present invention is explained in detail hereinafter. In Fig. 3, the decision circuit (DEC(1)) 3 generates the decision data Rn after deciding the correction signal Yn. The decision of the correction signal Yn in the decision circuit 3 is performed by comparing an ideal point of reception with a reception point corrected by the carrier phase control circuit 2 on a complex coordinate. The decision circuit (DEC(2)) 41 in the frequency conversion means 4 calculates an intermediate point A (see, Fig. 4) between the decision data Rn from the decision circuit 3 and the before decision data Rt delayed by the delay element 42 as explained in detail in Fig. 4. The switching device 43 generates the sampling signal Sn having a double baud-rate frequency by alternately switching the decision data Rn and the intermediate decision data Rd. The sampling signal Sn is input into the calculation circuit 14 and the difference signal Δ between the correction signal Yn and the sampling signal Sn is fed back to the equalization circuit 1 and the carrier phase control circuit 2 so that the difference signal becomes zero. Accordingly, it is possible to compensate the amplitude and delay of the base band signal Xn demodulated from the reception signal, and to correct the phase distortion in the equalization circuit 1 and the carrier phase control circuit 2 based on the difference signal Δ. Figure 4 is a view for explaining the intermediate point of the impulse response curve. "P2" denotes the point of the present decision data Rn and "P1" denotes the point just before decision data Rn. "A" denotes the intermediate point and "P" an amplitude. The point A is located at half of the amplitude P. The sampling frequency fs having a double baud-rate frequency can be obtained by switching the switching device 43 as explained below. Figure 5 and 6 are curves for explaining the roll-off rate (ROF). The roll-off rate ROF can be expressed by following formula. ROF = (α/1 x 100%) where, "1" is a frequency from "0" to "fc" (fc denotes a half amplitude point), and α is a difference frequency from "f1" to "fc" (f1 denotes a trailing edge of the amplitude curve). Accordingly, when the interval "1" is equal to the interval "α" as shown in Fig. 6, the roll-off rate ROF becomes 100% based on the above formula. Each of the impulse response curves shown in Fig. 4 has a roll-off rate of 100%. Three roll-off filters are provided in the system. That is, the first roll-off filter (ROF 1) is provided in the transmission system. The second roll-off filter (ROF 2) is provided for the inner or previous stage of the equalization circuit 1 in the reception system. The third roll-off filter (ROF 3) is provided in the interpolator shown in Fig. 8. The relationship among these roll-off filters is given by; ROF 1 x ROF 2 = ROF 3 Figure 7 is a view for explaining the sampling frequency of double the baud-rate frequency. The waveform (A) denotes a baud-rate frequency fb, for example, fb = 150 Hz. The baud-rate frequency fb is expressed by a reciprocal of a modulation rate. (B) denotes digital data train to be transmitted at the baud-rate frequency fb. (C) denotes impulse response curves each having a roll-off rate of 100%, corresponding to the digital data. (D) denotes a curve obtained by the connection of each of the point of the decision data from the decision circuits 3 and 41. (E) denotes the resultant digital data from each decision circuits 3 and 41. The data Rn is obtained from the decision circuit 3 and the data Rd from the decision circuit 41. (F) denotes the sampling frequency fs obtained from the data Rn and Rd. As is obvious, the sampling frequency fs is given by a frequency double the baud-rate frequency fb shown in (A). As explained above, in this embodiment, the base band signal demodulated from the reception signal or pass band signal having a roll-off rate of 100% can be processed by the sampling signal fs having a double baud-rate frequency fb. Accordingly, it is possible to easily suppress the phase jitter caused by the doubling of the power source frequency, based on the higher sampling frequency than the baud-rate frequency. Figure 8 is a schematic block diagram of a digital signal processing system according to another embodiment of the present invention. In Fig. 8, the frequency conversion means 4 of this embodiment is constituted by an interpolator 44. The frequency conversion means 4 of this embodiment is applied to the base band signal demodulated from the reception signal regardless of the previous roll-off filters (ROF 1) and (ROF 2). The interpolator 44 operates as a filter and generates a sampling frequency higher than the baud-rate frequency by multiplying the decision data Rn from the decision circuit 3. The calculation circuit 14 calculates the difference signal between the correction signal Yn and the output In from the interpolator 44, and the difference signal Δ is fed back to the equalization circuit 1 and the carrier phase control circuit 2 so that the difference signal becomes zero. Figure 9 is a view for explaining the difference signal output from the calculation circuit 14 shown in Figs. 2, 3 and 8. In Fig. 9, the ordinate is an imaginary part, and the abscissa is a real part. The reference letter In is the output of the interpolator 44 and Yn is the output of the carrier phase control circuit 2. The symbol Δ is the difference signal between the output In and the output Yn. It is necessary to reduce the difference signal by feeding back the difference signal to the equalization circuit 1 and the carrier phase control circuit 2. Figure 10 is a detail block diagram of the interpolator shown in Fig. 8. In Fig. 10, 441 is a zero insertion circuit, and 442 is a roll-off filter. The zero insertion circuit 441 receives the decision data Rn from the decision circuit 3, and outputs a switch signal Pn. The roll-off filter 442 receives the switch signal Pn, and outputs a filtered output In. Figure 11 is one example of the zero insertion circuit, and Figure 12 is a view for explaining the relationship between the decision data Rn and the switch signal Pn. In Fig. 11, the zero insertion circuit is constituted by a switching means SW having a plurality of terminals corresponding to the sampling number. When the switch is positioned at the terminal 1, the decision signal Rn is output from the circuit 441 as the switch signal Pn. When the switch is switched to other positions, the switch signal Pn becomes "0" as shown in Fig. 12. Figure 13 is one example of the roll-off filter 442, and Figure 14 is a view for explaining the filtered signal In. In Fig. 13, the roll-off filter 442 is constituted by a transversal type filter. The switch signal Pn is input into a first delay element T/m, and transferred sequentially after a predetermined delay time at each delay element T/m. Qk is a coefficient of the roll-off filter, and coefficient Qk is multiplied by each output of the delay element T/m. The filtered signal In is given by the sum of the multiplication Qk x Pn - k. In Fig. 14, T is a baud-rate period, and T/m is a sampling rate. For example, when the baud-rate period is 2400 bps and the sampling rate is 9600 bps, T/m is given by T/4. Accordingly, m/T denotes the sampling frequency. The curve shown in Fig. 14 shows the filtered signal In at each coefficient Qk. Figure 15 is one example of the equalization circuit 1 constituted by the transversal type filter having a shift register. This circuit is mainly used for compensating the signal delay distortion and the amplitude distortion on the line. The base band signal or pass band signal Xn is input to the delay element t/m, and the input signal is sequentially transferred after the predetermined delay in each delay element T/m. Ck is a tap coefficient at each delay element and multiplied by each output of the delay element T/m. The equalization signal Hn is given by the result of the multiplication Ck x Xn - k. In this case, Co is a center tap. Figure 16 is one example of the carrier phase control circuit for correcting the phase shift of the carrier. The equalization signal Hn is multiplied by the coefficient e jn , and outputs the correction signal Hn. Figure 17 is one example of the decision circuit 3. In Fig. 17, the decision circuit 3 is constituted by a read only memory ROM having a predetermined table. The decision data Rn is stored in the table.

Claims: A digital signal processing system in a modem, comprising: signal recovering means (1, 2) comprising at least an equalization means (1) for compensating amplitude and delay distortion of a base band signal (X n ) demodulated from a reception signal or pass band signal in the modem; a decision means (3) operatively connected to said signal recovering means (1, 2) and operated at a predetermined baud-rate frequency (f b ) for generating decision data (R n ) from said base band signal (Y n ) ; a calculation means (14) operatively connected between said signal recovering means (1, 2) and said decision means (3) for obtaining a difference signal (Δ), said difference signal (Δ) being fed back to said signal recovering means (1, 2) so that said difference signal (Δ) becomes zero; characterised in that said signal recovering means further comprises a carrier phase control means (2) operatively connected to said equalization means (1) and operated at a predetermined sampling frequency (f s ) higher than said predetermined band-rate frequency (f b ) for correcting a phase shift of said base band signal; and in that the system further comprises a frequency conversion means (4,44) operatively connected to said decision means (3) for converting the rate of said decision data from said predetermined band-rate frequency (f b ) to said predetermined sampling frequency (f s ) ; whereby said difference signal (Δ) represents the difference between an output (S n ) of said frequency conversion means and an output (Y n ) of said carrier phase control means so that said equalization means (1) compensates the amplitude and the delay distortion of said base band signal, and/or said carrier phase control means (2) corrects the phase shift of said base band signal, by using said difference signal (Δ) at the predetermined sampling frequency (f s ). A digital signal processing system as claimed in claim 1, wherein said frequency conversion means (4) comprises a second decision means (41) which is operated at said predetermined sampling frequency so as to perform detection of said decision data (R n ) and of intermediate points (R t ) thereof. A digital signal processing system as claimed in claim 2, wherein said frequency conversion means (4) comprises: a delay element (42) for delaying said decision data (R n ) and outputting delayed decision data (R t ), said decision data obtained from said base band signal demodulated from said reception signal having a roll-off rate of 100 %; said second decision means (41), which is arranged for inputting said decision data (R n ) and said delayed decision data (R t ), obtaining an intermediate point between present decision data and delayed decision data just before said present decision data, and outputting intermediate decision data; and a switching means (43) for switching between said decision data and said intermediate decision data, and obtaining a frequency at least double said baud-rate frequency (f b ) used as a sampling signal having said predetermined sampling frequency (f s ). A digital signal processing system as claimed in claim 1, wherein said frequency conversion means (44) comprises an interpolator for generating a sampling signal having said predetermined sampling frequency (f s ) based on said decision data (R n ).

Inventors: ENDO KYOKO, KAKU TAKASHI, ENDO, KYOKO, KAKU, TAKASHI, ENDO, KYOKO FUJITSU DAIICHI NAKAHARA, KAKU, TAKASHI LIONS MANSION TAMA CENTER
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H04L27
IPC codes: H04L27, H04B7, H04L25