CONTROL FOR A ROTATING MEDIA STORAGE SYSTEM

Abstract: The present invention is directed to a control system for a rotating media storage device. The rotating media storage device includes a control board having a ROM to store a basic power up control program, one or more processing means for control of the storage device and communication between the storage device and the host computer and a read/write memory means such as a RAM. When the storage device is powered up, the basic code in ROM initializes the control system, activates the rotating storage media, and accesses a control code stored on the storage media. This permits changing and updating of the control program simply by writing to disk and transferring the new program into the RAM for execution. In addition, it is not necessary to power down the drive in order to change the control program. The control system of the present invention includes a dual processor architecture for distributed control of storage device operations. Communication between the processors is accomplished on a microwire utilizing a novel communications protocol which permits high speed processing of individual distributed functions and high speed communication between the processors. The present invention provides a serial port coupled to the processors and used to implement a test environment with a host computer. Emulation code can be downloaded to the storage device to the serial port and stored in the RAM memory.

Description: II "Control for a Rotating Media Storage System' BACKGROUND OF THE PRESENT INVENTION: 1. FIELD OF THE PRESENT INVENTION This invention relates to the field of disk drives and to a method of providing onboard control to a disk drive system. 2. BACKGROUND ART Many computer systems utilize rotating media storage devices as a means of providing mass storage for data and other information. These storage devices may employ magnetic, optical, magneto-optical or other types of media for information storage. The storage device typically communicates with the host computer system through an interface, such as a small computer system interface (SCSI), ST-506 (J.D. check number) or ESDI. In the prior art, control or storage device functions and communications were handled by the host computer. This placed additional burden on the host computer system and limited performance of the storage devices. One method of improving a performance of the storage device is to make it a "smart" device. In other words, processing means were provided on the storage device itself to handle certain control functions and communication with the host computer system. Thus, prior art storage devices may include a processor on a control board for controlling certain functions of the operation of the storage device. This processor is controlled by a program (firmware) typically stored in read only memory, such as a ROM, EPROM or EEPROM. The manufacture of a disk type storage device, such as a Winchester type hard disk drive which utilizes such onboard control, requires that a control program be prepared and debugged to govern operations of the processor. An EPROM is then manufactured to store the control program on the control board or provide the programming to the processor when the storage device is active. This control program is burned into the EPROM and the EPROM is then soldered onto a control board in the storage device. One disadvantage of this prior art method of manufacturing disk drives is the fact that the EPROM must be removed from the board to correct any errors or mistakes in the control program. Additionally, when running emulators (testers) on the storage device, it is necessary to replace the control program with an emulation program, again requiring the opening of the storage device. Typically, storage devices are original equipment manufactured devices (OEM) which are tailored to each purchaser's particular package, therefore, for different purchasers , different control programs must be prepared, debugged and embedded in an EPROM before inserting onto a control board in a disk drive. Because of the difficulty of changing control programs and the expense and time associated with updating and changing control programs, there is an incentive to minimize the size of the control program, therefore minimizing the sophistication and intelligence of the onboard control of a memory storage device. That is, the fewer the number of lines of code in the control program, the less likely there will be bugs in the program. Therefore, the very nature of the prior art method of implementing control programs, limits the size and effectiveness of the program- It is also desired to reduce the size of the physical package comprising the storage device, while still improving the performance, features and capacity of the storage device. One method of reducing the physical size of the storage device is to reduce the size of the control board within the storage device. This may offer a lower profile storage device, or permit additional area to be dedicated to storage. One method of reducing the size of the control board is to pack individual components on the control board more tightly, or to condense functions and combine functions into a single component. Further, there are methods of mounting components on a control board which reduce the height of the control board and thereby provide space advantages. For example, by using a "surface mount" technology, a lower profile control board may be achieved. However, one disadvantage of surface mount technology with respect to control boards for storage devices is the fact that a surface mounted device cannot be easily removed from the board. Further, it is not possible to attach a probe to a surface mount device without running a high risk of breaking the connection leg from the device. If the control board processor cannot be removed, then the entire board must be replaced when the control program is changed. Without the ability to mount a probe to the processor, testing and emulation cannot be performed. In the prior art, testing of a storage device requires a single host computer for each storage device. Probes are coupled to the processor on the storage device and coupled to emulation hardware so that single step, break point and disassemble instructions can be utilized. Because probes cannot be attached to surface mount technology, it has not been possible in these prior art storage devices to utilize surface mounting. One approach to the use of surface mount technology is to provide an onboard emulator hardwired to the processor to single step and disassemble instructions. However, this takes up valuable board real estate and adds to the expense and complexity of the storage device. In storage devices with an onboard processor, it is desired to have the processor handle as many of the control functions as possible. This frees the host computer from such functions and improves the operation of the host system. There are two principal areas of control which have been allocated to onboard processors and prior art storage devices, namely interface control and device operations. Interface control includes communication with the host computer through the particular type of communication interface used in the computer system. For example, if a SCSI interface is used, the processor monitor the SCSI bus and looks for communication from the host computer system. Device operations entails management of the storage device itself such as rotation speed for rotating media, system, and read/ write head position, etc. In order to keep the cost of a storage device low, and to obtain size advantages, off the shelf, commercially available processing units are typically used as onboard control means for the storage device system. Because these commercially available processing units are not optimized for storage device operation, their performance often becomes a bottleneck to improved device efficiency. Storage device efficiency could be improved by making custom control units for the storage device, but this has the disadvantage of adding cost to the device. Therefore, it is the object of the present invention to provide a method of providing a control program which permits easy updating and replacement of the control program. It is yet another object of the present invention to provide a method of providing a control program whose ease of implementation and updating encourages sophisticated and complex programming. It is yet another object of the present invention to provide a method of providing a control program which may be easily updated without opening the disk drive itself. It is still another object of the present invention to provide a control board which takes advantage of optimum mounting technologies, such as surface mount technologies while still retaining emulation and testing capabilities. It is still a further object of the present invention to provide a storage device which utilizes commercially available control units while providing improved operating efficiency. SUMMARY OF THE PRESENT INVENTION The present invention is directed to a control system for a rotating media storage device. The rotating media storage device includes a control board having a ROM to store a basic power up control program, one or more processing means for control of the storage device and communication between the storage device and the host computer and a read/write memory means such as a RAM. When the storage device is powered up, the basic code in ROM initializes the control system, activates the rotating storage media, and accesses a control code stored on the storage media. The control code is transferred to the onboard RAM through a suitable interface, such as a SCSI connection. The control program of the storage device then executes from the RAM based control program. This eliminates the need for a "firm ware" based control program realized in an onboard EPROM. This permits changing and updating of the control program simply by writing to disk and transferring the new program into the RAM for execution, h addition, it is not necessary to power down the drive in order to change the control program. The control system of the present invention includes a dual processor architecture for distributed control of storage device operations. A master processor controls and monitor communication with a host computer system through a communications interface. In one embodiment of the present invention, the interface comprises a SCSI bus. A second "slave" processor controls device operations such as rotation speed, read/ write head position, and seek operations. The dual processor scheme of the present invention utilizes commercial processing units. Communication between the processors is accomplished on a microwire utilizing a novel communications protocol which permits high speed processing of individual distributed functions and high speed communication between the processors. To reduce the physical size of the storage device of the present invention, surface mount technology is employed for the control board architecture. Because this technology inhibits the use of probes for testing on the control board processors, the present invention provides a serial port coupled to the processors and used to implement a test environment with a host computer. Emulation code can be downloaded to the storage device to the serial port and stored in the RAM memory. This provides the ability to single step through programs and set break points, and disassemble instructions of the microprocessor while it is running out of the RAM memory. Because the microprocessor is running out of the RAM there is no need for external hardware to provide these break points and disassemble instructions. The use of a serial port and novel testing protocol permits the "daisy chaining" of a plurality of storage devices for testing and emulation with a single host computer. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a prior art storage device. Figure 2 is a block diagram of the present invention. Figure 3 is a block diagram of the system memory map of the present invention. Figure 4 is a block diagram of the master and slave processor of the present invention. Figure 5 is a timing diagram illustrating a normal command sequence of the present invention. Figure 6 is a timing diagram illustrating command with status return of the present invention. Figure 7 is a timing diagram illustrating an error handler of the present invention. Figure 8 is a block diagram illustrating a test configuration of the preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PRESENT INVENTION A control system for a rotating media storage device is described. In the following description, numerous specific details, such as program length, RAM capacity, etc., are described in detail in order to provide a more thorough description of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known features have not been described in detail in order not to obscure the present invention. The present invention is directed to a control system having method and apparatus for controlling the operation of a storage device, communication between the storage device and a host computer system, provision of control programming, and distribution of control functions. The following description of the present invention is made in connection with a Winchester type hard disk drive storage device. The disk drive includes one or more rotating storage disks, a read/write head for reading and writing information on storage tracks On a disk surface, a control board which includes architecture for controlling operation of the disk drive, and an interface for communication between the disk drive and a host computer. Although the present invention is described in connection with a hard disk drive system, it would be apparent, to one skilled in the art, that the present invention has equal application to any type of mass storage device which requires communication to a host system and control of storage device capabilities. For example, the present invention is not limited to rotating media type storage devices or magnetic media devices, but has application to optical, tape and other storage devices as well. BACKGROUND Figure 1 illustrates a block diagram of a prior art control system of a disk drive. The control board 12 is coupled to the disk drive 10 through 5 control lines 17 and 18. The control for the disk drive 10 is provided by processor 16 which is coupled to the disk through bus 18. Programming for the processor 16 is contained in EPROM 15 coupled to processor 16 through line 21. The processor 16 is coupled, through line 19, to a small computer systems interface (SCSI) bus 14. The SCSI bus 14 is coupled to a RAM buffer 10 13, through line 22. The RAM buffer is coupled to disk 10, through input/ output line 17. The disk 11 includes a user area 32 and a reserved special area (SA) 23. The special area 23 on prior art drives is typically reserved for diagnostics 15 and/ or calibration benchmarks, or is a parking area for the read/ write heads. The prior art disk drive of figure 1 is locked into the control program provided in EPROM 15. If it is desired to update or change the control programming for the disk drive, the entire EPROM 15 must be replaced. This requires that the drive be powered down and opened up. Of course the 20 disk drive is unusable during mis down time which can be often be substantial. PRESENT INVENTION 25 In the preferred embodiment of the present invention, a "soft loading" technique is utilized to provide a control program to an onboard processor- In the environment of a disk drive, the control program is stored on a hard disk in a restricted area of the disk surface, not accessible by the user. A control program kernel is stored in a small ROM on the control board to handle startup. On power up of the disk drive, the kernel drives the actuator to position the read/write heads over the control program location on the disk surface. The control program is then downloaded into a RAM on the control board. The control program kernel is used to verify the control program downloading and then operation of the processor is handed over to the stored control program in RAM. By utilizing this soft loading technique, the prior art disadvantages associated with the use of an EPROM stored firmware are eliminated. For example, because of the ease of updating the control program, debugging is cheaper and easier than with prior art firmware control programs. Thus, longer and more sophisticated programs are encouraged, improving disk operations. Further, it is easy to customize the control program for different purchasers, permitting the manufacturer of low volume "custom" disk drives utilizing specialized control programs which might otherwise be prohibited by the expensive EPROM development. Further, for upgrades to an operating control program it is not necessary to power down the drive. Upgrades can be copied onto the drive and booted into the onboard RAM. This reduces down time and improves disk operation and efficiency. In addition to a SCSI interface, the control board of the present invention utilizes a serial port coupled to the processing unit of the drive. The serial port permits the downloading of new control programs, emulation code and testing procedures. Emulation and testing programs can replace the control program in the RAM, permitting the use of programs to set break points, disassemble instructions and single step through disk processes. This eliminates the need for an onboard emulator or the connection of probes to the onboard processing units. This allows the use of surface mount technology since no external physical connection is required to the processing units. A special protocol allows a plurality of disk drives to 12 be daisy chained together for testing purposes with each disk drive assigned a slot on the chain so that test commands and responses can be differentiated between the plurality of drives. This improves the efficiency of manufacturer of drives since only a single host computer is required for a plurality (e.g. up to 254) drives. The preferred embodiment of the present invention utilizes distributed control by dividing a master processor for SCSI interface control and a slave processor for disk operation control. The slave processor monitors rotation speed, head position and seek operations. The master processor monitors the SCSI bus and controls communicating between the drive and host computer. To take advantage of the added speed which this architecture allows, a novel protocol for communication between the processors on a microwire is implemented in the preferred embodiment of the present invention. The master and slave processor in the preferred embodiment of the present invention are National Semiconductor HPC 46083 microcontrollors running at 24 megahertz. When the master processor wants to communicate with the slave processor, the master processor outputs a ready signal to the slave processor. The slave processor initializes and sends back a ready signal to the master processor. The master processor then sends a command byte to the slave processor and the slave processor responds with a status signal. Because of the distributed control functions of the master and slave processor, seeks can be performed more quickly than in prior art devices. Because the slave processor is constantly monitoring the head position and speed, when a seek command is received from the master processor, the seek can be implemented immediately. At the same time, the master processor can be communicating with the host computer, either obtaining information for the next seek or providing status or other information to the host computer. Because only a single processor is used on the prior art control board, certain inefficiencies are inherent in the operation of a prior art disk drive. For example, when a single processor is used to interface on the SCSI bus with a host computer, servo control is abandoned. When a seek command is received, the processor must first obtain servo status before beginning the seek operation. Referring now to Figure 2, a block diagram of the preferred embodiment of the present invention is illustrated. The control board 12 of the present invention includes two processors. Master processor 24 and slave processor 25 are both utilized to provide control over different aspects of the disk drive function. Master processor 24 is coupled to the disk drive through a SCSI bus and RAM buffer interface. The master processor 24 is coupled on line 29 to the SCSI bus 14. The SCSI bus 14 is coupled on line 22 to RAM buffer 13 and in turn to input output line 17. The master processor controls the SCSI interface and communication between the host computer system and the disk drive. The slave processor 25 is coupled to the disk drive 10 through connection 18 through line 18. The control board 12 includes a serial port 27 coupled to master processor 24 through line 30. A boot ROM 28 is coupled to slave processor 25 through line 33. The master processor is also coupled on line 29 to RAM 26. The slave processor monitors disk drive status and operations, such as rotation speed, head position and execution or seek commands. A serial port 27 is coupled to the master processor 24 through line 30. On power up, the ROM boot 28 provides basic code in order to initialize the SCSI interface, spin up the disk, read the control program into the RAM space and execute from the RAM based control program. The ROM boot 28 consists of the following code in address range FFFF-EOOO: 1. Simplified diagnostics 2. Microwire interface (communications with servo) 3. Basic flaw management (format of SA "save area") 4. Partial emulation code (init UART and load rest of emulation code) 5. Support SCSI bus phases 6. Support of RESET and NMI interrupts 7. Support the following SCSI commands: a. REQUEST SENSE b. READ DEFECTS LIST c. DOWNLOAD d. UPLOAD e. START EXECUTION f. INSTALL g. FORMAT h. READ SBL i. DIAGNOSTICS The program code loaded from the special area 23 is mapped to the following areas of the RAM 26 as illustrated in Figure 3. 1. Address 6000-61FF, Soft boot label area (512 bytes) 2. Address 6200-6220, interrupt vector table (32 bytes) 3. Address 6300-6400 JSRP, vector table for emulation code (256 bytes) 4. Address7000-BFFF, real firmware (20K bytes) 5. Address COOO-DFFF, emulation code (8K bytes) The soft boot label area contains revision, documentation numbers and other specific information about soft boot firmware. The interrupt vector table area is for all interrupts other than reset. The JSRP vector table area is for the emulation code interrupt table that is in use when emulation code is invoked. The "real" firmware supports all SCSI commands, all error-handling and normal disk operations. The monitor area is for diagnostic capabilities of customized control programs, and debugging the controller. When power is applied to the disk the ROM based code in the ROM boot 28 does the following: 1. Initialize the PROCESSOR 2. Initialize the SCSI interfaced 3. Initialize the microwire interface 4. Send diagnostic command down microwire I/F 5. Test Interface RAM area 6. Quick ROM Check 7. Spinup Disk 8. Read soft boot area and check for validity IF VALID 9. Read code into 32K RAM 10. Check some RAM to verify good transfer of code 11. Jump to code in 32K RAM 12. Wait for command. IF NOT VALID 9a check set condition and status byte. 10a Set additional sense byte to (hex) to be SBNV 11a jump back to limited command set in 8K ROM The soft boot area 23 on the disk is first loaded with a label. The label indicates validity, has numbers for revision and documentation and a production ID code. Immediately following this label is the code. The label and code are written in three separate areas within the soft boot area. The soft boot label format includes the 16 bytes of signature, revision number (16 bytes), documentation number (16 bytes), production ID number (16 bytes) and 122 to 326 bytes for an ASCI string for right notices, ownership notices, etc. The NMI interrupt, located in the 8K ROM initializes the processors UART port and allow the download of the rest of the emulation code. This will load into the monitor area of the 32K RAM via serial port 27 on PC to the processors UART port and then start the eulation code functions. The preferred embodiment of the present invention includes diagnostics on powerup which consist of initialization of the processors, SCSI interface chip, and microwire interface. The memory tests are basic reads/write O's and l's to SCSI memory and to the 32K RAM. To test the microwire interface there is a diagnostic command sent to the servo and echoed back. The commands are as follows: Command OP Code Description Request sense 03 Read defect list 37 Read the P list defects Download 35 From SCSI to RAM (Intel hex format) Upload Start Execution location Install 38 Load from where to disk Format SA 39 Format disk soft boot area Read SBL 3A Read soft boot label area to RAM Diagnostics 3B Run extended controller diagnostics In the preferred embodiment of the present invention, these are the only commands the controller accepts after a power on or reset until the code is loaded from the soft boot area if valid. If the soft boot area is not valid, the SCSI status byte will indicate a check condition. The OP code assignments are given by way of example of the preferred embodiment only. The OP code assignments can be shifted without departing from the scope of the present invention. When the host computer system issues a request sense command, the extended sense data returned will have a hex 2B in the additional sense byte indicating SBNV (soft boot not valid). The install command takes raw data from the RAM area starting with the label and loads all 32K bytes to the disk in the soft boot save area. Once loaded the disk will switch heads and start the same process over again. This process continues until there are three copies of the 32K RAM in soft boot area on the disk. Download command uses Intel hex format in the preferred embodiment of the present invention. The command strips the information bytes and loads 32K RAM with the data. The check sum is calculated and then checked with the checks sum bytes given by the Intel hex format to insure good data. The check sum is calculated by adding all bytes except begging of line marker, then taking the 2's complement of the sum. Upload command takes the raw data in 32K RAM and inserts the control fields for the intel hex format. The areas uploaded will be soft boot label and interrupt vector table, address range 6000-6220, and firmware, address range 7000-BFFF. Format SA command will format only the area on the disk which has the flaw map, soft boot label and firmware. It uses the P list to support some basic flaw management for defective areas within this special area 23. This area is formatted to 512 bytes per sector. Read defect list command transfers the P list in "bytes from index" format that was prerecorded on the disk from the factory to the host. Attempting to read the G-list or another defect list format causes an error setting a check condition status. This sets a sense key of "5" and the additional sense code to "24" (hex). The interrupt vectors are fixed locations in the boot ROM 28 . The vectors point to locations in the 32K RAM area 26. Since RAM comes up in an unknown state, the vectors must be initialized by whoever is going to use these vectors. The ROM boot code sets the NMI interrupt vector to point into 8K ROM space to invoke the emulation code. The emulation code must initialize it's vectors including NMI to point to its own routines for handling interrupts. The 32K RAM based firmware must load these vectors to allow normal disk operations. MICROWIRE F TERFACE The preferred embodiment of the present invention utilizes National Semiconductor HPC 46083 microcontrollers. However, any suitable 5 microcontroller can be utilized in the present invention. The connection of the master and slave processors is illustrated in figure 4. Voltage VCC is coupled through resistor Rl to master processor 24 and slave processor 25 at node 32. Number 32 is also coupled through 10 capacitor Cl to ground. Node 32 is coupled to the master and slate processors at the reset inputs. The master processor 24 sends commands to the slave processor 25 and the slave processor 25 provides status to the master processor 24. The master processor 24 signals the slave processor 25 that a command is to be sent by setting line 37 high. SCMD (SCSI command) 15 line and is provided to pin in PO of master processor 24 and inputed to pin D7 of processor 25. When the slave processor 25 is ready to receive a command it outputs a ready signal SRDY on line 34. The slave processor 25 ouputs a signal on pin PO and the master processor 24 receives it on pin D7. If there is an error, the slave processor 25 outputs a signal on Par line CERR 20 33. Line 33 is coupled to the processor at pin PI and to the master processor at pin D6. A clock signal SCLK is provided to the master and slave processor on line 36 at pin B6. After the command is received, if a status signal is required, the slave processor 25 outputs a status signal SSTAT on line 38 to the master processor 24. The signal is provided at pin B5 of slave processor 25 25 and inputed to pin SI of master processor 24. Data signal SDATA is provided on line 35 from pin SI of slave processor 25 to pin B5 of master processor 24. 20 The communication between processors is performed when the master processor requests information, seeks to cylinder, diagnostics, spins up/ down the drive, etc. to the slave processor. The communication link is performed with the microwire interface on each processor. The master processor is the master microwire, and the servo processor is the slave. All commands in the preferred embodiment are 16 bits in length, and all returned status is 16 bits. Status is only returned on the master processor sending a status command. The most significant bit of the status/command word is always sent first, the least significant bit (0 placement bit) is sent last. COMMUNICAπON SIGNALS: The microwire has an eight bit serial shift register, all commands and status are 16 bits. The slave processor asserts SRDY active high when it is ready to accept a command. SRDY asserts low after the first command byte has been received. The master processor then sends the final command byte. When SRDY is high, the operation is complete (seek complete or status read). During a status operation, the master processor reads the MSB (byte) or first byte of status, the slave processor asserts SRDY low and the second byte is read by the master processor. SRDY returns high after the last bit is read. When the master processor sets SCMD high, the master processor monitors an asynchronous SERR set high. SERR high indicates to the master processor that status should be performed to determine a fault condition. SCMD drops low and the master processor sends a command to receive status. After the last byte of status is sent from the servo processor, SERR returns low. SERR is asserted high for any fault condition that the master processor should be aware of. Microwire clock frequency is programmed to: SK = 24MHz/ 19 = 1.26 MHz or 160 Kbytes/sec Assuming about lOOus of processor overhead, one command word can be sent in: . 2* (l/160kbs) + lOOus = 112usec. COMMAND WORD: (MSB) (LSB) bl5 bl4 bl3 bl2 bll blO b09 b08 b07 b06 b05 b04 b03 b02 bOl bOO <COMMAND FLD> < DATA FIELD > Command Field Data Field OHz - spin up disk OOOHx lHx - spin down disk OOOHx 2Hx - seek Cylinder address <11:07> 0 to 4095 3Hx - thermal head Head address <11:0> 0 to 3 4Hx - Track offset Offset amount <11:0> 0 to 3 5Hx - Diagnostics echo number <11:0> 0 to 4095 6Hx - Status OOOHx THx - read sector stat OOOHx 8Hx - read track stat OOOHx 9Hx - set sector size, band 0 sector size in bytes <11:0> AHx - set sector size, band 1 sector size in bytes <11:0> Echo Number Status: (MSB) (LSB) bl5 bl4 bl3 bl2 bll blO b09 b08 b07 b06 b05 b04 b03 b02 bOl bOO < Echo Number <:0> > Read Sector Status: (MSB) (LSB) bl5 bl4 bl3 bl2 bll blO b09 b08 b07 b06 b05 b04 b03 b02 bOl bOO < send Sector Number (RPS) <11:0> > Read Track Status: (MSB) (LSB) bl5 bl4 bl3 bl2 bll blO b09 b08 b07 b06 b05 b04 b03 b02 bOl bOO < Echo Track Number (RPS) <15:0> > Read Status: (MSB) (LSB) bl5 bl4 bl3 bl2 bll blO b09 b08 b07 b06 b05 b04 b03 b02 bOl bOO bl5 - reserved bl4 - reserved bl3 - reserved bl2 - reserved bll - reserved blO - reserved b09 - spindle motor stopped by stop command b08 - power on reset condition exists b07 - reserved b06 - interface fault b05 - invalid command or unimplemented b04 - seek fault b03 - write gate with track offset fault b02 - reserved bOl - write fault bOO - reserved MICROWIRE INTERFACE FOR HPC The microwire I/F is used to communicate between the master processor and the slave processor, thus we have the Master (SCSI) and the Slave (SERVO). Upon reset condition, Power up or otherwise, the Slave waits for the Master to initialize first. This is signaled to the Slave by way of SCMD line going high Then the Slave can be initialized. The last thing the Slave does before it leaves its initialization is to clear the uWIREDONE flag, by writing to the SIO register. For a transfer: Slave waits for SCMD to go low. Indicating master wants to send a command. Master waits for SRDY to go hi. Set by slave when he's ready. Master sends first byte...and wait for uWIREDONE flag to be set. Slave waits for uWIREDONE flag to be set then reads the first byte from SIO. Slave resets uWIREDONE flag by writing to SIO reg. Slave sets SRDY low for second byte. Master waits for SRDY to go low. Master sends the second byte...and waits for uWIREDONE flag to be set. Slave waits for uWIREDONE flag to be set then reads the 2nd byte from SIO. Slave then resets uWIREDONE flag by writing to SIO reg. At this point, the Master and Slave determine which command has been sent. Depending on the command the Slave takes information from the rest of the command and responds to it with action or returns Status. In any event: Master waits for SRDY When slave is done with the action or has status ready Slave then sets SRDY high. If no status- Master checks for SERR to be high..meaning there is an error If no error... Master sets SCMD high. A command sequence is illustrated in Figure 5. The master processor pulls SCMD line low as shown at falling edge 50 to signal the slave processor that it is ready to send a command. The signal SRDY is set high by the slave processor as shown at rising edge 40 to indicate that slave processor is ready to receive the command. In the preferred embodiment, the first eight bits of the command are sent as shown by clock signal SCLK. The slave processor then sets SRDY low at falling edge 47 to indicate that the slave is ready to receive the second byte of the command signal (SCLK) and the command signwal SCMD goes high at rising edge 39 to indicate that the master is done sending the command. If no error is detected, the error signal SERR stays low. Referring to Figure 6, a command with status return is illustrated. As before, the master processor pulls SCMD line low as shown at falling edge 50 to signal the slave processor that it is ready to send a command. Signal SRDY is set high at rising edge 40 by the slave processor to indicate to the master that a command may be sent. The command sent, command 60 of SCLK, signals a status request command. The SRDY signal is pulled low at falling edge 41 and SCMND is set high at rising edge 51. The end of status command, command 00 of SCLK is transmitted and the SRDY signal is set high to flag the coming status information. The status, commands XX on SCLK, is provided to the master processor in two parts. The first byte is sent when SRDY is high. After SRDY is set low at falling edge 43 the second status byte is transmitted and SRDY is pulled high at rising edge 44 to signal the end of status Figure 7 illustrates error handling in the protocol of the present invention. SCMD is set low at edge 50 in preparation of sending a command. However, during command transmission, an error occurs and SERR is set high by the slave at rising edge 52. At this point, the slave and master repeat the process described with respect to Figure 6 in that the master asks for status regarding the error. Error status is sent in two bytes on high and low phases of the SRDY line. TESTING ENVIRONMENT The burn-in environment discussed in this specification makes use of he onboard microprocessor and serial interface of the disk drive to achieve a low cost test environment that has a high degree of automation and data collection. The diskdrive control program or the preferred embodiment of the present invention supports a simple LAN (local area network) environment. This support can be in the form as a special burn-in version of the firmware that contains the LAN support and several canned diagnostic routines that are referenced via the LAN by the master computer. Command Packet Format: Address Count Command Checksum Field Description Address 8 Bit Address Field - supports 256 addresses, with address OOh reserved for the host AT processor, and address FFh reserved for accessing all drives, allowing a maximum of 264 drives tested per AT serial communication port. Count 8 Bit Count Field - allows 4 to 256 byte transfers. Command 8 Bit Command Field - allows 256 commands. Checksum 8 Bit Checksum Field - checksum modulus 256 checksum code. This command format allows a single host AT to address one or all of the drives under test, and allows the drive under test to send response back to the host AT (address OOh). With 256 commands available, many may be reserved for "macro" commands, special testing sequences that may include a downloaded parameter table to control/alter each macro. Packets can be sent in as small as four bytes (address, count, command, and checksum) for single command operations (poll, reset, power-on, etc.), and for more complex command strings (if command chaining is included, command length can be near infinite. The checksum is reduced to 8 bits. The chances that a bad checksum not being detected are remote. Up to 4 device strings can be tested at once. The configuration for the testing environment of the present invention is illustrated in figure 8. A single host computer 50 is utilized to control testing for a plurality of drives P1-P(N). The drives are coupled to the host computer serially in a daisy chain configuration through the serial ports of each drive. The serial output of the host computer 50 is coupled on line 51 to the serial input of drive PI. The serial output of drive PI is coupled on line 52 to the serial input of drive P2. The serial output of drive P2 is coupled on line 53 to the input of the next drive. The output of drive P(N-1) is coupled on line 54 to the serial input of drive P(N). The output of drive P(N) is coupled on line 55 to the input of host computer 50. 1) The Host AT (HAT) sends a NOP over the STP (Serial Test Port), and expects to receive command back. This verifies the serial line is a closed circuit, and power is available to all connected drives. 2) The HAT sends a reset over the STP, this should not cause any action on the test drives. 3) The HAT sends select all signal over the line, waits for operator intervention, before proceeding. This will verify that all drives recognize the commands over the STP and are ready for further testing. Drives failing this test should be returned to SDS-1000 test station for debugging. 4) After the operator resumes testing, the HAT sends a Logical Drive Assignment (LAD) to the first drive, address Olh.. The first drive takes the packet, saves the logical drive address (Olh), increments the address field to 02h, and sends the packet to the next drive. Each drive will accept the LAD command, save the logical address, increment, and resend packet. The HAT receives the Command Packet (CP) and keep the CP address (decrement) for the number of drives under test (DUT). 5) The HAT POLLS each DUT for status, verifying each DUT responds to its logical address. The DUT responds to address OOh (HAT) with a health value (obtained from a basic ROM diagnostic to check RAM, registers, etc.) 6) The HAT sequences up each DUT, giving a proper interval for powering-up, then powering-up next logical DUT, then POLL for status of the previous DUT. 7) After all of the DUT's have been powered up, a preliminary seek test, 5 maximum access, to "warm up" the DUT prior to read and write tests. 8) The HAT requests drive information from the DUT during the seek test. The DUT provides the serial number, bad track table, an current status to the host. 9) The HAT POLLS status check on all drives every two minutes 10 maximum for DUT test/ status after this point. If a DUT's error rate exceeds the maximum threshold, the DUT is flagged as a failed drive. 10) The HAT sends a Download Test Command all drives. Each DUT reads the diagnostic programs from the disk to RAM and await next command from the HAT. 15 11) The HAT sends a Start Test Command (or a macro test) to start the testing. 12) Each drive maintains a Bad Track Table (BTT) in RAM, updating the BTT as required. 13) The HAT requests, compiles, and prints drive status for all DUT's. 0 This data includes the bad track table, test parameters, number of soft/hard errors detected, and a pass or fail statement. All of this data is available on the DUT's reserved data areas 14) The HAT maintains a combined history log of all tests run on the DUT's. 5 Preliminary Command Set: Download Test Format Logical Drive Assignment (LAD) Macro [50] Nop Poll Read Rad Physical Recal Reset Seek Start Test Status Write Write Physical Stop Test Send Results Thus, a control system and apparatus is described for a disk drive storage system which allows soft loading of control programming, testing of a plurality of disk drives with a single host computer, distributed control of drive operations and effecient communication between two onboard processors.

Claims: CLAIMS OF THE PRESENT INVENTION 1. A method for providing a control program to a contrl means of a rotating media storage system comprising the steps of: storing said control program on a portion of said rotating media; executing a startup program with said control means to read said control program from said rotating storage media; storing said control program in a memory means coupled to said control means; executing said control program by said control means to implement operation of said storage system. 2. The method of daim 1 further induding the step of verifying said control program when said control program is read from said storage media. 3. The method of claim 1 wherein the step of reading said control program comprises the steps of: initializing said control means; initializing an interface between said control means and a host computer; testing said memory means; initializing rotation of said storage media; reading said control program and verifying vailidity of said program; transferring said program to said memory means. 4. The method of daim 1 wherein said control means comprises a microprocessor. 32 5. The method of daim 1 wherein said memory means comprises a random access memory (RAM). 6. The method of daim 1 wherein said storage system comprises a magnetic disk drive. 7. The method of daim 1 wherein said start up program is stored in a read only memory (ROM). 8. A rotating media storage system comprising: control means for controlling operation of said storage system; first storage means coupled to said control means for storing an initializing program for start up of said storage system; read/write means coupled to said control means for reading a control program stored on said media when said initializing program is executed and storing said control program in a second memory means, said control program for controllig operation of said storage system after start up of said system; interface means coupled to a host computing means and to said control means for communication between said host and said control means. 8. The system of daim 7 wherein said rotating media comprises a magnetic disk and said control program is stored on a portion of said disk separate from a data area of said disk. 9. The system of daim 7 wherein said first memory means comprises a read only memory (ROM). 10. The system of daim 7 wherein said second memory means comprises a random access memroy (RAM). 11. The system of claim 7 wherein said control means comprises first and second processing means, said first processing means controlling said interface and said second processing means controls access to said rotating media. 12. The system of daim 11 wherein said serial input means comprises a serial port coupled to said first processing means. 13. In a rotating media storage system having first and second control means for controlling operation of said storage system, a method of communicating between said first and second control means comprising the steps of: providing a first signal of a first state from said first control means to said second control means; initializing said second control means and sending a second signal of a first state from said second control means to said first control means; providing one byte of a command signal from said first control means to said second control means when said second signal is at said first state providing a second byte of said command signal from said first control means to said second control means when said second signal is at a second state. 14. The method of claim 13 wherein said first control means comprises a first processor and said second control means comprises a second processor. 15. A method for testing a plurality of disk drives with a single host computer having an input serial port and an output serial port comprising the steps of: providing a serial input port and a serial output port on each of said plurality of disk drives; coupling said output serial port of said host computer to said input port of a first one of said plurality of disk drives; coupling said output serial port of said first disk drive to said input serial port of a second of said disk drives; coupling said output port of each consecutive disk drive to said input serial port of each next consecutive of said disk drives; coupling said output serial port of the nth disk drive to said input serial port of said host computer; providing test programming to a first memory means in each of said disk drives from said host computer; executing said test programming with a processing means in each of said plurality of disk drives. 16. The method of daim 15 wherein said test programming comprises the steps of: sending a first test command from said host computer to verify a complete circuit; sending a drive assignment command to each of said drives to identify each of said drives on said circuit; pollig each of said drives for status; sending a diagnostic test sequence to each of said drives; sending a start test sequence command to each of said drives; polling eadi of said drives for status after execution of said test sequence.

Inventors: GALE WARREN, MCKINLEY DAVID, TSENG JOHN, GALE, WARREN, MCKINLEY, DAVID, TSENG, JOHN
Applicants: MAXTOR CORP, MAXTOR CORPORATION
Application year: 1989
Main classification: G06F11
IPC codes: G06F3, G06F9, G06F13, G11C29