Field discrimination circuit

Abstract: A field discrimination circuit for use in a television receiver, which comprises a shift register (11) for shifting an input vertical synchronizing signal so as to produce n (n ≧ 6) pseudo vertical synchronizing signals having the same phase difference, a selector (12) for selecting one of the n pseudo vertical synchronizing signals and delivering the selected pseudo vertical synchronizing signal as a reference vertical synchronizing signal, a latch circuit (13) for detecting input timing of the reference vertical synchronizing signal into one of n time sections obtained by dividing one horizontal scanning period by n, to thereby generate a latch output signal, and a decoder (14) for effecting field discrimination on the basis of the latch output signal and generating a field discrimination signal.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION This invention relates to a field discrimination circuit used in a display signal processing circuit such as that incorporated in, for example, picture display apparatus (especially, various kinds of flat panel displays, liquid crystal displays and plasma displays) in which individual picture elements or individual scanning lines are fixed on a screen. DESCRIPTION OF THE RELATED ART First, a method for driving a picture display device will be briefly described. Fig. 1 is a schematic plan view of an example of known picture display devices 50 employed in the present invention. The illustrated picture display device 50 can display 440 scanning lines ℓ₁ to ℓ₄₄₀. The odd-numbered scanning lines ℓ₁, ℓ₃, ----, ℓ₄₃₉ are those belonging to a second field, while the even-numbered scanning lines ℓ₂, ℓ₄, ----, ℓ₄₄₀ are those belonging to a first field. Fig. 2 is a block diagram showing a circuit related to field discrimination in a drive circuit used for driving such a prior art picture display device 50. This drive circuit includes a decoder/vertical driver 51, a vertical address counter 52 and a latch circuit 53 for the field discrimination purpose. The vertical address counter 52 generates count data synchronous with a horizontal synchronizing signal H. The decoder/vertical driver 51 reads out vertical deflection data corresponding to the count data from a memory (not shown) and decodes the vertical deflection data to supply the decoded data to a vertical deflection electrode unit (not shown). The vertical address counter 52, which is reset by a vertical synchronizing signal Vin, counts the pulses of the horizontal synchronizing signal H. The field discrimination latch circuit 53 receives a signal H F with the timing of the vertical synchronizing signal Vin applied as a clock signal. The field discrimination latch circuit 53 generates a field discrimination output signal FLD which is applied to an LSB (least significant bit) terminal of the decoder/vertical driver 51. Fig. 3 is a timing chart for illustrating the operation of the drive circuit shown in Fig. 2. In Fig. 3, S p designates a picture signal of a first field, and S S designates a picture signal of a second field. The horizontal synchronizing signal H has a pulse interval of one horizontal scanning period, and the signal H F applied to the field discrimination latch circuit 53 has also a pulse interval of one horizontal scanning period for the purpose of field discrimination. The duty factor of this pulse signal H F is 50%. The field discrimination output signal FLD of the latch 53 has a waveform as shown in Fig. 3. Va, Vb, Vc and Vd represent four different forms of the vertical synchronizing signal Vin. That is, these signals Va to Vd have different delay times attributable to, for example, variations of the constants of a vertical hold circuit (not shown). Of course, an inverse interlace or an interlace stop should not occur regardless of application of the vertical synchronizing signal Vin having whatever delay time. The numerals appearing beneath the waveforms of the vertical synchronizing signals Va to Vd indicate the counts of the vertical address counter 52. The operation of the prior art drive circuit driving the known picture display device 50 will now be described with reference to Figs. 2 and 3. For the purpose of description, it is supposed that the decoder/vertical driver 51 is designed so that display of a picture is started from the time where the count of the vertical address counter 52 is "20". First, a description will be directed to the case where the vertical synchronizing signal Vin is represented by Va. In the case of the first field, the vertical synchronizing signal Va is applied with the timing where the signal H F is in its "L" level. As a result, the field discrimination output signal FLD of the latch 53 is turned into its "L" level. Further, when the screen is scanned with the scanning line ℓ₂, a picture signal portion corresponding to the count "20" of the vertical address counter 52, that is, a picture signal portion 2 ○ is displayed on the screen. Similarly, a picture signal portion 4 ○ is then displayed when the screen is scanned with the scanning line ℓ₄. In the case of the second field, the vertical synchronizing signal Va is applied with the timing where the signal H F is in its "H" level. As a result, the field discrimination output signal FLD of the latch circuit 53 is turned into its "H" level, and a picture signal portion 1 ○ and a picture signal portion 3 ○ are sequentially displayed when the screen is scanned with the scanning lines ℓ₁ and ℓ₃ respectively. Such a display mode is shown in Fig. 4 (a). Description will then be directed to the case where the vertical synchronizing signal Vb is applied. In the first field, the field discrimination output signal FLD of the latch circuit 53 is turned into its "H" level, and the picture signal portions 2 ○ and 4 ○ are sequentially displayed when the screen is scanned with the scanning lines ℓ₁ and ℓ₃ respectively. On the other hand, in the second field, the field discrimination output signal FLD of the latch circuit 53 is turned into its "L" level, and the picture signal portions 3 ○ and 5 ○ are sequentially displayed when the screen is scanned with the scanning lines ℓ₂ and ℓ₄ respectively. Such a display made is shown in Fig. 4 (b). Display modes, when the vertical synchronizing signals Vc and Vd are similarly applied, are shown in Fig. 4 (c) and 4 (d) respectively. Thus, when the field is discriminated in the manner described above, a normal interlaced picture can be displayed regardless of the value of a delay in the vertical synchronizing signal separation circuit. When, in the field discrimination circuit included in the drive circuit described above, the vertical synchronizing signal Vin is applied to the decoder/vertical driver 51 while the level of the signal H F is changing, the decoder/vertical driver 51 may not detect such a level change of the signal H F or may be unable to specify the field, resulting in a variation of its output. As a result, the decoder/vertical driver 51 may be unable to ensure the interlacing operation, or its driving operation may become unstable. JP-A-61-261972 (equivalent to US-A-4 792 853, published 20/12/88) discloses a video signal processing apparatus comprising means for separating vertical and horziontal synchronizing signals from each other and means for discriminating field numbers of the respective video signal by using the separated vertical and horizontal synchronizing signals and means for generating a signal representing a frame period, the apparatus processing the video signal by using the dicrimination signal and the frame period representing signal in an alternative way. From JP-A-61-264871 (also equivalent to US-A-4 792 853, published 20/12/88) synchronizing a signal circuit is known comprising a synchronizing signal separating circuit, a field discrimination circuit for deriving a field discrimination signal from separated horizontal and vertical synchronizing signals and a dectection circuit for detecting an abnormality of the field discrimination signal. SUMMARY OF THE INVENTION With a view to obviate such a malfunction or unstable operation of the prior art field discrimination circuit, it is an object of the present invention to provide a field discrimination circuit for use in a drive circuit driving a picture display device, in which a pull-in function is added to the prior art field discrimination circuit so as to always ensure the stable interlacing operation. The above object is achieved by a field discrimination circuit according to claims 1 and 2, respectively. As will be apparent from the above description of the operation of the prior art field discrimination circuit (the drive circuit), it is known that even the prior art field discrimination circuit can stably operate so far as the vertical synchronizing signal Vin is not applied to the decoder at a timing in the vicinity of a level change point of the signal H F . The field discrimination circuit of the present invention can ensure the stable interlacing operation even when a vertical synchronizing signal is applied at a timing in the vicinity of a level change point of the signal H F , because a vertical synchronizing signal which is inputted at a timing of the center portion of a pulse of the signal H F is always selected by the selector from among the six vertical synchronizing signals shifted by the shift register. On the other hand, in order that whether the signal being received is interlaced or not interlaced can be accurately detected, it is necessary to divide one horizontal scanning period into at least six time sections. That is, if the possibility of occurrence of malfunction of the field discrimination circuit is estimated beforehand to be within the range of ± 1, it is necessary to divide one horizontal scanning period into at least six time sections in total in which three time sections therein represent the noninterlaced state, while the remaining three time sections represent the interlaced state. This principle will now be described in further detail. In a picture signal used in a television system, the phase of a first field and that of a second field have the difference corresponding to 1/2 of one horizontal scanning period. Therefore, when the signal received is interlaced, if the vertical synchronizing signal is inputted at time t₁ in the first field, then, the vertical synchronizing signal is inputted at time t₁ + 1/2H in the second field, where H denotes a pulse interval of one horizontal scanning period. In order that such input timing of the vertical synchronizing signal can be detected correctly by a gate circuit, a best method for detecting the input timing of the vertical synchronizing signal is to divide one horizontal scanning period H into, for example, six time sections and to have the vertical synchronizing signal inputted at a timing of substantially the middle of the second time section and at that of the fifth time section. This is because the desired stable input timing of the vertical synchronizing signal can be accurately detected by using the pulse signal H, which provides the basis for determining the timing in one horizontal scanning period, while taking into consideration any possible malfunction of the field discrimination circuit. On the other hand, when the received signal is not interlaced, the vertical synchronizing signal for each of the first and second fields may be applied at substantially the same timing in one horizontal scanning period. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view for illustrating the order of scanning lines for scanning the screen of a picture display device. Fig. 2 is a block diagram of a field discrimination circuit incorporated in a drive circuit used for driving the picture display device shown in Fig. 1. Fig. 3 is a timing chart for illustrating the operation of the prior art field discrimination circuit shown in Fig. 2. Fig. 4 is a conceptional diagram showing various picture display modes changing due to changes in the phase of the vertical synchronizing pulses. Fig. 5 is a block diagram of a preferred embodiment of the field discrimination circuit according to the present invention. Fig. 6 is a timing chart for illustrating the operation of the field discrimination circuit of the present invention shown in Fig. 5. Fig. 7a is a conceptional diagram for illustrating the state transition in the state machine shown in Fig. 5. Fig. 7b is a block diagram showing in detail the structure of the shift register and selector shown in Fig. 5. DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the field discrimination circuit according to the present invention will now be described with reference to Figs. 5 to 7b. Fig. 5 is a block diagram of the field discrimination circuit embodying the present invention. Referring to Fig. 5, the field discrimination circuit comprises a 6-bit shift register 11, a selector 12, a latch circuit 13, a decoder 14, a state machine 15, a vertical address counter 16, and a vertical address decoder/vertical driver 17. The shift register 11 has a structure as, for example, shown in Fig. 7b. The field discrimination circuit and vertical driver circuit having the above structure will be described in further detail with reference to Fig. 6. As shown in Fig. 6, one horizontal scanning period is equally divided into six time sections, ₀, ₁, ----, ₅ and each of these six time sections is identified by the use of the combination of 3-bit signals H F0 H F1 and H F2 . These signals H F0 , H F1 and H F2 can be obtained by applying an oscillator output signal having a frequency higher than the horizontal frequency to a counter (not shown) and decoding the output signal of the counter. The six individual time sections obtained by dividing one horizontal scanning period are designated as ₀, ₁, ----, ₅, respectively, as described above. A pulse string CK having one pulse in each of the six time sections is applied, together with a vertical synchronizing signal Vin, to the shift register 11, and the vertical synchronizing signal Vin is shifted to form six kinds of vertical synchronizing signals Va, Vb, Vc, Vd, Ve and Vf synchronous with the pulse string input CK. This pulse string input CK can also be produced by means similar to the means used for producing the signals H F0 to H F2 . The six vertical synchronizing signals Va, Vb, Vc, Vd, Ve and Vf are applied to six input terminals S₁, S₂, S₃, S₄, S₅ and S₆ respectively of the selector 12, and one of those vertical synchronizing signals Va to Vf is selected to appear as an output signal V OUT from the selector 12. This selection of one of the six vertical synchronizing signals Va to Vf is determined by the state machine 15 which can take six operable states or modes σ₁, σ₂, σ₃, σ₄, σ₅ and σ₆. In response to the application of the one vertical synchronizing signal selected by the selector 12, the latch circuit 13 latches the 3-bit signals H F0 to H F2 . When the state machine 15 takes the operable mode σ₁, the selector 12 selects the vertical synchronizing signal Va applied to its input terminal S₁. Similarly, when the state machine 15 takes the operable modes σ₂, σ₃, σ₄, σ₅ and σ₆, the vertical synchronizing signals Vb, Vc, Vd, Ve and Vf applied to the selector input terminals S₂, S₃, S₄, S₅ and S₆ are selected respectively. The decoder 14 decodes the output signal of the latch circuit 13 and generates an output signal which controls the state machine 15. The decoder 14 also generates a field discrimination output signal FLD. On the basis of the output signal of the decoder 14, the state machine 15 controls the change-over of the input terminals S₁ to S₆ of the selector 12. The vertical address counter 16 and the vertical address decoder/vertical driver 17 are similar to those shown in Fig. 2. The operation of the field discrimination circuit will now be described with reference to Figs. 6, 7a and 7b. First, a description will be directed to the case where the application timing of the selected vertical synchronizing signal Vout corresponds to the time section ₀ (H F0 = "L", H F1 = "L", H F2 = "L"), that is, ₀ (0, 0, 0) or time section ₃ (H F0 = "H", H F1 = "H", H F2 = "L"), that is, ₃ (1, 1, 0). In this case, the state of the state machine 15 is changed or incremented by a mode "1" by the function of the decoder 14. If the state machine 15 was placed in the mode σ₆ already, the state transition from the mode σ₆ to the mode σ₄ occurs in this case. Therefore, there is a very high possibility that application timing of the vertical synchronizing signal Vout which will be selected next time will correspond to the time section ₄ or ₁ shown in Fig. 6. That is, the vertical synchronizing signal Va or Vd will be selected next time. On the other hand, when the application timing of the selected vertical synchronizing signal Vout corresponds to the time section ₁ (1, 0, 0) or ₄ (0, 0, 1), the decoder 14 does not act to change the stage of the state machine 15. Therefore, there is a very high possibility that application timing of the vertical synchronizing signal Vout which will be selected next time will correspond to the time section ₄ or ₁ shown in Fig. 6. When the application timing of the selected vertical synchronizing signal Vout corresponds to the time section ₂ (0, 1, 0) or ₅ (1, 0, 1) , the state of the state machine 15 is decremented by a mode "1" by the function of the decoder 14. If the state machine 15 was placed in the mode σ₁ already, the state transition from the mode σ₁ to the mode σ₃ occurs in this case. Therefore, there is a very high possibility that application timing of the vertical synchronizing signal Vout which will be selected next time will correspond to the time section ₄ or ₁. In the manner described above, regardless of the application timing of the vertical synchronizing Vin, the selected vertical synchronizing signal Vout is caused to have the timing corresponding to the time section ₁ or ₄ where the field can be discriminated stably. Fig. 7a shows the state transition in the state machine 15, and Fig. 7b shows the detailed structure of the shift register 11 and that of the selector 12. The field discrimination signal FLD of "L" level is generated from the decoder 14 when the selected vertical synchronizing signal Vout has the timing corresponding to the time section ₀, ₁ or ₂, while, the field discrimination signal FLD of "H" level is generated when the selected vertical synchronizing signal Vout has the timing corresponding to the time section ₃, ₄ or ₅. The functions of the vertical address counter 16 and the vertical address decoder/vertical driver 17 are similar to those of the vertical address counter 52 and the decoder/vertical driver 51 shown in Fig. 2. It will be understood from the foregoing description that, in the field discrimination circuit according to the present invention, the stable vertical synchronizing signal selected by the selector is used for field discrimination, so that any malfunction as well as any unstable operation of the field discrimination circuit can be completely prevented regardless of the application timing of the vertical synchronizing signal.

Claims: A field discrimination circuit characterized by a shift register (11) of at least six bits for shifting an incoming vertical synchronizing signal (V in ) by one to at least six pulses with different phases within one horizontal scanning period and having at least six output terminals from which respective signals (V a - V f ) are outputted; a selector (12) for selecting one of the output terminals (S₁-S₆) to take one of the signals (V a -V f ) at the terminals (S₁-S₆) as an output vertical synchronizing signal (V out ) shifted by said shift register (11); a phase detector (13) detecting the phase of the vertical synchronizing signal (V out ) selected by said selector for determining which one of the signals (V a -V f ) at the terminals (S₁-S₆) is taken as the output vertical synchronizing signal (V out ); and a decoder (14) and a state machine (15) for performing field discrimination and further altering the selection of one of the terminals (S₁-S₆) by said selector in accordance with the phase of the vertical synchronizing signal selected by said selector. A field discrimination circuit characterized by a shift register (11) receiving, as input signals thereto, a vertical synchronizing signal and a clock signal in the form of a pulse string including at least n, ≧ 6, pulses within one horizontal scanning period and having a pulse interval of a predetermined time interval, said shift register shifting said input vertical synchronizing signal in synchronism with said clock signal to thereby produce n phase shifted versions of said synchronizing signal having a phase difference corresponding to said predetermined time interval; a selector (12) receiving, as input signals thereto, said n phase shifted versions of said vertical synchronizing signals produced by said shift register, selecting one of said phase shifted versions of said vertical synchronizing signal, and outputting said selected phase shifted version of said vertical synchronizing signal as a reference vertical synchronizing signal; a latch circuit (13) receiving, as input signals thereto, said reference vertical synchronizing signal outputted from said selector and information signals indicating individual time sections obtained by equally dividing one horizontal scanning period by n, said latch circuit generating a latch output signal indicating in which one of said n time sections said reference vertical synchronizing signal has been inputted; and a decoder (14) receiving, as an input signal thereto, said latch output signal from said latch circuit (13), and, when said latch output signal does not indicate a first or a second predetermined time section among said n time sections, generating a control signal for controlling the selection of said selector so that said latch output signal indicates said first or second predetermined time section, said decoder performing field discrimination depending on said latch output signal indicating in which one of said first and second predetermined time sections said reference vertical synchronizing signal has been inputted, and generating a field discrimination signal as a result of said field discrimination.

Inventors: KURATA TAKATSUGU, NISHIDE TAKUYA, KURATA, TAKATSUGU, NISHIDE, TAKUYA
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1989
Main classification: H04N5
IPC codes: H04N5, G09G5