Charge injection device with low noise readout

Abstract: A charge injection imaging device comprises low bandwidth, low noise performance column amplifiers serially connected to respective charge coupled device storage lines. Image and/or noise defining electronic information signals are retrieved from the charge injection imaging device by way of the amplifiers and storage lines in a manner which provides image defining electronic information signals from which the noise defining electronic information signal portions have been automatically subtracted for each succeeding photo­ sensitive element of the device. The subtracted noise portions include both KTC noise and fixed pattern noise which are normally inherently associated with the image defining electronic information signals retrieved from the charge injection imaging device.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to a charge injection imaging device with low noise readout and, more particularly, to a charge injection imaging device which can provide image defining signals for each succeeding photosensitive element thereof from which noise defining signals are automatically offset. 2. Description of the Prior Art Charge injection imaging devices comprising a plurality of photosensitive elements arranged in a matrix of rows and columns are well known in the art. Each of the photosensitive elements comprises a row and column electrode. All the row electrodes in each row are in common connection with respect to each other, and all the column electrodes in each column are in common connection with respect to each other also. Incident scene light operates to photogenerate minority charge carriers in potential wells under each pair of electrodes in each photosensitive element. The photogenerated charges may be transferred between wells within each of the photosensitive elements by applying appropriate bias voltages to respective ones of the column and row electrodes. In one well-known mode of operation, the charges may be sensed from the electrodes out of the CID along common lines interconnecting each column of electrodes. Most recently, it has been suggested that amplifiers may be integrated with the column electrodes. Such amplifiers preferably should be of low bandwidth in order to facilitate low noise performance when reading out the charge injection imaging device. Each amplifier must also be of substantially narrow width or pitch in order to accommodate its alignment with a respective one of the columns without substantially increasing the width of the silicon area of the charge injection imaging device. Not only must the amplifiers be of the aforementioned narrow pitch while still exhibiting low noise and bandwidth performance characteristics, but noise inherent to the charges sensed from the photosensitive elements such as KTC noise and fixed pattern noise must also be offset from the output signal. KTC noise is inherently induced in each of the common column electrode interconnect lines upon resetting the electrode voltages while fixed pattern noise occurs due to variations in the crossing of the common column electrode interconnect lines with the common row electrode interconnect lines as a result of inherent limitations in processing. EP-A-0 045 608 discloses an apparatus for periodically reading image intensity information from M rows x N columns of charge storage sites in a CID array imager. The magnitudes of signal charges collected at the sites in response to incident radiation are sensed by a measuring circuit which measures changes in potential on column lines connected to (V RC ,V₁) the respective columns of sites. These changes in potential are caused by sequentially applying specific potentials (V RC ,V₁) to row lines connected to the respective rows of sites to effect injection of the signal charges into the substrate of the array. The apparatus operates to minimize charge transfers within the array during readout and is thus capable of accurately determining the magnitude of signal charges in arrays fabricated from semiconductor materials having low charge transfer efficiencies. It is a primary object of this invention to provide a charge injection imaging device in which image data is read out in a manner by which KTC noise and fixed pattern noise are automatically cancelled and in which low bandwidth amplifiers are confined within the narrow pitch between columns. The above technical problem is achieved by the combined features of patent claim 1. Further developments and improvements are specified in subclaims 2-10. SUMMARY OF THE INVENTION A charge injection device comprises an array of photosensitive elements, each one of which has noise defining electronic information signals associated therewith and generates image defining electronic information signals in response to incident scene light. Means are provided for sensing and amplifying the image and noise defining electronic information signals from the array of photosensitive elements in a selectively ordered sequence. A plurality of serially connected storage elements connects to receive the amplified image and noise defining electronic information signals in the selectively ordered sequence. Each of the storage elements is structured to store image and/or noise defining electronic information signals corresponding to one of the photosensitive elements in the array. Means are provided for advancing the image and noise defining electronic information signals through the serially connected storage elements in a manner whereby each of the storage elements stores a respective one of the image and/or noise defining electronic information signals for each photosensitive element for a determined time interval. Means operate to simultaneously retrieve selected image and noise defining electronic information signals from selected ones of the serially connected storage elements at select succeeding ones of the determined time intervals to provide image defining electronic information signals for each succeeding photosensitive element from which the noise defining electronic information signals are automatically cancelled. DESCRIPTION OF THE DRAWINGS The novel features that are considered characteristic of the invention are set forth with particularity in the appended claims. The invention itself, however, both as to its organization and its method of operation together with other objects and advantages thereof will be best understood from the following description of the illustrated embodiment when read in connection with the accompanying drawings wherein: FIG. 1 is a schematic block diagram for the charge injection imaging device of this invention including its special features for facilitating low noise readout; FIG. 2 is a schematic block diagram for the amplifier portion of the charge injection imaging device of FIG. 1 showing the amplifier portion in substantially greater detail; FIG. 3A is a schematic block diagram for the storage line portion of the charge injection imaging device of FIG. 1 showing the storage line in substantially greater detail; FIG. 3B is a time versus signal diagram showing the advancement of selected signal values with time along the storage line of FIG. 3A; and FIG. 3C is a timing diagram showing the variation in phase control voltages with time for the storage line of FIG. 3A. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1, there is shown generally at 10 the charge injection imaging device of this invention comprising a two-dimensional array of photosensitive elements 12 arranged in rows R₁ - R₄ and columns C₁ - C₄. Each of the photosensitive elements 12 comprises a row electrode 14 and a column electrode 16 disposed on a silicon substrate so as to store photogenerated charges 18 in potential wells under the electrodes in a manner as is well known in the art. As is readily apparent, the row electrodes 14 of each row are commonly interconnected by row lines 14 R₁ - 14 R₄. In like manner, the electrodes 16 of each column are commonly connected by column lines 16 C₁ - 16 C₄. The dwo-dimensional array of photosensitive elements 12 and their associated row and column electrodes 14, 16 and common interconnect lines herein described are well known in the art and thus need not be described in any further detail herein. It will be readily understood that although FIG. 1 shows only a four photosensitive element by four photosensitive element array, in actual practice such imaging arrays comprise a substantially greater number of photosensitive elements. The row electrode interconnect lines 14 R₁ - 14 R₄ are controlled by a row scan circuit 19 in a manner as to be more fully described in the following discussion. The column electrode interconnect lines 16 C₁ - 16 C₄ connect, respectively, to amplifier circuits 20₁ - 20₄ which operate in the manner of this invention to be hereinafter described. The output signals from amplifiers 20₁ - 20₄ are, in turn, directed to respective storage lines 22₁ - 22₄, the operation of which will again be described in substantially more detail in the following discussion. The storage lines 22₁ - 22₄, in turn, output signals to a serial shift register 24 which provides a continuous stream of electronic information signals corresponding to image data derived from each photosensitive element 12 in succeeding order along each succeeding row. Referring now to FIG. 2 where like numerals refer to previously-described elements, there is shown in substantially more detail the components of one of the amplifier circuits 20₁. It will be readily understood that the amplifier circuits 20₁ - 20₄ are identical and that only one amplifier circuit 20₁ need be described in detail. The amplifier circuit 20₁ comprises a pair of MOS field effect transistors T₁ and T₂ connected in cascaded relationship with respect to each other. The input to the amplifier circuit 20₁ from the column electrode, interconnect line 16 C₁ as shown at node A connects to the gate electrode of transistor T₁. The drain and source electrodes of transistors T₁ and T₂, respectively, are in common connection with respect to each other while the source electrode of transistor T₁ connects to a constant low voltage source V S . The gate electrode to the transistor T₂ connects to a control voltage V BIAS which controls the amplifier in the manner of this invention to be subsequently described wherein The drain electrode of transistor T₂ connects to a node B which, in turn, defines the output terminal for the amplifier at Vout. The transistors T₂ and T₁ are in serial connection with a load resistor R L and in parallel connection with an output capacitor C₀. The load resistor R L , in turn, connects to a steady state high voltage source V DD . The output capacitor C₀ and load resistor R L cooperate to limit the bandwidth of the amplifier circuit 20₁. The amplifier circuit 20₁ also includes means for resetting the voltage level at node A comprising two MOS field effect transistors T₃ and T₄ connected in cascade relationship with respect to each other. The source and drain electrodes of the transistors T₃ and T₄, respectively, are in common connection with respect to each other. The gate electrode to the transistor T₃ is in common connection with the node B and hence, the output terminal V out while the drain electrode of transistor T₃ connects to the high steady state voltage source V DD . The gate electrode to the transistor T₄, in turn, connects to a control voltage which varies in the manner of this invention to be subsequently described. The source electrode of the transistor T₄ is in common connection to the node A and the electrode common interconnect line 16 C₁. The amplifier 20₁ also includes means for clearing the node A comprising an MOS field effect transistor T₅ having its drain electrode connecting to the node A and the column electrode common interconnect line 16 C₁ and its source electrode connecting to a low steady state voltage source V SS . The gate electrode to the transistor T₅ connects to a control voltage which is varied in the manner of this invention to be subsequently described herein. Referring now to FIG. 3A, there is shown in substantial detail the storage line 22₁ comprising an input stage 26 in serial connection with a plurality of succeeding serially connected charge coupled device (CCD) storage stages 28₁ - 28 n . Again, as will be readily understood, all the storage lines 22₁ - 22₄ are identical and only one storage line 22₁ need be described in detail. Each of the CCD storage stages 28₁ - 28 n comprises four succeeding storage areas or phases ( 1 -  4). Charges corresponding to image and noise defining electronic information signals are advanced through succeeding phases of each succeeding stage 28₁ - 28 n in a sequential manner by transfer gates or electrodes (not shown) which are sequentially energized in a well-known manner. Four of the transfer gates or electrodes 30₁ - 30₄ are in common connection with respect to each other and retrieve image and noise defining electronic information signals from the storage line 22₁ in the manner of this invention as will be subsequently described herein. It will be readily understood that the first two transfer electrodes 30₁ and 30₂ connect, respectively, to the fourth phase  4 of the first storage stage 28₁ and the second phase  2 of the third storage stage 28₃. In like manner, the last two transfer gates 30₃ and 30₄ connect, respectively, to the fourth phase  4 of the third from the last storage stage 28 n-2 and the second phase  2 of the last storage stage 28 n . The line from which the transfer electrodes 30₁ - 30₄ are commonly interconnected, in turn, is directed by way of an amplifier circuit 32 to an output terminal V out . The input bias to the commonly connected transfer electrodes 30₁ - 30₄ is controlled by way of an MOS field effect transistor T₆ having a drain electrode connected to a high steady state voltage source V BIAS and a gate electrode connected to a variable control voltage V RES . Operation of the charge injection imaging device 10 of this invention proceeds as follows. Referring now to FIG. 2, image defining scene light is allowed to impinge during an exposure interval upon the photosensitive elements 12 so as to photogenerate charges 18 in potential wells under the row and column electrodes 14 and 16 as is well known in the art. During the exposure interval, both the row and column electrodes of all of the photosensitive elements 12 are energized to a high voltage level by way of the row electrode common interconnect lines 14 R₁ - 14 R₄ and the column electrode common interconnect lines 16 C₁ - 16 C₄ in a manner as is well known in the art. Under these conditions potential wells under the row electrodes 14 are deeper so that photogenerated charges 18 are stored under the row electrodes 14 as shown in the drawings. The charges stored in the photosensitive elements 12 in each of the columns (C₁ - C₄) are simultaneously read out for all the photosensitive elements 12 in each succeeding row starting with the first row R₁. Although the following description is limited primarily to the operation of only one amplifier 20₁ and one storage line 22₁, it will be readily understood that all the amplifiers 20₁ - 20₄ and all the storage lines 22₁ - 22₄ operate simultaneously and in the identical manner. At the beginning of each row readout starting with the first row R₁, the column electrodes 16 are reset to the voltage level of node B by applying a high voltage (binary logic 1) input signal to the gate electrode of transistor T₄, thereby establishing gain stabilization. After the reset is complete, the transistor T₄ is turned off by applying a low voltage (binary logic 0) input signal to its gate electrode. As a result of this resetting process, the voltage level of node A contains noise due to the fluctuation of the voltage across reset transistor T₄. This noise is KTC noise as previously discussed and ultimately will be cancelled in the manner of this invention. The row R₁ electrodes 14 are thereafter set to a low voltage level by the row scan circuit 19 applying the appropriate low voltage to the row electrode common interconnect line 14 R₁. The charge stored under the row R₁ electrodes 14, in turn, is transferred to the corresponding column electrodes 16 in the row R₁. The charges transferred into the column electrodes 16 in this manner cause the voltage or signal level at node A in each of the column electrode common interconnect lines 16 C₁ - 16 C₄ to change by an amount proportional to the size of the charge transferred thereto. This change in voltage at node A, in turn, is amplified by the transistors T₂ and T₁ to provide an amplified output voltage at node B. The changed voltage at node B corresponds to both image and noise defining electronic information signals including KTC noise induced at each one of the column electrode common interconnect lines 16 C₁ - 16 C₄ by the corresponding one of reset transistors T₄ and T₃ and fixed pattern noise resulting from the variations in the crossing of the row electrode common interconnect lines 14 R₁ - 14 R₄ with the column electrode common interconnect lines 16 C₁ - 16 C₄. In the preferred embodiment, the signal level at node B is repeatedly sampled a determinate number of times. During each sample time, a charge representing the signal is created and stored in the input stage 26 of the storage line 22₁. Thus, at the end of the sampling period a large charge composed of a plurality of small charges corresponding to each sample is present in the input stage 26 of the storage line 22₁. This sampling process enables the bandwidth of each amplifier to be substantially reduced without increasing the size of the storage capacitor C₀ and load resistor R L . In this manner, the amplifier circuits 20₁ - 20₄ can be maintained within the narrow pitch of each of the columns C₁ - C₄. The row scan circuit 19 next operates to apply a high voltage to the row electrodes 14 in the row R₁ thereby affecting the transfer of the charges under the column electrodes 16 back into the row R₁ electrodes 14. The signal level at node B is again sampled in the aforementioned manner and stored in the input stage 26 of the storage line 22₁. This last sampled signal contains KTC noise. As will be readily understood, prior to the transfer of the KTC noise defining electronic information signal to the input stage 26, the previously transferred image and noise defining electronic information signal is successively advanced from the input stage 26 to the first storage area or phase  1 of the first storage stage 28₁. Thus, in this manner first electronic information signals corresponding to the image, KTC noise, and fixed pattern noise and second electronic information signals corresponding to the KTC noise are successively transferred, respectively, into two succeeding stages of the storage line 22₁. Difficulty arises in reading out fixed pattern noise since it requires a sample of the output of the photosensitive element immediately after the photosensitive element has been cleared of photogenerated charges. However, as a result of the fact that a portion of the injected charge is recollected in nearby photosensitive elements, it is necessary to wait until one or more or, in this instance, three succeeding rows of photosensitive elements are read before transferring the charges which define fixed pattern noise. In other words, in order to transfer charges or signals corresponding to the fixed pattern noise of the photosensitive elements of row R₁, it is necessary to wait until the charges from the photosensitive elements 12 of the third succeeding row R₄ have been transferred. After transferring the charges from the third succeeding row R₄ of photosensitive elements 12, the column electrodes 16 must be thereafter set to a high voltage level in order to accommodate the readout of the fixed pattern noise. Toward that end and in conjunction with the subsequent transfer of charge from the photosensitive elements 12 of row R₄, the row R₁ electrodes 14 are set to a low voltage by turning on transistor T₅. In this manner, the row R₁ photosensitive elements 12 are cleared of charge since both the row electrodes 14 and the column electrodes 16 are simultaneously set to a low voltage. The row R₁ electrodes 14 are subsequently brought back to a high voltage level in concert with the aforementioned turning off of all the T₅ transistors. Resetting all the column electrode 16 voltages to the voltage level at each respective node B in the aforementioned manner by turning on all the T₄ transistors, as will be readily understood, also operates to set the column electrodes 16 of the row R₁ of photosensitive elements to a high voltage level. In the last step of the sequence, the row scan circuit 19 operates to set the row electrodes 14 of the first row R₁ of photosensitive elements 12 to a low voltage. As will be now understood, the four photosensitive elements 12 of row R₁ are cleared of signal charge so that the signal transfer to respective ones of the node A by way of respective ones of the column interconnect lines 16 C₁ - 16 C₄ defines the fixed pattern noise for respective ones of the photosensitive elements 12 of row R₁. In this manner fixed pattern noise defining electronic information signals for each photosensitive element 12 of row R₁ are transferred outside of the succeeding order in which image and KTC noise defining electronic information signals are transferred for the photosensitive elements of row R₁. Instead, the fixed pattern noise defining electronic information signals for the photosensitive elements 12 of R₁ are transferred in sequence with the transfer of image and KTC noise defining electronic information signals for the photosensitive elements 12 of row R₄. The signal level at node A is subsequently amplified in the aforementioned manner to provide an amplified output electronic information signal at node B corresponding to the fixed pattern noise. The fixed pattern noise defining electronic information signal is thereafter sampled and transferred in the aforementioned manner to the input stage 26 of the storage line 22₁. As will be readily understood, prior to the transfer of the fixed pattern noise defining electronic information signal to the input stage 26, the previously transferred image and KTC noise defining electronic information signals for the photosensitive elements of row R₁ are successively advanced in correspondence with the transfer of image and noise defining electronic information signals from the three succeeding rows R₂, R₃ and R₄ along succeeding storage areas or phases of the storage line 22₁. Thus, in this manner three succeeding electronic information signals for each photosensitive element 12 are provided in ordered spaced apart sequence from the amplifier 20₁ to the storage line 22₁. In this manner, three spaced apart electronic information signals are provided for each row R₁ photosensitive element wherein the first signal corresponds to image defining scene light incident to the row R₁ photosensitive element together with the KTC and fixed pattern noise associated with the row R₁ photosensitive element, and the second signal which immediately succeeds the first signal corresponds to the KTC noise associated with the row R₁ photosensitive element. The third signal which succeeds the transfer of signals from the row R₄ photosensitive element corresponds to the fixed pattern noise associated with the row R₁ photosensitive element. As is readily apparent, this ordered sequence for the transfer of electronic information signals although described only for the first row R₁ photosensitive elements is sequentially repeated for the photosensitive elements of all the succeeding rows R₂ - R₄. Referring now to FIG. 3A in conjunction with FIGS. 3B and 3C, there can be seen the location of charges in various storage areas or phases in the storage stages 28₁ - 28 n at various time intervals t₁ - t₄. Electrodes or gates associated with the various storage areas or phases ( 1 -  4) operate in a well-known manner to advance the aforementioned succeeding electronic information signals along the storage stages 28₁ - 28 n until reaching the positions as shown at t₁ in FIG. 3B. Thus, at time t₁ the first image defining electronic information signal including the KTC and fixed pattern noise first transferred from the amplifier 20₁ to storage line 22₁ is advanced to the fourth phase  4 of storage stage 28 n-1 as shown at SIG₁. In like manner, the second succeeding electronic information signal corresponding to the KTC noise is advanced to the fourth phase  4 of storage stage 28 n-2 as shown at KTC₁. It is readily apparent that this pattern is repeated for each succeeding photosensitive element 12 until reaching the electronic information signal for the KTC noise for the 4 th photosensitive element 12 as stored in the fourth phase  4 of the storage stage 28₂ and shown at KTC₄. The next succeeding electronic information signal stored in the fourth phase  4 of storage stage 28₁ corresponds to the fixed pattern noise for the first photosensitive element 12 to which the image defining electronic information signal SIG₁ and the KTC₁ correspond. As is readily apparent, for the aforementioned example n = 12, and thus the fixed pattern noise defining electronic information signal as shown at FPN₁ is transferred in succeeding order with the image and noise defining electronic information signals and the KTC noise defining electronic information signals (KTC₄) for the fourth photosensitive element in the column. The control voltages to the four phases ( 1 -  4) change in a time interval from t₁ to t₂ as shown in FIG. 3C to advance the charges along the storage stages 20₁ through 28 n as shown in line t₂ of FIG. 3B. In the next succeeding time t₃, the phase electrode control voltages change as shown in FIG. 3C to advance the charges to the position as shown at line t₃ in FIG. 3B. At time t₃ it can be seen that the image and noise defining electronic information signal (SIG₁) is located in the second phase  2 of storage stage 28 n adjacent transfer electrode 30₄. The fourth phase  4 of storage stage 28 n-2 under transfer electrode 30₃ has just been cleared of KTC defining electronic information signals (KTC₁) so as to leave a signal level corresponding to the negative value of the KTC defining electronic information signal (-KTC₁). The KTC defining electronic information signals (KTC₄) for the fourth succeeding photosensitive element 12 in the respective column can be seen to be advanced to the second phase  2 of the storage stage 28₃ under transfer electrode 30₂. The fourth phase  4 of the storage stage 28₁ under transfer electrode 30₁ has just been cleared of the fixed pattern noise defining electronic information signal (FPN₁) so as to leave a signal level corresponding to the negative value of the fixed pattern noise defining electronic information signal (-FPN₁). Thus, at the beginning of each line time (t₁) as is now readily apparent, the KTC noise defining electronic information signal (KTC₁) and a fixed pattern noise defining electronic information signal (FPN₁) are located, respectively, under the third and first floating transfer gates 30₃ and 30₁. At the same time, t₁ the storage areas or phases under the second and fourth floating transfer gates 30₂ and 30₄, respectively, are clear of charge. At this time (t₁), the floating transfer gates 30₁ - 30₄ are set to a high signal level V BIAS by transistor T₆ on through control voltage V RES . Transistor T₆ is thereafter turned off so as to allow the transfer gates 30₁ through 30₄ to float at the aforesaid high signal V BIAS . During the second succeeding transfer cycle as shown at line t₃ in FIG. 3B, the charges corresponding to KTC defining electronic information signals (KTC₁) and the fixed pattern noise defining electronic information signals (FPN₁) are transferred from the third and first floating transfer gates 30₃ and 30₁, respectively, offsetting the voltage at which the gates are floated. At the same time the image and noise defining electronic information signal (SIG₁) and the KTC noise defining electronic information signal (KTC₄) are transferred to the fourth and second transfer gates 30₄, 30₂, respectively, adding to the signal level at which the transfer gates are floated. In this manner an image defining electronic information signal is automatically provided at the common node of the transfer gates 30₁ through 30₄ from which KTC noise defining electronic information signals and fixed pattern noise defining electronic information signals are automatically cancelled. As will be readily understood, the fixed pattern noise defining electronic information signals are sensed from each photoresponsive element in each respective column after the charge has been cleared from the next three succeeding photoresponsive elements in each respective column. Thus, the fixed pattern noise defining electronic information signals are sensed from the photoresponsive elements 12 outside the succeeding order in which the image and KTC noise defining electronic information signals are sensed from the photosensitive elements. Instead, the fixed pattern noise defining electronic information signals are sensed from the photosensitive elements 12 in correlation with the sensing of image and KTC noise defining electronic information signals for photosensitive elements spaced apart therefrom by three photosensitive elements along their respective columns. As should now be readily apparent, the fixed pattern noise defining electronic information signal (FPN₁) sensed after the fourth photoresponsive element also inherently includes KTC noise defining electronic information signals for the fourth photoresponsive element. Thus, the transfer of the KTC noise defining electronic information signal (KTC₄) for the fourth photoresponsive element transferred to the second floating transistor electrode 30₂ is offset by its identical component which forms an inherent part of the fixed pattern noise defining electronic information signal (FPN₁) subtracted from the signal level of the first floating transfer electrode 30₁. The signal level at the common node between the floating transfer electrodes 30₁ through 30₄ thus provides an image defining electronic information signal in ordered sequence for each succeeding photosensitive element 12 from which both the KTC and fixed pattern noise defining electronic information signals are automatically offset. This image defining electronic information signal is amplified by the amplifier 32 and output at terminal V out to the serial shift register 24 which operates in a well-known manner to provide a continuous stream of image defining electronic information signals for each succeeding photosensitive element in each row. The invention herein described is by no means limited to the above-described order in which the image and noise defining electronic information signals are transferred from the photosensitive elements provided that the fixed pattern noise defining electronic information signals are transferred only after the next three succeeding rows of photosensitive elements are cleared of charge.

Claims: A charge injection device comprising: an array of photosensitive elements (12) each one of which has noise defining electronic information signals associated therewith and generates image defining electronic information signals in response to incident scene light; means (16,20) for transferring and amplifying said image and noise defining electronic information signals from said array of photosensitive elements (12) in a selectively ordered sequence; a plurality of serially connected storage elements (22) connected to receive said amplified image and noise defining electronic information signals in said selectively ordered sequence, each of said storage elements (22) being structured to store image and/or noise defining electronic information signals corresponding to one of said photosensitive elements (12) in said array; means for advancing said image and noise defining electronic information signals through said serially connected storage elements in a manner whereby each of said storage elements stores a respective one of the image and/or noise defining electronic information signals for each photosensitive element for a determined time interval; and means for simultaneously retrieving selected image and noise defining electronic information signals from selected ones of said serially connected storage elements (22) at select succeeding ones of said determined time intervals to provide image defining electronic information signals for each succeeding photosensitive element from which the noise defining electronic information signals are automatically cancelled. The charge injection device of claim 1 wherein: said array of photosensitive elements (12) is a two-dimensional array of photosensitive elements arranged in rows (R) and columns (C); said means for transferring (16) and amplifying (20) said image and noise defining electronic information signals operates to simultaneously transfer image and/or or noise defining electronic information signals for each photosensitive element (12) of each row (R) of said array, and also operates to transfer image and/or noise defining electronic information signals in succeeding order for each photosensitive element (12) along each column (C) wherein a portion of said noise defining electronic information signals for each photosensitive element (12) are transferred outside of said succeeding order in correlation with the transfer of image and noise defining electronic information signals for photosensitive elements (12) spaced apart therefrom along their respective columns (C); said serially connected storage elements (22) are structured to simultaneously store said image and/or noise defining electronic information signals for each said photosensitive element in each row (R) in the order in which said signals are transferred from their respective columns (C); said advancing means operates to simultaneously advance said image and/or noise defining electronic information signals for each photosensitive element (12) in each row (R) in the order in which said signals are transferred from their respective columns (C) along said serially connected storage elements (12) and said retrieving means includes means for simultaneously retrieving said image and/or noise defining electronic information signals for each photosensitive element in each row in succeeding order from their respective columns including said portions of said noise defining electronic information signals transferred outside of said succeeding order. The charge injection device of claim 2 wherein: said plurality of storage elements (28) comprises a plurality of serially connected charge coupled device (CCD) stages each stage of which comprises a select number of distinct storage areas (1 - 4) through which the advancement of image and/or noise defining electronic information signals are controlled by the selective sequential energization of a first plurality of electrodes (30) associated with respective ones of said stages (28) and said means for simultaneously retrieving selected image and/or noise defining electronic information signals comprises a second plurality of electrodes in common connection with respect to each other and associated with select ones of said distinct storage areas (1 - 4). The charge injection device of claim 2 wherein said means for simultaneously retrieving selected image and/or noise defining electronic information signals further comprises control means (T₆) for setting the signal level of said common connection between said second plurality of electrodes (30) to a select level immediately prior to said select succeeding ones of said determined time intervals during which said select image and/or noise defining electronic information signals are retrieved and thereafter floating said common connection during said select succeeding ones of said determined time intervals. The charge injection device of claim 3 wherein said means for transferring and amplifying said image and/or noise defining electronic information signals operates to transfer an image and noise defining electronic information signal corresponding to incident scene light, KTC noise and fixed pattern noise, and a KTC noise defining electronic information signal in succeeding order for each succeeding photosensitive element (12) in their respective columns (C) and a fixed pattern noise defining electronic information signal corresponding to each said succeeding photosensitive element (12) but transferred outside of said succeeding order of transfer, said storage means (22) operates to store said image and noise defining electronic information signal, said KTC noise defining electronic information signal and said fixed pattern noise defining electronic information signal in select succeeding ones of said storage area (1 - 4) of said serially connected charge coupled device (CCD stages), said advancing means operates to advance said image and noise defining electronic information signal, said KTC noise defining electronic information signal and said fixed pattern noise defining electronic information signal through said serially connected storage elements (28) and said retrieving means operates to simultaneously retrieve for each succeeding photosensitive element (12) the image and noise defining electronic information signal, and KTC noise defining electronic information signal, and fixed pattern noise defining electronic information signal for that photosensitive element (12) in a manner providing an image defining electronic information signal for each succeeding photosensitive element that does not include either KTC or fixed pattern noise defining electronic information signals. The charge injection device of claim 2 wherein said array of photosensitive elements (12) includes a column electrode (16) and a row electrode (14) for each photosensitive element (12) together with means (16R, 14C) for providing a common connection between all the electrodes in each column (C) and each row (R), respectively, and said means for transferring and amplifying said image and/or noise defining electronic information signals comprises amplifying means (20) for amplifying said image and/or noise defining electronic information signals from each of said columns (C) of commonly connected electrodes (16) reset means (T₃,T₄) for setting the signal level of each of said columns of commonly connected electrodes to determined high signal levels at select times, and clearing means (T₅) for setting the signal level of each of said columns (C) of commonly connected electrodes (16) to determined low signal levels at select times. The charge injection device of claim 6 including sampling means operatively associated with said amplifying means and said storage means for repeatedly sampling the signal level output from said amplifying means and directing the total value of said repeatedly sampled signal level for storage in the first of said serially connected storage elements (28) so as to reduce the bandwidth of said amplifying means (20). The charge injection device of claim 7 wherein said amplifying means (20) comprises for each column a pair of MOS field effect transistors (T₁,T₂) connected in cascade with respect to each other with the gate of one (T₁) of said MOS field effect transistors of each pair connecting to a respective one of said commonly connected column electrodes (16) each pair of MOS field effect transistors also being in serial connection with respect to a load resistor (R L ) and in parallel connection with respect to an output capacitor (C₀) said load resistor (R L ) and output capacitor (C₀) cooperatively operating to limit the bandwidth of said amplifying means (20). The charge injection device of claim 8 wherein said reset means for setting the signal level of each of said columns (C) of commonly connected electrodes comprises for each column another pair of MOS field effect transistors (T₃, T₄) connected in cascade with respect to each other wherein the drain electrode of one (T₃) of said MOS field effect transistors (T₃, T₄) of each of said other pair of reset transistors connects to a respective one of said commonly connected column electrodes (16), and the gate electrode of the other on (T₃) of said MOS field effect transistors of each of said other pair is in respective common connection with respect to said load resistor (R L ), said output capacitor (C₀) and the source electrode of the other (T₂) of said MOS field effect transistors of said pair of amplifier transistors (T₁,T₂). The charge injection device of claim 9 wherein said clearing means for setting the signal level of each of said columns (C) of commonly connected electrodes (12) to determined low signal levels comprises for each column an MOS field effect transistor (T₅) the source electrode of each one of which connects to a respective one of said commonly connected column electrodes (16) and the drain electrode of each one of which connects, respectively, to a source (V SS ) for providing said determinate low signal level.

Inventors: BENCUYA SELIM S, MICHON GERALD J, TIEMANN JEROME J, TOKER JAMES R, VOGELSONG THOMAS L, BENCUYA, SELIM S., MICHON, GERALD J., TIEMANN, JEROME J., TOKER, JAMES R., VOGELSONG, THOMAS L.
Applicants: POLAROID CORP, POLAROID CORPORATION
Application year: 1989
Main classification: H04N3
IPC codes: H04N5, H04N3, H01L29, H01L21, H01L27