Method for placement of nodes in a graph based diagram

Abstract: A method for the placement of nodes in a net diagram, whereby said method includes the determination of positional relationships between nodes that are not directly connected.

Description: BACKGROUND OF THE INVENTION The present invention relates to a method for automatic placement of nodes in a graph based diagram (net diagram) representing a technical system including a logic diagram, a process diagram, a relational tree diagram, a layout of a printed circuit board. For a conventional schematic generator, various proposals have been presented. For example, articles of such proposals have been described in the JP-A-61-204775, "A Method of Generating a Logic Diagram" in the Technical Report CAS84-134 published in 1984 from the Institute or Electronics and Communication Engineers of Japan, an article entilted "A Visibility Oriented Construction System for LOGIC diagrams", in SYSTEMS and COMPUTERS in JAPAN, VOL 17 NO 7, July 86, pages 40-48, T. Hasegawa et al., the JP-A-60-205672, and the JP-A-60-176177. In an ordinary schematic generator, an entire logic circuit is subdivided through a logic division such that for each subdivided portion, arrangement of diagram drawing symbols of respective circuit parts and the like are determined in the subdivided constituent circuit through an automatic placement or placement. Routings between the circuit parts are determined through an automatic routing. In another ordinary schematic generator, the circuit parts are arranged so as to be thereafter divided, thereby generating a logic circuit diagram. These methods produces a clear diagram primarily by subdividing a logic circuit diagram in an effective fashion, by employing a hierarchic representation of the logic circuit diagram, or by using properties of particular circuit parts other than the connective relationships between the circuit parts. Moreover, conventionally, according to a method of arranging circuit parts of a logical circuit diagram in the schematic generating method, locations in which drawing symbols are allocatable are limited to positions defined by assuming a checkerboard or grid on the objective diagram. The placements are then sequentially determined beginning from an end of the diagram in a fixed direction (for example, from an output side to an input side or in a reverse direction thereto) according to the connective relationships between the drawings symbols (namely, between the circuit parts). In a procedure to decide the placements, each drawing symbols are assigned with a level (namely, a column for placement or placement) based on the connective relationships with an input terminal (or an input port) or an output terminal (or an output port) set as a start point or an initial point. Subsequently, intersection of the routings between the drawing symbols of the previous column (level) already assigned with positions and drawing symbols to be positioned, or the total length of the routings is minimized so as to sequentially allocating the drawing symbols of the respective columns. However, the number of placements is not necessarily limited to one. Usually, a sequential position decision from the output terminal (or the input terminal) to the input terminal (or the output terminal) and a sequential position decision in the reverse direction are repeatedly executed, thereby determining a better placement in an ordinary case. This method however is considerably less advantageous as compared with a diagram manually produced by use of a computer aided system (CAD) such as a diagram editor with regard to visibility or easy understanding of the diagram. Incidentally, for information about this type of method, reference is to be made, for example, to pages 1901 to 1904 and pages 1973 to 1974 of the 30th National Conventional Record of the Information Processing Society of Japan (1st period of 1985), the JP-A-61-204775, and pages 47 to 54 of the Technical Report CAS84-134 published in 1984 from the Institute of Electronics and Communication Engineers of Japan. According to the conventional example above, for the placements of the drawing symbols representing the respective circuit parts and routings or routing therebetween, usually, provisional placements and routings are once determined so as to correct the resultant placements or routings in view of being easy to see. This operation however is attended with a disadvantage of a low processing efficiency. Furthermore, in the procedure of allocating the drawing symbols, the parts are located in the positions of the centers of gravity in which the parts are connected one other or the positions in which the total routing length will be minimized. In addition, in the allocate processing, the visibility of the routings to be processed later has not been taken into consideration. As a result, a produced logic circuit diagram has not a satisfactory visibility in some cases. Moreover, the schematic generating method has been strongly dependent on a utilization purpose thereof and on characteristics and technologies of an objective circuit, namely, considerations are not given to the generalized utilization. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for automatic placement of nodes in a graph based diagram representing a technical system, thereby removing the problems of the prior art technology. The object above can be achieved in a method as set out in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantages of the present invention will become apparent by reference to the following description and accompanying drawings wherein: Fig. 1 is a schematic configuration diagram of a schematic generator of automatically producing a logic circuit diagram as an embodiment according to the present invention; Fig. 2 is an explanatory diagram useful to explain an example of contour information; Fig. 3 is an explanatory diagram useful to explain an example of net information; Fig. 4 is an explanatory diagram useful to explain an example of logic diagram information; Fig. 5 is a logic circuit diagram showing an output example of a logic circuit diagram; Fig. 6 is a flowchart showing an example of processing to assign levels to elements; Fig. 7 is an explanatory diagram useful to explain an example of a net diagram; Fig. 8 is an explanatory diagram useful to explain an example of a data structure keeping loop information; Fig. 9 is an explanatory diagram useful to explain an example of a net diagram assigned with levels; Fig. 10 is a flowchart showing an example of processing to determine a reference level position; Fig. 11 is an explanatory diagram useful to explain a portion of a net diagram assigned with levels; Fig. 12 is an explanatory diagram useful to explain a priority order of node pairs; Fig. 13 is an explanatory diagram useful to explain a net diagram example after positional relationships are determined for the reference level; Fig. 14 is a flowchart showing an example of a relative placement processing of each level pair; Fig. 15 is an explanatory diagram useful to explain an example of a data structure keeping positional relationship information of nodes; Figs. 16, 19, and 20 are explanatory diagrams useful to explain example of positional relationship information of nodes; Fig. 17 is an explanatory diagram useful to explain a bipartite graph; Fig. 18 is an explanatory diagram useful to explain the maximum matching of the bipartite graph; Fig. 21 is an explanatory diagram useful to explain a pin placement of the elements; Fig. 22 is an explanatory diagram useful to explain relationships between placement elements and routing patterns; Fig. 23 is a logic circuit diagram for explaining determination of precise positions of placement elements; Fig. 24 is a flowchart showing an example of a routing processing at each level; Fig. 25 is an explanatory diagram useful to explain kinds of routings; Fig. 26 is a flowchart showing an example of a routing processing for each routing kind; and Fig. 27 is an explanatory diagram useful to explain a virtual routing length. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, a description will be given of an embodiment according to the present invention. Particularly, in this embodiment, although an example of an automatic generation of a logic circuit diagram based on connective information (i.e. a net list) of a logic circuit, creation of the other net diagrams will be easily inferred from the description. Overall System Configuration Fig. 1 shows a schematic generator for automatically generating a logic circuit as an embodiment according to the present invention. This system includes a net information file 1 storing therein information about element (including circuit parts) and connective or connecting information thereof, a contour information file 2 for storing therein contour or shape information of drawing symbols representing respective elements, a logic diagram information file 3 for storing therein drawing information about placements or placements and wirings or routings of a logic circuit diagram (also called a logic diagram), a cell library 4 storing therein contour information and functional information of each element, logic diagram drawing section 5 for receiving as an input thereto the logic diagram information to draw a logic circuit diagram by use of a drawing terminal 51 such as a display or a plotter, and a placement/routing processing section 11-16. For example, the net information file 1 keeps a net list (connective information) or the like of a logic circuit obtained as an output from an automatic logic synthesizing system or an automatic circuit transforming system. Information stored in the net information file 1 may also be employed for a logical vertification, a timing check, an automatic layout system, etc. In the element level assignment 11, based on the number of logical stages from an input port (input terminal) of each of the elements and the circuit parts contained in the net list kept in the net information file 1, a level is determined for each element and for each circuit part. In the reference level position determination 12, the system determines positional relationships in a direction orthogonal to a level direction between the elements or circuit parts at the reference level (namely, sequential relationships for placing or arranging elements or circuit parts in a direction vertical to the level direction). In this embodiment, for simplification, the maximum level (i.e. a level at which an output port exists) is set as the reference level; however, even if a level at which an input port exists (namely, level 0) is set as the reference or elements and circuit parts at a plurality of levels are assigned with the reference level, there does not occur any problem. In the relative placement at each level 13, based on sequential relationships of positions of the elements (i.e. components or circuit parts) at the reference level, positional relationships of positions are determined for elements at the next level (in this embodiment, at the next level in the descending order), thereby determining sequential relationships of positions for all elements of the logic circuit. In the placement processing 11 to 13, few considerations have been given to the contour of each placement element (namely, to the contour of each drawing symbol of the elements and circuit parts). In consequence, assuming that the level of each element determined through the placement steps 11 to 13 is a first (global) coordinate and that a sequence obtained from sequential relationships of positions also determined through the placement steps 11 to 13 is a second (global) coordinate, graphic placement (not related to the contour) is determined for each element. Incidentally, in this example, the sequential relationships of positions at each level are determined in a descending order. However, when the reference level is set to the level 0, the relationships are to be determined in the ascending level order; whereas in other cases, the relationships are to be determined in both directions including the ascending and descending level orders. On the other hand, the contour information file 2 keeps information related to the contour of each drawing symbol used in a logic diagram. As an example, Fig. 2 shows the contour information kept in the contour information file 2. This example includes sizes (size), positions of input pins (in(i) and in(ia)), and positions of output pins (out(o)) of drawing symbols of an inverter, a 2-input AND gate, and a 3-input AND gate. These positions are represented by use of relative coordinates with respect to the reference point of the respective symbol. However, the size of a drawing symbol is expressed with a pair of the minimum and maximum coordinates of vertices of a rectangle circumscribing the symbols. In the fine adjustment of element placement 14, based on the first and second coordinates of each placement element determined in the processing 11 to 13, the placement or placement thereof is roughly decided. Thereafter the system allocates signals to pins to determine connections between pins of each element and signal lines thereto so as to minimize bending portions and intersections of routings, orientations of the respective placement elements, and precise coordinates thereof by use of the contour information of the respective placement elements. In consequence, the processing 14 physically allocates the elements with consideration of the orientations (including the mirror inversion) thereof and positions and sizes of pins, thereby determining placements of the elements in the diagram. In the routing at each level 15, connecting signals between placement elements determined by the placement processing above are sequentially wired so as to determine the routes or routings between all placement elements. In this embodiment, although the description will be given of only a case where the routing is sequentially achieved for each level in order of the higher beginning from the output port side, the routing of the other cases may also be easily inferred from the description. Incedentally, the coordinate of the routing is represented by use of the global coordinate determined in the processing 11 to 13 and the local coordinate which is the detailed coordinate information obtained in the processing 14. In the absolute coordinate determination 16, based on the resultant data of the processing above including the allocating positions of the respective elements and the global and local coordinates representing the routing positions, the absolute coordinates of placements and routings of the overall logic circuit diagram are determined so as to be stored in the logic diagram information file 3. Fig. 3 shows an example of a net list to be stored in the net information file 3. This example indicates that an element of dev1 has a cell name inv00, an input signal k1, and an output signal net1, etc. Fig. 4 shows an example of logic diagram information to be kept in the logic diagram information file 3 in a case where the contour information file 2 before hand keeps contour information of Fig. 2 such that an example of Fig. 3 is inputted in this state to the system so as to execute the processings 11 to 16. In the example of Fig. 4, there are indicated placement information such that an element dev1 with a cell name inv00 has position of a reference point represented with a coordinate (12, 13) and a rotary angle is 0 without the mirror inversion and routing information such that end points of a signal line with a signal name net1 are denoted by coordinates (17, 13) and (25, 18) so as to link coordinates (17, 13), (21, 13), (21, 18), and (25, 18). Furthermore, when the logic diagram information of Fig. 4 is supplied to the logic diagram generate section 5, a logic diagram as shown in Fig. 5 is outputted on the drawing terminal (i.e. a display, a plotter, or the like) 51. Incidentally, the logic diagram generate section 5 is ordinarily a logic diagram edit system (schematic editor), which is provided with the cell library 4 and the drawing terminal 51. In this situation, integrity is required to be preserved between the information kept in the contour information file 2 and the content of the cell library 4. Next, a description will be given in detail of the placement/routing processings 11 to 16. Element Level Assignment A method of assigning levels to nodes of a net diagram will be described by referring to Fig. 6. Fig. 6 is a flowchart showing an example of a detailed processing procedure of the element level assignment 11. A step 61 is disposed to set level 0. In this embodiment, all input ports are assigned with level 0. However, for a circuit not having any input port, level 0 may possibly be assigned to an element or a circuit part which does not receive any input. In a step of loop detection 62, loops are detected in the circuit based on the net list to produce loop information. For example, in a case of an example of a net diagram shown in Fig. 7, three loops A → B → H → F → D → A, A → C → E → F → D → A, and H → F → D → G → I → H are detected to create loop information as shown in Fig. 8. However, in the example of Fig. 8, loop information is stored in a data structure of a list format. Arrows in this diagram represent pointers. Incidentally, referring to an example of a net diagram of Fig. 7, if the elements and signal lines of a logic circuit diagram are respectively assumed to be nodes and arcs, the logic circuit diagram may be considered as a kind of a net diagram. Although, this embodiment detects all loops, the system need not necessarily detect all loops. In a latch recognition 63, the loops detected in the loop detection 62 are checked so as to extract any loops having a latch structure. Namely, of all loops, any loop comprising a pair (latch pair) of two nodes (elements) is detected so as to be removed from the loop information. Thereafter, subsequent processing is executed on assumption that these pairs are at the same level. However, in a case where a node is included in a plurality of latch pairs, it may be possible to adopt a selection method to select, from the pairs, one having the smaller number of input arcs thereto. In a level assignment by logic stages 64, each node (element) is sequentially assigned with a level in a method such that if all nodes (elements) connected to an input of an assignment objective node (element) are assigned with levels and the maximum value of the level is L, the pertinent node (element) is assigned with a level L + 1. Incidentally, for a latch pair, a simple method may be adopted in which the latch pair is assumed to be a node (element). In a judge processing 65, the system judges to determine whether or not all nodes (elements) have been assigned with levels. If this is the case, a maximum level assignment 72 is processed; otherwise, the judge processing 66 is continuously executed. Incidentally, in this embodiment, the processing steps 64 and 65 are applied to the nodes (elements) other than an output port. In a judge processing 66, it is judged to determine whether or not the loop information is empty. If empty, the loop processing has been completed and hence a processing step 70 is executed; otherwise, the loop processing has not been completed yet and hence the processing 68 is achieved. In this description, when the loop information is empty, it is assumed that the loop information does not contain any loop registered thereto. In a processing step 67, the system detects, based on the loop information, a location (i.e. an arc) where the overlapping of a plurality of loops develops the maximum value. For example, in an example of Fig. 8, the degree of overlapping between the arcs D → A and H → F is two; whereas the overlapping degree of F → D is three. Consequently, the location of the maximum overlapping degree is determined to be the arc F → D. In this example, only one location is associated with the maximum overlapping degree; however, if a plurality of locations are related to the maximum overlapping degree, the system determines all the locations. In a processing step 68, the locations (arcs) of the maximum overlapping degree are checked to set an arc as a feedback arc. That is, a node having the feedback arc as an input thereto is determined and all loops including the pertinent node are removed from the loop information. For example, in the example of Fig. 8, the arc F → D is selected as the feedback arc and the node D is determined as the objective node. In consequence, all loops of Fig. 8 are removed and the loop information becomes to be empty. Furthermore, in a case where a plurality of maximum overlapping locations exist in this embodiment, from the start point nodes of input arcs to the node having the arcs regarding the maximum overlapping locations as inputs thereto, the system employs a method to sequentially select a node in the priority order of 1 ○ a node associated with a smaller number of nodes to which levels are not assigned, 2 ○ a node associated with a greater number of nodes to which levels are assigned, or 3 ○ a node associated with a smaller value of the maximum level of the nodes to which levels are assigned, thereby determining a node as an input destination of the feedback arc. However, various combinations of the priority rules 1 ○ , 2 ○ , or 3 ○ may be applicable. Incidentally, in this embodiment, a case in which the overlapping of arcs develops the maximum value has been considered; however, a case where the overlapping of nodes takes the maximum value may also be easily analogized from the description. In a processing step 69, the node determined in the step 68 (namely, the input destination node of the feedback arc) is assigned with a level. As a method of assigning a level to an objective node, in a case where of the start point nodes of the input arc to the objective node, the nodes already assigned with levels have the maximum level M; the objective node is then assigned with a level M + 1. In this processing, after a level is assinged to at least a node in the loop, the step 64 is executed again. Incidentally, in a case where any start point nodes of the input arcs to the node determined in the step 68 are not assigned with levels, a method similar to a method used in a processing step 71, which will be described later, is adopted to assign levels to the nodes. In a processing step 70, the nodes not assigned with levels in the processings 64 to 69 are checked so as to determine a node to be next assigned with a level. More concretely, the system selects a node not having an input arc. In a processing step 71, a level is assigned to the node determined in the step 70. For example, the nodes are checked beginning from the determined node in a direction toward an output thereof to find a first node assigned with a level so as to determine a level of the node which is selected in step 71 through a computation based on the level of a node having an input arc from the first node assigned with a level. Or, the node is assigned with a level 1 or 0. After a level is assigned to at least a node in the processing 71, the processing 64 is re-executed. Finally, in a maximum level setting step 72, assuming the maximum level of the nodes assigned with the levels to be N, the levels of all output ports are set to N + 1, thereby terminating the processing. Incidentally, in the processing steps 64 to 71, for simplification, a latch pair may be assumed to be a node for the processing. In the method of assigning levels to nodes of a net diagram, the levels of nodes of the example of Fig. 7 are assigned as shown in Fig. 9. As can be also easily seen from this example, the number of feedback arcs is decreased, which improves the visibility of the diagram and the understandability of the signal flows. In other words, the example of Fig. 7 includes three loops and hence there are generated three feedback arcs in the worst case; however, as can be seen from the result of Fig. 9, only a feedback arc F → D is used and hence the signal flows from the left to the right, which facilitates understanding of the signal flows in the obtained circuit diagram. Incidentally, in the example of Fig. 6, although the loop detection 62 and the latch recognition 63 are disposed as two separate steps, these operations may be executed in a step. Moreover, although these processing steps are consecutively achieved in the starting portion of the processing procedure, even if these operations are placed before the processing 66 or 67, there does not occur any particular problem. Determination of Reference Level Position Referring now to Fig. 10, a description will be given of a method of determining a node position of a net diagram according to the present invention. Fig. 10 shows a flowchart including processing steps 101 to 105 as an example of a detailed processing procedure of the reference level position determination 12. The respective processing steps will be specifically described in the following paragraphs. The processing 101 is disposed to set node pairs each including two nodes at the reference level (output ports in this embodiment) without duplication therebetween. For example, in an example of Fig. 11, the reference level is assigned to the nodes A, B, C, and D, and hence six pairs are established as A-B, A-C, A-D, B-C, B-D, and C-D. Incidentally, in this embodiment, only the output ports are set as the nodes at the reference level for simplification; however, any cases in which positional relationships are to be determined between nodes including elements and circuit parts other than the output ports may also be easily inferred from the description. In the processing 102, the node pairs set in the step 101 are checked to detect an ancestor common to the node pairs as follows so as to compute a level difference (generation difference) between each pair and the common ancestor and a degree of consanguinity thereof. As a method of detecting the common ancestor, the detection is achieved by assigning a higher priority to a node having a smaller level difference with respect to the node pair or to a node having the smaller sum of the number of arcs drawn from two nodes thereof. In addition, the degree of consanguinity of two nodes indicates the minimum value of the total of arcs existing in the paths from the respective nodes to the common ancestor. By the way, for a node pair for which the common ancestor is not detected, control is passed to the subsequent processing without executing the computations of the level difference and the degree of consanguinity with respect to the common ancestor. In the processing step 103, the system checks to determine whether or not all node pairs established in the step 101 have processed in the step 102. If any node pair is remained unprocessed, the processing 102 is conducted for the node pair; otherwise, the processing step 104 is executed. In the step 104, based on the computation results of the processing step 102, namely, the level difference and the degree of consanguinity of each node pair with respect to the common ancestor, the priority sequence is determined between node pairs. More specifically, a node pair having the smaller level difference with respect to the common ancestor takes precedence. Furthermore, a node pair having the smaller degree of consanguinity is assigned with the higher priority in the processing. For example, in the example of Fig. 11, the priority sequence is determined as shown in Fig. 12. That is, the priority sequence is set in an order of pairs A-C, B-C, A-B, B-D, A-D, and C-D. Finally, in the processing step 105, according to the priority sequence obtained in the preceding step 104, the positional relationships between nodes at the reference level are determined such that a node pair having the higher priority is assigned with the nearer positional relationship, thereby terminating the processing. For example, in the example of Fig. 11, the priority sequence of the node pairs is set as shown in Fig. 12. In consequence, by sequentially linking the node pairs beginning from the node pair which has the order of priority, the positional relationships can be decided. More concretely, based on the pair A-C, C is placed next to A; thereafter, from the pair B-C, B is located next to C. Next, if B is positioned next to A, a loop is formed. To avoid the condition of the loop, the pair A-B is not used such that based on the pair B-D, D is placed next to B. As a result, as shown in Fig. 13, the positional relationships between the nodes A to D are determined. In this example, in order to obtain the positional relationships, three pairs A-C, C-B, and B-D are employed; however, even if the pair A-B is adopted in place of the pair C-B, only the positions of A and C are exchanged in the result as compared with that shown in Fig. 13. Namely, with respect to the visibility of the diagram, there does not occur any problem. Furthermore, the order of A to D of Fig. 13 may be reversed. Also in this case, any problem does not take place in this regard. Actually, the order is to be determined depending on the other factors (for example, a meaning of a signal on an output port). In the method of determining positions of nodes or elements according to the present invention, as shown in Fig. 13, it is possible to minimize routing intersections in the proximity of the reference level. This unnecessitates the correction of placement or placement in the neighborhood of the output port of the logic circuit diagram after the placement is completed. In the examples above, the level difference with respect to the common ancestor takes precedence over the degree of consanguinity; however, a case where the consanguinity takes precedence over the level difference may also be easily analogized and hence a description thereof will be omitted. Relative Placement at Each Level Referring now to Fig. 14, a description will be given of an placement method of a net diagram according to an embodiment of the present invention. Fig. 14 is a flowchart including processing steps 141 to 148 as an example of a detailed processing procedure executed in the relative placement at each level 13. First, prior to a concrete description of the respective processing, a data structure of positional relationship information employed in these processing steps will be described. Fig. 15 shows a data structure of information representing positional relationships between the respective nodes. In this data structure, a plurality of node lists 151 are linked by means of cells 150 representing sequential relationships between the lists 151. Moreover, the cell 150 comprises a pointer 153 indicating a sequence associated with lists and a pointer 152 denoting a sequence of node lists. In addition, a cell 154 constituting the node lists includes a pointer designating a node name or a node and a pointer 156 indicating the remaining portion of the list 151. Referring next to the data structure of Fig. 15, description will be given of the respective processing. In the setting of nodes at maximum level 141, the positional relationships of the nodes at the reference level (namely, the output ports) determined at the reference level position are stored in the first positions of the respective node lists in the data structure of Fig. 15 so as to preserve the positional relationships. For example, in the example of Fig. 13, the positional relationship information is stored in a form of Fig. 16. Subsequently, in the processing 142, the maximum level (namely, the level of the output port) is set to the level counter L. In the next step 143, a bipartite graph is produced for the level L. More specifically, based on the respective node lists in the positional relationship information of Fig. 15, the system checks the final nodes (stored in the right-most portions in Fig. 15) to obtain nodes assigned with levels not less than the level L. These nodes constitute a set (to be called a relative position determined set). Furthermore, according to the linking or connective relationships of the net list, a sum-set (to be called a relative position undetermined set) is produced between a set of the nodes outputting input arcs to the nodes of the relative position determined set and a set of the nodes at a level L-1. In other words, the system generates a bipartite graphs associated with the relative position determined and undetermined sets and the arc (connective) relationships therebetween. The graph is to be used in the subsequent step 144. In the step 144, a pair of nodes associated with each other is determined through the maximum matching effected on the bipartite graph obtained in the step 143 so as to allocate the nodes at the same relative position. The bipartite graph and the maximum matching thereof are described, for example, in "Excercise of Graph Theory: Fundamentals and Applications" written by Masao Iri and published from Corona Inc. in 1983. For example, when the processing step 144 is effected on an example of the bipartite graph of Fig. 17, a matching (correspondence) state occurs between the nodes A and b, B and d, and C and a as shown in Fig. 18, thereby establishing the maximum matching. In consequence, the same relative locations are assigned to the pairs of nodes A and b, B and d, and C and a. In consequence, the positional relationship information is obtained as shown in Fig. 19. In this connection, when a plurality of maximum matchings take place, a matching having the larger level difference between the nodes thereof takes precedence over the other matchings. For example, under the condition of Fig. 18, two kinds of maximum matching are found as the matching of the nodes A and b, B and d, and C and a and that of nodes A and b, B and d, and C and c. In this situation, if the level difference between the nodes C and a is greater than that between the node C and c, the maximum matching of the nodes A and b, B and d, and C and a is preferentially selected. As a result of determination of placements based on the maximum matching of bipartite graph as described above, the increase of links between nodes are established with linkes like direct lines (along the horizontal direction), which facilitates understanding of the connective relationships and signal flows in the diagram. Furthermore, in the processing 145, a relative position is determined for any node at the level L-1 for previous step 144. That is, each node at the level L-1 selected from the relative position undetermined set excluding the nodes assigned with the relative positions in the processing 144 is located at a position of a center of gravity with respect to each relative position of the relative position determined nodes having an arc relationship with said each node or at a position in the neighborhood of the center of gravity. For example, since the desired center of gravity of node c and position of node a are assigned with an identical relative position in the example of Fig. 18, the pertinent node c need only be positioned between the nodes d and a or below the node a. In this case, since the node c is placed below the node a, the positional relationship information becomes to be as shown in Fig. 20. In the processing 146, in order to achieve the similar processing on the nodes at the level L-1, the content of the level counter L is decremented by one. The judge processing 147 determines whether or not the level counter L contain a count 0. If this is the case, the processing step 148 is executed; otherwise, the processing steps 143 to 145 are repeatedly executed for the next level. Finally, the processing 148 determines for each node, based on the positional relationship information stored in the data structure of Fig. 15, a level and a coordinate of the node in the vertical direction. For example, in the case of Fig. 20, the coordinates 1, 2, 3, and 4 are assigned to the nodes A and b, B and d, C and a, and the node c, respectively. With the provision of the reference level position determination 12 and the relative placement at each level 13 in the embodiment according to the present invention, it is possible to create a logic circuit diagram which facilitates understanding of the overall connective relationships and which enhances visibility thereof. In consequence, the placement or placement need not be corrected after the placement is once achieved and hence the efficiency of the processing is increased. Fine Adjustment of Element Placement A description will be given in detail of the fine adjustment of element placement 14. In this processing, based on the positional relationships determined by the coordinates (namely, global coordinates) of the respective placement elements and the contour information stored in the contour information file 2, signals are allocated to pins of the placement elements (nodes) and precise positions of the elements are determined. However, for simplification, in this description, it is assumed that the respective placement elements of a logic circuit diagram are each located to face toward a direction from the left to the right (namely, the rotary angle is zero). First, a description will be given of a method of allocating signals to the pins. Fig. 21 is a diagram including an placement element 210 at the center thereof in which start point element positions of input signal lines to the element 210 are associated with seven subregions. Regions A and G have a global first coordinate (a coordinate in the horizontal direction in this example) of the element 210. Region D possesses a global second coordinate (a coordinate in the vertical direction in this example) of the element 210. When the area subdivision is achieved as shown in Fig. 21, routing patterns of the signal lines from the placement elements in the respective regions are forecasted as shown in Fig. 22. As can be easily recognized from the routing patterns of Fig. 22, in order to minimize routing intersections, a signal line of which the start point placement element is in the upper field in Fig. 22 is assigned to an upper input pin of the placement element 210 in this embodiment. That is, a signal line is assigned with a higher priority according to the region of the associated start placement element in the following order, namely, region A > region B, region B > region C, region C > region D, region D > region E, region E > region F, and region F > region G. According to this order with respect to the associated start point placement element, the pertinent signal line is allocated to an input pin of the element 210 at the upper position in Fig. 21. Incidentally, the pin placement is achieved only for a logically equivalent pin. Moreover, only the pin placement is conducted in this example; however, by combining a rotation and a mirror inversion of placement elements, it is possible to wire the elements with a reduced number of intersections. In addition, also in each region, the pin placement priority sequence may also be determined depending on routing patterns forecasted based on the positions of the start point placement elements. For example, the region D is related to the routing patterns as shown in Fig. 22, a signal line associated with a start point placement element with the larger value of the global first coordinate (a coordinate in the horizontal direction) need only be allocated to an input pin at the upper location of the placement element 210. Next, a description will be given of the operation to determine precise coordinates of the respective placement elements. Since input/output pin locations vary depending on the contour of each element to be allocated, when only the global coordinate is used for the determination, even if the global second coordinates of two elements are identical to each other, a routing route therebetween is not necessarily drawn as a direct line. To overcome this difficulty, according to this embodiment, a local second coordinate is determined for each placement element such that for the adjacent elements associated with the same global second coordinate, a position of an output pin of one of the adjacent placement elements and a position of an input pin of the other one thereof to be connected to the output pin are assigned with an identical second coordinate (a coordinate in the vertical direction), so that the routing therebetween becomes to be a direct line. For example, as shown in Fig. 23, if the placement of the elements are accomplished only based on the global coordinate, a positional discrepancy takes place between the input and output pins, which causes the routing therebetween to include a bending portion. To avoid this disadvantage, the local coordinates are set so as to prevent the positional difference from appearing between the input and output pins to allocate the elements with the local coordinates also taken into consideration, thereby producing a circuit diagram with a satisfactory visibility. By the way, although only the second coordinate has been described in this example, it is also possible to similarly set the local coordinate for the first coordinate so as to conduct a fine adjustment. Routing at Each Level A method of routing a network will be next described by referring to Fig. 24. Fig. 24 is a flowchart including steps 241 to 248 showing an example of the processing procedure of the routing at each level 15. First, in the step 241, the maximum level (the level of the output port) is assigned to the level counter L. Next, in the processing steps 242 to 246, routings are conducted for the regions at the level L (namely, the global first coordinate L). In this routing operation, the net list, position coordinates of the respective placement elements and pins thereof, and connective information of routings between the levels L+1 and L are referenced to produce coordinates of the start, bending, and end points of each routing and the connective information of routings between the levels L and L-1. In addition, when the L-level routing operation is completed, the processing step 247 decrements the level counter L by one. Then, the judge processing 248 judges to determine whether or not the content of the level counter L is 0. If L is not 0, control returns to the step 242 to repeatedly execute the routing steps 242 to 246 for the next level. If L is 0, the routing processing at each level 15 is thereby completed. Next, a description will be given in detail of the L-level routing processing steps 242 to 246. Fig. 25 is a net diagram showing routing types of regions at the respective levels. A routing 251 passes from a region at the level L+1 to a region at the level L-1. A routing 252 is a feedback routing from a region of the level L+1 to an placement element at the level L. A routing 253 is a feed-forward routing from an placement element at the L-1 level to a region at the level L+1. A routing 254 is a feed-forward routing to an placement element at the level L. A routing 255 is drawn from an placement element at the level L-1 to a region at the level L-1. In this embodiment, a routing order is determined for each routing type of Fig. 25 so as to determine the routing according to the routing order. More specifically, as shown in Fig. 24, in the transit routing processing 242, routings of the type indicated by the routing 251 are conducted. In the feedback routing processing to level L 243, routings of the type associated with the routing 252 are accomplished. In the feed-forward routing processing from level L-1 244, routings of the kind related to the routing 253 are carried out. In the feed-forward routing processing to level L 245, routings of the kind of the routing 254 are achieved. In the feedback routing operation 246 from level L-1 246, routings of the type associated with the routing 255 are conducted. In this routing sequence, a routing with the earlier routing sequence is achieved in the nearer position of an placement element at the level L. However, although it may be considered that the processing sequence of the routing steps 244 and 245 of this embodiment is reversed, for simplicity, a description of such a case will be omitted. In addition, the respective routing steps 242 to 246 conduct processing as shown in Fig. 26. Fig. 26 shows a flowchart including steps 261 to 263 showing an example of a detailed processing procedure of the routing processing 242 to 246. In the flowchart, the step 261 is disposed to compute a virtual routing length of each routing line based on a vertical component of length in the routing operation. In the processing 262, the routings are sorted according to the virtual routing lengths to determine a routing sequence. Furthermore, in the step 263, depending on the routing sequence, the routing is conducted from the side of routing elements at the level L without allowing any overlapping between the routings. By the way, in a region of the level L, for a routing which has not any bending portion, the steps 261 and 262 are skipped so as to preferentially achieve the routing. In this connection, according to this embodiment, for simplicity, the virtual routing length is in principle set to be equal to the vertical component of length in the routing operation. However, for the routing kinds of the routings 253 and 254, if the upper end of the vertical component of the routing is bent toward the level L-1, the upper end is assumed to have a sufficiently large coordinate (for example, the coordinate of the upper-most position of the diagram) so as to compute the virtual routing length. Conversely, if the lower end of the vertical component of the routing is bent toward the level L-1, the lower end is assumed to have a sufficiently small coordinate (for example, the coordinate of the lower-most position of the diagram) so as to compute the virtual routing length. For example, as shown in Fig. 27, the virtual routing length of the routings 271 to 273 are determined as ℓ a 274, ℓ b 275, and ℓ c 276, respectively. Furthermore, in this embodiment, the step 262 conducts the sorting operation in the ascending order in the routing steps 243 to 245 and in the descending order in the routing step 246. In the routing operation described above, for simplicity, the description has been given of a case where a routing with the earlier routing sequence is effected at the nearer placement element at the level L. The reverse case may also be easily inferred from the description. With provisions of the pin placement in the fine adjustment of element placement 14 and the routing processing at each level 15 according to the embodiment, it is possible to produce through a simple processing a logic circuit diagram raving a reduced number of routing intersections. In consequence, once the routing operation is completed, it is not necessary to correct the routing results, which improve the efficiency of the routing processing. According to the schematic generator to automatically produce a logic circuit diagram, it is possible to automatically generate a logic circuit diagram in which the feedback signal lines are reduced, the signal lines drawn like a direct line is increased, the number of bending portions and intersections of signal lines are respectively minimized, thereby improving the understandability of the logic functions. Furthermore, in the schematic generator, only one process of placement and routing is required, namely, neither the placement correction nor the routing correction is necessitated, which enables an efficient placement and routing processing to be achieved. In addition, since the contour information file keeps physical information related to the placement elements, there is developed an effect that any changes, for example, of the technology of the objective circuit may be easily coped with. As described above, the node level assignment can be conducted with a reduced number of feedback arcs and positional relationships of nodes at the reference level are appropriately determined. Based on the positional relationships, the nodes can be placed on corrective relationships, which can be easily traced. Moreover, taking the routing sequence and the virtual routing lengths into consideration, the number of routing intersections can be reduced. Consequently, there is obtained an advantageous effect that a net diagram or a logic circuit diagram is produced with an improved visibility of connective relationships and with an increased understandability of the content expressed in the diagram. In addition, physical information of the placement elements is kept in the contour information file so as to be separated from the placement processing, which leads to an excellent effect that the system can easily cope with changes in the utilization purpose of the net diagram and in characteristics and technologies of the objective circuit. While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made.

Claims: A node placement method for automatic placement of nodes in a graph based diagram representing a technical system, said diagram having levels assigned to its nodes, said method including a step (12) of determining positional relationships between a plurality of nodes in one level and not directly connected with each other in the diagram, said method characterized in that said step includes; a substep (101) of determining all possible node pairs among said plurality of nodes; a substep (102) of regarding arcs as parent child relationships, detecting one of a common ancestor node and a common descendant node for each of said node pairs, determining for each of said node pairs the level difference and the total number of arcs from the node pair's nodes to said common ancestor node or said common decendant node; a substep (104) of determining a priority sequence among said node pairs, said priority sequence comprising assigning a higher priority to each one of said node pairs which has a respective one of a smaller value of said total number of arcs or a smaller value of said level difference; and a substep (105) of determining the positional relationships between said plurality of nodes so that those of said node pairs that have higher priorities are located closer to each other.

Inventors: NISHIYAMA TAMOTSU, NISHIYAMA, TAMOTSU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1989
Main classification: G06F17
IPC codes: G06F17