Conductive pattern for electric test of semiconductor chips

Abstract: A conductive pattern for electric test of a semiconductor chip with which probes are in contact is disclosed. The pattern comprises a plurality of probing pads (7) for electric test and at least two unit continuity check patterns (11) provided within an area for determining alignment of the probes with said probing pads (7), and each of said unit continuity check patterns (11) comprises a plurality of conductive pads (2′, 3′,5′) and a conductive line connecting the pads (4).

Description: BACKGROUND OF THE INVENTION This invention relates to a semiconductor chip according to the preamble of claim 1 and to two semiconductor chips in a semiconductor arrangement according to the preamble of claim 2. In general, in the final stage of manufacturing semiconductor devices, various electric tests for determining pass/fail of semiconductor chips are performed by contacting the probes of a testing apparatus to probing pads provided in the periphery of a semiconductor chip formed on a wafer. Aligning the probes with the pads is performed by observing the relationship of their positions with a microscope disposed above the pads of the semiconductor chip. In the alignment, if an area having the probes is small, the magnification of the microscope for observation is increased to obtain the necessary accuracy of alignment. However, there is the tendency for the area having the probes (i.e. the alignment determination area) to become larger because of the increase in semiconductor chip sizes for semiconductor devices because of the realization of high performance and simultaneous probing for multiple chips. This tendency for the probing area to become larger results in the problem that the alignment of the probe with pads becomes difficult. This is because if the magnification of the microscope is increased, the entire probing area cannot be observed in the field of view of the microscope, and only partial observation is possible. On the other hand, if the magnification of the microscope is decreased in order to observe the entire probing area, it becomes difficult to obtain satisfactory accuracy for aligning the probes with the pads. Because of the alignment determining area becoming larger due to increase in chip sizes and multiple probing as described above, there arise problems of the high magnification of the microscope resulting in difficulty of performing alignment, and of low magnification of the microscope resulting in lowered accuracy of alignment. US-A-3 974 443 describes a method and apparatus for measuring or determining characteristics such as width and resistivity of a given conductive line, particularly a conductive line produced by integrated circuit technology. The conductive line, having a first width which is formed on an insulating medium is disposed in the vicinity of or adjacent to a second line having a second width different from the first width, which is also conductive and which is made by the same process by which the given conductive line was made. A common constant current is passed through the given conductive line and through the second line. A first voltage is measured between two points spaced apart by a given distance along the given conductive line and a second voltage is measured between two points spaced apart by the given distance along the second line. Characteristics, such as width and resistivity of the given conductive line as well as those of the second line are then determined by utilizing relationships between the measured voltages and known line constants. US-A-4 386 459 discloses a multiple-chip integrated circuit wafer including at least one chip for use as a test device for checking mask level-to-level misalignment during fabrication. This test chip includes a plurality of probing pads in one level and a conductive pattern in another level, the probing pads being electrically connected through windows to the conductive pattern. By contacting the probing pads with probes and electrically measuring the resistance of the conductive pattern portions between respective probing pads misalignment between the windows in one level and the conductive pattern in the other level can be determined and thereby the level-to-level registration in the circuit-containing chips be indicated. SUMMARY OF THE INVENTION Accordingly, the object of the invention is to provide a conductive pattern for electric test of a semiconductor chip which can achieve the high accuracy alignment of probes with probing pads even if microscope observation at low magnification is employed in order to cover a large alignment determination area. According to the present invention, there is provided a semiconductor chip according to claim 1 and two semiconductor chips in a semiconductor arrangement according to claim 2. By the use of the check pattern according to the present invention, since the alignment of a probe with a probing pad is conducted by detecting electrical continuity, a high accuracy of alignment is obtained even if a low magnification of a microscope is employed in order to enlarge the probing area. Furthermore, since the alignment of probes with pads is determined by direct contact of the probes with the pads, the alignment accuracy of the probes and pads can be improved. In this case, the accuracy of alignment will be further improved if the widths of the conductive pads are made narrower than the widths of the probing pads. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIG. 1 is a plan view of a unit continuity check pattern according to an embodiment of the present invention; FIG. 2 is a perspective view of a probe aligning method using the continuity check pattern according to the present invention; FIG. 3 is a plan view showing two continuity check patterns disposed in a semiconductor chip; FIGS. 4A to 4E are plan views showing variations of dispositions of the unit continuity check patterns; FIG. 5 is a plan view showing another embodiment of a unit continuity check pattern according to the present invention so as to be suitable for corners; FIGS. 6 and 7 are plan views showing embodiments in which the pad widths are made narrower than other probing pads; FIG. 8 is a plan view showing a further embodiment of a unit continuity check pattern according to the present invention, in which a probing pad is disposed between two pads of the check pattern; FIG. 9 is a plan view showing a further embodiment of a unit continuity check pattern connected to a probing pad; FIG. 10 is a plan view showing a further embodiment in which two unit continuity check patterns are disposed in two chips; and FIG. 11 is a plan view showing dislocation by rotation. DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiments of the invention will now be described with reference to the accompanying drawings. FIG. 1 is a plan view showing an embodiment of a unit continuity check pattern 1 according to the present invention. This pattern is configured by two conductive pads 2 and 3 and a straight connecting line 4 connecting the two pads 2 and 3. As shown in FIG. 2, probes 21 and 22 are placed in contact with the conductive pads 2 and 3 respectively, and the continuity between the probes 21 and 22 is checked by using a continuity checker (not shown). If continuity is observed, it is determined that the probes 21 and 22 and pads 2 and 3 are in correct contact, and it is assumed that if the probes 21 and 22 are in correct contact with the unit continuity check pattern 1, the probes 21 and 22 are in contact with the other probing pads provided in the periphery of a semiconductor chip. However, if the determination for alignment is conducted by one point within the alignment determination area, a misjudgement of alignment may occur when dislocation due to rotation is generated. That is, as shown in Fig. 11, when a unit check pattern 30a locates at the center of rotation, even if the alignment is determined as correct because continuity is observed at the continuity determination area, other probing pads may not be in contact with the probes. According to the present invention, correct alignment is achieved even if dislocation between probes and pads due to rotation occurs. For this purpose, as shown in FIG. 3, at least two unit check patterns 30a and 30b are provided in alignment determination area which is an area of a semiconductor chip. FIG. 4A to FIG. 4G are plan views showing embodiments of the present invention, in which a plurality of unit continuity check patterns are provided in the alignment determination area. FIG. 4A shows an embodiment in which two unit continuity check patterns 1-1 and 1-2 are provided on one side of a semiconductor chip 12, while FIG. 4B shows another embodiment of the present invention in which two unit continuity check patterns 1-3 and 1-4 are provided on the upper side and opposing bottom side of a semiconductor chip 12. FIG. 4C shows a further embodiment in which two unit continuity check patterns 1-3 and 1-5 are provided at two adjacent aides, FIG. 4D shows another embodiment in which three unit continuity check patterns 1-3, 1-4 and 1-5 are provided on three of the four sides of the chip 12 and FIG. 4E shows a further embodiment in which four unit continuity check patterns 1-3, 1-4, 1-5 and 1-6 are provided on four sides of the semiconductor chip 12. Thus, since a plurality of unit continuity check patterns 1 are disposed in an alignment determination area, if the correct alignment is not achieved due to the occurrence of rotation, continuity is not observed at at least one check pattern of the check patterns 1-1 to 1-6. Moreover, if continuity is not observed at at least one portion of a plurality of unit continuity check patterns, it is judged that probes and pads are not in correct alignment. Determination by using the continuity check pattern and actual alignment status of probes and probing pads will therefore be substantially the same and no erroneous judgement will occur. FIG. 5 shows another embodiment of a unit continuity check pattern which is suitable for corners of a semiconductor chip. This check pattern has a pad 5 below the pad 3 in addition to the configuration shown in FIG. 1. Rotation can be observed by one check pattern when this unit continuity check pattern is used. FIGS. 6 and 7 are embodiments of unit continuity check patterns according to the present invention, and correspond to the embodiments shown in FIG. 1 and FIG. 5, respectively. In these embodiments, since the widths of pads 2', 3' and 5' shown in FIGS. 6 and 7 are made narrower than the probing pad 7 which is actually probed, the alignment accuracy for other probing pads can be improved. It is not always necessary to connect adjacent pads 2 and 3 through connecting line 4. Therefore, another embodiment is possible as shown in FIG. 8, where an actual probing pad 9 is disposed between the continuity check pads 2 and 3 connected by a connecting line 8. In the above-mentioned embodiments, the unit check patterns are formed using pads which are not used for actual probing, but pads for actual probing can be used as continuity check pads. FIG. 9 shows such an embodiment in which a conductive pad 13 is connected to a pad 15 used for actual probing. In this embodiment, the fact that the pad 15 is connected to the pad 13 does not adversely affect the result of probing. Furthermore, though, in FIGS. 1, 6, 8 and 9, pads for continuity check are latitudinally elongated, they can be rotated 90 degrees and longitudinally elongated. Continuity check patterns shown in FIGS. 5 and 7 can be disposed by rotating 90 degrees or 180 degrees to locate them at every corner. It is to be noted that only one continuity check pattern is sufficient in the case where no rotation between probes and pads is ensured, for example, in the case where there has been previous calibration for the rotation between a fixture for probes and a fixing stage for a wafer on which semiconductor chips are formed. When a plurality of semiconductor chips are probed, a plurality of probing patterns need not necessarily be formed in a semiconductor chip. That is, when there is simultaneous probing for two semiconductor chips 23 and 24 having pads to be probed, the unit continuity check patterns 1 are disposed to both semiconductor chips 23 and 24. In this case, since two continuity check patterns are provided in the area having the probes, an appropriate alignment between the probes and the pads is achieved.

Claims: A semiconductor chip (12) comprising a conductive pattern and a plurality of probing pads (7; 9), said pads (7; 9) being contactable by probes (21, 22), for electric test of said semiconductor chip (12) characterized in that at least two unit continuity check patterns (1) are provided within an area of said chip (12) for determining alignment of said probes (21, 22) with said probing pads (7; 9); in that each of said unit continuity check patterns (1) comprises a plurality of conductive pads (2, 3) and one conductive line (4) connecting said conductive pads (2, 3); and in that the continuity is checked at each of said unit continuity check patterns (1) thus determining whether said plurality of conductive pads (2, 3) are contacted by said probes (21, 22), whereby correct relative alignment of said semiconductor chip (12; 23, 24) against said probes (21; 22) is determined. Two semiconductor chips (23, 24) in a semiconductor arrangement, each semiconductor chip (23, 24) comprising a conductive pattern and a plurality of probing pads (7; 9), said pads (7; 9) being contactable by probes (21, 22), for electric test of said semiconductor chips (23, 24) characterized in that one unit continuity check pattern (1) each is provided within an area of said chips (23, 24) for determining alignment of said probes (21, 22) with said probing pads (7; 9); in that each of said unit continuity check patterns (1) comprises a plurality of conductive pads (2, 3) and one conductive line (4) connecting said conductive pads (2, 3); and in that the continuity is checked at each of said unit continuity check patterns (1) thus determining whether said plurality of conductive pads (2, 3) are contacted by said probes (21, 22), whereby correct relative alignment of said semiconductor chips (23, 24) against said probes (21; 22) is determined. A semiconductor chip as set forth in claim 1 or 2, characterized in that one of said conductive pads (15) of said unit continuity check patterns (1) is provided in common to one of said probing pads (15). A semiconductor chip as set forth in claim 1, characterized in that one of said at least two unit continuity check patterns (1-1, 1-2) is disposed at one side of said semiconductor chip (12). A semiconductor chip as set forth in claim 1, characterized in that said unit continuity check patterns (1-3, 1-6) are disposed on at least two of four sides of said semiconductor chip (12). A semiconductor chip as set forth in claim 1, characterized in that one of said unit continuity check patterns (1) has a first conductive pad (3), a second conductive pad (5) disposed in a longitudinal direction and a third conductive pad (2) disposed in latitudinal direction, the first conductive pad (3) and the second conductive pad (5) being connected by a first conductive line (6) and the second conductive pad (5) and the third conductive pad (2) being connected by a second conductive line (4). A semiconductor chip as set forth in claim 1, characterized in that widths of said conductive pads (2', 3') are smaller than those of said probing pads (7). A semiconductor chip as set forth in claim 1, characterized in that at least one probing pad (9) is disposed between two conductive pads (2, 3).

Inventors: ISHIKAWA MICHIHIRO, ISHIKAWA, MICHIHIRO
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G01R31
IPC codes: H01L23, H01L21, G01R31, G01R1