Circuit for synchronizing transitions of bits in a digital code

Abstract: An electronic circuit contains a main stage (10 and 12) that produces a digital code consisting of a plurali­ ty of bits (B₀ - B M-1 ) that make binary transitions as a function of an input parameter (V I ). A synchronization stage (14 and 16) synchronizes transitions of bits (B₀ - B K-1 ) in one part of the code with corresponding transitions of bits (B K - B M-1 ) in another part. When the input parameter is in transition regions where bits in the first-mentioned part of the code could go to wrong values, the synchronization stage suitably replaces the values of bits in the first part with information based on bits in the other part.

Description: This invention relates to an electronic circuit comprising a main stage for producing a digital code formed with a plurality of binary bits that make transitions between a pair of binary values as a function of an input parameter, the transitions ideally occurring in accordance with a prescribed algorithm as the input parameter traverses an input range, the bits divided into a first set of at least one bit and a second set of at least one bit. In an analog-to-digital converter (ADC) of the folding type, the bits that form the digital output code are typically generated along two largely separate paths. A coarse conversion circuit produces a set of coarse (higher-order) bits directly in response to an analog input voltage. A fine conversion circuit produces a set of fine (lower-order) bits in response to one or more signals supplied from a circuit that folds the input voltage. See van de Grift et al, "A Monolithic 8-Bit Video A/D Converter", IEEE JSSC , June 1984, pp. 374-378. One difficulty with a folding ADC is that the bits in the coarse set sometime make transitions between binary "0" and binary "1" at values of the input voltage that are slightly different from those at which the bits in the fine set make corresponding transitions between "0" and "1". For example, consider a simple 4-bit "binary" code consisting of two bits supplied from the coarse converter and two bits supplied from the fine converter. Assume that the input voltage is in that portion of the input voltage range where the code is (0011). The left-most bit is the most significant bit (MSB). The right-most bit is the least significant bit (LSB). If the input voltage is increased by an amount equivalent to one LSB, the code should change to (0100). This is not always the case. Because the coarse bits are generated along a separate path from the fine bits, phenomena such as input offset errors, delay differences, and/or noise may cause the second most significant bit to switch from "0" to "1" either before or after the two fine bits switch from "1" to "0". The code changes to either (0111) or to (0000). The actual value produced by the code is nowhere near the intended (0100). A similar problem occurs with the MSB. The present invention is an electronic circuit that utilizes a bit synchronization scheme to overcome bit transition problems of the foregoing type. The starting point for the invention is a main stage that produces a digital code formed with a plurality of bits that make transitions between a pair of binary values as a function of an input parameter. The transitions ideally occur in accordance with a prescribed algorithm as the input parameter traverses a suitable input range. The bits are divided into first and second sets, each consisting of one or more bits. The bits in the second set are usually generated along a different electronic path through the main stage than those in the first. A synchronization stage synchronizes transitions of bits in the first set with corresponding transitions of bits in the second set. The basic approach is to define transition regions for bits in the first set. A transition region is basically that portion of the input range where phenomena of the type mentioned above can cause a bit in the first set to go to a wrong value. Using signals keyed to the transition regions, the values of bits in the first set are suitably replaced with information based on bits in the second. A single bit in the second set is preferably used in making every replacement in a transition region. No replacements are made outside the transition regions. In particular, the synchronization stage implements this scheme with a control circuit and a substitution circuit. The control circuit generates at least one synchronization signal. Each synchronization signal reaches a specified signal level when the input parameter is in a sub-range of the input range where a bit in the first set associated with that synchronization signal makes a single transition and where a corresponding bit in the second set makes a single transition. When each synchronization signal reaches its specified signal level, the substitution circuit replaces the value of each associated bit in the first set either with the value of the corresponding bit in the second set or with the value of the complement of the corresponding bit in the second set in such a way as to satisfy the prescribed algorithm. UK Patent Application GB-A-2 090 707 discloses a analogue-to-digital converter having a flash converter for providing a first set of coarse bits and a dual folding converter for providing a second set of fine bits. Transitions in the coarse bits are replaced with transitions from the fine bits in substitution means. The substitution means, however, are not responsive to synchronization signals indicating that the input parameter is in a sub-range of the input range where a bit in the first set of coarse bits associated with that synchronization signal makes a single transition and where a corresponding bit in the second set of fine bits also makes a single transition. The algorithm is typically a binary code in which each bit in the first set is a coarse bit and in which each bit in the second set is a fine bit. In this case, only the most significant fine bit is used in performing the replacements. The substitution circuit specifically replaces the value of each coarse bit either with the value of the complement of the most significant fine bit if that coarse bit is the most significant bit making a transition within the appropriate sub-range or with the value of the most significant fine bit if that coarse bit is not the most significant bit making a transition within the sub-range. The invention eliminates synchronization errors in an easy and dependable way. In folding ADCs, the synchronization can be achieved with a small amount of circuitry. Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which: Fig. 1 is a block diagram of an ADC employing a bit synchronization scheme in accordance with the invention; Figs. 2 and 3 are graphs indicating how the synchronization signals and bits vary as a function of input voltage for the ADC of Fig. 1; Fig. 4 is a block diagram of a folding-type embodiment of the ADC of Fig. 1; Fig. 5 is a circuit diagram of the input amplifier and summing arrays in the ADC of Fig. 4, Fig. 6 is a graph showing how the output voltage from a typical input amplifier in the amplifier array of Fig. 5 varies with input voltage and Fig. 7 is a circuit diagram of this amplifier; Fig. 8 is a graph showing how a typical folding voltage supplied from the interpolation circuit in the ADC of Fig. 4 varies with input voltage; Fig. 9 is a logic diagram for the bit substitution circuit in the ADC of Fig. 4. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. "N" is used as a subscript to indicate signals complementary to previously defined signals. Referring to the drawings, Fig. 1 illustrates an analog-to-digital converter containing a main stage that converts an analog input voltage V I into an M-bit digital code divided into a set of K first binary bits B O , B₁, ... B K-1 and a set of M-K second binary bits B K , B K+1 , ... B M-1 . K is typically two or more but may be as small as 1. The same applies to M-K. Bits B O - B M-1 make transitions between "0" and "1" as input voltage V I traverses an input range extending from a low voltage level V O to a high voltage level V F . The code is fixed at one value, usually "all Os", when input V I is at or below V O . The code is fixed at another value, usually "all 1s", when input V I is at or above V F . The binary transitions ideally occur in accordance with a prescribed algorithm. The main ADC stage consists of a first conversion circuit 10 and a second conversion circuit 12. Conversion circuit 10 generates bits B₀ - B K-1 along one general electronic path. Conversion circuit 12 similarly generates bits B K - B M-1 along another general electronic path. Slight, but significant, differences in signal transmission delay typically exist between the two paths. If not suitably accounted for, these delay differences can cause transitions in certain of bits B₀ - B M-1 to occur at wrong points. The same applies to noise. Small offset errors in the input circuitry of circuits 10 and 12 affect the values of input V I at which bits B₀ - B M-1 make their transitions. A bit synchronization stage operating according to the teachings of the invention synchronizes transitions of bits B₀ - B K-1 in the first-mentioned set with corresponding transitions of bits B K - B M-1 in the second-mentioned set so as to avoid code errors due to the preceding phenomena. The synchronization stage is formed with a synchronization control circuit 14 and a bit substitution circuit 16. Control circuit 14 generates one or more synchronization voltage signals V A that indicate when bits B₀ - B K-1 in the first set are near values of input V I at which these bits make transitions that are ideally intended to be simultaneous with transitions of bits B K - B M-1 in the second set. When one of the V A signals provides such an indication for one of the bits in the first set, substitution circuit 16 replaces the current value of that bit with information derived from the bits in the second set. Circuit 16 thus provides a set of K bits B₀′, B₁′, ... B K-1 ′ synchronized with the M-K bits in the second set. Except where a replacement is performed, each bit in the synchronized set is the same as the like-numbered bit in the original set. The specific operation of the synchronization stage is facilitated with the assistance of the graph shown in Fig. 2. Depending on the algorithm followed by the code, one or two situations exists for each value of input V I at which a bit in the first set makes a transition: (1) at least one bit in the second set ideally makes a simultaneous transition, or (2) no bit in the second set ideally makes a simultaneous transition. Starting with the last-mentioned situation, this case is represented by transition T of bit B₁ in Fig. 2. None of bits B K - B M-1 ideally make transitions simultaneous with transition T. Consequently, no bit synchronization problem exists here. Turning to the first-mentioned situation, a voltage transition region is defined around each value of input V I at which a bit in the first set makes a transition ideally intended to be simultaneous with the transition of a corresponding bit in the second set. The transition regions are sufficiently narrow that each bit within a transition region makes only a single transition between "0" and "1". However, the regions are sufficiently wide that the likelihood of a transition occurring outside the intended region is usually very small. Fig. 2 illustrates three transition regions X, Y and Z generally centered around respective transitions in bits B₀, B₁, and B K-1 . Bit B K-1 is also shown as making a transition within region Y. The transitions for the corresponding bits in the second set can be seen by inspection. Note that there are two possible corresponding bits in the second set for the B K-1 transition in region Z. Control circuit 14 supplies one V A synchronization signal for each transition region. Each synchronization signal is thereby associated with one or more particular bits in the first set. Each V A signal reaches a specified condition when input V I is in the transition region for the associated bit or bits in the first set. Fig. 2 depicts three such synchronization signals V AX , V AY , and V AZ respectively associated with transition regions X, Y, and Z. Each of signals V AX - V AZ is normally at a low voltage V L and goes to a high voltage V H when input V I enters the associated transition region. The boundaries of regions X - Z are set at points where the V A signals are approximately equal to (V L + V H )/2. That is, the specified V A condition mentioned in the previous paragraph occurs when each V A signal rises above a threshold voltage approximately equal to (V L + V H )/2. When a V A signal is at the specified condition, substitution circuit 16 replaces the value of each associated bit in the first set either (a) with the value of the corresponding bit in the second set or (b) with the value of the binary complement of the corresponding bit in the second set in such a way as to meet the prescribed algorithm. For example, circuit 16 uses the true value of the corresponding bit in a second set when the transitions of the two bits are in the same direction. The reverse applies when the transitions are in opposite directions. The dotted lines in Fig. 2 indicate the replaced bit values. In this way, the invention synchronizes transitions in bits B₀ - B K-1 with transitions in bits B K - B M-1 . Synchronization errors of lesser significance may exist among transitions of bits in the second set. The effect of these errors can be minimized by utilizing a single bit in the second set for performing all the replacements within a transition region. That is, circuit 16 performs each replacement in the region using either the true or complementary value of this bit. Depending on the algorithm prescribed for bits B₀ - B M-1 , one bit in the second set may be used in performing all the replacements in all the transition regions. The prescribed algorithm is preferably a binary code in which bits B₀ - B M-1 decrease progressively in significance as the bit number increases. Bits B₀ - B K-1 are thereby the coarse bits. Bits B K - B M-1 are the fine bits. Fig. 3 illustrates how a binary code varies as a function of input V I for the case where both K and M-K are equal to 2. To obtain the greatest synchronization accuracy in the binary-code situation, substitution circuit 16 only uses the most significant fine bit B K for replacement purposes. This is bit B₂ in Fig. 3. More specifically, circuit 16 employs the following replacement procedure in each transition region. The value of the complement of the most significant fine bit is substituted for the value of each coarse bit if it is the most significant bit making a transition within that region. The true value of the most significant fine bit is substituted for the value of each other coarse bit that makes a transition within that region. The replacement algorithm can be expressed as: where the subscript j is an integer from 0 to K-1, p is an integer equal in value to the subscript of the most significant coarse bit B p making a transition within the transition region, and B NK is the complement of B K . The transition regions have largely the same width. As indicated in Fig. 3, the width is preferably equal to one half of the average spacing between consecutive transitions of the least significant coarse bit B K-1 . In addition, the number of transition regions is equal to the number of transitions made by bit B K-1 . The invention is particularly useful in ADCs of the folding type. Turning to Fig. 4, it depicts an application of the invention to a multiple-folding ADC that generates an 8-bit binary code consisting of two coarse bits supplied along one analog path and six fine bits supplied along another analog path. Coarse conversion circuit 10 of Fig. 1 is implemented with an input amplifier array 18, a summing array 20, and a group of coarse comparators 22. Fine conversion circuit 12 of Fig. 1 is formed with arrays 18 and 20, an interpolation circuit 24, a group of fine comparators 26, and an encoder 28. The V A synchronization signals consist of part of the amplifier signals normally supplied from amplifier array 18. No additional circuitry beyond that already present in array 18 is needed to implement control circuit 14 of Fig. 1. This provides a particularly efficient arrangement. Fig. 5 shows details of arrays 18 and 20. Amplifier array 18 contains 64 input amplifiers A₀ - A₆₃ arranged in 8 rows by 8 columns. Letting i be a running integer, each amplifier A i amplifies the difference between input voltage V I and a corresponding reference voltage V Ri to produce an intermediate voltage V Ai . Reference voltages V RO , V R1 ... V R63 are supplied from a resistive divider at equally spaced intervals across the input range from V RO to V R63 . Fig. 6 illustrates the general shape for typical voltage V Ai as a function of V I . V Ai would ideally have the triangular shape shown in dashed line. Due to practical amplifier characteristics, V Ai actually has the more rounded shape indicated in solid line. Each voltage V Ai exceeds threshold voltage (V L + V H )/2 when V I is between V Ri-8 and V Ri . The internal configuration for typical amplifier A i is depicted in Fig. 7. The collectors of emitter-coupled NPN transistors Q Li and Q Ri are respectively connected to the collectors of transistors Q Ri-8 and Q Li+8 in amplifiers A i-8 and A i+8 . Amplifier A i operates in a differential manner in conjunction with amplifier A i-8 . When V I equals V Ri , the differential pair Q Li and Q Ri is balanced so that V Ai has a zero crossing. The differential pair Q Li-8 and Q Ri-8 in amplifier A i-8 is similarly balanced when V I equals V Ri-8 . Due to the collector cross coupling, V Ai has another zero crossing at that point. The result is that V Ai reaches V H when V I equals V Ri-4 and is constant at V L when V I is less than V Ri-12 or greater than R Ri+4 . Summing array 20 is subdivided into a folding array 30 and a coarse summing section 32 as indicated back in Fig. 5. Folding array 30 electrically combines every sixteenth intermediate signal V Ai to produce eight pairs of complementary folded voltages V B . Summing section 32 electrically combines certain of the V Ai signals to generate two pairs of complementary voltages V C . The circles in Fig. 5 represent the particular couplings to the A i amplifiers. Returning to Fig. 4, coarse comparator group 22 consists of two master-slave flip-flops that generate coarse bits B₀ and B₁ by comparing the two true V C voltages with their respective complements. Interpolation circuit 24 interpolates by a factor of four between consecutive V B voltages to produce 32 pairs of complementary folded voltages V D . Circuit 24 is preferably embodied in the manner disclosed in EP-A-0 319 097. Fig. 8 depicts a typical one of voltages V D as a function of V I . Fine comparator group 26 consists of a flip-flop ladder that compares the 32 true V D voltages with their respective complements to generate a string of 32 bits B in a circular code. The bit signals supplied from the ladder include the most significant fine bit B₂ and its complement B N2 as indicated in Fig. 4. The ladder is preferably implemented in the manner described in EP-A-0 328 215, entitled "Error Correction Circuit Suitable for Thermometer or Circular Code". Encoder 28 converts bit string B into fine bits B₃ - B₇. Encoder 28 is formed with suitable input logic and an appropriately programmed read-only memory. The additional digital processing used to generate bits B₃ - B₇ beyond that experienced by bit B₂ usually does not in itself introduce any significant synchronization problems among the fine bits. Fig. 9 shows a functional equivalent of a preferred embodiment for the internal circuitry of substitution circuit 16. This functional equivalent consists of a complementary-output buffer 34, an OR/NOR gate 36, AND gates 38, 40, 42, 44, and 46, and OR gates 48 and 50 interconnected in the indicated way. Gates 34 - 50 operate according to conventional combinatorial principles. Gates 38 - 50 are preferably implemented in current-mode logic (CMJ) using one CML gate for gates 38, 40, and 48 and another CML gate for gates 42 - 46 and 50. Synchronization signals V A supplied to substitution circuit 16 in Fig. 9 consist of amplifier voltages V A19 , V A35 , and V A51 provided from input amplifier array 18 in Fig. 4. Although the ADC in Fig. 4 generates an 8-bit binary code, only coarse bits B₀ and B₁ and fine bit B₂ are specifically involved in the synchronization scheme. The same applies to the 4-bit binary code represented in Fig. 3. Consequently, the three synchronization signals that respectively identify when input V I is in the low, middle, and high transition regions shown in Fig. 3 are roughly equivalent to signals V A19 , V A35 , and V A51 . The specific operations performed by circuit 16 in Fig. 4 consist of (a) replacing the value of bits B₀ and B₁ respectively with the values of bits B N2 and B₂ if V A35 is greater than (V L + V H )/2 and (b) replacing the value of bit B₁ with the value of bit B N2 if V A19 or V A51 is greater than (V L + V H )/2. A noteworthy feature of this substitution is that the value of bit B₁ is replaced with the value of bit B N2 when V I is in either the low or high transition region shown in Fig. 3. Consequently, a logical OR combinatorial operation can be performed on voltages V A19 and V A35 as indicated by OR/NOR gate 36 in Fig. 9. More generally, circuit 16 can use a gate that generates the logical OR or each group of synchronization signals for which the same replacements are performed. While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, the definitions of binary "0" and "1" are arbitrary and could be reversed from what is described above. Where the same replacements are made in a group of transition regions, a single synchronization signal could be initially defined instead of a group of synchronization signals combined by a logical OR operation. The algorithm for the bits could consist of two or more sub-algorithms such as a binary code for the bits in the first set and a Gray code for the bits in the second set. Multiple applications of the invention can be made if there are three or more generally different sets of bits. Various modifications and applications may thus be made by those skilled in the art without departing from the true scope of the invention as defined in the appended claims.

Claims: An electronic circuit comprising a main stage (10, 12) for producing a digital code formed with a plurality of binary bits (B₀..B M-1 ) that make transitions between a pair of binary values as a function of an input parameter (V I ), the transitions ideally occurring in accordance with a prescribed algorithm as the input parameter (V I ) traverses an input range (V₀-V F ), the bits being divided into a first set (B₀..B K-1 ) of at least one bit and a second set (B K ..B M-1 ) of at least one bit, characterized by a synchronization stage (14, 16) comprising: control means (14) responsive to the input parameter (V I ) for generating at least one synchronization signal (V A ), each synchronization signal having a specified signal level indicating that the input parameter (V I ) is in a sub-range of the input range (V₀-V F ) where a bit in the first set (B₀..B K-1 ) associated with that synchronization signal makes a single transition and where a corresponding bit in the second set (B K ..B M-1 ) also makes a single transition; and substitution means (16) responsive to each synchronization signal (V A ) when it has the specified signal level for replacing the value of each associated bit in the first set (B₀..B K-1 ) either with the value of the corresponding bit in the second set (B K ..B M-1 ) or with the value of the binary complement of the corresponding bit in the second set (B K ..B M-1 ) in such a manner as to satisfy the prescribed algorithm. A circuit as claimed in claim 1, characterized in that the substitution means (16) performs every replacement in a subrange using either the value of a single one of the bits in the second set (B K ..B M-1 ) or the value of the binary complement of that single bit. A circuit as claimed in claim 1, characterized in that there are first (10) and second (12) bit generation paths through the main stage (10, 12), each bit in the first set (B₀..B K-1 ) being generated along the first path (10), each bit in the second set (B K ..B M-1 ) being generated along the second path (12) and in that the specified signal level for each synchronization signal (V A ) consists of it being greater than or being less than a threshold voltage. A circuit as claimed in claim 3, characterized in that there is only one subrange for each synchronization signal (V A ). A circuit as claimed in claim 3 wherein there are at least two bits in each set, characterized in that the substitution means (16) performs every replacement in a subrange using either the value of a single one of the bits in the second set (B K ..B M-1 ) or the value of the binary complement of that single bit. A circuit as claimed in claim 1, characterized in that: the main stage comprises means (18) responsive to the input parameter (V I ) for producing a plurality of intermediate signals (V A0 -V A63 ) that vary between first (V L ) and second (V H ) levels as the input parameter (V I ) traverses the input range (V R0 -V R63 ), each intermediate signal (V A0 -V A63 ) being at the first level (V L ) for most of the traverse of the input parameter (V I ) across the input range (V R0 -V R63 ) and reaching the second level (V H ) at a different value (V Ri-4 ) of the input parameter (V I ) than each other intermediate signal, and means (20, 24, 26, 28) responsive to the intermediate signals (V A0 -V A63 ) for generating each bit in the second set (B₂..B₇); and the synchronisation stage comprises part (18, 16) of the main stage, each synchronization signal (V A19 , V A35 , V A51 ) being one of the intermediate signals (V A0 -V A63 ).

Inventors: BALTUS PETER GERARDUS, VAN DE PLASSCHE RUDY JOHAN, BALTUS, PETER GERARDUS, VAN DE PLASSCHE, RUDY JOHAN
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1989
Main classification: H03M1
IPC codes: H03M1