Filter circuit

Abstract: A filter circuit uses a reversible counter (31) to eliminate noise from an input signal (5) which changes between high and low levels. The input signal (5) is sampled in response to a clock signal (7) of selected frequency and the reversible counter is incremented by a sampled value at the high level and decremented by a sampled value at a low level. A hysteresis is built into the counting sequence by jumping the count by a predetermined value when the count is incremented over a first threshold value or decremented below a second threshold value.

Description: The present invention relates to a filter circuit, and more particularly to a filter circuit of the kind referred to in the preamble portion of patent claim 1. Such a filter circuit is known from US-A-4 667 338. A control system for a programmable controller and the like receives a state signal indicative of the state or condition of a controlled device or system and then processes such signal to generate and output a required control signal. In this case, the state signal, i.e. an input signal of the control system, typically includes a significant amount of noise, and hence, the noise must be removed from the state signal and then the waveform of such state signal must be shaped, so as to produce the state signal with accuracy and with a timing which permits accurate processing thereof. The present invention relates to a filter circuit for performing the above-mentioned operations. One of the examples of a conventional filter circuit is shown in Fig. 1, and the operating waveforms thereof are shown in Fig. 2. In Fig, 1, a programmable controller 10 receives a state signal S from an external device 9, which may be the controlled device or system. This state signal is subjected to level conversion in a circuit 11, which also provides isolation, so that the state signal S is converted into a signal 5, as shown in Fig. 2, and this signal 5 is then supplied to a capacitance-resistance (CR) filter 12. In the CR filter 12, the signal 5 is integrated by a capacitor-resister circuit so that the noise will be removed therefrom. The CR filter 12 outputs the integrated signal as a filter output signal 15, the waveform of which is shaped by a receiver 13 having a hysteresis characteristic. As a result, as seen in Fig. 2, the shaped signal has delays 17 and 18, respectively, at the rising and falling portions thereof. In the conventional circuit shown in Fig. 1, the following inherent problems exist. First, the "L" potential level at the input of the receiver 13 tends to be increased because of the voltage drop across the resister in the filter circuit 12, with the undesirable possibility that the "1" signal will be misjudged as a "H" signal in the receiver 13. Also, since the charging and discharging waveforms of the capacitor are not uniform, and due to variation of the threshold value of the receiver 13, which depends on the temperature, variation of the delay times 17 and 18 are necessarily large. In addition, the hysteresis characteristic depends on the threshold voltage of the receiver input, so that it is impossible to enlarge the hysteresis width of the receiver 13. Lastly, the capacitor in the filter circuit 12 is not suitable for circuit integration. Fig. 3 shows an example of a conventional digital filter circuit, which is disclosed in Japanese Patent Laid-Open Publication No. 61-109317; and, Fig. 4 is a time chart showing the operation of this conventional circuit. A digital filter 1 receives a filter input signal 5, which is sampled at the D input of a shift register 30 driven by a sampling clock 7. If four successive signal samples of the filter input signal 5 are at the "H" level, so that all outputs Q₁ to Q₄ of the shift register 30 are at the "H" level, an output set signal 28 of level "L" is produced by a NAND gate 311, so that a flip-flop 301 is set. On the other hand, if four successive signal samples of the filter input signal 5 are at the "L" level, so that all outputs Q₁ to Q₄ are at the level "L", an output reset signal 29 of level "L" is produced by gate 32, so that the flip-flop 301 is reset. The output of this flip-flop 301 is taken out as a filter output signal 6. In the conventional circuit shown in Fig. 3, if the noise 22, as shown in Fig. 4, is inputted before the output signal 6 is changed over, the output signal 6 may not be set until the sampling data representing the noise sample is shifted out of the shift register 30. In this case, there is a disadvantage in that the turn-on time 17 necessarily becomes large. A similar problem occurs with respect to the turn-off time 18. Hence, these delay times are undesirably affected by the noise. In addition, no consideration is given in this conventional circuit to the possibility of variable setting of the noise removal and delay time characteristic of the filter circuit, which affects the overall speed of operation of the filter circuit. Meanwhile, Japanese Patent Laid-Open Publication No. 56-114002 discloses a filter circuit which is capable of setting a variable delay time. The noise removal characteristic and delay time can be varied in this conventional circuit by varying the capacitor storage time of a capacitor-resistor filter, and so, the foregoing disadvantages relating to the filter circuit of Fig. 1 are also present in this conventional circuit. US-A-4 667 338 discloses a filter circuit comprising clock signal generating means for generating a sampling clock signal, means for two-level sampling of an input signal, a reversible counter for performing a count-up operation when a sampled value of said input signal is at the high level and a count-down operation when a sampled value of said input signal is at the low level, first control means coupled to said reversible counter for detecting a first threshold value of a count by said reversible counter, second control means coupled to said reversible counter for detecting a second threshold value of a count by said reversible counter, means for providing a filter circuit output. It is an object of the present invention to provide a stable filter circuit from which a satisfactorily shaped waveform can be obtained. It is a further object of the present invention to provide a stable filter circuit which is suitable for circuit integration and whose time constant is variable. These objects are accomplished with a filter circuit as claimed in claim 1. Dependent claims are directed on features of preferred embodiments of the invention. In other words: The above-mentioned objects can be achieved by providing a reversible counter which counts up or down in response to the "H" or "L" level of the input signal and which skips to an advanced count value when the count value becomes larger than a threshold value to provide an inherent hysteresis characteristic. In addition, the above objects can be achieved by operating a sampling clock generating circuit to generate plural clock signals each having a different frequency, and by selecting one of the plural clock signals having a frequency according to a value set by a time constant setting circuit so that the selected clock signal is set as the clock signal of the above-mentioned reversible counter. For this reason, it is possible to obtain a filter characteristic which operates to remove sharp pulses and the like. Further, this reversible counter skips to an advanced count value at the time when the count value becomes larger than the threshold value, so that the count value does not revert to the count value representing the threshold value immediately, even when a noise signal of opposite polarity is inputted thereto. Hence, it is possible to obtain a stable and satisfactory hysteresis characteristic. In addition, the sampling clock generating circuit generates plural clock signals, one of which is selected and then supplied to the reversible counter. Therefore, it is possible to control the counting operation of the reversible counter and also control the time constant of the filter operation. Moreover, it is easy to stabilize this clock signal, so that any variation of the time constant can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 and 2 respectively show a block diagram and time chart indicative of the operation of the input portion of a programmable controller which uses a conventional CR filter; Figs. 3 and 4 respectively show a circuit diagram and time chart indicative of the operation of a conventional digital filter using a shift register; Fig. 5 is a block diagram of one embodiment of the present invention using a reversible counter; Fig. 6 is a time chart showing the operation of the circuit shown in Fig. 5; Figs. 7(a) through 7(c) show several state transition diagrams of the reversible counter shown in Fig. 5; Figs. 8 and 9 respectively show one specific state transition diagram and an embodiment of a digital filter for realizing such a state transition; Fig. 10 is a block diagram showing another embodiment of the digital filter according to the present invention using a presetable up/down counter; Figs. 11 and 12 respectively show a specific example and a time chart indicating the operation of the digital filter shown in Fig. 10; Fig. 13 is a state transition diagram which is obtained by arbitrarily assigning other count values to the states in the state transition diagram shown in Fig. 8; Fig. 14 is a circuit diagram of a filter circuit which operates according to the state transition diagram of Fig. 13; Fig. 15 is a block diagram of programmable controller to which the present invention may be applied; and Fig. 16 is a circuit diagram showing one example of the portion which supplies respective clock signals to plural digital filters according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to various preferred embodiments. Fig. 5 is a block diagram showing a basic configuration of the filter circuit according to the present invention. In Fig. 5, a digital filter 1, constituted by an up/down counter, receives a filter input signal 5, which typically includes noise and chattering components therein. The digital filter 1 performs count-up or countdown operations in response to the "H" or "L" level of the filter input signal 5 every time the sampling clock signal 7 is inputted thereto. As a result, the digital filter 1 outputs a filter output signal 6 from which the noise is removed. One clock signal identified by the time constant (or delay time) setting circuit 3 is selected from plural clock signals of different frequency, which are obtained by dividing a basic clock input signal 42 in a clock signal generating circuit 2 by a sampling clock selecting circuit 4, so that such selected clock signal is set as the sampling clock signal 7 supplied to the digital filter 1. Next, the operation of the filter circuit of Fig. 5 will be described by use of the time chart shown in Fig. 6. The filter input waveform 5, including the highest degree of noise and chattering etc., is sampled by the sampling clock signal 7, and a count value is incremented when the sampled filter input waveform has the "H" level (as shown by hollow circles), while the count value is decremented when the sampled filter input waveform is at the "L" level (as shown by black circles). In accordance with the present invention, the counting operation is controlled according to the following rules. When the count value is incremented over three, the filter output signal 6 is set to have the "H" level and the count is advanced to seven. When the count value is decremented below four, the filter output signal 6 is set to have the "L" level and the count is jumped to zero. By using an up/down counter in this way, the counter value is changed from zero to one, but is not incremented over three unless the proper succession of positive pulses is detected. Even if a positive pulse (or noise) 24 shown in Fig. 6 is inputted to the digital filter 1 during a sequence of negative pulses, the filter output signal 6 is not effected by this positive pulse 24, so that the noise can be removed from the filter input signal 5. Similarly, in the case where negative pulses 22, 23 and 24 etc. are inputted to the digital filter 1 during a succession of positive pulses, the count value is decremented by one for each of these unwanted pulses, but the counting is continued after each unwanted pulse, so that it is possible to remove the effects of these negative pulses from the filter output signal 6. The pulse removal ability of the filter in accordance with the invention can be expressed by the following equation. For this reason, it is possible to obtain the ideal low-pass filtering characteristic which can remove all pulses having a pulse width satisfying this equation. (Removable Maximum Pulse Width) = (Sampling Clock Period: Ts) x (Count Distance to Threshold Value) In the present embodiment, it is possible to certainly remove the noise whose pulse width is under 4Ts. In addition, since the count distance to the threshold value is determined when the circuit is designed, on the basis of the above-mention rules for example, the filtering characteristic obtained by the present embodiment will be identified as a function whose value depends on the sampling clock period Ts only. Therefore, in the case where the basic clock signal is generated by use of a crystal oscillator etc., there is an advantage in that it is possible to obtain a stable filtering characteristic having a high accuracy. Further, it is the characteristic of the present invention that a satisfactory hysteresis characteristic is obtained by setting the counting operation so that it is discontinuous when the count value is incremented over the threshold value. Hereinafter, an example will be given with reference to Fig. 6 similar to the above description. When the count value is incremented over three, the next count value is not set to four, but is set to seven as shown by time slot 19, Thus, even if the negative pulse 43 is inputted to the digital filter 1 just after the level of the filter output waveform 6 changes to the "H" level, the count value is decremented to six, for example. In this case, there is a gap between the count value of six and the threshold value of four, so that it is possible to prevent the level of the filter output signal from being inverted to the "L" level again by a single pulse of opposite polarity. Similarly, when the count value is decremented below the threshold value, the next count value is not decremented to three, but is set to Zero, as shown by time slot 20, so that it is possible to prevent the filter output waveform from being inverted to the positive or "H" level again by a single positive pulse 24. Therefore, no chattering is produced in the filter output waveform 6 as a result of this built-in hysteresis. In the present embodiment, the hysteresis width is set to 4Ts (Ts: sampling clock period). However, this hysteresis width can be freely varied from 2Ts to 4Ts by varying the count distance to be jumped when the count value is incremented over the threshold value. This is shown in Figs. 7(a) through 7(c). Figs. 7(a) through 7(c) show state transition diagrams indicating the relation between the counting operation of a reversible counter of three bits and the hysteresis width. In the case where a binary up/down counter is used as the reversible counter, the suffix number "S" directly corresponds to the count value of the up/down counter in each state. The value of the filter output signal Y equals "1" when the count value is over "4", while such value of the filter output signal Y equals "0" when the count value is below "3". In short, the value of the filter output signal Y equals the value of most significant bit (MSB) of the counter. The transition condition depends on the filter input signal at each sampling timing. In Fig. 7, "X" refers to "H" samples, while " X " refers to "L" samples. The jump count distance 4, as described in Fig. 6, corresponds to the diagram shown in Fig. 7(a), which is an example for setting the hysteresis width to the maximum. Fig. 7(b) illustrates a jump count distance of 3, while Fig. 7(c) shows a jump count distance of 2. The hysteresis width set as described above depends on N times the sampling clock period, where N is an integer. Hence, there is an advantage in that the present filter is hardly subjected to the effects of temperature variation, which is such a disadvantage in the use of the CR filter. Fig. 8 is a state transition diagram which is obtained by adding a reset operation to the state transition diagram shown in Fig. 7(a) reset operation responsive to an applied reset signal 8, as shown in Fig. 5 The value in parenthesis in each state indicates the count value of the up/down counter. Fig. 9 is a circuit diagram showing an example of a digital filter which is constituted by a master-slave JK flip-flop and which operates according to the state transition diagram of Fig. 8. A JK flip-flop 25 designates the least significant bit of an up/down counter, while a JK flip-flop 26 designates a middle bit and a JK flip-flop 27 designates the most significant bit (MSB) thereof. The reset operation is executed by setting the J input of each flip-flop to the "L" level, and also by setting the K input of each flip-flop to the "H" level. In addition, the counting operation is executed by respectively controlling the J and K inputs of each flip-flop at every sampling clock timing based on the output state of each flip-flop and the state of the input signal 5. In this embodiment, the number of gates is small; hence, this embodiment is not only effective in removing the chattering and noise from applied input signals, but is easy to fabricate. Fig. 10 shows another embodiment of the digital filter which is constituted so as to directly control the variation of each bit based on a state transition diagram. The digital filter 1 shown in Fig. 5 also can be constituted as shown in the block diagram of Fig. 10. The filter input signal 5 is inputted to the presetable reversible up/down counter 31 to thereby initiate by its logic level a count-up operation mode or a countdown operation mode. The sampling clock signal 7 starts the counting operation, and the output signal of the reversible counter 31 is monitored by threshold value detecting circuits 44 and 45. When the value of this output signal reaches the preset threshold value, the threshold value detecting circuits 44 and 45 output threshold detecting signals 62 and 63 . Based on these threshold detecting signals 62 and 63 , a preset command generating circuit 46 generates a preset command 34 and a preset data generating circuit 47 generates preset data 35. The preset command 34 and the preset data 35 are supplied to the reversible up/down counter 31. By use of these circuits 44 to 47, the count value is forcibly preset to the proper value depending on the current output of the reversible counter 31, so that the counting operation is executed discontinuously. Hence, it is possible to obtain a satisfactory hysteresis characteristic. Fig. 11 shows a more specific example of the embodiment shown in Fig. 10. In this embodiment, a synchronous binary reversible up/down counter 31 of four bits is used as the up/down counter so as to provide an operation involving sixteen states, in which the threshold is eight rather than four. In contrast to the circuit shown in Fig. 9, this circuit shown in Fig. 11 uses an ordinary up/down counter. Therefore, in the case where a general-purpose logical IC is used for realizing this embodiment, it can be said that this embodiment provides an advantage because of the small number of elements required. Fig. 12 shows a time chart of the operation of the embodiment of Fig. 11. In the case where the level of filter input signal 5 is the "H" level when the count value of counter 31 is seven (Q a =1, Q b =1, Q c =1 and Q d =0), the turn-on threshold value detecting signal 62 takes the "L" level, so that the level of the filter output signal 6 becomes "H" at the input timing of the sampling clock, i.e. as the reversible counter 31 increments. Similarly, in the case where the level of the filter input signal 5 is the "L" level when the count value is eight (Q a =0, Q b =0, Q c =0 and Q d =1), the turn-off threshold value detecting signal 63 takes the logic "L" level so that the level of the filter output signal 6 becomes "L" at the input timing of the sampling clock, i.e. as the reversible counter 31 decrements. It is possible to perform the reset operation by forcibly presetting the counter to zero by means of the reset signal 8. In the case where there is a reset input to the reversible up/down counter 31, as shown by dotted line in Fig. 12, it is possible to perform the reset operation by directly supplying this reset input to the counter. However, in the example of Fig. 11, the output data signal 35 of the preset data generating circuit 47 is set to indicate zero or fifteen depending on the current state of the reversible counter 31. Instead, it is possible to output other values from the preset data generating circuit 47 so that the hysteresis width will become small. For example, the hysteresis width can be reduced from 8Ts to 7Ts by presetting the circuit 47 to produce one and fourteen. In the above-mentioned embodiment, the digital filter is constituted by use of a binary up/down counter. However, the counter to be used in accordance with the present invention is not necessarily limited to a binary up/down counter. The present invention basically uses a reversible counter and provides hysteresis to the state transition at the time the count value is incremented or decremented past a threshold value. Thus, by use of a counter in this way, it is possible to provide a digital filter having a satisfactory hysteresis. Figs. 7(a) through 7(c) described previously are state transition diagrams for a digital filter using a binary up/down counter in the case of eight states, in accordance with the present invention, and Fig. 7(a) shows the largest pulse removal ability and hysteresis width. Similarly, it is possible to produce a state transition diagram having 2 N states at maximum by using N flip-flops in general. In this case, the output is subjected to the states shown in the state transition diagram having the hysteresis as shown in Fig. 7(a), but without the use of a binary counter. Thus, it is possible to constitute a digital filter having a pulse removal ability and hysteresis width of ₂N-1.Ts simply using flip-flops and logic elements. Fig. 13 shows an embodiment based on this concept. In Fig. 13, the value in parentheses in each state indicates one example of an assigned count value corresponding to each state, and an important feature of this invention is that this assignment can be arbitrarily performed. This embodiment shows an example of an assignment according to the characters of m bits in the case where only one bit number must be varied in the transition between the adjacent states. In this regard, a comparison of Figs. 8 and 13 will show that the count values for the states S₂, S₃, S₆ and S₇ are different in the respective diagrams. Fig. 14 shows one of a filter circuit in accordance with the state transition diagram of Fig. 13. In Fig. 14, a D flip-flop 48 designates the least significant bit (LSB), a D flip-flop 49 designates a middle bit, while a D flip-flop 50 designates the most significant bit (MSB). The reset operation is executed by supplying a clear input to the D flip-flop of each bit. The reversible counting operation is executed by controlling the D inputs of the D flip-flops 48 to 50 based on the filter input signal 5 and the output state of each flip-flop. As described above, the reversible counter counts its count value by m bits. Hence, control logic of the input of each bit in the flip-flop can be simplified, and a small number of gates is needed.. For this reason, the present embodiment is advantageous for large scale circuit integration (LSI) of a gate array and the like in the case where a significant number of input signals are processed by the filter. While the description heretofore has focused on the constitution of the digital filter 1, other features of the filter circuit of the present invention as illustrated in Fig. 5 are worthy of note. For example, the sampling clock generating circuit 2 generates plural sampling clocks each having a different frequency, as mentioned above, and one of these sampling clock signals is selected by the sampling clock selecting circuit 4 in accordance with the value set by the time constant setting circuit 3. Thus, it is possible to vary the period of the sampling clock signal supplied to the digital filter 1, and it is also possible to vary the time constants corresponding to the maximum removal pulse width and input/output delay time. For example, in the time chart shown in Fig. 4, the turn-on delay time 17 is determined by when the output level changes to the "H" level by counting how many times the sampled input level is at the "H" level. Therefore, when the "H" levels are continuously sampled, the delay time becomes equal to 3Ts to 4Ts. On the other hand, when the "L" level is sampled only one time during a positive sequence, as shown by the pulse 22 in Fig. 6, the delay time becomes equal to 5Ts to 6Ts. On the other hand, one-time sampling of the "L" level greatly enlarges the delay time from 3Ts to 7Ts and 8Ts in the conventional filter circuit shown in Fig. 3. Compared to the conventional filter circuit, it is possible to obtain a stable operation in an advantageous way in accordance with the present invention. Similar advantages relate to the turn-off time 18. In general, the maximum delay time can be expressed by (Maximum Delay Time) = (Transition Distance to Threshold Value) x (Sampling Period: Ts) (1) in case where the digital filter is not effected by chattering. As described before, the maximum removable pulse width can be expressed by (Maximum Removable Pulse Width) = (Transition Distance to Threshold Value) x (Sampling Period: Ts) (2) so that this maximum removable pulse width takes the same value of the maximum delay time. As described heretofore, both the maximum delay time and the maximum removable pulse width can be expressed by a function whose value depends on the sampling period Ts. For this reason, these values can be varied by varying the sampling period Ts as described in the embodiment shown in Fig. 5. Therefore, in the case where the filter circuit according to the present invention is adopted for an input portion 38 of a programmable controller 10, as shown in Fig. 15, it is possible to reduce the delay time by supplying a sampling clock having a short period to the digital filter when the external device demands a fast response. In addition, in the case where the external device 9 does not demand such a fast response, it is possible to sufficiently remove the noise and chattering by supplying a sampling clock signal having a long period to the digital filter. In the former case, it is important to obtain the response that the sampling period Ts is selected so that the following condition can be satisfied: Ts ≦ (Program Scan Time) (3) The program scan time equals one process time (or one execution time) when the operation portion 14 repeatedly executes a control program stored in a storing portion 40 in the programmable controller 10. Therefore, in the case where the above condition is satisfied, it is possible to perform the operation based on the new input signal data at every process, so that it is possible to practically use the process speed of the operation portion. In the case where a high speed pulse supplied from a rotary encoder or the like is received to perform a position determining control, speed control or a cutting length control of a roll cut, the following relation must be satisfied in order to input the "L" or "H" level of the input signal: (Maximum Removable Pulse Width) < (Minimum Period of Input Signal)/2 = 1/2 x (Maximum Frequency of Input Signal) (4) Based on the equations (2) and (4), the sampling period Ts must be determined to satisfy the following relation: (State Transition Distance to Threshold Value) x (Sampling Period: Ts) < 1/2 x (Maximum Frequency of Input Signal: f max ) ∴ Ts < 1/2f max x (State Transition Distance to Threshold Value) (5) Meanwhile, in case of an external device in which a speedy response is not demanded, the sampling clock period is set in response to the characteristic of the device connected to the input portion 38 so that the inputted chattering and noise can be sufficiently removed. For example, in the case where bounding of relay contact is around some milli-second order, the maximum removable pulse width can be set to 10 msec. This can be expressed by the following relation: (Maximum Removable Pulse Width) ≧ ( Maximum Pulse Width of Input Noise) (6) Hence, based on the relations (2) and (6), the sampling period must be set to the contact so that the following relation will be satisfied: Ts ≧ (Maximum Pulse Width of Input Noise)/(State Transition Distance to Threshold Value) (7) It is possible to provide a plurality of time constant setting circuits 3 and sampling clock selecting circuits 4 by which the different sampling clock signals are supplied respectively to process a plurality of input signals. Fig. 16 shows one embodiment in this case. In this embodiment, two 2-bit registers which can set the value from the operation portion are provided as the time constant setting means 3, a frequency dividing counter is provided as the sampling clock generating circuit 2, and two data selectors which can select one data signal from four inputted data signals are provided as the sampling clock selecting circuit 4. Therefore, different set values are written into two time constant setting registers 3 whose outputs are independently selected by two data selectors 4 to thereby obtain two sampling clock signals 7, which are supplied to plural digital filters 1. Thus, it is possible to shorten the delay time for the filter input signal for which high speed response is demanded. In addition, it is possible to sufficiently remove the noise and chattering from other filter input signals to which such high speed response is not demanded. Incidentally, it is possible to constitute the time constant setting circuit 3 shown in Fig. 5 by a switch, register or other conventional device. Instead of obtaining the clock signals having different frequencies by dividing the basic clock input signal 42 in the sampling clock generating circuit 2, it is possible to use a known oscillator circuit which directly generates plural clock signals. Further, it is obvious that the sampling clock signal 7 which is supplied to the digital filter 1 can be supplied from a variable frequency oscillator. Since the present invention has a large hysteresis width and high pulse removal ability, resistance quantities of chattering and noise for the input waveform can be improved. In addition, there are no capacitances included in the circuit according to the present invention, so that a characteristic stabilized against temperature can be obtained and the present invention is suitable for circuit integration. Further, the time constant can be varied by varying the clock frequency, so that it is possible to reduce the delay time for the input signs which needs high speed input. Furthermore, it is possible to obtain an optimum filtering characteristic against the noise which depends on environment and power conditions, and the stability of the delay time can be remarkably improved.

Claims: A filter circuit comprising clock signal generating means (2) for generating a sampling clock signal, means (4) for two-level sampling of an input signal, a reversible counter (31) for performing a count-up operation when a sampled value of said input signal is at the high level and a count-down operation when a sampled value of said input signal is at the low level, first control means (44) coupled to said reversible counter (31) for detecting a first threshold value of a count by said reversible counter (31), second control means (45) coupled to said reversible counter (31) for detecting a second threshold value of a count by said reversible counter (31), means for providing a filter circuit output (6), characterized in that the first control means (44) are provided for setting the count of said reversible counter (31) to a value equal to said first threshold value plus a predetermined value when said count is incremented over said first threshold value, the second control means (45) are provided for setting the count of said reversible counter (31) to a value equal to said second threshold value minus said predetermined value when said count is decremented below said first threshold value, and in that the most significant bit (MSB) output of said reversible counter is provided as filter circuit output. A filter circuit according to claim 1, wherein said reversible counter is a synchronous binary up/down counter (31). A filter circuit according to claim 2, wherein said first control means and said second control means comprise respective logic gates connecting outputs of said up/down counter to inputs thereof. A filter circuit according to claim 1, wherein said reversible counter includes a plurality of flip-flops (25, 26, 27) interconnected by a logic gate arrangement. A filter circuit according to claim 1, wherein said first threshold value is three, said second threshold value is four and said predetermined value is four. A filter circuit according to claim 1, wherein said first threshold value is seven, said second threshold value is eight and said predetermined value is eight. A filter circuit according to claim 1, wherein said first threshold value is different from said second threshold value, and said predetermined value is equal to said first threshold value. A filter circuit according to claim 1, wherein said first threshold value is different from said second threshold value, and said predetermined value is equal to said second threshold value. A filter circuit according to claim 1, wherein said first threshold value, said second threshold value and said predetermined value are all different from each other. A filter circuit according to claim 1, wherein said clock signal generating means (2) comprises a crystal oscillator. A filter circuit according to claim 1, wherein said clock signal generating means (2) comprises: generating means (36) for generating a plurality of clock signals each having a different frequency; and selecting means for selecting one of said clock signals generated by said generating means and for outputting said selected one clock signal as a sampling clock signal. A filter circuit according to claim 11, wherein said generating means comprises a crystal oscillator connected to a frequency divider. A filter circuit according to claim 1, wherein said reversible counter comprises a plurality of flip-flops (48, 49, 50) interconnected by a logic circuit arrangement to produce a sequence of count states each having an arbitrarily assigned count value. A filter circuit according to claim 13, wherein the count values of said sequence of count states are assigned so that only one bit number is varied in the transition between the adjacent count states in said sequence.

Inventors: KASAHARA TOSHIRO, KASAHARA, TOSHIRO
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1989
Main classification: H03K5
IPC codes: G06F3, H03H17, H03K5