Transistor base current compensation circuitry

Abstract: The accuracy of a bandgap type reference voltage generator (102) which contains bipolar load elements (310,360,340;320,350) is increased by the use of current compensation circuitry (104) which includes a dummy load element (120,124) which is the electrical equivalent of the load elements of the generator, an operational amplifier (112) and a current mirror (118). The operational amplifier and the current mirror act to cause the same potential level (voltage) to be applied to the dummy load element as is applied to the load elements of the generator. A master leg of the current mirror generates a first output current which is identical to the current drawn by the load elements of the generator and provides (at 116) the current to the dummy load element. A slave leg of the current mirror generates a second output current which is identical to the first output current and which is coupled (at 690) to the load elements of the generator. Thus current used to drive the load elements of the generator is supplied by the compensation circuitry. This improves the accuracy of the output voltage generated by the reference voltage generator.

Description: This invention relates to a system which compensates for load current drawn from a source to limit loading of the source and in particular to a system which effectively cancels the loading effects of bipolar transistors of a voltage reference circuit so as to increase the accuracy thereof. U.S. Patent No. 4,263,519, in which there is common inventorship and a common assignee with the present patent application, is directed to a plurality of voltage reference circuits that each use the parasitic bipolar transistors formed by the drain regions, p-wells and the monolithic substrate of a Complementary Metal-Oxide Silicon (CMOS) integrated circuit. Reproduced herewith as FIG. 1 is the circuitry of FIG. 5 of the U.S. Patent No. 4,263,519. The E REF voltage appearing at output terminal 70 is a reference voltage that is relatively accurate. The bandgap voltage (E BG ) appears between terminals 69 and 30. If resistor 61 is equal to resistor 62, then E REF = 2 E BF . The operation of the circuit of FIG. 1 herein is well known: its description in U.S. Patent No. 4,263,519 is incorporated herein by reference. Some applications require greater accuracy than this circuit is capable of. One limiting factor on the accuracy of this circuit is that base current is drawn from node 69 to drive transistors 31 and 32. This base current, even through it is typically only a small fraction of the current flow through resistor 61, limits the accuracy of the voltage appearing at output terminal 70. In some applications, the needed accuracy of a reference voltage is greater than can be achieved by the circuitry of U.S. Patent No. 4,263,519. U.S. Patent No. 3,551,832 (J. G. Graeme) is directed to complementary bipolar circuitry which generates a current equal to load base current it draws from a source. The generated current is fed back to the source such that effectively the circuitry draws essentially no current from the source. Accordingly, there is effectively no loading of the source and the output voltage thereof can stay within a highly accurate range. One requirement of the Graeme circuitry is that the collectors of the transistors be separate. A silicon chip in which there are fabricated complementary metal-oxide silicon (CMOS) transistors inherently contains parasitic bipolar transistors in which all of the collectors are common, typically being part of the substrate of the chip. Thus, the Graeme circuitry is not easily fabricated in such a chip since it requires bipolar transistors with separate collectors. A chip, which includes CMOS and bipolar transistors in which the collectors are separate, is more complex to fabricate and therefore generally more expensive than one which uses the inherent parasitic bipolar transistors. It is thus desirable to have circuitry which can be formed using the parasitic bipolar transistors and conventional Field Effect Transistors (FETs) of a Complementary Metal-Oxide-Silicon (CMOS) integrated circuit to compensate for the needed base drive of a voltage reference circuit as described. In a preferred embodiment the present invention is directed to current compensation circuitry which is connectible to a voltage generator (e.g., the previously discussed bandgap reference voltage generator) which comprises or drives a load element, such as bipolar transistors, whose base current requirements limit the accuracy of the voltage generator. The compensation circuitry is adapted to supply the needed base current and thus improves the accuracy of the voltage generator. It preferably is fabricated on a CMOS integrated circuit chip using parasitic bipolar transistors. In one embodiment the compensation circuitry comprises an operational amplifier having two inputs and an output, a current mirror having an input and two outputs and a load element. The output of the operational amplifier is coupled to the input of the current mirror. The first output of the current mirror is coupled to the second input of the operational amplifier and to the load element. The second output of the current mirror is coupled to the first input of the operational amplifier. The output of the operational amplifier is coupled to the input of the current mirror. In another embodiment the compensation circuitry comprises a first load element, first circuit means having first and second inputs and an output with the output being coupled to the second input thereof for generating at the second input thereof a potential level which is essentially the same as one applied to the first input thereof, and second circuit means coupled to the first and second inputs of the first circuit means for sensing current drawn by the first load element and for generating an essentially identical current flow into a node coupled to the first input of the first circuit means. The invention will be better understood from the following detailed description taken in connection the accompanying drawings, in which : FIG. 1 shows a schematic of a prior art reference voltage generator as already discussed; FIG. 2 shows a reference voltage generator with current compensation circuitry in accordance with the present invention; and FIG. 3 shows a preferred embodiment of the current compensation circuitry of FIG. 2. Referring now to FIG. 2, there is shown a reference voltage generator circuit with current compensation 100 comprising within a first dashed line rectangle a reference voltage generator 102 and within a second dashed line rectangle current compensation circuitry 104 in accordance with the present invention. Reference voltage generator 102 is the same as the prior art reference voltage circuitry shown in FIG. 1 herein. The reference numbers used for the components and terminals of circuitry 102 are the same as those used for the corresponding components and terminals of the prior art circuitry shown in FIG. 1 with a "0" added there after. One limitation of the accuracy of reference voltage generator 102 is that base current needed to bias n-p-n transistors 310 and 320 is drawn from resistor 610 via node 690. The base current for transistors 310 and 320 varies with the betas of the transistors and with temperature. Transistor 310 and resistors 340 and 360 and transistor 320 and resistor 350 may be denoted as load elements. As will become clear from the following description, current compensation circuitry 104 generates a current which flows into node 690 and is essentially identical to the base current which flows from node 690 and into the bases of transistors 310 and 320. The base current normally drawn through node 690 from resistor 610 is replaced by current compensation circuitry 104 and thus essentially all of the current flow through resistor 610 flows through resistor 620. This improves the accuracy of the output voltage E REF0 appearing at terminal 700 of reference generator circuitry 102 by typically an order of magnitude or better. Current compensation circuitry 104 comprises a two input operational amplifier 112, a current mirror circuit 118, an n-p-n transistor 120 and a resistor 124. Operational amplifier 112 may be denoted as a first circuit means; current mirror circuit 118 may be denoted as a second circuit means; and transistor 120 and resistor 124 may be denoted as a load element or as a dummy load element. Node 690 is coupled to a positive input terminal of operational amplifier 112 and to a second (slave) output terminal of current mirror circuit 118. A negative input terminal of operational amplifier 112 is coupled to a first (master) output terminal of current mirror circuit 118, to the base of transistor 120 and to a node 116. An output terminal of operational amplifier 112 is coupled to an input (generally denoted in the art as a common terminal) of current mirror circuit 118 and to a node 114. The emitter of transistor 120 is coupled to a first terminal of resistor 124 and to a node 122. The collector of transistor 120 is coupled to a terminal 200 and to a positive voltage +VO. A second terminal of resistor 124 is coupled to a terminal 300 and a reference voltage which is shown as ground. The electrical path from the output of operational amplifier 112, through current mirror circuit 118 and to the negative input of operational amplifier 112 and the base of transistor 120, effectively causes the potential of node 116 to be essentially the same as the potential of node 690. Transistor 120 is designed to be the equivalent of transistors 310 and 320 and resistor 124 is designed to be equal to the equivalent of resistors 340, 360 and 350. If the same power supplies and base voltages are applied to transistors 310, 320 and 120, then the same total base current that flows into both transistors 310 and 320 flows into the base of transistor 120. Current mirror 118 acts to generate a flow of current into the bases of transistors 310 and 320 (node 690) which is identical to that flowing into the base of transistor 120 (node 116). Thus the current flow from node 690 to provide base current for transistors 310 and 320 is supplied into node 690 by circuitry 104 instead of having to be supplied from resistor 610. Accordingly, circuitry 104 supplies all of the base current for transistors 310 and 320 and thus all the current which flows through resistor 610 also flows through resistor 620. This improves the accuracy of the voltage E REF0 appearing at the output terminal 700 of reference voltage generator 102 by typically an order of magnitude or better. Referring now to FIG. 3, there is illustrated a preferred embodiment of current compensation circuitry 104 with circuitry of operational amplifier 112 shown within a dashed line rectangle 112a and circuitry of the current mirror circuit 118 shown within a dashed line rectangle 118a. Operational amplifier 112 comprises Field Effect Transistors (FETs) 124, 126, 128 and 130, an n-p-n bipolar transistor 132 and a resistor 138. Current mirror circuit 118 comprises FETs 134 and 136. In a preferred embodiment FETs 124 and 126 are both n-channel Metal-Oxide-Silicon (MOS) FETs and FETs 128, 130, 134 and 136 are all p-channel MOS FETs. The gate of transistor 124 is coupled to the source of FET 136 and to node 690. The sources of transistors 124 and 126 are coupled to a first terminal of resistor 138 and to a node 144. Second terminals of resistors 138 and 124 are coupled to terminal 300 and to ground potential. The sources of transistors 128 and 130 and the collectors of transistors 120 and 132 are coupled together to terminal 200 and to positive voltage +VO. The drain of transistor 124 is coupled to the gates of transistors 128 and 130, to the drain of transistor 128 and to a node 140. The drain of transistor 126 is coupled to the drain of transistor 130, to the base of transistor 130 and to a node 142. The emitter of transistor 132 is coupled to the sources of transistors 134 and 136 and to node 114. The gates of transistors 126, 134 and 136 are coupled to the drain of transistor 134, to the base of transistor 120 and to node 116. The emitter of transistor 120 is coupled to one terminal of resistor 124 and to a node 122. Transistors 134 and 136 serve as the master and slave legs, respectively, of the current mirror 118. The current that flows through transistor 134 is duplicated and flows through transistor 136. Thus the current that flows into the base of transistor 120 is essentially the same as flows into node 690 from transistor 136. The gates of transistors 124 and 126 draw essentially no current out of nodes 690 and 116, respectively, since the input impedance of transistors 124 and 126 is high as they are both FETs. Since transistor 120 and resistor 124 are the equivalent of transistors 310 and 320 and resistors 340, 360 and 350, and the supply voltages ,+VO and ground, used for power are identical, the current flowing into the base of transistor 120 is essentially equal to the sum of the currents flowing into the bases of transistors 310 and 320. In view of this it is clear that the current needed to bias transistors 310 and 320 is supplied by compensation circuitry 104. Thus the current which flows through resistor 610 is the same as flows through resistor 620 and accordingly the accuracy of voltage generator circuitry 102 is improved.

Claims: Circuitry (100) which compensates for load current from a source circuit, said circuitry comprising : a first load element (120,124); an operational amplifier (112,112a) having first and second inputs and an output; a current mirror (118,118a) having an input coupled to the output of the operational amplifier, having a first output coupled to the second input of the operational amplifier and to said first load element and having a second output coupled to the first input of the operational amplifier; and a second load element (310,320,340,350,360) which is essentially an electrical equivalent of the first load element and is a part of or is driven by said source circuit, said operational amplifier first input being connected to said second load element. The circuitry of Claim 1 wherein each of the load elements comprise a bipolar transistor (120,310,320) and a resistor (124,340,350,360). The circuitry of Claim 2 wherein the operational amplifier comprises field effect transistors (124,126,128,130). The circuitry of Claim 3 wherein the operational amplifier further comprises a bipolar transistor (132). The circuitry of Claim 4 wherein the field effect transistors are metal-oxide silicon transistors and the load elements each comprise at least one n-p-n bipolar transistor (120,310,320). The circuitry of Claim 4 wherein all the transistors are formed in a single integrated circuit chip with then n-p-n transistors all having common collectors. The circuitry of Claim 6 wherein the source circuit is formed on the same integrated circuit chip as the circuitry and comprises n-p-n transistors having collectors which are common with the collectors of the n-p-n transistors of the circuitry. A reference voltage generator comprising the current compensation circuitry of Claim 1 : the reference voltage generator (1020) comprising first (320) and second (310) n-p-n transistors and first (610), second (620), third (350), fourth (360) and fifth (340) resistors and a first operational amplifier (330) having first and second inputs and an output; the bases of the first and second transistors being coupled to first terminals of the first and second resistors; the emitter of the first transistor being coupled to a first terminal of the third resistor and to the first input of the operational amplifier; the emitter of the second transistor being coupled to a first terminal of the fourth resistor; a second terminal of the fourth resistor being coupled to a first terminal of the fifth resistor and to the second input of the operational amplifier; the output of the operational amplifier being coupled to a second terminal of the first resistor; said current compensation circuitry (104) being coupled to the bases of the first and second transistors as a second load, and to the base of a third n-p-n transistor (120), as the first load, said first load also comprising a sixth resistor (124) having a first terminal coupled to the emitter of said third transistor. The reference voltage generator of Claim 8 wherein the collectors of the first, second and third n-p-n transistors are coupled together and the second terminals of the third, fifth and sixth resistors are coupled together. The reference voltage generator of Claim 9 wherein the second resistor has a second terminal which is coupled to the second terminal of the third resistor. The reference voltage generator of Claim 10 wherein the second operational amplifier comprises : first (128), second (130), third (124) and fourth (126) field effect transistors (FETs), a fourth n-p-n transistor (132) and seventh resistor (138), each of the FETs having a gate, a drain and a source; the fourth n-p-n transistor having a base, an emitter and a collector; the sources of the first and second FETs being coupled to the collector of the fourth n-p-n transistor; the sources of the third and fourth FETs being coupled to a first terminal of the seventh resistor; a second terminal of the seventh resistor being coupled to a second terminal of the seventh resistor being coupled to a second terminal of the sixth resistor; the gates of the first and second FETs being coupled to the drains of the first and third FETs; the drains of the second and fourth FETs being coupled to the base of the fourth n-p-n transistor being coupled to the input of the current mirror; and the gate of the fourth FET being coupled to the first output of the current mirror and to the base of the third n-p-n transistor, the gate of the third FET being coupled to the second output of the current mirror. The reference voltage generator of Claim 11 wherein the current mirror comprises : firth (134) and sixth (136) field effect transistors (FETs) each having a fate, a source and a drain; the sources of the fifth and sixth FETs serving as the input of the current mirror and being coupled to the emitter of the n-p-n fourth transistor; the gates of the fifth and sixth FETs and the drain of the fifth FET serving as the first output of the current mirror and being coupled to the gate of the fourth FET and to the base of the third n-p-n transistor; and the drain of the sixth FET serving as the second output of the current mirror and being coupled to the gate of the third FET. The reference voltage generator of Claim 12 wherein the first, second, third, fourth, fifth and sixth FETs are n-channel metal-oxide-silicon transistors.

Inventors: SCHADE OTTO HEINRICH JR, SCHADE, OTTO HEINRICH, JR.
Applicants: GEN ELECTRIC, GENERAL ELECTRIC COMPANY
Application year: 1989
Main classification: G05F3
IPC codes: H03K17, G05F3