Method of manufacturing a semiconductor wafer

Abstract: A method for manufacture of a semiconductor wafer in a manner to attain a high uniformity in the thickness of a semiconductor layer, by first forming hardly polishable stoppers of mutually different thicknesses in the semiconductor, then polishing the semiconductor until the thicker stopper is exposed on one main surface of the semiconducbor, subsequently removing the thicker stopper to attain a thickness less than that of the thinner stopper, and thereafter polishing the aforesaid one main surface of the semiconductor until the thinner stopper is exposed. There is also disclosed a semiconductor device of a quantum well wire structure comprising a semiconductor layer formed on an insulator substrate, a thermally oxidized film of the semiconductor layer formed on such layer, and a gate electrode formed on one side of the semiconductor layer, wherein the channel width is determined by the thickness of the semiconductor layer. And a method of manufacturing such a semiconductor device with high precision comprises a step of forming a thin film by thermally oxidizing a semiconductor layer on an insulator substrate, a step of selectively removing the thin-film semiconductor layer, and a step of forming a gate electrode on one side of the semiconductor layer removed selectively.

Description: The present invention relates to a method of manufacturing a semiconductor wafer and, more particularly, to a method adapted to manufacture a highly flat semiconductor wafer having a uniform thickness. With regard to the method for manufacture of an SOI type semiconductor substrate, the art of utilizing a joining technique has already been developed by the present applicant. Fig. 3 (A) through (D) are sectional views illustrating the sequential steps in such manufacturing method mentioned. (A) One surface of a silicon semiconductor substrate a is selectively etched to form recesses b, b ... each having a depth of 1000 angstroms or so as illustrated in Fig. 3 (A). Regions c, c ... surrounded with such recesses b, b ... are used to serve as element-forming semiconductor layers later. (B) Subsequently, as illustrated in Fig. 3 (B), a silicon dioxide (SiO 2 ) layer d (e.g. 1 micrometer in thickness) is formed on the same surface of the semiconductor substrate a . (C) Then a silicon semiconductor substrate e is joined to the surface of the silicon dioxide layer d as illustrated in Fig. 3 (C). The semiconductor substrate e is to finally become the base of the SOI type semiconductor substrate as a whole. (D) Thereafter the reverse surface [lower surface in Fig. 3 (D)] of the semiconductor substrate a is polished to expose the surface of the silicon dioxide layer d as illustrated in Fig. 3 (D). Since the silicon dioxide (SiO 2 ) layer d has a high hardness, it serves as a stopper in the polishing step. Thus, there is obtained a semiconductor wafer where the semiconductor layers c, c ... are existent dispersively due to the silicon dioxide layer d . It is a matter of course that the lower surface of the semiconductor wafer in Fig. 3 (D) serves as the main surface thereof. According to the semiconductor wafer manufacturing method shown in Fig. 3, there exists a problem that the semiconductor layers c, c ... are prone to become nonuniform in thickness as shown in Fig. 4. Since the silicon semiconductor wafer has a size of 4 to 8 inches (1 inch = 2.54 cm), some thickness variation of 1 to 2 micrometers may occur if the silicon semiconductor wafer of such dimensions is polished to a depth of 600 micrometers or so. Consequently, as illustrated in the left-hand area of Fig. 4, the semiconductor layers c, c ... become excessively thicker to be connected eventually to one another through silicon. Meanwhile in some other portions, the semiconductor layers c, c ... become thinner as illustrated in the right-hand area of Fig. 4. It follows that, in such portions, the silicon dioxide layer d serving as a stopper is somewhat polished to be thinner. As a result, there may arise a fault that, in the worst case, some portions of the semiconductor layers c, c ... are completely eliminated by the polishing. Accordingly, the yield rate is deteriorated in the production to consequently bring about nonnegligible impediment in realizing low-cost production of IC, LSI, VLSI and so forth. It is therefore an object of the present invention to provide an improved method of forming semiconductor layers which are uniform in thickness. According to the present invention there is provided a method of manufacturing a semiconductor wafer, comprising the steps of: forming in a first surface of a first semiconductor substrate at least one first recess and at least one second recess shallower than said at least one first recess; forming a layer of hardly polishable material on said first surface of said first semiconductor substrate whereby the material filling said at least one first recess forms at least one first polishing stopper and the material filling said at least one second recess forms at least one second polishing stopper thinner than said at least one first polishing stopper; flattening the exposed surface of said layer (4) of hardly polishable material opposite said first surface of said semiconductor substrate; joining a second semiconductor substrate to said surface of said layer of hardly polishable material which has been flattened; polishing the exposed surface of said first semiconductor substrate opposite said first surface until said at least one first polishing stopper is exposed; selectively removing at least a portion of said at least one first polishing stopper until the exposed surface of said at least first polishing stopper becomes at least level with the bottom face of said at least one second recess; and polishing said first semiconductor substrate until said at least one second polishing stopper is exposed. The present invention is so contrived as to attain a high uniformity in the thickness of a semiconductor layer. Any other features, advantages and effects of the present invention than those mentioned above will become more apparent from the following detailed non-limitative description and the accompanying drawings. Figs. 1 and 2 illustrate an exemplary embodiment for carrying out the semiconductor wafer manufacturing method of the present invention, in which Figs. 1A through 1F are sectional views showing the sequential steps of the method, and Fig. 2 is a schematic sectional view of an apparatus used for the polishing operation; Figs. 3A through 3D are sectional views showing the sequential steps of a background art; Fig. 4 is a sectional view representing the problems to be solved by the present invention; Hereinafter the semiconductor wafer manufacturing method of the present invention will be described in detail with reference to a preferred embodiment shown in the accompanying drawings. Figs. 1 and 2 illustrate an exemplary embodiment contrived to carry out the semiconductor wafer manufacturing method of the invention, in which Fig. 1 (A) through (F) are sectional views representing the sequential steps of such method. (A) As illustrated in Fig. 1 (A), there are formed, in the surface of a semiconductor substrate 1, deep recesses 2 of several thousand angstroms (1 angstrom = 0.1 nanometer) in depth and shallow recesses 3 of one thousand angstroms or less. The deep recess 2 is formed in a portion to become a scribe region, while the shallow recess 3 is formed in a portion to define a field insulator film within an area which is surrounded with such scribe region and is used as a semiconductor chip later. It makes no difference if the deep recess 2 or the shallow recess 3 is formed first. (B) Then a silicon dioxide (SiO 2 ) layer 4 is formed on the surface of the semiconductor substrate 1 by a process of, e.g. CVD (chemical vapor deposition), and thereafter the surface of the silicon dioxide layer 4 is flattened. Fig. 1 (B) illustrates the state posterior to such flattening. Denoted by 5 is a portion filling the deep recess 2 of the silicon dioxide layer 4 to serve as a first stopper. And denoted by 6 is a portion filling the shallow recess 3 to serve as a second stopper. (C) Subsequently a semiconductor substrate 7 is joined to the surface of the silicon dioxide layer 4 as illustrated in Fig. 1 (C). This semiconductor substrate 7 finally serves as the substrate of the semiconductor wafer. (D) Thereafter the bottom surface of the semiconductor substrate is polished until the first stopper 5 of the silicon dioxide layer 4 is exposed as illustrated in Fig. 1 (D). Fig. 2 is a schematic sectional view of an exemplary polishing apparatus including a level block 8; heads 9, 9; mount plates 10, 10 attached to the heads 9, 9; and a wax 11 through which a semiconductor wafer W to be polished is secured to the mount plate 10. And a polishing operation is performed by moving the semiconductor wafer W relatively to the level block 8 by means of the heads 9, 9 in a state where an abrasive material 12 is interposed between the surface of the semiconductor wafer W to be polished and the level block 8. One of preferred abrasive materials is obtained by dispersing fine particles (e.g. 0.02 micrometer or so in particle size) of high-purity quartz into an alkaline solution of pH 10 to 11. During the polishing operation, the abrasive material 12 is dripped onto the level block 8 while the semiconductor wafer W is rotated with a slight gap maintained to the level block 8. It is also permitted of course to adopt the known polishing method which performs the operation while keeping a polishing cloth in contact with the surface of the semiconductor wafer W. However, according to such conventional method, there exists the possibility that the polishing cloth may be compressed and deformed along the surface of the semiconductor wafer W. Consequently the polishing with an abrasive material is considered superior. (E) Then the first stopper 5 of the silicon dioxide layer 4 exposed on the surface of the semiconductor wafer 1 is removed by the process of RIE (reactive ion etching) or wet etching. Fig. 1 (E) illustrates a state after removal of the first stopper 5. Although in this embodiment the first stopper 5 is wholly removed in its entire thickness, such complete removal is not exactly necessary. However, the minimum necessity is to execute the removal until the thickness of the first stopper 5 becomes less than or equal to that of the second stopper 6. (F) Thereafter a second polishing operation is performed until the surfaces of the second stoppers 6, 6 ... of the silicon dioxide layer 4 are exposed as illustrated in Fig. 1 (F). Denoted by 1a, 1a ... are semiconductor layers separated by the second stoppers 6, 6 ... of silicon dioxide and used to form thereon elements such as transistors. Such second stoppers 6, 6 ... directly serve as field insulator films. It is preferred that this polishing operation be performed in the same manner as the foregoing first polishing operation. Of course the conventional method employing a polishing cloth may be adopted as well. In this semiconductor wafer manufacturing method, the polishing after joining the semiconductor wafers together is executed in two stages. In the first polishing stage, the first stopper 5 positioned in the scribe region is used as a stopper to achieve macroscopic flattening. In this stage, thickness variation of the first stoppers 5 caused to the polishing corresponds to thickness variation of the semiconductor wafer substantially directly, and such variation ranges from 1 to 2 micrometers in the entire wafer. However, after termination of the first polishing stage, the first stopper 5 is so removed that its thickness becomes equal to or smaller than that of the second stopper 6, and then another polishing operation is performed while using the second stopper 6, whereby the thickness variation relative to the first stopper 5 is eliminated to nil. And by the next polishing with the second stopper 6, complete flattening can be realized in the microscopic region of each semiconductor chip. That is, in the stage posterior to termination of the first polishing operation, there is existent some thickness variation on the reverse surface of the semiconductor substrate 1. However, the first stoppers 5 composed of hardly polishable silicon dioxide with such thickness variation are removed immediately thereafter, and merely the semiconductor alone is left on the surface. And in the semiconductor which is a workpiece to be polished, such thickness variation can be eliminated almost completely in the second polishing operation. Although the thickness variations of the second stoppers 6, 6 ... correspond to those of the semiconductor wafer, fundamentally the film thicknesses of the second stoppers 6, 6 ... are substantially uniform, so that in the second polishing operation for abrading the semiconductor of a slight thickness, the stoppers 6, 6 ... are scarcely abraded differently from the first polishing operation. Thus, it becomes possible to attain a remarkably uniform film thickness of the individual semiconductor layers. As described hereinabove, the semiconductor wafer manufacturing method of the present invention comprises a step of forming, in a semiconductor, at least a first stopper of a hardly polishable material and a second stopper thinner than the first stopper, a step of polishing the semiconductor until the first stopper is exposed, a step of removing the first stopper until the thickness of the same becomes equal to or less than the thickness of the second stopper, and a step of polishing the semiconductor until the second stopper is exposed. Therefore, according to the above-described method of the present invention, even relatively great thickness variation of 1 to 2 micrometers or so caused in the entire semiconductor wafer during the first polishing step can almost be eliminated in the subsequent stage where the first stopper is removed after termination of the first polishing step. And the second polishing step is executed to finish the surface where such thickness variation is no longer existent, so that the thickness variation left finally on the surface is merely slight in value induced in the second polishing step. Consequently, the thickness variation can be rendered extremely small in comparison with the conventional polishing operation performed in a single step.

Claims: A method of manufacturing a semiconductor wafer, comprising the steps of: forming in a first surface of a first semiconductor substrate (1) at least one first recess (2) and at least one second recess (3) shallower than said at least one first recess (2); forming a layer (4) of hardly polishable material on said first surface of said first semiconductor substrate (1) whereby the material filling said at least one first recess forms at least one first polishing stopper (5) and the material filling said at least one second recess (3) forms at least one second polishing stopper (6) thinner than said at least one first polishing stopper; flattening the exposed surface of said layer (4) of hardly polishable material opposite said first surface of said semiconductor substrate (1); joining a second semiconductor substrate (7) to said surface of said layer (4) of hardly polishable material which has been flattened; polishing the exposed surface of said first semiconductor substrate (1) opposite said first surface until said at least one first polishing stopper (5) is exposed; selectively removing at least a portion of said at least one first polishing stopper (5) until the exposed surface of said at least first polishing stopper (5) becomes at least level with the bottom face of said at least one second recess (2); and polishing said first semiconductor substrate (1) until said at least one second polishing stopper (6) is exposed. A method according to claim 1, wherein said semiconductor substrate (1) is composed of silicon. A method according to claim 1 or 2, wherein said first stopper (5) is formed in a scribe region for isolating chips mutually. A method according to claim 1, 2 or 3, wherein at least one of the two mentioned polishing steps is executed while supplying an abrasive material (12) between said semiconductor substrate (1) and a level block (8), and causing a relative movement between said level block (8) and said semiconductor substrate (1). A method according to claim 4, wherein said abrasive material (12) is composed of an alkaline solution containing high-purity quartz. A method according to any one of the preceding claims, wherein said hardly polishable material is silicon dioxide. A method according to claim 6, wherein said at least one first stopper is removed by etching. A method according to claim 7, wherein said at least one first stopper is removed by reactive ion etching or by wet etching. A method according to any one of claims 6 to 8, wherein said layer (4) of hardly polishable material is formed by chemical vapour deposition.

Inventors: HASHIMOTO MAKOTO, MATSUSHITA TAKESHI, YAGI ATSUO, HASHIMOTO, MAKOTO, MATSUSHITA, TAKESHI, YAGI, ATSUO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1989
Main classification: H01L21
IPC codes: H01L21, H01L29