A distributed processing system

Abstract: In a distributed processing system, in which a knowledge base is stored in a data network having nodes keeping arbitrary data items and arcs reflecting relations among them, said nodes additionally keeping an own intelligence for interpreting instructions of programs (strings) in a suited language, for storing intermediate results, for exchanging messages with other nodes, for handling local control functions, for working instructions out of the program related to the corresponding node, and for transmitting the non-worked tail of the program string to other nodes addressed by the program through the arcs, an advantageous architecture is characterized in that parts of the data network together with the related intelligencies are put into interpretation modules (IM) which form an interpretation network in which said interpretation modules (IM) are connected to each other in a regular mesh and one outcome of each of a number of the interpretation modules (IM) are connected to the same common bus (CB), and that the common buses (CB) are each connected to an access processor (AP) which form an acess network.

Description: The invention is related to a distributed processing system comprising a number of similar interpretation modules, each said interpretation module comprising at least one processing unit, memory and a number of channels for communication with other interpretation modules or processors, said distributed processing system being suitable for storing a knowledge base in the form of a data network comprising logical nodes with data items and further comprising relations among said items, where said interpretation modules carry out the function of one or more logical nodes, interpret instructions of programs, strings, in a suited language, carry out instructions of said programs, store intermediate results, exchange messages with other nodes, and transmit non-worked tails of program strings to other nodes addressed by the programs. A highly distributed processing system for knowledge representation has been disclosed by the inventor in "Parallel processing - State of the Art Report" published by the Pergamon Infotech Ltd., Maidenhead Berkshire, 1987 pages 104 - 119 and in Future Generations Computer Systems, Vol. 4, 1988, pages 1 to 14. There is disclosed a Data Network the nodes of which keeping the pieces of information and being connected to other nodes by arcs which can be oriented or unoriented. Each node is associated with some data item which may correspond either to a name of some concept or to an arbitrary value. Each node may have more than one arc with the same name coming into them or emanating from them. Two nodes may be connected by an arbitrary number of arbitrary-oriented but differently namend arcs. In the Data Network there may be more than one node having the same data item, so, pointing some name or value of the node in the Data Network, some set of nodes may be identified. In the Active Data Network also disclosed in said publication as an extension of the Data Network each node keeps a special activity, enabling it to do local processing on the local data item, storing the intermediate results, exchanging messages with other nodes and handling a number of local control functions necessary for distributed processing in the Active Data Network. There are different kinds of links between nodes of the Active Data Network, namely "surface links", corresponding to the arcs of the Data Network, "extra links" and "loops". The surface links represent bidirectional channels permitting them to pass messages both along and opposite the orientation of the corresponding arcs. Their names and orientations are pointed together with the addresses of the nodes from which they emanate or to which they lead in both nodes connected by them. Each surface link has its personal order as regards each node it is incident to. The extra links enable the transfer of messages from each node of the Active Data Network directly to each other one using the special kinds of internode communications, for example a full graph of internode bonds may be supported by the extra links. The transference of messages through both surface and extra links may be either selective or "broadcasting" (to all the nodes these links lead to). The loops are used as some abstraction for the description of virtual propagation of wavefronts in the data space where they physically remain in the same nodes of the Active Data Network. All nodes of the Active Data Network may access a number of common channels, binding it with the external world, which are used concurrently by different nodes. It is also assumed that all nodes of the Active Data Network may work concurrently and asynchronously, exchanging messages with the other ones, without any centralised control device. The special "entry" node is added to the Active Data Network having only extra links with all other nodes of the Active Data Network. The activity in each node is provided by the same copy of the interpreter of a special language in which all tasks to be solved by the Active Data Network are presented. The main feature of this language is that programs in it operate not over a data structure, as usual, being constantly allocated to one or to a number of processors operating on common or distributed data, but among the active distributed data. They spread through them and dynamically form directly in their space integrated with the data parallel operational structures. In the Active Data Network the programs begin to spread through it by the node activities using surface and extra links and loops, with their selective or broadcasting modes of operation. This wave propagation may take place concurrently in different directions of the Active Data Network, creating, in general, multiple wavefronts proceeding all over the active data structure. During their propagation the wave formulae with special syntax and semantics may be replicated, split, modified by the node activities, loosing their utilised parts until finally exhausting their possibilities for colonising and transforming the data space. Figure 1 shows in principle a structure of nodes of an Active Data Network, each node having a data item associated with it and its own intelligence I, wherein the nodes are connected to each other by surface links (shown in figure 1 by fat lines), and extra links (shown by dotted lines). Furthermore figure 1 shows the loops described above. A special WAVE language has been disclosed for solving tasks by the distributed processing system. The WAVE language is able to formulate the tasks in a very dense manner and is highly suited for the distributed processing by distributed intelligencies. The language instructions are spread over the Active Data Network by strings worked by the nodes. Each activated node will work the instructions of the language string addressed to it and will send the non-worked tail of the instruction string to other nodes addressed by the tail. The proposed distributed processing system avoids traditional serial processing and is, therefore, the strictest parallel processing system avoiding main bottlenecks occuring with former proposals for parallel processing. In the most common parallel processing system, the SIMD system, parallel processing is provided for but the instructions are sent into the parallel processing system serially by a central intelligence. The above mentioned parallel processing system avoids centralized intelligence but works exclusively with the intelligences spread over the data network and being parts of the nodes. It is the object of the present invention to provide for a hardware solution realizing the above described overall idea in a highly advantageous manner. According to the present invention as claimed in claim 1 in a distributed processing system the interpretation modules are connected to each other by number of communication channels in a regular mesh, wherein said distributed system further has a number of buses, each said bus being connected to an access processor and all said access processors being connected together in a network, with every interpretation module being connected to a bus via a further one of said communication channels. In the parallel processing system according to the present invention one node, but for the sake of efficiency preferably a number of nodes with their data items together with the relations among them, represented by the arcs in the model of figure 1, are materialized in interpretation modules which form a network, in which the interpretation modules form groups being each connected to a common bus so that for each group there is a common bus. The common buses are controlled by access processors each of which is correlated to a common bus. The access processors are advantageously connected serially for forming an access ring. The access processors enable the entry into the interpretation network by means of terminals etc. The combination of the interpretation network with an access network, especially an access ring structure, provides the possibility of a highly efficient entry into the interpretation network, which entry can be performed by more than one user simultaneously. The instructions sent by the user will spread over the network structure in the above described manner. If more than one user enter the network simultaneously there can be an overlapping spreading over the network. The network is preferably a regular mesh with columns and rows, wherein the common buses collect the interpretation modules either of any row or of any column. In a highly advantageous embodiment of the present invention the interpretation modules form a 3-neighbour mesh. Preferably such a 3-neighbour mesh is performed in a network with common buses connecting all interpretation modules of a row by omitting every second horizontal interconnection of a usual 4-neighbour mesh. The fourth outcomes of the interpretation modules are now free for the connection to the common bus. The 3-neighbour mesh shows the same fine addressability for message routing as a 4-neighbour mesh, where normal processors with four outcomes are used. The access processors may keep the same local copies of language interpreters as the interpretation modules. The access processors are, in the same way as the interpretation modules, able to process and to distribute the instruction string in a highly efficient manner to the modules concerned. The interpretation modules could be realized by usual transputers. However, for sophisticated tasks it will be highly advantageous to realize a distributed processing system as mentioned above wherein the interpretation modules (IM) as claimed in claim 5 comprise six processors (CP, WA, DP, LP, TP, MR) communicating with each other either directly or indirectly and which are associated to memories, which processors are: a control processor for preparing the language string execution, creating control tracks reflecting the propagation of language string among the distributed network data, and for handling semantics of all control functions of the language, a wave analyser for string parsing and syntactical analysis, and for all necessary dynamic transformations of language strings, acting in close cooperation with the control processor, a data processor, especially for handling and processing the information contents of nodes as well as front variables and node variables of the language string, a link processor for traversing data bonds in the network knowledge base and for sending language strings along them, a track processor for working with track forests created by control processor and for sending language string tails along the tracks and merging different types of echo messages and for eliminating unnecessary tracks and activating garbage deletion in the data processor a message router establishing the external connections to other interpretation modules or access processors. The functions of the proposed six-processor interpretation modules as well as the used memories in the interpretation modules and their advantages will be described hereinafter with reference to the enclosed drawing, in which: figure 1 - shows in principle the structure of an Acitve Data Network figure 2 - shows the architecture of a computer implementing the Active Data Network and showing an interpretation network and an access ring figure 3 - shows a block diagram of a six processor interpretation module. Figure 2 shows an interpretation network IN wherein interpretation modules are arranged in a regular network consisting of columns C and rows R. The interpretation modules contain the data items of one node, preferably of a number of nodes, together with their relations among them, represented by the arcs in the model of figure 1. For example, the number of nodes and arcs, shown in figure 1, could be implemented in one interpretation module (IM). The interpretation modules IM each have four outcomes, one of which of each interpretation module IM of a row R is connected to a common bus CB associated to that row R. The other three outcomes of the interpretation modules form a regular 3-neighbour mesh, which is modified from a usual 4-neighbour mesh by omitting any second horizontal interconnection. The fringe interpretation modules in each column C and in each second row R are interconnected to form a torus-like topology. Each common bus CB is connected to an access processor AP, which also has four outcomes. Two of the outcomes form connection to neighbour access processors AP so that the access processors are serially connected with each other and form an access ring AR. The fourth outcome of each access processor is connected to a terminal T or a memory device MD, such as a magnetic disk. A user can enter the interpretation network IN through a terminal T and the corresponding access processor AP. The access processor AP interpretes the instruction string in the suited language, such as WAVE language, and distributes the rest of the instruction string either to all or to some dedicated interpretation modules IM. The program is worked within the interpretation network autonomously with a wavefront spreading over the network space. A multi-user operation is possible, if more than one user enters the interpretation network IN through different terminals T. The different wavefronts can overlap in the interpretation network IN. Figure 2 shows that the distances along the interpretation modules IM along the rows R are in general longer than along the columns C, so that the overall network is not square but oblong, approximately 2:1 with longer dimension in column C for minimizing the diameter of the network in relation to the number of the interpretation modules IM. The proposed topolgy is simple and can be realized by very large scale integrated (VLSI) technology without problems. The topolgy is especially suited for matching different graph structures often used in knowledge processing. Through the access ring AR initial activation of the interpretation network IN, collection of results emitted by the interpretation modules IM and the connection to terminals and external memories are performed. The memory devices MD are keeping not resident parts (subnetworks) of the network knowledge base as well as copies of the network knowledge base parts distributed among the interpretation modules. From a terminal a user may access each interpretation module IM either directly, through the access processor connected to this terminal, or by first sending a message through the access ring AR to the access processor AP connected to the proper common bus CB. The interpretation modules IM may access the memory devices MD also either directly, through the corresponding access processor AP, if it accesses the needed memory device MD, or by a transit to a neighbouring access processor. The access processors AP keep the same local copies of the language interpreter as the interpretation modules IM, and are generally invoked in processing of some parts of the language strings, sending the rest of them to different interpretation modules IM either directly, through the corresponding common bus, or by first propagation through the access ring AR. Figure 3 shows a multiprocessor architecture of an interpretation module, where the specialized processors directly communicate with each other in an asynchronous mode using buffering of messages for smoothing differences in rates and loads. The interpretation module IM consists of six specialized processors: control processor CP, wave analyser WA, track processor TP, data processor DP, link processor LP and message router MR. Control processor makes initial preparations for the wave language string execution, creates control tracks reflecting the WAVE parsing, execution and propagation among the distributed network data, and handles semantics of all control functions of the language. The control processor CP works in close cooperation with the wave analyser WA, which is dedicated especially for string parsing and syntactical analysis of the WAVE sentences, making all necessary dynamic transformations of the WAVE string (searching for the head, splitting into branches, replicating, deleting brackets etc.) Wave analyzer WA reaching elementary actions or transitions in the heads of formulae during their decomposition sends these operations to data processor DP or link processor LP. Data processor DP handles main operations on integers and strings and also some universal operations on simple lists (vectors), and works with contents of nodes of the network knowledge base as well as with front and node variables of the WAVE language. Link processor is a device for a fast search of tables and is used for traversing data bonds in the network knowledge base and sending WAVE strings along them. Data processor DP and link processor LP inform control processor CP about success or failure of their operation with resultant checking these situations in tracks. Track processor works directly with the track forests, created by the control processor CP, and specializes in very fast forward/backward track scanning, sending wave tails along the tracks and merging different types of echo messages (according to special logic of merging). It also eliminates unnecessary tracks, activates garbage deletion in data processor (utilized node variables). The track processor TP works in tough cooperation with the control processor CP, informing it of reaching nodes in the track forest under control or receiving orders for fast spreading tails of formulae along the tracks. The message router MR is used to receive wave formulae from access processors AP or other interpretation modules IM as well as to send them to the neighbouring interpretation modules, if data links of the network knowledge base match nodes in different interpretation modules. It also transmits echo signals passing through the part of the network knowledge base, resident in this interpretation module IM, as well as sends resultant messages to the access ring AR, which messages are obtained from the data processor DP. The interconnection topology of the interpretation module IM is as follows. The control processor CP is linked by bidirectional channels with wave analyser WA, data processor DP, link processor LP and track processor TP, and in one direction with message router, edged at control processor. Wave analyser WA has bidirectional links with control processor CP and data processor DP and unidirectional link with link processor LP, edged at link processor LP. Data processor DP is connected bidirectionally with control processor CP, wave analyser WA, and message router MR and unidirectionally with link processor LP, edged at link processor LP, and track processor TP, edged at data processor DP. Link processor LP is linked bidirectionally with control processor CP and unidirectionally with data processor DP, edged at link processor LP, wave analyser WA, edged at link processor LP, and message router MR, edged at message router MR. Track processor TP has bidirectional links with control processor CP and message router MR, and an unidirectional link with data processor DP, edged at data processor DP. Message router MR has bidirectional links with data processor DP and track processor TP, and unidirectional links with control processor CP, edged at control processor CP, and link processor LP, edged at message router MR. Message router MR has also bidirectional external communications EC with three other interpretation modules IM and one common bus CB, when meshed in an architecture as shown in figure 2. The processors of the interpretation module IM work with memory modules. Two of them are individual two-port memories, shared by two processors. Others may be internal memories of processors or separated modules. The memories are in detail: Suspended wave memory SW is a storage of WAVE formulae and their fragments, waiting to be activated and sent to wave analayser WA. Some of them are accessed by attached identification tokens. Identification stack IS is a stack keeping identification tokens which are attached by control processor CP to each wave string put into operation through wave analyser WA. The overall number of these tokens controls a number of wave strings under operation, which are spread among processors of the interpretation module IM. The tokens also ease addressability problems when many wave strings are processed concurrently. Directly accessible nodes memory DA represent a list of node addresses associated with each interpretation module IM which are directly content-addressable from access ring AR. Only through these nodes the initial injection of wave strings into the interpretation network IN is possible, other nodes should be inferenced by traversing the data links. This memory DA is a two port memory and accessible by control processor CP and data processor DP. Wave stack WS is a stack buffer of wave formulae under processing by wave analyser WA, especially in cooperation with data processor DP. Node table NT is a table of large volume keeping contents of the network knowledge base nodes and their abstract addresses. Node table NT is connected to data processor DP. Node variables memory NV represents a storage for spatial variables of the WAVE language which are dynamically attached to the node of the network knowledge base during wave strings propagations and subsequently shared by different wavefronts. These variables live on the network nodes until the latter keep tracks of the wave strings propagations. Node variables memory NV is connected to data processor DP. Front variables memory FV is a temporal storage occupied by transit front variables of the wave string during its presence within the current interpretation modules IM. Front variables are deleted from the interpretation module IM when the wave string propagates to another interpreatation module IM. The front variables propagate on wavefronts with the string. The front variable memory is accessible by the data processor DP. Link table LT is a storage for keeping the topolgy of part of the network knowledge base resident in the current interpretation module IM as well as links with the other parts, in other interpretation modules IM. Link table LT keeps node addresses and their links with contents of the links and is addressable by link processor LP. Track forest memory TF contains a forest-like list structure reflecting tracks which remain in the network knowledge base during wave string propagations, and which are used for further deployment of the wave processors and spatial control of distributed computing. Track forest memory is a two-port memory and shared by control processor CP and track processor TP. Reentry indicators memory RI is a table keeping addresses of the nodes, passed by wavefronts, together with the levels of their reenterability. When tracks are deleted, these indicators decrease. Null contents of indicators result in activating of garbage deletion by data processor, eliminating node variables attached to these nodes. Reentry indicators memory is used by track processor TP and control processor CP. Communication buffer CB is associated with the message router MR and buffers message traffic through the current interpretation module. The architecture shown in figure 3 works as a highly asynchronous direct interpreter of the WAVE language and the network knowledge base subnetwork, spatially matching one with the other and also spreading the wave logic to the other interpretation modules IM, if the network knowledge base is distributed among the interpretation modules IM and the wavefronts penetrate beyond the interpretation module borders. The specialized processors of the interpretation module IM may have firmware or direct hardware support of different operations on the described data structures serving for the interpretation process.

Claims: A distributed processing system comprising a number of similar interpretation modules, each said interpretation module comprising at least one processing unit, memory and a number of channels for communication with other interpretation modules or processors, said distributed processing system being suitable for storing a knowledge base in the form of a data network comprising logical nodes with data items and further comprising relations among said items, where said interpretation modules carry out the function of one or more logical nodes, interpret instructions of programs, strings, in a suited language, carry out instructions of said programs, store intermediate results, exchange messages with other nodes, and transmit non-worked tails of program strings to other nodes addressed by the programs, and said interpretation modules being connected to each other by a number of said communication channels in a regular mesh, wherein said distributed system further has a number of buses (CB), each said bus being connected to an access processor (AP) and all said access processors being connected together in a network, with every interpretation module being connected to a bus via a further one of said communication channels. A distributed processing system according to claim one, wherein that each access processor (AP) has output terminals, one of which is taken by the correlated common bus (CB), two of which are connected to neighbour access processor (AP) so as to form an access ring (AR) and another of which is connected to a terminal (T) or an external memory device (MD). A distributed processing system according to claim 1 or 2, wherein each interpretation module (IM) has four output terminals, three of which of all interpretation modules (IM) forming a regular 3-neighbour mesh, and the fourth of which is connected to one of the common buses (CB). A distributed processing system according to one of the claims 1 to 3, wherein the access processors (AP) keep the same local copies of the language interpreter as the interpretation modules (IM). A distributed processing system, comprising a number of similar interpretation modules, each said interpretation module comprising at least one processing unit, memory and a number of channels for communication with other interpretation modules or processors, said distributed processing system being suitable for storing a knowledge base in the form of a data network comprising logical nodes with data items and further comprising relations among said items, where said interpretation modules carry out the function of one or more logical nodes, interpret instructions of programs, strings, in a suited language, carry out instructions of said programs, store intermediate results, exchange messages with other nodes, and transmit non-worked tails of program strings to other nodes addressed by the programs, wherein the interpretation modules (IM) comprise six processors (CP, WA, DP, LP, TP, MR) communicating with each other either directly or indirectly and which are associated to memories, which processors are: a control processor (CP) for preparing the language string execution, creating control tracks reflecting the propagation of language string among the distributed network data, and for handling semantics of all control functions of the language, a wave analyser (WA) for string parsing and syntactical analysis, and for all necessary dynamic transformations of language strings, acting in close cooperation with the control processor (CP), a data processor (DP), especially for handling and processing the information contents of nodes as well as front variables and node variables of the language string, a link processor (LP) for traversing data bonds in the network knowledge base and for sending language strings along them, a track processor (TP) for working with track forests created by control processor and for sending language string tails along the tracks and merging different types of echo messages and for eliminating unnecessary tracks and activating garbage deletion in the data processor (DP) a message router (MR) establishing the external connections to other interpretation modules (IM) or access processors (AP). A distributed processing system according to claim 5, wherein each processor works with one or more data memories storing data from the network knowledge base and/or data transmitted and/or induced by the language string.

Inventors: SAPATY PETER S, SAPATY, PETER S.
Applicants: SAPATY PETER S, SAPATY, PETER S.
Application year: 1989
Main classification: G06F9
IPC codes: G06F9, G06F15