Logic circuit

Abstract: A logic circuit having a differential amplifier comprising a transistor pair of first (T₁) and second (T₂) transistors and further comprising a third transistor (T₃) connected in parallel with the second transistor (T₂), a first driving circuit (1) operatively connected to drive the first and second transistors with complementary output signals (A, A ) having a first (H₁) and second (L₁) levels, and a second driving circuit (2) operatively connected to drive the third transistor (T₃) with an output signal (B) having third (H₂) and fourth (L₂) levels, one (H₂) of which third and fourth levels is beyond one end of the range between the first and second levels and the other (L₂) of which levels is either within that range or beyond the other end of that range.

Description: The present invention relates to logic circuits, and more particularly to differential-input type logic circuits. Differential-input type logic circuits, for instance emitter-coupled logic (referred to hereinafter as ECL) circuits or current-mode logic (CML) circuits, have been widely employed because of their high-speed switching capability. When constituting an ECL logic circuit, such as a high-speed clock-pulse distributor, a first transistor Q₁ of two paired transistors forming an ECL circuit has a reference voltage V ref input (input C), and a second transistor Q₂ of the two paired transistors, having an input A, is generally provided with an additional, third transistor Q₃ in parallel thereto, as shown in Fig. 1, which third transistor Q₃ has an input B. In order to provide an effective input voltage difference between differential inputs A and C, it is required that a logical high level (referred to hereinafter as H level) and a logical low level (referred to hereinafter as L level) of input signals A and B to the second and third transistors Q₂ and Q₃ are typically 0.3 V higher and lower than the reference voltage V ref , in other words, peak-to-peak 0.6 V, as shown in Fig. 1, where input signal levels are illustrated by pulse forms drawn below the corresponding input terminals. The 0.3 V differences from the reference voltage V ref are required for the switching of current flowing through the paired transistors by only one of the input signals, allowing a margin for noise. In this example, clock pulses are input to the second transistor Q₂ (input A). The clock signal is enabled/disabled by input signal B taking L/H levels as input to the third transistor Q₃. The method involving employment of a reference voltage is referred to hereinafter as a reference voltage method, and is disadvantageous in terms of high-speed switching of the clock pulse in the case of the above logic circuit, because, as shown in Fig. 3(a), rise/fall time t₁ of the 0.6 V peak-to-peak input signal is, roughly speaking, twice the rise/fall time t₂ of a 0.3 V peak-to-peak input signal, as shown in Fig. 3(b), required by an ordinary ECL circuit having no reference voltage, where the paired transistors perform a full differential operation; that is, when one of the base electrode voltages is increased the other base electrode voltage is decreased. Another ECL-type logic circuit having a plurality of logical input signals thereto and having different input voltage levels is illustrated in Fig. 2, which is derived from the description of a preferred embodiment disclosed in U.S. Patent 4 745 582 (Fukushi, et al). In the Figure, an ECL circuit is composed of: first and second transistors Q₅ and Q₆ connected in parallel; a third transistor Q₇; and a current source IS2 connected to the emitters of the three transistors Q₅, Q₆ and Q₇. Collectors of the parallel-connected transistors Q₅ and Q₆ are connected together to a power source V CC line through a resistor, whereby the result of the logic operation is output to an output transistor Q₈. The collector electrode of the third transistor Q₇ is directly connected to the power source V CC line. In the cited U.S. patent, OR/NOR operation of inputs A and B, applied to the first and second transistors Q₅ and Q₆, respectively, is enabled when the input ( A ) to the third transistor Q₇ is high (this "high" level being chosen to lie between high and low levels of the inputs A and B); and the OR/NOR operation of the inputs A and B is disabled when the input ( A ) to the third transistor Q₇ is low (this "low" being chosen lower than the low level of the inputs A and B). The high level of the input to the third transistor Q₇ acts as a reference voltage for the inputs A and B, which accordingly must have peak-to-peak 0.6 V amplitude. Now, assuming that an attempt is made to utilise this circuit as a clock pulse distributor, then complementary clock pulses are input to the first and third transistors Q₅ and Q₇, as shown in Fig. 2, where signal levels to the input terminals are illustrated in the same way as in Fig. 1. The term "complementary" is used in the last sentence to express the fact that the two signals are seesawing though the levels involved are not symmetric, as described below. Signal levels of the input A to the third transistor Q₇ are chosen such that its high level H' is between high and low levels H and L of the inputs A/B to the first/second transistors Q₅/Q₆, and such that its low level L' is lower than the low level L of the inputs A/B. Levels H/L of the input B to the second transistor Q₆ disable/enable the clock pulses A/ A . When enabled by a low level L applied to input B (to the second transistor Q₆) the low level L acts as a reference voltage for the third transistor Q₇. Accordingly, the amplitudes of the inputs A and A , i.e. the clock pulse, must be as large as 0.6 V, which causes the same disadvantageous problem as is described for the circuit of Fig. 1. When the input B to the second transistor Q₆ is at the high level H, the output of the ECL is always low regardless of the logical levels of the inputs A and A (to the first and third transistors Q₅ and Q₇) and thus output of clock pulses is disabled. DE-A-1 230 079 discloses a logic circuit having the features of the preamble of accompanying claim 1. This logic circuit is a bistable multivibrator having a driving circuit in the form of a pair of feedback transistors within the multivibrator for producing a latch effect. Set and reset inputs of the multivibrator are supplied with voltage levels different from those supplied by the feedback transistors. According to the present invention there is provided a logic circuit comprising:- a differential amplifier having a transistor pair of first and second transistors connected to an output stage; a third transistor connected in parallel with the second transistor; and a first driving circuit operatively connected to drive the first and second transistors with complementary driving signals having first and second levels; and wherein the third transistor is arranged to be driven by another driving signal having third and fourth levels, wherein the third level is beyond one end of the range between the first and second levels; characterised in that:- a second driving circuit is operatively connected to drive the third transistor with said another driving signal having said third and fourth levels; both of said first and second driving circuits are provided independently of said differential amplifier, without being connected to the output stage, so as to allow selection of the levels of said driving signals; and in that the levels of said driving signals are selected such that the fourth level is either substantially equal to, or beyond, the other end of the range between the first and second levels. An embodiment of the present invention can provide a high-speed differential-input type logic circuit, for instance an ECL/CML-type logic circuit, operating with a plurality of logical inputs thereto. In an embodiment of the present invention, one of two paired transistors, which form an ECL/CML-type differential amplifier and which are driven by complementary pulse signals, is provided with at least one additional transistor in parallel thereto. The additional transistor has as its input, for instance, a signal whose high level is effectively higher than the high level of input signals of the paired transistors forming the ECL/CML, and whose low level is effectively lower than the high level of input signals of the paired transistors. When the input to the additional transistor takes its low level, the paired transistors perform a differential operation so as to output the complementary inputs (provide outputs corresponding to the complementary pulse input signals). When the input to the additional transistor takes its high level, the paired transistors are dominated by the high level input to the additional transistor; accordingly, the output of signals corresponding to the complementary input signals to the paired transistors is disabled. The above-described circuit maintains the advantage of the high-speed switching capability of ECL/CML circuitry to amplify the complementary signals. Reference is made, by way of example, to the accompanying drawings, in which:- Fig. 1 shows a previously proposed ECL circuit having a plurality of logical inputs and employing a reference voltage; Fig. 2 shows another previously proposed ECL circuit having a plurality of logical inputs, Fig. 3(a) illustrates signal levels and rise/fall times of input signals in relation to an ECL circuit using a reference voltage method, Fig. 3(b) illustrates signal levels and rise/fall times of input signals in relation to an ECL circuit employing no reference voltage, Fig. 4(a) illustrates an ECL circuit in accordance with an embodiment of the present invention, Fig. 4(b) illustrates a first driving circuit for connection to the ECL circuit of Fig. 4(a), Fig. 4(c) illustrates a second driving circuit for connection to the ECL circuit of Fig. 4(a), to input a larger signal than the first driving circuit, Fig. 5 illustrates an alternative possible variation of signal levels of the output of the second driving circuit, Fig. 6 is a truth table of logic operation of the circuit of Fig. 4(a), Fig. 7 illustrates an ECL circuit in accordance with another embodiment of the present invention, Fig. 8 is a truth table of logic operation of the circuit of Fig. 7. Fig. 9 illustrates a circuit in accordance with another embodiment of the present invention, the circuit employing GaAs source-coupled FET logic, Fig. 10 is a logic diagram of a clock pulse distributor employing circuits in accordance with an embodiment of the present invention, and Fig. 11 is a truth table of logic operation of the circuit of Fig. 10. With reference to the circuit diagrams of Fig. 4(a) to 4(c), and the truth table in Fig. 6, an embodiment of the present invention will hereinafter be described in some detail. First and second transistors T₁ and T₂ are paired to form a CML-type differential amplifier, and a third transistor T₃ is additionally connected in parallel with the second transistor T₂. Emitter electrodes of the three transistors T₁, T₂ and T₃ are connected together to (one terminal of) a constant-current source IS3, whose opposite terminal is connected to a negative terminal V EE line, for example at -5.2 V, of a direct current (DC) power source (not shown in the Figures). The constant-current source IS3 allows a constant DC current flow of, for example, 1 mA. Details of the constant-current source IS3 are not shown. The source may be composed, for instance, of a transistor having a resistor serially connected to its emitter electrode and having a constant voltage applied to its base electrode. The source may alternatively be a resistor. A resistor R₁ having, for example, a resistance value 300 ohms, is connected between one end of a common resistor R₃ having, for example, a resistance value 300 ohms and collector electrode of the first transistor T₁. The other end of the common resistor R₃ is connected to a positive terminal V CC line, for example at 0 V, of the DC power source. A resistor R₂ having a resistance value of, for example, 300 ohms, is connected between the said one end of the common resistor R₃ and collector electrodes of the second and third transistors T₂ and T₃. Collector electrodes of the first and second transistors T₁ and T₂ (T₃) are respectively connected to base electrodes of fourth and fifth transistors T₄ and T₅, having respective resistors R₄ and R₅ serially connected to their emitter electrodes. Thus, signals generated at the collector electrodes of transistors T₁ and T₂ (T₃) are amplified and output as output signals Q and Q from respective emitter electrode of the fourth and fifth transistors T₄ and T₅. The base electrodes of the first and second transistors T₁ and T₂ are respectively connected to output terminals O₁ and O₂ of a first driving circuit 1 shown in Fig. 4(b), which also has an ECL configuration. In the first driving circuit 1, emitter electrodes of sixth and seventh transistors T₆ and T₇, which are paired together, are connected together to a constant current source IS4, allowing a flow of, for example, 1mA, composed for instance in the same way as the constant current source IS3 of Fig. 4(a). Collector electrodes of T₆ and T₇ are connected to resistors R₆ and R₇, each having a resistance value of, for example, 300 ohms, which are in turn connected to one end of a common resistor R₈ having a resistance value of, for example, 300 ohms, the other end of which is connected to the DC power source V CC line. Output transistors T₈ and T₉ and resistors R₉ and R₁₀ are provided in a configuration similar to that of transistors T₄ and T₅ and resistors R₄ and R₅ in Fig. 4(a). Base electrode of third transistor T₃ (Fig. 4(a)) is connected to an output terminal O₃ of a second driving circuit 2 which is illustrated in Fig. 4(c) and which also has an ECL configuration. In the second driving circuit 2, emitter electrodes of tenth and eleventh transistors T₁₀ and T₁₁, which are paired together, are connected together to a constant current source IS5 allowing a flow of, for example, 1 mA, composed for instance in the same way as the current source IS3 of Fig. 4(a). A resistor R₁₁ having a resistance value of, for example, 600 ohms connects the collector electrode of the eleventh transistor T₁₁ to the DC power source V CC line. The collector electrode of the tenth transistor T₁₀ is directly connected to the DC power source V CC line. An output transistor T₁₂ and a resistor R₁₂ are configured in a similar way to transistor T₅ and resistor R₅ in Fig. 4(a). Signal levels of the outputs from the terminals O₁ and O₂ of the first driving circuit 1, i.e. the inputs A and A to the first and second transistors T₁ and T₂, are such that the high level H₁ is typically -1.2 V, and the low level L₁ is typically -1.5 V. Signal levels of the output from the terminal O₃ of the second driving circuit 2, i.e. the input B to the third transistor T₃, are such that the high level H₂ is typically -900 mV, which is 300 mV higher than the high level H₁ of the signals A/ A of the first driving circuit 1, and the low level L₂ is typically -1.5 V, which is essentially the same as the low level L₁ of the signals input A and A to the first and second transistors T₁ and T₂. The amount 300 mV is provided as an effective difference from the high level of the input signals A/ A so as to make allowances for possible problems caused by noise or transitions. The levels of the input signals A, A and B are illustrated in blocks corresponding to the relevant driving circuits drawn below corresponding input terminals in Fig. 4(a) for comparison. When the input B to the third transistor T₃ is of low level L₂, the third transistor T₃ has no effect on the differential operation of the first and second transistors T₁ and T₂, and the complementary signal inputs, for example in this case clock pulses, A and A are output as Q and Q , in other words, output of the clock signal is enabled. When the input B to the third transistor T₃ is of high level H₂, the third transistor T₃ dominates over the high level H₁ input to the first transistor T₁. Consequently, current is switched from the first transistor T₁ to flow in the third transistor T₃. Thus in this state, output of the complementary input signals, i.e. the clock pulses, A and A is disabled. Furthermore, the inputs A and B perform an OR/NOR operation. Results of these logic operations are shown in the truth table of Fig. 6. Although, in the above-described embodiment, the low level L₂ of the input B is chosen essentially the same as the low level L₁ of the inputs A and A , the low level L₂ of the input B may be chosen lower, as denoted by L₂'' in Fig. 5, than the low level L₁ of the inputs A and A , as long as the low level L₂'' is effectively lower than the high level H₁ of the inputs A and A , as described previously. Selection of an appropriate low level (L₂ or L₂'') is determined as a compromise between the required switching speeds of the signal A/ A and the signal B depending upon circuit requirements. In an application to a clock pulse distributor, the clock pulse switching has priority over the switching speed of the enable/disable signal pulse B. Therefore, the amplitude of the enable/disable signal pulse B is generally chosen larger than the clock signal pulse A/ A (consequently the rise/fall time of the enable /disable signal pulse B is generally longer than the rise/fall time(s) of the clock signal pulse A/ A . Moreover, in a clock pulse distributor, even though the amplitude of the enable/disable signal pulse B is chosen larger than that of the clock signal pulse A/ A , operation speed of the circuit as a whole is not deteriorated because the frequency of the clock signal pulse A/ A is incomparably higher than that of the enable/disable signal. A second embodiment of the present invention is illustrated in the circuit diagram in Fig. 7 and a truth table in Fig. 8. The circuit of the second embodiment is the same as that of the first embodiment shown in Fig. 4(a) except that a further additional transistor T₃′, connected to a further driving circuit 3, is provided in parallel to the third transistor T₃. The base electrode of the further additional transistor T₃′ is connected to the third driving circuit 3 which is of the same constitution as and has the same output levels as the second driving circuit 2. Accordingly, a high level of input C to the transistor T₃′ dominates the operation of the first and second transistors T₁ and T₂, as well. Thus, the three inputs A, B and C perform an OR/NOR operation. Results of these logic operations are shown in the truth table of Fig. 8. Although in the above-described embodiments of the present invention the ECL circuits are indicated to be composed of bipolar transistors, it will be apparent that embodiments of the present invention can be applied also to other transistor types, for example to a source-coupled FET logic (SCFL) circuit composed of gallium arsenide (GaAs) FETs (field effect transistors) as shown in Fig. 9, which corresponds to the upper half of the circuit shown in Fig. 4(a). An application of an embodiment of the present invention to a clock pulse distributor for branching clock pulses is illustrated in a logic diagram in Fig. 10 and a truth table in Fig. 11. In Fig. 10, blocks 1 and 2 represent first and second driving circuits 1 and 2, respectively. Block 3 represents the ECL circuit shown in the upper half of Fig. 4(a). The signals A, A and B correspond to those of Figs. 4. A complementary clock pulse signal C/ C is branched to two groups C₁/ C ₁ and C₂/ C ₂. Each of signals S₁ and S₂ enables/disables the output clock pulse C₁/ C1 and C₂/ C ₂, respectively. Results of the logic operation of the clock pulse distributor are shown in truth table of Fig. 11. As described above, the distribution of a high-speed clock pulse can be controlled by signals S₁ and S₂, respectively, while reserving the advantage of the high-speed ECL configuration. A circuit configuration in accordance with an embodiment of the present invention can be advantageous particularly in a standard cell type LSI (large-scale integrated circuit), where an unused output terminal of the clock pulse distributor must be kept at a DC voltage so that noise radiation therefrom is prevented. If a circuit configuration not having the signal level conditions of an embodiment of the present invention is employed, the reference voltage method must be employed, where the input clock pulse amplitude must be large, resulting in deterioration of operation speed of the entire LSI. Pulse delay time of the output pulse from the input pulse A to transistors T₁ and T₂ in the circuit of Fig. 4(a) can be as short as 80 ps, compared with a delay time of 100 ps for the circuit of Fig. 1. As a result, clock pulse frequency can be increased with the embodiment of the present invention. Although in the above-described embodiments of the present invention the ECL circuits are shown composed of NPN transistors, it is apparent that embodiments of the present invention can be applied to ECL/CML circuits composed of PNP transistors, where the condition "the level H₂ is higher than the other high-level H₁" is replaced with a condition "a low-level L₂ of the input B is lower than the low-level L₁ of the complementary inputs A/ A ", so that the third transistor can dominate over the first transistor, etc. Although in the above-described embodiments of the present invention the circuits have an ECL configuration with two output transistors T₄ and T₅, providing output signals Q and Q respectively, it is apparent that embodiments of the present invention can be applied to circuits having both or either of the two output transistors T₄ and T₅ omitted. The voltage levels and the resistance values, etc., referred to in the above-description of embodiments of the present invention are given only by way of example. It will be apparent that these circuit values can be arbitrarily modified according to circuit requirements, and that the common resistor, such as R₃ or R₈, can be omitted, as long as the level conditions of the present invention are satisfied.

Claims: A logic circuit comprising:- a differential amplifier having a transistor pair of first and second transistors (T₁, T₂) connected to an output stage (T₄, T₅); a third transistor (T₃; T₃, T₃') connected in parallel with the second transistor (T₂) ; and a first driving circuit (1) operatively connected to drive the first and second transistors (T₁, T₂) with complementary driving signals ( A , A) having first and second levels (L₁, H₁); and wherein the third transistor (T₃; T₃, T₃') is arranged to be driven by another driving signal (B; B, C) having third and fourth levels (L₂, H₂), wherein the third level (e.g. H₂) is beyond one end of the range between the first and second levels (L₁, H₁) ; characterised in that:- a second driving circuit (2; 2, 3) is operatively connected to drive the third transistor (T₃; T₃, T₃') with said another driving signal (B; B, C) having said third and fourth levels; both of said first and second driving circuits are provided independently of said differential amplifier, without being connected to the output stage, so as to allow selection of the levels of said driving signals ( A , A; B; B, C); and in that the levels of said driving signals are selected such that the fourth level (e.g. L₂) is either substantially equal to, or beyond, the other end of the range between the first and second levels (L₁, H₁). A logic circuit as claimed in claim 1, wherein a high level (H₂) of said another driving signal (B; B, C) of the second driving circuit (2; 2, 3) is effectively higher than a high level (H₁) of said complementary driving signals ( A , A) of the first driving circuit (1). A logic circuit as claimed in claim 2, wherein the low level (L₂) of said another driving signal (B; B, C) of the second driving circuit is substantially equal to the low level (L₁) of said complementary driving signals ( A , A) of said first driving circuit (1). A logic circuit as claimed in claim 2, wherein the low level (L₂) of said another driving signal (B; B, C) of the second driving circuit (2; 2, 3) is lower than the low level (L₁) of said complementary driving signals ( A , A) of the first driving circuit (1). A logic circuit as claimed in claims 2, 3 or 4, wherein the said transistors (T₁, T₂, T₃, T₃') are NPN transistors. A logic circuit as claimed in claim 1, wherein the said transistors (T₁, T₂, T₃, T₃') are PNP transistors, and wherein a low level (L₂) of said another driving signal (B; B, C) of the second driving circuit (2; 2, 3) is effectively lower than a low level (L₁) of said complementary driving signals ( A , A) of the first driving circuit (1). A logic circuit as claimed in claim 6, wherein the high level (H₂) of said another driving signal (B; B, C) of the second driving circuit (2; 2, 3) is substantially equal to the high level (H₁) of the complementary driving signals ( A , A) of the first driving circuit (1). A logic circuit as claimed in claim 6, wherein the high level (H₂) of said another driving signal (B; B, C) of the second driving circuit (2; 2, 3) is higher than the high level (H₁) of said complementary driving signals ( A , A) of the first driving circuit (1). A logic circuit as claimed in any one of claims 5 to 8, wherein emitters of the first, second and third transistors (T₁, T₂, T₃, T₃') are operatively connected with each other, and connected to an essentially constant-current source (IS3, IS1). A logic circuit as claimed in claim 9, wherein the essentially constant-current source (IS3, IS1) comprises a fourth transistor having a resistor serially connected to an emitter electrode of the fourth transistor and an essentially constant voltage applied to a base electrode of the fourth transistor. A logic circuit as claimed in claim 9, wherein the essentially constant-current source (IS3, IS1) comprises a resistor. A logic circuit as claimed in any one of claims 5 to 11, wherein a resistor (R₁, R₂) is connected between a collector power source (V cc ) and one of the collectors of the first and second transistors (T₁, T₂), whereby a logic signal is output from the collector connected to the said resistor. A logic circuit as claimed in any preceding claim, wherein the rise time and fall time of said another driving signal (B; B, C) of the second driving circuit (2; 2, 3) are longer than the rise time and fall time of said complementary driving signals ( A , A) of the first driving circuit (1). A logic circuit as claimed in any preceding claim, wherein the frequency of said another driving signal (B; B, C) of the second driving circuit (2; 2, 3) is lower than the frequency of said complementary driving signals ( A , A) of the first driving circuit (1). A logic circuit as claimed in claim 1, wherein the said transistors (T₁, T₂, T₃, T₃') are GaAs FETs.

Inventors: EMORI SHINJI, SHIMOTSUHAMA ISAO, TAMAMURA MASAYA, WATANABE YOSHIO, EMORI, SHINJI, SHIMOTSUHAMA, ISAO, TAMAMURA, MASAYA, WATANABE, YOSHIO, EMORI, SHINJI C/O FUJITSU LIMITED, SHIMOTSUHAMA, ISAO C/O FUJITSU LIMITED, TAMAMURA, MASAYA C/O FUJITSU LIMITED, WATANABE, YOSHIO C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H03K19
IPC codes: H03K19