Complementary output circuit for logic circuit

Abstract: An output circuit for a high speed and low power logic circuit is disclosed. The logic circuit (7) performs a logic operation on a plurality of input data signals supplied thereto and produces true and complementary intermediate output signals (P, P ), the logic high level of the intermediate output signal being lower than a first power voltage (V DD ) and the logic low level thereof being substantially equal to a second power voltage (GND). The output circuit (8) includes a P-channel MOS transistor (MP11, MP12) having a gate supplied with the complementary intermediate output signal ( P ,P), a source connected to a power voltage supplied with the first power voltage and a drain connected to an output terminal, and an N-channel MOS transistor (MN11, MN12) having a gate connected to the power terminal, a source supplied with the true intermediate output signal (P, P ) and a drain connected to the output terminal, and thus produces at the output terminal an output signal having a substantial logic amplitude between the first (V DD ) and second power voltages (V GND ).

Description: BACKGROUND OF THE INVENTION The present invention relates to a MOS transistor logic circuit and, more particularly, to an output circuit for a high speed and low power logic circuit. There are two types in a logic circuit. One of them is a complementary MOS transistor logic circuit and the other is a single channel, N-channel in particular, MOS transistor logic circuit. The complementary MOS transistor logic circuit uses P- and N-channel MOS FET's and has an advantage of a low power consumption, but has a disadvantage of a relatively low speed operation. This is because a P-channel MOS transistor has a switching speed slower than that of an N-channel MOS transistor. Particularly, a logic circuit including a plurality of P-channel MOS transistors connected in series between a power supply terminal and an output terminal requires a considerably long switching time. In contrast, the N-channel MOS transistor logic circuit uses enhancement and depletion type MOS FET's and has an advantage of a high speed operation. However, the logic circuit employing enhancement and depletion N-channel MOS transistors has a disadvantage of large power consumption. As a high speed and low power logic circuit, therefore, is utilized such a logic circuit that employs only enhancement N-channel MOS transistors driven in a push-pull manner with a power supplied between higher and lower power supply voltages. However, such a logic circuit has a disadvantage that the logic high level of an output signal produced therefrom does not reach the higher power supply voltage, although the logic low level of the output signal reaches the lower power supply voltage. This is because there exists a MOS transistor whose source is connected to an output terminal and shows drain is connected to a power supply terminal supply with the higher power supply voltage. The logic high level of the output signal becomes therefore lower than the higher power supply voltage by a threshold voltage of the used transistor. A so-called bootstrap circuit is often employed to raise the logic high level of the output signal up to the higher power supply voltage. However, the bootstrap circuit lowers an operation speed of the logic circuit. Therefore, a level conversion circuit is added as an output circuit, in place of using the bootstrap circuit, to convert the logic high level of the output signal into a voltage level equal to the higher power supply voltage. A complementary MOS (C-MOS) inverter is well known in the art as a level conversion circuit. The C-MOS inverter consists of P-channel and N-channel MOS transistors connected in series between the higher and lower power terminals, and the output signal produced from the logic circuit is applied to the gates of these transistors. The high level of the output signal turns the N-channel transistor ON and the low level thereof turns the P-channel transistor ON. As a result, the output signal from the logic circuit is widened to have an amplitude between the first and second power supply voltages. It should be, however, noted that the logic high level of the output signal is still slightly lower than the first power supply voltage, not exactly equal thereto. For this reason, the conductive resistance of the N-channel transistor is relatively large to reduce the load driving capability thereof. The operation speed for changing the output signal from the higher power supply voltage to the lower power supply voltage is thereby made slow. Moreover, the C-MOS inverter operates as additional gate circuit, so that the above changing speed is further lowered. From GB-A-2 113 936 a digital level shifter is known which latches one transistor of a transistor pair off to prevent a current dissipation. Furthermore, GLASSER et al.: "The Design and analysis of VLSI circuits", Addison-Wesley, 1985, Reading, US, pages 20, 21 and 31, teaches that the enhancement type MOS transistor supplied at its drain and gate with the same voltage produces at its source an output voltage lower than the gate voltage by its threshold voltage. As a solution, a combination of both pass transistors and restoring gates is proposed. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an improved output circuit of a logic circuit for improving a high speed operation and a lower power consumption of the logic circuit. Another object of the present invention is to provide an output circuit which receives a signal having a first amplitude and outputs a signal having a second, enlarged amplitude without lowering an operation speed. Still another object of the present invention is to provide a logic gate which operates at a high speed with a low power consumption and produces an output signal whose logic high level is substantially equal to a higher level of a power supply and whose logic low level is substantially equal to a lower level of the power supply. According to the present invention, an output circuit is provided with the features defined in claim 1. When the input signal takes the logic high level, the N-channel transistor is biased by a voltage slightly smaller than a threshold voltage thereof and is thus turned OFF. On the other hand, the P-channel transistor is supplied at the gate thereof with the second power voltage and is thus turned ON. Accordingly, the output terminal is raised up to the higher power voltage. When the input signal takes the logic power level, the N-channel transistor is biased by the higher power voltage and is thus turned ON. Since the N-channel transistor is biased by the power voltage, the conductive resistance thereof is extremely small to drive the output terminal with a large current. Moreover, since the input signal is applied to the source of the N-channel transistor, not to the gate thereof, the output terminal is changed to the lower power voltage at a high speed. On the other and, the P-channel transistor is supplied at the gate thereof with the logic high level of the input signal. Since the logic high level of the input signal is lower than the higher power voltage, the P-channel transistor is not in the turned-OFF state, but in a high internal impedance state. For this reason, the output terminal is not lowered up to the lower power voltage, and it takes a voltage slightly higher than the lower power voltage. However, since the N-channel transistor has a large current capacity, the voltage slightly higher than the lower power voltage is negligible value. The output terminal thus obtained takes the lower power voltage substantially. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantage and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a circuit diagram representative of a first embodiment of the present invention; Fig. 2 is a circuit diagram representative of a second embodiment of the present invention; Fig. 3 is a circuit diagram representative of a third embodiment of the present invention; Fig. 4 is a circuit diagram representative of a fourth embodiment of the present invention; and Fig. 5 is a circuit diagram representative of a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS Referring to Fig. 1, there is shown a 2-input EX-OR (Exclusive OR) gate circuit as a first embodiment of the present invention. This gate circuit includes first true and complementary input data terminals 1 and 2, second true and complementary input data terminals 3 and 4, true and complementary output terminals 5 and 6, a logic operation circuit 7, and an output circuit 8. The terminal 1 is supplied with a first data signal IA whose logic high level is substantially equal to a first power voltage and whose logic low level is substantially equal to a second power voltage. In the present and following description, the first power voltage is a positive voltage of 5V and indicated as "V DD ", and the second power voltage is a ground level, i.e. 0V, and indicated as "GND". The terminal 2 is supplied with an inverted signal IA of the first data signal IA. The terminal 3 is supplied with a second data signal IB whose logic high level is substantially V DD and whose logic low level is substantially GND, and the terminal 4 is supplied with an inverted signal IB of the second data signal IB. The logic operation circuit 7 is constituted of eight MOS transistors MN13 to MN20, all of which are of an enhancement N-channel type. The transistors MN13 and MN14 are connected in series between a first power supply terminal 9 applied with V DD and a second power supply terminal 10 applied with GND. The transistors MN15 and MN16 are also connected in series between the terminals 9 and 10. The transistor MN17 is connected between a node N1 of the transistors MN13 and MN14 and an intermediate complementary output terminal 11 and the transistor MN18 is connected between the node N1 and an intermediate true output terminal 12. The transistor MN19 is connected between a node N2 of the transistors MN15 and MN16 and the terminal 12 and the transistor MN20 is connected between the node N2 and the terminal 11. The input terminal 1 is connected in common to the gates of the transistors MN14 and MN15 and the terminal 2 is connected in common to the gates of the transistors MN13 and MN16. The terminal 3 is connected in common to the gates of the transistors MN18 and MN20 and the terminal 4 is connected in common to the gates of the transistors MN17 and MN19. When the first and second input data signals IA and IB both take the logic high level, the transistor MN14, MN18, MN15 and MN20 are turned ON and the remaining transistors MN13, MN17, MN16 and MN19 are turned OFF. In case where both of the data signals IA and IB take the logic low level, the transistors MN14, MN18, MN15 and MN20 are turned OFF, and the transistors MN13, MN15 MN16 and MN19 are turned ON. Accordingly, so long as both of the data signals IA and IB take the same logic level, an intermediate true output signal P at the terminal 2 takes the logic low level and an intermediate complementary output signal P at the terminal 11 takes the logic high level. On the other hand, when the first and second data signals IA and IB takes the different logic levels from each other, the transistors MN14, MN17, MN15 and MN19 (or MN13, MN18, MN16 and MN20 are turned ON, and the transistors MN13, MN18, MN16 and MN20 (or MN14, MN17, MN15 and MN19) are turned OFF. Accordingly, the intermediate true and complementary output signals P and P take the logic low level and logic high level, respectively. Thus, the logic operation circuit 7 performs an EX-OR logic operation on two input data signals IA and IB. Since the circuit 7 is composed only of the enhancement N-channel MOS transistors, it performs the logic operation at a high speed. Moreover, the transistor MN13 and MN14 and those MN15 and MN16 are driven in a push-pull manner, respectively, and hence the power consumption of the circuit 7 is very small. However, since the logic operation circuit 7 includes only the enhancement N-channel MOS transistors, the logic high level of the intermediate output signal P (or P ) does not reach the V DD level. It is lower than the V DD level by the threshold voltage (V TN ) of the N-channel MOS transistor. Thus, the logic high level of the intermediate output signal P ( P ) takes (V DD - V TN ) level and the logic low level thereof takes GND level. In other word, the intermediate output signal P ( P ) has a logic amplitude between (V DD - V TN ) level and GND level. In order to produce an output signal having a substantial logic amplitude between V DD and GND levels without lowering a total logic operation speed, the output circuit 8 is provided between the intermediate output terminals 11 and 12 and the output terminals 5 and 6 as the final output terminals of the EX-OR gate circuit. The output circuit 8 includes an enhancement P-channel MOS transistor MP11 having a source connected to the V DD terminal 9, a drain connected to the complementary output terminal 6 and a gate connected to the intermediate true terminal 12, an enhancement N-channel MOS transistor MN11 having a drain connected to the terminal 6, a source connected to the intermediate complementary terminal 11 and a gate connected to the V DD terminal 9, and enhancement P-channel MOS transistor MP12 having a source connected to the V DD terminal 99, a drain connected to the true output terminal 5 and a gate connected to the intermediate complementary terminal 11, and an enhancement N-channel MOS transistor MN12 having a drain connected to the terminal 15, a source connected to the intermediate true terminal 12 and a gate connected to the V DD terminal 9. When the intermediate output signal P is at the logic low level (i.e., GND level), the transistor MN12 is supplied with V DD voltage between the gate and source thereof, so that the conductive resistance thereof is extremely small to drive the output terminal 5 with a large current. The potential at the terminal 5 is thereby change to the GND level at a high speed. At this time, the transistor MP12 is applied at the gate thereof with the (V DD - V TN ) level, so that it is not in the cut-off state, but in the high internal impedance state. Since the transistor MN12 has a large current ability, however, the potential at the terminal 5 is slightly higher than the GND level and takes about 0.2 V. This voltage is negligible. Thus, a true output signal O is produced at the terminal 5 with the logic low level of a substantial GNE level. The logic low level of the intermediate signal P is supplied to the transistor MP11 to turn the same ON. On the other hand, the transistor MN11 is supplied at the source with the (V DD - V TN ) level. The gate of the transistor MN11 is supplied with V DD level, and hence the voltage between the gate and source thereof is equal to V TN . Since a so-called back gate bias effect occurs in the transistor MN11, the transistor MN11 is biased by a voltage slightly smaller than the threshold voltage thereof. The transistor MN11 is thereby in the cut-off state, so that the potential at the terminal 6 is changed up to the V DD level. Thus, a complementary output signal O is produced at the terminal 6 with the logic high level of the V DD level. When the intermediate signals P and P is changed to the logic high and low level, respectively, the true and complementary signals O and O are changed to V DD level and substantial GND level, respectively. Thus, the EX-OR gate circuit shown in Fig. 1 performs an exclusive OR logic operation on two data signals IA and IB at a high speed and with a low power and produces true and complementary output signals O and O each having a logic amplitude between V DD level and substantially GND level. In the gate circuit shown in Fig. 1, when the intermediate signal P is at the logic low level, the transistor MP12 is not in the cut-off state, so described hereinbefore. This reason, a slight current flows from the V DD terminal 9 to the GND terminal 10 through the transistors MP12, MN12, MN18 (or MN19) and MN14 (or MN16). In case where the signal P is at the low level, a slight current flows through the transistors MP11 and MN11 to the GND terminal 10. For this reason, the power consumption of Fig. 1 gate circuit is slightly larger than that of a C-MOS logic circuit. In order to further reduce the power consumption, a gate circuit shown as a second embodiment of the present invention in Fig. 2 includes a power reduction circuit 20. This gate circuit is also a 2-input EX-OR gate circuit, and hence the same constituents as those shown in Fig. 1 are denoted by the same reference numerals and symbols to omit the further description thereof. The power reduction circuit 20 includes an enhancement P-channel MOS transistor MP23 connected between the terminal 11 and a node N3 and having a gate connected to the terminal 12, an enhancement P-channel MOS transistor MP24 connected between the terminal 12 and the node N3 and having a gate connected to the terminal 11, and an enhancement P-channel MOS transistor MP25 connected between the node N3 and the V DD terminal 9 and having a gate connected to a control terminal 21 which is in turn supplied with a power reduction control signal PD. When this control signal PD takes the V DD level, the transistor MP25 is turned OFF to disconnect the node N3 from the V DD terminal 9. Accordingly, the logic circuit in this case performs the same operation as that of Fig. 1. When the control signal PD takes the GND level, the transistor MP25 is turned ON to supply the V DD level to the node N3. Assuming that the signal P is at the logic low level at this time, the transistor MP23 is turned ON. The logic high level of the signal P is thereby changed from the (V DD - V TN ) level to the V DD level. As a result, the transistor MP12 is changed from the high impedance state to the cut-off state. A current no longer flows through the transistor MP12. Similarly, in case of the signal P being at the logic low level, the transistor MP24 is turned ON to change the transistor MP11 to the cut-off state. No power is thereby consumed. By supplying the control signal PD of the GND level to the terminal 21 during the stand-by period of the logic gate and/or during the steady period in the logic level of the input data signals IA and IB, the power consumption of gate circuit shown in Fig. 2 is relatively reduced. Turning to Fig. 3, there is shown a 3-input EX-OR gate circuit as a third embodiment of the present invention, in which the same constituents as those shown in Fig. 1 are denoted the same reference numerals and symbols to omit the further description thereof. In this gate circuit, the transistors MN17 and MN20 are connected in common at a node N4 and an enhancement N-channel MOS transistor MN31 is connected between this node N4 and the terminal 11. The transistors MN18 and MN19 are connected in common at a node N5 and an enhancement N-channel MOS transistor MN34 is connected between this node N5 and the terminal 11. Enhancement N-channel MOS transistors MN32 and MN33 are further provided and connected between the node N4 and the terminal 12 and between the node N5 and the terminal 12, respectively. A third input data signal IC, whose logic high level is the V DD level and whose logic low level is the GND level, is supplied to a third true input terminal 30 which is in turn connected in common to the gates of the transistors MN31 and MN33. An inverted data signal IC of the signal IC is supplied to a third complementary input terminal 31 which is in turn connected in common to the gates of the transistors MN32 and MN34. The remaining circuit construction is the same as that shown in Fig. 1. Accordingly, the gate circuit shown in Fig. 3 performs an exclusive OR logic operation on three input data signals IA, IB and IC at a high speed with a low power and produces true and complementary output signals O and O each having a logic amplitude between the V DD level and the substantial GND level. The power reduction circuit 20 shown in Fig. 2 can be incorporated into the 3-input EX-OR gate circuit shown in Fig. 3. Such a gate circuit is shown in Fig. 4 as a fourth embodiment of the present invention. Turning to Fig. 5, there is shown a gate circuit according to a fifth embodiment of the present invention, in which the same constituents as those shown in the previous drawings are indicated by the same reference numerals and symbols to omit further description thereof. The logic operation circuit 7 disclosed therein consists of twelve MOS transistors MN51 to MN62, all of which are of an enhancement N-channel type. These transistors MN51 to MN62 are connected and supplied selectively with data signals IA to IC as shown in the drawing. Therefore, the circuit 7 performs a logic operation of IA x (IB + IC) on three input data signals IA, IB and IC. The power reduction circuit 20 shown in Fig. 2 can be incorporated into the gate circuit shown in Fig. 5. The present invention is not limited to the above embodiments, but may be changed and modified without departing from the scope as defined in the appended claims.

Claims: An output circuit (8) comprising a power terminal (9) supplied with a power potential (V DD ) with respect to a reference potential (GND), first and second input terminals (11, 12), first and second output terminals (6, 5), a first insulated gate transistor (MP11) of one channel type having a source connected to said power terminal (9), a drain connected to said first output terminal (6) and a gate connected to said second input terminal (12), a second insulated gate transistor (MN11) of an opposite channel type having a source connected to said first input terminal (11), a drain connected to said first output terminal (6) and a gate connected to said power terminal (9), a third insulated gate transistor (MP12) of said one channel type having a source connected to said power terminal (9), a drain connected to said second output terminal (5) and a gate connected to said first input terminal (11), a fourth insulated gate transistor (MN12) of said opposite channel type having a source connected to said second input terminal (12), a drain connected to said second output terminal (5) and a gate connected to said power terminal (9), means for supplying a binary data signal to said first input terminal (11), and means for supplying an inverted signal of said data signal to said second input terminal (12), said binary data signal and inverted signal having levels in a range limited by said power potential and said reference potential such as to cause widened complementary logical transitions at said output terminals (6,5). An output circuit as claimed in claim 1, characterized in that said first and third insulated gate transistors (MP11, MP12) are of a P-channel type and said second and fourth insulated gate transistors (MN11, MN12) are of an N-channel type. An output circuit as claimed in claim 1 , characterized by further comprising a power reduction circuit (20) which includes a fifth insulated gate transistor (MP23) of said one channel type connected between said first input terminal (11) and a node (N3) and having a gate connected to said second input terminal (12), a sixth insulated gate transistor (MP24) of said one channel type connected between said second input terminal and said node and having a gate connected to said first input terminal, and a seventh insulated gate transistor (MP25) of said one channel type connected between said node and said power terminal (9) and having a gate supplied with a power control signal (PD). An output circuit as claimed in claim 3, characterized in that said power control signal (PD) turns said seventh insulated gate transistor (MP25) ON during a stand-by period of said output circuit and/or a steady period in logic levels at said first and second input terminals.

Inventors: AOKI YASUSHI, AOKI, YASUSHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: H03K19
IPC codes: H03K19