Solid-state image pickup device having shared output line for photoelectric conversion voltage

Abstract: There is disclosed a solid-state image pickup device formed by integrating, on a semiconductor substrate (1), a plurality of photosensitive pixels (PE₁ ... PE n ) producing signal charges corresponding to a quantity of an incident light, a shift register (2) responsive to a pulse input from the external to generate a predetermined control pulse, a plurality of charge/voltage conversion elements (A₁ ...A n ) provided in correspondence with the plurality of photo­ sensitive pixels, respectively, and an element-shared output line (5) for the external output of the plurality of charge/voltage conversion elements. The charge/voltage conversion elements (A₁ ... A n ) are operative to respond to a predetermined control pulse generated from the shift register (2) to detect quantities of integration of signal charges generated from corresponding photosensitive pixels (PE₁ ... PE n ) and zero reference levels of the quantitiy of integration to convert these detected values into voltages to sequentially output them to the element-­ shared output line (5).

Description: BACKGROUND OF THE INVENTION This invention relates to a solid-state image pickup device. For the linear image sensor, CCD linear image sensors, image sensors of the contact type using amorphous silicon and the like, have been conventionally used. In the case of the above-described CCD sensors, since readout of signals is carried out typically using a CCD analog shift register, they had the problem that the manufacturing process was complicated and they were expensive. On the other hand, in the case of image sensors of the contact type using amorphous silicon, since an output is obtained in the form of a light current, they had the problems that it was required to externally provide a suitable integrator, and that a sufficient signal-to-noise (SN) ratio could not be obtained. EP-A-0 260 954 shows a device comprising shift registers for generating control signals, charge voltage conversion elements and an element-shared output line, but two capacitors are required, together with switching circuits for each pixel to separate reference signals and sensor signals. EP-A-0 254 497 shows a device including source-follower type charge/voltage conversion circuits. SUMMARY OF THE INVENTION This invention has been made in view of the above-mentioned problems, and its object is to provide a solid-state image pickup device which has a simple manufacturing process, and which is capable of providing a sufficient SN ratio. According to the present invention, there is provided a solid-state image pickup device as set out in claim 1. In accordance with the solid-state image pickup device according to this invention thus constructed, since readout of signal charges is conducted in accordance with a predetermined control pulse, e.g., the formation of multilayer polysiiicon becomes unnecessary, so the manufacturing process is simplified, unlike the case of conventional CCD sensors. Moreover, this device adopts such a scheme to detect quantities of integration of signal charges and zero reference levels of the quantity of integration by the charge/voltage conversion elements to convert the values detected to corresponding voltage values, to therefore sequentially output them to the outside through the shared output line. This permits execution of processing, e.g., correlative double sampling, etc., resulting in a sufficient SN ratio. As just described above, in accordance with the solid-state image pickup device according to this invention, the manufacturing process is simple and a sufficient SN ratio can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIG. 1 is a block diagram showing the schematic configuration of a solid-state image pickup device but not showing all the features of this invention; FIG. 2 is a circuit diagram showing the configuration of a shift register used in the solid-state image pickup device according to a first arrangement, not including all the features of this invention; FIG. 3 is a timing chart for explaining the operation of the shift register shown in FIG. 2; FIG. 4 is a circuit diagram showing the circuit configuration of a charge/voltage conversion element used in the solid-state image pickup device according to the arrangement of figure 2. FIG. 5 is a schematic diagram showing the structure of a photosensitive pixel used in the solid-state image pickup device according to figure 2; FIG. 6 is a timing chart for explaining the operation of the charge/voltage conversion element used in the solid-state image pickup device according to figure 2; FIG. 7 is a circuit diagram showing the whole configutation of a solid-state image pickup device according to an embodiment of this invention; FIG. 8 is a circuit diagram showing the detailed circuitry of a charge/voltage conversion element used in the solid-state image pickup device shown in FIG. 7; and FIG. 9 is a timing chart showing pulse waveforms of each node shown in FIG. 8 for explaining the operation of the image pickup device according to the embodiment of this invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of this invention will be described with reference to the attached drawings. Referring to FIG. 1, there is shown a fundamental configuration of a solid-state image pickup device. On a semiconductor substrate designated by reference numeral 1, a shift register 2, photosensitive pixels PE 1 , ..., PE n , charge/voltage conversion elements A 1 , ..., A n , a current source 4, and an element-shared output line 5 are integrated. The semiconductor substrate 1 is provided with terminals 8a, 8b, 8c, 8d, 8e, 8f and 8g. To the shift register 2, drive pulses  1 and  2 are steadily applied from the external through terminals 8a and 8b, respectively. Furthermore, a start pulse  * is applied to the shift register 2 through terminal 8c, and a d.c. voltage (e.g., 5V or 12V) is applied to the shift register 2 and to charge/voltage conversion elements A 1 , ..., A n through terminal 8d. Furthermore, a reset pulse  R input through terminal 8e is applied to charge/voltage conversion elements A 1 , ..., A n . The terminal designated by reference numeral 8f serves as a ground terminal. On the basis of the fundamental configuration as mentioned above, a first arrangement is explained in accordance with the detailed circuitry and function of the image pickup device shown in FIGS. 2 to 6. At first, the shift register 2 responds to drive pulses  1 and  2 and start pulse  * to generate control pulses  Si and  Bi (i = 1, 2, ..., n) to output them to a charge/voltage conversion element A i . An actual example of the shift register 2 constructed so that it generates control pulses  Si and  Bi (i = 1, 2, ..., n) on the basis of drive pulses  1 and  2 and start pulse  * in this way is shown in FIG. 2. As shown in this figure, the shift register 2 is composed of a starter circuit SR 0 and a number n of control pulse generation circuits SR 1 , ..., SR n . More particularly, the starter circuit SR 0 is composed of four MOS transistors (hereinafter simply referred to as transistors, respectively) M 01 , ..., M 04 , and one capacitor C 0 , and the control pulse generation circuit SR i (i = 1, 2, ..., n) is each composed of eight MOS transistors, for example, transistors M 11 , ..., M 18 and two capacitors C 11 and C 12 in the circuit SR 1 in FIG. 2. It is to be noted that an indication of four MOS transistors M 25 , M 26 , M 27 and M 28 and capacitor C 22 in the control pulse generation circuit SR 2 is omitted. The operation of the starter circuit SR 0 and the control pulse generation circuit SR i will now be described with reference to FIG. 3. It is assumed that when drive pulses  1 and  2 shown in FIG. 3 are applied to the shift register 2, a start pulse  * is applied at time of t 1 . A d.c. voltage of 5V is applied to the source side of the MOS transistor M 01 of the starter circuit SR 0 through the terminal 8d shown in FIG. 1. When start pulse  * is applied to the gate of the MOS transistor M 01 at time t 1 , a potential  a on the point a on the drain side of the transistor M 01 is raised from low level to reach a value less than 5V. When the start pulse  * shifts from high level to low level at time t 2 , the potential  a on the point a remains at a value less than 5V by the influence of the capacitor C 0 . This potential  a is applied to the gate of the transistor M 02 . However, since the drive pulse  2 is at low level, the potential  b on the point b is also at low level. Such a state is continued until the drive pulse  2 shifts from low to high level at time t 4 . When the drive pulse  2 shifts from low to high level at time t 4 , the potential  b on the point b is raised. Accordingly, the potential  a a on the point is raised by the step-up action to reach a value larger than 5V as shown in FIG. 3. Such a state is continued until time t 5 . Since the drive pulse  2 shifts from high to low level at time t 5 , the potential  b on the point b also shifts from high to low level. Accordingly, the potential  a on the point a is also lowered from a value larger than 5V to a value lower than 5V. On the other hand, a d.c. voltage of 5V is applied through terminal 8d shown in FIG. 1 to the source side of the transistor M 11 of the control pulse generation circuit SR 1 . Since the potential  b is applied to the gate of the transistor M 11 , a potential  c on the point c on the drain side of the transistor M 11 is raised from low level to a value lower than 5V in the same manner as in the case of the potential  a on the point a of the start circuit SR 0 . Such a state is continued until the time t 6 when the drive pulse applied to the source side of the transistor M 12 shifts from low to high level. Since the potential  c is applied to the gate of the transistor M 12 and the drive pulse  1 shifts from low to high level at time t 6 , a potential  d on the point d is raised. Accordingly, the potential  c on the point c is also raised by the step-up action to reach a value larger than 5V. Such a state is continued until t 7 when the drive pulse  1 shifts from high to low level. Since the potential  d shifts from low to high level at time t 6 , the gate of the transistor M 03 of the start circuit SR 0 to which the potential  d is applied is opened at time t 6 . As a result, the potential  a on the point a shifts to low level. When the drive pulse  1 shifts from high to low level at time t 7 , the potential  d on the point d also shifts from high to low level. Accordingly, the potential  c on the point c is also lowered from a value larger than 5V to a value smaller than 5V. On the other hand, a d.c. voltage of 5V is applied through the terminal 8d shown in FIG. 1 to the source side of the transistor M 15 of the control pulse generation circuit SR 1 , and the potential  d is applied to the gate of the transistor M 15 . As a result, a potential  e on the point e on the drain side of the transistor M 15 is raised from low level to a value larger than 5V. Such a state is continued until t 8 when the drive pulse  2 applied to the source side of the transistor M 16 shifts from low to high level. Since the potential  e is applied to the gate of the transistor M 16 and the drive pulse  2 shifts from low to high level at time t 8 , a potential  f on the point f is raised. Accordingly, the potential  e on the point e is also raised by the step-up action. Such a state is continued until time t 9 when the drive pulse  2 shifts from high to low level. Since the potential  f on the point f shifts from low to high level at time t 8 , the gate of the transistor M 13 to which the potential  f is applied is opened at time t 8 . As a result, the potential  c on the point c shifts to low level. Then, these potentials  c and  f are taken out from the control pulse generation circuit SR 1 as control pulses  S1 and  B1 , respectively. These control pulses thus taken out, are output to the voltage/charge conversion element A 1 . The potential  f is applied from the control pulse generation circuit SR 1 to the gate of the transistor M 21 of the control pulse generation circuit SR 2 . Thus, control pulses  S2 and  B2 are taken out from the control pulse generation circuit SR 2 in the same manner as in the case of the control pulse generation circuit SR 1 . These pulses thus taken out are output to the charge/voltage conversion element A 2 . By repeatedly carrying out such an operation in sequence, control pulses  Si and  Bi are taken out from a control pulse generation circuit SR i (i = 1, ..., n). These control pulses thus taken out, are output to the corresponding charge/voltage conversion element A i . It is to be noted that the control pulse  Si is a trinary pulse as shown in FIG. 3, and its maximum level is larger than the power supply voltage (5V). Referring again to FIG. 1, the charge/voltage conversion element A i (i = 1, ..., n) responds to control pulse  Si and  Bi and reset pulse  R applied through terminal 8e to detect a quantity of integration of signal charges generated by the photosensitive pixel PE i and a zero reference level of the quantity of integration to convert these values detected to a voltage, thus to specifically output the voltage to the element-shared output line 5. The output V out of the charge/voltage conversion element A i specifically output to the common line 5 is output to the external through the terminal 8g. An actual example of such a charge/voltage conversion element A i is shown in FIG. 4. The circuit configuration shown in this figure includes a capacitor 11 for storing signal charges generated in a photosensitive pixel (e.g., a photodiode) PE i , a reset transistor 12, MOS transistors (hereinafter simply referred to as transistors) 14 to 19, a current source 20, a driver gate 21, and a step-up capacitor 24. As shown in FIG. 4, the control pulse  Si is applied to the gates of transistors 15 and 18, and the control pulse  Bi is applied to the gate of the transistor 17. In addition, the reset pulse  R is applied to the source of the transistor 16. It is to be noted that the photodiode PE i is constituted, e.g., as shown in FIG. 5, by forming a P-well on an N type semiconductor substrate and forming an N region and a P + region on the side of the surface of the P-well. In FIG. 5, LOCOS represents a selective oxidation structure of the silicon substrate by a silicon nitride film and is an abbreviation of localized oxidation of silicon. Further, two n + regions are separately formed on the side of the surface of the P-well, and one n + region thereof is in contact with the n region. The n + region and an electrode formed between two n + regions constitute the above-mentioned reset transistor 12. Next, the operation of the device according to the first embodiment will be explained with reference to FIG. 4 and a characteristics diagram shown in FIG. 6. A d.c. voltage of 5V is applied to the source and the gate of the transistor 14 through the terminal 8d shown in FIG. 1 (see FIG. 4). When the control pulse  Si is applied to the gate of the transistor 15 at time T 1 , a potential  α on the point α shown in FIG. 4 is slightly raised from low level to reach a predetermined level (see FIG. 6). Since the control pulse  Si shifts to high level at time T 2 , the potential  α shifts to a standby level. Since the reset pulse  R shifts from low to high level at time T 3 , the potential  α on the point α is raised by the step-up action to reach a predetermined level (hereinafter referred to as a reset level). Since the reset pulse  R shifts from high to low level at time T 4 , the potential  α shifts to the standby level for a second time. This standby level is continued until T 5 . As stated above, the pulse  RSi (=  α ) applied to the gate of the reset transistor 12 becomes a quarternary pulse. For a time period during which the pulse  RSi is at standby level, the capacitor 11 holds signal charges without being reset by the reset transistor 12. The capacitor 11 is reset at time T 3 when the pulse  RSi shifts to reset level. This reset state is continued until T 4 . Thereafter, the potential  β on the point β shown in FIG. 4 is lowered accordingly as signal charges from the photodiode PE i are stored into the capacitor 11. When the control pulse  Si is at the maximum level (from T 2 to T 5 ), the transistor 19 becomes active as a source-follower circuit. For a time period during which the pulse  RSi is at the standby level and the control pulse  Si is at the maximum level (from T 2 to T 3 ), a potential  γ corresponding to a quantity of signal charges stored in the capacitor 11 after the last reset operation until T 2 is detected at the source follower circuit. For a time period during which the pulse  RSi is at reset level and the control pulse  Si is at the maximum level (from t 3 to t 4 ), the potential  β across the capacitor 11 is reset. Furthermore, for a time period during which the pulse  RSi is at the standby level and the control pulse  Si is at the maximum level (from T 4 to T 5 ), a potential across the capacitor 11 exists where there is little signal charge at the time when signal charges flows thereinto from the photodiode PE i after reset. The level at this time can be considered as a zero reference for signal charges. The potential  γ thus detected is amplified by the driver gate 21 and is output to the shared output line 5. It is to be noted that the potential  γ on the point γ is equal to zero before the control pulse  Si is applied to the gate of the transistor 18, and this potential  γ is applied to the driver gate 21, the shared output line 5 is not affected by the potential on the point γ. Furthermore, when the potential  γ on the point or of the charge/voltage conversion element A i is not equal to zero, i.e., the control pulse  Si is not at the low level, a control pulse  sj applied to other (n-l) charge/voltage conversion elements A j (j ≠ i) is at low level. As a result, outputs from other (n-l) charge/voltage conversion elements A j will be cut off. Accordingly, readout of potentials, i.e., signal charges can be sequentially carried out on the shared output line 5. As just described above, in accordance with the first arrangement, since readout of signal charges is carried out in accordance with a predetermined control pulse, e.g., formation of a multilayer polysilicon becomes unnecessary, resulting in a simplified manufacturing process, unlike the case of the conventional CCD sensors. Furthermore, quantities of integration of signal charges and zero reference levels of the quantity of integration are converted to voltage values and are sequentially output to the external through the element-shared output line 5. Thus, processing e.g., correlative double sampling, etc. can be performed, resulting in a sufficient SN ratio. In addition, the solid-state image pickup device can be driven by a low voltage of 5V. Though the solid-state image pickup device according to the first arrangement comprises the charge/voltage conversion element having the circuitry shown in FIG. 4 and driven by the control pulse of 5V, the device of the present invention is realised in an embodiment having the configuration and function each shown in FIGS. 7 to 9. FIG. 7 shows the entire configuration of a solid-state image pickup device according to the invention. As elements having the same numerals of FIGS. 1, 4 and 5 are the same or equivalent elements thereof, duplicate explanation will be omitted. The embodiment is different from the first arrangement having the conversion element shown in FIG. 4 at two points hereinafter. The first is when the image pickup device is formed in a chip, the capacitors for raising the voltage occupy large areas within a chip. On the contrary, the conversion element according to the embodiment does not have capacitors for raising the voltage, and so the chip of a device can be integrated higher. Next, though the concept was already created in the first arrangement, it is possible for the embodiment to form a solid-state image sensor into a multichip circuit in which a plurality of chips are interconnected with each other after each image pickup device is completed on the semiconductor substrate 1. Therefore, a chip-shared output line 9 is provided for interconnecting the chips in each chip. However, a conversion element A i of the embodiment is driven by a 12V control voltage different to the 5V of the first arrangement. At first, the entire configuration of the image pickup device according to the embodiment is described with reference to FIG. 7. The chip-shared line 9 for interconnecting chips and achieving a multichip, has in both ends an input terminal 8g 1 having a current source 6, and an output terminal 8g 2 to which the element-shared output line 5 is connected through a buffer 7. The buffer 7 is provided for output voltage of the element-shared line 5 to the chip-shared line 9 having the low impedance. The current source 6 and buffer 7 form a source follower circuit. A pixel PE i (i = 1, 2, ..., n) comprised of diodes and the like is connected to a corresponding charge/voltage conversion element A i (i = 1, 2, ..., n). The element A i functions for potential detection and output of the pixel PE i . Namely, the electric charges of the pixel PE i flowing in a capacitor 36 (CP i ) are charged therein and then, two-stage source followers read out the change of potential between both ends of the capacitor 36 (CP i ). After reading out the potential change, a reset pulse  R impressed from the outside resets and equalizes the potential of both ends of the capacitor 36 (CP i ) to an external power source ⊕ by a reset transistor (35). The two-stage source followers comprise a first stage source follower 40 which is controlled in operation by a set pulse  Si , and a second stage source follower which is controlled by the first stage source follower 40. The second stage source follower concretely comprises the current source 4 and driver 31. A numeral 32 denotes a gate for selecting the conversion element and then, while the gate 32 opens by the set pulse  Si and output of the driver 31, the conversion element having the open gate 32 outputs a converted voltage to the element-shared output line 5. In the embodiment, a shift register comprises a first shift register 2A for generating a set pulse  Si , and a second shift register 23 for generating a clear pulse  Ci which is made in each chip on the basis of the reset pulse  R supplied from the outside. The external power source ⊕ is supplied the terminal 8d of the chip in the same manner as in the first arrangement. Next, there will be explained the detailed configuration of the charge/voltage conversion element A i formed on the semiconductor substrate 1 corresponding to the pixel PE i with reference to FIG. 8. In the figure, the first stage source follower 40 is designated in detail. In FIG. 8, the first stage source follower 40 comprises MOS (metal oxide semiconductor) transistors 25 and 26 forming a voltage divider circuit 27 which generates a load-bias voltage in response to the set pulse  Si , a driver 29 to which the voltage of the capacitor 36 is impressed, and a current source 30 to which the voltage divided by the divider 27 is impressed. The operation of the image pickup device according to the embodiment is described in detail with reference to FIG. 9 which shows pulse waveforms of nodes δ, ε and  of the conversion element A i and output waveform of node λ of the element-shared output line 5 in addition to FIG. 8. When the first stage source follower 40 receives the set pulse  Si generated in the first shift register 2A, the voltage divider circuit 27 generates a load-bias voltage. The load-bias voltage which appears at the node δ synchronous with the set pulse  Si supply, as shown in FIG. 9, is output between times T 2 to T 5 with 3 to 5V against 12V of set pulse  Si as the driving voltage. Namely, the voltage of the node δ raises at the time T 2 and falls at the time T 5 synchronous with the set pulse  Si . At this time, the potential difference Dp occurs at the node ε according to quantity of light sensed by the pixel PE i before and after the clear pulse  Ci generated in each element A i in response to the reset pulse  R . The output of the first stage source follower 40 is determined by both waveforms of the nodes δ and ε. Accordingly, the pulse waveform of the node  between the driver 29 and current source 30, as shown in FIG. 9, falls gradually until time T 2 and abruptly at time T 2 . At time T 3 , the voltage of the node  raises with an amount of the potential difference Dp corresponding to the quantity of light sensed by pixel PE i , and falls at time T 4 . After the waveform of the node  falls gradually between times T 4 and T 5 , raises again at the time T 5 , and falls gradually after the time T 5 . Thus, the waveform of node  is controlled in the offset and impedance on the basis of waveforms of the nodes δ and ε. The output of the first stage source follower 40 mentioned above, namely the waveform of the node , is output to the element-shared line 5 through the driver 31 and selection gate 32. The element-shared line 5 is sequentially supplied with the outputs of each element A i , that is, elements A 1 to A n . Accordingly, the waveform of node  between times T 2 to T 5 is repeatedly output to the node λ of the shared line 5 every time the driving pulse of the shift register 2 is raised, so that output pulses can be read out in response to the quantity of light sensed by the pixel PE i . As described above, the outputs of each element A i (i = 1, 2, ..., n) are output to the node λ in time series, so that the output of the element A i supplied the set pulse  Si can be sequentially (in time series) read out between times T 2 to T 5 . In the embodiment, times T 1 and T 6 which are the adjacent raising times of the driving pulse  2 , do not relate directly to the output pulses of the node λ because the element A i of the embodiment does not operate for raising the voltage. There are some following effects peculiar to the embodiment mentioned above. At first, as the chip-shared line 9 for successively connecting chips one by one is formed in each chip, it is possible to form a multichip image pickup device in which a plurality of single chips are successively interconnected from the first to the n-th chips in the manner that an input terminal 8g 1 of the first chip is bonded to the substrate 1, an output terminal 8g 2 of the first chip is connected to an input terminal 8g 1 of the second chip, and an output terminal 8g 2 of the n-th chip is connected to a terminal of a processing unit. Next, as the capacitor for raising voltage is eliminated from a chip, it is possible for a chip to have large-scale integration. At the same time, as an impedance of a chip is reduced, it is possible to perform the converting operation rapidly in each chip. As understood from the foregoing description, it is needless to say that the solid-state image pickup device according to the embodiment also provides the same advantages as those with the above-described first arragement.

Claims: A solid-state image pickup device comprising integrated on a semiconductor substrate (1): a plurality of photosensitive pixels (PE 1 ...PE n ) producing signal charges corresponding to a quantity of incident light; a shift register (2A, 2B) responsive to external control pulse inputs ( * ,  1 ,  2 ,  R ) to generate predetermined set and reset pulses ( Si ,  Ci ); a plurality of charge/voltage conversion elements (A 1 ...A n ) provided in correspondance with said plurality of photosensitive pixels, respectively, to detect and read out said signal charges and receiving said predetermined set and reset pulses sequentially; a common output line (5, 9) for the readout pulses of said plurality of charge/voltage conversion elements; wherein each of said charge/voltage conversion elements comprises: a charge storage capacitor (36) to store said signal charges produced by the corresponding photosensitive pixel; a two-stage source follower (40; 4, 31) to read out a change of potential of said capacitor corresponding to a signal charge, the first stage source follower (40) being connected to said capacitor and controlled by said predetermined set pulses, and the second stage source follower (4, 31) being connected to said common output line and controlled by said first stage follower; a selection gate (32) to select the corresponding charge/voltage conversion element in response to said predetermined set pulses supplied from said shift register; and a reset gate (35) to reset the capacitor potential to an external voltage level (+) in response to said predetermined reset pulses supplied from said shift register; wherein said predetermined set and reset pulses are adapted to control the charge/voltage conversion elements so that each readout pulse of a charge/voltage conversion element comprises a signal voltage level corresponding to a signal charge stored on said capacitor and a reference voltage level derived from said capacitor after resetting said capacitor; and wherein said common output line comprises: an element-shared output line (5) to which said second stage source follower is connected to sequentially take out the readout pulses of each of said charge/voltage conversion elements, and a chip-shared output line (9) to which said element-shared output line is connected through a buffer (7) forming a source follower with a current source (6) connected to said chip-shared output line. A solid-state image pickup device as set forth in claim 1, wherein said second stage source follower (4, 31) has a driver MOS (31) to control the output of the charges within the individual conversion element (A i ) to said element-shared output line (5) in response to the output of said first stage source follower (40), and a further current source (4) connected to said element-shared output line. A solid-state image pickup device as set forth in claim 2, wherein said two stage source follower comprises a first driver gate (29) to receive the potential of said charge storage capacitor (36), a current source (30) connected in series between one end of said first driver gate and a ground terminal, and said second driver gate (31) having one end connected to one end of said selection gate (32) the other end of which being connected to said element-shared output line (5), the connection point of said first driver gate and said current source being connected to said second driver gate. A solid-state image pickup device as set forth in claim 2, wherein said further current source (4) is integrated on said semiconductor substrate. A solid-state image pickup device as set forth in claim 3, wherein said first stage source follower comprises a voltage divider circuit (27) to divide the voltage of a set pulse as said first control pulse and to generate a load bias voltage to be supplied to a load, a metal oxide semiconductor (MOS) element as said load supplied with said bias voltage output from said divider circuit and forming said current source (30) connected in series between one end of said first driver gate (29) and said ground terminal. A multichip solid-state image pickup device comprising a plurality of solid-state image pickup devices integrated on a plurality of separate chips as set forth in any one of the preceding claims, wherein said chip-shared output line (9) successively interconnects said plurality of chips (1) with each other.

Inventors: GOTO HIROSHIGE, GOTO, HIROSHIGE, GOTO, HIROSHIGE 239, PARK-HEIGHTS-TSURUMI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H01L27
IPC codes: H04N3, H04N1, H04N5, H01L27