SEMICONDUCTOR THIN FILM AND PROCESS FOR FABRICATING THE SAME

Abstract: An InP semiconductor thin film is formed by a process in which an amorphous GaAs buffer layer (2) having a good surface flatness, and then an amorphous InP buffer layer (3) having a good surface flatness are formed on an Si substrate (1), and then an InP monocrystalline thin film (4) is grown on the InP buffer layer (3). GaAs has a lattice constant intermediate between Si used as the substrate and InP, so the lattice mismatch is reduced.

Description: The present invention relates to an indium phosphide (InP) semiconductor thin film and process of fabricating the same, and more particularly a process of fabricating a semiconductor thin film comprising an InP monocrystalline layer on an Si substrate used for opto-electronic integrated circuits (OEICs), optical devices, and the like. In the prior-art process for fabricating an InP semiconductor thin film, an InP monocrystalline thin film is formed directly on an Si substrate. In another prior-art process, an InP buffer layer is formed on an Si substrate, and then an InP semiconductor thin film is formed on the InP buffer layer. Figure 2 shows an InP semiconductor thin film formed in the latter process. In the Figure, reference numeral 1 denotes an Si substrate having a surface within a (100) orientation. Reference numeral 3 denotes an InP buffer layer. Reference numeral 4 denotes an InP monocrystalline layer. This InP semiconductor thin film is formed by first using reduced-pressure metal organic chemical vapor deposition (MOCVD), and triethyl-indium (TEI) and phosphine (PH₃) as raw materials, to form the InP buffer layer 3 on the Si substrate 1 at a temperature of 380°C, and then crystal-growing InP monocrystalline thin film 4 on the InP buffer layer 3 at 600°C. As this process achieves InP crystal growth in two steps, this process is called two-step growth method. See for example Ohyobutsuri Gakkai Gakujutsu Koenkai Yokoshu (Preprints of the Symposium of the Japan Society of Applied Physics) 1986 (Autumn), page 706, No. 30p-D-6. The Inp monocrystalline thin film 4 formed by the two-step crystal-growth method has an improved surface state than an InP monocrystalline thin film obtained by the single-step growth method in which an InP monocrystalline film is directly formed on an Si substrate. However, the surface of the resultant InP semiconductor thin film obtained by the prior-art process is not flat, nor specular (mirror-like), and the film is therefore not satisfactory for practical use. This is considered to be due to the fact that InP having a lattice constant about 8% larger than that of Si is directly crystal-grown on the Si substrate, and crystal defects due to lattice mismatch occur. In EP-A-0291346 which belongs to the state of the art according to Article 54(3) EPC there is described a laminated semiconductor structure comprising an Si substrate, a compound GaAs layer composed of a GaAs layer formed at low temperature and a GaAs layer formed at high temperature, a compound InP layer composed of an InP layer formed at low temperature and an InP layer formed at high temperature, a compound semiconductor layer composed of a plurality of alternate layers consisting of InAsxP 1-x (0 < x < 1) thin layers and InP thin layers and a compound InP layer, in that order. In US-A-4561916 there is described a method of forming a compound semiconductor comprising an Si substrate on which is formed a layer of a Group III-V compound semiconductor and on which in turn is formed a compound layer comprising alternating layers of: (1) the same Group III-V compound semiconductor as in the first-mentioned layer and (2) a Group III-V compound semiconductor having a lattice constant approximating that of the compound semiconductor in the first alternate layer. Finally a layer of a desired Group III-V compound semiconductor is grown on the alternating layers. The present invention seeks to eliminate the problem of crystal defects and surface roughness due to the crystal mismatch in the InP semiconductor thin film formed by the prior-art method. The present invention also seeks to provide a process of fabricating an InP semiconductor thin film having an InP monocrystalline thin film with an improved crystal quality. According to a first aspect of the invention, there is provided an InP semiconductor thin film comprising: an Si substrate; an amporphous GaAs buffer layer formed on the Si substrate; an amporphous InP buffer layer formed on the GaAs buffer layer; and an InP monocrystalline thin film formed on the InP buffer layer. According to a second aspect of the invention, there is provided a process for fabricating an InP semiconductor thin film, said process comprising the steps of; providing an Si substrate; performing heat-treatment of the Si substrate; forming an amorphous GaAs buffer layer having a good surface flatness on the Si substrate; forming an amorphous InP buffer layer having a good surface flatness on the GaAs buffer layer; and growing an InP monocrystalline thin film on the InP buffer layer. The GaAs used for InP semiconductor thin film in the present invention has a lattice constant intermediate between the lattice constants of Si used as the substrate and of InP. Distortion of the lattice of the InP monocrystalline thin film is therefore smaller than if the InP moncrystalline thin film is formed directly on the Si substrate or grown on an InP buffer layer which in turn is formed on an Si substrate. Incidentally, another method for alleviating lattice mismatch can be contemplated in which a GaAs buffer layer, a GaAs monocrystalline thin film are stacked in this order on an Si substrate. But, according to the invention, the object is accomplished by simply inserting a GaAs layer and without substantially increasing the number of process steps. In order that the invention may be better understood, some embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings in which:- Figure 1 is a sectional view for explaining the structure of an InP semiconductor thin film according to the invention; Figure 2 is a diagram for explaining the structure of a prior-art InP semiconductor thin film; and Figure 3 is a diagram for showing an example of temperature-time program in the process of the invention. Figure 1 is a sectional view for explaining an InP semiconductor thin film according to the invention. In the figure, reference numeral 1 denotes an Si substrate having a surface with (100) orientation. Reference numeral 2 denotes a GaAs buffer layer 2. Reference numeral 3 denotes an InP buffer layer. Reference numeral 4 denotes an InP monocrystalline thin film. The InP semiconductor thin film according to the invention has a structure as shown in Figure 1, in which the GaAs buffer layer 2, the InP buffer layer 3, and the InP monocrystalline thin film 4 are stacked in this order on the Si substrate 1. The InP semiconductor thin film shown in Figure 1 is fabricated by a process in which the Si substrate 1 is cleaned, the amorphous GaAs buffer layer 2 having a good surface flatness and amorphous InP buffer layer 3 having a good surface flatness are successively formed on the Si substrate 1, and then the InP monocrystalline thin film 4 is grown on the InP buffer layer. The above-mentioned reduced-pressure MOCVD is preferably used for the formation of the layers 2 to 4. The respective process steps will now be described. First, a Si substrate is provided. The Si substrate should have a surface with an orientation (100). The amorphous GaAs buffer layer 2 having a good surface flatness is formed on the Si substrate 1. The amorphous GaAs buffer layer 2 having a good surface flatness can be formed, for example by the method described in the following publication: Journal of Crystal Growth, Vol. 7, Pages 490 to 497 (1986). That is, the Si substrate 1 is first subjected to chemical-etching using hydrofluoric acid (HF) to remove the surface oxide film. Then, the Si substrate 1 is introduced in a reduced-pressure MOCVD reactor. The Si substrate 1 is then subjected to heat-treatment or baking in a mixture gas of arsine (AsH₃) gas and hydrogen and at a temperature of 900°C or higher. With this heat-treatment, the surface of the Si substrate 1 is effectively cleaned. Then, the GaAs buffer layer 2 of a thickness of 20 nm (200 angstroms) or less is formed using arsine gas and trimethyl-gallium (TMG) as raw materials and at a temperature of 450°C or lower (the lower limit is the limit of growth which is about 300°C). If the GaAs buffer layer 2 is formed under such a condition, an amorphous GaAs buffer layer 2 having a good surface flatness is obtained. Incidentally, where a GaAs monocrystalline layer is grown directly on the Si substrate 1, there will be lattice mismatch of 4% and the surface will not be flat. Other conditions of growth can be adopted as long as the GaAs buffer layer 2 is amorphous and has a flat surface. Next, the amorphous InP buffer layer 3 having a similarly good surface flatness is grown to overlie on the amorphous GaAs buffer layer 2 having a good surface flatness that has thus been grown. The film of the InP buffer layer 3 can be formed using the reduced-pressure MOCVD, at a temperature of 550°C or lower (the lower limit is the limit of growth which is about 300 to 350°C), and using phosphine and trimethyl-indium (TMI) or triethyl-indium (TEI) as raw materials, with a molar ratio PH₃/TMI or TEI being in the order of 500. The InP buffer layer 3 will be an amorphous film having a good surface flatness. It is more desirable that the InP buffer layer 3 is thinner, within the limit in which the lattice distortion can be alleviated. The thickness of about 20 nm (200 angstroms) is preferable. On top of the InP buffer layer 3, the InP monocrystalline thin film 4 is grown to a predetermined thickness, at a temperature of 600 to 650°C. As the raw materials, phosphine and TMI or TEI can be used with the molar ratio PH₃/TMI or TEI being about 100. Figure 3 shows an example of temperature-time program in the present invention. The exact time in the figure differs depending on the growth conditions, and should be determined to give the predetermined film thickness. In the present invention, both of the GaAs buffer layer 2 and the InP buffer layer 3 are formed at a temperature lower, by 100 to 200°C or more, than the normal crystal growth temperature. Accordingly, flat layers are obtained even on a crystal having a substantially different lattice constant. However, these layers have poor monocrystalline quality, as evidenced by X-ray diffraction, or the like, and cannot be used for formation of semiconductor devices. For this reason, InP having a good monocrystalline quality is grown at a temperature of 600° or higher. It is considered that the GaAs buffer layer 2 and the InP buffer layer 3 having poor crystal quality serve to alleviate distortion in the lattice within InP monocrystalline layer during temperature elevation above 600°C or during growth of the InP monocrystalline thin film 4, and while many crystal defects are left in these buffer layers, the InP monocrystalline thin film 4 will have a good flatness and good crystal quality. As has been described in detail, a GaAs buffer layer having a lattice constant intermediate between the InP and Si is formed on the Si substrate, and InP buffer layer is formed thereon, to form two-layer buffer layer. Accordingly, distortion and crystal defects due to lattice mismatch can be absorbed, and their occurrence can thereby be avoided. As a result, on the buffer layer, an InP monocrystalline thin film having a flat surface and a good crystal quality can be formed.

Claims: An InP semiconductor thin film comprising: an Si substrate (1); an amporphous GaAs buffer layer (2) formed on the Si substrate; an amporphous InP buffer layer (3) formed on the GaAs buffer layer (2); and an InP monocrystalline thin film (4) formed on the InP buffer layer (3). An InP semiconductor thin film according to Claim 1, wherein said Si substrate (1) has a surface with substantially (100) orientation. A process for fabricating an InP semiconductor thin film, said process comprising the steps of; providing an Si substrate (1); performing heat-treatment of the Si substrate (1); forming an amorphous GaAs buffer layer (2) having a good surface flatness on the Si substrate (1); forming an amorphous InP buffer layer (3) having a good surface flatness on the GaAs buffer layer; and growing an InP monocrystalline thin film (4) on the InP buffer layer (3). A process according to Claim 3, wherein said Si substrate (11) has a surface with substantially (100) orientation. A process according to Claim 3, further comprising the step of performing chemical-etching of the surface of the Si substrate (11) using hydrofluoric acid to remove surface oxide film on the Si substrate; wherein said heat-heat treatment is performed in a mixture gas of arsine gas (AsH₃) and hydrogen and at a temperature of 900°C or higher. A process according to Claim 5, wherein said heat-treatment is performed in a reduced-pressure MOCVD reactor in which the subsequent formation of the GaAs buffer layer (2) and the InP buffer layer (3) performed. A process according to Claim 3, wherein said GaAs buffer layer (2) is formed to a thickness of about 20 nm (200 angstroms) or less by a reduced-pressure metal organic chemical vapor deposition using arsine gas and trimethyl-gallium (TMG) as raw materials and at a temperature of 450°C or lower (the lower limit is the limit of growth which is about 300°C). A process according to Claim 3, wherein said InP buffer layer (3) is formed by a reduced-pressure metal organic chemical vapor deposition at a temperature of 550°C or lower, and using phosphine and trimethyl- indium (TMI) or triethyl-indium (TEI) as raw materials, with a molar ratio PH₃/TMI or TEI being in the order of 500. A process according to Claim 8, wherein said reduced-pressure metal organic chemical vapor deposition is performed at a temperature not lower than about 300°C. A process according to Claim 8, wherein the thickness of the InP buffer layer (3) is about 20 nm (200 angstroms). A process according to Claim 3, wherein said InP monocrystalline thin film (4) is grown to a predetermined thickness, at a temperature of 600 to 650°C, using phosphine and TMI or TEI, as raw materials, with the molar ratio PH₃/TMI or TEI being about 100.

Inventors: AKIYAMA, MASAHIRO, HORIKAWA, HIDEAKI
Applicants: OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1989
Main classification: H01L31
IPC codes: H01L21, H01L33, H01L31