Bias circuit for a subranging analog to digital converter

Abstract: Through first and second external terminals (T₂, T₃), fixed potentials are applied to both ends of a first stage of ladder resistor network. A second stage of ladder resistor network is connected at one end to a second transistor (Q₂). The first external terminal (T₂) is connected to a first transistor (Q₅) through a resistor (R M ), the resistor (R M ) and the resistors of the first and second stage of ladder resistor networks being of the same kind. A positive input terminal of an operational amplifier (1) is connected to a node (A) between the resistor (R M ) and the first transistor (Q₅). A negative input terminal of the amplifier (1) receiving a reference voltage is connected to the second external terminal (T₃). The first and second transistors (Q₂, Q₅) are driven by the output signal of the amplifier (1). The amplifier (1) cooperates with the first transistor (Q₅) such that a potential at the node (A) is equal to the potential of the reference voltage. As a result, a current (I₂/M (M = constant)) flowing through the resistor (R M ) is proportional to a current (I₂) flowing through the first stage of ladder resistor network. Since the current, which is based on the operation of the second transistor (Q₂), flows into the second stage of ladder resistor network, the current flowing through the first transistor (Q₅) is propor­ tional to a current (I₃) flowing through the second stage of ladder resistor network.

Description: The present invention relates to a bias circuit as a reference voltage generator in use with a subranging or two step parallel analog to digital (A/D) converter. In the A/D conversion of an image signal, the conversion speed must be extremely high. The high speed A/D converters currently used are parallel A/D converters, subranging A/D converters, and the like. It is said that for reproduction of a normal image, 6 bits of a resolution of the A/D converter provide a reproduced image of a tolerable quality, and 7 bits of the resolution provide a reproduced image of a satisfactory quality. At present, the 7-bit resolution of the A/D converter is dominantly employed in the broadcasting system, but the A/D converter of a high resolution of 9 to 10 bits gradually increases its share of the A/D converters now marketed. To realize the high precision A/D converter of the resolution of 9 to 10 bits, use of the parallel A/D converter is impractical, because the required number of components, such as comparators and resistors, is increased. The subranging A/D converter may be simplified in circuit construction. In this respect, the subranging A/D converter is suitable for realizing the high precision A/D converter. Such a subranging A/D converter is discussed by Sugiyama et al. (including the inventor of the present invention) in their paper entitled "Two Step Parallel ADC with Peripheral Analog and Digital Circuit", Technical Report of the Electronic Information Communication Society of Japan, September 22, 1987, pp 13 to 17. In the A/D converter, an analog input signal is compared with the potentials each between adjacent resistors of the ladder resistors of a first stage of ladder resistor network (these resistors are connected in series and for generating reference voltages), thereby to determine the upper order bits of a digital value. Then, a potential within a fixed range within which the analog input signal exists is transferred to a second stage of ladder resistor network through analog switches, thereby to determine the lower order bits of the digital value. Thus, it may have the ladder resistors of the second stage for common use. Accordingly, the circuit construction of the A/D converter may be simplified. The A/D converter disclosed in the paper, as shown in Fig. 1, is made up of a first stage of ladder resistor network having resistors R F0 to R FL , a second stage of ladder resistor network having resistors R R1 to R RN , analog switches SW for transferring potential within the fixed range from the first stage of ladder resistor network to the second stage of ladder resistor network, transistors Q₃ and Q₄ for transferring the potential transferred through the switches SW to the second stage of ladder resistor network, comparators COM X for determining the upper order bits of a digital value, and comparators COM Y for determining the lower order bits. To arrange an actual subranging A/D converter, a bias circuit must be coupled with the first and second stage of ladder resistor networks. The bias circuit, as shown in Fig. 1, includes a diode D and transistors Q₁ and Q₂, which make up a mirror circuit, resistors R₀₀ to R₂₂, an external terminal T₁ of the IC chip, an externally coupled resistor R EX , and voltage sources V (++) and V (+) . In the subranging A/D converter thus arranged, the comparators COM X and the first stage of ladder resistor network cooperate to coarsely detect a potential of an analog input signal. The voltage across the ladder resistor located between the comparator COM X producing a first logic level and that COM X producing a second logic level, is transferred to the second stage of ladder resistor network, by way of paired switches SW and the transistors Q₃ and Q₄. The comparators COM Y and the second stage of ladder resistor network cooperate to finely detect the transferred potential. In the circuit arrangement shown in Fig. 1, to exactly transfer the potential across the ladder resistor R F , that is selected from among the resistors of the first stage of ladder resistor network, to the second stage of ladder resistor network, the following two conditions must be satisfied. (1) I₃ = I₄ (The base-emitter voltage V BEQ3 of the transistor Q₃ = base-emitter voltage V BEQ4 of the transistor Q₄) where I₃: current flowing through the resistors of the second stage of ladder resistor network, and I₄: current flowing through a collector-emitter path of the transistor Q₄. (2) I₃ × N × R R = I₂ × R F where N : number of the second stage ladder resistors, R R : resistance of each second stage ladder resistor R F : resistance of each first stage ladder resistor. Accordingly, the current condition is given by I₃ = I₄ = (R F /NR R )I₂. A potential difference I₂ x R F , that is transferred from the first stage of ladder resistor network to the second stage of ladder resistor network, is determined by the following facts: 1) the reference current I₁ is determined by the externally connected resistor R EX , 2) the current I₂ varies with a variation of the power source voltage, and 3) the ladder resistors R F are not uniform in resistance, and have a temperature dependency. The variation of the potential difference is undesirable, because it leads to a variation of a dynamic range of the A/D converter (voltage range within which the A/D conversion of an analog input signal is allowed). Accordingly, an object of the present invention is to provide a bias circuit (reference voltage generator) for a subranging A/D converter which minimizes a variation of the dynamic range. To achieve the above object, there is provided a bias circuit for a subranging A/D converter of the type in which a potential between the adjacent resistors of a first stage of ladder resistor network is compared with an analog input voltage, thereby to determine the upper order bits of a digital value, and a potential within a fixed range within which the analog input signal value exists is transferred through analog switches and transistors to the ladder resistors of a second stage of ladder resistor network, thereby to determine the lower order bits of the digital value, comprising: first and second voltage input terminals for supplying fixed potentials to the ends of the first stage of ladder resistor network; an operational amplifier having first and second input terminals and an output terminal, the first input terminal receiving a reference voltage of a predetermined potential; a first current source connected to the output terminal of the operational amplifier, and being controlled by the operational amplifier; resistor means connected between the first voltage input terminal and the first current source, a node between the resistor means and the first current source being connected to the second input terminal of the operational amplifier, and the operational amplifier and the first current source operating so that the potential applied to the second input terminal is equal to the reference voltage, and that a current flowing through the resistor means is proportional to a current flowing through the resistors of the first stage of ladder resistor network; and a second current source connected between the resistors of the second stage of ladder resistor network and the output terminal of the operational amplifier, for operating, under control of the output signal of the operational amplifier, such that a current proportional to the current flowing through the resistor means flows into the resistors of the second stage of ladder resistor network, the resistors of the first stage of ladder resistor network, the resistors of the second stage of ladder resistor network, and the resistor means being of the same kind. In other words, a bias circuit for subranging A/D converter, according to the present invention, comprises: first means (including resistor means, operational amplifier, and first current source) for generating a current proportional to a current flowing through a first stage of ladder resistor network, which are externally applied with voltages; and second means (including a second current source) for feeding a current proportional to the proportional current generated by the first means to a second stage of ladder resistor network. The present invention has the following advantageous features. A voltage across each of the resistors of the first stage of ladder resistor network is fixed. The resistors of the first and second stages of ladder resistor networks are of the same kind. The voltage generated across each of the resistors of the first stage of ladder resistor network is free from the nonuniform resistance values of the ladder resistors and the temperature variation. The currents flowing through the first and second stages of ladder resistor networks are proportionally related with one another (in other words, those currents vary at the same rate). The currents of the transistors, which serve to transfer the voltage to the second stage of ladder resistor network, can be kept equal to each other. With the above advantageous features, the voltage can exactly be transferred from the first stage of ladder resistor network to the second stage. The transferred voltage is free from the nonuniformity in the resistance values of the ladder resistors, and the temperature variation. Therefore, a variation of the dynamic range of the A/D converter is minimized. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a bias circuit for a conventional subranging A/D converter; Fig. 2 is a circuit diagram of a bias circuit for a subranging A/D converter according to a first embodiment of the present invention; and Fig. 3 is a circuit diagram of a bias circuit for a subranging A/D converter according to a second embodiment of the present invention. A first embodiment of the present invention will be described with reference to Fig. 2. A first stage of ladder resistor network having "L" ladder resistors R F1 to R FN connected in series, is provided with first and second external terminals T₂ and T₃ at both ends. The first external terminal T₂ applies a fixed voltage V (+) , e.g., 5 V, to the first stage of ladder resistor network. The second external terminal T₃ applies another fixed voltage V (-) , e.g., 3 V, to the first stage of ladder resistor network. A node "O" between the adjacent ladder resistors R F1 to R FL of the first stage of ladder resistor network is connected to one of comparators COM X . The comparator COM X compares a potential at the node "O" with an input analog voltage. Through the comparison operation, those comparators determine the upper order bits of a digital value. Those nodes "O" are connected respectively through analog switches SW to the bases of transistors Q₃ and Q₄. The collectors of the transistors Q₃ and Q₄ are connected to the fixed potential point V (+) . The emitters of those transistors are connected to both ends of a second stage of ladder resistor network having "N" ladder resistors R R1 to R RN , which are connected in series. A node "P" between the adjacent ladder resistors R R1 to R RN of the second stage of ladder resistor network is connected to one of comparators COM Y . The comparator COM Y compares a potential at the node "P" with an input analog voltage. Through the comparison operation, those comparators determine the lower order bits of a digital value. The emitter of the transistor Q₄ is connected to a fixed potential point V (--) , e.g., ground point, through a collector-emitter path of a transistor Q₂ as a current source, and a resistor R₂₂. The numbers L and N of the ladder resistors are determined by the number of bits of the A/D converter. The first external terminal T₂ is connected to the fixed potential point V (--) , through a resistor R M , the collector-emitter current path of a transistor Q₅, and a resistor R₃₃. A node A between the resistor R M and the collector of the transistor Q₅, is connected to a positive input terminal of an operational amplifier 1. A negative input terminal of the operational amplifier 1, which is for receiving the voltage V (-) as a reference voltage, is connected to a node B between the second external terminal T₃ and the ladder resistor R FL . The output terminal of the operational amplifier 1 is connected to the bases of the transistors Q₂ and Q₅. The ladder resistors R F1 to R FL of the first stage of ladder resistor network and the ladder resistors R R1 to R RN of the second stage, and the resistor R M are of the same kind, viz., made of materials which are equal in quality and temperature characteristic. Accordingly, the operational amplifier 1 cooperates with the transistor Q₅ connected to its output, to keep a potential at the node A at the reference voltage V (-) . A current I₂/M (M = constant) flowing through the resistor R M is proportional to a current I₂ flowing through the ladder resistors R F1 to R FL of the first stage. The transistors Q₂ and Q₅ serving as the current sources are driven by the output signal of the operational amplifier 1. Further, the current based on the operation of the transistor Q₂ flows into the ladder resistors R R1 to R RN of the second stage. A current (corresponding to I₂/M) flowing through the collector-emitter current path of the transistor Q₅ is proportional to the current I₃ flowing into the ladder resistors R R1 to R RN . In the circuit arrangement of Fig. 2, the potentials at both the ends of the first stage of ladder resistor network are fixed by the external power sources, as in the ordinary video A/D converter. Accordingly, in this circuit arrangement, a value of "ladder resistors of the first stage x I₂" is kept constant irrespective of the variation in the resistance of the ladder resistors and the temperature change. In this point, this arrangement is distinguished from the arrangement of Fig. 1. Consequently, the voltage at both the ends of the first stage of ladder resistor network, and the voltage at point B are made constant. Because the potentials at points A and B are equal to each other, the current I₂ is proportional to the current I₂/M, and the current from the current source Q₅ is proportional to that of the current source Q₂. As a consequence, the current I₂ is proportional to the current I₃. In the arrangement of Fig. 2, to exactly transfer the potential across the first stage ladder register to the second stage of ladder register network, the following relations must hold I 3 = I 4 , and I 3 × N × R R = I 2 R F = constant where I₄: current flowing through the collector-emitter path of the transistor Q₄, N : number of the resistors of the second stage of ladder resistor network, R R : resistance of each resistor of the second stage of ladder resistor network, and R F : resistance of each resistor of the first stage of ladder resistor network. Hence, I₃ can be rewritten into I 3 = (R F /NR R )I 2 Where the relation (2) holds, the current I₂ is exactly proportional to the current I₃, because the resistors of the first and second stages of ladder resistors are of the same kind, and R F /NR R is constant. Therefore, the potentials between the adjacent resistors of those ladder resistors of the first stage, and the potential applied to the resistors of the second stage are little influenced by the variation in resistance and the temperature variation. Therefore, the dynamic range of the A/D conversion is minimized in variation. Fig. 3 is a circuit diagram showing an arrangement of a second embodiment of the present invention. The second embodiment is featured in that the negative input terminal of the operational amplifier 1 is connected to a node C of the resistors R FK and R F(K+1) of the first stage of ladder resistor network, and a potential at the node C is used as a reference voltage applied to the negative input terminal of the amplifier 1. Also in this case, as in the first embodiment, the operational amplifier 1 operates so that the potential at point A is equal to the reference voltage, i.e., the potential at point C. The remaining arrangement of Fig. 3 is substantially equal to that of the first embodiment. Accordingly, the operation of and the advantages attained by the second embodiment are substantially the same as those of the first embodiment. The reference voltage may be obtained at any node of the ladder resistors R F1 to R FL of the first stage. As described above, in a bias circuit for a subranging A/D converter according to the present invention, the voltages between the adjacent resistors of those ladder resistors of the first stage, and the potential applied to the resistors of the second stage are little influenced by the variation in resistance and the temperature variation. Therefore, the dynamic range of the A/D conversion is minimized in variation. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A bias circuit for a subranging analog to digital (A/D) converter of the type in which a potential between the adjacent resistors (R F1 to R F2 ) of a first stage of ladder resistor network is compared with an analog input voltage, thereby to determine the upper order bits of a digital value, and a potential within a fixed range within which said analog input signal value exists is transferred through analog switches (SW) and transistors (Q₃,Q₄) to the ladder resistors (R R1 to R RN ) of a second stage of ladder resistor network, thereby to determine the lower order bits of the digital value, comprising: first and second voltage input terminals (T₂, T₃) for supplying fixed potentials to the ends of said first stage of ladder resistor network; an operational amplifier (1) having first and second input terminals and an output terminal, said first input terminal receiving a reference voltage of a predetermined potential; a first current source (Q₅, R₃₃) connected to said output terminal of said operational amplifier (1), and being controlled by said operational amplifier (1); resistor means (R M ) connected between said first voltage input terminal (T₂) and said first current source, a node between said resistor means (R M ) and said first current source being connected to said second input terminal of said operational amplifier (1), and said operational amplifier (1) and said first current source operating so that the potential applied to said second input terminal is equal to said reference voltage, and that a current flowing through said resistor means (R M ) is proportional to a current flowing through said resistors (R F1 to R FL ) of said first stage of ladder resistor network; and a second current source (Q₂, R₂₂) connected between said resistors (R R1 to R RN ) of said second stage of ladder resistor network and the output terminal of said operational amplifier (1), for operating, under control of the output signal of said operational amplifier (1), such that a current proportional to the current flowing through said resistor means (R M ) flows into said resistors (R R1 to R RN ) of said second stage of ladder resistor network, and whereby said resistors (R F1 to R FL ) of said first stage of ladder resistor network, said resistors (R R1 to R RN ) of said second stage of ladder resistor network, and said resistor means (R M ) are of the same kind. The bias circuit according to claim 1, characterized in that said first input terminal of said operational amplifier (1) is connected to said second voltage input terminal (T₃) so that said first input terminal receives the fixed potential applied to said second voltage input terminal (T₃) as said reference voltage. The bias circuit according to claim 1, characterized in that said first input terminal of said operational amplifier is connected to between the appropriate adjacent resistors (R FK , R F(K+1) ) of the ladder resistors (R F1 to R FL ) of said first stage of ladder resistor network, such that said first input terminal receives an appropriate potential between the fixed potentials applied to said first and second voltage input terminals (T₂, T₃). The bias circuit according to claim 2 or 3, characterized in that said first current source includes a first transistor (Q₅) with base, collector, and emitter, and the base of said first transistor (Q₅) is connected to said output terminal of said operational amplifier (1), the collector is connected to said resistor means (R M ) and said second input terminal of said operational amplifier (1), and the emitter is connected to a fixed potential point whose potential is lower than said fixed potentials applied to said first and second voltage input terminals (T₂, T₃). The bias circuit according to claim 4, characterized in that said second current source includes a second transistor (Q₂) with base, collector and emitter, and the base of said second transistor (Q₂) is connected to said output terminal of said operational amplifier (1), the collector is connected to said resistor (R R1 to R RN ) of said second stage of ladder resistor network, and the emitter is connected to said fixed potential point whose potential is lower than said fixed potentials applied to said first and second voltage input terminals (T₂, T₃). The bias circuit according to claim 5, characterized in that the fixed potential applied to said first voltage input terminal (T₂) is higher than the fixed potential applied to said second voltage input terminal (T₃). The bias circuit according to claim 6, characterized in that said first input terminal of said operational amplifier (1) is a negative input terminal and said second input terminal is a positive input terminal.

Inventors: SUGIMOTO YASUHIRO, SUGIMOTO, YASUHIRO, SUGIMOTO, YASUHIRO INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H03M1
IPC codes: H03M1