PHASE-LOCKED LOOP TYPE SYNTHESIZER HAVING MODULATION FUNCTION

Abstract: In a phase-locked loop type synthesizer comprising a phase-locked loop which comprises a phase comparator, a loop filter, a voltage controlled oscillator having a gain Kv, and a circuit for feeding back an output from the voltage controlled oscillator to the phase comparator through a frequency divider having a frequency division ratio N and which is supplied with first and second modulation signals at first and second sections through first and second adders, first and second gain control circuits are provided on input lines of the first and the second modulation signals, respectively. The first gain control circuit has a first gain adjusted to be in inverse proportion to the frequency division ratio N while the second gain control circuit has a second gain adjusted to be in inverse proportion to the gain Kv. Preferably, the first adder is connected between the phase comparator and the loop filter while the second adder is connected between the loop filter and the voltage controlled oscillator. If the voltage controlled oscillator is used as a fixed gain type, the second gain control circuit may be omitted.

Description: This invention relates to a phase-locked loop (PLL) type synthesizer with modulation function which is suitable for modulating a carrier signal by a digital signal or a voice signal. Such a synthesizer is particularly useful in a radio communication device. A synthesizer of the type described is disclosed in United States Patent No. 4,052,672 issued to Enderby et al and assigned to Motorola, Inc., and comprises a phase-locked loop circuit comprising a phase comparator, a loop filter, a voltage controlled oscillator having a gain Kv, and a circuit for feeding back a frequency signal produced from the voltage controlled oscillator to the phase comparator. The feedback operation is carried out through a frequency divider having a frequency division ratio (N). For modulation, a digital signal is supplied to a specific section of the phase-locked loop circuit as a first modulation signal through a first adding circuit. A voice signal is supplied to another section of the phase-locked loop circuit as a second modulation signal through a second adding circuit. Such a synthesizer is desirable to have a constant modulation sensitivity and a flat frequency characteristic over a wide range. The modulation sensitivity may be called audio sensitivity. The modulation sensitivity represents an input level of the modulation signal necessary for giving a predetermined reference variation to a modulated signal. Although the synthesizer of the type described has a flat frequency characteristic over a full frequency band of the modulation signal, it tends to have the influence of output frequency, namely, carrier frequency, of the voltage controlled oscillator. Namely, if the voltage controlled oscillator has wide band in frequency band thereof, the frequency division ratio N of the frequency divider (or the gain Kv of the voltage controlled oscillator) varies in dependence on the carrier frequency of the voltage controlled oscillator. This means that the modulation sensitivity fluctuates in dependence on the output frequency of the voltage controlled oscillator. In order to obtain the constant modulation sensitivity, a phase comparator of a variable gain type has been used for another type synthesizer. Such a synthesizer is disclosed in United States Patent No. 4,313,209 issued to Drucker and assigned to John Fluke Mfg. Co., Inc. In the synthesizer, a gain of the phase comparator is controlled in proportion to the frequency division ratio N and in inverse proportion to the gain Kv. Simultaneously, the input level of the modulation signal is controlled in inverse proportion to the gain Kv. Although the synthesizer has a constant modulation sensitivity, it needs the variable gain type phase comparator which is expensive. It is therefore an object of this invention to provide a PLL type synthesizer having constant modulation sensitivity regardless of an output frequency of a voltage controlled oscillator. It is another object of this invention to provide a PLL type synthesizer of the type described which is low in cost. A PLL type synthesizer to which this invention is applicable comprises a PLL circuit which comprises a phase comparator, a loop filter, a voltage-controlled oscillator having a gain Kv, and a circuit for feeding back an output from the voltage-controlled oscillator to the phase comparator through a frequency divider having a frequency division ratio N, a first adder for adding a modulation signal through a compensator to an output of the phase comparator to produce a first composite signal, and a second adder for adding the modulation signal to an output of the loop filter to produce a second composite signal. The first composite signal is applied to the loop filter while the second composite signal is applied to the voltage controlled oscillator. According to this invention, first and second gain control circuits are provided on an input line of the modulation signal for the compensator and an input line of the modulation signal for the second adder, respectively. The first gain control circuit has a first variable gain G1 adjusted to be in inverse proportion to the frequency division ratio N. The second gain control circuit has a second variable gain G2 adjusted to be in inverse proportion to the gain Kv of the voltage-controlled oscillator. Fig. 1 is a block diagram of a conventional PLL type synthesizer; Fig. 2 is a block diagram of another conventional PLL type synthesizer; Fig. 3 is a block diagram of a PLL type synthesizer according to a first embodiment of this invention; Fig. 4 is a block diagram of a PLL type synthesizer according to another aspect of this invention; and Fig. 5 is a block diagram of a PLL type synthesizer according to a second embodiment of this invention. Referring to Fig. 1, a conventional PLL type synthesizer will be described at first in order to facilitate a clear understanding of the present invention. The synthesizer is of the type disclosed in the United States Patent No. 4,052,672 referred to hereinabove. In Fig. 1, the synthesizer comprises a reference oscillator 11, a first frequency divider 12 having a first frequency division ratio M, and a feedback loop circuit 13. The feedback loop circuit 13 comprises a phase comparator 14, a loop filter 15 having a predetermined transfer function, a voltage controlled oscillator 16, and a second frequency divider 17 having a second frequency division ratio N and feeds back a frequency signal S16 produced from the voltage controlled oscillator 16 to the phase comparator 14 through the second frequency divider 17. First and second adders 21 and 22 and a compensator 23 are used for modulation, as will later be described. A reference frequency signal S11 produced from the reference oscillator 11 is divided in frequency by the first frequency divider 12. The first frequency divider 12 supplies a first divider frequency signal S12 to the phase comparator 14. The second frequency divider 17 divides the frequency signal S16 and supplies a second divided frequency signal S17 to the phase comparator 14. The phase comparator 14 compares the first divided frequency signal S12 with the second divided frequency signal S17 and produces a phase error signal S14 as a comparison result signal. For modulation, a modulation signal Sm, namely, a digital signal or a voice signal, is supplied to the feedback loop circuit 13 from an input terminal 24 through two circuits. A first of the two circuits is the compensator 23 which is an integrator and the first adder 21 interconnected between the phase comparator 14 and the loop filter 15. The modulation signal Sm is applied to the first adder 21 through the compensator 23 and added to the phase error signal S14 to produce a first composite signal S21 which is supplied to the loop filter 15. Supplied with the first composite signal S21, the loop filter 15 delivers a filtered signal S15 to the second adder 22. A second of the two circuits is the second adder 22 interconnected between the loop filter 15 and the voltage controlled oscillator 16. The modulation signal Sm is applied to the second adder 22 and is added to the filtered signal S15 to produce a second composite signal S22. The second composite signal S22 is fed to the voltage controlled oscillator 16. The voltage controlled oscillator 16 produces a modulated signal So as an output signal. The above-described synthesizer has a flat frequency characteristic over a full frequency band of the modulation signal Sm even if a voice signal and a digital signal are used for the modulation signal Sm. However, the synthesizer has a problem that modulation sensitivity changes when an output frequency of the voltage controlled oscillator 16, namely a carrier frequency has a wide band. That is, the frequency division ratio N changes in dependence on the carrier frequency and the gain Kv. Referring to Fig. 2, description will proceed to another conventional PLL type synthesizer disclosed in the United States Patent No. 4,313,209 referred to hereinabove. The synthesizer comprises similar parts designated by like reference numerals. Detailed description is therefore omitted. In the synthesizer, a variable gain type phase comparator 30 having a gain K is used in place of the phase comparator 14 of a fixed gain type shown in Fig. 1. The gain K of the phase comparator 30 is controlled by a first digital to analog converter 31. A second digital to analog converter 32 and an amplifier 33 are provided on an input line of the modulation signal Sm to control a level of the modulation signal Sm. The first digital to analog converter 31 controls the gain of the phase comparator 30 to be in proportion to the frequency division ratio N of the second frequency divider 17 but in inverse proportion to the gain Kv of the voltage controlled oscillator 16. The second digital to analog converter 32 controls the input level of the modulation signal Sm to be in inverse proportion to the gain Kv. The synthesizer can suppress variation of the modulation sensitivity due to a wide band of the carrier frequency of the voltage controlled oscillator 16 but needs the variable gain type phase comparator which is expensive. Referring to Fig. 3, description will be made as regards a PLL type synthesizer according to a first embodiment of this invention. The synthesizer is similar to that illustrated in Fig. 1 except for first and second gain control circuits 41 and 42 each of which has first and second gains G1 and G2. The first gain control circuit 41 is provided on an input line of the modulation signal Sm for the compensator 23. The compensator 23 has a predetermined transfer function G(S). On the other hand, the second gain control circuit 42 is provided on an input line of the modulation signal Sm for the second adder 22. A reference frequency signal S11 produced from the reference oscillator 11 is divided in frequency by the first frequency divider 12. The first frequency divider 12 supplies a first divided frequency signal S12 to the phase comparator 14 having a gain K. The second frequency divider 17 divides the frequency signal S16 and delivers a second divider frequency signal S17 to the phase comparator 14. The phase comparator 14 compares the first divided frequency signal S12 with the second divided frequency signal S17 and produces a phase error signal S14 as a comparison result signal. The modulation signal Sm is supplied to the first adder 21 through the first gain control circuit 41 and the compensator 23 and is added to the phase error signal S14. The first adder 21 delivers a first composite signal S21 to the loop filter 15 having a predetermined transfer function F(S). The loop filter 15 supplies a filtered signal S15 to the second adder 22. The modulation signal Sm is also supplied to the second adder 22 through the second gain control circuit 42 and is added to the filtered signal S15. The second adder 22 delivers a second composite signal S22 to the voltage controlled oscillator 16. The first gain G1 is controlled to be in inverse proportion to the frequency division ratio N while the second gain G2 is controlled to be in inverse proportion to the gain Kv. Modulation characteristic of the synthesizer is given by the following equation (1): where, Δωo(S): frequency deviation of the carrier frequency in the voltage controlled oscillator 16, S: Laplacian operator, and Em(S): input level of the modulation signal Sm. Here, it is assumed that the following equation (2) is given: the following equation (3) is led: Δωo(S) = Em(S)·Kv·G2 (3) If τ represents a time constant of the integrator of the compensator 23 and the transfer function G(S) of the compensator 23 is given by: G(S) = 1/S·τ), equation (2) is rewritten as: From equation (4), the following equation (5) is obtained: G1 = G2·τ·K·Kv/N. (5) If equation (5) is satisfied and if Kv G2 in the right side of equation (3) is made constant, that is, the following equation (6) is satisfied: Kv·G2 = C, (6) where C represents a constant, the frequency deviation Δωo(S) can be made constant and flat in no relation to the carrier frequency and the frequency of the modulation signal Sm. From equation (6), the following equation (7) is obtained: G2 = C/Kv (7) Applying equation (7) to equation (5), is obtained, where β = C·τ·K . It will be understood from equations (7) and (8) that the object of the invention can be realized by controlling G1 and G2 in inverse proportion to the frequency division ratio N and the gain Kv, respectively. The control is realized by the use of a central processing unit (not shown) known in the art. That is, the central processing unit controls the gains G1 and G2 of the first and the second gain control circuits 41 and 42 to be in inverse proportion to data of the frequency division ratio N and the gain Kv input thereto, respectively. Referring to Fig. 4, description will proceed to another aspect of the PLL type synthesizer described in conjunction with Fig. 3. The synthesizer is similar to that illustrated in Fig. 3 except for the first and the third gain control circuits 41 and 43 each of which has the first and the third gains G1 and G3 (= G2/G1) . In the synthesizer, the first gain control circuit 41 is provided on an input line of the modulation signal Sm common for the compensator 23 and the second adder 22. The gain G1 is controlled in inverse proportion to the frequency division ratio N. On the other hand, the third gain control circuit 43 is provided on an input line of the modulation signal Sm for the second adder 22. The gain G3 is controlled in proportion to the frequency division ratio N but in inverse proportion to the gain Kv of the voltage controlled oscillator 16. In Fig. 3, input voltages V1 and V2 to the first and the second adders 21 and 22 are represented by: V1 = Em(S)·G1·G(S)∝1/N V2 = Em(S)·G2∝1/Kv On the other hand, input voltages V1 and V2 in the circuit in Fig. 4 are given by: because G3 = G2/G1 . The above-described gain control operation is carried out by a central processing unit described in conjunction with Fig. 3. Thus, it is possible to obtain a constant modulation sensitivity with no use of a variable gain type phase comparator. Referring to Fig. 5, description will be made as regards a PLL type synthesizer according to a second embodiment of this invention. The synthesizer is similar to that illustrated in Fig. 3 except that the second gain control circuit 43 is omitted and that a fixed gain type voltage controlled oscillator 44 is used in place of the voltage controlled oscillator 16 shown in Fig. 4. This is based on a following reason. In Fig. 4, if the gain Kv of the voltage controlled oscillator 16 is made constant in no relation to the carrier frequency, it is possible to make the second gain G2 constant. In the case, the first gain G1 may only be controlled in inverse proportion to the frequency division ratio N. Thus, the second gain control circuit can be omitted by using the fixed gain type voltage controlled oscillator 44. Such a voltage controlled oscillator is disclosed in Japanese Published Unexamined Utility Model Application No. 48112/83 (Kôkai Shô 58-48112 Gou) assigned to the present assignee. While this invention has thus far been described in conjunction with preferred embodiments thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, the PLL circuit may comprise other components.

Claims: A phase-locked loop type synthesizer comprising a phase-locked loop circuit which comprises a phase comparator (14), a loop filter (15), a voltage controlled oscillator (16) having a gain Kv, and a circuit (17) for feeding back an output from said voltage controlled oscillator (16) to said phase comparator (14) through a frequency divider having a frequency division ratio N, a first adder (21) for adding a modulation signal (Sm) through a compensator (23) to an output of said phase comparator (14) to produce a first composite signal (S21), said first composite signal being applied to said loop filter (15), and a second adder (22) for adding said modulation signal (Sm) to an output of said loop filter (15) to produce a second composite signal (S22), said second composite signal being applied to said voltage controlled oscillator (16), characterized in that a first (41) and second (42) gain control circuits are provided on an input line of said modulation signal (Sm) for said compensator (23) and an input line of said modulation signal (Sm) for said second adder (22), respectively; said first gain control circuit (41) having a first variable gain G1 adjusted to be in inverse proportion to said frequency division ratio N, said second gain control circuit (42) having a second variable gain G2 adjusted to be in inverse proportion to said gain Kv of said voltage controlled oscillator (16). A phase-locked loop type synthesizer as claimed in Claim 1, characterized in that first gain control circuit (41) is provided on a common input line of said modulation signal (Sm) for said compensator (23) and said second adder (22), the first variable gain G1 of said first gain control circuit (41) being controlled to be in inverse proportion to said frequency division ratio N, a third gain control circuit (43) being provided in place of said second gain control circuit (43) on the input line of said modulation signal (Sm) for said second adder 22, said third gain control circuit (43) having a third variable gain given by G2/G1, said third variable gain being adjusted to be in proportion to said frequency division ratio N but in inverse proportion to said gain Kv of said voltage controlled oscillator (16). A phase-locked loop type synthesizer comprising a phase-locked loop circuit which comprises a phase comparator (14), a loop filter (15), a voltage controlled oscillator (16) having a gain Kv, and a circuit (17) for feeding back an output from said voltage controlled oscillator (16) to said phase comparator (14) through a frequency divider having a frequency division ratio N, a first adder (21) for adding a modulation signal (Sm) through a compensator (23) to an output of said phase comparator (14) to produce a first composite signal (S21), said first composite signal being applied to said loop filter (15), and a second adder (22) for adding said modulation signal (Sm) to an output of said loop filter (15) to produce a second composite signal (S22), said second composite signal being applied to said voltage controlled oscillator (16), characterized in that said voltage controlled oscillator is used as a fixed gain type, and in that a first gain control circuit (41) being provided to an input line of said modulation signal (Sm) for said compensator (23), said first gain control circuit (41) having a first variable gain G1 adjusted to be in inverse proportion to said frequency division ratio N.

Inventors: SAI, KENJI C/O JAPAN RADIO CO., LTD.
Applicants: JAPAN RADIO CO., LTD
Application year: 1989
Main classification: H03C3
IPC codes: H03C3