Method of forming a semiconductor integrated circuit having isolation trenches

Abstract: Trenches (21) for separating semiconductor elements are laid out in a matrix fashion on a semiconductor substrate. A region surrounded with the trenchs (21) serves as an element forming region (22) where a semi­ conductor element is to be formed. An interval between the adjacent trenches (21) is so selected that the ele­ ment forming region (22) defines a minimum size of semi­ conductor element. A semiconductor element requiring an area larger than the element forming region (22) is formed by using a plurality of element forming regions (22) with their trenches (21) partially removed. A capacitor resistors may be formed above the trench.

Description: The present invention relates to a method of forming a semiconductor device, and particularly to a bipolar transistor integrated circuit of the type in which a trench isolation is used for elements separation. More particularly, the present invention relates to a method of forming an integrated circuit for an analog circuit that is used for a high speed logic operation or operable at high frequencies. Recently, the technical field of the semiconductor devices, particularly bipolar integrated circuits, which are constantly under pressures to increase an integration density and to improve the performances, has begun to use a technique to isolate semiconductor elements from one another, that is called a trench isolation. A typical bipolar integrated circuit fabricated by using the trench isolation will be described with reference to Fig. 1 showing a plan view of a part of its structure including elements, trenches, and the like. As is shown, a plurality of element forming regions 1 are each enclosed by trenches 2. A base contact 3B, emitter contact 3E, and collector contact 3C are laid out on the top of each element forming area 1. The adjacent trenches 2 are separated by a distance "d" from each other. A sectional view of the structure whose top is thus laid out is shown in Fig. 2. As is shown, the side wall of each element forming region 1 is defined by the trench 2. An N + collector buried layer 5 and an N type epitaxial layer 6 are layered on a P type semiconductor substrate 4 in this order. An SiO 2 film 7 is laid over the surface of the structure containing the element forming regions 1 and the trenches 2, and covers the inner wall of each trench 2. Each trench 2 is filled with polysilicon film 9. A P + type channel cut layer 10 is formed in contact with the outside of the SiO 2 film 7 at the bottom of each trench 2. In designing the above type of the integrated circuits, a designer must devote a great care to the distance "d" between the adjacent trenches 2. In the structure of the integrated circuit as is shown in Figs. 1 and 2, a great stress is applied to the corners 11 and 12 of the SiO 2 film 7 as indicated by dotted line circles, possibly causing crystal defects. For example, if the intertrench distance "d" is set at 2 µm or less, the stress is concentrically applied to the corners, so that many crystal defects are caused and consequently a production yield is remarkably reduced in the production of the semiconductor devices. As a matter of course, the occurrence of such a phenomenon depends on the structure of trench and the manufacturing process used. In this case, to lessen the stress, the distance "d" must be broadened to be 5 to 10 µm, for example. To realize this, a complicated design work and an increase of the device geometry are necessitated. Generally, a reactive ion etching using gas of CBrF 3 , for example, is employed for forming the trenches for the trench isolation. This etching process have a great loading effect. Because of this, an etching rate depends on the areas of the trench. Therefore, in fabricating the semiconductor device, time-consuming works to obtain a required etching rate are needed, for example, to previously calculate the surface area of the trench in design stages or to etch the semiconductor structure for each type of the devices by using the same mask and to measure the depth of trench. The etching rate calculating work is an abstract to the mass production of many types of semiconductor devices. An integrated circuit known from FR-A-2 030 843 comprises a plurality of small islands made from monocrystalline silicon and element forming regions which are surrounded by polycrystalline silicon. The polycrystalline silicon surrounding the element regions is formed in a lattice fashion and serves as an electrical isolation for the islands or element regions. In the different element regions transistors or the like are formed. A further semiconductor device disclosed in US-A-4 009 484 has monocrystalline regions and polycrystalline regions which are arranged in the lattice-like manner for forming element regions in which circuit elements such as transistors can be provided. A transistor with an advanced isolation known from IEEE Transactions on Electron Devices ED-34 (11), November 1987, pages 2246-2254, is formed on a semiconductor substrate and is isolated by a trench. A first polysilicon layer serving as a base electrode and a second polysilicone layer serving as an emitter electrode are formed on the substrate. The first polysilicon layer is used as a resistor. Another semiconductor device disclosed in W083/04343 comprises a silicon chip having a first portion in which MOS-transistors are formed. A second portion of the silicon chip includes a polyoxid capacitor which is formed on a field oxide film, i.e. above an isolating region which is not used for forming transistors or the like. The object of the present invention is to provide a method of producing a semiconductor device using a trench isolation for isolating elements, which reduces the complexity in design and manufacturing process, and improves an integration density. According to the present invention this object is achieved by a method as defined in claim 1 or 2. Further advantageous embodiments and improvements of the invention can be taken from the dependent claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a plan view of a conventional integrated circuit formed using a trench isolation; Fig. 2 is a sectional view of the integrated circuit of Fig. 1; Fig. 3 is a plan view of a integrated circuit formed using a trench isolation produced according to an embodiment of a semiconductor device of the present invention; and Fig. 4 is a sectional view of the integrated circuit of Fig. 3. A specific embodiment of a method of forming a bipolar transistor integrated circuit as a semiconductor device according to the present invention will be described with reference to the accompanying drawings. A layout of semiconductor elements and trenches in a bipolar transistor integrated circuit is shown in Fig. 3. As is shown, trenches 21 are laid out in a matrix or lattice fashion. Each block enclosed by trenches 21 defines an element forming region 22. It is designed that the size of the region 22 defines a minimum element. Accordingly, a distance between the adjacent trenches 21 is at least 10 µm. This reduces the possibility that the crystal defect occurs. The above integrated circuit is designed and manufactured in the following manner. In circuit design, a designer selects element forming regions 22 separated by the trenches 21 in accordance with a circuit to be designed. As is shown, an element 23 having an emitter contact 23E, base contact 23B, and collector contact 23C, requires large areas each larger than an area of the element forming region 22 that is limited by the block of the trenches 21 arrayed in a matrix fashion. Such large area can obtained by removing a part 24 of the trench 21. The trenches defining the regions 22 where no element is formed are left as intact. A cross section of the integrated circuit thus designed and manufactured is illustrated in Fig. 4. In the figure, an npn bipolar transistor 25 is formed in an element forming region 22. In the transistor 25, an n + collector buried layer 26 is layered on a p-type semiconductor substrate 27. An n-type epitaxial layer 28 is layered on the collector buried layer 26. A base region 25b is formed in the n-type expitaxial layer 28. An emitter region 25e is formed in the base region 25b. The base region 25b is connected to a base Aℓ (aluminum) lead 25B by a p-type polysilicon film 29 as a base region contact. The silicon film 29 is led out onto an SiO 2 film 30, such as the silicon film 29 is arrayed facing the SiO 2 film 30 through the collector region of the substrate. The base Aℓ lead 25B is formed on the silicon film 29. The silicon film 29 is doped with boron, for example. The emitter region 25e is connected to an emitter Aℓ lead 25E by an n-type polysilicon film 31 as an emitter contact. In this case, an n-type polysilicon film 31 for an emitter contact is doped with arsenic, in this instance. The base Aℓ lead 25B and the emitter Aℓ lead 2E are formed by coating with aluminum film and then patterning appropriately. The trenches 21 are each filled with polysilicon film 33. A p + channel cut layer 35 is downwardly formed on the bottom of an SiO 2 film 34 covering the polysilcion film 33. In a region outside the element forming region 22 to which the p-type polysilicon film 29 extends, a dielectric layer 37 is interlaid between the p-type polysilicon film 29 and an n-type polysilicon film 36. These thus arranged cooperate to form a capacitance 38. The polysilicon film 29 is coated with a lower electrode 38a of the capacitor 38. An aluminum film is applied over the upper surface of the polysilicon film 36, and patterned, thereby to form an upper electrode 38b of the capacitor 38. The structure of Fig. 4 contains a plurality of resistors 39 and 40. The resistor 39 is provided with a plurality of Aℓ leads (in this instance, only an Aℓ lead 39a is illustrated for simplicity) that are formed on P-type polysilicon film 29 by a patterning process and are parted by given distance. The resistor 40 is provided with a plurality of Aℓ leads (in this instance, only an Aℓ lead 40a is illustrated for simplicity) that are formed on an n-type polysilicon film 41 by a patterning process and are parted by given distance. These resistances 39 and 40 are stacked one upon the other. As seen from the foregoing, the capacitors and resistors are formed on the trenches 21. Therefore, if the trenches are formed in even the regions where no elements are formed, an integration density may be improved. As seen from the foregoing description, in the semiconductor device according to the present invention, the bipolar transistor integrated circuit is featured in that trenches are previously formed in a matrix fashion. With this feature, designers can make a pattern design not taking into account intertrench intervals. Further, differences of the etching rates among the different types of elements that arises from the loading effect at the time of etching for trench formation, may be minimized. The n-type polysilicon films 36 and 41 may be the same polysilicon film 31 as formed in the same process. In other words, a high integration density of the npn bipolar integrated circuit can be attained by using two types of polysilicon films, one for leading out the base electrode and the other for leading out the emitter electrode.

Claims: Method of forming a bipolar transistor integrated circuit comprising the following steps: a) forming a plurality of insulating trenches (21) in a semiconductor substrate (27), said insulating trenches (21) enclosing semiconductor element forming regions (22) in a matrix fashion; b) forming a silicon dioxide layer (30) on said substrate (27); c) forming a bipolar transistor (25) in a first of said semiconductor element forming regions (22), said bipolar transistor (25) comprising a base region (25b) having a first conductivity type, and collector (26) and emitter (25e) regions having a second conductivity type; d) forming a first polysilicon film (29) having said first conductivity type on said silicon dioxide layer (30), said first polysilicon layer (29) comprising a first portion above said first semiconductor element forming region (22) where said bipolar transistor (25) is formed contacting said base region (25b) via a first opening in said silicon dioxide layer (30) and a second portion outside said first semiconductor element forming region (22) and above one of said plurality of insulating trenches (21); e) deposing a dielectric layer (37) on parts of said second portion of said first polysilicon film (29); f) depositing a second polysilicon film (31) having said second conductivity type, said second polysilicon film (31) comprising a first portion above said first semiconductor element forming region (22), contacting said emitter region (25e) via a second opening in said silicon dioxide layer (30), and a second portion formed on said dielectric layer (37); g) forming base (25B) and emitter (25E) leads connected to said first portions of said first and second polysilicon films (29, 31), respectively; and h) forming a first electrode (38a) on an exposed part of said second portion of said first polysilicon film (29) and a second electrode (38b) on said second portion of said second polysilicon film (31), wherein said first and second electrodes (38a, 38b) cooperate to form a capacitor (38). Method of forming a bipolar transistor integrated circuit comprising the following steps: a) forming a plurality of insulating trenches (21) in a semiconductor substrate (27), said insulating trenches (21) enclosing semiconductor element forming regions (22) in a matrix fashion; b) forming a silicon dioxide layer (30) on said substrate (27); c) forming a bipolar transistor (25) in a first of said semiconductor element forming regions (22), said bipolar transistor (25) comprising a base region (25b) having a first conductivity type, and collector (26) and emitter (25e) regions having a second conductivity type; d) forming a first polysilicon film (29) having said first conductivity type on said silicon dioxide layer (30), said first polysilicon layer (29) comprising a first portion above said first semiconductor element forming region (22) where said bipolar transistor (25) is formed contacting said base region (25b) via a first opening in said silicon dioxide layer (30), and a second portion outside said semiconductor element forming region (22) and above one of said plurality of insulating trenches (21); e) depositing a dielectric layer (37) on parts of said second portion of said first polysilicon film (29); f) depositing a second polysilicon film (31) having said second conductivity type, said second polysilicon film (31) comprising a first portion above said first semiconductor element forming region (22) contacting said emitter region (25e) via a second opening in said silicon dioxide layer (30), and a second portion formed on said dielectric layer (37); g) forming base (25B) and emitter (25E) leads connected to said first portions of said first and second polysilicon films (29, 31), respectively; and h) forming a plurality of spaced first electrodes (39a) on exposed parts of said second portion of said first polysilicon film (29) and a plurality of spaced second electrodes (40a) on said seccnd portion of said second polysilicon film (31), wherein said first and second plurality of electrodes (39a, 40a) contact first and second stacked resistances (39, 40) formed by the second portions of the first and second polysilicon films, respectively. A method according to claim 2, characterized in that a) said first polysilicon film (29) comprises a third portion formed outside said semiconductor element forming region (22) above a further one of said insulating trenches (21); b) said dielectric layer (37) is also formed on parts of said third portion of said first polysilicon film (29); c) said second polysilicon film (31) comprises a third portion formed on said dielectric layer (37); and in that d) a third electrode (38a) is formed on an exposed part of said third portion of said first polysilicon film (29), and a fourth electrode (38b) is formed on said third portion of said second polysilicon film (31), wherein said third and fourth electrodes (38a, 38b) cooperate to form a capacitor (38). The method according to one of claims 1 to 3, characterized by providing an intertrench interval which is equal to a predetermined minimum element size. The method according to claim 4, characterized in that said intertrench interval is approximately 10 µm. The method according to claim 5, characterized in that a semiconductor element of larger size than said minimum element size is formed by forming a plurality of adjacent element forming regions (22) between which an insulating trench (21) is not formed.

Inventors: HIRAKAWA KENJI, HIRAKAWA, KENJI, HIRAKAWA, KENJI INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27