Time continuous, differential analog-to-digital converter

Abstract: The invention is for an analog-to-digital converter which is useful for audio applications owing to its insensitivity to noise. The converter achieves this insensitivity by utilizing a differential, common node integrator having a non-switching capacitive feed-back loop.

Description: The invention relates to analog-to-digital converters, and more particularly to a monolithic, time continuous over-sampled analog-to-digital converter having a differential, time continuous integrator that is forgiving of capacitive tolerances. There are many different types of analog-to-digital converters. Analog-to-digital converters which have a single ended structure are generally sensitive to cross-talk from other circuits on a chip. They are also sensitive to power supply noise, and di/dt effects and other forms of common mode generated noise. In addition, this type of converter will produce a high degree of unwanted asymmetrical voltage output due to miss-balances in the positive versus negative scales. To counter these disadvantages, switching capacitors with differential integration have been applied. However, this approach is not entirely successful, since this type of structure is sensitive to clocks feed-through, and requires precisely matched capacitance. In the fabrication of these devices on a chip using a CMOS process, such structures require an additional masking step. EP-A-0169535 discloses an analog-to-digital converter in which an analogue input voltage is sampled and compared with an analogue reference voltage derived from an internal D/A converter responsive to an up/down counter, the counter being incremented or decremented whenever the input voltage differs from the reference voltage and providing the digital output when the comparator detects coincidence. EP-A-0293780 discloses an analog-to-digital converter according to the preamble portion of present claim 1. According to the present invention there is provided a differential analog-to-digital converter, comprising: a continuous non-switched capacitive integrator having a differential input and a differential output, the integrator including a split input stage wherein analogue input voltages are converted to differential analogue current signals for comparison with differential reference currents supplied by a digital-to-analogue converter forming a feed-back loop circuit with the integrator; and a comparator operatively connected to the differential output of the integrator within the said loop circuit, the input signals being sampled and digitised by clocking the comparator; characterised in that the integrator further includes a common mode feedback circuit, and a binary counter is operatively connected to the output of said comparator, the counter being incremented or decremented one step in response to each comparison, the split input stage including a first operational amplifier having a first input terminal connected to receive an analog input voltage and a second input terminal connected to the output terminal of the amplifier, and a second operational amplifier having a first input terminal connected to ground potential and a second input terminal connected through a first resistor to the output terminal of the second amplifier and through a second resistor to the output terminal of the first amplifier. The linear, time continuous, over-sampling analog-to-digital converter disclosed herein by way of example is constructed utilizing a 1.2u CMOS process, which is described in AMD DSLAC DESIGN REVIEW I & II (1987). The converter operates in the differential mode and provides the capability of delivering up to the high dynamic range without the use of any switch capacitance techniques or the use of precisely matched capacitance. The converter has particular application in audio systems, such as CODECs and MODEMs, particularly where such devices operate together in a noisy environment. The analog-to-digital converter forms a CMOS integrated circuit. Accordingly, there is provided an improved analog-to-digital converter that is useful in audio applications and is characterised by its noise insensitivity. In the accompanying drawings, by way of example only: FIGURE 1 is a circuit diagram of a prior art integrator utilizing switch capacitance. FIGURE 2 is a circuit diagram of the analog-to-digital converter of this invention utilizing a differential, non-switch capacitive integrator. FIGURE 3 is a circuit diagram of the integrator for the analog-to-digital converter shown in FIGURE 2. Generally speaking, the invention pertains to an analog-to-digital converter that samples the analog signals in a differential mode and is relatively insensitive to noise by virtue of a non-switch capacitive integrator of unique design. The non-switch capacitive design of the integrator is ideally suited for CMOS fabrication, since this construction does not require an additional masking step. Now referring to FIGURE 1, a prior art switch capacitive integrator circuit 10 is shown. Such an integrator circuit 10 is useful in suppressing noise, since noise signals will be equally amplified and integrated by the differential structure of the circuit. Such noise suppression is most useful in audio systems. However, such a circuit 10 is sensitive to clocks feed-through, and in most cases requires highly accurate and precise capacitors. It is one of the objects of the current invention to provide a low-cost integrated circuit, and the need for precision capacitors is contrary to this objective. Furthermore, such a design can only be achieved by utilizing an additional masking step in a CMOS process, such as that described in IEEE International Solid-State Circuits Conference ISSCC (1988) page 258, "Design of a CMOS Second Order Sigma-Delta Modulator," by Bernhard E. Bosen & Bruce A. Wooley. Such an additional processing step obviously increases costs, and is not compatible with the stated objective. Referring to FIGURE 2 a circuit 20 is shown of the time continuous, over-sampled, differential analog-to-digital converter of this invention. The analog signals are supplied to the circuit 20 by means of a split input stage 25 comprising two operational amplifiers 26 and 27, respectively, which receive the analog voltage input via line 28 and convert this input to differential analog current signals by means of resistors R2 and R3, respectively. These current signals are fed to the integrator (input) stage 30, via lines 28 and 29. A 6.02 dB per bit DAC 35 supplies differential reference currents to the integrator stage 30 via lines 31 and 32. The respective analog and reference currents are combined at nodes 33 and 34 of the novel dual common node feed-back loop 36. The integrator 37, similar in operation to AMD Model No. 7930, is composed of several GM and high gain stages, and a common mode stage for maintaining the differential integrator output centered about a zero voltage at all times. The circuit for integrator 37 is shown in FIGURE 3. The combined currents are integrated within the loop 36 by capacitors C1 and C2, and form the inputs to an AMD Model No. 7910 comparator 40. The comparator 40 digitizes signals by comparing the analog current signals with the reference generated current signals. A clocked, binary counter 41 having similar characteristics as a Texas Instruments, Model No. 74AS169 counter, increments and decrements the comparison signals. If the input (analog) currents are higher than the DAC currents, the counter 41 will decrement one step down, and another comparison will take place. The binary counter 41 is clocked at a clocking rate of 2.048 MHz. The analog-to-digital circuit 20 of this invention is currently available as a CMOS AMD chip, Model No. Am79C02 or & Am9489, Austin, Texas division. Other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art.

Claims: A differential analog-to-digital converter (20), comprising: a continuous non-switched capacitive integrator (37) having a differential input and a differential output, the integrator (37) including a split input stage (25) wherein analogue input voltages are converted to differential analogue current signals for comparison with differential reference currents supplied by a digital-to-analogue converter (35) forming a feed-back loop circuit with the integrator (37); and a comparator (40) operatively connected to the differential output of the integrator (37) within the said loop circuit, the input signals being sampled and digitised by clocking the comparator; characterised in that the integrator (37) further includes a common mode feedback circuit, and a binary counter (41) is operatively connected to the output of said comparator (40), the counter being incremented or decremented one step in response to each comparison, the split input stage (25) including a first operational amplifier (26) having a first input terminal connected to receive said analog input voltages and a second input terminal connected to the output terminal of the amplifier, and a second operational amplifier (27) having a first input terminal connected to ground potential and a second input terminal connected through a first resistor (R4) to the output terminal of the second amplifier (27) and through a second resistor (R5) to the output terminal of the first amplifier (26). A differential analog-to-digital converter according to claim 1 wherein the comparator (40) and binary counter (41) are clocked at 2.048 MHz. A differential analog-to-digital converter according to claim 1 or claim 2, wherein said converter forms a CMOS integrated circuit. The use of a differential analog-to-digital converter according to any one of the claims 1-3 in an audio system. The use of a differential analog-to-digital converter according to any one of the claims 1-3 in a CODEC. The use of a differential analog-to-digital converter according to any one of the claims 1-3 in a MODEM.

Inventors: MOYAL MIKI ZVI, MOYAL, MIKI ZVI
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1989
Main classification: H03M1
IPC codes: H03M3, H03M1