Semiconductor device having a reduced parasitic capacitance and manufacturing method thereof

Abstract: A semiconductor device comprises a substrate (10), a collector region formed of an epitaxial layer (12) of a first conduction type formed on the substrate (10), a field oxide layer (14) formed on the epitaxial layer (12) so as to define a device formation zone in a device isolation manner, a recess formed in the device formation zone in alignment with an edge of the field oxide layer (14), a polycrystalline silicon layer (18) of a second conduction type opposite to the first conduction type and formed on a side wall of the recess and on the field oxide layer (14), and an base region composed of a graft base region (32) and an active base region (34). The graft base region (32) is formed of a diffused region of the second conduction type formed in the epitaxial layer (12) within the device formation zone by diffusion of impurity from the polycrystalline silicon layer (18) of the second conduction type, and the active base region (32) is formed of a doped region of the second conduction type formed integrally with the polycrystalline silicon layer (18) of the second conduction type under a bottom surface of the recess. The semiconductor device also comprises an insulating layer (20) formed to cover the polycrystalline silicon layer (18) of the second conduction type, a polycrystalline silicon layer (36) of the first conduction type formed on at least a bottom of the recess, and an emitter region (38) formed of a diffused region of the first conduction type formed in the diffused region of the second conduction type by diffusion of impurity from the polycrystalline silicon (36) layer of the first conduction type.

Description: The present invention relates to a semiconductor device, and more specifically to a semiconductor device including a bipolar transistor having a reduced parasitic capacitance, and a method for manufacturing such a semiconductor device. In the prior art, as means for realizing a high speed bipolar transistor by reducing a base resistance and a junction capacitance, it has been known to form a graft base in a self-alignment manner by using as a diffusion source a polycrystalline silicon film which forms a base electrode. This is known, for example, from EP-A-0 170 250. In another known example, a n-type epitaxial layer, which forms a n-type collector region, is formed on an upper surface of a silicon substrate. A field isolation oxide layer is then formed on the n-type epitaxial layer by means of a local oxidation of silicon so as to define a device formation zone. Further, an oxide film is formed on the n-type epitaxial layer within the device formation zone surrounded by the field oxide layer. Thereafter, a p-type polycrystalline silicon layer and an insulating layer are formed in the named order to cover the whole upper surface of the substrate. A first window is formed through the insulating layer situated within the device formation zone, and the p-type polycrystalline silicon layer and the oxide film are etched using as a mask the insulating layer having the first window, so that a second window in alignment with the first window and larger than the first window is formed through the p-type polycrystalline silicon layer and the oxide film. In other words, the edge portion of the insulating layer defining the first window overhangs over the edge of the p-type polycrystalline silicon layer defining the second window. In this condition, a p-type polycrystalline silicon film is filled into a space formed by the n-type epitaxial layer, an inner wall surface of the second window formed in the oxide film and the p-type polycrystalline silicon layer, and the overhanging edge portion of the insulating layer forming the first window. Then, the substrate is heat-treated to the effect that p-type impurities contained in the p-type polycrystalline silicon film are diffused into the n-type epitaxial layer to form a p⁺ type graft base region on the upper surface of the n-type epitaxial layer. Thereafter, an insulating film for isolating an emitter electrode and a base electrode from each other is formed on an inner vertical wall of each of the p-type polycrystalline silicon film and the insulating layer and on an upper surface of the insulating layer. Thereafter, p-type impurities are ion-implanted into an exposed area of the n-type epitaxial layer, so as to form a p-type active base region in a surface portion of the n-type epitaxial layer surrounded by the p⁺ graft base region. Then, a polycrystalline silicon film is deposited on the exposed area of the epitaxial layer and on the above mentioned insulating film for isolating an emitter electrode and a base electrode from each other, and n-type impurities are ion-implanted so as to bring the deposited polycrystalline silicon film into an n-type and also to form an n-type emitter region in a surface portion of the p-type base region under the deposited polycrystalline silicon film. In the above mentioned semiconductor device manufacturing process, the graft base region is formed in the self-alignment manner, and therefore, it is possible to a base resistance and a collector junction capacitance. However, since the p-type polycrystalline silicon film used for forming the graft base region in the self-alignment manner is formed beneath the overhanging edge portion of the insulating layer defining the first window, namely at an outside of the contour line defined by the first window formed in the insulating layer, the area of the base region including the graft base region becomes larger than an opening having a minimum dimension which can be formed under a current photolithography technique. Therefore, it has been necessary to ensure a margin between the base region and the field isolation oxide layer, and accordingly, the semiconductor device manufactured in accordance with the above mentioned conventional process could not have a reduced MOS parasitic capacitance between the n-type epitaxial layer forming the collector region and the p-type polycrystalline silicon layer which forms the base electrode. In addition, the window for forming the graft base region and the emitter region is determined by a photolithographic step which is different from that for defining the field isolation oxide layer, and therefore, the above mentioned margin has to be further enlarged by an extra portion corresponding to an amount of mismatching between the two mask patterns used. Accordingly, it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof which have overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a semiconductor device having a minimum MOS parasitic capacitance between a collector region and a base electrode conductor. A further object of the present invention is to provide a semiconductor device manufacturing method capable of forming a base region formation window in self-alignment with a field isolation oxide without an extra margin thereby to reducing a MOS parasitic capacitance between a collector region and a base electrode conductor to a minimum extent. The above and other objects of the present invention are achieved in accordance with the present invention as set out in the appended set of claims. In particular, there is provided a semiconductor device comprising a substrate, a collector region formed of an epitaxial layer of a first conduction type formed on the substrate, a field oxide layer formed on the epitaxial layer so as to define a device formation zone in a device isolation manner, a recess formed in the device formation zone in alignment with an edge of the field oxide layer, a polycrystalline silicon layer of a second conduction type opposite to the first conduction type and formed on a side wall of the recess and on the field oxide layer, an base region composed of a graft base region and an active base region, the graft base region being formed of a diffused region of the second conduction type formed in the epitaxial layer within the device formation zone by diffusion of impurity from the polycrystalline silicon layer of the second conduction type, the active base region being formed of a doped region of the second conduction type formed integrally with the polycrystalline silicon layer of the second conduction type under a bottom surface of the recess, an insulating layer formed to cover the polycrystalline silicon layer of the second conduction type, a polycrystalline silicon layer of the first conduction type formed on at least a bottom of the recess and an emitter region formed of a diffused region of the first conduction type formed in the diffused region of the second conduction type by diffusion of impurity from the polycrystalline silicon layer of the first conduction type. According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising the steps of preparing a substrate having an epitaxial semiconductor layer of a first conduction type formed on an upper surface of the substrate, forming a field oxide layer on the epitaxial semiconductor layer so as to define a device formation zone in a device isolation manner, etching the epitaxial semiconductor layer within the device formation zone by using the field oxide layer as a mask, so as to form a recess in the device formation zone in alignment with an edge of the field oxide layer, forming a polycrystalline silicon layer of a second conduction type opposite to the first conduction type on a side wall of the recess and on the field oxide layer, forming an insulating layer to cover the polycrystalline silicon layer of the second conduction type, causing impurity contained in the polycrystalline silicon layer of the second conduction type to diffuse into the epitaxial layer within the device formation zone so as to form a diffused region of the second conduction type in a peripheral portion of the epitaxial layer within the device formation zone, forming a doped region of the second conduction type in a central portion of the epitaxial layer within the device formation zone and integrally with the a diffused region of the second conduction type, forming a polycrystalline silicon layer of the first conduction type on at least a bottom of the recess, and doping impurity of the first conduction type into a surface region of the diffused region of the second conduction type so as to form a diffused region of the first conduction type in the doped region of the second conduction type. In the semiconductor device manufactured in accordance with the above mentioned process, the epitaxial layer of the first conduction type forms a collector region, the diffused region and the doped region of the second conduction type form a base region, and the diffused region of the first conduction type forms an emitter region. In a preferred embodiment, the polycrystalline silicon layer of a second conduction type opposite to the first conduction type is formed not only on the side wall of the recess and on the field oxide layer, but also on a bottom of the recess, the insulating layer is formed to cover the polycrystalline silicon layer of the second conduction type not only at the side wall of the recess and on the field oxide layer, but also at the bottom of the recess. In addition, the step of forming the diffused region of the second conduction type includes the steps of depositing a non-doped polycrystalline silicon layer on the insulating layer formed to cover the polycrystalline silicon layer of the second conduction type, doping impurity of the first conduction type to a portion of the non-doped polycrystalline silicon layer situated on the bottom of the recess so as to form a first conduction type impurity doped polycrystalline silicon layer on the bottom of the recess, selectively etching the non-doped polycrystalline silicon layer and the first conduction type impurity doped polycrystalline silicon layer situated on the bottom of the recess so as to cause the first conduction type impurity doped polycrystalline silicon layer to be completely removed from the bottom of the recess, but the non-doped polycrystalline silicon layer to still remain, etching the insulating layer by using the remaining non-doped polycrystalline silicon layer as a mask, so as to remove a portion of the insulating layer situated on the bottom of the recess, removing the remaining non-doped polycrystalline silicon layer and the polycrystalline silicon layer of the second conduction type situated on the bottom of the recess by using the remaining insulating layer as a mask, so as to expose the epitaxial layer at the bottom of the recess, and heat-oxidizing an exposed surface of the epitaxial layer at the bottom of the recess thereby to cause the impurity contained in the polycrystalline silicon layer of the second conduction type to diffuse into the epitaxial layer within the device formation zone so as to form the diffused region of the second conduction type in the epitaxial layer within the device formation zone. The above and other objects, features and advantages of the present invention will be apparent from the following description of a preferred embodiment of the invention with reference to the accompanying drawings. Figures 1A to 1G are diagrammatic sectional views illustrating various steps of an embodiment of the semiconductor device manufacturing method in accordance with the present invention; and Figure 2 is a diagrammatic sectional view illustrating an embodiment of the semiconductor device in accordance with the present invention. Referring to Figures 1A to 1G, there are diagrammatic sectional views illustrating various steps of an embodiment of the semiconductor device manufacturing method in accordance with the present invention. As shown in Figure 1A, on a p-type silicon substrate 10, an n-type epitaxial layer 12 is formed, and then, a field isolation oxide layer 14 is formed by a selective oxidation such as a local oxidation of silicon, so that a device formation zone is defined. This field isolation oxide layer 14 extends downwardly into the n-type epitaxial layer 12 to a depth deeper than a principal surface of the substrate. Thereafter, the device formation zone which is not covered by the field isolation oxide layer 14 is etched by using the field isolation oxide layer 14 as a mask, so that a recess 16 having a depth of 300nm to 500nm is formed in a self-alignment with the field isolation oxide layer 14, as shown in Figure 1A. Then, as shown in Figure 1B, a p-type polycrystalline silicon layer 18 having a thickness of 200nm to 400nm is deposited to cover an inner surface of the recess 16 and an upper surface of the field isolation oxide layer 14, and further etched to form a desired pattern of p-type polycrystalline silicon layer 18 which functions as a base electrode and conductor. Thereafter, an insulating layer 20 such as a silicon oxide layer having a thickness of 200nm to 400nm is formed to cover the patterned p-type polycrystalline silicon layer 18, and a polycrystalline silicon layer 22 having a thickness of 200nm is deposited to cover the insulating layer 20. This polycrystalline silicon layer 22 is doped with no impurity. Thereafter a silica film formation solution containing 4 to 12 mol % of phosphorus is deposited to have a thickness of 100nm to 200nm. Further, the substrate is baked at a temperature of about 600°C, and the dried silica is etched to leave a silica film 24 containing the phosphorus only at a bottom of the recess 16. Thereafter, the substrate is heat-treated at a temperature of about 900°C, so that the phosphorus contained in the silica film 24 diffuses into the polycrystalline silicon layer 22, so that the polycrystalline silicon layer 22 on the bottom of the recess 16 is converted into an n⁺ polycrystalline silicon layer 26. Then, the silica film 24 is removed by a hydrofluoric acid (HF), as shown in Figure 1C. As shown in Figure 1D, the non-doped polycrystalline silicon layer 22 and the n⁺ polycrystalline silicon layer 26 are etched by a reactive ion etching using a gas including carbon and chlorine. In this reactive ion etching, since the etching rate for the n⁺ polycrystalline silicon layer 26 is about double of that for the non-doped polycrystalline silicon layer 22, the n⁺ polycrystalline silicon layer 26 on the bottom of the recess 16 are removed in a self-alignment manner, and on the other hand, the non-doped polycrystalline silicon layer 22 remains. In addition, an exposed insulating layer 20 is anisotropically etched by a reactive ion etching using a fluorocarbon gas, by using the remaining non-doped polycrystalline silicon layer 22 as a mask, as shown in Figure 1D. Thereafter, the remaining non-doped polycrystalline silicon layer 22 and the p⁺ polycrystalline silicon layer 18 within an opening defined by the remaining insulating layer 20 are removed so that the n-type epitaxial layer 12 within the opening is exposed as shown in Figure 1E. Then, the exposed n-type epitaxial layer 12 within the opening is heat-oxidized to form an silicon oxide layer 30 on the n-type epitaxial layer 12. In this heat-oxidation process, p-type impurities (for example, boron) contained in the p-type polycrystalline silicon layer 18 is diffused into the n-type epitaxial layer 12, so that a p⁺ graft base region 32 is formed, as shown in Figure 1F. In addition, p-type impurities is ion-implanted into the bottom of the recess 16 through the oxide layer 30, so that a p-type active base region 34 is formed integrally with the p⁺ graft base region 32 under the oxide layer 30. The oxide layer 30 is anisotropically removed by a reactive ion etching, and thereafter, a polycrystalline silicon layer 36 is deposited on the exposed p-type base region 34. Then, arsenic is ion-implanted to the deposited polycrystalline silicon layer 36 and through deposited polycrystalline silicon layer 36 to the p-type base region 32, so that an n-type emitter region 38 is formed in the p-type base region 32. Thereafter, the arsenic-doped deposited polycrystalline silicon layer 36 is patterned. In the semiconductor device thus formed, the patterned p-type polycrystalline silicon layer 18 forms a base electrode and wiring conductor, and the patterned arsenic-doped deposited polycrystalline silicon layer 36 forms an emitter electrode and wiring conductor. In addition, as shown in Figure 2, a collector electrode and wiring conductor 40 is formed in contact with an n⁺ region 42 formed in the n-type epitaxial layer 12. Thus, an npn bipolar transistor is formed. As seen from the above mentioned description with reference to the drawings, the p-type polycrystalline silicon layer 18 functioning as the base electrode and wiring conductor extends from the graft base region 32 along a vertical wall of the recess 16 formed in alignment with the field isolation oxide 14, and also extends from an upper edge fo the recess 16 directly onto the the field isolation oxide 14. Namely, there is no thin insulating layer formed at the inside of the field isolation oxide. Therefore, the p-type silicon layer 18 extending from the graft base region has no portion extending over the thin insulating layer formed at the inside of the field isolation oxide. In other words, the p-type, silicon layer 18 extending from the graft base region and the n type epitaxial layer 12 forming the collector region are separated only by the thick field isolation oxide. As a result, a MOS parasitic capacitance between the collector region 12 and the base electrode and wiring conductor 18 can be greatly reduced as compared with the conventional one in which a portion of a base electrode and wiring conductor extends over the insulating layer formed at the inside of the field isolation oxide. Furthermore, the diffusion source for formation of the graft base region 32 has a horizontal size (or length or width) corresponding to a sum of the thickness of the p-type silicon layer 18 and the thickness of the insulating layer 20. In other words, the thickness of the p-type silicon layer 18 and the thickness of the insulating layer 20 are precisely controlled. Therefore, the diffusion source for formation of the graft base region 32 can have a precisely controlled horizontal size, as compared with the diffusion source formed under the overhanging edge portion of the insulating layer in the conventional process, since the amount of overhang is difficult to control. In addition, the thick oxide layer 14 for a device isolation is selectively formed, and the graft base region 32 is formed in alignment with an edge of the device isolation thick oxide layer 14, and thereafter, the emitter region 38 is formed in alignment with the base region. If the device isolation pattern is designed to realize the above mentioned relation, a plurality of different diffusion layers are all formed in a self-alignment manner. Therefore, it is not necessary to provide for a margin including an amount of mismatching between different patterns, and accordingly, it is possible to reduce a transistor to a minimum size required. In addition, the number of mask patterns used can be reduced by three or four as compared with the conventional method.

Claims: A semiconductor device comprising a substrate (10), a collector region formed of an epitaxial layer (12) of a first conductivity type formed on the substrate (10), a field oxide layer (14) formed on the epitaxial layer (12), whereby an isolated device formation zone is defined, a recess (16) formed in said device formation zone in alignment with the edge of the field oxide layer (14) bounding said device formation zone, a polycrystalline silicon layer (18) of a second conductivity type opposite to the first conductivity type and formed on a side wall of said recess (16) and on the field oxide layer (14), a base region composed of a graft base region and an active base region, said graft base region being formed of a first doped region (32) of the second conductivity type formed in said epitaxial layer (12) within said device formation zone and adjoining said polycrystalline silicon layer (18) of the second conductivity type, said active base region being formed of a second doped region (34) of the second conductivity type in physical contact with said first doped region (32) of the second conductivity type under a bottom surface of said recess (16), an insulating layer (20) covering said polycrystalline silicon layer (18) of the second conductivity type, a polycrystalline silicon layer (36) of the first conductivity type formed on at least a bottom of said recess (16), and an emitter region formed of a doped region (38) of the first conductivity type formed in said second doped region (34) of the second conductivity type under said polycrystalline silicon layer (36) of the first conductivity type. A method for manufacturing the semiconductor device of claim 1 comprising the steps of preparing a substrate (10) having an epitaxial semiconductor layer (12) of a first conductivity type formed on an upper surface of the substrate (10), forming a field oxide layer (14) on said epitaxial semiconductor layer (12), whereby an isolated device formation zone is defined, etching the epitaxial semiconductor layer (12) within said device formation zone by using said field oxide layer (14) as a mask, whereby a recess (16) in said device formation zone is formed in alignment with the edge of said field oxide layer (14) bounding said device formation zone, forming a polycrystalline silicon layer (18) of a second conductivity type opposite to the first conductivity type on a side wall of said recess (16) and on the field oxide layer (14), forming an insulating layer (20) covering said polycrystalline silicon layer (18) of the second conductivity type, causing impurity contained in said polycrystalline silicon layer (18) of the second conductivity type to diffuse into said epitaxial layer (12) within said device formation zone, whereby a diffused region (32) of the second conductivity type is formed in a peripheral portion of said epitaxial layer (12) within said device formation zone, forming a doped region (34) of the second conductivity type in a central portion of said epitaxial layer (12) within said device formation zone and in physical contact with said diffused region (32) of the second conductivity type, forming a polycrystalline silicon layer (36) of the first conductivity type on at least a bottom of said recess (16), and doping impurity of the first conductivity type into a surface region of said doped region (34) of the second conductivity type, whereby a diffused region (38) of the first conductivity type is formed in said doped region (34) of the second conductivity type, wherein said epitaxial layer (12) of the first conductivity type forms a collector region, said diffused region (32) and said doped region (34) of the second conductivity type form a base region, and said diffused region (38) of the first conductivity type forms an emitter region. A method claimed in Claim 2 wherein said polycrystalline silicon layer (18) of a second conductivity type opposite to the first conductivity type is formed not only on said side wall of said recess (16) and on the field oxide layer (14), but also on a bottom of said recess (16), said insulating layer (20) covers said polycrystalline silicon layer (18) of the second conductivity type not only at said side wall of said recess (16) and on the field oxide layer (14), but also at said bottom of said recess (16), and wherein the step of forming said diffused region (32) of the second conductivity type includes the steps of depositing a non-doped polycrystalline silicon layer (22) on said insulating layer (20) covering said polycrystalline silicon layer (18) of the second conductivity type, doping impurity of the first conductivity type to a portion of said non-doped polycrystalline silicon layer (22) situated on said bottom of said recess (16) thereby forming a first conductivity type impurity doped polycrystalline silicon layer on the bottom of said recess (16), selectively etching said non-doped polycrystalline silicon layer (22) and said first conductivity type impurity doped polycrystalline silicon layer (26) situated on the bottom of said recess (16) thereby causing said first conductivity type impurity doped polycrystalline silicon layer (26) to be completely removed from the bottom of said recess (16), but said non-doped polycrystalline silicon layer (22) to still remain, etching said insulating layer (20) by using the remaining non-doped polycrystalline silicon layer (22) as a mask, thereby removing a portion of said insulating layer (20) situated on the bottom of said recess (16), removing the remaining non-doped polycrystalline silicon layer (22) and said polycrystalline silicon layer (18) of the second conductivity type situated on the bottom of said recess (16) by using the remaining insulating layer (20) as a mask, thereby exposing said epitaxial layer (12) at said bottom of said recess (16), and heat-oxidizing an exposed surface of said epitaxial layer (12) at said bottom of said recess (16) thereby forming a heat-oxidized layer (30) at said exposed surface of said epitaxial layer (12) at said bottom of said recess (16) and causing the impurity contained in said polycrystalline silicon layer (22) of the second conductivity type to diffuse into said epitaxial layer (12) within said device formation zone whereby said diffused region (32) of the second conductivity type is formed in said epitaxial layer (12) within said device formation zone. A method claimed in Claim 3 wherein the step of forming said first conductivity type impurity doped polycrystalline silicon layer (26) on the bottom of said recess (16) includes the step of applying a solution containing impurity of the first conductivity type on said non-doped polycrystalline silicon layer (22) in said recess (16), drying said solution, thereby forming residue (24) containing the impurity of the first conductivity type on said non-doped polycrystalline silicon layer (22) situated on said bottom of said recess (16), heat-treating, thereby causing the impurity of the first conductivity type contained in said residue (24) to diffuse into said non-doped polycrystalline silicon layer (22) situated on said bottom of said recess (16), and removing said residue (24). A method claimed in Claim 4 wherein the step of forming said doped region (34) of the second conductivity type includes the step of ion-implanting the impurity of the second conductivity type into said epitaxial layer (12) within said device formation zone through said heat-oxidized layer (30) formed at said exposed surface of said epitaxial layer (12) at said bottom of said recess (16). A method claimed in Claim 4 wherein the step of forming said diffused region (38) of the first conductivity type in said doped region (34) of the second conductivity type includes the step of removing said heat-oxidized layer (30) formed at said exposed surface of said epitaxial layer (12) in said bottom of said recess (16), thereby exposing said doped region (34) of the second conductivity type within said recess (16), depositing a polycrystalline silicon layer (36) on an exposed surface of said doped region (34) of the second conductivity type within said recess (16), and ion-implanting the impurity of the first conductivity type into said doped region (34) of the second conductivity type within said recess (16) through said polycrystalline silicon layer (36) formed on said exposed surface of said doped region (34) of the second conductivity type.

Inventors: SHIMIZU JUNZOH, SHIMIZU, JUNZOH
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: H01L29
IPC codes: H01L29, H01L21