Semiconductor commutator

Abstract: A semiconductor commutator (Fig.4) which is constructed by providing a semiconductor region of a first conductivity type (3) and a semiconductor region of a second conductivity type, wherein there is provided a grain boundary (5) which is located near a junction surface (6) of the semiconductor region of the first conductivity type (3) and the semiconductor region of the second conductivity type so as not to cross said junction surface (6). The commutator may be manufactured by using a technique of selective nucleation and growth.

Description: The present invention relates to a diode for use in a high speed switching commutator circuit. It also relates to a commutator circuit including such diode and a method of producing such a diode. For commutator circuit applications diodes should have fast switching characteristics. Furthermore, for efficient operation such diodes should also exhibit low leakage current when reversed biased to the OFF state condition. In a monocrystalline PN junction diode carrier lifetimes ordinarily are long. When the diode is switched from the ON state to the OFF state, excessive minority carriers remain and, as a consequence, the delay time for switching following bias voltage reversal is long. The switching speed in such diodes, accordingly, is unsatisfactory for high speed switching applications such as commutator circuit application. Hitherto, in order to improve switching speed, a heavy metal, for example gold, has been introduced to act as a recombination centre to reduce minority carrier lifetime and thus decrease switching delay time. A high switching speed PN junction diode using recombination centres to reduce minority carrier lifetime is disclosed in United States Patent US-A-4259683. The diode disclosed therein is of a type which comprises: first and second semiconductor regions of opposite conductivity type adjoined at a PN junction; and a localised region of recombination centres, disposed in said first semiconductor region, and which is offset from the PN junction so that the recombination centres do not cross the PN junction. The diode of the present invention is a diode of this type. The diode described in US-A-4259683, is such that the peak amount of carrier recombination occurs during device turnoff. The region of reduced carrier lifetime such as that provided by gold heavy metal recombination centres, causes fast carrier recombination during device turnoff such that the device switching speed is correspondingly increased over that of comparable conventional diodes. However, where gold is used as a recombination centre, a problem arises in that electric field is concentrated in the vicinity of the gold centres, which therefore can lead to premature electric field breakdown and an increase in leakage current. There is also known a PN diode comprising adjoining regions of opposite electroconductivity type of monocrystalline semiconductor material and polycrystalline semiconductor material, respectively. Although, in a diode of this construction, the lifetime of minority carriers in the polycrystalline material is relatively low, it is a problem that the PN junction interface between these materials is crossed by numerous grain boundaries. It is a problem that impurities tend to be segregated at these grain boundaries and lead thus to field concentration and increased leakage current. Figure 1 shows a typical current versus voltage characteristic of a PN junction diode. In the figure, the solid curve shows the ideal preferred characteristic. A typical characteristic, however, is shown by broken line. It can be seen from this characteristic that there is a substantial leakage current in the state of reverse bias. For the above reason it has been considered undesirable to have polycrystalline material grain boundaries in the immediate vicinity of the diode PN junction. In Patent Abstracts of Japan, Vol. 9, No. 131, (E-319) [1854] June 6, 1985 and published Japanese Patent Application JP-A-60016466 there is described a method of producing a PN junction diode in which a region of polycrystalline silicon thin film is radiated by laser and a corresponding monocrystalline silicon region is grown from the resulting liquid phase. Subsequently, respective P and N type impurities are introduced to define a PN junction in the monocrystalline region. The size of the monocrystalline region is chosen such that the characteristics of the PN junction are determined by the monocrystalline material and thus unaffected by the polycrystalline material at the boundaries of this region which are remote from the PN junction. In this way a stable breakdown voltage and a low reverse bias current can be achieved. Such a diode, however, exhibits long minority carrier lifetime and is thus unsuitable for high speed switching applications. In accordance with the present invention there is provided a diode for use in a high speed switching commutator circuit which is of the type discussed hereinabove with reference to US-A-4259683. The diode of the present invention, however, is characterised in that: the first semiconductor region includes a grain boundary defining the localised region of the combination centres and is located to lie beyond the depletion region extending into the first semiconductor region within a minority carrier diffusion length from a depletion edge thereof when the diode is reverse biassed to the OFF state condition. The grain boundary aforementioned is effective in reducing minority carrier lifetime and thus effective to reduce the time taken to switch off the diode. Furthermore, since the grain boundary is offset from the depletion region, the problem of increase in leakage current is avoided. In order that the invention may be more readily understood, embodiments thereof will now be described by way of example and with reference to the accompanying drawings in which: Fig. 1 is a graph showing the current to voltage characteristics of a PN junction diode; Fig. 2 is a schematic partial cross sectional view for explaining a construction of a semiconductor commutator of an embodiment 1 of the invention; Fig. 3 is a schematic partial plan view of the semiconductor commutator; Fig. 4 is a schematic partial cross sectional view for explaining an arrangement of a grain boundary of the semiconductor commutator; Figs. 5A to 5E are respectively schematic vertical sectional views showing manufacturing steps to form a crystal substrate which is used in the semiconductor commutator of the embodiment of the invention; Fig. 6 is a schematic perspective view showing an Si 3 N 4 film formed on an SiO 2 film; Fig. 7 is a schematic partial plan view showing a construction of a semiconductor commutator of an embodiment 2 of the invention; Fig. 8 is a schematic partial plan view showing a wiring state of the semiconductor commutator of the embodiment 2 of the invention; and Fig. 9 is a circuit diagram showing a circuit which is used to measure a recovery time in the reverse direction of the semiconductor commutator of the embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the invention will be described in detail hereinbelow with reference to the drawings. First, manufacturing steps to form a crystal substrate having a grain boundary which is used in a semiconductor commutator of the embodiment of the invention will be described. For instance, a crystal growing method disclosed in E.P. Application Publication No. 0,244,081 can be used. Figs. 5A to 5E are vertical sectional views showing an example of the manufacturing steps to form a crystal substrate which is used in the semiconductor commutator in the embodiment of the invention. Fig. 6 is a perspective view showing an Si 3 N 4 film formed on an SiO 2 film and corresponds to the manufacturing step shown in Fig. 5A. First, as shown in Figs. 5A and 6, SiO 2 film 1 having a thickness of 2000 Å serving as a non-nucleus forming surface is formed on a silicon wafer of (100) by using a thermal oxidation process. An Si 3 N 4 film of 300 Å is deposited onto the SiO 2 film 1. Further, the Si 3 N 4 film is patterned by using a well-known fine processing technique in a manner such that nuclei each having a size of 2 µm□ are arranged at at an interval b (in this case, b = 100 µm). A resultant Si 3 N 4 film 8 serving as a nucleus forming surface which was formed is hereinafter called a site. Next, as shown in Fig. 5B, by executing a vapor phase growing process of the SiH 2 Cℓ 2 /H 2 /PH 3 system, a crystal nucleus of Si can be formed only in the site 8 since the nucleus forming concentration of Si 3 N 4 is larger than that of SiO 2 . If the size of the site 8 is set to be sufficiently small, only one crystalline nucleus 9 of Si to be grown into single crystalline silicon can be formed in the single site 8. Next, as shown in Fig. 5C, when crystal is subsequently grown, only one crystalline nucleus 9 on each site 8 continuously grows, an Si monocrystalline grain 10 is formed, and the Si monocrystalline grain 10 can be further grown. Next, as shown in Fig. 5D, the Si monocrystalline grains 10 which grew from both of the adjacent sites 8 are joined at the center between the sites 8, thereby forming a grain boundary 11. As shown in the diagram, the grain boundary 11 is formed in the direction perpendicular to the substrate. Then, as shown in Fig. 5E, the substrate on which the grain boundary 11 was formed by joining the Si monocrystalline grains 10 is ground until the thickness of the crystalline layer becomes 2 µm, thereby forming a monocrystalline layer 2. Thus, an n type silicon crystalline substrate in which the position of the grain boundary was controlled like a lattice of an interval of 100 µm and a phosphorus (P) concentration is set to 1 x 10 16 atom/cm 3 was obtained. In the invention, the crystalline substrate in which the position of the grain boundary was controlled is a significant component member and, preferably, it can be formed by using the crystal growing method disclosed in the E.P. Application Publication No. 0,244,081 mentioned above. However, the invention is not limited to such a method but any other preferable methods can be also used, if a grain boundary position can be controlled by the methods. The semiconductor commutator of the invention can be manufactured as follows by using the n type silicon crystalline substrate formed by the manufacturing steps described above. (Embodiment 1) Fig. 2 is a partial cross sectional view for explaining a construction of a semiconductor commutator of the embodiment 1 of the invention. Fig. 3 is a partial plan view of the semiconductor commutator. Fig. 4 is a partial cross sectional view for explaining an arrangement of a grain boundary of the semiconductor commutator. First, on the n type silicon crystalline substrate, an SiO 2 film with a thickness of 5000 Å is formed. Next, in order to form high impurity concentration region within only a desired single crystal grain in the single crystal layer 2, a portion of the SiO 2 film corresponding to the single crystalline grain is removed. In the present embodiment, a 93 µm square portion of SiO 2 was removed. Next, using SiO 2 film as a mask, BN diffusion is conducted at a temperature 100°C for 2 hours, thereby generating an impurity diffusion layer which extends through the layer (silicon wafer in the present embodiment). A high impurity p type semiconductor region 3 as shown in Fig. 2 is formed. The state of this is described with reference to Fig. 4 as follows. In Fig. 4, reference numeral 13 denotes a BN diffused oxide film for masking. c indicates the distance from a grain boundary 5 to the edge portion of the SiO 2 film (in this case, about 3.5 µm) and d represents the distance of the diffusion in the lateral direction by the BN diffusion (in this case, about 1.4 µm and corresponds to about 70 % of the depth). The main surface on which the p type semiconductor region 3 and an n type semiconductor region 2a were ground and the grain boundary 5 are perpendicularly formed almost in parallel with a junction surface 6. In order to form an n + type semiconductor region 4 which contacts the n type monocrystalline grain (n type semiconductor region 2a) adjacent to the monocrystalline grain in which the p + type semiconductor region 3 is formed, a thermal oxide film having a thickness of 4000 Å is formed. Thereafter, the SiO 2 film is selectively eliminated, a PSG film having a thickness of 4000 Å is deposited, a heat treatment is executed at 900°C for 30 minutes, and impurities (P) are diffused. As shown in Fig. 3, contact holes are formed and aluminum (Aℓ) is evaporation deposited and they are used as electrodes. An SiO 2 film having a thickness of 1000 Å is deposited as a protective film. It should be noted here that, as shown in Fig. 4, the grain boundary 5 exists in a region which extends from a depletion edge 12 for a diffusion length L p (L p denotes a diffusion length of a hole). In the embodiment, the diffusion length L p is set to about up to 5 µm and the junction surface 6 exists at a position which is spaced from the grain boundary 5 by about 2 µm when considering also the diffusion distance d in the lateral direction due to the BN diffusion. On the other hand, since a depletion layer width is set to about 1 µm at 20 volts, as shown in Fig. 4, the grain boundary 5 is located within the diffusion length L p from the depletion edge 12. In the embodiment, a number of excessive minority carriers exist in the region from the depletion edge 12 to the diffusion length L p and the recombination center existing in such a region most effectively functions. Therefore, even if the number of defects existing in this region is not so large, the switching operation can be executed at a high speed. That is, according to the invention, there is provided a semiconductor commutator which can operate at a high speed and has good current to voltage characteristics by effectively using a grain boundary defect, as a recombination center, in which a grain boundary is arranged between the junction surface and the electrode so as not to cross the junction surface. It is considered that the defect level of the grain boundary defect exists at the center than 0.2 eV of gold, and the grain boundary defect functions as a more effective recombination center than gold. That is, a level which most effectively operates as the recombination center is ones at a midst of the bandgap. A level of gold is at 0.2 eV from the midst of two bandgap, while, since the defect level of the grain boundary is at the midst, the defect energy level effectively acts as the recombination center rather than that of the gold. Since its concentration lies within a range about from 10 12 /cm 2 to 10 13 /cm 2 , it corresponds to 10 17 /cm 3 or more in the case where gold is used as a recombination center. Thus, the current density in the reverse direction is set to up to 10 -8 Å and this value is not so different from that of the commutator formed on the monocrystalline substrate obtained by a Cz method. The semiconductor commutator of the embodiment exhibits the good I-V characteristics of the low dark current. An external circuit is set such that I F (V F ) V R /R ∼ 100 by using a circuit shown in Fig. 9 and the recovery time in the reverse direction was measured. Thus, the high speed switching characteristics of up to 5 nsec were obtained. (Embodiment 2) This embodiment relates to the case where the semiconductor commutator in embodiment 1 mentioned above was two-dimensionally arranged. Fig. 7 is a partial plan view showing a construction of a semiconductor commutator in the embodiment 2 of the invention. Fig. 8 is a partial plan view showing a wiring state of the semiconductor commutator. As shown in Fig. 7, in the embodiment, P type semiconductor regions and N type semiconductor regions are alternately arranged like a zigzag pattern with respect to the columns and rows. Fig. 7 shows a part of the arrangement of the matrix of 10 rows x 10 columns. The semiconductor commutator of the embodiment can be also formed by using the crystal growing method disclosed in E.P. Application Publication No. 0,244,081 in a manner similar to the embodiment 1. The SiCℓH 2 /H 2 /HCℓ system is used as a material gas system and the crystalline layer is grown until a single crystalline grain diameter becomes 50 µm. Thereafter, it is ground until the thickness of the monocrystalline layer becomes 2 µm. Then, under the conditions similar to those in the embodiment 1, after a P + layer and an N + layer were formed, contact holes and Aℓ wirings are formed and an SiO 2 layer having a thickness of 10000 Å is further deposited as a protective film by a sputtering method. In the embodiment 1, since a junction area larger than the area which is occupied by the device cannot be obtained, there will be a case that the embodiment 1 cannot cope with the situation where a relatively large current is needed. However, in the embodiment 2, by arranging the N and P type semiconductor regions like a zigzag pattern a current value which is two or more times as large as that in the embodiment 1 can be obtained by the same area. Therefore, by using such an arrangement, a semiconductor commutator having a large junction area can be also manufactured in a small space. The semiconductor commutator obtained in the embodiment exhibits the good I/V characteristics as shown by a solid line in Fig. 1. An external circuit is set such that the switching speed becomes. I F (V F ) V R /R ∼ 100 by using the circuit shown in Fig. 9. The recovery time in the reverse direction was measured. Thus, the high speed switching characteristics of up to 5 nsec were obtained. As described in detail above, according to the semiconductor commutator of the invention, it is possible to realize the semiconductor commutator in which the good I-V characteristics are obtained and the recovery time in the reverse direction has a value on the order of nsec and which can operate at a high speed.

Claims: A diode for use in a high-speed switching commutator circuit, said diode comprising: first and second semiconductor regions (2a, 3) of opposite conductivity type adjoined at a pn junction (6); and a localised region of recombination centres, which localised region is disposed in said first semiconductor region, and is offset from said pn junction (6) so as not to cross the same (6); which diode is characterised in that: said first semiconductor region includes a grain boundary (5) defining said localised region, located to lie beyond the depletion region extending into said first semiconductor region within a minority carrier diffusion length (4) from the depletion edge (12) when said diode is reverse biassed to OFF state condition. A diode as claimed in claim 1 wherein: said first semiconductor region has a planar main surface; and said grain boundary (5) extends from said planar main surface in a perpendicular direction. A diode as claimed in either preceding claim wherein said first semiconductor region comprises first and second monocrystalline grains adjoined at said grain boundary (5), and said second semiconductor region (3) is defined within said second monocrystalline grain. A diode as claimed in any preceding claim wherein said first semiconductor region is of n conductivity type and said second semiconductor region is of p conductivity type. A diode as claimed in claim 1 comprising a semiconductor layer (2) defining said first semiconductor region (2a); a plurality of grain boundaries (5) defining a lattice network dividing said semiconductor layer (2) into a plurality of grains; and a plurality of separate second semiconductor regions (3), formed in said semiconductor layer (2), each formed at a respective lattice position in a respective one of said grains without crossing said grain boundaries (5), each of opposite conductivity type to the surrounding first semiconductor region (2a), and of relatively higher dopant concentration than said first semiconductor region (2a), with respective pn junctions (6) between said first semiconductor region (2a) and said second semiconductor regions (3) being arranged thus in a zig-zag pattern in diagonal directions of said lattice network. Use of a diode, claimed in any preceding claim, in a commutator circuit. A commutator circuit including a diode claimed in any of claims 1 to 5, connected to respective sources of forward and reverse bias via a switch. A method of producing the diode of claim 1 including: producing a planar semiconductor layer having first and second grains adjoined at a vertical grain boundary (5); diffusing a first type dopant impurity into said semiconductor layer; masking said semiconductor layer by a mask (13) overlapping said grain boundary (5), and a part of said second grain adjacent to said grain boundary (5), the edge of said mask (13) being offset from said grain boundary (5) by a first predetermined distance (c); diffusing a second type dopant minority, opposite in type to said first type, into said second grain, to form a pn junction (6) beneath said mask (13) at a second predetermined distance (d) from the edge of said mask (13), such that said grain boundary (5) shall be offset from said pn junction (6) so as not to cross the same (6) and located to lie beyond the depletion region extending into said first semiconductor region within a minority carrier diffusion length (4) from the depletion edge (12) when said diode is reverse biassed to OFF state condition. A method as claimed in claim 8 wherein said planar semiconductor layer is produced by defining nucleation sites (8) on the surface of a substrate (1), producing a single nucleus (9) of the semiconductor material on both sites (8), epitaxially growing semiconductor material from each nucleus until two grains (10) are grown which meet at a grain boundary (11; 5), and flattening and thinning said grains by grinding.

Inventors: KOIZUMI TORU, MIZUTANI HIDEMASA, KOIZUMI, TORU, MIZUTANI, HIDEMASA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1989
Main classification: H01L29
IPC codes: H01L29, H01L21