Noise immune current mirror circuit

Abstract: A conventional PNP transistor current mirror circuit (10) provides identical first and second reference currents (Ir) each containing the same noise component (which may be due to high frequency supply voltage Vs variations). An input current (Ii) is subtracted from the first reference current to provide a difference current (Id) containing the noise component in the first reference current. An NPN current mirror circuit (20) subtracts the difference current from the second reference current such that the noise component in the difference current cancels the noise component in the second reference current to provide an output current (Io) which is an identical "mirror image" of the input current and which is free of the cancelled noise component.

Description: This invention relates to a current mirror circuit. More particularly, the invention relates to a circuit for providing current mirror operation with enhanced noise immunity. A conventional current mirror circuit is a transistor circuit which produces one or more output currents each of which is a "mirror image" of an input current, that is, each output current is in the same direction as the input current (either both into the mirror circuit or both out of the mirror circuit) and each output current is ratioed to the input current (1:1, n:1, or 1:n). Although current mirror circuits can be constructed with discrete transistors, they are most widely utilized within integrated circuits where the required matching relationships between the transistor devices are more readily effected through integrated circuit processing techniques. Nevertheless, the present invention may be practiced in discrete circuit form as well as integrated circuit form. In a conventional current mirror circuit, a problem can arise in that the current mirror may become a source of noise, meaning that a noise component not present in the input current appears in the output current. As an example, the noise component may be generated by high frequency variations in the supply voltage. This particular source of noise is especially prevalent in integrated circuit current mirrors composed of "lateral" PNP transistor structures, due to the finite bandwidth and parasitic junction capacitances of such devices. The present invention provides a solution to this problem. US-A-4,103,249 discloses a current mirror circuit which provides first and second reference currents. However, as admitted in this document, no provision is made to remove noise components in the circuit. To this end, a current mirror circuit in accordance with the present invention is characterised by the features specified in claim 1. According to one aspect of the invention, a conventional current mirror circuit is utilized to generate first and second identical reference currents each containing the same noise component. An input current is then subtracted from the first reference current to provide a difference current including the noise component. Next, the difference current is subtracted from the second reference current to provide an output current which is an identical "mirror image" of the input current. Advantageously, in the latter subtraction process, the noise component in the difference current cancels the noise component in the second reference current so that the output current is free of the noise component. In another aspect of the invention, the input current and/or the difference current are subtracted from the first and second reference currents, respectively, through the action of a conventional current mirror employing transistors of a conductivity type opposite to the conductivity type of the transistors employed in the current mirror circuit utilized to generate the first and second reference currents. In one embodiment, the invention is realized within a bipolar integrated circuit in which the first and second reference currents are provided by a PNP transistor current mirror circuit and the difference current is subtracted from the second reference current by an NPN transistor current mirror circuit so as to provide a PNP current mirror operation with NPN current mirror noise immunity (which is inherently superior to PNP current mirror noise immunity, assuming "lateral" PNP structures). The present invention will now be described, by way of example, with reference to the following detailed description when taken in conjunction with the accompanying drawings, in which:- Figures 1A through 1F are schematic diagrams of conventional current mirror circuits useful in respect to the invention; Figure 2 is a combined schematic and block diagram of one embodiment of the present invention; and Figures 3A and 3B are graphs depicting the noise immunity improvement brought about by the Figure 2 embodiment of the invention. Referring to Figures 1A through 1F, there are shown six common current mirror configurations. For purposes of illustration, PNP transistors are employed in each configuration. However, it is to be understood that NPN transistors could alternately be employed. In addition, other current mirror configurations are also possible. Each of the Figures 1A through 1F current mirror configurations includes an input leg and output leg (separated by a dashed line for purposes of illustration) connected to a supply voltage Vs. Assuming that the transistors have matched characteristics, the imposition of an input current Ii in the input leg results in the development of a "mirror image" output current Io in the output leg. Additional output currents Io can be developed by simply replicating the output leg of the given current mirror configuration. In the conventional current mirror configurations of Figures 1A through 1F (as well as in other possible current mirror configurations) a problem can arise in that the output current Io may contain a noise component not present in the input current Ii. One source of such noise may be high frequency variations or perturbations in the supply voltage Vs which are translated into the output current Io by the transistors employed in the current mirror. This problem is especially manifest in integrated circuit current mirrors employing "lateral" PNP transistors at supply voltage variations exceeding about 200 KHz (because of the limited bandwidth and parasitic junction capacitances of the PNP devices). The present invention offers a remedy for this problem. Referring to Figure 2, a conventional current mirror circuit 10 includes PNP transistors Q1, Q2 and Q3. PNP transistor Q1 is connected as a diode which forms the input leg of the current mirror circuit 10. The diode Q1 is connected in series with a current sink 12 which establishes an input sink current Is as the input current of the current mirror circuit 10. PNP transistors Q2 and Q3 form dual output legs of the current mirror circuit 10 for providing first and second reference currents Ir as the output currents of the current mirror circuit 10. Owing to the current mirror action of the current mirror circuit 10, the reference currents Ir are proportional (and may be identical) to the input sink current Is. The characteristics of PNP transistors Q2 and Q3 are matched so that the reference currents Ir are identical to each other -- meaning that each of the reference currents Ir contains the same identical noise component, including in particular the same noise component due to high frequency variations in the supply voltage Vs as previously explained. The first and second reference currents Ir are applied to first and second summing nodes 14 and 16, respectively. An input circuit 18 is connected to the first summing node 14 for withdrawing an input current Ii from the first summing node 14 so as to subtract the input current Ii from the first reference current Ir to leave a difference current Id flowing from the first summing node 14. Importantly, the difference current Id includes the noise component contained in the first reference current Ir. It is implicit in the foregoing that the reference currents Ir must exceed the input current Ii. A current mirror circuit 20, composed of matched NPN transistors Q4 and Q5, is responsive to the difference current Id issuing from the first summing node 14 to withdraw the same difference current Id from the second summing node 16 so as to subtract the difference current Id from the second reference current Ir to leave an output current Io which flows from the second summing node 16 into an output circuit 22. As a result of this latter subtraction process, the noise component in the difference current Id cancels the noise component in the second reference current Ir so that the output current Io is free of the cancelled noise component. It will be noted that the output current Io is opposite in direction to the input current Ii, that is, the output current is a "mirror image" of the input current. Accordingly, the circuit of Figure 2 acts as a true current mirror. One use for such a current mirror circuit is as a constant current source. Advantageously, the Figure 2 circuit has enhanced immunity to noise, including noise generated by high frequency variations in the supply voltage Vs. Figures 3A and 3B depict the results of computer simulations of the output current response of the (PNP) current mirror circuit 10 to high frequency variations in the supply voltage Vs, both without the invention (Figure 3A) and with the invention (Figure 3B). Note that the frequency at which noise begins to increase significantly in the output current is more than two orders of magnitude higher with the invention than without the invention. This is due in large part to the higher bandwidth of the NPN transistors in the current mirror circuit 20 as compared to the PNP transistors in the current mirror circuit 10 (assuming fabrication in accordance with common bipolar integrated circuit techniques). In effect, the circuit of Figure 2 provides PNP current mirror operation with NPN current mirror noise immunity. It will be noted that the current mirror circuit 20 is the NPN transistor counterpart of the PNP transistor current mirror circuit illustrated in Figure 1A. However, it is to be understood that the current mirror circuit 20 could just as well be the NPN transistor counterpart of one of the Figures 1B through 1F configurations, or some other current mirror circuit. Further, it will be appreciated that the input circuit 18 may also comprise an NPN transistor current mirror if desired.

Claims: A current mirror circuit (10,20) comprising: first means (10) for providing first and second reference currents (Ir); second means (18) for subtracting an input current (Ii) from the first reference current to provide a difference current (Id); and third means (20) for subtracting the difference current from the second reference current to provide an output current (Io) which is a "mirror image" of the input current; characterised in that the first means comprises a current mirror (Q1-Q3) with two outputs providing two identical reference currents (Ir) each containing the same noise component; such that the difference current (Id) contains the noise component in the first reference current, and such that the noise component in the difference current (Id) cancels the noise component in the second reference current to provide an output current (Io) which is free of the cancelled noise component. A current mirror circuit as claimed in claim 1, wherein the first means includes a current mirror (10) composed of transistors (Q1,Q2,Q3) of one conductivity type; and wherein the third means includes a current mirror (20) composed of transistors (Q4,Q5) of the opposite conductivity type. A current mirror circuit as claimed in claim 2 for a bipolar integrated circuit; wherein the transistors of the one conductivity type are PNP transistors (Q1,Q2,Q3) in which the noise component is due to high frequency supply voltage (Vs) variations; and wherein the transistors of the opposite conductivity type are NPN transistors.

Inventors: GOSE MARK W, GOSE, MARK W.
Applicants: DELCO ELECTRONICS CORP, DELCO ELECTRONICS CORPORATION (A DELAWARE CORP.)
Application year: 1989
Main classification: G05F3
IPC codes: H03F3, H03F1, G05F1, G05F3