Analog-to-digital converter and method

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal. During deintegration of the capacitor by a reference signal the polarity of the error signal is inverted during successive or consecutive deintegration cycles so that the error voltage is self-cancelling in two successive deintegrations and is eliminated from the summed digital output.

Description: This invention is directed to integrating analog-to-digital (A/D) converters and more particularly to dual slope A/D converters having an improved arrangement for offset or correction and to methods of corrected A/D conversion by integration. Dual slope A/D converters designed to achieve optimum conversion accuracy have required and have incorporated arrangements for providing offset and drift voltage correction. A representative drift compensated circuit is described in U.S. Patent No. 3,654,560 issued April 4, 1972 to Cath et al. That patent describes a "rezero" or autozero state during which a feedback loop is closed around a storage capacitor provided for correction purposes. Considerable care is required to properly charge the storage capacitor to an accurate offset level since noise, loop instability, settling time effects, leakage, and capacitor anomalies can all detrimentally affect conversion accuracy. DE-A-2 752 560 and US-A-4 195 283 both disclose analog-to-digital converters in which conversion occurs over two cycles. In the first cycle, a capacitor is charged in response to the input voltage and discharged using a reference voltage, and the reverse occurs during the second cycle. (In US-A-4 195 283, the period in which the reference voltage is applied is subdivided into two sub-periods, between which the polarity of the reference voltage is reversed.) The object is to derive a value, which is a function, inter alia, of the times required to discharge the capacitor, which represents the input voltage and which is unaffected by amplifier offsets. Aspects of the present invention are set out in the accompanying claims. The invention provides a method and apparatus for analog-to-digital conversion, in which a capacitor means is charged over two periods, the charging current in the first period being dependent upon an input voltage and an amplifier offset, and in a second period by the input voltage and the inverse of the amplifier offset, whereby the total accumulated charge is representative of the input voltage substantially unaffected by the offset. The invention may be utilized with an integrating resistor and capacitor and high gain integrating amplifier arranged to integrate an unknown analog signal for a predetermined period of time. As is customary with such arrangements there is an offset error signal associated with the amplifier. According to the invention a switching and control means is provided so that the integrating capacitor is charged for substantially one-half of the predetermined time period with a current which is a function of the level of the analog signal and the level of the error signal. The capacitor is then charged for the remainder of such predetermined time period with a current which is a function of the level of the analog signal and the invert of the level of the error signal so that the capacitor reaches a level of charge which is a function of the level of the analog signal substantially unaffected by the level of the error signal. The net effect of integrating over the cumulative predetermined time period comprised of the two halves is that the total charge placed on the integrating capacitor is identical to the charge which would be present if the offset or error voltage had been zero. That is, the net effect of the offset or error voltage is self-cancelling and the need for the previously conventional corrective storage capacitor is eliminated. In the conventional dual slope analog-to-digital converter the integrated charge on the capacitor is generally converted to a digital signal by generating a digital output which is a function of the time required to de-integrate the capacitor in response to the application of a reference signal or voltage. This reference integration or de-integration is also subject to error as a result of the existence of the offset or error voltage associated with the amplifier. According to another feature of the present invention this error is eliminated in a digital fashion through a switching and control arrangement which inverts the polarity of the error signal during successive or consecutive deintegration cycles so that the error voltage is self-cancelling in two consecutive de-integrations of the capacitor and is eliminated from the summed digital output count. While a summed digital output signal is preferred according to the invention the error is also eliminated with respect to the average of two consecutive counts. The unique features of the invention may be implemented by various circuitry arrangements. Thus according to one embodiment of the invention the polarity of the error signal during the charge cycle may be inverted by inverting the inputs of the integrator amplifier while simultaneously inverting its output. This reversal of polarity occurs at the midpoint of the capacitor charging time period. The reversed polarity may be allowed to remain through deintegration and the first half of the next charge cycle. Re-reversal then occurs to return the polarity to the initial status through the second half of the second charging cycle and through the second deintegration. The error voltage thus cancels itself during both integration cycles and cancels itself from the sum or the average of the de-integration cycles. The inventive arrangement may also be implemented in a circuit such as previously described but wherein a high impedance buffer amplifier is connected between the analog signal input and the input to the integration amplifier. According to this second embodiment of the invention the desired cancelling reversal is achieved by a switching and control arrangement which has the effect of interchanging the integrating and buffer amplifiers at the time of reversal as above described. Still a further circuit arrangement for implementing the invention involves switching and control circuitry for reversing the connections between the integration amplifier and the integration capacitor. Arrangements embodying the invention will now described with reference to the accompanying drawings wherein: Fig. 1 is a simplified schematic diagram of a dual slope analog to digital converter having conventional offset correction circuitry; Fig 2 is a schematic diagram of one embodiment of an A/D converter having an offset correction circuit constructed according to the invention; Fig. 3 is a graphic representation of waveforms showing operation of the improved converter; Fig. 4 is a schematic diagram of another preferred embodiment of an A/D converter constructed according to the invention; Fig. 5 is a schematic diagram of a further preferred embodiment of an A/D converter constructed according to the invention; and Fig. 6 is a simplified diagram of an A/D converter constructed according to the invention in an application wherein it produces a numeric digital display. The improved offset corrected dual slope A/D converter of the invention is better understood in comparison to the construction and operation and limitation of conventional dual slope A/D converters with offset correction. Accordingly a brief description of such a conventional converter or sensor is first provided. Attention is directed to Fig. 1 which illustrates in basic schematic form a known dual slope A/D offset corrected convertor of the general type disclosed in aforementioned United States Patent No. 3,654,560. Referring to Fig. 1 there is shown a dual slope AID converter comprising an integrator operational amplifier ("Op-Amp") 10 having an integrating capacitor C INT connected between the output of the amplifier 10 and the Summing Point P located at the inverting input of the amplifier. The Summing Point P is connected through the integrating resistor R INT and through integrate switch 12 to an input terminal 14 for connection to an unknown voltage V IN to be measured. The switch 12 is shown for purposes of simplicity as a simple electromechanical switch. It will be understood that in a commercial embodiment it would normally take the form of an electronic switch controllable by a suitable control source such as the control logic and clock indicated at 16. The integrate resistor R INT is also connected through a suitable reference voltage integrate switch 18 to a reference voltage source indicated V REF . The reference integrate switch 18 is also controlled by the control logic 16. The junction of the connection to the integrate resistor R INT and the reference integrate switch 18 is connected to a comparator zero or autozero switch indicated at 20. This switch also is under control of the control logic 16. The output of the integrator Op-Amp 10 is fed to the inverting input of a comparator or level crossing detector 22 which has its non-inverting input connecting to ground. The output of the comparator 22 is fed to the control logic 16 for controlling the production of a digital output signal such as by a digital display or readout in a conventional manner not shown in Fig. 1. The output of the comparator is further connected through a zeroing resistor R ZERO and a zero switch 24 to a zeroing capacitor C ZERO . The capacitor C ZERO is connected between the non-inverting input of the integrator amplifier 10 and common or ground. The zero switch 24 is controlled by the control logic 16 as will be understood. The zeroing capacitor C ZERO , zero switch 24 and zero resistor R ZERO is utilized to correct for zero offset voltages of the integrator amplifier 10 and any buffer amplifier (not shown) during autozeroing. During such action the zeroing capacitor C ZERO is placed in a closed loop around the integrator amplifier and comparator and charges to the appropriate offset voltage. During the autozero operation the two zeroing switches 20 and 24 are closed. The input to the integrator resistor R INT is grounded through switch 20. The offset voltage to compensate for the offset of the comparator amplifier 22 is stored on the integrating capacitor C INT , and the offset voltage to compensate for the offset of the integrator amplifier is stored on the zeroing capacitor C ZERO . The result is that the summing point P is brought to zero or ground potential during an ideal autozeroing operation. In practice it is difficult to achieve this ideal situation. It generally takes an appreciable time to store the correct integrator offset voltage because (a) it must be established to be within an error band less than the resolution of the system, and (b) it is subject to the noise in the operational amplifier which conventionally has a high DC gain. Thus, any noise at the input of the device may also be stored on the zeroing capacitor C ZERO so that erroneous storage is possible. This offset correction system is essentially analog in nature and depends on the absolute charge stored on two capacitors. With this arrangement autozero is implemented with two time constants in series, charging the zeroing capacitor C ZERO and the integrate capacitor C INT to store the integrator amplifier offset and comparator offset respectively. Such a use of multiple time constants in series is well recognized as requiring compromises in settling time in order to guarantee loop stability. The foregoing problems are inherent in the conventional autozeroing arrangement for dual slope A/D converters but are very significantly minimized according to the present invention. Pursuant to the invention the analog charging of an offset capacitor is eliminated through use of a unique digital type error cancellation arrangement. Referring to Fig. 2 one embodiment of the new converter is shown in simplified form in order to illustrate the basic difference from the analog approach illustrated in Fig. 1 as used in the prior art. Referring to Fig. 2 an integrator amplifier indicated at A1 is arranged to receive input from an unknown voltage terminal 14 through an integrate switch 12 and integrate resistor R INT . A reference voltage indicated at V REF is arranged to be connected to the integrator amplifier A1 through a reference integrate switch S3 corresponding to the switch 18 in Fig. 1. The output of the integrator amplifier A1 is connected to a comparator Op-Amp A2 whose output is connected to a control logic and clock circuit indicated at 16 in the same manner as the arrangement of Fig. 1. An integrate capacitor C INT is connected to the integrator resistor R INT . The basic differences in circuitry from the conventional arrangement of Fig. 1 are now described. The converter of the invention shown in Fig. 2 is provided with an offset reverse switch shown for convenience as an electromechanical multiple pole switch S1A through S1F. The switch is controlled by the control logic 16 and is arranged to effectively reverse the polarity of offset which can be attributed to integrator amplifier A1. The switches S1A and S1B are connected to the inverting input of the integrator amplifier A1 while the switches S1C and S1D are connected to the non-inverting input of the amplifier A1. The other side (movable contact) of switch S1A is connected to the integrate resistor R INT . The movable contacts of switches S1B and S1C are connected together and to common or ground. The other terminal (movable contact) of switch S1D is connected to the integrate resistor R INT . Switch S1E is connected between the output of the integrator amplifier A1 and the inverting input of the comparator Op-Amp A2. Switch S1F has its stationary contact connected to the non-inverting input of comparator A2. The other movable contact of switch S1F is connected to the output of the integrator amplifier A1 through an inverter or Gain -1 operator 26 which serves to invert the output of the integrator amplifier A1. A comparator zeroing loop is shown connected from the output of the comparator A2 through the zeroing resistor R ZERO , through comparator zeroing switch S2 and integrate resistor R INT . The zeroing switch S2 is controlled by the control logic 16. As it is closed switches 12 and 18 are opened to isolate the comparator zeroing loop from the unknown and reference inputs. Referring to the offset reverse switch S1, it will be seen that as it is shown in Fig. 2 switch S1A is in its normally closed position, switch S1B is in its normally open position, switch S1C is in its normally closed position and switch S1D is in its normally open position. Referring to switches S1E and S1F, switch S1E is in its normally closed position while switch S1F is in its normally open position. Upon actuation of switch S1 the positions are reversed. In the actuated position switch S1A is open, S1B is closed, S1C is open, S1D is closed, S1E is open and S1F is closed. The effect of actuating the offset reverse switch S1 is to reverse the connections to the inverting and non-inverting input of the integrator amplifier A1 and to re-route the output of that amplifier through the inverter or Gain -1 stage 26. The purpose of the inverter or Gain -1 stage 26 is to provide a compensating phase inversion at the output of the integrator amplifier A1 to permit its input to be reversed. Referring to Fig. 3 there is an illustration of the waveforms which result from the unique operation of the A/D converter according to the invention. In this Figure the voltage across the integrate capacitor C INT is plotted against time. The time scale is divided into eight segments indicated as T₁ through T₈ illustrating two cycles or samples. In the timing sequence illustrated in Fig. 3 time period T₁ is an initialization period which establishes the comparator zero crossing level. This time period is somewhat analogous to the prior autozero state except that one offset storage capacitor has been eliminated. This time period is used to permit the integrate capacitor C INT to acquire an initial charge equal to the comparator offset through switch S2 which is closed at this time by the control logic 16. The settling time necessary to establish a comparator zero is an order of magnitude shorter than is the settling time of the prior art which relied on a two time constant autozero loop involving an integrator zeroing capacitor in addition to the integrate capacitor. Such conventional operation has been discussed herein in relation to Fig. 1. Referring to Fig. 3 the first integrate interval T₂ starts from the comparator initialization level. During T₂ the input V IN applied to the integration resistor R INT through switch 12 is effectively added to the offset E OS of the integrator amplifier A1. For the following discussions of Figures 2 and 3, it is assumed that during time interval T₂, the closed contacts of switch S1 are as shown in Figure 2. For the purpose of understanding the slope changes shown in Figure 3, it is also assumed that E OS causes the A1(-) terminal to be more positive than the A1(+) terminal. During the time period T₃ S1 is caused to switch and the offset E OS of amplifier A1 is reversed in polarity effectively causing E OS to be subtracted from V IN . The net effect of integrating over the cumulative time periods T₂ plus T₃ where T₂ is equal to T₃ is that the total charge placed on the integrating capacitor C INT is identical to that charge which would be present if the offset E OS had been zero. That is, the net effect of the offset potential E OS is zero because it is self-cancelling. The average charging current of the integrate capacitor C INT over periods T₂ and T₃ is a function of the level of the analog signal V IN substantially unaffected by the level of the offset voltage E OS . This addition and subtraction of the integrator amplifier offset voltage EOS to the integrated V IN is illustrated in Fig. 3 by an exaggerated change in slope of the integrated signal for purposes of clarity. The offset reverse point which occurs at the transition from time period T₂ to time period T₃ is indicated at REV. As stated, the control is designed so that the reverse point occurs exactly half way through the predetermined integrate cycle established by the controller 16. Thus the integrate capacitor C INT is charged for one-half of the predetermined time period with a current which is a function of the level of the analog signal V IN and the level of the error signal E OS . The capacitor C INT is charged for the remainder of the predetermined period with a current which is a function of the level of the analog signal and the invert of the error signal E OS so that the capacitor reaches a level of charge which is a function of the level of the analog signal V IN substantially unaffected by the level of the error signal E OS . As is customary with conventional A/D converters, the total integrate time is chosen as a multiple of both 50 and 60 Hz line cycle periods to eliminate power line frequency interference. Following the conclusion of the integrate time periods T₂ + T₃ the integration or de-integration of the reference signal V REF occurs as indicated at time period T₄. During this reference integrate period the time count of T4 will be in error by the ratio of E OS to V REF . At this time the reference integrate switch 18 is closed, the integrate switch 12 is open, and the switches S1B and S1D are closed. Switches S1A and S1C are open. The reverse switch S1 is reversed at the mid cycle of T₂ + T₃ but is not reversed at the transition between T₃ and T₄. Thus the same offset E OS is applied during both T₃ and T₄. This creates the effect of rotating the slope of both the T₃ and T₄ ramps in a clockwise direction. The change in slope of the T₃ ramp is offset by the opposite change in the slope of the ramp during T₂. The error which would be caused by this change in the ramp during T₄ is eliminated according to the invention as follows. Following T₄ there is an optional hold indicated at T₅ to permit maintaining a synchronous system relative to the 50 or 60 Hz line. At the end of the hold period T₅ a second sample cycle of integration of V IN commences as indicated at time period T₆. During this time the offset voltage E OS is applied in the same direction as during time periods T₃ and T₄. This is opposite to its polarity during the initial integration time period T₂ in the first cycle. At the end of time period T₆ the reversing switches S1 are reversed to again reverse the polarity of application of E OS . During time period T₆ switches S1A, S1C and S1E are open while switches S1B, S1D and S1F are closed. At the commencement of time period T₇ and continuing through T₈ the switch is reversed so that switches S1A, S1C and S1E are closed and switches S1B, S1D and S1F are open. The slope of the integrate and de-integrate ramps during T₇ and T₈ are modified accordingly in a counter clockwise direction. The slope of the de-integrate ramp representing the integration of the V REF now defines a time period T₈ which is in error by exactly the same amount as previously occurred during T₄ but in the opposite direction. As a result the error is cancelled. The preferred form of analog-to-digital converter of the invention utilizes two minor cycles to provide maximum correction for offset error. This involves summing of at least two cycles and may be advantageously incorporated in the type of summing circuit disclosed in assignee's U.S. Patent No. 4,556,867 issued December 3, 1985. It will be obvious that cycles in addition to two may be summed and that the resolution of the digital indication will be improved in proportion to the number of cycles summed. Means may be provided for correcting the accumulated total from multiple counts as described in detail in said Patent 4,556,867. The effect of this novel methodology and arrangement according to the invention is illustrated in the following mathematical analysis: T 4 T 2 +T 3 = V IN V REF +E OS T 8 T 6 + T 7 = V IN V REF - E OS Solving for (T₄ + T₈), where K = (T₂ + T₃) = (T₆ + T₇) In many practical dual slope converter designs the offset voltage E OS is on the order of 10 millivolts and the reference voltage V REF is one volt. From equation 3 it can be calculated that the resulting measurement error from these typical values is only 0.01% of reading. Further, that error can nearly always be corrected by an initial scale factor calibration adjustment which is needed in any event to account for other component tolerance effects. A still further advantage of the method and apparatus is that troublesome low frequency semiconductor noise of the integrator amplifier is reduced due to translation of the noise spectrum to a higher frequency band than that utilized in prior dual slope implementations. The noise is moved to a higher frequency due to effectively chopping each signal integrate phase at its midpoint. Referring to Fig. 4 there is shown a second and preferred embodiment of the invention. In that Figure there is shown a first amplifier A1 in an integrator Op-Amp circuit which includes an integrate capacitor C INT and integrate resistor R INT . A comparator Op-Amp A2 is connected across the integrate capacitor C INT and has its output connected to control logic and clock 28. A comparator zeroing loop comprising resistor 30 and switch 32 are connected from the output of the comparator amplifier A2 to its inverting input. A high impedance buffer amplifier A3 is connected between the input of the integrator amplifier A1 and the unknown voltage input terminal 14 to which the voltage V IN is connected for measurement. It will be understood by those skilled in the art that it is desirable to utilize a high impedance buffer at the input of the integrator amplifier to avoid undesirable loading. The prior art circuit of Fig. 1 is shown without such an amplifier for simplicity of illustration and description. However, it will be understood that in normal practice such a buffer amplifier would be utilized. In Fig. 2 there was described an embodiment of the invention wherein a digital type cancellation of integrator offset was achieved in a digital manner. According to the arrangement and method of that embodiment of the invention this was achieved by in effect reversing the input connections to the integrator amplifier while inverting its output. The embodiment of the invention illustrated in Fig. 4 provides for digital type cancellation of integrator and buffer amplifier offsets in a modified manner which permits elimination of the inverter or Gain -1 Op-Amp 26 used in the embodiment of the invention illustrated in Fig. 2. According to the preferred embodiment of the invention illustrated in Fig. 4 there is provided in conjunction with the amplifier A1 and amplifier A3 an array of switches to achieve what may be termed an amplifier interchange or swap. According to this embodiment of the invention the switching array is actuated by the control logic 28 to affect a chopping of the integration ramp during the integration of the unknown voltage as is illustrated in Fig. 3 and was described in conjunction with the embodiment of the invention of Fig. 2. This switching has the effect of reversing or interchanging the positions of the amplifiers A1 and A3 at the time of the reversal shown in Fig. 3 at REV. Referring to Fig. 4 it will be seen that amplifier A1 is provided with a three pole double throw switch S4A, B and C. The amplifier A1 and its switches S4A, B and C constitute switching array 34. Similarly amplifier A3 is provided with a three pole double throw switch S5A, B and C. This switch with amplifier A3 comprises the switching array 36. The movable contact of the switch S4A is connected to the inverting input of the amplifier A1 while the movable contact of the switch S4B is connected to the non-inverting input of amplifier A1. The output of amplifier A1 is connected to the movable contact of switch S4C. The amplifier A3 and its switch S5 are similarly connected. Thus switch S5A has its movable contact connected to the non-inverting input of amplifier A3 while the switch S5B has its movable contact connected to the inverting input of amplifier A3. The output of amplifier A3 is connected to the movable contact of switch S5C. The normally closed contact of switch S5C as shown in Fig. 4 is connected to the integrate resistor R INT which in turn is connected to the normally closed contact of switch S4A feeding the inverting input of amplifier A1. The integration resistor R INT is connected to the integration capacitor C INT at the summing point indicated at P. The normally closed contact of switch S4C is connected to the other terminal of the integration capacitor C INT and to the non-inverting input of the comparator A2. The various fixed contacts of the switches S4 and S5 are interconnected by leads or connections 38, 40, 42, 44, 46 and 48 through a suitable interchange or swap bus indicated at 50. It will be seen that with the switches S4 and S5 in the positions indicated in Fig. 4 the input of amplifier A3 is connected through S5A and the integrate switch 12 to the input terminal 14. The inverting input of amplifier A3 is connected through switch S5B and feedback switch 52 to the output of amplifier A3 through switch S5C. This output is connected to the integrating resistor R INT through the hold switch 54 which is in a closed position. These switch positions effectively configure A3 as a unity gain, high impedance, buffer amplifier. Similarly, the switch positions indicated in Figure 4 effectively configure A1 as an integrating amplifier whose time constant equals (R INT x C INT ). The integration resistor R INT is connected to the inverting input of amplifier A1 through switch S4A. The non-inverting input of the amplifier A1 is connected to common or ground through switch S4B. The output of amplifier A1 is connected through switch S4C to the integrate capacitor C INT and to the non-inverting input of the comparator Op-Amp A2. In this configuration the integrating capacitor C INT will charge during the time period T₂ illustrated in Fig. 3 with the offset voltages of amplifiers A1 and A3 being applied in a first direction. This will continue at the ramp slope indicated during T₂ until the reversal REV. At the time of reversal and transition from time period T₂ to time period T₃ the switches S4 and S5 reverse and integrate switch 12 remains closed. The effect of actuation of the. reverse switches S4 and S5 is to effectively interchange or swap the positions of the amplifiers A1 and A3. Integrating capacitor C INT will continue charging through a circuit extending from the input terminal 14 through integrate switch 12, lead 38, interchange bus 50, switch S4A, non-inverting input of amplifier A1 (now acting as a buffer amplifier), output of amplifier A1, switch S4C, lead 48, interchange bus 50, lead 48, hold switch 54, integrate resistor R INT , summing point P and integrate capacitor C INT . The amplifier A3 at this time is connected as an integrate amplifier with its non-inverting input connected through switch S5A to lead 44, interchange bus 50, and lead 44 to input common or ground. Its inverting input is connected through switch S5B, lead 42, interchange bus 50 and lead 42 to summing point P so that the amplifier is in a high gain state to act as the integration amplifier. Conversely the amplifier A1 has its non-inverting input connected through switch S4B, lead 38, interchange bus 50 and lead 38 so that it now performs as a unity gain high impedance buffer. With this interchange of amplifiers A1 and A3 at REV the charging of the integration capacitor C INT continues but at a different ramp slope. The interchange of the amplifiers A1 and A3 has placed their offset voltages on opposite sides of the integration resistor R INT and summing point P. As a result their effect on the rate of charge of the integration capacitor in time frame T₃ is opposite with respect to each amplifier to that which it had during the time period T₂. The result is a digital type cancellation of the effect of the offset error voltage of the amplifiers A1 and A3. At time period T₄ the integrate switch 12 opens, the reference integrate switch 18 closes and the amplifier switches S4 and S5 remain in the position opposite to that shown in Fig. 4. Application of the V REF voltage now causes de-integration as shown by the downward ramp in time period T₄ in Fig. 3. During this time period the amplifier A1 is still acting as a buffer amplifier while amplifier A3 is in the integration amplifier configuration. Cross-over or completion of the de-integration is detected by the comparator A2 and the previously described hold period of T₅ occurs as switches 18 and 54 are opened. At the commencement of time period T₆ the amplifier switches S4 and S5 remain in the same position which is opposite to that shown in Fig. 4. Switches 12 and 54 close to institute a new charge cycle for the integration capacitor C INT . The charge occurs through the amplifiers A2 and A3 in the same interchanged position just described for time periods T₃ and T₄. This results in creation of the ramp shown in time period T₆ in Fig. 3. The net system offset (due to amplifiers A1 and A3) at this time is the same as it was during time periods T₃ and T₄ in the first cycle. At the reversal point REV the amplifiers A1 and A3 are again interchanged through actuation of the amplifier switches S4 and S5 so that those switches return to the position indicated in Fig. 4. The amplifier A3 is now again acting as a unity gain high impedance buffer amplifier and amplifier A1 is acting as a high gain integration amplifier. The respective offset voltages of the two amplifiers have now again been moved to opposite sides of the summing point P so that the effect on the slope of the charging ramp is reversed as shown in the time period T₇ in Fig. 3. This state continues until transition between time periods T₇ and T₈ whereupon switch-over to reference integration or de-integration occurs as indicated in time period T₈ in Fig. 3. The amplifier switches S4 and S5 remain unchanged during this transition from T₇ to T₈ and the slope of the de-integrate ramp as seen in Fig. 3 is different than the corresponding ramp during time period T₄. The offset voltages act in exactly opposite and cancelling polarities in time frames T₄ and T₈ to effect substantial cancellation of the reference de-integration offset voltages during the occurrence of two cycles. The operation of this embodiment is accordingly pursuant to equations 1 through 3. The embodiment of the invention illustrated in Fig. 4 thus achieves the same digital type cancellation of amplifier offset as the embodiment of Fig. 1 but eliminates the necessity for the inverter Op-Amp 26. It will be understood that the actuation of the various switches is performed under control of the control logic 28 via a switch drive line bus 56. Referring to Fig. 5 there is shown a further preferred embodiment of the invention capable of performing the same offset cancellation of the embodiments of Figs. 2 and 4 but with simplified switching circuitry. According to the embodiment of the invention illustrated in Fig. 5 switching is provided to interchange or reverse connection of the integrating capacitor without the necessity for electrical interchange of the buffer and integrator amplifiers. This requires somewhat less switching circuitry and is advantageous in that regard. Referring to Fig. 5 there is shown an A/D converter comprising an integrator amplifier A1, comparator A2 and buffer amplifier A3. The buffer amplifier A3 has its inverting input connectible to the unknown voltage input terminal 12 through switch S6 and is connectible to common or ground through switch S7. The output of buffer amplifier A3 is connectible to the integration resistor R INT and into a feedback loop through switches S8A and B respectively. The feedback loop from the output of buffer amplifier A3 to its inverting input may also be closed through switch S16. The integrator amplifier A1 has its inverting input connected to the integrating resistor R INT and has its non-inverting input connectible through switch S9 to unknown voltage input terminal 12. The non-inverting input of amplifier A1 is also connectible through switch S10 to common or ground. The reference voltage V REF is connectible to the non-inverting inputs of the buffer and integrator amplifiers A3 and A1 through switches S11 and S12 respectively. The integrating capacitor C INT is connectible across the inverting input and the output of the integrating amplifier A1 in a first direction through switches S13A and B and in an opposite direction through switches S14A and B. The terminals of the integrating capacitor C INT are directly connected to the inputs of comparator A2. The output of comparator A2 is connected to a zeroing circuit comprising switch S15 and resistor R ZERO . The output of the comparator is also connected to the control logic in the manner described in connection with the preceding embodiments of the invention. The operation of this embodiment of the invention effectuates integration and de-integration and chopping of the integrate phase to achieve the error cancellation in the manner illustrated by the wave forms in Fig. 3. Referring to Figs. 3 & 5, the integration period T₂ is initiated with switches S6, S13 A and B, S10 and S8A & B closed. All other switches are open. In this configuration the unknown voltage is inputted to the non-inverting input of buffer amplifier A3 and then connected through switch S8A to the integrating resistor R INT and integrating capacitor C INT through switches S13A and B. The integrating capacitor in turn is connected from the inverting input of the integrating amplifier A1 to its output through switches S13A and S13B. The integrating capacitor C INT charges as shown in Fig. 3 during period T₂. At this time the signal or unknown voltage causes current to flow through the integrating resistor R INT into the integrating capacitor C INT in a first direction. Also the offset voltages of the integrating and buffer amplifiers A1 & A3 cause current flow in a first direction. The total current flow caused by the signal to be determined and the offset voltages determines the slope of the ramp during the time period T₂ in Fig. 3. At the mid point REV of the capacitor charging cycle the previously closed switches S6, S10 and S13A & B are opened and switches S9, S7 and S14A & B are closed. With the circuit disposed in this configuration the unknown voltage at terminal 12 is inputted directly to the non-inverting input of amplifier A1 and causes a reversal of the unknown signal current flow in integrate resistor R INT . However this reversal is not seen by the integrate capacitor C INT with respect to the unknown signal current because the connection of the capacitor is reversed with respect to the amplifier A1. On the other hand the current flow due to the amplifier offset voltages is reversed at the summing point P so that the effect of such offset voltages is cancelled during the integrate cycle occurring during time periods T₂ and T₃ and T₆ and T₇. The reversal of the current flow due to the offset voltages during periods T₄ and T₈ is cancelled by totalling the result of two cycles as discussed previously and as analyzed in the foregoing equations 1-3. Comparator zeroing is accomplished during the time period T₁ by closing the switch S15 while switches S13A and B are closed and switches S8A & B are open. Similarly the hold time period T₅ is effected by opening switches S8A & B and simultaneously closing S16 in order that A3 be maintained in a closed-loop configuration. The method and apparatus of the invention may be used in a wide variety of applications as will be apparent to those skilled in the art. Fig. 6 illustrates in simplified diagrammatic form a digital indicating instrument utilizing the improved A/D converter of the invention. Referring to that Figure there is seen a dual slope integrator and switching array 60 having connections for an analog voltage V IN to be measured and a reference voltage V REF . The integrator provides an output to a comparator 62 which is connected to a control logic and clock unit 64 in the manner described in connection with the preceding embodiments of the invention. The clock pulses occurring during the de-integrate cycles for at least two consecutive cycles are counted and stored in the sample counter and these are then accumulated or summed in accumulator 68 as described for example in assignee's U.S. Patent No. 4,556,867. The accumulator 68 provides an input to a decoder and numeric display 70 which produces a visible digital indication of the analog input V IN . It will be apparent from the foregoing that there is provided by the invention an improved integrating A/D converter and method of conversion wherein error signal is eliminated or minimized in digital fashion. The invention may be embodied in other specific forms without departing from the essential characteristics as defined in the claims. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being determined by the appended claims rather than by the foregoing description.

Claims: An integrating analog-to-digital converter comprising differential amplifier means (A1;A1,A3) selectively coupled to both terminals of a capacitor means (C INT ) ; analog signal input means (14); and control means (16;28;64) for: (a) connecting said analog signal input means (14) to said capacitor means (C INT ) for a first predetermined period of time (T₂) to cause a first current to charge said capacitor means (C INT ), said first current being a function of the level of said analog signal and the level of offset error signal in said amplifier means, and (b) connecting said analog signal input means (14) to said capacitor means (C INT ) for a second predetermined period of time (T₃) to cause a second different current to charge said capacitor means, said second current being a function of the level of said analog signal and an invert of the level of offset error signal in said amplifier means, characterised in that the control means is arranged so that the second current charges said capacitor means (C INT ) in the same direction as the said first current, whereby the total charge acquired after the first and second periods of time is a function of the level of said analog signal substantially unaffected by the level of said offset error signal, the control means (16;28;64) being operable to discharge the capacitor means and to provide a digital output signal which is a function of said total charge. A converter according to claim 1, wherein said control means (16;28;64) is operable to discharge said capacitor means (C INT ) at the termination of said first and second predetermined time periods; said capacitor means (C INT ) discharging at a rate which is a function of the charge in said capacitor means and said level of offset error signal; said control means (16;28;64) being effective to cause at least two cycles of charge and discharge of said capacitor means and to cause said capacitor means to discharge at a first current in one of two consecutive cycles and at a second different current in the other of said two consecutive cycles, the first current being a function of the charge of said capacitor means and the level of said offset error signal and the second current being a function of the charge of said capacitor means and an invert of the level of said error signal, said control means (16;28;64) providing a digital signal which is a function of the charge of said capacitor substantially unaffected by the level of said offset error signal. A converter according to claim 1 or 2, wherein said control means (16) is operable to reverse the input connections to said amplifier means (A1) to cause the capacitor means (C INT ) to be charged by said second current, means (26) being provided to invert the output of said amplifier means (A1) during said second predetermined time period (T₃). A converter according to claim 1 or 2, wherein said amplifier means comprises a buffer amplifier means (A3) and an integrator amplifier means (A1); said capacitor means (C INT ) being connected across an input of said integrator amplifier means (A1) and its output; and resistor means (R INT ) connected between said input of said integrator amplifier means (A1) and the output of said buffer amplifier means (A3); said control means (28) being operable for interchanging said buffer amplifier means (A3) and said integrator amplifier means (A1) during said second predetermined time period. A converter according to claim 1 or 2, wherein said amplifier means includes buffer amplifier means (A3) and integrator amplifier means (A1); said capacitor means (C INT ) being connected between an input to said integrator amplifier means (A1) and the output of said integrator amplifier means (A1); and resistor means (R INT ) connected between the output of said buffer amplifier means (A3) and said capacitor means (C INT ) ; said control means being operable for reversing the connections of said capacitor means (C INT ) to said input and output of said integrator amplifier means (A1) during said second predetermined time period. A converter according to any preceding claims including comparator means (A2) connected to said capacitor means (C INT ) for providing an output signal when the potential across said capacitor means (C INT ) is reduced to a predetermined level, and means (S2;S15) for zeroing said comparator means (A2) prior to the commencement of a said predetermined period. A method of analog-to-digital conversion comprising the steps of: (a) charging a capacitor (C INT ) with a current which is a function of the level of an analog signal and the level of an offset error signal; (b) charging said capacitor (C INT ) with a current which is a function of said level of said analog signal and the invert of the level of said offset error signal; (c) discharging said capacitor (C INT ) at a rate which is a function of a reference voltage; and (d) producing a digital signal which is a function of the time required to discharge said capacitor; characterised in that steps (a) and (b) are performed for, substantially, respective halves of a first predetermined time period so that said capacitor reaches a level of charge which is the sum of the charges accumulated in steps (a) and (b) and thus a function of said level of said analog signal substantially unaffected by the level of said offset error signal, the digital signal thus being a function of the time required to discharge the capacitor (C INT ) from this level. A method as claimed in claim 7, wherein, in step (c), the discharging of said capacitor is carried out at a first rate of discharge which is a function of a reference voltage and the level of said offset error signal; the method including the further steps of: (e) charging said capacitor for substantially one-half of a predetermined second time period with a current which is a function of the level of said analog signal and the level of said offset error signal; (f) charging said capacitor for the remainder of said predetermined second time period with a current which is a function of said level of said analog signal and the invert of the level of said offset error signal so that said capacitor reaches a level of charge which is a function of said level of said analog signal substantially unaffected by said offset error signal; and (g) discharging said capacitor at a second rate of discharge which is a function of said reference voltage and the invert of the level of said offset error signal; said digital signal being a function of the time required to discharge said capacitor in said steps (c) and (g). A method according to claim 8, wherein the steps (a) to (c) and (e) to (g) are carried out in the order: (a), (b), (c), (f), (e), (g).

Inventors: BARR ANDREW BRINKLEY, GEORGE RICHARD E, WIESMANN THOMAS W, BARR, ANDREW BRINKLEY, GEORGE, RICHARD E, WIESMANN, THOMAS W.
Applicants: FLUKE MFG CO JOHN, JOHN FLUKE MFG. CO., INC.
Application year: 1989
Main classification: H03M1
IPC codes: H03M1