III-V group compounds semiconductor device Schottky contact

Abstract: A compound semiconductor device comprises: a III-V group compound semiconductor substrate (1,2) and a Schottky junction electrode of a p-type amorphous silicon carbide (a-SiC) layer (5a) provided on the III-­ V group compound semiconductor substrate (1,2) and an amorphous silicon-germanium-boron (a-Si-Ge-B) layer (5b) provided on the p-type amorphous silicon carbide layer (5a). This construction increases the stability of the Schottky junction.

Description: The present invention relates to a compound semiconductor device, more particularly it relates to a gate electrode of a GaAs Schottky gate field effect transistor (GaAs MESFET). A III-V group compound semiconductor, for example, a GaAs crystal, has a band gap of 1.43 eV at room temperature, which is larger than that of silicon, and has a high resistivity of 10⁸ Ω·cm or more. When the GaAs is used as a substrate of a single device and an integrated circuit, the parasitic capacitance is decreased and the elements are easily isolated from each other. Accordingly, GaAs is widely used for forming a transistor, particularly, a MESFET (Metal Semiconductor Field Effect Transistor), HEMT (High Electron Mobility Transistor) or a Schottky diode. Figure 1 shows a cross sectional view of a conventional GaAs MESFET, which comprises a semi-insulating GaAs substrate 1, an n-type GaAs active layer 2 formed on the GaAs substrate 1, a source electrode 3, a drain electrode 4, and a gate electrode 5. To enhance the barrier height between the gate electrode 5 and the n-type GaAs active layer 2, amorphous Si-Ge-B is presently used as a gate electrode material. The barrier height therebetween is about 1.0 eV. However, the Schottky junction between the amorphous Si-Ge-B layer and the GaAs active layer is unstable, and therefore, a threshold voltage (V th ) of the FET after annealing decreases with an elapse of time, as shown in Figure 5. The reason why the Schottky junction becomes unstable is that the Ge in the amorphous Si-Ge-B layer readily reacts with GaAs. IEEE ED-33 (1986) July, No 7, pgs 919-924 concerns such compound semiconductor devices It is desirable to provide a gate electrode in a III-V group compound semiconductor device wherein the barrier height between the amorphous Si-Ge-B layer and GaAs active layer is maintained, and accordingly, the stability of the Schottky junction therebetween is improved. According to one aspect of the present invention, there is provided a compound semiconductor device comprising: a III-V group compound semiconductor substrate; a Schottky junction electrode of a p-type amorphous silicon carbide (a-SiC) layer provided on the III-V group compound semiconductor substrate; and an amorphous silicon-germanium-boron (a-Si-Ge-B) layer provided on the p-type amorphous silicon carbide layer. According to a further aspect of the present invention, there is provided a compound semiconductor device comprising: a III-V group compound semiconductor substrate; an active layer of a III-V group compound semiconductor formed on said substrate; a gate electrode formed on said active layer so as to form a Schottky junction therebetween, said gate electrode including:- an amorphous silicon carbide layer formed on the active layer; an amorphous silicon-germanium-boron layer formed on said amorphous silicon carbide layer; and source and drain electrodes formed on said active layer at both sides of the gate electrode so as to form an ohmic contact to said active layer. Reference is made, by way of example, to the accompanying drawings in which:- Figure 1 is a cross sectional view of an existing GaAs MESFET; Fig.2 is a cross-sectional view of an example of a GaAs MESFET according to the present invention; Figs.3A to 3E are cross-sectional views of steps in the production of the example shown in Fig.2; Fig.4 is a band diagram of a two layer gate electrode obtained by the present invention, and a GaAs substrate; and Fig.5 is a graph illustrating the changes of FET properties, particularly the V th , after annealing at a temperature of 300°C. The preferred embodiments will now be described. Figure 2 is a cross-sectional view of an example of the present invention. In Fig.2, the structure composed of a semi-insulating GaAs substrate 1, an n-type GaAs layer 2, AuGe/Ni source drain electrodes 3 and 4 is the same as the existing structure. The gate electrode 5 has a two-layer structure and consists of a p-type amorphous silicon carbide (a-SiC) layer 5a having a thickness of, for example 800 Å, and an existing-type amorphous Si-Ge-B layer 5b having a thickness of, for example, 3000 Å. The a-SiC layer 5a of the present invention preferably has a thickness of 150 to 1000 Å. The production process of the compound semiconductor shown in Figure 2 will now be explained with reference to Figures 3A to 3E. As shown in Fig. 3A, a GaAs active layer 2 is formed at a surface of a semi-insulating GaAs substrate 1 by implanting n-type ions, e.g., silicon ions therein to a dosage of 10¹⁴ to 10¹⁵ /cm³, whereby an n-type GaAs active layer 2 is formed on the substrate 1. Then a center portion of the n-type GaAs layer 2 wherein a gate electrode is to be formed is etched so that a recess A is formed therein. Then, as shown in Fig. 3B, a p-type amorphous silicon carbide (a-SiC) layer 5a having a thickness of 150 to 1000 Å (10 Å = 1 nm) is formed by a plasma CVD process on the entire exposed surface of the n-type GaAs layer 2 having the recess A, at a growth temperature of from 300 to 450°C using reactive gases, e.g., SiH₄ , CH₄ and B₂H₆ , at a pressure of 0.2 to 2 Torr (1 Torr = 133·3 Pa). A growth temperature of 300 to 450°C is preferably used to prevent the diffusion of arsenic (As) from the n⁻-type GaAs layer 2 during the growth of the p-type a-SiC layer. Then an amorphous silicon-germanium-boron (a-Si-Ge-B) layer 5b having a thickness of about 3000 Å is formed on the p-type a-SiC layer 5a by a reduced pressure CVD process using reactive gases e.g., SiH₄ , GeH₄ and B₂H₆. As the formation process of the a-SiC layer, an ECR (Electron Cyclotron Resonance) CVD using reactive gases Si₂H₆ , C₂H₆ , C₃H₈ may be used, except for the plasma CVD process. After the a-SiC layer and the a-Si-Ge-B layer are formed, a patterned resist 7 is formed over the gate forming region. Then, as shown in Fig 3c, the a-SiC layer 5a and the a-Si-Ge-B layer 5b are dry-etched by using the resist 7 as a mask, and thus a gate electrode 5 composed of the two layers is formed on the n-type GaAs layer 2. Then, as shown in Fig. 3D a patterned resist 7b is formed over the gate electrode 5a, 5b at the recess portion, and a AuGe/Ni metal layer 8 is sputtered on the entire exposed surface. Subsequently, the AuGe/Ni layer 8 on the resist 7b is lifted off, and source and drain electrodes 3 and 4 of AuGe/Ni are formed on the n-type GaAs layer 2 as shown in Fig. 3E. These source and drain electrodes 3, 4 ohmicly contact to said n-type GaAs layer 2. Accordingly a GaAs compound Schottky gate transistor having a gate electrode composed of a p-type a-SiC layer 5a, which prevents a reaction with the GaAs layer, and an a-Si-Ge-B layer 5b can be realized. The obtained GaAs compound MESFET of the GaAs substrate and the two layer electrode composed of the p-type a-SiC layer 5a and the a-Si-Ge-B layer 5b, has a band diagram as shown in Fig. 4. The band gap between the conduction band and the valence band of GaAs is 1.4 eV and the band gap of the p-type a-SiC is 2.0 eV. The barrier height of the p-type a-SiC from the Fermi level is 1.6 eV, which shows that the barrier height is sufficient. When the gate voltage (VG) is applied, since the electric field in the GaAs surface is reduced owing to the existence of p-type a-SiC, the threshold voltage V th is increased. According to this embodiment, as shown in Fig. 5 the FET properties after annealing at a temperature of 300°C, particularly a change of threshold voltage (V th ), are maintained at a substantially constant level even though a time of e.g., 300 min., has elapsed. One reason for this stability may be that the a-SiC is such a hard film that the a-SiC could be a barrier for diffusion of Ge of the Si-Ge-B layer. On the other hand, the threshold voltage of an existing device not having the a-SiC gradually deteriorates, as explained above. Furthermore, according to the above embodiment, a threshold voltage larger than that of the existing device can be obtained. The above-mentioned advantageous points can be realized by providing the a-SiC layer between the existing two layers i.e., GaAs and Si-Ge-B layers, which prevents a diffusion of Ge of the Si-Ge-B layer into GaAs layer, whereby the Schottky junction between the GaAs layer and the gate electrode is stabilized. The present invention may be used not only in the gate electrode of above-explained MESFET but also in the gate electrode of an HEMT having an active layer of GaAs, an electron supply layer of AlGaAs, and a Schottky diode having a substrate of a III-V group compound semiconductor, e.g., GaAs, Al x Ga 1-x As, InP or In x Ga 1-x As, etc.

Claims: A compound semiconductor device comprising: a III-V group compound semiconductor substrate and a Schottky junction electrode consisting of a p-type amorphous silicon carbide (a-SiC) layer provided on the III-V group compound semiconductor substrate and an amorphous silicon-germanium-boron (a-Si-Ge-B) layer provided on the p-type amorphous silicon carbide layer. A compound semiconductor device according to claim 1, wherein the thickness of the p-type a-SiC layer is 150 to 1000 Å (10 Å = 1 nm). A compound semiconductor device according to claim 1 or 2, wherein said III-V group compound semiconductor is one of GaAs, Al x Ga 1-x As, InP and In x Ga 1-x As. A process for forming a compound semiconductor device according to claim 1 or 2 or 3, wherein the p-type a-SiC layer is formed by a plasma or ECR CVD process at a growth temperature of 300 to 450°C. A compound semiconductor device comprising: a III-V group compound semiconductor substrate; an active layer of a III-V group compound semiconductor formed on said substrate; a gate electrode formed on said active layer so as to form a Schottky junction therebetween, said gate electrode including an amorphous silicon carbide layer formed on the active layer and an amorphous silicon-germanium-boron layer formed on said amorphous silicon carbide layer; and source and drain electrodes formed on said active layer at both sides of the gate electrode so as to form an ohmic contact to said active layer.

Inventors: TAKASAKI KANETAKE, TAKASAKI, KANETAKE
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H01L29
IPC codes: H01L29, H01L21