An output circuit of a charge transfer device

Abstract: There is disclosed an output circuit of a charge transfer device including an output section of the charge transfer device which has a floating diffusion region receiving charges transferred through the charge transfer section to detect the quantity of the charges, an output holding section which holds the DC level of the voltage outputted from the output section, a comparing section which compares the DC level held by the output holding section with a reference voltage Vref, and means for applying the output of the comparing section to the floating diffusion region to reset charges in the floating diffusion region.

Description: The present invention relates to an output circuit of a charge transfer device and, more particularly, to an improvement thereof for controlling the DC level of an output signal. The charge transfer device such as a charge-coupled device (CCD) transfers charges through a semiconductor substrate along a channel on which a plurality of electrodes are aligned in a line through a thin insulator film. Charges transferred along the channel are detected in a form of voltage by introducing them into a floating diffusion region formed in contact with the channel. The floating diffusion region is formed in the semiconductor substrate as a diode region to operate as a capacitor element. The capacitor element produces a voltage in accordance with the quantity of the introduced charges. The produced voltage is amplified by a MOS source-follower circuit to derive it as an electrical signal. The electrical signal is supplied to a clamping circuit to remove an affection thereon from the pulses for operating the CCD, and then used in various circuits using the output from the CCD. This output circuit comprising the features of the preamble of claim 1 has been demonstrated by M.H. White et al in a publication of "IEEE JOURNAL OF SOLID-STATE CIRCUITS" Vol. SC-9 (February, 1974), pp 1-12 and is shown in Fig. 1 of the attached drawings in a simplified fashion. The output circuit shown in Fig. 1 includes an output-detection circuit 20 and a clamp circuit 30. The output-detection circuit 20 is formed on a silicon substrate together with a charge transfer region 10 in which a channel is formed for transferring charges. Charges transferred through the channel are injected into a diode 27 which is formed as a floating diffusion region in the charge transfer region 10 in contact with the channel. A change in potential at an electrode P of the diode 27 is detected and amplified by a source follower circuit formed of transistors 22 and 23. Thereafter, the detected and amplified potential change is applied to the clamp circuit 30 having a capacitor 36, a transistor 35 and a buffer amplifier 4, thus obtaining an output the DC level of which is clamped at V CL by the clamp circuit 30. It should be noted that a transistor 21 is a depletion type MOS transistor which functions as a reset transistor of the diode 27 and the reference symbols RD and  R denote a reset drain terminal held at a constant potential and reset pulse for operating the reset transistor 21, respectively. Further, AG denotes a bias voltage for controlling a DC current flowing through the source follower circuit. The DC level of the output voltage V OUT from the output-detection circuit 20 is expressed as follows. If the threshold voltage of the transistor 22 is represented by V T2 , the threshold voltage of the transistor 23 by V T3 , the voltage at the terminal OD by V OD , the voltage at the terminal RD by V RD , the voltage at the terminal AG by V AG , the voltage gain β of the transistor 22 by β₂, and the voltage gain β of the transistor 23 by β₃, the following relationship holds upon condition that the transistors 22 and 23 in the source follower circuit operate in the saturation region: I OD = β₂ (V RD - V OUT - V T2 )² = β₃ (V AG - V T3 )² and from the above expression, the following formula (2) is obtained: V OUT = V RD - V T ₂ - β₃ β₂ (V AG - V T3 ) In the above-described output-detection circuit 20, however, the threshold voltages V T2 and V T3 of the MOS transistors 22 and 23 vary due to variations in the manufacturing process and, therefore, it has heretofore been impossible to adjust the level of the output DC potential V OUT as will be understood from the formula (2). Accordingly, it has heretofore been difficult to connect directly the charge transfer device with a peripheral circuit using the output V OUT . Therefore, it is necessary to interpose the clamp circuit 30 or the like as shown in Fig. 1 in order to control the DC level together with to remove the affection from the pulses for operating the charge transfer region 10. It is, therefore, a primary object of the present invention to provide an output circuit of a charge transfer device producing an output having a controlled amplitude irrespective of manufacturing errors. It is another object of the present invention to provide an output circuit which is connectable to a circuit using the CCD output without interposing a clamp circuit. These objects are achieved by an output circuit as defined in claim 1; the dependent claims are related to further developments of the invention. According to the present invention, since the constant voltage to which the floating diffusion region is reset is controlled by the output holding section, the comparing section and the controlling means, so as to keep the D.C. level of the voltage form output signal at the reference D.C. voltage, it is possible to give a constant and controlled D.C. level to the voltage form output signal even if the threshold voltages of the transistors used vary. Due to this constant and controlled D.C. level, the voltage form output signal can be directly applied to a circuit using the CCD output without interposing any clamp circuit. There is another merit based on the constant and controlled D.C. level that the derived voltage form output signal does not have a noise component which fluctuates the D.C. level of the voltage form output signal by the affection of the pulses for operating the charge transfer device. The above and further object, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a circuit diagram of an output circuit of a charge coupled device in the prior art; Fig. 2 is a circuit diagram of an output circuit of a charge coupled device according to a first preferred embodiment of the present invention; and Fig. 3 is a circuit diagram of an output circuit of a charge coupled device according to a second preferred embodiment of the present invention. Fig. 2 is a circuit diagram showing a first embodiment of the present invention. A charge transfer device is formed on a silicon substrate with a charge transfer region 70 and an output detection circuit 60. The charge transfer region 70 has a channel region on which a plurality of transfer electrodes are formed in series via a thin-insulator film to form a charge coupled device. At an end of the channel region, a diode 67 is formed as a floating diffused region of a conductivity type opposite to the silicon substrate to receive charges transferred through the channel region. The floating diffused region is connected to receive a reset voltage R DB through a reset transistor 61. The ON and OFF of the reset transistor 61 are controlled by a reset pulse  R applied to a gate electrode of the reset transistor 61. By turning the reset transistor 61 ON, charges in the stray capacitance of the diode 67 are reset to the reset voltage V RD at the terminal R DB . After turning the reset transistor 61 OFF, charges transferred through the channel are injected into the stray capacitance of the diode 67. As a result, the voltage at the floating diffusion region changes in accordance with the quantity of injected charges. The obtained voltage is applied to a source-follower transistor 62 to be amplified. A bias-current control transistor 63 is connected to the source electrode of the source-follower transistor 62 as a load. The bias current flowing through the source-follower transistor 62 is controlled by a bias control voltage VAG at a terminal AG. An output signal Vout B is derived from the source electrode of the source-follower transistor 62. In this embodiment, a dummy output circuit 50 is employed to hold the same DC level as the output signal V out B . The DC level held by the dummy output circuit 50 is derived as the output V out A . In the dummy output circuit 50, a diode 57 and transistors 51 to 53 having the same dimensions and impurity concentrations as the diode 67 and the transistors 61 to 63 are connected in the same circuit as the output-detection circuit 60, except for the connection of the gate electrode of the transistor 51, to produce the same DC voltage as the output signal V out B as the output V out A . The same reset voltage V RD the same bias-control voltage V AG and the same power voltage V DD are similarly applied to the terminals RDA, AG and OD in the dummy output circuit 50. The output V out A of the dummy output circuit 50 is compared with a reference voltage V ref . by a comparator 5. The comparison result is commonly applied to the terminals RDA and RDB as the reset voltage V RD . The dummy output circuit 50 and the comparator 5 form a feedback loop to control the level of the output V out A to have a value of the reference voltage V ref . In other words, by the application of the comparison result of the comparator 5, that is, the reset voltage V RD to the terminal RDB, the DC level of the output V out B from the output-detection circuit 60 is controlled to have the value of the reference voltage V ref . The operation of the first preferred embodiment will be described below in more detail. The output V out A of the dummy output circuit 50 is compared with a reference voltage Vref by a comparator 5. Assuming that V out A > V ref , the output voltage of the comparator 5 lowers to lower the reset voltage V RD . When the reset voltage V RD lowers, since the transistor 51 is constantly ON, the gate potential of the source-follower transistor 52 also lowers, resulting in a lowering in the output V out A . The lowering of the output V out A stops when the output V out A becomes equal to the reference voltage Vref. In this way, the DC voltage level of the output V out A is constantly controlled so as to be the same as the reference voltage Vref. Thus, even if the threshold voltage of the transistors 52 and 53 varies, a difference between the threshold voltage and the reference voltage Vref is detected by means of the comparator 5 and the detected difference is applied to the drain of the reset transistor 61 in the output circuit 60 as the reset voltage V RD , thereby enabling the DC level of the output V out B of the output circuit 60 to equal the reference voltage Vref. The dummy output circuit 50 is constructed of the diode 57 and the transistors 51 to 53 having the same dimensions and the same impurity concentrations as those of the diode 67 and the transistors 61 to 63 of the output detection circuit 60 to have the same stray capacitance and the same voltage gains, respectively. The dummy output circuit 50 thus formed of the same constituent elements as the output-detection circuit 60 has the same input-output characteristics as the latter. Therefore, it is possible to effect control such that Vref = V out A = V out B by connecting the output of the comparator 5 to the terminal RDA connected to the drain of the transistor 51 in the dummy output circuit 50 in the same way as in the case of a terminal RDB which is connected to the drain of the reset transistor 61 in the output-detection circuit 60, as shown in Fig. 2. It should be noted that the diode 67 in the output-detection circuit 60 is constituted of a floating diffusion region formed at an end of a channel portion in the charge transfer region 70 and the potential at the node between the diode 67 and the reset transistor 61 is outputted through the source follower circuit formed of the transistors 62 and 63 to be directly applied to a peripheral circuit using the output of the charge transfer region 70 or a CCD device. Fig. 3 is a circuit diagram showing a second preferred embodiment of the present invention. This embodiment differs from the first preferred embodiment shown in Fig. 2 in that a sample-hold circuit (S/H) 2 is employed in place of the dummy output circuit 50 for holding the DC level of the output-detection circuit 40. The sampled voltage and the reference voltage V ref are compared with each other by the comparator 5 to control the reset voltage V RD at the terminal RDC. The basic feedback operation of this embodiment is the same as that of the first embodiment shown in Fig. 2. Thus, the DC level of the output V out C from the output-detection circuit 60 is held at the reference voltage V ref . In the circuit operation of this second embodiment, however, the S/H pulse  SH is synchronized with the reset pulse  R so that, at least during the period when the reset pulse  R is ON, the DC level of the output V out C is sampled to be held, whereas, during the period when a signal involving the charge information is being outputted (i.e., during the period when the reset pulse  R is OFF), the DC level of the output V out C is not sampled. In short, the arrangement is such that the sample-and-hold operation is conducted only during the period when the DC level of the output V out C is being outputted. By conducting the sample-and-hold operation in this way, the sampled DC level is compared with the reference voltage V ref to apply the comparison result to the terminal RDC (drain electrode of the reset transistor 61) as the reset voltage V RD . Due to the feedback operation in a loop of the output-detection circuit 60, the sample-hold circuit 2 and the comparator 5, the DC level of the output V out C is controlled to keep the same level as the reference voltage Vref, similarly to the first preferred embodiment shown in Fig. 2. As the sample-hold circuit 2, any kind of the well-known sample-hold circuit may be used. One example is shown in the above-mentioned publication "IEEE JOURNAL OF SOLID-STATE CIRCUITS" Vol. SC-9 (February 1974) page 4, at the right-hand side of Fig. 5 in which the switch 2 ○ should be formed of a MOSFET. As has been described above, the output circuit of a charge transfer device according to the present invention incorporates a feedback circuit which applies a reset voltage having a controlled potential to a floating diffusion region through a reset transistor for resetting the charges in the floating diffusion region and is, therefore, capable of controlling the DC level of the output signal which varies in accordance with manufacturing error of circuit elements in the output circuit, so that it is advantageously possible to connect the output circuit directly to a peripheral circuit using the output signal. It is a matter of course that it is possible not only to remove the above-described variations in the offset of the output DC voltage but also to control the output DC voltage itself by controlling the drain terminal voltage of the reset transistor and hence possible to effect adjustment for direct connection to the peripheral circuit. The above-described feedback circuit may be applied not only to a floating diffusion type sense amplifier but also to a floating gate type sense amplifier.

Claims: An output circuit of a charge transfer device comprising an output section (60) which includes a floating diffusion region (67) for detecting a quantity of charges transferred through a charge transfer section (70) of said charge transfer device to produce a voltage form signal (P), a signal output section (62, 63) receiving said voltage form signal (P) and producing an output signal (VoutB, VoutC), and resetting means (61) for resetting in response to a reset signal ( R ), said voltage form signal (P) to a reset voltage (V RD ), characterized in that said output circuit further comprises a holding section (2, 50) holding at its output a DC level having a value that is the same as the DC level of said output signal (VoutB, VoutC) at a time when said voltage form signal (P) is reset by said resetting means (61), and a comparing section (5) comparing said DC level held by said holding section (2, 50) with a reference voltage (Vref), and supplying a comparison output to said resetting means (61) as said reset voltage (V RD ). The output circuit as claimed in claim 1, wherein said holding section (50) is a circuit section constituted of the same circuit elements as those of said output section (60) connected in the substantially same circuit configuration as said output section, said circuit elements in said holding section having the substantially same electrical characteristics as those of said output section. The output circuit as claimed in claim 2, wherein said output section (60) and said holding section (50) are constituted of a diode (67, 57), a reset transistor serving as said resetting means (61, 51) and being connected with said diode to periodically reset said voltage form signal (P), and wherein said signal output section (62, 63; 52, 53) comprises a source follower circuit (62, 63) receiving the signal of the point connecting said diode and said reset transistor to produce said output signal (VoutB), said diode (67) in said output section (60) being formed by said floating diffusion region receiving said charges transferred through said charge transfer section (70). The output circuit as claimed in claim 1, wherein said holding section is a sample-and-hold circuit (2) holding the DC level of said output signal (VoutC) by sampling the same. The output circuit as claimed in claim 4, wherein said output section is constituted of a diode formed by said floating diffusion region (67), a reset transistor serving as said resetting means (61) and being connected to said diode to periodically reset said voltage form signal (P), and wherein said signal output section (62, 63; 52, 53) comprises a source follower circuit receiving the signal of the point connecting said diode and said reset transistor, said diode receiving charges transferred through said charge transfer section (70).

Inventors: MIWADA KAZUO, MIWADA, KAZUO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: G11C19
IPC codes: H01L21, G11C19, H03K17, H01L29