Memory comprising a programmable static selection circuit for programmable devices

Abstract: The circuit comprises: a pair of programmable cells connected in series, one conducting, the other one open, with one free terminal connected to the ground and the opposite free terminal connected to a supply voltage; a threshold circuit having one input connected to the node between the two programmable cells, a switching threshold lower than the difference between the supply voltage and the threshold voltage of one of the programmable cells, and an output adapted to assume one of two logic levels depending on whether the tension on the input is higher or lower than the threshold; and a first transistor which is connected between the ground and the opposite end of the pair of programmable cells, is normally off and has a gate which can be driven to make it conduct.

Description: The present invention relates to a programmable static selection circuit to be included in integrated circuits with programmable cells, such as EPROMs, EEPROMs, FLASHs and the like, for example programmable logic devices (also known as PLDs) and analog or hybrid programmable devices. As is known, PLDs (and other similar devices) perform the required logic functions by appropriately programming arrays of programmable cells, some of which are preset for the once-only selection of accessory conditions, such as the definition of the pins as input or output terminals. In order to provide such selections, circuits are known which assume one of two different operative conditions depending on the state (virgin or written) of a preset cell of the integrated device. Said circuits must meet, among other things, the requirement of an extremely reduced or even nil power consumption. Known circuits having this purpose such as the circuit described by San C. Wong et al. in "Logic Arrays and Memories", IEEE International Solid-state Circuits Conference, February 21, 1986, pages 242-243, typically employ capacitors which occupy a considerable silicon area, and since they reach their operative condition by means of a dynamic operation, in extreme conditions of the operating parameters they can assume an undefined state which prevents the correct operation of the PLD. The aim of the invention is therefore to provide a memory comprising a programmable static selection circuit of the above described aim, which has nil power consumption, does not use capacitors and is more reliable than known circuits which have an equivalent function. This aim, as well as other objects and advantages which will become apparent hereinafter, is achieved by a memory comprising a programmable static selection circuit for programmable devices and a pair of programmable cells as defined in claim 1. The invention is now described in greater detail with reference to a preferred embodiment thereof which relates to a PLD implemented in CMOS technology, shown in the accompanying drawings, given only by way of non-limitative example, wherein: figure 1 is a diagram of a known programmable static selection circuit for PLDs; and figure 2 is a diagram of a preferred embodiment of a programmable static selection circuit according to the invention. With reference to figure 1, a cell MC2, having a gate controlled by a line WL2 which is normally connected to the power source, has one terminal connected to the ground and the opposite terminal connected to a circuit which comprises an inverter INV which has its input connected to the positive supply voltage V cc , through a P-channel transistor M3 in parallel with a capacitor C1, and has its output connected to the ground through the parallel arrangement of an N-channel transistor M5 and a capacitor C2. Said transistor M3 is controlled by the output OUT of the inverter INV, while the transistor M5 is controlled by a power-on reset signal. When the power supply V cc is applied, the circuit assumes one of two operative conditions, high output or low output, depending on whether the cell MC2 conducts or is open. With reference to figure 2, which illustrates a circuit according to the preferred embodiment of the invention, a pair of cells MC1 and MC2, which have respective gates controllable by lines WL1, WL2, are connected in series so as to define a voltage divider, with one free terminal connected to the ground and the opposite free terminal connected to a positive supply voltage V cc of 5 V through a diode-connected transistor M1. A second transistor M2 is connected between said opposite terminal and the ground, and its gate is driven by a signal EN with which the transistor M2 can be enabled in order to connect the free terminal of the cell MC1 to the ground when the cells are to be programmed or tested. The output, or intermediate node, of the voltage divider MC1, MC2 is connected, through a transfer transistor M4, to the input of an inverter INV, the output OUT whereof is fedback to the gate of a P-channel pull-up transistor M3 for the input of the inverter INV. The two cells MC1, MC2 always have mutually different programming states, i.e. one must conduct when the other is open. If the cell MC2 of the lower branch conducts (and therefore MC1 is open), the output of the divider is be nil; therefore the output OUT of the inverter is high and keeps the pull-up transistor M3 off. Instead, if MC2 is open (and MC1 conducts), the output of the divider reaches a value equal to the difference between V cc and the cell's threshold voltage. The inverter INV has such dimensions as to have a low switching threshold, safely lower than said value. Thus, in this case, the output OUT is low and enables the pull-up transistor M3 so as to thus raise the input of the inverter to the full logic level. It can be seen that the inverter INV, together with the transistor M3, constitutes a threshold circuit the output whereof switches from one of two logic levels to the other (i.e. between 0 and V cc ) depending on whether the input is higher or lower than the threshold voltage. If the PLD comprises a plurality of programmable circuits of the described kind, which in practice is the norm, the same pair of transistors M1 and M2 can simultaneously feed a plurality of circuits of the above described type. Though two cells are required for the operation of the described circuit, differently from prior circuits having identical purpose which require a single cell, one should not deduce that the circuit causes a greater use of cells, because since the cells are designed in pairs there is an unused cell even in known circuits in any case. This can also be seen in the circuit of figure 1. A preferred embodiment of the invention has been described, but naturally it is susceptible to modifications and variations which are obvious for the expert in the field according to the given teachings. For example, the threshold circuit which comprises the inverter INV and the transistor M3 may be replaced with another circuit having an equivalent function. The transistor M1, instead of being diode-connected, may furthermore be driven by a signal which makes it conduct when M2 is off and vice versa, or may even be replaced by a resistor or by any other switching or current-limiting device. The polarities of the various transistors may also vary with respect to the illustrated ones. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly, such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: A memory comprising a programmable static selection circuit for programmable devices and a pair of programmable cells (MC1,MC2) connected in series, one of said pair of programmable cells (MC1,MC2) having a free terminal connected to the ground, wherein said selection circuit comprises a threshold circuit (INV,M3) having an input connected to the node between said two programmable cells (MC1, MC2), characterized in that the opposite free terminal of the other one of said pair of cells (MC1,MC2) is coupled to a supply voltage (V cc ), one of said programmable cells (MC1,MC2) conducting, the other being open; in that said threshold circuit (INV,M3) has a switching threshold lower than the difference between said supply voltage (V cc ) and the threshold voltage of one of said programmable cells (MC1,MC2), and an output (OUT) adapted to assume one of two logic levels depending on whether the voltage on the input of said threshold circuit is higher or lower than said threshold; and in that a first transistor (M2) is connected between the ground and said opposite terminal of the pair of programmable cells (MC1,MC2) coupled to the supply voltage (V cc ), said first transistor (M2) being normally off and having a gate which can be driven to make it conduct. Memory according to claim 1, characterized in that said threshold circuit (INV,M3) is connected to said node between said two cells (MC1,MC2) through a second transfer transistor (M4). Memory according to claims 1 or 2, characterized in that said threshold circuit (INV,M3) comprises an inverter (INV) which has an output (OUT) and an input coupled to the node between said two programmable cells (MC1,MC2); and a third P-channel transistor (M3) which is connected between the supply voltage (V cc ) and the input of the inverter (INV) and has a gate connected to the output (OUT) of the inverter (INV). Memory according to one or more of claims 1-3, characterized in that said opposite terminal of the pair of programmable cells (MC1,MC2) is coupled to the supply voltage (V cc ) through a current limiter element (M1). Memory according to claim 4, characterized in that said current limiter element (M1) is a resistor. Memory according to one of claims 1-3, characterized in that said opposite terminal of the pair of programmable cells (MC1,MC2) is connected to the supply voltage through a switching device (M1) controlled in a complementary manner with respect to said first transistor (M2). Memory according to claim 6, characterized in that said switching device (M1) is a fourth transistor. Memory according to one or more of claims 1-7, characterized in that the input of the threshold circuit (INV,M3) is coupled to the node between said two programmable cells (MC1,MC2) through a series-connected transfer transistor (M4).

Inventors: CHIRIATTI ANTONIO, MASINI MARCO, CHIRIATTI, ANTONIO, MASINI, MARCO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1989
Main classification: G11C16
IPC codes: G11C16, G11C17