Linear-gain amplifier arrangement

Abstract: A linear-gain amplifier arrangement comprises a current amplifying cell constructed by means of field-effect transistors and comprising a first (M1, M3) and a second (M2, M4) current-mirror circuit whose respective input transistors (M1; M2) and output transistors (M3; M4) constitute a first and a second differential pair. The input transistors (M1; M2) have their drain electrodes connected to a voltage-­ current converter (V/I) comprising field-effect transistors, which supplies difference currents (I in1 , I in2 ) which are square-law functions of the input voltage (U in ) to be amplified. The difference between these input currents (I in1 ; I in2 ) is a linear function of the input voltage (U in ). When the transistors are operated in their saturation regions the difference between the output currents (I out1 ; I out2 ) is also a linear function of the input voltage (U in ). By adding a direct voltage (V c ) to the gate-source voltage of the input and output transistors (M1, M2; M3, M4) or by adding a direct current (I c ) to the respective input currents (I in1 ; I in2 ) the gain can be varied without a change in bandwidth. When the arrangement is constructed as an integrated semiconductor circuit its gain can be made immune to temperature variations and tolerances in the fabrication process.

Description: The invention relates to a linear-gain amplifier arrangement comprising: a current-amplifying cell including a first and a second current-mirror circuit, the first and second current-mirror circuits each comprising a diode-connected input transistor and an output transistor, the input transistors having main current paths arranged to receive difference input currents and the output transistors having main current paths arranged to supply difference output currents, the current-amplifying cell further including means coupled to the cell for defining the gain of the amplifier arrangement by controlling the amplitude ratio of the difference output currents in response of the difference input currents, and a voltage-to-current converter having an input for receiving an input voltage to be amplified by the amplifier arrangement, the voltage-to-current converter having outputs coupled to the main current paths of the input transistors for supplying the difference input currents which are related to said input voltage as a square-law function. Such an amplifier arrangement is known from US-A-4 459 555. In this known amplifier arrangement the means to define the gain is formed by a field effect control transistor having its source-drain path connected across the input terminals of the current mirrors. The current-amplifying cell per se comprising bipolar transistors is described inter alia in "A New Wide-Band Amplifier Technique" by B. Gilbert, IEEE Journal of Solid State Circuits, vol. SC-3, no. 4, December 1968, pp. 353-365. In the technology of electronically amplifying electric signals it is generally known that the bandwidth of an amplifier arrangement can be extended by applying negative feedback. However, a problem is arising when negative feedback is applied to amplifiers is the trade-off between the bandwidth and the linearity of the transfer function. This is because the amplifier arrangement tends to become less stable as the bandwidth is extended by increased negative feedback. Conversely, open-loop amplifier arrangements, which do not employ any form of negative feedback whatsoever have an excellent linearity without a trade-off in bandwidth of the amplifier arrangement. The amplifier arrangement defined in the opening paragraph is of the type without negative feedback and has a wide-band frequency response, a desired linear transfer characteristic, and electronically controllable gain. These properties make the amplifier arrangement very suitable for uses where amplifier arrangements with a linear gain at high frequencies beyond 100 MHz are required. As is generally known, the current in the drain-source path of a field-effect transistor operating in the saturation region has a substantially square-law relationship with the gate-source voltage, so that the desired linear gain cannot be obtained by simply replacing bipolar transistors by field-effect transistors. If the current amplifying cell comprising field-effect transistors is controlled by means of difference currents having a square-law relationship with the input voltage to be amplified it is achieved that the difference between the currents in the drain-source paths of the input transistors, which are arranged as a differential pair, and consequently in the output transistors, which together with said input transistors are arranged in a current-mirror configuration will be a linear function of the input voltage. Voltage-current converters comprising field-effect transistors and supplying output currents having a square-law relationship with the input voltage are known per se and are described inter alia in "A Versatile CMOS Linear Transconductor/Square Law Function Circuit", by E. Seevinck and R.F. Wassenaar, IEEE Journal of Solid-State Circuits, vol. SC-22, no. 3, June 1987, pp. 366-377. In the known arrangement the gain is varied by controlling the resistance of the field effect control transistor, which shortens the differential component of the input currents, thereby leaving the current gain of the current-mirrors unchanged. It is the object of the invention to provide a linear open loop amplifier arrangement of the type defined in the opening paragraph, in which the gain is controlled by changing the internal current gain of the current-amplifying cell. To this end this still further embodiment of the amplifier arrangement in accordance with the invention is characterized in that the source electrodes of the input transistors and the output transistors are commoned to form a common first and second source terminal respectively, means being provided for making the currents in the first and the second source terminal equal to each other, the means for defining the gain of the amplifier arrangement comprising means connnected to a source terminal for supplying a direct current. By making the sum of the currents in the drain source path of the input transistors and the output transistors respectively equal to one another the required linearity of the voltage to current conversion in the output transistors is achieved. By applying an additional direct current it is possible to define the gain of the arrangement. An embodiment of the amplifier arrangement in accordance with the invention is characterized in that the means for making the currents in the first and the second source terminal equal to one another comprise a current-mirror circuit having its input connected to the first source terminal and having its output connected to the second source terminal, and a current-reference circuit connected to the second source terminal to supply the direct current for defining the gain of the amplifier arrangement. For the current-mirror circuit and the current-reference circuit it is possible to employ state-of-the-art field-effect transistor circuits which are known per se and which are suitable for this purpose. In order to provide variable gain an embodiment of the invention is characterized in that the means for defining the gain of the amplifier arrangement are adapted to supply a variable direct current. The gain of the current-controlled amplifier arrangement in accordance with the invention can be rendered independent of temperature variations and fabrication tolerances. To this end a further embodiment of the invention is characterized in that the transistors are biassed by means for applying a direct current, which means have fabrication process and temperature dependence properties comparable to those of the means for applying a direct current for defining the gain of the amplifier arrangement. The invention will now be described in more detail, by way of example, with reference to the accompanying drawings. Fig. 1 shows a basic diagram of the amplifier arrangement in accordance with the invention, in which the gain can be controlled by means of a direct current, and Fig. 2 shows a basic diagram of a prior-art voltage-to-current converter for use in the arrangements shown in Figs. 1 and 2. Hereinafter it is assumed that the field-effect transistors are all of the MOS (Metal Oxide Silicon) type operating in their saturation regions and having their substrate connected to their source electrodes. Fig. 1 shows the basic diagram of an amplifier arrangement in accordance with the invention. The arrangement comprises a current-amplifying cell comprising input transistors M1, M2 and output transistors M3, M4. The two input transistors M1, M2 are connected as diodes, i.e. the gate electrode of the respective transistor is connected to the associated drain electrode. The respective source electrodes of the two input transistors M1, M2 are connected to a common first source terminal 1. The source electrodes of the output transistors M3, M4 are commoned to a second source terminal 2. Thus, the two input transistors and the output transistors in fact constitute a first and a second differential pair respectively. The inputs 3, 4 of the current-amplifying cell thus formed are the drain electrodes of the two input transistors (M1, M2) to which a voltage-to-current converter (VI converter) comprising MOS transistors is connected, which supplies difference currents I in1 , I in2 which are square-law functions of the input voltage U in to be amplified. The output currents in the drain-source paths of the output transistors M3, M4 are referenced I out1 and I out2 respectively. A current-voltage converter, known per se, is connected to the drain electrodes of the two output transistors M3, M4 to convert the difference between the output currents into a suitable output voltage. In principle, the drain electrodes of the transistors M3, M4 may be connected to the V dd voltage supply of the arrangement by means of a resistor. The amplifier arrangement operates as follows. The input currents are assumed to approximately comply with: I in1 = K v (V bias +U in ) 2 I in2 = K v (V bias -U in) 2 where: K v = the transconductance parameter for transistors of the VI converter, V bias = a bias voltage, and U in = the input signal to be amplified. It follows from (1a) and (1b) that the difference between the input currents is a linear function of U in : ΔI in = I in1 -I in2 = 4K v V bias U in As the difference between the input currents constitutes the signal to be amplified, equations (1a) and (1b) are expressed in terms of the difference between the input currents: I in1,2 = I in0 [1 ± ΔI in 4 I in0 ] 2 where the plus sign corresponds to I in1 and the minus sign to I in2 and where I in0 is the input bias current, which for voltage-to-current converters in accordance with equation (1) complies with: I in0 = K v V 2 bias For implicity it is assumed that all the input and output transistors are identical and that initially the drain current I d is equal to: I d = K g (V gs -V th ) 2 for V gs > V th where: K g is the transconductance parameter for the input and output transistors, V gs is the associated gate-source voltage, and V th is the threshold voltage of the field-effect transistor. The input currents in accordance with equation (3) applied to the input transistors, will give rise to gate-source voltages V gs1 , V gs2 for the respective input transistors M1, M2, which after substituting equation (3) in equation (5) and after further reduction of the result thus obtained comply with: V gs1,2 = V th + I in0 /K g ± Δ I in 4 K g I in0 where the plus sign of the ± sign refers to V gs1 and the minus sign to V gs2 . It follows from equation (6) that the difference between the gate-source voltages of the transistors M1 and M2 is directly proportional to the difference ΔI in between the input currents. In order to obtain a linear current gain this voltage difference should be converted linearly into a difference current of the output transistors M3, M4. Now reference is made to the current-mirror circuit 6, which has its input connected to the first source terminal 1 and which has its output connected to the second source terminal 2. The common connection line of the current-mirror circuit 6 is connected to the signal earth of the amplifier arrangement. Further, a current reference element 7 is connected to the second source terminal 2 and is constructed as a current source which is known per se . In its simplest form the current-mirror circuit 6 is identical to, for example, a combination similar to that of the transistors M1 and M3, whose source electrodes are connected to signal earth. The purpose of the use of an additional current-mirror circuit 6 and a current-reference circuit 7 may be explained as follows. The difference ΔI out between the output current of the transistors M3, M4 may be represented as follows by conversion of equation (5): ΔI out = 2K g (I out1 +I out2 ) - 1/2 K g (V gs1 -V gs2 ) 2 (V gs1 -V gs2 ) If the sum of the output currents is made to depend on the difference between the gate-source voltage of the first transistor M1 and the second transistor M2 in conformity with a suitable square-law function the voltage-to-current conversion can be linearised. Substitution of the difference current ΔI in in conformity with equation (6) in equation (3) yields: I in1 +I in2 = 2 I in0 + 1/2 K g (V gs1 -V gs2 ) 2 As a result of the use of the current-mirror circuit 6 the sum of the input currents I in1 and I in2 , as available in the first source terminal 1, will be added to the direct current Ic from the current-mirror circuit 7, so that the sum of the output currents I out1 and I out2 in the second source terminal 2 complies with: I out1 +I out2 = I c +2 I in0 +1/2 K g (V gs1 -V gs2 ) 2 Substitution of equation (9) in equation (7) and inserting the result thus obtained for the gate-source voltages of the transistors Ml and M2 in equation (6) shows that the current gain of this arrangement complies with: A i = ΔI out ΔI in = 1+ I c 2 I in0 Consequently, a linear current amplifier arrangement is obtained whose gain can be controlled with the direct current I c . By making the current-reference element 7 adjustable the gain A i can be controlled over a wide range. The bandwidth of the arrangement is not affected by the control current I c . If the direct current I c and the bias current I in0 are supplied by corresponding circuits the gain A i can be rendered independent of temperature variations and tolerances in the fabrication process of the amplifier arrangement. It will follow from equation (10) that the gain A i = 1 if I c respectively is zero. The arrangement shown in Fig. 1 then operates as a pair of current-mirrors having a bandwidth which is mainly dictated by the transconductance of the input transistors M1, M2 and the capacitance at the input terminals. The gain can be changed by means of I c without a change of said bandwidth because the transconductance of the input transistors and the capacitance at the input terminals is not altered. Experimental results obtained by means of circuits comprising MOS transistor arrays of the type CA3600E show that the bandwidth/gain product of the amplifier arrangement in accordance with the invention for small signals is at least eight times as large as that of the prior-art current-mirror using similar MOS field-effect transistors. It is obvious that the invention is not limited to embodiments comprising N-channel MOS transistors as shown, but that the arrangement can also be constructed by means of P channel field-effect transistors, if required with the use of additional transistors to increase the signal voltage swing of the output transistors, bias resistors etc. The control current I c can be supplied by separate auxiliary circuits, for example, when the arrangement in accordance with the invention is employed for automatic gain control in receivers. Fig. 2 shows a voltage to current converter which is known from the said publication by E.Seevinck et al, comprising field-effect transistors and suitable for use in the arrangement in accordance with the invention. The arrangement basically comprises a matched pair of P-channel transistors Q1 and Q2 whose gate electrodes are connected to input terminals 8, 9 for the application of the input voltage U in to be amplified. For biasing the two transistors Q1 and Q2 the transistor circuits Q3, Q4, Q5 and Q6, Q7, Q8 respectively are provided, which each constitute an N-channel current-mirror pair Q4, Q5 and Q7, Q8, respectively, which via the respective P-channel transistors Q3 and Q6 supply a bias voltage V bias whose value can be varied by means of the bias current I bias applied to the inputs of said current-mirror pairs by the current-reference elements 10, 11. Now the currents I in1 and I in2 are available on the respective drain electrodes of the transistors Q1 and Q2, which currents are in a square-law relationship with the input voltage U in in conformity with equations (1a) and (1b). The circuit further comprises power supply terminals 12, 13 for applying a suitable supply voltage. It will be evident that the invention is not limited to arrangements employing the voltage to current converter described herein or the inverse version thereof but that other suitable voltage to current converters which are known per se may be employed, for example as described in "A Class of Analog CMOS Circuits Based on the Square Law Characteristic of a MOS Transistor in Saturation", by K.Bult and H.Wallinga, IEEE Journal of Solid-State Circuits, vol. SC-22, no. 3, June 1987, pp. 357-365; "Design of Linear CMOS Transconductance Elements" by A. Nedungadi and T.R.Viswanathan, IEEE Trans. Circuits and Systems, vol. CAS-31, no. 10, October 1984, pp. 891-894; "CMOS Voltage-to-Current Transducers" by R.R.Torrance et al, IEEE Trans. Circuits and Systems, vol. CAS-32, no. 11, November 1985, pp. 1097-1104, and "CMOS Transconductance Element" by T.R.Viswanathan, Proc. IEEE, vol. 74, no. 1, January 1986, pp. 222-224.

Claims: A linear-gain amplifier arrangement comprising: a current-amplifying cell including a first (M1, M3) and a second (M2, M4) current-mirror circuit, the first and second current-mirror circuits each comprising a diode-connected input transistor (M1, M2) and an output transistor (M3, M4), the input transistors (M1, M2) having main current paths arranged to receive difference input currents (Iin1, Iin2) and the output transistors (M3, M4) having main current paths arranged to supply difference output currents (lout 1, Iout2), the current-amplifying cell further including means coupled to the cell for defining the gain of the amplifier arrangement by controlling the amplitude ratio of the difference output currents (Iout1, Iout2) in response of the difference input currents (Iin1, Iin2), and a voltage-to-current converter (V/I) having an input (Uin) for receiving an input voltage to be amplified by the amplifier arrangement, the voltage-to-current converter (V/I) having outputs (3, 4) coupled to the main current paths of the input transistors (M1, M2) for supplying the difference input currents (Iin1, Iin2) which are related to said input voltage as a square-law function characterized in that the source electrodes of the input transistors (M1, M2) and the output transistors (M3, M4) are commoned to form a first (1) and second (2) source terminal respectively, means (6) being provided for making the currents in the first (1) and the second (2) source terminal equal to each other and the means for defining the gain of the amplifier arrangement comprising means (7), connected to a source terminal (2), for supplying a direct current. An amplifier arrangement as claimed in Claim 1, characterized in that the means for making the currents in the first (1) and the second (2) source terminal equal to one another comprise a current-mirror circuit (6) having its input connected to the first source terminal (1) and having its output to the second source terminal (2), and said means for supplying a direct current includes a current-reference circuit (7) connected to the second source terminal (2) to supply the direct current for defining the gain of the amplifier arrangement. An amplifier arrangement as claimed in Claim 1 or 2, characterized in that the means for defining the gain of the amplifier arrangement are adapted to supply a variable direct current. An amplifier arrangement as claimed in Claim 1, 2 or 3, characterized in that the transistors (M1, M2, M3, M4) are biassed by means for applying a direct current (6), which means (6) have fabrication process and temperature-dependence properties comparable to those of the means (7) for applying a direct current for defining the gain of the amplifier arrangement. An amplifier arrangement as claimed in any one of the preceding Claims, characterized in that the transistors are all of the insulated-gate type, the amplifier arrangement being constructed as an integrated semiconductor circuit.

Inventors: KLUMPERINK ERIC ANTONIUS MARIA, SEEVINCK EVERT, KLUMPERINK, ERIC ANTONIUS MARIA, SEEVINCK, EVERT
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1989
Main classification: H03G1
IPC codes: H03F3, H03F1, H03G3, H03G1