Semiconductor integrated circuit including output buffer

Abstract: A semiconductor integrated circuit having a test mode in addition to a normal mode, includes a mode detecting circuit (14) for detecting a state of each mode and generating a mode signal, a prebuffer circuit (12) for receiving the mode signal generated by the mode detecting circuit, amplifying an input signal by using an output driving capacity corresponding to the mode signal, and outputting the amplified signal, and an out­ put buffer circuit (13) for receiving an output from the prebuffer circuit and outputting data outside the integrated circuit.

Description: The present invention relates to a semiconductor integrated circuit having a test mode in addition to a normal mode and comprising a mode detecting means for detecting a state of each mode and generating a mode signal, such semiconductor integrated circuit being disclosed in US-A-4 733 168. The known circuit is a test enabling circuit for actuating specific testing circuitry contained within a programmable device, whereby the test enabling circuit and a portion of the normal operational circuits of the device share a common input pin. Because of the dual functionality of the common input pin, the test enabling circuit is designed to respond to a specified test signal, which is either of an opposing polarity, or of a higher magnitude of the same polarity with respect to the normal operational signal. The enabling circuit includes several IGFET devices arranged such that the noise margin of the enabling circuit may be adapted for accommodating varying environments of noise. ESD circuitry is included to protect the testing and test enabling circuits against electrostatic discharge. EP-A-0 087 006 discloses a bit line sense amplifier circuit for an Electrically Alterable Read Only Memory. A reference voltage is produced which tracks a power supply voltage, remaining a threshold voltage away therefrom at all times. The reference voltage is fed to one input terminal of a differential amplifier comparator, the other input terminal of which is connected to the bit line. A voltage clamping circuit is also provided on the bit line which prevents negative excursions of the bit line voltage to a point just below that at which the switch point occurs. A pull-up circuit, which pulls the bit line toward the power supply voltage, supplies an increasing drive capability as the bit line voltage moves toward the switching point and a lesser drive capacity thereafter to prevent excessive excursions of the bit line voltage. A buffer level shifting output circuit converts the output of the differential amplifier to logic levels. A semiconductor integrated circuit (IC), especially a digital IC such as a memory IC or a logic IC receives an external signal or data, performs internal processing such as arithmetic and logic operations, and externally outputs the processing result. For example, a memory IC receives an address or control signal as an input signal. In this memory IC, data prestored at an address designated in accordance with an address signal is read out and output as an output signal from a data output pin. In the memory IC, a large load capacitor having a capacitance of, e.g., 100 pF must be driven by an output buffer arranged at the output stage of the IC. For this reason, an output buffer having a relatively large current driving capacity must be used. The load driving capacity of the output buffer for an IC used in a field requiring higher operation speed must be increased accordingly. This is because the time required for driving an external load capacity is treated as part of an access time. EP-A-0 255 449 discloses a mode detecting means functioning as a switching signal generating circuit. Depending on either a normal operating mode signal or a test signal applied to an input terminal of the mode detecting means, transmission gates are selectively switched ON or OFF, these transmission gates being provided in a test signal generator, an input buffer having an input terminal (for normal operating mode signals), and an output buffer. In this manner, either a test signal is supplied to a test circuit and outputted at a terminal of the output buffer, or a "normal" signal at the input terminal is supplied through a logic circuit and through the output buffer through the output terminal thereof. One of the problems posed during a practical use or a test operation of an IC is generation of noise. That is, when a current flowing through the output buffer in the IC is instantaneously changed, an electromotive force is generated in the power source wiring in the IC, thus generating so-called power source noise. Fig. 1 is a circuit diagram showing a schematic arrangement of an IC mounted on a wiring board. Referring to Fig. 1, a region enclosed by a dotted line corresponds to an IC 90. The IC 90 comprises an internal circuit 91 to which an input voltage Vin is applied and an output buffer 94 having an output stage constituted by p- and n-channel MOSFETs 92 and 93 and adapted to be driven by an output from the internal circuit 91. Reference symbol Vcc denotes a positive power source potential of, e.g., 5 V to be applied to the wiring board; and Vss, a ground potential of 0 V to be applied to the wiring board. The potentials Vcc and Vss to be applied to the board are applied to the inside of the IC through inductance components L1 and L2 as the sums of inductances which are parasitically present in the wiring on the board, the wiring in the IC, the bonding wires in the IC, and the like. A capacitance C1 of an external load is connected between a signal output terminal 95 of the IC and the ground potential Vss; and an internal capacitance C2 of the IC itself, between the power source potential Vcc and the ground potential Vss. The capacitance C1 as an external load to be driven by the output buffer 94 in the IC has a large capacitance of, e.g., about 100 pF, as described above. The above power source noise is generated when the capacitance C1 is driven by the output buffer 94. Assume that the IC shown in Fig. 1 is a memory IC and its input voltage Vin corresponds to one bit of an address signal consisting of a plurality of bits. As indicated by a timing chart in Fig. 2, when address signals are switched, output data Dout from the output buffer 94 is switched from "H" level to "L" level. This operation is called, for example, a "0"-read operation. In this operation, the charge prestored in the capacitance C1 is discharged to the ground potential Vss when the n-channel MOSFET 93 as an output stage of the output buffer 94 is turned on. As a result, the output data Dout is changed from "1" level to "0" level. At this time, a current flowing through the wire of the ground potential Vss changes as shown in Fig. 2. In this case, due to a rate of change (with respect to time) dIss/dt of the ground current Iss and the above inductance component L2, a counter electromotive force L2·dIss/dt is generated in the wire of the ground potential. That is, in the IC, the ground potential Vss rises immediately after the n-channel MOSFET 93 in the output buffer 94 is turned on. Thereafter, the ground potential Vss is attracted to the negative polarity with a decrease in ON current. When no ON current flows, the potential Vss returns to the original 0 V and is stabilized. In contrast to this, in a "1"-read operation when the output data Dout from the output buffer 94 is switched from "0" level to "1" level, the p-channel MOSFET 92 in the output buffer 94 is turned on to charge the capacitance C1, thereby changing the output data Dout from "0" level to "1" level. At this time, a current Icc flowing through the wire of the power source potential Vcc changes as shown in Fig. 2. In this case, due to a rate of change dIcc/dt of the current Icc and the inductance component L1, a counter electromotive force L1·dIcc/dt is generated in the wire of the power source potential, and the power source potential Vcc changes as shown in Fig. 2. As described above, the power source potential Vcc or the ground potential Vss in the IC is changed upon operation of the output buffer. In contrast to this, the input potential Vin is always kept constant regardless of changes in the potential Vcc or Vss on the board. This is because, as shown in Fig. 1, the power source potential Vcc and the ground potential Vss of the other IC (not shown) which generates the input potential Vin are isolated from the IC on the board so as to constitute a different system, and no interaction is present between the power source potentials or ground potentials of the ICs. For this reason, variations in the power source potential Vcc or the ground potential Vss in the IC on the board may cause an error of the IC on the board. For example, as indicated by a timing chart in Fig. 3, when the input voltage Vin is set at a high potential and a potential difference (Vin - Vss) between the input voltage Vin and the ground potential Vss becomes smaller than a threshold voltage VIL on the low-level side of the input-stage transistor of the IC upon variation in the ground potential Vss in the IC, the IC detects the input voltage Vin at this time as a low-level potential. Therefore, at this time, erroneous data is output, and a failure occurs in the IC. In order to suppress noise which is generated when the output buffer is operated in the above-described manner, the following two methods can be provided: (a) to reduce the rate of change dI/dt of the ground current Iss or the power source current Icc, and (b) to reduce the inductance components L1 and L2. Furthermore, in order to reduce the rate of change dI/dt, the following two methods can be provided: (1) to reduce the steepness at the leading or trailing edge of the waveform of an input signal to be supplied to the output buffer, and (2) to reduce the element size of each MOSFET constituting an output stage of the output buffer so as to interfere with the flow of a large current. Method (1) is equivalent to delaying of the timing at which each MOSFET in the output buffer is turned on upon switching of the output data Dout. Method (2) causes a decrease in load driving capacity of the output buffer. In both methods (1) and (2), noise suppression is realized by delaying an access time. Method (a) of reducing dI/dt is to be employed by a manufacture of ICs, whereas method (b) of reducing inductance components is to be employed by a designer of boards. That is, by designing the length of the wiring on a board to be minimum, an inductance component can be reduced. It is not preferable for an IC designed to be operated at high speed to delay the access time. In general, an output buffer is designed to drive a load capacitor as fast as possible, and noise suppression is realized by optimization of a board. In order to obtain a high-speed IC, therefore, generation of a certain amount of noise in an output buffer must be accepted, and a board must be designed not to cause an operation error in spite of the noise. In this case, noise generated during a wafer test such as a die sort test poses the most serious problem. Such a wafer test is generally performed by a test system having an arrangement shown in Fig. 4. More specifically, input data Din, a power source potential Vcc, and a ground potential Vss from a tester 100 are applied to a wafer-like IC 90 set on a probe 101. Output data Dout from the IC 90 is then supplied to the tester 100. The distance from the tester 100 to the probe 101 sometimes becomes very large, e.g., 1 m or more. For this reason, inductance components in the respective wires between the tester and the probe become much larger than those on the board. In low- and intermediate-speed ICs, since generation of noise is suppressed by method (a) described above, substantially no operation error need be considered even in a wafer test operation. However, in high-speed ICs designed assuming that noise suppression can be satisfactorily realized on boards, generation of noise in a wafer test operation poses a problem. More specifically, since a high-speed IC is designed such that the rate of change dI/dt becomes large, variations in the power source potential Vcc and the ground potential Vss to be applied to the IC are greatly increased. For this reason, measurement of such an IC may not be satisfactorily performed by a normal test system using presently available testers and probes. EPROMs and one-time PROMs (OTPs) are known as programmable memory ICs using nonvolatile transistors or the like for memory cells. In such a nonvolatile memory IC, it is known that power source noise tends to be generated when data programming is performed by using a programmer. Hence, noise generated in this programming operation poses a problem. Programming of data in an EPROM is performed in accordance with, e.g., the procedure of a flow chart shown in Fig. 5. More specifically, a power source potential Vcc and a high power source voltage potential Vpp for a write operation are respectively set to be 6.25 V ± 0.25 V and 12.75 V ± 0.25 V. In this state, data programming is performed in units of memory cell bits. Upon programming, verification is performed. After data writing is satisfactorily performed in units of memory cells, the potentials Vcc and Vpp are set at 5 V. The data are read out from all the memory cells to be verified. The word "verification" means an operation of reading out programmed data and confirming it. As described above, in programming, an operation of reading out data in units of bits while the power source potential Vcc is set at about 6.25 V, and an operation of reading out data in units of bits while the high power source voltage potential Vpp is set at about 12.75 V are performed. Various types of EPROM programmers are commercially available. However, all of such programmers are designed for low-noise, intermediate- and low-speed memory ICs, and no satisfactory countermeasure against noise has been taken so as to enable programming of high-speed ICs which generate very large noise. In addition, the amount of noise is increased with an increase in the power source potential Vcc. In the above-described programming operation, a problem is posed especially in a verify operation of reading out data in units of bits after data writing is performed while the power source potential Vcc is set at about 6.25 V. A high potential of 6.25 V causes an output buffer to generate very large noise. For this reason, in addition to the phenomenon that the power source potential vcc and the ground potential Vss greatly vary to change the threshold voltage of the transistor on the input stage, power source noise generated by the output buffer may adversely affect a sense amplifier in a memory, thereby causing an operation error in the sense amplifier. It is, therefore, an object of the present invention to provide a semiconductor IC including an output buffer, which can obtain a sufficiently high operation speed in practical use, can suppress generation of noise in a test operation, and allows satisfactory measurement even by using a normal test system. It is another object of the present invention to provide a semiconductor IC including an output buffer, which can obtain a sufficiently short access time in a normal data read operation, can suppress generation of noise in a verify operation in programming, and allows a satisfactory write operation using a conventional programmer. According to the present invention, there is provided a semiconductor integrated circuit having a test mode in addition to a normal mode, comprising mode detecting means for detecting a state of each mode and generating a mode signal, output buffer means for driving an external load by using a selected driving capacity, thereby outputting data outside the integrated circuit, and prebuffer means for receiving the mode signal generated by the mode detecting means, selecting a driving capacity of the output buffer means and/or the prebuffer means in dependence of the mode signal, amplifying an input signal, and supplying an output to the output buffer means. Preferred embodiments of the present invention are indicated in the dependent claims 2 to 10. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a schematic arrangement of a semiconductor IC mounted on a wiring board; Fig. 2 is a timing chart of the circuit in Fig. 1; Fig. 3 is a timing chart showing the waveforms of signals in the circuit of Fig. 1; Fig. 4 is a circuit diagram showing a test system used to test an IC; Fig. 5 is a flow chart showing an operation procedure for programming data in an EPROM; Fig. 6 is a block diagram showing a schematic arrangement of a semiconductor IC according to a first embodiment of the present invention; Fig. 7 is a circuit diagram showing a detailed arrangement of a part of the semiconductor IC according to the first embodiment; Fig. 8 is a circuit diagram showing an arrangement of a modification of the first embodiment; Fig. 9 is a circuit diagram showing a detailed arrangement of a part of a semiconductor IC according to a second embodiment of the present invention; Fig. 10 is a circuit diagram showing a detailed arrangement of a part of a semiconductor IC according to a third embodiment of the present invention; Fig. 11 is a circuit diagram showing a detailed arrangement of a part of a semiconductor IC according to a fourth embodiment of the present invention; Fig. 12 is a circuit diagram showing a detailed arrangement of a modification of the fourth embodiment; Fig. 13 is a circuit diagram showing a detailed arrangement of a part of the circuit of each of the above embodiments; Fig. 14 is a circuit diagram showing a detailed arrangement of a part of the circuit of each of the above embodiments; Fig. 15 is a block diagram showing a schematic arrangement of a semiconductor IC according to another embodiment of the present invention; and Fig. 16 is a circuit diagram showing a detailed arrangement of a part of the semiconductor IC in Fig. 15. Embodiments of the present invention will be described below with reference to the accompanying drawings. Fig. 6 is a block diagram showing a schematic arrangement of a semiconductor IC according to the present invention. Referring to Fig. 6, reference numeral 11 denotes an internal logic circuit for generating output data in accordance with input data. Two operation modes, i.e., a normal operation mode and a wafer test mode are set in the internal logic circuit 11. An output from the internal logic circuit 11 is supplied to a prebuffer circuit 12. The prebuffer circuit 12 amplifies the output from the circuit 11. An output from the prebuffer circuit 12 is supplied to an output buffer circuit 13. The output buffer circuit 13 outputs data outside the IC in accordance with the output from the circuit 12. Reference numeral 14 denotes a mode detecting circuit. The mode detecting circuit 14 detects the two operation mode states of the internal logic circuit 11 on the basis of an external input signal. A detection output from the mode detecting circuit 14 is supplied to the prebuffer circuit 12. The driving capacity of the prebuffer circuit 12 with respect to the output buffer circuit 13 or that of the output buffer circuit 13 with respect to an external load is set in accordance with the detection output from the mode detecting circuit 14. Fig. 7 is a circuit diagram showing detailed arrangements of the prebuffer circuit 12 and the output buffer circuit 13 in the circuit shown in Fig. 6. In this case, Fig. 7 shows only an arrangement of a circuit associated with one-bit data. However, identical circuits corresponding to the number of required bits are arranged. The prebuffer circuit 12 comprises a first prebuffer circuit 12A and a second prebuffer circuit 12B. The first prebuffer circuit 12A includes a CMOS inverter circuit 21 for receiving one internal data Dout 1′ output from the internal logic circuit 11, and a CMOS inverter circuit 22 for receiving the internal data Dout 1′. The CMOS inverter circuit 22 is controlled in accordance with a wafer test signal WT and its inverted signal WT , and has an output terminal commonly connected to the output terminal of the CMOS inverter 21. The CMOS inverter circuit 22 has two enhancement type p-channel MOSFETs 23 and 24, and two enhancement type n-channel MOSFETs 25 and 26. The source of the MOSFET 23 is connected to a positive power source potential Vcc of, e.g., 5 V. The wafer test signal WT is supplied to the gate of the MOSFET 23. The source and the drain of the MOSFET 24 are respectively connected to the drain of the MOSFET 23 and an output terminal 27 of the CMOS inverter circuit 22. The internal data Dout 1′ is supplied to the gate of the MOSFET 24. The source of the MOSFET 25 is connected to a ground potential Vss of 0 V. The wafer test signal WT is supplied to the gate of the MOSFET 25. The source and the drain of the MOSFET 26 are respectively connected to the drain of the MOSFET 25 and the output terminal 27. The internal data Dout 1′ is supplied to the gate of the MOSFET 26. The second prebuffer circuit 12B includes a CMOS inverter circuit 31 for receiving the other data Dout 2′ output from the internal logic circuit 11, and a CMOS inverter circuit 32 for receiving the internal data Dout 2′. The CMOS inverter circuit 32 is controlled in accordance with the wafer test signal WT and the inverted signal WT , and has an output terminal commonly connected to the output of the CMOS inverter circuit 31. The CMOS inverter circuit 32 has two enhancement type p-channel MOSFETs 33 and 34, and two enhancement type n-channel MOSFETs 35 and 36. The source of the MOSFET 33 is connected to the power source potential Vcc. The wafer test signal WT is supplied to the gate of the MOSFET 33. The source and the drain of the MOSFET 34 are respectively connected to the drain of the MOSFET 33 and an output terminal 37 of the CMOS inverter circuit 32. The internal data Dout 2′ is supplied to the gate of the MOSFET 34. The source of the MOSFET 35 is connected to the ground potential Vss. The wafer test signal WT is supplied to the gate of the MOSFET 35. The source and the drain of the MOSFET 36 are respectively connected to the drain of the MOSFET 35 and the output terminal 37. The internal data Dout 2′ is supplied to the gate of the MOSFET 36. The output buffer circuit 13 comprises a p-channel MOSFET 42 having a source connected to the power source potential Vcc and a drain connected to an output terminal 41 for the data Dout, and an n-channel MOSFET 43 having a source connected to the ground potential Vss and a drain connected to the output terminal 41. An output from the first prebuffer circuit 12A is supplied to the gate of the MOSFET 42. An output from the second prebuffer circuit 12B is supplied to the gate of the MOSFET 43. In the circuit of this embodiment, the conductances of the MOSFETs 42 and 43 in the output buffer circuit 13 are set to be sufficiently large so as to charge and discharge an external load capacitance (not shown) connected to the output terminal 41 at high speed. In addition, in the first prebuffer circuit 12A, the conductances of the respective MOSFETs are set such that the driving capacities of the two CMOS inverter circuits 21 and 22 with respect to the the gate of the p-channel MOSFET 41 are set at a ratio of, e.g., 1 to 9. Similarly, in the second prebuffer circuit 12B, the conductances of the respective MOSFETs are set such that the driving capacities of the CMOS inverter circuits 31 and 32 with respect to the gate of the n-channel MOSFET 43 are set at a ratio of, e.g., 1 to 9. In the circuit having the above-described arrangement, the wafer test signal WT and the inverted signal WT are respectively set at "L" level and "H" level during a normal operation. As a result, in the first prebuffer circuit 12A, both the CMOS inverter circuits 21 and 22 are operated, and the internal data Dout 1′ is inverted by the two CMOS inverter circuits 21 and 22. The inverted data is then supplied to the gate of the p-channel MOSFET 41 in the output buffer circuit 13. Similarly, in the second prebuffer circuit 12B, both the CMOS inverter circuits 31 and 32 are operated, and the internal data Dout 2′ is inverted by the two CMOS inverter circuits 31 and 32. The inverted data is then supplied to the gate of the n-channel MOSFET 43 in the output buffer circuit 13. In this case, if one internal data Dout 1′ is set at "1" level, the output level of the first prebuffer circuit 12A is quickly driven to "0" level by the two CMOS inverter circuits 21 and 22. As a result, the p-channel MOSFET 42 in the output buffer circuit 13 is quickly turned on, and the data Dout output from the output terminal 41 quickly rises to "1" level. In contrast to this, if the other internal data Dout 2′ is set at "0" level, the output level of the second prebuffer circuit 12B is quickly driven to "1" level by the two CMOS inverter circuits 31 and 32. As a result, the n-channel MOSFET 43 in the output buffer circuit 13 is quickly turned on, and the data Dout output from the output terminal 41 quickly falls to "0" level. That is, a sufficiently high operation speed can be obtained in the normal operation mode. An operation of a wafer test will be described below. In the wafer test mode, the wafer test signal WT and the inverted signal WT are respectively set a "1" level and "0" level. At this time, in the first prebuffer circuit 12A, only the CMOS inverter circuit 21 is operated, and the internal data Dout 1′ is inverted. The inverted data is then supplied to the gate of the MOSFET 42 in the output buffer circuit 13. Similarly, in the second prebuffer circuit 12B, only the COMS inverter circuit 31 is operated, and the internal data Dout 2′ is inverted. The inverted data is then supplied to the gate of the MOSFET 43 in the output buffer circuit 13. In this case, the load driving capacities of the two CMOS inverter circuits 21 and 22 of the first prebuffer circuit 12A are set at a ratio of 1 to 9, and the load driving capacities of the two CMOS inverter circuits 31 and 32 of the second prebuffer circuit 12B are set at a ratio of 1 to 9. For this reason, in the wafer test mode, the gate of each of the MOSFETs 42 and 43 in the output buffer circuit 13 is driven by a driving capacity 1/10 that in the normal operation mode. Therefore, the fall or rise time of the output signal from each of the first and second prebuffer circuits 12A and 12B is increased to 10 times that in the normal operation mode, and a rate of change dI/dt (with respect to time) of a current flowing when the MOSFET 42 or 43 in the output buffer circuit 13 is turned on is sufficiently decreased. As a result, noise due to variation in the power source potential Vcc or the ground potential Vss in the IC can be suppressed, and measurement can be satisfactorily performed by a wafer test using the normal test system shown in Fig. 4. Note that since the operation speed is decreased in this wafer test operation, the access time of a memory IC or the like cannot be measured. However, since meansurement of DC characteristics, detection of defective memory cells, and the like are main test items to be performed in the wafer test mode, even if the operation speed of an IC itself is decreased, measurement can be performed without a problem. Fig. 8 is a circuit diagram showing an arrangement of a modification of the circuit of the above-described embodiment. According to the circuit shown in Fig. 7, in order to change the driving capacities with respect to the gates of the p- and n-channel MOSFETs 42 and 43 in the output buffer circuit 13, the first and second prebuffer circuits 12A and 12B are respectively constituted by the CMOS inverter circuits 21 and 31, and the CMOS inverter circuits 22 and 32 whose operations are controlled by the wafer test signals WT and WT . In the circuit of this modification, the first prebuffer circuit 12A is modified as shown in Fig. 8. More specifically, in place of the p-channel MOSFET 23, a depletion type n-channel MOSFET 28 is connected between the power source potential Vcc and the output terminal 27. The wafer test signal WT is supplied to the gate of the MOSFET 28. In addition, in place of the n-channel MOSFET 25, a depletion type n-channel MOSFET 29 is connected between the ground potential Vss and the output terminal 27. The wafer test signal WT is supplied to the gate of the MOSFET 29. In the first prebuffer circuit 12A having the above-described arrangement, if the wafer test signal WT is set at "H" level in the normal operation mode, the ON resistances of the MOSFETs 28 and 29 are sufficiently reduced, and the gate of the p-channel MOSFET 42 in the output buffer circuit 13 can be driven by a sufficiently large driving capacity. In contrast to this, in the wafer test mode, by setting the signal WT at "L" level, the ON resistances of the MOSFETs 28 and 29 can be set to be larger than those in the normal operation mode, and the gate of the p-channel MOSFET 42 in the output buffer circuit 13 can be driven by a smaller driving capacity than that in the normal operation mode. A second prebuffer circuit 12B (not shown) in this modification has the same arrangement as that of the first prebuffer circuit 12A except that the input data Dout 1′ is replaced by the data Dout 2′. Fig. 9 shows an arrangement of a second embodiment of the present invention. Fig. 9 is a circuit diagram showing detailed arrangements of the prebuffer circuit 12 and the output buffer circuit 13 shown in Fig. 6. Similarly, Fig. 9 shows only an arrangement of a circuit portion associated with one-bit data. However, identical circuits corresponding to the number of required bits are arranged. In the circuit of this embodiment, two p-channel MOSFETs 44 and 45, and two n-channel MOSFETs 46 and 47 are arranged in an output buffer circuit 13. In addition, a first prebuffer circuit 12A is constituted by the above CMOS inverter circuit 21 and a CMOS-NAND circuit 30 and a second prebuffer circuit 12B is constituted by the above CMOS inverter circuit 31 and a CMOS-NOR circuit 40. In the output buffer circuit 13, the sources of the p-channel MOSFETs 44 and 45 are connected to a power source potential Vcc, and their drains are connected to an output terminal 41 for data Dout. The sources of the n-channel MOSFETs 46 and 47 are connected to a ground potential Vss, and their drains are connected to the output terminal 41. An output from the CMOS inverter circuit 21 in the first prebuffer circuit 12A is supplied to the gate of the MOSFET 44 in the output buffer circuit 13. An output from the CMOS-NAND circuit 30 in the first prebuffer circuit 12A is supplied to the gate of the MOSFET 45. The internal data Dout 1′ and the wafer test signal WT are supplied to the CMOS-NAND circuit 30. Outputs from the CMOS inverter circuit 31 and the CMOS-NOR circuit 40 in the second prebuffer circuit 12B are respectively supplied to the gates of the MOSFETs 46 and 47 in the output buffer circuit 13. The internal data Dout 2′ and the wafer test signal WT are supplied to the CMOS-NOR circuit 40. In the circuit of this embodiment, the conductances of the two p-channel MOSFETs 44 and 45 in the output buffer circuit 13 are equal to each other, and the sum of the conductances is set to be equal to the conductance of the single MOSFET 42 in the circuit shown in Fig. 7. Similarly, the conductances of the two n-channel MOSFETs 46 and 47 in the output buffer circuit 13 are equal to each other, and the sum of the conductances is set to be equal to the conductance of the single MOSFET 43 in the circuit shown in Fig. 7. In the circuit having the above-described arrangement, the wafer test signal WT and its inverted signal WT are respectively set at "L" level and "H" level in the normal operation mode. As a result, in the first prebuffer circuit 12A, the CMOS-NAND circuit 30 serves as an inverter circuit for inverting the internal data Dout 1′, and hence the internal data Dout 1′ is inverted by the CMOS inverter circuit 21 and the CMOS-NAND circuit 30 to be supplied to the gates of the p-channel MOSFETs 44 and 45 in the output buffer circuit 13 in parallel. Similarly, in the other prebuffer circuit 12B, the CMOS-NOR circuit 40 serves as an inverter circuit for inverting the internal data Dout 2′, and hence the internal data Dout 2′ is inverted by the CMOS inverter circuit 31 and the CMOS-NOR circuit 40 to be supplied to the gates of the n-channel MOSFETs 46 and 47 in the output buffer circuit 13 in parallel. Therefore, if one internal data Dout 1′ is set at "H" level, outputs from both the circuits 21 and 30 in the first prebuffer circuit 12A are at "L" level, and both the MOSFETs 44 and 45 in the output buffer circuit 13 are turned on. As a result, the data Dout at the output terminal 41 quickly rises to "1" level. If the other internal data Dout 2′ is set at "0" level, both the circuits 31 and 40 in the second prebuffer circuit 12B are set at "H" level, and both the MOSFETs 46 and 47 in the output buffer circuit 13 are turned on. As a result, the data Dout at the output terminal 41 quickly falls to "0" level. That is, a sufficiently high operation speed can be obtained in the normal operation mode. In the wafer test mode, the wafer test signal WT and the inverted signal WT are respectively set at "H" level and "L" level. Since outputs from the CMOS-NAND circuit 30 and the CMOS-NOR circuit 40 are always set at "H" level and "L" level, respectively, both the p-channel MOSFET 45 and the n-channel MOSFET 47 in the output buffer circuit 13 are set in an OFF state. For this reason, in the wafer test mode, the rate of change dI/dt of a charge/discharge current flowing when the MOSFET 44 or 46 in the output buffer circuit 13 is turned on is satisfactorily reduced, thereby suppressing noise due to variation in the power source potential Vcc or the ground potential Vss in the IC. Fig. 10 shows an arrangement of a third embodiment of the present invention. Fig. 10 is a circuit diagram showing detailed arrangements of the prebuffer circuit 12 and the output buffer circuit 13 in the circuit shown in Fig. 6. Similarly, Fig. 10 shows only a circuit portion associated with one-bit data. However, identical circuits corresponding to the number of required bits are arranged. An IC of this embodiment is obtained by combining the circuits of the embodiments described with reference to Figs. 7 and 9. The same reference numerals in Fig. 10 denote the same parts as in Fig. 7 and 9, and a description thereof will be omitted. Fig. 11 shows an arrangement of a fourth embodiment of the present invention. Fig. 11 is a circuit diagram showing detailed arrangements of the prebuffer circuit 12 and the output buffer circuit 13 in the circuit shown in Fig. 6. Similarly, Fig. 11 shows only a circuit portion associated with one-bit data. However, identical circuits corresponding to the number of required bits are arranged. In the circuit of this embodiment, similar to the circuit of the embodiment described with reference to Fig. 9, an output buffer circuit 13 is constituted by two p-channel MOSFETs 44 and 45, and two n-channel MOSFETs 46 and 47. However, the conductance of the MOSFET 44 is set to be larger than that of the MOSFET 45, and the conductance of the MOSFET 46 is set to be larger than that of the MOSFET 47. In addition, the circuit of the fourth embodiment is different from the circuit shown in Fig. 9 in that a circuit equivalent to the first prebuffer circuit 12A is constituted by two CMOS-NAND circuits 51 and 52, and a circuit equivalent to the second prebuffer circuit 12B is constituted by two CMOS-NOR circuits 53 and 54. One internal data Dout 1′ and a wafer test signal WT are supplied to the CMOS-NAND circuit 51, and an output therefrom is supplied to the gate of the MOSFET 44 in the output buffer circuit 13. One internal data Dout 1′ and a wafer test signal WT are supplied to the CMOS-NAND circuit 52, and an output therefrom is supplied to the gate of the MOSFET 45 in the output buffer circuit 13. The other internal data Dout 2′ and the wafer test signal WT are supplied to the CMOS-NOR circuit 53, and an output therefrom is supplied to the gate of the MOSFET 46 in the output buffer circuit 13. The other internal data Dout 2′ and the wafer test signal WT are supplied to the CMOS-NOR circuit 54, and an output therefrom is supplied to the gate of the MOSFET 47 in the output buffer circuit 13. In the circuit having the above-described arrangement, the wafer test signal WT and its inverted signal WT are respectively set at "L" level and "H" level in the normal operation mode. Therefore, in the first prebuffer circuit 12A, the CMOS-NAND circuit 51 serves as an inverter, and the internal data Dout 1′ is inverted thereby to be supplied to the gate of the p-channel MOSFET 44 in the output buffer circuit 13. Similarly, in the second prebuffer circuit 12B, the CMOS-NOR circuit 53 serves as an inverter, and hence the internal data Dout 2′ is inverted thereby to be supplied to the gate of the n-channel MOSFET 46 in the output buffer circuit 13. If the internal data Dout 1′ is set at "1" level, an output from the first prebuffer circuit 12A is set at "0" level, and the p-channel MOSFET 44 having a larger conductance in the output buffer circuit 13 is turned on. As a result, data Dout output from an output terminal 41 quickly rises to "1" level. In contrast to this, if the other internal data Dout 2′ is set at "0" level, an output from the second prebuffer circuit 12B is set at "1" level, and the n-channel MOSFET 46 having a larger conductance in the output buffer circuit 13 is turned on. As a result, the data Dout output from the output terminal 41 quickly falls to "0" level. That is, a sufficiently high operation speed can be obtained in the normal operation mode. When a wafer test is to be performed, the wafer test signal WT and the inverted signal WT are respectively set at "H" level and "L" level. At this time, in the first prebuffer circuit 12A, the CMOS-NAND circuit 52 serves as an inverter, and hence the internal data Dout 1′ is inverted thereby to be supplied to the gate of the MOSFET 45 having a smaller conductance in the output buffer circuit 13. Similarly, in the second prebuffer circuit 12B, the CMOS-NOR circuit 54 serves as an inverter, and hence the internal data Dout 2′ is inverted thereby to be supplied to the MOSFET 47 having a smaller conductance in the output buffer circuit 13. As a result, in the wafer test mode, the output terminal 41 is charged/discharged through the MOSFET 45 or 47 having a smaller conductance in the output buffer circuit 13. Therefore, the rate of change dI/dt of a current flowing through the output buffer circuit 13 is sufficiently reduced. Fig. 12 is a circuit diagram showing an arrangement of a modification of the circuit of the embodiment described with reference to Fig. 11. In the circuit of this modification, n-channel MOSFETs 48 and 49 are used in place of the p-channel MOSFETs 44 and 45. That is, the output buffer circuit 13 in the circuit of the modification is constituted by only n-channel MOSFETs. Similarly, in this case, the conductance of the MOSFET 48 is set to be larger than that of the MOSFET 49. In accordance with the above-described modification, a first prebuffer circuit 12A comprises two CMOS-NOR circuits 53 and 54 in place of the CMOS-NAND circuits 51 and 52. Internal data Dout 1′ and a wafer test signal WT are supplied to the CMOS-NOR circuit 53, and the internal data Dout 1′ and a wafer test signal WT are supplied to the CMOS-NOR circuit 54. Fig. 13 shows a circuit for generating the wafer test signals WT and WT used in the circuits of the above-described embodiments. Referring to Fig. 13, reference numeral 61 denotes an input pad to be set at "H" level at the time of the wafer test mode. The input pad 61 is normally set at "L" level of the ground potential Vss by a resistor 62 having a high resistance. When an internal chip enable signal CE′ is set at "L" level, an output from a NOR circuit 63 is set at "H" level; an output from an inverter circuit 64 for inverting the output from the circuit 63, i.e., the wafer test signal WT, at "H" level; and an output from an inverter circuit 65 for inverting the output from the circuit 64, i.e., the inverted signal WT , at "L" level. In the wafer test mode, the input pad 61 is set at "H" level, and the signals WT and WT are respectively set at "L" level and "H" level. Fig. 14 shows another circuit for generating the wafer test signals WT and WT used in the circuit of the above-described embodiments. Referring to Fig. 14, reference numeral 71 denotes an input pad for supplying a normal control signal to the IC. In the wafer test mode, a signal having a level sufficiently higher than that of a normal control signal, i.e., higher than the potentials Vss and Vcc is supplied to the input pad 71. The source-drain paths of two p-channel MOSFETs 72 and 73 and one n-channel MOSFET 74 are connected in series between the input pad 71 and the ground potential Vss. One input terminal of a NAND circuit 75 is connected to the node between the MOSFETs 73 and 74. A predetermined bias voltage Vb is applied to the gate of the MOSFET 73. When an internal chip enable signal CE′ is set at "L" level and a voltage which is higher than the bias voltage Vb by the sum of the threshold voltages of two p-channel MOSFETs is applied to the input pad 71 in the wafer test mode, an output from the NAND circuit 75 is set at "L" level; an output from an inverter circuit 76 for inverting the output from the circuit 75, i.e., the wafer test signal WT, at "H" level; and an output from an inverter circuit 77 for inverting the output from the circuit 76, i.e., the signal WT , at "L" level. A case wherein the present invention is applied to a programmable nonvolatile memory IC having a normal data read mode and a programming mode accompanied by a verify operation will be described below. Fig. 15 is a block diagram showing a schematic arrangement of a nonvolatile memory IC to which the present invention is applied. Referring to Fig. 15, reference numeral 15 denotes a programmable memory circuit using nonvolatile transistors as memory cells. A data read mode for performing a normal data read operation and a programming mode for performing data programming are set in the memory circuit 15. In the programming mode, a verify operation is performed with a high power source voltage as described above. Data read out from the memory circuit 15 is supplied to a prebuffer circuit 12 in the same manner as in the circuit in Fig. 6. The prebuffer circuit 12 amplifies the data read out from the memory circuit 15. An output from the prebuffer circuit 12 is supplied to an output buffer circuit 13. The output buffer circuit 13 externally outputs the readout data on the basis of the output from the prebuffer circuit 12. Reference numeral 14 denotes a mode detecting circuit. The mode detecting circuit 14 detects the two operation mode states of the memory circuit 15 on the basis of an external input signal. A detection output from the mode detecting circuit 14 is supplied to the prebuffer circuit 12. The driving capacity of the prebuffer circuit 12 with respect to the output buffer circuit 13 or the driving capacity of the output buffer circuit 13 with respect to an external load is set in accordance with the detection output. The prebuffer circuit 12 and the output buffer circuit 13 of the nonvolatile memory IC having the above-described arrangement respectively have the same arrangements as those of the circuits of the IC in Fig. 6 using the first and second prebuffer circuits shown in Fig. 7, 9, 10, 11, 12, or 8. According to this nonvolatile memory IC, however, data read out from the memory circuit 15 are supplied as the internal data Dout 1′ and Dout 2′. In addition, the wafer test signals WT and WT are used as signals representing the read mode and the programming mode. An operation of the circuit of this embodiment which employs circuits having the arrangements shown in Fig. 7 as a prebuffer circuit 12 and an output buffer circuit 13 will be described below. In the normal data read mode, the detection signal WT from the mode detecting circuit 14 is set at "L" level; and the signal WT , at "H" level. At this time, in the first prebuffer circuit 12A, the internal data Dout 1′ is inverted by two CMOS inverter circuits 21 and 22. In the second prebuffer circuit 12B, the internal data Dout 2′ is inverted by two CMOS inverter circuits 31 and 32. As a result, in this case, the load driving capacity of the prebuffer circuit 12 with respect to the output buffer circuit 13 is increased, and output data Dout quickly rises to "1" level or quickly falls to "0" level. That is, when a normal data read operation is to be performed in the memory circuit 15, since the output buffer circuit 13 is driven by the prebuffer circuit 12 with a sufficiently large capacity, the access time can be satisfactorily shortened. An operation of the programming mode will be described below. When this mode is set, the detection signal WT from the mode detecting circuit 14 is set at "1" level; and the signal WT, at "0" level. At this time, in the first and second prebuffer circuits 12A and 12B, the CMOS inverter circuits 22 and 32 do not operate. That is, the internal data Dout 1′ and Dout 2′ are respectively inverted by only the CMOS inverter circuits 21 and 31. Hence, each of the MOSFETs 42 and 43 of the output buffer circuit 13 is driven by a driving capacity 1/10 that in the normal data read mode. Therefore, a rate of change dI/dt of a current flowing when the p-channel MOSFET 42 or the n-channel MOSFET 43 in the output buffer circuit 13 is turned on is satisfactorily reduced. As a result, noise due to variation in the power source potential Vcc or the ground potential Vss in the IC can be suppressed. Even if programming is performed by using an EPROM programmer for low or intermediate speed, the problem of an operation error due to noise need not be considered, and a verify operation can be satisfactorily performed. Note that a verify operation in the programming mode is normally performed while the operation speed is decreased, and hence measurement of an access time cannot be performed. However, since a verify operation to be performed by an EPROM programmer is designed to check whether a sufficient amount of data is written in each selected cell, no problem is posed in measurement performed while the operation speed of an IC itself is decreased. A detailed arrangement of a circuit for generating the signals WT and WT used by the above-described non-volatile memory IC will be described below with reference to Fig. 16. The power source potential Vcc or the high power source voltage potential Vpp can be used as a factor for detecting the operation mode of the memory circuit 15. More specifically, as described with reference to the flow chart in Fig. 5, when a verify operation in the programming mode is performed, the value of the power source potential Vcc is increased from 5 V in the normal data read mode to about 6.25 V, and the value of the high power source voltage potential Vpp is increased from 5V in the normal data read mode to about 12.7 V. Therefore, mode detection can be performed by detecting the value of the potential Vcc or Vpp. Fig. 16 shows a circuit arrangement of a mode detecting circuit 14 for performing mode detection by detecting the value of the high power source voltage potential Vpp. More specifically, two p-channel MOSFETs 82 and 83 and one n-channel MOSFET 84 are connected in series between an input terminal 81 for receiving the potential Vpp and the ground potential Vss. Two CMOS inverters 86 and 87 are series-connected to a node 85 of the MOSFETs 83 and 84. The gate and the drain of the MOSFET 82 are connected to each other. The power source potential Vcc is applied to the gates of the MOSFETs 83 and 84. The detection signal WT is obtained as an output from the inverter 86, and the detection signal WT is obtained as an output from the inverter 87. Note that a conductance βp of each of the p-channel MOSFETs 82 and 83 is set to be sufficiently larger than a conductance βn of the n-channel MOSFET 84. In this mode detecting circuit, in the normal data read mode, a voltage of 5 V is applied to the input terminal 81. At this time, since Vpp - 2Vthp ≦ Vcc (where Vthp is the threshold voltage of each p-channel MOSFET), the MOSFET 83 is turned off. However, since the MOSFET 84 is turned on, the potential of the node 85 set at the potential Vss of 0 V. As a result, the detection signal WT output from the inverter 86 is set at "H" level, and the detection signal WT output from the inverter 87 is set at "L" level. In the programming mode, a voltage of about 12.75 V is applied to the input terminal 81. At this time, since Vpp - 2Vthp > Vcc, the MOSFET 83 is turned on. In addition, the MOSFET 84 is turned on. However, since βp > βn, the voltage at the node 85 is increased to a high voltage near the potential Vpp. As a result, the detection output WT from the inverter 86 is set at "L" level, and the detection output WT from the inverter 87 is set at "H" level. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor integrated circuit having a test mode in addition to a normal mode, comprising: mode detecting means (14) for detecting a state of each mode and generating a mode signal; and output buffer means (13) for driving an external load by using a selected driving capacity, thereby outputting data outside said integrated circuit; characterized by pre-buffer means (12) for receiving the mode signal generated by said mode detecting means, selecting a driving capacity of said output buffer means (13) and/or the prebuffer means (12) in dependence of the mode signal, amplifying an input signal, and supplying an output to said output buffer means (13). A circuit according to claim 1, characterized in that said pre-buffer means comprises: a first pre-buffer circuit (12A) including a first CMOS inverter circuit (21) for receiving a first input signal (Dout 1′), and a CMOS-NAND circuit (30) for receiving the first input signal (Dout 1′) and a first mode signal ( WT ), and a second pre-buffer circuit (12B) including a second CMOS inverter circuit (31) for receiving a second input signal (Dout 2′), and a CMOS-NOR circuit (40) for receiving the second input signal (Dout 2′) and a second mode signal (WT); and said output buffer means (13) comprises: a first MOSFET (44) of a first conductivity type having a source, a drain, and a gate respectively connected to the first potential (Vcc), an output terminal (41) for data, and an output terminal of said first CMOS inverter circuit, a second MOSFET (45) of the first conductivity type having a source, a drain, and a gate respectively connected to the first potential (Vcc), the output terminal (41) for data, and an output terminal of said CMOS-NAND circuit, a third MOSFET (46) of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential (Vss), the output terminal (41) for data, and an output terminal of said second CMOS inverter circuit, and a fourth MOSFET (47) of the second conductivity type having a source, a drain, and a gate respectively connected to the second potential (Vss), the output terminal (41) for data, and an output terinal of said CMOS-NOR circuit. A circuit according to claim 1, characterized in that said pre-buffer means (12) comprises: a first pre-buffer circuit (12A) including a first CMOS inverter circuit (21) for receiving a first input signal (Dout 1′), a second CMOS inverter circuit (22) for receiving the first input signal (Dout 1′), said second CMOS inverter circuit having an output terminal commonly connected to an output terminal of said first CMOS inverter circuit and being controlled in accordance with first and second mode signals (WT, WT ), and a CMOS-NAND circuit (30) for receiving the first input signal (Dout 1′) and the second mode signal ( WT ), and a second pre-buffer circuit (12B) including a third CMOS inverter circuit (31) for receiving a second input signal (Dout 2′), a fourth CMOS inverter circuit (32) for receiving the second input signal (Dout 2′), said fourth CMOS inverter circuit having an output terminal commonly connected to an output terminal of said third CMOS inverter circuit and being controlled in accordance with the first and second mode signals (WT, WT ), and a CMOS-NOR circuit (40) for receiving the second input signal (Dout 2′) and the first mode signal (WT); and said output means (13) comprises: a first MOSFET (44) of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential (Vcc), an output terminal (41) for data, and the common output terminal of said first and second CMOS inverter circuits, a second MOSFET (45) of the first conductivity type having a source, a drain, and a gate respectively connected to the first potential (Vcc), the output terminal (41) for data, and an output terminal of said CMOS-NAND circuit, a third MOSFET (46) of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential (Vss), the output terminal (41) for data, and the common output terminal of said third and fourth CMOS circuits, and a fourth MOSFET (47) of the second conductivity type having a source, a drain, and a gate respectively connected to the second potential (Vss), the output terminal (41) for data, and an output terminal of said CMOS-NOR circuit. A circuit according to claim 1, characterized in that said pre-buffer means (12) comprises: a first pre-buffer circuit (12A) including a first CMOS-NAND circuit (51) for receiving a first input signal (Dout 1′) and a first mode signal ( WT ), and a second CMOS-NAND circuit (52) for receiving the first input signal (Dout 1′) and a second mode signal (WT), and a second pre-buffer circuit (12B) including a first CMOS-NOR circuit (53) for receiving a second input signal (Dout 2′) and the second mode signal (WT), and a second CMOS-NOR circuit (54) for receiving the second input signal (Dout 2′) and the first mode signal ( WT ); and said output buffer means (13) comprises: a first MOSFET (44) of a first conductivity type having a source, a drain, and a gate respectively connected to the first potential (Vcc), an output terminal (41) for data, and an output terminal of said first CMOS-NAND circuit, a second MOSFET (45) of the first conductivity type having a source, a drain and a gate respectively connected the first potential (Vcc), the output terminal (41) for data, and an output terminal of said second CMOS-NAND circuit, a third MOSFET (46) of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential (Vss), the output terminal (41) for data, and an output terminal of said first CMOS-NOR circuit, and a fourth MOSFET (47) of a second conductivity type having a source, a drain, and a gate respectively connected to the second potential (Vss), the output terminal (41) for data, and an output terminal of said second CMOS-NOR circuit. A circuit according to claim 1, characterized in that said pre-buffer means (12) comprises: a first pre-buffer circuit (12A) including a first CMOS-NOR circuit (53) for receiving a first input signal (Dout 1′) and a first mode signal (WT), and a second CMOS-NOR circuit (54) for receiving the first input signal (Dout 1′) and a second mode signal ( WT ), and a second pre-buffer circuit (12B) including a third CMOS-NOR circuit (52) for receiving a second input signal (Dout 2′) and the first mode signal (WT), and a fourth CMOS-NOR circuit (40) for receiving the second input signal (Dout 2′) and the second mode signal ( WT ); and said output buffer means (13) comprises: a first MOSFET (48) of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential (Vcc), an output terminal (41) for data, and an output terminal of said first CMOS-NOR circuit, a second MOSFET (49) of the first conductivity type having a source, a drain, and a gate respectively connected to the first potential (Vcc), the output terminal (45) for data, and an output terminal of said second CMOS-NOR circuit, a third MOSFET (46) of the first conductivity type having a source, a drain, and a gate respectively connected to a second potential (Vss), the output terminal (41) for data, and an output terminal of said third CMOS-NOR circuit, and a fourth MOSFET (47) of the first conductivity type having a source, a drain, and a gate respectively connected to the second potential (Vss), the output terminal (41) for data, and an output terminal of said fourth CMOS-NOR circuit. A circuit according to claim 1, characterized in that said pre-buffer means comprises: a first pre-buffer circuit (12A) including a first CMOS inverter circuit (21) for receiving a first input signal (Dout 1′), and a second CMOS inverter circuit (22) for receiving the first input signal (Dout 1′), said second CMOS inverter circuit having an output terminal commonly connected to an output terminal of said first CMOS inverter circuit and being controlled in accordance with first and second mode signals (WT, WT ), and a second pre-buffer circuit (12B) including a third CMOS inverter circuit (31) for receiving a second input signal (Dout 2′), and a fourth CMOS inverter circuit (32) for receiving the second input signal (Dout 2′), said fourth CMOS inverter circuit having an output terminal commonly connected to an output terminal of said third CMOS inverter circuit and being controlled in accordance with the first and second mode signals (WT, WT ); and said output buffer means (13) comprises: a first MOSFET (42) of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential (Vcc), an output terminal (41) for data, and the common output terminal of said first and second CMOS inverter circuits (21, 22); and a second MOSFET (43) of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential (Vss), said output terminal (41) for data, and the common output terminal of said third and fourth CMOS inverter circuits (31, 32). A circuit according to claim 6, characterized in that each of said second and fourth CMOS inverter circuits (22, 32) comprises: an enhancement type first MOSFET (23; 33) of the first conductivity type having a source, a drain, and a gate, the source being connected to the first potential (Vcc), and the first mode signal (WT) being supplied to the gate; an enhancement type second MOSFET (24; 34) of the first conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said first MOSFET and an output terminal, and the first or second input signal being supplied to the gate; an enhancement type third MOSFET (25; 35) of the second conductivity type having a source, a drain, and a gate, the source being connected to the second potential (Vss), and the second mode signal being supplied to the gate; and an enhancement type fourth MOSFET (26; 36) of the second conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said third MOSFET and the output terminal, and the first or second mode signal being supplied to the gate. A circuit according to claim 6, characterized in that each of said first and second CMOS inverter circuits (22, 23) comprises: a depletion type first MOSFET (28) having a source, a drain, and a gate, the source being connected to the first potential (Vcc), and the mode signal ( WT ) being supplied to the gate; an enhancement type second MOSFET (24) of the first conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said first MOSFET and an output terminal, and the first or second input signal being supplied to the gate; a depletion type third MOSFET (29) having a source, a drain, and a gate, the source being connected to the second potential (Vss), and the mode signal ( WT ) being supplied to the gate; and an enhancement type fourth MOSFET (26) of the second conductivity type having a source, a drain, and a gate, the source of the drain being respectively connected to the drain of said third MOSFET and the output terminal, and the first or second input signal being supplied to the gate. A circuit according to claim 1, characterized in that said pre-buffer means (12) receives a signal from a programmable non-volatile memory circuit (15) having a normal data read mode and a programming mode accompanied by a verify operation.

Inventors: ATSUMI SHIGERU INTELLECTUAL PR, IMAMIYA KENITI INTELLECTUAL PR, MIYAMOTO JUNICHI INTELLECTUAL, OHTSUKA NOBUAKI INTELLECTUAL P, TANAKA SUMIO INTELLECTUAL PROP, ATSUMI, SHIGERU INTELLECTUAL PROPERTY DIVISION, IMAMIYA, KENITI INTELLECTUAL PROPERTY DIVISION, MIYAMOTO, JUNICHI INTELLECTUAL PROPERTY DIVISION, OHTSUKA, NOBUAKI INTELLECTUAL PROPERTY DIVISION, TANAKA, SUMIO INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G01R31
IPC codes: G06F11, G11C29, G11C7, G01R31