Current switch logic circuit with controlled output signal levels

Abstract: A current switch emitter-follower logic circuit allows both the UP output logic level and the DOWN output logic level to be independently controlled with respect to a fixed reference voltage so as to permit very small output level swings. A feedback circuit (40) generates two different control signals (V CS , V CCC ) which are independently variable and are input to a control circuit (42) and to a logic circuit (1) to compensate for fluctuations in power supply voltages, temperature and circuit parameters. These control signals are applied to a variable current source within the logic circuit and to a dynamic resistance within the control circuit to compensate almost instantaneously to fluctua­ tions in power supply voltage, temperature or circuit device parameters, maintaining the logic circuit output levels close to reference levels so as to permit small output signal swings. The output logic levels need not be symmetrical around a central reference point.

Description: Background of the Invention The present invention relates to logic circuit networks, and more particularly to a circuit for compensating for significant fluctuations in power supply, circuit and environmental parameters. A purpose of the invention is to maintain close control over logic signal levels, in order to permit a reduced output signal swing. Yet more specifically, the invention pertains to a current switch emitter-follower (CSEF) logic circuit network having an associated control circuit which includes a dynamic, controllable resistance and a controllable current source. The resistance and the current source are controlled, respectively, by two independently variable control signals for independently adjusting the CSEF output logic signal levels. The network operates in such a way that the logic UP and DOWN levels of the logic circuit output are held to be essentially constant about a reference voltage with little or no additional power consumption and using a low-voltage power supply, despite significant fluctuations in the power supply voltage, temperature or parameters of the circuit devices. Because of this stability in the UP and DOWN levels, extremely small logic signal levels can be used, thus allowing the circuit switching speed to be increased and the circuit power to be decreased. Current switch emitter-follower logic circuits are known. Typical prior art CSEF circuits are disclosed in U.S. Pat. No. 4,575,647 (FIG. 1), in U.S. Pat. No. 4,709,169 (Col. 1), in US. Pat. No. 3,501,647, and in FIGS. 1 and 2 herein. A detailed description of the operation of a typical prior art CSEF logic circuit is useful for understanding the present invention. Accordingly, turning to the drawings, FIG. 1 is a simplified block diagram of a logic circuit 1, having logic signal inputs and outputs, power supply voltage input terminals and an optional control signal input. Logic circuit 1 may comprise a standard CSEF circuit (sometimes referred to as emitter coupled logic, or ECL) performing one or more logical functions such as OR, NOR, NAND, etc. This circuit will typically have one or more logical signal inputs and one or two logical signal outputs. In a two-output case, one output will typically be the logical complement of the other. Standard CSEF circuits, being active devices, also require one or more sources of power for operation, which are normally supplied by positive and negative voltages from a power supply, commonly designated as V CC and V EE . Other voltages, sometimes called reference voltages, V T and V Ref , are also supplied, generally from the same power supply. V Ref could also be of ground potential. The various inputs, outputs and voltage attachments of the prior art logic circuit 1 are shown in more detail in FIG. 2. In the circuit of FIG. 2, which illustrates an n-input OR/NOR gate, input transistors 12, 14 and 16 are provided in a parallel configuration for receipt of one or more logical signal inputs. Although three input transistors are shown, a greater or lesser number may be employed. The bases of transistors 12, 14 and 16 are connected to input terminals IN₁, IN₂ ... IN n for receipt of the input logic signals, which are typically binary signals arbitrarily designated as UP or DOWN. The commonly connected collectors of transistors 12, 14 and 16 are coupled through a resistor 26 to a terminal to which a positive power supply voltage V CC is applied. Transistors 12, 14 and 16 are connected in a differential amplifier configuration with a fourth transistor 18, the collector of which is coupled through a resistor 28 to the V CC terminal. The base of transistor 18 is connected to a first logic level reference voltage V Ref , here assumed to be ground although other potentials may be used. The emitters of all four transistors 12, 14, 16 and 18 are commonly connected to the collector of a fifth transistor 22, the latter device serving as a constant current source for the differential amplifier circuit. The emitter of transistor 22 is connected through a resistor 32 to a second power supply terminal to which a negative supply voltage V EE is applied. A second logic level reference voltage or control signal V CS may be applied to the base of transistor 22. In some prior art circuits, signal V CS may be used to provide limited control over the DOWN level of the output signals. Two output transistors 10 and 20 are typically provided in the prior art circuit of FIG. 2, both of these being connected in an emitter-follower configuration with their emitters coupled through resistors 24 and 30, respectively, to another, secondary power supply voltage terminal, V T . The base input to transistor 10 is supplied from the commonly connected collectors of transistors 12, 14 and 16, while the base input to transistor 20 is supplied from the collector of transistor 18. The emitters of the transistors 10 and 20 are connected to output terminals OUT₁ and OUT₂, respectively. The operation of the circuit of FIG. 2 is well known. When at least one of the input signals applied to the terminals IN₁, IN₂ ... IN n is in the UP (positive) level, the corresponding transistor 12, 14, or 16 is turned on, thereby causing most of the current which flows through the constant current source transistor 22 to flow through the respective transistor 12, 14 or 16 and the resistor 26. Transistor 18 is then off and transistor 20 on, thereby causing the output signal on the terminal OUT₂ to be at the UP level. The voltage at the base of transistor 10 is lower than the voltage at the base of transistor 20, and therefore terminal OUT₁ is at the DOWN level. In this manner, the logical OR of the signals on the input terminals IN₁, IN₂ ... IN n is produced on the terminal OUT₂ and the logical NOR of those signals on the terminal OUT₁. In a typical CSEF logic network, many circuits such as the one shown in FIG. 2 are contained on a single integrated circuit chip. Power is supplied from a remote power supply located "off-chip". The power supply voltages V CC , V EE , V T and V Ref , usually all taken from the same supply, are normally intended to be held constant, but in practice some fluctuations will occur since these voltages provide large variable currents to a large number of logic circuits. A typical fluctuation in a nominal value of + 1.4 volts for V CC might be ± 85 mv. Fluctuations in V CC and/or V EE will, in turn, give rise to fluctuations (noise) in the output levels of the logic circuits, adversely affecting circuit performance. Because of these fluctuations, the relative UP and DOWN output levels at transistors 10 and 20 of the prior art circuits must be kept rather high, typically on the order of ± 350 mv, to overcome the power supply noise and coupled signal noise to ensure successful communication between circuits on the chip. This, in turn, has a tendency to limit the switching speed of the circuit because large signal swings generally require longer turn-on and turn-off times for the circuit components. Fluctuations in environmental factors, such as temperature, and in circuit component parameters, such as resistance and transistor gain, also adversely affect the performance of the circuit by requiring large signal swings to overcome this type of noise. Different schemes have been proposed in the prior art for stabilizing or compensating for fluctuations in the primary power supply voltages V CC or V EE or for fluctuations in temperature or device parameters. These schemes typically employ either a current source controller, a voltage divider or a Schottky barrier diode clamp. Only partial compensation, however, is achieved, or other disadvantages are present, either because changes in V CC or other voltages cannot be accurately tracked, or only a center reference level is tracked, or only one of the two logic output levels may be adjusted, or no accurate temperature or device parameter compensation is achieved, or a relatively high voltage power supply must be used. In Ashton et al. U.S. Patent No. 4,575,647, a control signal V CS is generated for input to the base of the current source transistor (such as transistor 22 in the prior art circuit of FIG. 2 herein). This signal, together with back-to-back Schottky barrier diodes, causes the output UP and DOWN levels to be maintained around a center reference voltage in symmetrical fashion. A drawback of this approach, however, is that only one point of control is provided. Merely varying V CS by itself does not permit the independent tracking and control of each output level. Also, a symmetrical output is not always advantageous, and the use of a single control signal does not permit full compensation for all changes in V CC , temperature or device parameters. In addition, the output signal cannot be reduced below the forward drop of the diode 44 of that patent. Ashton et al. U.S. Patent No. 4,709,169 discloses a different circuit and method for controlling CSEF output levels. There, extra current is drawn, as needed, through resistors 26 or 30 of FIG. 1 (analogous to resistors 26 and 28 of FIG. 2 herein). A Schottky barrier diode is also employed. A disadvantage of this scheme, however, is that extra capacitance is added to the critical output nodes 10 and 12 of FIG. 1 (analogous to the bases of transistors 10 and 20 of FIG. 2 herein). Another disadvantage is that extra power is required to drive this circuit. Other output level control devices are described in Masaki U.S. Patent No. 3,778,646 and in Betts et al., "Emitter-Coupled Logic Circuit", IBM Technical Disclosure Bulletin, Vol. 15, No. 7, Dec. 1972, at pp. 2178-79. These devices, however, suffer from various disadvantages such as the inability to compensate for changes in the V CC supply or the inability to independently control both the UP and DOWN levels. Thus, because the prior art regulatory schemes do not fully compensate for changes in power supply levels, temperature or device parameter fluctuations, the UP and DOWN levels produced by the circuits must be kept relatively large with respect to the logic signal reference level (ground in the case of the circuit of FIG. 2 herein). This is, of course, undesirable in that the nominal noise margin and consequently the speed of the circuit is adversely affected. The present invention is intended to remedy the above-mentioned disadvantages, and provide a current switch logic circuit, the output signal swing of which is reduced to a minimum and the UP and DOWN levels are made substantially insensitive to power supply voltage fluctuations, junction temperatures and absolute device parameters. Thus, maximum speed and minimum power dissipation are achieved simultaneously. Summary of the Invention The problem to be solved by the present invention is to improve the insensitivity of a logic circuit network to the power supply voltage fluctuations, junction temperatures and device parameters. This problem is solved by the invention as claimed in claims 1 and 3. Briefly, the present invention comprises a logic circuit network for producing an adjustable first logic level and a different adjustable second logic level in response to at least one input signal, comprising: a logic circuit having at least one input terminal, an output terminal, a complement output terminal, at least one power supply terminal for receiving power, circuit components having parameters and a first control terminal; a control circuit coupled to the logic circuit and having a second control terminal; means for independently generating a first control signal and a second control signal responsive to changes in the power supply, temperature and logic circuit component parameters; and means for supplying the control signals to the first and second control terminals, respectively, so as to maintain the first and second logic levels at different predetermined reference levels despite changes in the power supply, temperature and logic circuit component parameters. In the embodiment of present claim 1, the control circuit comprises: a load resistor, a controllable dynamic resistance connected across the resistor, comprising one or more transistors of one type; a controllable current amplifier comprising one or more transistors of the opposite type, connected to control the dynamic resistance; and means for applying a signal to the current amplifier to change the dynamic resistance in order to keep a logic signal level constant with respect to a reference voltage. An alternative arrangement is defined in claim 3 and recites the use of a field effect transistor which is connected as a controllable dynamic resistance and which replaces the combination of the load resistance and the bipolar transistor. In a further embodiment of the present invention, the logic circuit comprises a compensated current switch emitter-follower circuit having a controllable current source coupled to a differential amplifier configuration driving emitter-follower output transistors. The first and second control signals, input to the logic circuit and control circuit respectively, are generated by a control signal generator including circuits employing logic level reference and sample generators in a feedback loop arrangement. The present invention further includes a method for producing an adjustable first logic level and a different adjustable second logic level in response to at least one input signal, comprising the steps of: generating a first control signal and a second control signal, each of which is a function of at least one power supply voltage, temperature and parameters of circuit devices; and independently controlling the first and second logic levels by way of the first and second control signals, respectively, so as to maintain the first and second logic levels at different predetermined reference levels. The use of the feedback controlled signal generator and the dynamic resistance holds the UP and DOWN output logic levels independent of power supply and environmental conditions over a significant range. This allows the nominal output signal swing to be reduced without reducing the worst case signal swing. In addition, the output levels need not be symmetrical with respect to any reference level, and relatively low power supply voltages may be used. In simulation, it has been found that the reduced signal swing can thus permit the circuit to easily achieve a 20% performance (speed) improvement over standard CSEF logic circuits. Brief Description of the Drawings FIG. 1 is a block diagram of a typical prior art CSEF logic circuit. FIG. 2 is a schematic circuit diagram of the logic circuit of FIG. 1. FIG. 3 is a block diagram of one embodiment of the present invention. FIG. 4 is a schematic circuit diagram of one embodiment of FIG. 3. FIG. 5 is a block diagram of one embodiment of a feedback circuit of the present invention which may be utilized to generate the control signals V CCC and V CS for input to the circuits of FIGS. 3 and 4. FIG. 6 is a schematic circuit diagram of one embodiment of the reference generators 72 and 78 of FIG. 5. FIG. 7 is a schematic circuit diagram of one embodiment of the differential amplifiers 74, 80 of FIG. 5. Detailed Description of the Preferred Embodiments Referring now to FIG. 3, there is shown therein a functional block diagram of one embodiment of the present invention. The present invention is not, however, limited to this particular configuration. In FIG. 3, logic circuit 1 provides one or more logic signal outputs in response to one or more logic signal inputs, in an arrangement similar to that shown in FIG. 1. Powering this logic circuit are primarily power supply voltages V CC , V EE , V T and V Ref . Normally, V Ref is ground. The difference between V CC and V EE may, for example, be on the order of 3 volts, and the difference between V CC and V T may, for example, be on the order of 2 volts. A feature of the present invention is the use of a power supply control circuit 42. Control circuit 42 may be powered by the same V CC and V T voltages that are used to power logic circuit 1, thus not requiring a large or separate power supply. Control circuit 42 provides a fifth voltage input V CR to logic circuit 1. In one specific embodiment, as best seen in FIG. 4, this fifth voltage input V CR is supplied from a node 60 to resistors 26 and 28 of the logic circuit 1. As can be seen by comparing FIG. 4 to FIG. 2, this arrangement is a departure from prior art arrangements in which resistors 26 and 28 receive only the standard primary power supply voltage, V CC , the same voltage applied to the collectors of output transistors 10 and 20. Voltage input V CR at node 60 is a stabilized substitute for the fluctuating V CC , V CR being held constant by the power supply control circuit 42. In the embodiment of FIG. 3, this control circuit has three inputs -- a primary power supply voltage V CC , a secondary power supply voltage V T , and a second control signal V CCC , another feature of the invention. The voltage V CR is thus a function of the inputs V CC , V T and V CCC . Second control signal V CCC , which may be a variable voltage, is generated by yet another feature of the invention, a control signal generator 40 (see FIG. 3). Signal generator 40 also generates a first control signal V CS , which may also be a variable voltage, for input to the logic circuit 1. Inputs to signal generator 40 are the standard power supply voltages V CC , V T , V EE and V Ref . Signals V CCC and V CS are also fed back into signal generator 40 to form closed feedback loops. Control signals V CCC and V CS fluctuate in response to fluctuations in V CC , V EE , V T , V Ref , temperature and parameters of the components making up logic circuit 1. The primary purpose of V CCC is to control the UP output logic level of logic circuit 1 with respect to V Ref , and the primary purpose of V CS is to control the DOWN output level with respect to V Ref . Therefore, the difference between the signal levels is also controlled. Each control signal influences both levels by virtue of the feedback arrangement of signal generator 40. Control signals V CCC and V CS , together with control circuit 42 and its output V CR , thus accomplish the voltage, temperature and device parameter stabilizing functions of the present invention so as to maintain the output logic levels of logic circuit 1 extremely close to their ideal, preselected reference levels. Normally, these "ideal" levels are selected to be as small as possible to allow faster operation. One embodiment of a particular circuit arrangement of the control circuit 42 is shown in FIG. 4. In FIG. 4, the dotted portion of the circuit represents a typical prior art CSEF circuit, such as that shown in FIG. 2, except that the voltage V CR at node 60 now replaces the V CC connection. In the present invention, as mentioned above, the terminal for power supply voltage V CC is not connected to resistors 26 and 28, as in the prior art. Instead, a load resistor 50 and a first control transistor 52 are provided in a parallel configuration between the V CC terminal and node 60 which, in turn, is connected to resistors 26 and 28. In a preferred embodiment, transistor 52 is a bipolar transistor, preferably of a type opposite to the type employed in the logic circuit (i.e., transistors 10, 12, 14, 16, 18, 20 and 22). Here, transistor 52 is of the PNP type, while transistors 10, 12, 14, 16, 18, 20 and 22 are of the NPN type. In addition, transistor 52 is emitter coupled to the V CC terminal, is collector coupled to node 60 and is configured to operate as a dynamic resistance in response to a signal at its base. A second control transistor 54 has its collector coupled to the base of transistor 52. The emitter of transistor 54 is connected to a resistor 56 and then to one of the secondary power supply voltage terminals, V T . The base of transistor 54 receives the first variable control signal V CCC from control signal generator 40. Transistor 54 acts as a current amplifier and provides additional amplification for the V CCC signal, but is not essential for the operation of the circuit if the beta (gain) of transistor 52 is high (i.e., above 60). In practice, such a high beta is difficult to achieve for an integrated PNP transistor, but if available, then control signal V CCC may, for example, be inverted and input directly to a resistor in series with the base of transistor 52. Resistor 50, which is the highest value of resistance required of transistor 52 over the power supply voltage V CC range, acts to reduce the current required to be supplied by transistor 52. This increases the effective beta of transistor 52, reducing the required base current even further. The effect is to reduce the overhead power required of the control circuit 42. In another embodiment of the invention, transistors 52 and 54, and resistor 56, are replaced by a field effect transistor (either PFET or NFET), the source-drain current path of which is connected between the V CC terminal and node V CR , and the gate of which receives V CCC . Of course, in such case, the appropriate phase and signal amplitude for V CCC would need to be adjusted appropriately. The first variable control signal, V CS , from control signal generator 40, is input to the base of transistor 22 in logic circuit 1 of the preferred embodiment as shown in FIG. 4. Control signal V CS varies the current in the collector-emitter path of transistor 22 and hence through transistors 12, 14, 16 and 18, and indirectly through transistors 10 and 20. As long as V CS is controlling transistor 22, and as long as the voltage at node 60 is maintained at a constant level by way of V CCC , the voltages and currents at the outputs of the CSEF circuit will be maintained at a substantially constant, known level, thus permitting the signal swing at the outputs to be reduced to a minimum, because noise has been reduced to a minimum. FIG. 5 shows the control signal generator 40 of FIG. 3 of the present invention, which generator is used to generate the control signals V CCC and V CS . In FIG. 5, an UP-level sample generator 70 and an UP-level reference generator 72 are provided, each having an output that is fed into a first differential amplifier 74. A DOWN-level sample generator 76 and a DOWN-level reference generator 78 are also provided, each having an output that is fed into a second differential amplifier 80. UP-level sample generator 70 is intended to generate a logical UP output signal representative of the actual level of an UP output signal generated by a typical CSEF circuit in operation in a typical environment (for example, on a semiconductor chip in a central processing unit). Sample generator 70 may, for instance, be the logic circuit 1, together with control circuit 42, of FIG. 4, with one or more of its input transistors constantly "off", i.e., tied to the DOWN position. These inputs could be taken from the DOWN-level reference generator 78. The UP-level output of the sample generator 70 may, in one embodiment, be on the order of +350 to -50 millivolts when the feedback loop is open. When closed, the output voltage will be the same as the reference generator output. The UP-level reference generator 72 of FIG. 5 is used to provide a standard reference UP level logical signal (i.e., a constant UP level representative of the "ideal" UP logical output level desired for the particular configuration and environment intended for the CSEF circuit). A typical voltage at the output of reference generator 72 might, for example, be on the order of + 150 millivolts. A specific embodiment of reference generator 72 could, for example, be a circuit as described in an article by J. R. Cavaliere and G. E. Smith, III, the inventors of the present invention, entitled "Reference Generator Insensitive to Power Supply Variations," IBM Technical Disclosure Bulletin, Vol. 30, No. 10, March 1988, p. 27 and illustrated herein by FIG. 6. Differential amplifier 74, which receives as its inputs the outputs of sample generator 70 and reference generator 72, has as its output the second control signal V CCC . Differential amplifier 74 could be a differential bipolar amplifier such as the one described in the above-mentioned article by Cavaliere and Smith and shown in FIG. 7 herein. The gain required for amplifier 74 is determined by the amount of change one chooses to allow in a DC output logic level of the CSEF logic circuit 1. In the present embodiment, it has been found that a gain of 100 is satisfactory. The V CCC output of amplifier 74 is input to the power supply control circuit 42 (FIG. 3), specifically to the base of transistor 54 (FIG. 4). This V CCC signal controls the absolute value of the UP level of the CSEF logic circuit, and is also fed back into both sample generators 70 and 76 to form a closed loop for tighter control of both control signals V CCC and V CS , and consequently more effective, independent control of both the UP and DOWN output levels of the logic circuit. A similar arrangement exists in this embodiment with respect to DOWN-level sample generator 76, DOWN-level reference generator 78 and differential amplifier 80. Sample generator 76 may, for instance, be the standard CSEF logic circuit 1 (with control circuit 42) of FIG. 4, with one or more of its input transistors constantly "on", i.e., tied to the UP level. These inputs could be taken from the UP level reference generator 72. In this way, sample generator 76 generates a DOWN level output signal representative of the actual DOWN level output signal generated by a typical CSEF logic circuit in the particular operating environment. This DOWN-level output may be on the order of -200 to -300 millivolts in the present embodiment. DOWN-level reference generator 78, which may, for example, be a circuit such as that described in the above-mentioned Cavaliere and Smith article and shown in FIG. 6 herein, produces a standard reference logical DOWN signal representative of the "ideal" DOWN level desired for the particular configuration and environment of the CSEF logic circuit. In a typical environment, the DOWN level signal could be on the order of -230 millivolts. The outputs of sample generator 76 and reference generator 78 are applied to the input of differential amplifier 80, which could be a differential bipolar amplifier, as in FIG. 7, with a gain, for example, of 100. Amplifier 80 has an output which is the second control signal (V CS ) for input to the CSEF logic circuit 1 (FIG. 3), specifically to the base of transistor 22 (FIG. 4). This V CS signal controls the difference between the UP level and the DOWN level of the CSEF circuit, and is also fed back into both sample generators 70 and 76 to form a closed loop for tighter control of both the V CS and the V CCC signals, and consequently more effective, independent control of both the UP and DOWN output levels of the logic circuit. The feedback arrangement of the control signal generator 40 (FIG. 5) thus provides a means to vary the control voltages V CCC and V CS in such a manner as to compensate for fluctuations in the main power supply voltages V CC , V EE and V T . This control arrangement also helps compensate for fluctuations in temperature and in parameters of various devices in the CSEF circuits through the use of the sample generators. The nominal output signal swing may thus be reduced without reducing the worst case signal swing. The UP-level and DOWN-level reference generators provide UP and DOWN-level standards that are independent of V CC , V EE , V T , temperature and device parameters, but that are directly proportional to V Ref . FIG. 6 is an example of a specific embodiment, described in the above-mentioned Cavaliere and Smith article, which may be employed for the reference generators 72 and 78 of FIG. 5. FIG. 7 shows a circuit, also described in the above-mentioned article, which could be used as the differential amplifiers 74 and 80 of FIG. 5. In FIG. 6, power supply voltages V CC and V EE are input to terminals 88 and 91, respectively. Coupled to and extending between these two terminals are several circuit paths which, in one embodiment, include the following elements in series connection, as follows: First path: a resistor 84, the collector-emitter path of a transistor 82 and a resistor 83. Second path: resistor 84, a resistor 85, the collector-emitter path of a transistor 86 and a resistor 87. Third path: the collector-emitter path of a transistor 89 and a resistor 90. Fourth path: a resistor 92, the collector-emitter path of a transistor 93 and a resistor 94. Fifth path: the collector-emitter path of a transistor 95 and a resistor 96. The base of transistor 82 receives power supply voltage V Ref , which is ground in this embodiment. The bases of transistors 86 and 93 are both coupled to the emitter of transistor 89. The bases of transistors 89 and 95 are coupled to the collectors of transistors 86 and 93, respectively. For optimal operation, the V BE of transistor 82 should be equal to the V BE of transistor 89, and the V BE of transistor 93 should be equal to the V BE of transistor 95. In addition, the resistance of resistor 83 should be equal to the resistance of resistor 84, and the ratio of resistor 92 to resistor 94 should equal the ratio of resistors 84, plus 85, plus 87, to resistor 87. Output terminal 97 of FIG. 6, which is taken from the emitter of transistor 95, supplies the output UP-level reference signal for input to amplifier 74 of FIG. 5, or the DOWN-level reference signal for input to amplifier 80 of FIG. 5. These logic level reference signals are independent of V CC , V EE , V T , temperature and device parameters but track V Ref . FIG. 7 shows a differential amplifier which could serve either as differential amplifier 74 or differential amplifier 80 of FIG. 5. Although the general appearance of FIG. 7 is similar to that of FIG. 6, the circuits perform quite different functions. Power supply voltages V CC and V EE are input to terminals 106 and 108, respectively. Coupled to and extending between these two terminals are several circuit paths which, in one embodiment, include the following elements in series connection, as follows: First path: a resistor 110, the collector-emitter path of a transistor 111 and a resistor 112. Second path: resistor 110, a resistor 113, the collector-emitter path of a transistor 114 and a resistor 115. Third path: the collector-emitter path of a transistor 116 and a resistor 117. Fourth path: a resistor 98, the collector-emitter path of a transistor 99, the collector-emitter path of a transistor 118 and a resistor 119. Fifth path: a resistor 100, the collector-emitter path of a transistor 101, the collector-emitter path of transistor 118 aid resistor 119; Sixth path: the collector-emitter path of a transistor 102 and resistor 103. The base of transistor 111 receives power supply voltage V Ref , which is ground in this embodiment. The bases of transistors 114 and 118 are both coupled to the emitter of transistor 116. The bases of transistors 116 and 102 are coupled to the collectors of transistors 114 and 101, respectively. Transistor 118 operates as a constant current source. For optional operation, resistors 98 and 100 should be equal, and resistors 110, 112 and 113 should be equal. In addition, the ratio of resistor 98 (or 100) to 119 should equal the ratio of resistor 110, plus resistor 113, plus twice resistor 115, to resistor 115. When the circuit of FIG. 7 serves as differential amplifier 74 of FIG. 5, then input "A" from UP-level sample generator 70 is applied to the base of transistor 101, and input "B", from UP-level reference generator 72, is applied to the base of the transistor 99. The output, namely control signal V CCC , is taken from the emitter of transistor 102. An analogous arrangement exists when the circuit of FIG. 7 is used for differential amplifier 80 of FIG. 5. In that case, input "C" from DOWN-level sample generator 76 is applied to the base of transistor 99, and input "D" from DOWN-level reference generator 78 is applied to the base of transistor 101. The output for this arrangement is control signal V CS , taken from the emitter of transistor 102. The elements on the left-hand side of the circuit of FIG. 7 (namely, transistors 111, 113, 114, 116 and 118, and resistors 110, 112, 113, 115, 117 and 119 help keep the output free of extraneous fluctuations, by virtue of a stable constant current source configuration. The voltage at the output of the circuit of FIG. 7 is proportional only to the difference between the voltage at the two inputs, the circuit being independent of V CC , V EE , V T , temperature and device parameters. The operation of one embodiment of the present invention will now be described. Consider first the V CC power supply voltage. If a transient drop occurs in this voltage, this drop will cause the outputs of sample generator 70 and sample generator 76 (FIG. 5) to fluctuate downward momentarily, a fluctuation which is amplified by the differential amplifiers 74 and 80. The outputs of the reference generators 72, 78 are not affected because their outputs are independent of V CC and V EE . Accordingly, the control signal V CCC at the output of amplifier 74 is increased by an amount which is a function of the V CC and V EE fluctuation, and control signal V CS at the output of amplifier 80 is decreased by an amount which is also a function of the V CC and V EE of fluctuation. The V CCC signal, fed into the base of transistor 54 (FIG. 4), will, in turn, cause a corresponding almost instantaneous upward fluctuation in the current gated through transistor 54, and thus through the base of transistor 52. This fluctuation, in turn, will cause an almost instantaneous downward fluctuation in the resistance in the emitter-collector current path of transistor 52. In this example of this embodiment, the dynamic resistance of transistor 52 will typically vary from near zero ohms to near infinity as the power supply voltage V CC varies from 200 millivolts above to 200 millivolts below a nominal "centered" V CC value of +1.4 volts. This variation is sufficient to maintain the UP level at the outputs OUT₁ and OUT₂ extremely close to its ideal reference level. When V CC is at its nominal value (i.e., when the circuit is centered), then the emitter-collector resistance of transistor 52 will be approximately equal to the resistance of resistor 50. If voltage V CC rises, transistor 52 will begin to turn more off (i.e. draw less current), thus increasing the emitter-collector resistance accordingly, which increases the voltage drop across V CC to V CR . Transistors 52 and 54 have a response time which is fast enough to reflect, almost instantaneously, variations in control signal V CCC which, in turn, varies almost instantaneously with variations in power supply voltages V CC and V EE . Resistor 56 operates together with transistor 54 to provide current amplification and control to the base of transistor 52, to help contribute to the gain of the feedback loop. As a result, the logic circuit output levels are also substantially independent of variations in the voltage V T . In addition, V CS varies almost instantaneously with variations in V EE . For example, if V EE becomes more positive, V CS will be increased. An additional feature of the present invention is the low overhead power consumption required by the regulation circuits (control signal generator 40 and control circuit 42). Transistor 52 (FIG. 4) is of the PNP type in the present embodiment because use of a PNP type greatly reduces the power consumed by the control circuit 42. The additional power required per CSEF logic circuit is given by: (V CC - V T ) (i sw/2 ) (β PNP ) (α NPN ) where i sw the current switch current flowing through transistor 52, β is the base current to collector current gain for transistor 52, and α is the ratio of the collector current to the emitter current for transistor 54. The i sw term is divided by 2 because resistor 50 typically provides half of the current of the current switch. Because of this arrangement, the control signal generator 40 adds only a small power overhead when distributed over many logic circuits. The same power supply used for the logic circuits could also be used for the sample generators, reference generators and differential amplifiers. It has been found through simulation that, by using the present invention, the nominal UP and DOWN levels of +150 mv and -220 mv, respectively, at the outputs of the CSEF logic circuit 1 (FIG. 4) can be made to vary by less than 1% as the V CC , V EE or V T voltages vary by up to 20%. Similarly, these output levels vary by less than 1% as the ambient temperature varies from 45°C. to 85 °C., and as logic circuit device parameters (e.g., the resistance of resistors 26, 28 and 32, or the V BE of transistors 10, 12, 14, 16, 18, 20 and 22) vary over a range of ±20%, provided the corresponding elements of sample generators 70 and 76 (FIG. 5) vary accordingly. In other words, the present invention compensates for all typical semiconductor manufacturing variations in device parameters. This degree of control permits the output levels to be reduced to such an extent that at least a 20% speed improvement over standard CSEF logic circuits may be achieved. Signal generator 40 (FIG. 5) is typically located on the same chip as the CSEF circuits, to more accurately track changes in circuit device parameters. This permits the two control signals, V CCC and V CS , to be distributed to numerous CSEF logic circuits, resulting in lower overhead power per circuit. It is estimated that the number of such logic circuits able to receive these signals from the same generator is in excess of 400. The control afforded by the present invention permits lower power supply operation, resulting in less power dissipation at the same current for the logic circuit. This, together with the improved performance, results in an improved speed power product over CSEF logic circuits using the same type of devices. An additional benefit of the present invention is that control circuit 42 (FIG. 4) can filter out some high frequency switching noise (also known as driver induced or Δi noise) from the power supply, provided circuit 42, sample generator 70 and differential amplifier 74 are designed to be sufficiently fast. Additional filtering may be obtained if a capacitor is placed at node 60 of circuit 42. In the manner described above, the present invention permits the output signal swing of a typical current switch logic circuit to be reduced to a minimum, because the up and down levels are made substantially insensitive to power supply voltage fluctuations, junction temperature fluctuations and absolute device parameter fluctuations. Thus, maximum speed and minimum power dissipation are achieved simultaneously. The present invention thus solves an important problem faced by high performance logic circuit designers, namely how to compensate effectively for the environmentally-caused fluctuations described above. This permits more or equal noise margin for a smaller signal. While the present invention has been particularly shown and described with reference to preferred embodiments therefor, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein.

Claims: A logic circuit network for producing an adjustable first logic level and a different adjustable second logic level in response to at least one input signal, comprising: a logic circuit (1) comprising at least one input transistor (12, 14, 16) provided in a parallel configuration for receipt of one or more logical signal inputs (IN1, IN2, ...) at their base, the collector of each of said input transistors (12, 14, 16) being coupled through a resistor 26 to a first power supply terminal (VCR) for receiving power, said at least one input transistor (12, 14, 16) being connected in a differential amplifier configuration with a transistor 18 having a collector coupled through a resistor (28) to said first power supply terminal (VCR), said transistor 18 having a base connected to a first logic level reference voltage (Vref), the emitters of said at least one input transistor (12, 14, 16) and said transistor 18 being commonly connected to the collector of a transistor 22, said transistor 22 being connected in a constant current source configuration having an emitter that is connected through a resistor 32 to a second power supply terminal (VEE) and having a base that is connected to a first control terminal; said logic circuit further comprising a first and second output transistor (10, 20) having a base respectively connected to the collector of said at least one input transistor (12, 14, 16) and the collector of said transistor 18, said first and second output transistors (10, 20) being connected in an emitter-follower configuration and providing first and second output voltages (OUT1, OUT2), characterized in that it includes: means (40) for independently generating a first and a second control signal (VCS, VCCC) responsive to changes in the power supply voltage VCC, temperature and logic circuit component parameters, said first control signal (VCS) being applied to said first control terminal and said second control signal (VCCC) being applied to a second control terminal; a power supply control circuit (42) comprising a load resistor 50 and a first control transistor (52) being of the type opposite of said at least one input transistor (12, 14, 16), and being connected in parallel between the source of said power supply voltage VCC and said first power supply terminal (VCR), said first control transistor (52) being controlled by said second control signal (VCCC) existing on said second control terminal in order to operate as a controllable dynamic resistance; whereby the control of the signals (VCS,VCCC) applied to said first and second control terminals allows the compensation of changes that might have occured in the power supply and the temperature of the circuit components. Logic circuit network according to claim 1 characterized in that said power supply control circuit (42) further comprises a second control transistor (54) having its collector connected to the base of said first control transistor (52), its base connected to said second control terminal and its emitter connected to a third power supply terminal (VT). A logic circuit network for producing an adjustable first logic level and a different adjustable second logic level in response to at least one input signal, comprising: a logic circuit (1) comprising at least one input transistor (12, 14, 16) provided in a parallel configuration for receipt of one or more logical signal inputs (IN1, IN2, ...) at their base, the collector of each of said input transistors (12, 14, 16) being coupled through a resistor 26 to a power supply terminal (VCR) for receiving power, said at least one input transistor (12, 14, 16) being connected in a differential amplifier configuration with a transistor 18 having a collector coupled through a resistor (28) to said first power supply terminal (VCR), said transistor 18 having a base connected to a first logic level reference voltage (Vref), the emitters of said at least one input transistor (12, 14, 16) and said transistor 18 being commonly connected to the collector of a transistor 22, said transistor 22 being connected in a constant current source configuration having an emitter that is connected through a resistor 32 to a second power supply terminal (VEE) and having a base that is connected to a first control terminal; said logic circuit further comprising a first and second output transistor (10, 20) having a base respectively connected to the collector of said at least one input transistor (12, 14, 16) and the collector of said transistor 18, said first and second output transistors (10, 20) being connected in an emitter-follower configuration and providing first and second output voltages (OUT1, OUT2), characterized in that it includes: means (40) for independently generating a first and a second control signal (VCS, VCCC) responsive to changes in the power supply voltage VCC, temperature and logic circuit component parameters, said first control signal (VCS) being applied to said first control terminal and said second control signal (VCCC) being applied to a second control terminal; a power supply control circuit (42) comprising a field effect transistor connected as a controllable dynamic resistance and having the source-drain current path connected between the source of said power supply voltage VCC and said first power supply terminal (VCR), and having a gate connected to receive said second control signal (VCCC) existing on said second control terminal; whereby the control of the signals (VCS, VCCC) applied to said first and second control terminals allows the compensation of changes that might have occured in the power supply and the temperature of the circuit components. Logic circuit network according to claim 1, 2 or 3 characterized in that said means (40) for generating said first and second control signals (VCS, VCCC) further comprises: a first and a second sample generator (70, 76), each comprising a current switch emitter-follower with its inputs being fixed at a predetermined logic reference level; a first and a second reference generator (72, 78); a first and a second differential amplifier (74, 80), each amplifier having its output being applied to each of said sample generator (70, 76) and the output of each of said sample generator (70, 76) being applied to one input of a different respective differential amplifier (74, 80); said first differential amplifier (74) providing the first control signal (VCS) which is transmitted to said first control terminal; and said second differential amplifier (80) providing the second control signal (VCCC) which is transmitted to said second control terminal. A logic circuit network according to claim 4 characterized in that each reference generator (72, 78) comprises: first and second terminals (88, 91) for receiving first and second power supply voltages, respectively, and an output terminal (97); first (82), second (86), third (89), fourth (93) and fifth (95) transistors; and first (84), second (83), third (85), fourth (87), fifth (90), sixth (92), seventh (94) and eighth (96) resistors; the resistors and the collector-emitter paths of the transistors being connected to each other and to and between the first and second terminals (88, 91), respectively, in series connections, as follows: first resistor (84), first transistor (82) and second resistor (83); first resistor (84), third resistor (85), second transistor (86) and fourth resistor (87); third transistor (89) and fifth resistor (90); sixth resistor (92), fourth transistor (93) and seventh resistor (94); and fifth transistor (95) and eighth resistor (96); the bases of the transistors being connected as follows: the base of the first transistor (82) connected to a third power supply voltage; the bases of the second (86) and fourth (93) transistors connected to the emitter of the third transistor (89); and the base of the fifth transistor (95) connected to the collector of the fourth transistor (93); the output terminal being connected to the emitter of the fifth transistor (95). A logic circuit network according to claim 4 characterized in that each of said differential amplifier (74, 80) comprises: first (106) and second (108) terminals for receiving first and second power supply voltages, respectively, two input terminals and an output terminal (104); first (111), second (114), third (116), fourth (101), fifth (118), sixth (99) and seventh (102) transistors; and first (110), second (112), third (113), fourth (115), fifth (117), sixth (100), seventh (119), eighth (98) and ninth (103) resistors; the resistors and the collector-emitter paths of the transistors being connected to each other and to and between the first and second terminals (106, 108), respectively, in series connections, as follows: first resistor (110), first transistor (111) and second resistor (112); first resistor (110), third resistor (113), second transistor (114) and fourth resistor (115); third transistor (116) and fifth resistor (117); sixth resistor (100), fourth transistor (101), fifth transistor (118) and seventh resistor (119); and eight resistor (98), sixth transistor (99), fifth transistor (118) and and seventh resistor (119); and seventh transistor (102) and ninth resistor (103); the bases of the transistors being connected as follows: the base of the first transistor (111) connected to a third power supply voltage; the bases of the second (114) and fifth (118) transistors connected to the emitter of the third transistor (116); the bases of the fourth (101) and sixth (99) transistors connected to the input terminals, and the base of the seventh transistor (102) connected to the collector of the fourth transistor (101); the output terminal being connected to the emitter of the seventh transistor (102).

Inventors: CAVALIERE JOSEPH RICHARD, SMITH GEORGE EARL III, CAVALIERE, JOSEPH RICHARD, SMITH, GEORGE EARL, III
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: H03K19
IPC codes: H03K19