Method of manufacturing metal-semiconductor field effect transistors

Abstract: A semiconductor device which comprises a semi-­ insulating substrate (1) and a plurality of field effect transistors (FETs) formed on the semi-insulating sub­ strate (1). An epitaxial layer (2)of one conductivity type is formed on the semi-insulating substrate by a crystal growth technique which is capable of controlling a film thickness at an atomic level. At least some of channel active layers of the FETs have different threshold voltages one another due to a difference in thickness of the epitaxial layer (2) and/or due to an additional ion implantation region selectively formed in the epitaxial layer (2). A manufacturing method of the semiconductor device is also disclosed, wherein a portion of the epitaxial layer (2) corresponding to the channel active layer of a FET is thickened by the repetition of an epitaxial growth, thinned by the etching of the epitaxial layer or ion implanted thereby obtaining a different threshold voltage from that of another FET.

Description: The present invention relates to a method of manufacturing MESFETs (Metal Semiconductor Field Effect Transistor) having different threshold voltages. A GaAs MESFET as a typical MESFET has already been proposed by the present inventor in Japanese Patent Application No. 61-104693 wherein an epitaxial active layer is obtained by controlling and depositing a channel active layer region of the GaAs MESFET at an atomic layer level. A MESFET using the above epitaxial active layer can be manufactured as a MESFET having a uniform threshold voltage. However, an application of such a MESFET to an integrated circuit in which MESFETs having different threshold voltages are formed on a single substrate is not considered at all in Japanese Patent Application No. 61-104693. Prior art document Patent Abstracts of Japan, vol. 10, No. 376 (E-464) (2433), 13 December 1986 & JP-A-61 168 965, discloses a semiconductor device including an improved enhancement-type FET and a depression-type FET on the same substrate by inserting separation layers having a different thickness from each other between the gate electrodes and a channel layer. In this known semiconductor device, an etching step is applied to make the separation layers different from each other in thickness. Further, prior art document Patent Abstracts of Japan, vol. 10, No. 279 (E-439) (2335) 20 September 1986 & JP-A-61 099 379, describes a FET device wherein a p⁺ semiconductor layer is deposited on a portion of a semiconductor layer having a broad width of the forbidden band for blocking leakage of holes from a p-channel layer. It is an object of the present invention to provide a method of manufacturing MESFETs which have different threshold voltages and can be formed on a single substrate. To solve this object the present invention provides a method as specified in the claim. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1(A) to 1(F) are sectional views showing steps in manufacturing MESFETs according to an embodiment of the present invention; Fig. 2 and Figs. 3(A) to 3(F) are sectional views showing steps in manufacturing MESFETs; Fig. 4 is a circuit diagram of a basic logic circuit; and Figs. 5(A) to 5(E) are sectional views showing steps in manufacturing MESFETs. A GaAs MESFET according to an embodiment of the present invention will be described hereinafter with reference to the accompanying drawings. Since a channel active layer of a GaAs MESFET has a small thickness of 100 nm or less, a change in thickness of the layer directly influences a threshold voltage vth. Since a dynamic range (a voltage difference between high and low levels, i.e., a logic amplitude) in a digital circuit of the GaAs MESFET is small, a variation in threshold voltage Vth between elements is required to fall within an extremely small allowance of ± (50 to 100) mV. In order to sufficiently satisfy this requirement with high controllability, it is primarily very important that the distribution of impurity concentration in the channel active layer and its thickness must always be uniform. A recent crystal growth technique employing molecular beam epitaxy (to be referred to as MBE), metalorganic molecular beam epitaxy (to be referred to as MO-MBE), or metalorganic chemical vapor deposition (to be referred to as MO-CVD) is often called as a technique wherein atomic or molecular layers are stacked one by one. In a crystal growth technique for controlling a film thickness at an atomic level in the present invention, the above method is employed. This technique can control the film thickness in units of several atomic layers or less, and can confirm the thickness by growth rate measurement, or the like. First, an n-type GaAs epitaxial layer 2 having a thickness of 100 nm or less is formed on a semi-insulating GaAs substrate 1 having a resistivity of 10⁷ (Ω·cm) or more, using a crystal growth apparatus which employs MBE, MO-MBE, or MO-CVD, by a technique wherein atomic layers are stacked one by one. A donor concentration is determined in accordance with the thickness of the n-type GaAs epitaxial layer 2 and a target value of the threshold voltage Vth. However, the. donor concentration is generally set within the range of 10¹⁵ to 10¹⁸ atoms/cm² (Fig. 1(A)). Then, an epitaxial layer 5 having an atomic layer level is deposited on only a predetermined portion of the n-type GaAs epitaxial layer 2 using the above-mentioned crystal growth apparatus and the crystal growth technique. For example, as shown in Fig. 1(B), a selective epitaxial layer growth method may be employed to deposit an insulating film 3 of SiO₂, SiN, SiON, or the like, on the epitaxial layer 2, an opening 4 is formed on the predetermined portion, and selectively deposit the epitaxial layer 5 in the opening 4. Thereafter, the insulating film 3 is entirely removed. Since the thickness of the deposited epitaxial layer is increased, a channel active layer having a threshold voltage Vth shifted to a negative side is formed. In the case of a GaAs IC, the step of isolating MESFETs is required. Therefore, as shown in Fig. 1(C), the step of etching the GaAs substrate by about 0.2 to 0.5 µm deep may be provided and an isolation trench 6 is formed. If necessary, an insulating material 7 may be buried in the isolation trench 6. Then, a refractory metal or refractory metal compound 8 such as tungsten silicide (WSi) or tungsten nitride (WN) is deposited as a gate electrode by sputtering, CVD, or the like (Fig. 1(D)). An insulating film 9 such as a silicon nitride film or silicon oxide film is deposited by, e.g., plasma CVD or CVD, and a gate electrode is formed by RIE (Reactive Ion Etching) (Fig. 1(E)). Si ions are implanted in the substrate 1 to form self-aligned n⁺-type layers 10 for prospective source and drain regions by using the gate electrode 8 as a mask. Then, cap annealing using phosphosilicate glass (PSG) or the like, or capless annealing in an arsine atmosphere is performed to activate the n⁺-type layers 10 (Fig. 1(F)). Thereafter, an Au-Ge ohmic metal which achieves an ohmic contact with the n⁺-type layers 10 serving as the source and drain is deposited by a well known method to form source and drain electrodes. Then, a wiring operation is performed, and an integrated circuit device of the GaAs MESFETs is thus manufactured. Fig. 2 shows a method of manufacturing MESFETs not covered by the present invention. In Fig. 2, as a method of manufacturing MESFETs having different threshold voltages Vth, an insulating film 11 of SiO₂, SiN, SiON, or the like is deposited on an n-type epitaxial layer 2. An opening 12 is formed in a predetermined portion to form an etched portion 13 in the epitaxial layer 2, thus controlling the threshold voltage Vth. A channel active layer having a threshold voltage Vth shifted to a positive side is formed. The following steps are the same as those in the above embodiment, and an integrated circuit device of GaAs MESFETs is thus manufactured. An excellent controllability of threshold voltage which cannot be obtained in channel layer formation by conventional ion implantation can be achieved. A MESFET having an epitaxial active layer has excellent controllability of impurities or crystal state in the channel active layer. Therefore, high controllability of the threshold voltage as a characteristic of the MESFET can be achieved. At the same time, the uniformity of the threshold voltage in a substrate is sufficiently assured. This is a necessary condition to realize a larger integrated circuit with a high production yield and excellent reproducibility. The following GaAs integrated circuit devices can be easily realized. For example, in order to provide a high-output MESFET for an output buffer, with a large transconductance, a MESFET having a varied threshold voltage can be used. Or, in order to realize a high integration and low power consumption, a GaAs integrated circuit device mounted thereon with a basic logic comprising E (enhancement) type and D (depletion) type MESFETs for example DCFL (Direct Coupled FET Logic) can be easily manufactured. A still a method of manufacturing MESFETs not covered by the present invention will be described below with reference to Figs. 3(A) to 3(F). In this method, a technique for forming a channel active layer by a crystal growth method such as MBE, MO-MBE, or MO-CVD for controlling crystal growth at an atomic layer level in the same manner as in the above methods is employed as a basic technique. In addition, ions are implanted in the channel active layer to form another channel active layer having a uniform impurity concentration and a uniform film thickness. Figs. 3(A) to 3(F) are sectional views of elements showing steps in manufacturing GaAs MESFETs. First, an n-type GaAs epitaxial layer 22 having a thickness of 100 nm (1,000 Å) or less is formed on a semi-insulating GaAs substrate 21 having a resistivity of 10⁷ (Ω·cm) or more using a crystal growth apparatus employing MBE, MO-MBE, or MO-CVD by a technique for depositing atomic layers one by one. The donor concentration is determined in accordance with the thickness of the n-type GaAs epitaxial layer 22 and the target value of threshold voltage Vth, and is generally set within the range of 10¹⁵ to 10¹⁸ atom/cm² (Fig. 3(A)). Subsequently, ions are implanted in only the n-type GaAs epitaxial layer 22, or in both the n-type GaAs epitaxial layer 22 and the GaAs substrate 21 to form an ion-implanted layer 23 (Fig. 3(B)). At this time, when Si ions are implanted, the impurity concentration is increased, and the threshold voltage Vth is set at a deeper level (shifted to the negative side). On the other hand, Zn or B ions are implanted, n-type impurity compensation is performed, and the concentration is decreased. Therefore, the threshold voltage Vth is set at a shallow level. For example, when a DCFL which is a basic logic of GaAs is formed, a shallow, lightly-doped E MESFET which is difficult to manufacture is controlled by the n-type GaAs epitaxial layer at an atomic layer level. Then, Si ions are implanted in a D MESFET, the concentration of the channel active layer is partially increased, and the threshold voltage Vth may be set at a shallow level (Fig. 3(B)). If necessary, capless annealing is performed in an arsine atmosphere to activate the ion-implanted layer. When a GaAs IC is manufactured, the step of isolating MESFETs is required. Therefore, the step of etching a GaAs substrate by about 0.2 to 0.5 µm deep is provided, and an isolation trench 24 may be formed, as shown in Fig. 3(C). If necessary, an insulating material 25 may be buried in the isolation trench 24. Then, a refractory metal compound 26 such as tungsten silicide (WSi) or tungsten nitride (WN) is deposited as a gate electrode by sputtering, CVD, or the like (Fig. 3(D)). An insulating film 27 such as a silicon nitride film or silicon oxide film is deposited by, e.g., plasma CVD or CVD, and gate electrodes are formed by RIE (Fig. 3(E)). Si ions are implanted in the substrate 1 to form self-aligned n⁺-type layers 28 for prospective source and drain regions by using the gate electrodes 26 as masks. Then, cap annealing using PSG or the like, or capless annealing in an arsine atmosphere is performed to activate the n⁺-type layers 28 (Fig. 3(F)). Thereafter, an Au-Ge ohmic metal which achieves an ohmic contact with the n⁺-type layers 28 serving as the source and drain is deposited by a well known method to form source and drain electrodes. Then, a wiring processing is performed, and an integrated circuit device of the GaAs MESFETs is finally manufactured. These two types of GaAs MESFETs constitute a DCFL circuit shown in Fig. 4. Reference numeral 29 denotes a D MESFET; and 30, an E MESFET. Figs. 5(A) to 5(E) show a method of manufacturing MESFETs not covered by the present invention. An n-type GaAs epitaxial layer 32 is formed on a GaAs semi-insulating substrate 31, and an element isolation trench 33 is formed. These steps are the same as in those in the above methods. Then, a first metal film 34 having a thickness of 100 nm (1,000 Å) or less is continuously deposited on the entire surface of the epitaxial layer 32 using a crystal growth apparatus. A refractory metal compound such as tungsten silicide (WSi x ) or tungsten nitride (WN x ) is used as the metal film. A part of the first metal film 34 serves as a Schottky gate electrode in the subsequent process. Ions are implanted through the metal film 34 to form another channel active layer region 35 (Fig. 5(A)). In the MESFET, a signal response delay occurs in proportion to a product of the sheet resistance of a gate electrode and a gate electrode capacitance. For example, the resistivity of WSi x or WN x of a gate electrode material is 100 to 200 µΩ·cm. When higher-speed operation is required, the above-mentioned delay is not negligible. In particular, when the gate width is increased to obtain a large amount of current, a delay and the gate electrode capacitance are increased, and an operation speed is reduced. Then, a second metal film 36 having a thickness of 100 nm (1,000 Å) or more is formed on the first metal film 34, and an insulating film 37 is formed thereon. As the insulating film 37, e.g., a silicon nitride film formed by plasma CVD or a silicon oxide film formed by CVD may be used. A refractory metal such as W, Mo, or Ti is used as the second metal film 36. When the next gate electrode is formed by RIE, selectivity between the first and second metal films 34 and 36 is preferably large (Fig. 5(B)). First, the insulating film 37 on the gate electrode is left as it is and the insulating film on the portion except the gate electrode is etched by RIE. After a resist is removed, an RIE gas is changed, and the gate electrode is formed by the second metal film 36 using the insulating film 37 as a mask. As shown in Fig. 5(C), ions are implanted in heavily-doped prospective source and drain formation regions 38 using a multi-layered film consisting of the second metal film 36 and the insulating film 37 as a mask. Then, n⁺-type heavily-doped layers 38 for prospective source and drain are self-aligned with the gate electrode. That allows an increase in transconductance gm, and high-speed operation can be further effectively realized. After the insulating film 37 on the gate electrode 36 is removed, in order to activate the channel active layer or prospective source and drain n⁺-type layers 38 by ion implantation, e.g., a silicon dioxide film containing phosphorus for preventing As ion removal, a silicon dioxide film containing arsenic, a silicon dioxide film containing both phosphorus and arsenic, or silicon nitride film not containing phosphorus or arsenic is deposited on the metal film as a protective film 39, and annealing, i.e., so-called cap annealing is performed (Fig. 5(D)). In the above-mentioned activation annealing process in the manufacturing method, capless annealing process using a dangerous arsine gas is not employed, but cap annealing process using a metal film as a protective film is employed. Then, the protective film such as silicon dioxide film or silicon nitride film used as a cap is removed. In addition, gate electrodes are formed by the first metal film 34 using the second metal film 36 as a mask by RIE (Fig. 5(E)). The following steps are the same as those in the above methods, and GaAs MESFETs are formed. As described above, the threshold voltage Vth of the MESFET formed in the epitaxial active layer has high controllability, as a matter of course. When ions are implanted in the epitaxial active layer, the controllability of the threshold voltage Vth of MESFET becomes more excellent as compared with the conventional case wherein only ion implantation is performed. This high controllability of the threshold voltages Vth realizes the manufacture of various GaAs basic logic circuits. A high-output MESFET for an output buffer having a large gm (transconductance) and a negative threshold voltage (largely shifted in the negative direction) can be easily manufactured. On the other hand, a basic logic circuit such as a DCFL (Direct Coupled FET Logic) including both a D MESFET and an E MESFET to realize high integration and low power consumption can be easily realized, thus providing an excellent manufacturing technique of an LSI constituted by GaAs MESFETs. For example, in the present invention, two or more channel active layers having different concentrations may be formed on a single semiconductor substrate. As has been described above, according to the present invention, the controllability of a threshold voltage which cannot be obtained in the conventional channel layer formation by only ion implantation, can be achieved. A MESFET having an epitaxial active layer has excellent controllability of an impurity and crystal state in the channel active layer. Therefore, there is provided a semiconductor device in which uniformity in a substrate is sufficiently assured in addition to good controllability of the threshold voltage as the characteristic of a MESFET, and a method of manufacturing the same.

Claims: A method of manufacturing MESFETs having different threshold voltages comprising the steps of: forming a first epitaxial layer (2) of a first conductivity type on a semi-insulating substrate (1) by a crystal growth technique which is capable of controlling a film thickness at an atomic level, said first epitaxial layer forming at least one first channel active layer, selectively depositing a second epitaxial layer (5) of said first conductivity type on a portion of said first epitaxial layer (2) by a crystal growth technique which is capable of controlling a film thickness at an atomic level, said second epitaxial layer together with said portion forming at least one second channel active layer laterally spaced from and having a thickness greater than said first channel active layer, forming an element isolation trench (6) between said first channel active layer and second channel active layer; selectively forming a gate electrode (8) on each of said first channel active layer and said second channel active layer; and performing ion implantation using said each gate electrode (8) as a mask to form source/drain regions (10).

Inventors: IWASAKI HIROSHI C O PATENT DIV, IWASAKI, HIROSHI C/O PATENT DIVISION K.K. TOSHIBA
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21