Logic circuit arrangements

Abstract: A logic circuit comprises digital signal input and output terminals (1a,1c,1e;2a,2b) and a differential amplifier circuit comprising two amplifier circuits each using a feedback load. Each amplifier circuit includes a first amplifier (5a,5b), an amplifier element (6a,6b) connected to the output terminal of the first amplifier (5a,5b) as the feedback load, and a further amplifier element (12a,12b) connected between the output and input terminals of the amplifier element (6a,6b), and performs negative feedback through a load (RL1) of the first-stage amplifier (5a,5b). As the amplifier element (6a,6b), a transistor is used, and as the further amplifier element (12a,12b), an emitter-follower transistor is preferably used.

Description: The present invention relates to logic circuit arrangements. Fig. 1 is a circuit diagram showing a conventional wide-band feedback type differential amplifier circuit (H. Hillbrand, J. Gruber and P. Russer, "Computer Aided Design of a 1 GHz Band-width Monolithic Integrated Amplifier", ESSCI-RC, 1977, pp. 122 - 124). Referring to Fig. 1, reference numerals 1a and 1b denote input terminals for receiving input signals V in and V in ; 2a and 2b, output terminals for outputting output signals V out V out ; 3, a high-potential power supply terminal for receiving a potential V CC ; 4, a low-potential power supply terminal for receiving a potential V EE ; 5a and 5b, a pair of input differential transistors as a first pair of differential transistors; 6a and 6b, a pair of output differential transistors as a second pair of differential transistors; 7a and 7b, and 8a and 8b, load resistors having resistances R L1 and R L2 , respectively; 9a and 9b, load capacitors having a capacitance C L ; and 10 and 11, first and second current supply circuits for supplying currents I 1 and I 2 . The circuit shown in Fig. 1 is constituted by the pair of input differential transistors 5a and 5b connected to the load resistors 7a and 8a, and 7b and 8b as loads, respectively, and the pair of output differential transistors 6a and 6b connected to the load resistors 8a and 8b as loads. As the characteristic feature of this circuit, the collectors of the transistors 6a and 6b are connected to their bases through the load resistors 7a and 7b, respectively. Collector signals of the transistors 6a and 6b are fed back to their bases in opposite phases through the load resistors 7a and 7b, in other words, feedback loads are used for the transistors 5a and 5b, thereby realizing a wide-band operation. If transconductances of the transistors 5a and 5b, and 6a and 6b are represented by gml and gm2, base resistances are represented by rb1 and rb2, input capacitances are presented by Cπ1 and Cπ2, and an angular frequency is represented by ω, a voltage gain A V of this conventional circuit is given by: A V = gm1·gm2·R L1 ·R L2 (1+gm2·R L2 )(1+jωa)(1+jωb)(1+jωc) where a is the time constant at the bases of the transistors 5a and 5b, b is the time constant at the bases of the transistors 6a and 6b, and c is the time constant at the collectors of the transistors 6a and 6b, and these constants are respectively given by: a = Cπ1.rb1 b = {Cπ2·(R L1 + R L2 + rb2)/ (1 + gm2·R L2 )}·{(1 + jωC L ·R L2 ) /(1 + jωc)} c = C L ·R L2 /(1 + gm2·R L2 ) The gain of the circuit shown in Fig. 1 in a low-frequency mode is approximated by gm1·R L1 from equation (1). The gain in a high-frequency mode is decreased as a frequency increases in accordance with the time constants a , b , and c . However, as can be seen from equations (3) and (4), since the time constants of the bases and collectors of the transistors 6a and 6b can be reduced to 1/(1+gm2·R L2 ) by a feedback effect, a wide-band operation is allowed as compared to a conventional differential amplifier circuit. The time constant b given by equation (3) has an imaginary number component. The imaginary number component is increased as the capacitances C L of the load capacitors 9a and 9b are increased, and operates to cause peaking in frequency characteristics. For this reason, the capacitances C L of the load capacitors 9a and 9b are optimized, thus achieving a wider-band operation. Fig. 2(a) is a graph showing simulation results of frequency characteristics of the circuit shown in Fig. 1. In Fig. 2(a), a frequency is plotted along the abscissa, and a gain is plotted along the ordinate. A plurality of characteristics 21, 22, 23, and 24 are obtained by changing the capacitance C L of the load capacitor to 0.2 pF, 0.1 pF, 0.05 pF, and 0. As can be seen from the graph, peaking characteristics can be provided by increasing the capacitance C L , and the capacitance C L is optimized to realize wide-band characteristics. For this reason, wide-band characteristics can be obtained by utilizing an input capacitance or wiring capacitance of the output-side circuit. Note that a bipolar transistor having a high-frequency cutoff frequency of 60 GHz was assumed for simulation. However, the circuit shown in Fig. 1 suffers from the following drawbacks. Since bias currents from two transistors, i.e., 5a and 6a, and 5b and 6b are flowed into the load resistors 8a and 8b, respectively, tradeoff (the relationship that when one is established, the other cannot be established) between two differential circuit design occurs, and it is not easy to optimize circuit constants. Since the gain of the circuit shown in Fig. 1 is determined by gm1·R L1 , as described above, when this circuit is applied to a variable gain amplifier circuit, it can be realized by controlling gm1 by changing a current value I 1 of the current source circuit. Thus when DC direct coupling is to be realized, DC potentials at the output terminals 2a and 2b are undesirably changed upon control of the current value I 1 . Furthermore, the amplitude of the output signal of the circuit shown in Fig. 1 is determined by R L1 ·I 1 , and may be applied to a limiter amplifier circuit. When the current I 1 of the current source circuit 10 is changed to allow adjustment of the amplitude of the output signal, the DC potentials at the output terminals 2a and 2b are varied in the same manner as in the variable gain amplifier circuit. Since R L1 and R L2 are directly coupled to each other, when a signal large enough to cause a switching operation (logic operation) is input to the input terminals 1a and 1b, the base-collector capacitance is largely changed due to a change in base-collector voltage of the transistors 6a and 6b. Thus, an output waveform S 2 is distorted, as shown in Fig. 2(b). For this reason, the circuit shown in Fig. 1 cannot be applied to a high-speed logic circuit. Note that S 1 denotes an input waveform. Furthermore, in monolithic amplifier circuits which will suffer from a variation in manufacturing, peaking characteristics tend to vary, and optimal frequency characteristics are not easy to obtain. An object of the present invention is to provide an improved logic circuit arrangement, for example having a good logic waveform as shown in Figure 8. The present invention is characterised as set out in Claim 1. The combination of features set out in Claim 1 as sub-paragraphs (a) to (f) thereof is known per se in a different technical field as a differential amplifier circuit arrangement described in US-A-3399357. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a conventional amplifier circuit having a feedback load; Fig. 2(a) is a graph showing gain-frequency characteristics of the conventional circuit; Fig. 2(b) is a graph showing input and output waveforms of the conventional circuit; Fig. 3 is a circuit diagram showing a differential amplifier circuit having a feedback load; Fig. 4 is a graph showing gain-frequency characteristics of the circuit of Fig. 3; Fig. 5 is a circuit diagram of another variable gain amplifier circuit; Fig. 6 is an I 1 -output voltage graph of Fig. 5; Fig. 7 is a circuit diagram of a limiter amplifier circuit which can perform output amplitude control; Fig. 8 is a graph showing input and output waveforms of the circuit shown in Fig. 7; Fig. 9 is a circuit diagram of a wide-band amplifier circuit which can change peaking characteristics; Figs. 10 to 15 are circuit diagrams showing logic circuit arrangements according to six embodiments of the present invention; and Fig. 16 is a diagram of a logic decision circuit including a logic circuit arrangement, according to the present invention. Figs. 3 to 9 relate to circuits which per se are outside the scope of the present invention, but are helpful in understanding the invention. In those circuits, emitter-follower transistors are added to a feedback circuit portion, and have impedance and bias conditions of the feedback circuit portion different from those of the conventional circuit of Figs. 1 and 2. Referring to Fig. 3, reference numerals 1a and 1b denote input terminals for receiving input signals V in and V in ; 2a and 2b, output terminals for outputting output signals V out and V out ; 3, a high-potential power supply terminal for receiving a potential V CC ; 4, a low-potential power supply terminal for receiving a potential V EE ; 5a and 5b, a pair of input differential transistors as a first pair of differential transistors; 6a and 6b, pair of output differential transistors as a second pair of differential transistors; 7a and 7b, and 8a and 8b, load resistors having resistances R L1 and R L2 , respectively; 9a and 9b, load capacitors having a capacitance C L ; 10 and 11, first and second current supply circuits for supplying currents I 1 and I 2 ; and 12a and 12b, feedback emitter-follower transistors. The transistors 12a and 12b and the load resistors 7a and 7b constitute a feedback means. In this circuit, the emitter-follower transistors 12a and 12b are added to the conventional circuit shown in Fig. 1, so that a wider-band operation than in the conventional circuit is achieved by the buffer effect of the transistors 12a and 12b. In addition, the circuit shown in Fig. 3 is arranged in a DC manner so that currents flowed through the transistors 5a and 5b are not flowed through the load resistors 8a and 8b, thus facilitating DC design of the circuit. If transconductances of the transistors 5a and 5b, and 6a and 6b are represented by gm1 and gm2, base resistances are represented by rb1 and rb2, input capacitances are presented by Cπ1 and Cπ2, and an angular frequency is represented by ω, a voltage gain A V of the circuit shown in Fig. 3 is given by: A V = gm1·gm2·R L1 ·R L2 (1+gm2·R L2 )(1+jωa)(1+jωb)(1+jωc) where a is the time constant at the bases of the transistors 5a and 5b, b is the time constant at the bases of the transistors 6a and 6b, and c is the time constant at the collectors of the transistors 6a and 6b, and these constants are respectively given by: a = Cπ1·rb1 b = {Cπ2·(R L1 + rb2)/(1+ gm2·R L2 )} ·{(1 + jωC L ·R L2 )/(1 + jωc)} c = C L ·R L2 /(1 + gm2·R L2 ) The gain of the circuit shown in Fig. 3 in a low-frequency mode is approximated by gm1·R L1 from equation (5) in the same manner in the conventional circuit. The gain in a high-frequency mode is decreased as a frequency increases in accordance with the time constants a , b , and c . As can be seen from equations (7) and (8), since the time constants of the bases and collectors of the transistors 6a and 6b can be reduced to 1/(1+gm2·R L2 ) due to the feedback effect, a wider-band operation can be realized as compared to a conventional differential amplifier circuit. Upon comparison between equation (3) of the conventional circuit shown in Fig. 1 and equation (7), since R L2 is eliminated in equation (7) in the circuit of this embodiment, wider-band characteristics than in the conventional circuit shown in Fig. 1 can be realized in principle. This advantage can be obtained by utilizing the fact that impedances from the emitters of the transistors 12a and 12b are low. Fig. 4 is a graph showing simulation results of frequency characteristics of the circuit of Fig. 3. In Fig. 4, a frequency is plotted along the abscissa, and a gain is plotted along the ordinate. A plurality of characteristics 31, 32, 33, and 34 are obtained by changing the capacitance C L of the load capacitor to 0.2 pF, 0.1 pF, 0.05 pF, and 0. In this simulation, the resistance R L1 of the resistors 7a and 7b = 500 Ω, the resistance R L2 of the resistors 8a and 8b = 500 Ω, I 1 = 3 mA, I 2 = 3 mA, and transistors used had a high-frequency cutoff frequency f T = 60 GHz and a current gain β = 50. Upon comparison with the frequency characteristics of the conventional circuit shown in Fig. 1 (Fig. 2(a)), a band-width can be improved by about 25% in the circuit of Fig. 3. Like in the conventional circuit shown in Fig. 1, a band-width can be further increased by peaking due to the effect of the capacitance C L . For this reason, by utilizing an input capacitance or wiring capacitance of the output-side circuit, characteristics over a wider band can be obtained. Furthermore, the circuit of Fig. 3. has the following advantages in addition to the band characteristics as compared with the conventional circuit. (1) The current gain β of a bipolar transistor is normally 100 or more. For this reason, currents flowed in the bases of the transistors 12a and 12b are as small as 1/β the collector currents. The bias current of a differential pair consisting of the transistors 5a and 5b and the bias current of a differential pair consisting of the transistors 6a and 6b are separated by the transistors 12a and 12b. For this reason, bias design and gain design of the differential pairs can be independently made, thus allowing easier design than the conventional circuit. Note that in an ultra-high speed transistor, may often be decreased to be equal to or smaller than 100 due to tradeoff with an operating speed. In principle, however, if β of 1 or more is provided, an effect of improving the conventional circuit can be obtained. (2) Since the transistors 12a and 12b are operated as the emitter-follower transistors, when signals are extracted from the emitters of the transistors 12a and 12b, a low output impedance advantageous for voltage amplification can be obtained. Like in the conventional circuit, output signals can be extracted from the collectors of the transistors 6a and 6b. (3) Fig. 5 shows a variable gain amplifier circuit. The circuit shown in Fig. 5 employs a variable current source circuit 13 in place of the first current source circuit in the circuit shown in Fig. 3. A current I 1 flowed through a differential pair consisting of transistors 5a and 5b is controlled to change the transconductance gml of the transistors 5a and 5b, thereby realizing a variable gain function. In this circuit, even if the current I 1 is changed, bias voltages at output terminals 2a and 2b will not be changed (characteristic curve P) due to the emitter follower effect of transistors 12a and 12b unlike in a conventional circuit (characteristic curve Q) shown in the graph of Fig. 6. For this reason, the circuit shown in Fig. 5 can be applied to a multi-stage amplifier circuit realized by DC direct coupling. The circuit arrangement shown in Fig. 5 is suitable for a monolithic IC with which a large-capacitance capacitor is difficult to realize. Note that reference numerals 9a' and 9b' denote load capacitors C L '. (4) Fig. 7 is a circuit diagram of a limiter amplifier circuit which can control an output amplitude. The circuit shown in Fig. 7 additionally employs resistors 14a and 14b having a resistance R E1 connected to the emitters of transistors 5a and 5b in the circuit shown in Fig. 3, and also employs a variable current source circuit 13 in place of the first current source circuit. The gain of the circuit shown in Fig. 7 is given by R L1 /R E1 due to the feedback effect of the resistors 14a and 14b, and its output amplitude is given by I 1 ·R L1 . For this reason, the circuit shown in Fig. 7 has a function of adjusting an output amplitude by controlling a current I 1 while the gain is kept constant. In this circuit, even if the current I 1 is changed, bias voltages at output terminals 2a and 2b will not be changed due to the emitter follower effect of transistors 12a and 12b as same as circuit shown in Fig. 5 unlike in the conventional circuit shown in Fig. 1. Therefore, the circuit shown in Fig. 7 can be applied to a multi-stage amplifier circuit realized by DC direct coupling. The circuit arrangement shown in Fig. 7 is suitable for a monolithic IC with which a large-capacitance capacitor is difficult to realize. Fig. 8 shows input and output waveforms S1 and S2 when the circuit shown in Fig. 7 is used. As can be seen from these input and output waveforms, even if an input signal is increased, an output waveform can be prevented from being distorted due to the effect of the transistors 12a and 12b. Since the base-emitter voltage of the transistors 12a and 12b is applied as a reverse-bias voltage of the base-collector junction of the transistors 6a and 6b, even if a signal large enough to cause a switching operation is input to the input terminals 1a and 1b, a change in base-collector capacitance of the transistors 6a and 6b is smaller than in the conventional circuit. (5) Fig. 9 shows a wide-band amplifier circuit which can adjust a peaking amount. In the circuit shown in Fig. 9, the collectors of transistors 12a and 12b in the circuit shown in Fig. 3 are separated from the high-potential power supply terminal 3, and are connected to a control terminal 15, so that an arbitrary voltage can be independently applied. A voltage V PC applied to the control terminal 15 is controlled to adjust a junction capacitance as a load capacitance component between the bases and collectors of the transistors 12a and 12b, thereby adjusting a peaking amount. In the conventional circuit arrangement shown in Fig. 1, it is difficult to adjust the peaking amount. In addition, a monolithic amplifier circuit is assumed to suffer from a variation in the manufacture, and a circuit correction is not easy. Therefore, the circuit shown in Fig. 9 is effective for obtaining optimal band-width characteristics. Figs. 10 to 15 show embodiments of the present invention as logic circuit arrangements. In this case, Fig. 10 shows an n-input OR/NOR gate. The circuit shown in Fig. 10 has transistors 5a 2 to 5a n which are connected in parallel between the collector and emitter of a transistor 5a. N digital inputs are applied to the bases of these transistors, and a transistor 5b receives a reference voltage V R . Other arrangements are the same as those in Fig. 3. In this manner, an OR output appears at an output terminal 2a, and a NOR output appears at an output terminal 2b. Fig. 11 shows an emitter-follower type OR/NOR gate. The circuit shown in Fig. 11 has an input terminal la connected to the base of a transistor 5a, and transistors 18 1 to 18 n whose collectors are commonly connected to a high-potential power supply terminal 3. The bases of the transistors 18 1 to 18 n receive digital inputs. The emitters of these transistors are connected to a potential V EE through a current source 19. Fig. 12 shows an EXOR/EXNOR gate. In this circuit, differential pairs of transistors 19a and 19b, and 19c and 19d are additionally connected between transistors 5a and 5b and load resistors 7a and 7b, respectively. The common emitter of the transistors 19a and 19b is connected to the collector of the transistor 5a. Similarly, the common emitter of the transistors 19c and 19d is connected to the collector of the transistor 5b. The collector of the transistor 19a is connected to the resistor 7a and the collector of the transistor 19c, and the collector of the transistor 19d is connected to the resistor 7b and the collector of the transistor 19b. The bases of the transistors 19a and 19c are commonly connected to an input terminal 1c which receives a digital input. The bases of the transistors 19b and 19d are connected to a reference voltage V R1 ' (this voltage can be an input having a phase opposite to that at the terminal 1c) through a terminal 1d. An input terminal 1a of the transistor 5a receives another digital input. An input terminal 1b of the transistor 5b is connected to a reference voltage V R2 ' (this voltage can be an input having a phase opposite to that at the terminal 1a). Other arrangements are the same as those in Fig. 1. When digital inputs are supplied to the input terminals 1a and 1c, an EXNOR output appears at the terminal 2a, and an EXOR output appears at the terminal 2b. Fig. 13 shows an AND/NAND gate. The transistors 19c and 19d shown in Fig. 12 are omitted from the circuit shown in Fig. 13 to leave the transistors 19a and 19b. The collector of the transistor 19b is connected to the collector of a transistor 5b. The base inputs of the transistors 5a, 5b, 19a, and 19b are the same as those in Fig. 12. With this arrangement, when digital inputs are supplied to input terminals 1a and 1c, an AND output appears at a terminal 2a, and a NAND output appears at a terminal 2b. Fig. 14 shows a 2 : 1 multiplier. The transistors 19a and 19b, and 19c and 19d are used in the same manner as in Fig. 12 but have different I/O connections as follows. More specifically, the collector of the transistor 19a is connected to a resistor 7a and the collector of the transistor 19c, and the base of the transistor 19a is connected to an input terminal 1c which receives a digital input. The collector of the transistor 19b is connected to a resistor 7b, and its base is connected to a terminal 1d 1 which receives a reference voltage V R1 ' or an input having a phase opposite to that at the terminal 1c. The base of the transistor 19c is connected to a terminal 1e which receives a digital input. The collector of the transistor 19d is connected to the resistor 7b and the collector of the transistor 19b, and the base of the transistor 19d is connected to a terminal 1d 2 which receives the reference voltage V R1 ' or an input having a phase opposite to that at the terminal 1e. In this case, a terminal 1a connected to the base of a transistor 5a receives a clock signal. A terminal 1b connected to the base of a transistor 5b receives a reference voltage V R2 ' or an input having a phase opposite to that of the clock signal. With this arrangement, digital inputs supplied to the terminals 1c and 1e are subjected to 2 : 1 multiplication and appear at the terminals 2a and 2b, respectively. Fig. 15 shows an embodiment wherein the circuit shown in Fig. 14 is developed to constitute a D-latch. In this case, the emitters and bases of transistors 19a, 19b, 19c, and 19d are connected in the same manner as in Fig. 14 but connections of their collectors are different. More specifically, the collector of the transistor 19a is connected to a resistor 7a and the collector of the transistor 19d, and the collector of the transistor 19b is connected to a resistor 7b and the collector of the transistor 19c. Data is input to an input terminal 1c connected to the base of the transistor 19a, and a reference voltage V R1 ' or an input having a phase opposite to the data input is input to an input terminal 1d 1 connected to the base of the transistor 19b. Reference numerals 121a, 121b, 122a, and 122b denote emitter-follower transistors connected in series. The emitters of these transistors are connected to a low potential V EE through current sources 123 to 126. The base of the transistor 19d is connected to the emitter of the transistor 122a, and a Q latch output terminal 128a. The base of the transistor 19c is connected to the emitter of the transistor 122b and a Q latch output terminal 128b. With this arrangement, data input to the terminal 1c appears at the terminals 128a and 128b as Q and Q latch outputs. In this manner, when the present invention is applied to the logic circuits shown in Figs. 10 to 15, a good logic waveform shown in Fig. 8 can be obtained by the buffer effect of the transistors 12a and 12b. When a current flowed through a current source circuit of an amplifier included in a feedback load is changed, a DC output level and an output signal amplitude can be arbitrarily obtained. If the conventional circuit shown in Fig. 1 is applied to a logic circuit, since the current I 1 is flowed to the resistor 8a, it is very difficult to assure a high DC output level. Fig. 16 shows a decision circuit to which the present invention can be applied. In Fig. 16, reference numeral 31 denotes a pre-amplifier including the circuit shown in Fig. 3; 32, a data discriminating unit arranged at the output side of the pre-amplifier 31 and constituted by a master-slave type flip-flop, a data latch, or the like; and 33, an output buffer. Reference numeral 34a denotes a data input terminal; and 34b, a reference voltage input terminal. These terminals are connected to the inputs of the pre-amplifier. Reference numeral 35 denotes a clock input terminal for supplying a clock signal to the level discriminating unit 31. Reference numeral 36 denotes an identification output terminal. In this manner, when the circuit of the present invention is adopted as the pre-amplifier constituting the decision circuit, a high-gain, wide-band operation can be performed. Therefore, good decision sensitivity characteristics can be obtained over a wide frequency range. In circuits according to the present invention, 3-terminal amplifier elements including PNP or FETs (including MIS FETs) may be used in place of NPN bipolar transistors. As described above, according to the present invention, since emitter-follower transistors are added as a feedback means, the buffer effect can be provided, and the following effects can be obtained. (1) Characteristics over a larger band-width can be obtained. (2) A good logic waveform can be obtained due to the buffer effect of a transistor arranged in a feedback system of transistors included in a feedback load. (3) Since a high-gain, wide-band amplifier circuit can be obtained, if the present invention is applied to a decision circuit, a highly sensitive, high-speed decision circuit can be realized.

Claims: A logic circuit arrangement comprising: a plurality of digital signal input terminals (1a,1b,1c,1d,1e); and first and second digital signal output terminals (2a,2b;128a,128b); characterised by: first and second feedback load circuit arrangements connected between said input terminals and said output terminals; each said feedback load circuit arrangement comprising: (a) a first amplifier including a 3-terminal first amplifier element (5a) having an input terminal and two output terminals; and (b) a feedback load for said first amplifier; (c) said input terminal of said first amplifier element (5a) being arranged to receive an input signal from said digital signal input terminals, and one output terminal of said first amplifier element is connected to a first potential (4); (d) said feedback load comprises: (d1) 3-terminal second and third amplifier elements (6a,12a) each having an input terminal and two output terminals, and (d2) first and second impedances (7a,8a), (d3) said input terminal of said second amplifier element (6a) and one terminal of said first impedance (7a) are connected to the other output terminal of said first amplifier element (5a), one output terminal of said second amplifier element (6a) is connected to a second potential (4), and the other output terminal of said second amplifier element (6a) is connected to a third potential (3) through said second impedance (8a), and (d4) said input terminal of said third amplifier element (12a) is connected to said other output terminal of said second amplifier element (6a), one output terminal of said third amplifier element (12a) is connected to a fourth potential (3), and the other output terminal of said third amplifier element (12a) is connected to the other terminal of said first impedance (7a); and (e) said one output terminal of said first amplifier element (5a) of said first feedback load circuit arrangement and said one output terminal of said first amplifier element (5b) of said second feedback load circuit arrangement are commonly connected to constitute a first differential pair commonly connected to said first potential (4); (f) said one output terminal of said second amplifier element (6a) of said first feedback load circuit arrangement and said one output terminal of said second amplifier element (6b) of said second feedback load circuit arrangement are commonly connected to constitute a second differential pair commonly connected to said second potential (3); (g) said first and second digital signal output terminals are provided in the respective first and second feedback load circuit arrangements either at a connecting node between said second impedance (8a) and said other output terminal of said second amplifier element (6a) or at a connecting node between said first impedance (7a) and said other output terminal of said third amplifier element (12a). A logic circuit arrangement according to Claim 1 characterized in that each said first, second and third amplifier elements (5a,6a,12a) comprise transistors. A logic circuit arrangement according to Claim 1 or Claim 2 characterized in that each said first impedance (7a) includes a resistor (7a). A logic circuit arrangement according to any one of Claims 1 to 3 characterized in that a first current source (10) is connected between said one output terminal of each said first amplifier element (5a) and said first potential (4), and a second current source (11) is connected between said one output terminal of each said second amplifier element (6a) and said second potential (4). A logic circuit arrangement according to any one of Claims 1 to 4 characterized in that said third and fourth potentials (3) are equal to each other. A logic circuit arrangement according to Claim 1 characterised in that: said first amplifier in said first feedback load circuit arrangement comprises a plurality of said 3-terminal first amplifier elements (5a,5a2...5an) connected in parallel between the output terminals of said first amplifier elements; said plurality of digital signal input terminals (1a...1n) are connected to the respective input terminals of said plurality of first amplifier elements; and said first amplifier element (5b) of said second feedback load circuit arrangement is connected to a reference voltage signal source (VR); whereby said logic circuit arrangement constitutes an n-input OR/NOR gate. A logic circuit arrangement according to Claim 2 characterised by: a plurality of transistors (18-1...18-n) whose collectors are commonly connected to said third potential (3), and whose emitters are commonly connected to said first potential (4) and also to said input terminal of said first amplifier element (5a) in said first feedback load circuit arrangement; said plurality of digital signal input terminals (1a...1n) are connected to the respective bases of said plurality of transistors (181...18n); and said first amplifier element (5b) of said second feedback load circuit arrangement is connected to a reference voltage signal source (VR); whereby said logic circuit arrangement constitutes an emitter-follower OR/NOR gate. A logic circuit arrangement according to Claim 2 characterised by: first and second differential pairs of transistors (19a,19b;19c,19d) connected between said first transistors (5a,5b) and said first impedances (7a,7b) of said first and second feedback load circuit arrangements; the common emitter of the transistors (19a,19b) of said first differential pair being connected to the collector of said first transistor (5a) of said first feedback load circuit arrangement, and the common emitter of the transistors (19c,19d) of said second differential pair being connected to the collector of said first transistor (5b) of said second feedback load circuit arrangement; the collectors of the first transistor (19a) in the first pair and of the second transistor (19c) in the second pair being connected to said one terminal of said first impedance (7a) of said first feedback load circuit arrangement, and the collectors of the second transistor (19b) in the first pair and of the first transistor (19d) in the second pair being connected to said one terminal of said first impedance (7b) of said second feedback load circuit arrangement; the bases of the first transistors (19a,19d) in the first and second pairs being connected to a said digital signal input terminal (1c); the bases of the second transistors (19b,19c) in the first and second pairs being connected to a reference voltage signal source (1d); the input terminal of the first transistor (5a) of said first feedback load circuit arrangement being connected to another said digital signal input terminal (1a); and the input terminal of the first transistor (5b) of said second feedback load circuit arrangement being connected to another reference voltage signal source (1b); whereby said logic circuit arrangement constitutes an EXOR/EXNOR gate. A logic circuit arrangement according to Claim 2, characterised by: a differential pair of transistors (19a,19b) connected between said first transistor (5a) of said first feedback load circuit arrangement and said first impedances (7a,7b) of said first and second feedback load circuit arrangements; the common emitter of the transistors (19a,19b) of said pair being connected to the collector of said first transistor (5a) of said first feedback load circuit arrangement; the collector of the first transistor (19a) in the pair being connected to said one terminal of said first impedance (7a) of said first feedback load circuit arrangement, and the collector of the second transistor (19b) in the pair being connected to said one terminal of said first impedance (7b) of said second feedback load circuit arrangement; the base of the first transistor (19a) in the pair being connected to a said digital signal input terminal (1c); the base of the second transistor (19b) in the pair being connected to a reference voltage signal source (1d); the input terminal of the first transistor (5a) of said first feedback load circuit arrangement being connected to another said digital signal input terminal (1a); and the input terminal of the first transistor (5b) of said second feedback load circuit arrangement being connected to another reference voltage signal source (1b); whereby said logic circuit arrangement constitutes an AND/NAND gate. A logic circuit arrangement according to Claim 2 characterised by: first and second differential pairs of transistors (19a,19b;19c,19d) connected between said first transistors (5a,5b) and said first impedances (7a,7b) of said first and second feedback load circuit arrangements; the common emitter of the transistors (19a,19b) of said first differential pair being connected to the collector of said first transistor (5a) of said first feedback load circuit arrangement, and the common emitter of the transistors (19c,19d) of said second differential pair being connected to the collector of said first transistor (5b) of said second feedback load circuit arrangement; the collectors of the first transistor (19a) in the first pair and of the first transistor (19c) in the second pair being connected to said one terminal of said first impedance (7a) of said first feedback load circuit arrangement, and the collectors of the second transistor (19b) in the first pair and of the second transistor (19b) in the second pair being connected to said one terminal of said first impedance (7b) of said second feedback load circuit arrangement; the bases of the first transistors (19a,19d) in the first and second pairs being connected to respective individual said digital signal input terminals (1c,1e); the bases of the second transistors (19b,19c) in the first and second pairs being connected to respective reference voltage signal sources (1d1,1d2); the input terminal of the first transistor (5a) of said first feedback load circuit arrangement being connected to a clock signal source (1a); and the input terminal of the first transistor (5b) of said second feedback load circuit arrangement being connected to another reference voltage signal source (1b); whereby said logic circuit arrangement constitutes a 2:1 multiplier. A logic circuit arrangement according to Claim 2 characterised by: first and second differential pairs of transistors (19a,19b;19c,19d) connected between said first transistors (5a,5b) and said first impedances (7a,7b) of said first and second feedback load circuit arrangements; the common emitter of the transistors (19a,19b) of said first differential pair being connected to the collector of said first transistor (5a) of said first feedback load circuit arrangement, and the common emitter of the transistors (19c,19d) of said second differential pair being connected to the collector of said first transistor (5b) of said second feedback load circuit arrangement; the collectors of the first transistor (19a) in the first pair and of the second transistor (19d) in the second pair being connected to said one terminal of said first impedance (7a) of said first feedback load circuit arrangement, and the collectors of the second transistor (19b) in the first pair and of the first transistor (19c) in the second pair being connected to said one terminal of said first impedance (7b) of said second feedback load circuit arrangement; the base of the first transistor (19a) in the first pair being connected to a said digital signal input terminal (1c); the base of the second transistor (19b) in the first pair being connected to a reference voltage signal source (1d); the base of the first transistor (19c) in the second pair being connected to a Q latch output terminal; the base of the second transistor (19d) in the second pair being connected to a Q latch output terminal; the input terminal of the first transistor (5a) of said first feedback load circuit arrangement being connected to a clock signal source (1a); the input terminal of the first transistor (5b) of said second feedback load circuit arrangement being connected to another reference voltage signal source (1b); wherein there are provided first and second pairs of emitter-follower transistors (121a,122a;121b,122b) connected in series to the respective said first and second digital signal output terminals (2a,2b); the emitters of said emitter-follower transistors being connected to a low reference voltage through respective current sources (123,124,125,126); and the emitters of the second transistors in the first and second pairs of emitter-follower transistors also being connected respectively to said Q and Q latch output terminals; whereby said logic circuit arrangement constitutes a D-latch. A digital circuit arrangement characterised by: a logic circuit arrangement according to Claim 1; a data discriminating unit (32) having first and second inputs connected to said first and second digital signal output terminals (2a,2b) of said logic circuit arrangement; a clock signal source (35) connected to a clock input terminal of said data discriminating unit (32); an output buffer (33) connected to the output of said data discriminating unit; and an identification output terminal (36) connected to the output of said output buffer; whereby said digital circuit arrangement constitutes a decision circuit.

Inventors: ICHIHARA NOBORU, ICHINO HARUHIKO, ICHIHARA, NOBORU, ICHINO, HARUHIKO
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1989
Main classification: H03K19
IPC codes: H03F3, H03K19