Electroluminescent storage display with improved intensity driver circuits

Abstract: In the present invention a matrix array of organic electroluminescent storage display elements along with row and column selection circuitry (12, 14, 16) are used to select the particular display elements (40) within the matrix to be illuminated. Interposed between the column and row selection electronics are a plurality of memory cells (22) receiving as inputs bit values (B n -B o ) that correspond to the desired intensity requested from a display element (40). The memory cells (22) output activation signals which drive corresponding MOS switches (24) each of which in turn is parallel connected as part of a current driver source (28) feeding a single display element (40). Activation of one or more of the MOS switches (24) provides a controlled amount of current to be applied to the display element (40) to in turn provide a related amount of light from the display element (40).

Description: The present invention relates to the field of thin film electroluminescent display devices and, more particularly, to organic electroluminescent display devices with driver circuitry. Electroluminescence is the emission of a light from a luminescent material when an electrical field of proper value is applied to the material. This property has been utilized in the prior art to construct display panels. The first wave of devices were of the AC type which used the luminescent material as the dielectric in a parallel plate capacitor where one of the parallel plates was transparent. When an alternating voltage was applied to the parallel plates the luminescent material emitted light. By depositing rows of conductive material on one surface of the luminescent material and columns of conductive material on the opposite surface, an X-Y matrix is formed. At each crossover point of a column and a row a pixel for a video display is formed. With the proper excitation at the crossover points the pixel positioned at that point will emit light. Drive circuits are then coupled to the rows and the columns to vary the level of current or voltage that is applied as a function of the amount of light that is to be generated by each pixel. Advances in the electroluminescent material art have led to organic materials being used in such type displays which materials provide high brightness levels, and low DC voltage requirements along with multicolors. In addition, recent developments have resulted in display panels with a high density of addressable pixels. With such displays, it is desirable to be able to store imaging data so that the display can be operated without external memory and without continual refreshing. In addition, it would be advantageous to be able to control the brightness of the display with binary signals rather than analog signals thereby permitting the display to be driven by a computer. US-A-3,740,570, US-A-3,629,653 and US-A-4,559,535 disclose electroluminescent matrix pannels comprising column means and row means, each having a plurality of parallel outputs. A plurality of electroluminescent elements are actuated through a respective plurality of switch means. However, in said documents, the instant brightness of the elements is not modified. It is only the duration of the energisation which "fool" the human eye. It is already known by an article of C.W. Tang SA Vanslyke published in Applied Physics letter 51(12) on September 21, 1987 by American Institute of Physics to use organic electroluminescent diodes. The invention provides an electroluminescent storage display according to claim 1 wherein the brightness of the electroluminescent does not have to "fool" the human eye since each electroluminescent element is continuously energized by a current, the intensity of which is dependent on the brightness contemplated. According to one aspect of the present invention, each organic electroluminescent pixel element in a matrix of organic electroluminescent pixel elements is provided with a plurality of memory cells for receiving a corresponding plurality of binary input bits. The output of each memory cell is connected to a current driver such that each memory cell controls a portion of the total current applied to the pixel element. Each memory cell activates a MOS transistor to place it into parallel circuit with other activated MOS transistors such that the combination of parallel activated transistors controls the current flowing to the pixel element and in turn the intensity of the light generated by the pixel element. The memory driver circuit for each pixel element thus acts as a memory cell, a D/A converter, and as an electronic switch for controlling the current supplied to the pixel element. This particular driver configuration allows for a continuous, static current to be driven through the pixel element for each brightness level in response to a binary number. In turn, this reduces the peak drive current required to light the pixel elements and indirectly reduces the voltage and the power consumption levels for a matrix display incorporating the improved intensity drivers. Figure 1 is a block diagram illustrating the arrangement of an addressable matrix display incorporating the improved driver circuits. Figure 2 is a block circuit diagram of an improved driver circuit of the type used in Figure 1. Figure 3 is a transistor level schematic of a memory cell that may be used as a memory cell of Figure 2. Figure 4 is a transistor level schematic of a memory cell which also may be used as a memory cell of Figure 2. Figure 5 is a drawing of the layers of one type of electroluminescent device that can be used as the pixel element in a matrix of such elements. In Figure 1, a control logic circuit 10 receives incoming data (DATA IN) and other interface timing signals. The control logic synchronizes the incoming data with the signals PIXEL CLK, LINE CLK, and FRAME RST as is standard procedure. A SYSTEM CLK signal provides a high speed clock for controller internal timing. An IN/OUT line allows data to be read in and out of the memory storage. This mode is also useful in automating the testing of the display circuitry. The #PIXEL TO AVG. signal allows data from sources of varying resolution to be displayed. Normally, the data would be subsampled or otherwise pre-processed external to the display system. This feature allows the data to be averaged while it is incoming direct from the data source. A BRIGHTNESS CONTROL allows for an adjustment of the display brightness level for various applications. The level of this input may be controlled, for example, by a user through a potentiometer, by a light meter circuit, or by other means. Outputs from the control logic circuitry are directed to a column data register 12, a display input/readout logic circuit, and a row strobe register 16 over lines 6, 7, and 8, respectively. The parallel outputs 9 from the column data register 12 are connected to the display input/readout logic 14 to provide bidirectional data paths therebetween. The display input/readout logic 14 has a corresponding number of bidirectional lines output 15. The row strobe register 16 has a number of output lines 17 corresponding in number to the number of rows in a driven display matrix. A memory driver circuit 20 is connected to a column line 15 by means of a MOS switch 18 when the row line 17 associated with a memory driver circuit is selected (energized). The output of the memory driver circuit 20 is connected to an electroluminescent cell 40 (pixel element). An image display is formed by physically positioning a plurality of these pixel elements 40 closely together, generally in a matrix configuration of rows and columns or by forming the pixel elements 40 in a VLSI multilayer type structure. Each pixel element is provided with its own memory driver circuit 20. Within each memory driver circuit there is a memory cell 22 that is connected on its input via the switch 18 to the line 15. The output of the memory cell is connected to a current drive source 28. The current driver source is powered by a voltage supply +V to provide a driving current to the pixel element 40. The magnitude of the driving current is controlled by the output signal from the memory cell 22 which magnitude in turn determines the brightness level of the light emitted by the pixel element 40. The combination of an active IN signal and FRAME RST signal causes the controller 10 to load in new data for display. This is accomplished by setting the display input/readout 14 to its read-in state with an enable signal on line 7. The incoming data is averaged as directed by the #PIXEL TO AVG. signal, and then passed on to the memory driver circuitry 20. This is done by conveying the data serially to the column data register 12 over line 6 in a line-by-line fashion. When an entire line has been conveyed, the control logic sends out a pulse to the row strobe register 16 over line 8, which closes the transistor switch(s) 18 associated with that row, thereby enabling the transfer of column data to the memory cell(s) 22. Following the loading of the data, the row switch(s) 18 are re-opened and the next line is loaded. The combination of an active OUT signal and FRAME RST signal cause the control logic to set the display input/readout 14 to its read-out state. As each row strobe line 17 is enabled, and the logical state of each memory cell 22 is sensed on each column line 15, the data in each memory cell is transferred in parallel to the column data register 12 which serially conveys the data out, line-by-line on the serial out line. In Figure 2 a group of memory cells, 22n through 22n-3, responding to binary bit signals, B n through B n-3 activate one or more MOS transistors 24. The MOS transistors 24, 26, and 27 form the current driver 28 for driving the pixel element 40. The MOS transistors 26 and 27 are connected and sized to function as current mirrors, that is, the current through MOS transistor 27, which can be called I pixel , is equal to the current flowing through MOS transistor 26, which current can be called I₂. The current I₂ is a function of the number of MOS transistor 24 that are turned ON or OFF (actively connected in parallel). With all MOS transistors 24 turned ON the highest level of current flows through the pixel element 40. With all of the MOS transistors 24 in an OFF state the pixel element 40 is not illuminated. Generally speaking, when devices 26 and 27 are the same size the following relationship holds true: I pixel = I₂ + I n + I n+1 + · · · · . If each MOS transistor is fabricated to have a different current flow when it is ON then a selection can be made as to which transistors are turned ON, in combination, to achieve the desired intensity level. Selection of the MOS transistors 24 is accomplished by applying an enable signal to the ROW inputs of the memory cells 22n through 22n-3. The column bits are applied to the B n inputs prior to the ROW enable signal and are latched into the memory cells upon receipt of the ROW enable signal. Figure 3 illustrates a first circuit implementation for a memory cell 22 n . A column input, signal B n , is gated to the input of a CMOS inverter gate 36 and to one electrode of a MOS transmission gate 34 via a MOS transmission gate 30. A ROW input is connected to the input of a CMOS inverter 32, to the gate electrode of the MOS transistor 34, and to the gate electrode of the MOS transistor 30. One electrode of the MOS transistor 34 is connected to the input to a CMOS inverter 38. The output of the memory cell 22 n directed to the gate electrode of an associated MOS transistor 24. Figure 4 illustrates a second circuit implementation for a memory cell 22 n . A MOS transistor 31 has its drain electrode connected to receive the signal B n , its gate electrode is connected to receive the ROW signal and its source electrode is connected to the inputs of CMOS inverters 33 and 35. The outputs from inverter 33 and inverter 35 are connected to the gate electrode of an associated MOS transistor 24. Referring to Figure 5, the pixel element 40 is formed on a glass base 41 having an indium-tin-oxide (ITO) layer 42 vacuum deposited thereon. A positive electrode is affixed to layer 42. A first organic layer 43 of an aromatic diamine is vacuum deposited on layer 42. A second organic layer 44 is a luminescent ALq₃ film which is vacuum deposited onto layer 43. An electrode 45, which is an alloy or mixture of magnesium and silver (MgAg), is vacuum deposited onto layer 44. A conductor is connected to layer 45 and to a source of negative potential, with respect to the positive potential of layer 42. The device thus formed is an organic electroluminescent diode which is responsive to d.c. to provide a light output. Such a device is described in detail in an article entitled "Organic Electroluminescent Diodes" by C.W. Tang, Appl. Phys. Lett. 51(12), 21 September 1987, pps 913 and 914. To form a large scale display a plurality of these elements can be positioned together in a frame type structure or they may be fabricated as either a single or as separate VLSI chips which are interconnected to form the display.

Claims: Electroluminescent storage display comprising : a column means (12, 9, 14) having a plurality of parallel outputs (15) ; a row means (16) having a plurality of parallel outputs (17) ; a plurality of switch means (18), each connected to a respective one of said plurality of row outputs (17) for connecting a respective one of said column outputs (15) to a switch output ; a plurality of electroluminescent elements (40), each actuated by one of said plurality of switch means (18) ; characterized in that each electroluminescent element is associated with a plurality of memory elements (22) ; a current source (28) connected in circuit to said electroluminescent element (40) ; a plurality of current control elements (24), corresponding in number to said plurality of memory elements (22), each connected to a respective memory element (22) and responsive to the signals stored therein for causing a current being incremental in dependence of said signals to flow from said current source (28) to said electroluminescent element (40) ; and means (10, 12, 14, 16, 18) for applying signals (B n -B o ) to said memory elements (22) indicative of the intensity desired from said electroluminescent element (40). Electroluminescent storage display of claim 1 wherein said plurality of elements (24) are MOS transistors each having a gate electrode connected to a respective memory element (22). Electroluminescent storage display of claim 1 wherein said means for applying signals to said memory elements is comprised of : a plurality of binary bits (B n -B o ) corresponding in number to said plurality of memory elements (40) and an enabling signal source for providing an enabling signal (16) for loading said binary bits (B n -B o ) into said memory elements (22). Electroluminescent storage display of claim 1 wherein the column means comprises : a column data register means (12) having an input (6) for serially receiving image signals, and having a plurality of parallel outputs (9) for providing said image signals thereon ; an input/output logic means (14) responsive to an enable signal (7), and coupled to the plurality of parallel outputs (9) of said column register means (12) for gating said image signals to respective column outputs (9). An electroluminescent storage display according to claim 4 and further comprising : a control logic means (10) responsive to input control signals, image data signals and brightness signals for providing image signals to said column register means (12), enable signals (7) to said input/output logic means (14), and an input signal (8) to said row register means (16). An electroluminescent storage display according to any of the preceding claims wherein each of said plurality of current sources (28) is comprised of : a two MOS device current mirror (26, 27), with the first of said MOS devices (27) connecting said electroluminescent element (40) to a source of power (+V) and with the second of said MOS devices (26) connecting said source of power to a selectable current means (24) ; and a selectable current means (24) connected to said plurality of storage means (22) and responsive to the signals stored therein for causing the current in said second MOS device (26) to be a function of the signals (B n -B o ) stored in said plurality of storage means (22).

Inventors: BELL CYNTHIA SUE EASTMAN KODAK, GABOURY MICHAEL JOSEPH EASTMAN, BELL, CYNTHIA SUE EASTMAN KODAK COMPANY, GABOURY, MICHAEL JOSEPH EASTMAN KODAK COMPANY
Applicants: EASTMAN KODAK CO, EASTMAN KODAK COMPANY (A NEW JERSEY CORPORATION)
Application year: 1989
Main classification: G09G3
IPC codes: G09G3, H04N3, H01L27, H05B33, H01L51