Integrated trench-transistor structure and fabrication process

Abstract: An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer (12) is grown on a substrate (10) and contains an n-well (14), and n+ source (16) and p+ source regions (18). Shallow trenches (20, 22) are disposed in the epitaxial layer (12) and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region (24) connects the trenches (20, 22) and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer (26) of silicon dioxide on the trench walls of the gates. The p+ drain region (28), along with the filled trench gate element and the p+ source region (18), form a vertical p-channel (PMOS) trench-transistor. The n+ drain region (30), along with filled trench gate element and the n+ source (16) form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions (34) and an oxide layer (38).

Description: The present invention relates to complementary metal-oxide-semiconductor (CMOS) fabrication methods and devices and, more particularly, to the fabrication and structure of vertical trench CMOS devices for integrated circuits. U.S. Patent 4,670,768 issued June 2, 1987 to Sunami et al, entitled COMPLEMENTARY MOS INTEGRATED CIRCUITS HAVING VERTICAL CHANNEL FETS, describes a CMOS having a vertical channel with a gate metal disposed vertically in a groove. More specifically, a semiconductor integrated circuit is described comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film. A MOSFET with a vertical channel is shown in JP-A-583287 to Furumura, entitled VERTICAL CYLINDRICAL MOS FIELD EFFECT TRANSISTOR, more particularly, to improve the integrtion of an MOS field effect transistor and to form a flat structure for forming a source region and a drain region in the end surface of vertical hollow cylindrical insulating layer buried with a gate electrode, an insulating layer is formed in a vertical hollow cylindrical shape sequentially with bottom regions to become drain or source formed in contact with or above the outside surface. In U.S. Patent 4,319,932 issued March 16, 1982 to Jambotkar, entitled METHOD OF MAKING HIGH PERFORMANCE BIPOLAR TRANSISTOR WITH POLYSILICON BASE CONTACTS, the step of doping a substrate from a deposited polysilicon layer is shown. Bipolar transistor devices are formed by employing polysilicon base contacts self-aligned with respect to a diffusion or ion implantation window used to form emitter, intrinsic base and raised subcollector regions. The polysilicon acts as a self-aligned impurity source to form the extrinsic base region therebelow and, after being coated with silicon dioxide on its surface and along the sidewalls of the diffusion or ion implantation window, as a mask. Directional reactive ion etching is used to form a window in the silicon dioxide while retaining it along the sidewalls. Ion implantation, for example, may be used to form, through the window, an emitter, intrinsic base and raised subcollector region. The silicon dioxide is used as an insulator to separate the emitter contact from polysilicon. U.S. Patent 4,523,369 issued June 18, 1985 to Nagakubo et al, entitled METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, shows a method including the step of forming a sidewall layer which is used for defining a trench. The method for manufacturing more particularly includes the steps of: forming a first mask member which has an opening to expose a desired portion of one major surface of a semiconductor substrate, doping an impurity which has the same conductivity type as that of the semiconductor substrate through the opening of the first mask member to form an impurity region of a high concentration in the surface layer of the semiconductor substrate; forming second mask member on the side surface of the opening of the first mask member while the first mask member is left as it is; forming a groove by selectively etching the semiconductor substrate using the first and second mask members, and at the same time leaving an impurity region of the high concentration at least on the side surface of the groove; and burying an insulating isolation material in the groove. Other patents related to the field of FETs, CMOS, V-grooves and trenches include the following: U.S. Patent 4,509,991 issued April 9, 1985 to Taur, entitled SINGLE MASK PROCESS FOR FABRICATING CMOS STRUCTURE; U.S. Patent 4,517,731 issued May 21, 1985 to Khan et al, entitled DOUBLE POLYSILICON PROCESS FOR FABRICATING CMOS INTEGRATED CIRCUITS; U.S. Patent 4,455,740 issued June 26, 1984 to Iwai, entitled METHOD OF MANUFACTURING A SELF-ALIGNED U-MOS SEMICONDUCTOR DEVICE; U.S. Patent 4,541,001 issued September 10, 1985 to Schutten et al, entitled BIDIRECTIONAL POWER FET WITH SUBSTRATE-REFERENCED SHIELD; U.S. Patent 4,454,647 issued June 19, 1984 to Joy et al, entitled ISOLATION FOR HIGH DENSITY INTEGRATED CIRCUITS; U.S. Patent 3,893,155 issued July 1, 1975 to Ogiue, entitled COMPLEMENTARY MIS INTEGRATED CIRCUIT DEVICE ON INSULATING SUBSTRATE; U.S. Patent 4,131,907 issued December 26, 1978 to Ouyang, entitled SHORT-CHANNEL V-GROOVE COMPLEMENTARY MOS DEVICE. An object of the present invention is to provide structure and fabrication process for an integrated self-aligned CMOS trench-transistor employing a vertical trench strapping transistor to bias the buried source of vertical CMOS devices. Another object of the present invention is to provide structure and fabrication process for an integrated trench-transistor device for high density VLSI applications. Another object of the present invention is to provide a three-dimensional integrated transistor structure which has a vertical transistor built on the surfaces of a U-groove between the surface of the silicon and a buried source junction beneath the U-groove. Another object of the present invention is to provide an improved fabrication process for providing a self-aligned silicide layer on a silicon surface and interconnection layer and over predefined contacts and interconnection layer, which forms a self-aligned contact connection. Another object of the present invention is to provide an improved fabrication process for providing small coupling capacitances between the gate and drain junctions by using the side-wall spacer technology. Still another object of the present invention is to provide an improved fabrication process for providing a flat topography structure after forming gate level and then several additional levels of interconnection metallurgy can be easily added. Another object of the present invention is to provide a fabrication method for a vertical transistor where only one contact area for drain junction is needed, the other gate and source contacts are contained within the same area. A further object of the present invention is to provide a layout method using the buried junction as common source. A further object of the present invention is to provide a vertical strapping transistor and vertical CMOS transistors combination for use as an inverter circuit. Still another object of the present invention is to provide a vertical strapping transistor and vertical CMOS transistors combination for use as a NOR gate. Another object of the present invention is to provide a vertical strapping transistor and vertical CMOS transistors combination for use as a NAND gate. And another object of the present invention is to provide an interdigated layout for vertical CMOS transistors. An integrated, Self-aligned trench-transistor structure according to the present invention is defined in claim 1. Claim 12 defines a method of fabricating a structure according to claim 1. The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the invention as illustrated in the accompanying drawings. Fig. 1 is a schematic illustration of a vertical cross section of an embodiment of a trench-transistor CMOS structure according to the principles of the present invention. Fig. 2 is a schematic illustration of a horizontal cross section of the trench-transistor CMOS structure of Fig. 1. Figs. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 and 13 show schematic cross-sectional views illustrating various stages in the fabrication of the trench-transistor CMOS structure of Fig. 1 and Fig. 2 employing a method according to the principles of the present invention. Fig. 14 is a schematic circuit diagram illustrating the trench-transistor CMOS structure of the present invention employed as an inverter. Figs. 15 and 16 are schematic illustrations of the vertical cross sections and plan view of the inverter circuit of Fig. 14. Fig. 17 is a schematic circuit diagram illustrating the trench-transistor CMOS structure of the present invention employed as a combination NOR-NAND gate. Figs. 18 and 19 are schematic illustrations of the vertical cross sections and plan view of the inverter circuit of Fig. 17. Figs. 20 and 21 are schematic drawings of a vertical MOS transistor structure for interdigit layout. Figs. 22 and 23 are schematic illustrations of the vertical cross sections and plan view of the structure of Fig. 21. In present VLSI technology, three dimensional active devices have demonstrated significant advantages. In Fig. 1, a new design of an integrated, self-aligned trench-transistor technology is illustrated. The use of a vertical trench-transistor called "strapping transistor", to bias the common buried source of the vertical transistor is also described. The cross section of this new concept of trench CMOS device and vertical "strapping transistor" is shown in Fig. 1 and a plan view of the structure of Fig. 1 is shown in Fig. 2. The shallow trench-transistors and the strapping trench-transistors are built on top of the buried source junctions. The layout of this structure provides the advantages of flexibility in the biasing of buried junctions in integrated circuit technology. The circuit layout designs are no longer necessary for the use of the substrate to serve as the common terminal. The interdigated layout technique using vertical transistors and CMOS devices can be achieved successfully. This technique provides higher packing density for circuit layout design. More particularly, the embodiment illustrated in Fig. 1 includes a substrate 10. The structure of Fig. 1 will be described with specific conductivities provided, for example, substrate 10 may be p+, however, one skilled in the art will know that the p, n and signal polarities may be different in other embodiments. A p- epitaxial layer 12 is grown on substrate 10 and contains n-well 14, an n+ source 16 and p+ source 18 regions. Shallow trenches 20 and 22 are disposed in epitaxial layer 12 and contain n+ polysilicon 58 or metal, such as tungsten 62, to provide the trench CMOS gates. A gate contact region 24 connects trenches 20 and 22 and the n+ polysilicon 58 or metal 62 in trenches 20 and 22. The n+ polysilicon 58 or metal 62 in trenches 20 and 22 are isolated by a thin layer 26 of silicon dioxide on the trench walls of the gates. The p+ drain region 28, along with filled trench gate element 24 and p+ source region 18, form a vertical p-channel (PMOS) trench-transistor. Likewise, the n+ drain region 30, along with filled trench gate element 24 and n+ source 16 form a vertical n-channel (NMOS) trench-transistor. The PMOS and NMOS trench-transistors are isolated by shallow trench isolation regions 34 and an oxide layer 38 disposed over the epitaxial layer 12. An important feature of the PMOS and NMOS trench-transistors is the silicon nitride spacer regions 36 and the self-aligned feature of the contiguous drain regions 28 and 30. The structure of Fig. 1 further includes the vertical trench strapping transistors 40 and 42. Vertical trench-transistor 40 includes a vertical trench 44 filled with n+ polysilcon 58 or metal such as tungsten 62 which extends to the p+ source region 18. The trench 44 is lined with thin gate oxide 46. Strapping transistor 40 is a vertical PMOS trench-transistor which includes p+ drain regions 48 along with filled trench gate element 44 and p+ source region 18 and further includes nitride spacers 36 and shallow trench isolation regions 34. Strapping transistor 42 is a vertical NMOS trench-transistor which includes n+ drain regions 30 along with filled trench gate element 50 with n+ polysilcon 58 or metal such as tungsten 62 which extends to the n+ source region 16. The trench 50 is lined with thin gate oxide 46. Strapping transistor 42 further includes nitride spacers 36 and shallow trench isolation regions 34. An embodiment of a novel process sequence to fabricate the vertical n- and p- channel MOS field-effect transistors (NMOS and PMOS) is described in the following steps: (Step 1) A p- doped monocrystalline silicon film 12 is grown epitaxially on p+ doped substrate 10. A composite layer 13 of pad SiO₂ 15 and Si₃N₄ 17 is formed on epitaxial layer 12. After suitable lithography and photoresist steps, an opening is made in the photoresist layer to expose the regions for n-well formation. Then n-type dopants are implanted through the composite layer of SiO₂ and Si₃N₄ on the substrate to form retrograde n-well 14 regions. Photoresist outside the n-well region blocks the n-type implantation. After the photoresist is removed, a short thermal cycle is used to drive in the n-type dopant into the p- epi layer 12 (Fig. 3). (Step 2 ) A composite layer 23 of SiO₂ 25 and Si₃N₄ 27 is formed on epitaxial layer 12. After suitable lithography and photoresist steps, then p-type dopants are implanted through the composite layer of SiO₂ and Si₃N₄ on the surface of n-well to form a p+ buried junction region 18. Then the composite layer of SiO₂ and Si₃N₄ is removed. The p+ buried junction region 18 will be formed as a common p+ source junction of the vertical p-channel (PMOS) trench-transistor (Fig. 4). Next, after suitable lithography and photoresist steps, then n-type dopants are implanted through the composite layer of SiO₂ and Si₃N₄ on the surface of outside n-well region to form a n+ buried junction region 16. Then the composite layer of SiO₂ and Si₃N₄ is removed. The n+ buried junction region 16 will be formed as a common n+ source junction of the vertical n-channel (NMOS) trench-transistor (Fig. 5). (Step 3) A composite layer of pad SiO₂ and Si₃N₄ is formed on the substrate. After suitable lithography and photoresist steps, then p-type field dopants are implanted through the composite layer of SiO₂ and Si₃N₄ on the surface of substrate. After suitable lithography and photoresist steps, the composite layer which remains is then used to mask the etch of a shallow trench isolation 34 into substrate 10 by RIE (reactive ion etching). A thin oxide is grown over the shallow trench isolation 34 surface, followed by depositing a thick oxide layer to fill the shallow trench isolation and planarization to result in a coplanar surface between the oxide isolation 34 and substrate surface (Fig. 6). (Step 5) A composite layer of pad SiO₂ and Si₃N₄ is formed on epitaxial layer 12. After suitable lithography and photoresist steps, then medium p-type dopants are implanted through the composite layer of SiO₂ and Si₃N₄ on the surface of n-well to form a buried p-channel threshold-controlled region 56. Next, after suitable lithography and photoresist steps, then medium n-type dopants are implanted through the composite layer of SiO₂ and Si₃N₄ on the surface of outside n-well region to form a buried n-channel threshold-controlled region 54. Then the composite layer of SiO₂ and Si₃N₄ is removed (Fig. 7). (Step 6) A thin lightly doped polysilicon layer 66 is deposited on the surface of the epitaxial layer 12. Then a composite layer of pad SiO₂ and Si₃N₄ is formed on polysilicon layer 66. After suitable lithography and photoresist steps, then p-type dopants are implanted through the composite layer of SiO₂ and Si₃N₄ on the surface of n-well to form p+ doped polysilicon 60 self-aligned contact regions. Next, after suitable lithography and photoresist steps, then n-type dopants are implanted through the composite layer of SiO₂ and Si₃N₄ on the surface of outside n-well region to form n+ doped polysilicon 58 self-aligned contact regions. Then the composite layer of SiO₂ and Si₃N₄ is removed (Fig. 8). (Step 7) A thin metal film (e.g., titanium) is deposited on the surfaces of the eptiaxial layer 12 and polysilicon layers. The metal silicide (e.g., titanium silicide) is formed over the exposed polysilicon areas under a proper heat treatment. Then the remaining unreacted metal (titanium) film is oxidized by heating in oxygen at proper temperatures for a period of time. A thick metal oxide (titanium oxide) which can act as an etch stop is formed. Next, a thick low pressure CVD silicon oxide layer 38 is blanketed over the surface of the substrate 10 (Fig. 9). (Step 8) After suitable lithography steps, an opening is made in the silicon oxide layer 38. The silicon oxide layer 30 which remains is then used to mask the etch of gate opening areas 19 into silicide 61 and polysilicon layers, 58 and 60 by using two different reactive ion etch (RIE) steps (Fig. 10). (Step 9) A silicon nitride layer is chemically deposited over the surface of substrate. The sidewall silicon nitride spacer 36 is formed by RIE nitride at proper treatments (Fig. 11). (Step 10) The sidewall nitride spacer is then used to mask the etch shallow trench using RIE into the substrate 10 to form vertical transistor regions 20, 22, 40, and 42. The depth of this shallow trench is designed to connect to the buried source region (Fig. 12). (Step 11) Grow a thin gate oxide on the vertical walls at the shallow trench and on the other area. Because of the high diffusivity of thin n+ and p+ polysilicons, the self-aligned drain junctions of the vertical n-channel and p-channel transistors are formed automatically through this hot temperature cycle (Fig. 13). The thin gate oxide of the reach-through trench acts as the transfer gate oxide of the trench-transistors. (Step 12) Fill shallow trench with CVD n+ polysilicon or metal (e.g., tungsten), chem-mech polishing and pattern to form the transfer gate and the contact. The rest of the fabrication processes are kept the same as standard CMOS technology to complete the chip fabrication procedures. The final cross section of the trench CMOS device and strapping transistor is shown in Fig. 1. It should be noted that planar transistors can also be fabricated and incorporated with vertical transistors. Thus, the planar transistor can be used for performance-driven circuits. And it is preferred that the vertical transistor is employed for density-driven or pitch-limited circuits. The function of the strapping transistors 40 and 42 is to input the power supply voltage to the buried source regions of the vertical transistors. The advantages of the integrated trench-transistor technology in particular applications and embodiments are described hereinbelow. Trench CMOS Inverters Design: Fig. 14 is an example of a set of vertical CMOS inverters. Referring to Fig. 14, an application of the vertical CMOS devices of the present invention as inverters is shown. The VDD voltage is supplied to the gates and drains of the strapping transistors 40, 42 through hardwires when the power supply is ramped up. In this case, the voltage may also be supplied through a chain of inverters if planar transistors were used. As a result, both strapping transistors are turned on so that the VDD and ground can be supplied to the buried source regions. The cross section and its layout of the inverter are shown in FIGS. 15 and 16, respectively. For simplicity, its cross section only shows the front-end-of-the-line. The NMOS acts as driver and PMOS acts as load. Two MOSFETs are in series with drain tied together and output taken from this node to connect to the next stage. The two gates are connected and the input is applied to the common gate. The buried sources 16 and 18 of NMOS and PMOS are connected to the power supply and ground through the two different strapping transistors, respectively. The reduction of the layout areas are clearly demonstrated. Trench CMOS NOR and NAND Gate Design: A vertical CMOS NOR gate is obtained by connecting NMOS drivers in parallel and PMOS loads in series. A vertical CMOS. NAND gate is obtained by connecting NMOS drivers in series whereas the corresponding PMOS loads are placed in parallel. The configuration of the combination of NOR-NAND gate is shown in Fig. 17. The cross section of this gate and its layout are shown in FIGS. 18 and 19, respectively. There are two types of buried junctions: one type serves as the intra-connection islands 17 and 19 of two vertical transistors, its potential level is left floating; and the other type serves as the common sources 16 and 18 of the vertical transistors and is connected to the outside world through the "strapping transistors". The biasing conditions for each strapping transistors (NMOS and PMOS) are shown in FIGS. 18 and 19. Vertical Interdigated Layout Design: The effective channel length of the vertical transistor is determined by the thickness of epitaxial layer minus the shallow drain junction depth. For a larger sized vertical MOS transistor, the new interdigated layout method should be used. The circuit diagram of a typical example of a vertical transistor with larger W/L ratio is shown in Fig. 20 together with its cross section and layout diagrams (FIGS. 21 and 22). Here again, the strapping transistor is built on top of the buried source junction and is biased to any controllable voltage levels. The gates of active transistors are folded in the vertical direction and the drains of the active transistors are shared with the same top drain junction. All the isolation regions between each drain regions are saved. This method will lead to the advantages of reduction of transistor area, higher packing density and the flexibility in circuit layout design. The integrated vertical CMOS devices are now available to perform a wide variety of logic and memory functions, for example: flip-flops, registers, decoders and SRAM cells.

Claims: An integrated, self-aligned trench-transistor structure comprising: a substrate of (10) semiconductor material, a layer (12) of epitaxial material of a first conductivity type located on said substrate (10), a well region (14) of a second different conductivity type disposed in said epitaxial layer (12), a first buried source element region (18) of said first conductivity type disposed in said well region (14), a second buried source element region (16) of said second conductivity type disposed in said epitaxial layer (12) proximate to said well region (14), a first trench (20) disposed in said well region (14) and extending into said first buried source element region (18), said first trench (20) including a layer (26) of isolation material on the walls thereof and being filled with conductive material to form a first filled trench gate element region, a second trench (22) disposed in said epitaxial layer (12) and extending into said second buried source element region (16), said second trench (22) including a layer (26) of isolation material on the walls thereof and being filled with conductive material to form a second gate filled trench element region, a layer (38) of oxide isolation material disposed over said epitaxial layer (12), said oxide layer having openings located over said first and second trenches (20, 22) wherein said openings in said oxide layer are filled with conductive material in contact with said conductive material in said first and second trenches and wherein said conductive material is disposed in said openings in said oxide layer and isolated from said oxide layer by vertical silicon nitride spacer regions (36) which are disposed in said openings and located on the surface of said epitaxial layer at the edges of said first and second trenches, a first drain element region (28) of said first conductivity type disposed in the surface of said well region (14) around said first filled trench (20) and extending to the wall of said first trench (20), a second drain element region (30) of said second conductivity type disposed in the surface of said epitaxial layer (12) around said second filled trench (22) and extending to the wall of said second trench (22), said first filled trench gate element region, said first buried source element region (18) and said first drain element region (28) forming a first conductivity type vertical transistor, said second filled trench gate element region, said second buried source element region (16) and said second drain element region (30) forming a second conductivity type vertical transistor, and a region (24) of conductive material connecting said conductive material in said first trench (20) and said conductive material in said second trench (22). The integrated, self-aligned trench-transistor structure according to claim 1 wherein said epitaxial layer (12) is composed of p-type material, said well region (14) is composed of n-material, said first buried source element region (18) is composed of p+ material, said first drain element region (28) is composed of p+ material to form in combination with said first trench gate element a vertical p-channel first PMOS trench-transistor, said second buried source element region (16) is composed of n+ material, and said second drain element region (30) is composed of n+ material to form in combination with said second trench gate element a vertical n-channel first NMOS trench-transistor. The integrated, self-aligned trench-transistor structure according to the claim 1 or 2 wherein a region (34) of isolation material is disposed in the surface of said epitaxial layer (12) intermediate said PMOS and NMOS vertical trench-transistors. The integrated, self-aligned trench-transistor structure according to any one of the claims 1 to 3 further including a third trench (44) disposed in said well region (14) and extending into said first buried source element region (18) in said well region (14) proximate to said first trench (20), said third trench (44) being filled with conductive material (58/62) to form a third gate element region, a third drain element region (48) disposed in the surface of said well region (14) around said third trench(44), said third trench gate element region, said first source element region (18) and said third drain element region (48) forming a first conductivity type vertical trench strapping transistor (40). The integrated, self-aligned trench transistor structure according to claim 4 further including a fourth trench (50) disposed in said epitaxial layer (12) and extending into said second buried source element region (16), proximate to said second trench (22), said fourth trench (50) being filled with conductive material to form a fourth gate element region, a fourth drain element region (30) disposed in the surface of said epitaxial layer (12) around said fourth trench (50), and said fourth filled trench gate element region, said second source element region (16) and said fourth drain element region (30) forming a second conductivity type vertical trench strapping transistor (42). The integrated, self-aligned trench-transistor structure according to claim 4 wherein said third drain element region (48) is composed of p+ material to form in combination with said first p+ material buried source element region (18) and said third trench gate element region a vertical second PMOS strapping transistor. The integrated, self-aligned trench-transistor structure according to claim 5 or 6 wherein said fourth drain element region is composed of n+ material to form in combination with said second n+ material buried source element region (16) and said fourth trench gate element region a vertical second NMOS strapping transistor. The integrated, self-aligned trench-transistor structure according to claim 4 or 5 further including a layer (38) of oxide isolation material disposed over said epitaxial layer (12), said oxide layer having openings located over said third and fourth trenches (44, 50) wherein said openings in said oxide layer are filled with conductive material in contact with said conductive material in said third and fourth trenches, and wherein said conductive material disposed in said openings in said oxide layer (38) is isolated from said oxide layer by vertical nitride spacer regions (36) disposed in said openings. The integrated, self-aligned trench-transistor structure according to any one of the claims 4 to 8 wherein said third and fourth trenches (44, 50) include a layer (46) of isolation material on the walls thereof, and wherein regions (34) of isolation material are disposed on the surface of said epitaxial material between said first and third trenches (20, 44) and said second and fourth trenches (22, 50). The integrated, self-aligned trench-transistor structure according to claims 9 further including a third PMOS vertical transistor disposed in said first buried source element region (18) in said well region (14) having drain and gate elements similar to said first PMOS vertical transistor, a third NMOS vertical transistor disposed in said second buried source element region (16) in said epitaxial layer having drain and gate elements similar to said first NMOS vertical transistor, means for connecting a voltage source to said gate elements of said second PMOS vertical strapping transistor and said second NMOS vertical strapping transistor, means for connecting a voltage source to said third drain element of said second PMOS vertical strapping transistor, means for connecting a reference potential to said fourth drain element of said second NMOS strapping transistor; an input signal terminal connected to said first and second gate elements of said first PMOS and first NMOS vertical trench-transistors, and an output signal terminal connected to said drain elements of said third PMOS and third NMOS vertical transistors to provide a CMOS inverter structure. The integrated, self-aligned trench-transistor structure according to claim 9 further including a third buried source element disposed proximate to said first buried source element region (18) in said n-well region in said epitaxial layer, a fourth buried source element disposed in said epitaxial layer proximate to said second buried source element region (16), a third PMOS vertical transistor disposed in said first buried source element region (18) in said well region (14) having drain and gate elements similar to said first PMOS vertical transistor, a third NMOS vertical transistor disposed in said second buried source element region (16) in said epitaxial layer having drain and gate elements similar to said first NMOS vertical transistor, fourth and fifth PMOS vertical transistors disposed in said third buried source element and having drain and gate elements similar to said first, second and third PMOS vertical transistors, fourth and fifth NMOS vertical transistors disposed in said fourth buried source element and having drain and gate elements similar to said first, second and third NMOS vertical transistors, means for connecting a voltage source to said third drain element of said second PMOS strapping transistor and to said third gate element of said second NMOS strapping transistor, means for connecting a reference source to said third gate element of said second PMOS strapping transistor and to said third drain element of said second NMOS strapping transistor, means for connecting said gate elements of said first NMOS and fourth PMOS vertical transistors together to a first input terminal, means for connecting said gate elements of said third NMOS and fifth PMOS vertical transistors together to a second input terminal, means for connecting said gate element of said fourth NMOS and first PMOS vertical transistor together to a third input terminal, means for connecting said gate elements of said third PMOS vertical transistor, said drain element of said fifth PMOS vertical transistor, said gate element of said fifth NMOS and said drain element of said third NMOS transistor together, and means for connecting said drain elements of said first PMOS; third PMOS and fifth NMOS vertical trench-transistors to an output terminal to provide a vertical CMOS NOR/NAND gate structure. A method of fabricating an integrated, self-aligned trench-transistor structure according to claim 1 comprising the steps of: Step 1) Form an epitaxial layer (12) of a first conductivity type on a semiconductor substrate (10); Step 2) Using photoresistive and lithographic techniques, form a well region (14) of a second different conductivity type in said epitaxial layer (12) and implant dopants into said well region (14) to provide a first buried source element region (18) of said first conductivity type; Step 3) Using photoresistive and lithographic techniques, implant dopants into said epitaxial layer outside said well region (14) to form a second buried source element region (16) of said second conductivity type; Step 4) Form a composite layer of pad SiO₂ and Si₃N₄ on said substrate and using lithographic and photoresistive techniques, implant field dopants through said composite layer of SiO₂ and Si₃N₄ on the surface of said epitaxial layer (12) where a shallow trench isolation (34) is to be formed in step 5); Step 5) After using suitable lithography and photoresist steps, said composite layer which remains is then used to mask the etch of a shallow trench isolation into said epitaxial layer (12) by reactive ion etching; Step 6) Grow a thin oxide over said shallow trench isolation surface, followed by depositing a thick oxide layer to fill said shallow trench isolation to provide a coplanar surface between the oxide isolation and the surface of said epitaxial layer (12); Step 7) Form a composite layer of pad SiO₂ and Si₃N₄ on said epitaxial layer and after suitable lithography and photoresist steps, implant dopants through said composite layer of SiO₂ and Si₃N₄ on the surface of said well to form a first buried channel threshold-controlled regio (56); Step 8) After suitable lithography and photoresist steps, implant dopants through said composite layer of SiO₂ and Si₃N₄ on the surface of said epitaxial layer outside said well region to form a second buried channel threshold-controlled region (54); Step 9) Remove said composite layer of SiO₂ and Si₃N₄ and deposit a thin lightly doped polysilicon layer (66) on the surface of said epitaxial layer; Step 10) Form a composite layer of pad SiO₂ and Si₃N₄ on said thin lightly doped polysilicon layer and after suitable lithography and photoresist steps, implant dopants through said composite layer of SiO₂ and Si₃N₄ on the surface of said well to form first doped polysilicon self-aligned contact regions (60) of said first conductivity type; Step 11) After suitable lithography and photoresist steps, implant dopants through said composite layer of SiO₂ and Si₃N₄ on the surface of said epitaxial layer outside said well region to form second doped polysilicon self-aligned contact regions (58) of said second conductivity type; Step 12) Remove said composite layer of SiO₂ and Si₃N₄ and deposit a thin metal film on the surfaces of said epitaxial layer and said polysilicon contact regions (58, 60) wherein metal silicide (61) is formed over exposed polysilicon areas under a heat treatment; Step 13) The remaining unreacted metal film is oxidized by heating to form a thick metal oxide which acts as an etch stop; Step 14) A thick low pressure CVD silicon oxide layer (38) is blanketed over the surface of said substrate and after suitable lithography steps, an opening is made in said silicon oxide layer and the silicon oxide layer which remains is then used to mask the etch of gate opening areas (19) into said silicide and said polysilicon contact regions (60, 58) by using reactive ion etch steps; Step 15) A silicon nitride layer is deposited over the surface of said substrate and sidewall silicon nitride spacers are formed by reactive ion etching said silicon nitride (36); Step 16) Using said sidewall nitride spacers as a mask, etch first and second shallow trenches (20, 21) using reactive ion etching into said epitaxial layer to form vertical transistor regions wherein the depth of said first and second trenches is sufficient to connect to said first buried source element region (18) and said second buried source element region (16), respectively; Step 17) Grow a thin gate oxide (26) on the vertical walls of said first and second shallow trenches and on the other area wherein, because of the high diffusivity of thin n+ and p+ polysilicon self-aligned contact regions (58, 60), self-aligned drain junctions of said vertical transistors are formed and said thin gate oxide of said first and second shallow trenches acts as the transfer gate oxide of said trench-transistors; Step 18) Fill said shallow trenches with conductive material to form the transfer gate and contact. The method according to claim 12 wherein steps 1, 2 and 3 include more specifically a p-doped monocrystalline silicon film grown epitaxially on p+ doped substrate, a composite layer of pad SiO₂ and Si₃N₄ is formed on said epitaxial layer and after suitable lithography and photoresist steps, an opening is made in said photoresist layer to expose said regions for n-well formation and n-type dopants are implanted through said composite layer of SiO₂ and Si₃N₄ on said substrate to form retrograde n-well regions, said photoresist is removed and a short thermal cycle is used to drive in the n-type dopant into the p- epi layer. The method according to claim 12 or 13 wherein steps 1, 2 and 3 further include a composite layer of SiO₂ and Si₃N₄ formed on said epitaxial layer and after suitable, lithography and photoresist steps, then p-type dopants are implanted through said composite layer of SiO₂ and Si₃N₄ on the surface of said n-well to form a p+ buried junction region and said composite layer of SiO₂ and Si₃N₄ is removed such that said p+ buried junction region is formed as a common p+ source junction of a vertical p-channel (PMOS) trench-transistor, and after suitable lithography and photoresist steps, n-type dopants are implanted through said composite layer of SiO₂ and Si₃N₄ on the surface of outside said n-well region to form a n+ buried junction region and said composite layer of SiO₂ and Si₃N₄ is removed such that n+ buried junction region is formed as a common n+ source junction of a vertical n-channel (NMOS) trench-transistor. The method according to claim 12 wherein in step 7) a composite layer of pad SiO₂ and Si₃N₄ is formed on said epitaxial layer and after suitable lithography and photoresist steps, medium p-type dopants are implanted through said composite layer of SiO₂ and Si₃N₄ on the surface of said n-well to form a first buried p-channel threshold-controlled region (56) and after suitable lithography and photoresist steps, medium n-type dopants are implanted through said composite layer of SiO₂ and Si₃N₄ on the surface of outside said n-well region to form a second buried n-channel threshold-controlled region (54). The method according to claim 12 wherein in steps 8,9 and 10 said composite layer of SiO₂ and Si₃N₄ is removed and a thin lightly doped polysilicon layer is deposited on the surface of said epitaxial layer and a composite layer of pad SiO₂ and Si₃N₄ is formed on said polysilicon layer and after suitable lithography and photoresist steps, p-type dopants are implanted through said composite layer of SiO₂ and Si₃N₄ on the surface of said n-well to form first p+ doped polysilicon self-aligned contact regions (60) and after suitable lithography and photoresist steps, n-type dopants are implanted through said composite layer of SiO₂ and Si₃N₄ on the surface of outside said n-well region to form second n+ doped polysilicon self-aligned contact regions (58).

Inventors: DAVARI BIJAN, HWANG WEI, LU NICKY C, DAVARI, BIJAN, HWANG, WEI, LU, NICKY C.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21