AN IMPROVED OSCILLATOR

Abstract: An oscillator is provided with an internal, high gain hysteresis effect so as to offset the linear regions thereof and avoid spikes upsetting the count of a reference divider controlling the oscillator. The oscillator comprises a pair of emitter coupled transistors (T1, T2). A crystal (10) and a capacitor (11) are connected between the collector of a first transistor (T2) and the base of a second transistor (T1). A third transistor (T3) is connected as a load in the collector of the second transistor.

Description: AN IMPROVED OSCILLATOR This invention relates to oscillators particularly reference oscillators for use in phase locked loops. There is a requirement for oscillators capable of providing a clean, well balanced stable output frequency for use in phase locked loops to control, for example, the frequency of some other local oscillator the output of which is mixed with a received signal in a tuner to provide an appropriate intermediate frequency. Conventionally, a crystal oscillator has been used to provide a reference oscillator due to the inherent stability of the crystal. A simple circuit is shown in Figure 1 in which the crystal 10 and a tuning capacitor 11 are connected between the emitters of a pair of transistors 12, 13 to the respective bases of which an input signal is differentially fed. The output of such a circuit, taken from the collectors of the transistors 12, 13 is shown in Figure 2. The output comprises asymmetric signals and is rich in harmonics. If such a reference oscillator, operating at, for example, 4 MHz, is for use in a television tuner having an intermediate frequency of, for example, 39 MHz and a bandwidth of 6 MHz, the 9th, 10th and 11th harmonic of the output of the reference oscillator may appear on the I.F. signal and cause patterning on the video display. Figure 3 shows a better circuit for a reference oscillator. The circuit provides a linear sinusoidal output. In this form, the crystal 10' is connected between the collector of one transistor T2' of a diffferential pair Tj' __-__ T2' and the base of the transistor T Bond pads 14, 15 permit external components such as the crystal 10' and capacitor 11' to be connected to the circuit. The output of such an oscillator, again taken from the collectors is shown in Figure 4. It is well balanced and has much lower radiation levels but is of low gain at the oscillation frequency. However, present in a digital TV tuner are data signals. These are square wave signals at a frequency of approximately 100 KHz and have very fast rise times giving rise to radiation which appears as spikes on the output of the oscillator. Such spikes 16 and 17 are shown in Figure 4. If the spikes (spikes 16) occur on the linear portions of the output, problems arise in a divider normally provided downstream of the reference oscillator. Spikes 17 have little effect. The spikes 16 cause misdivision, the phase locked loop becomes as table and hence control of the loop by the reference oscillator becomes difficult. It is an object of the present invention to provide an oscillator wherein the aforesaid disadvantages are minimised or obviated. According to the present invention, there is provided a crystal oscillator comprising a pair of differentially arranged transistors to the bases of which an input signal may be differentially applied, a crystal and a capacitor being connectable between the collector of a first of the transistors and the base of a second of the transistors, the oscillator outputs being provided differentially of the collectors of the first and second transistors, and a feedback loop established by an output of one of the transistors serving to drive a further transistor connected as a load in the collector of the other of the transistors. The invention will be described further, by way of example, with reference to Figures 5 and 6 of the accompanying drawings, in which:- Figure 5 is a circuit diagram of an oscillator constructed in accordance with the present invention; and Figure 6 is a graphical representation of the output of the oscillator shown in Figure 5. Referring to Figures 5 and 6, an oscillator in accordance with the present invention comprises a differential pair of NPN transistors Tι t T2 having external components, a crystal 10 and a capacitor 11 (shown in broken lines), coupled via bond pads 14, 15 between the collector of transistor T2 and the base of transistor Tj . An input signal is provided to the bases of transistors Tj and T2. The emitters of the transistors Tj and T2 are coupled to a current source Ii . Load resistors RL are provided in the collector loads of the transistors Tj and T2 as also are transistors T3 and T4 (to be described later). Outputs from the oscillator are taken from the collectors of transistors Tj and T2. The outputs are buffered through respective emitter follower transistors T5 and T6 and applied to the bases of a differential amplifier formed by emitter coupled transistors T7 and Tg. The outputs of the oscillator are taken above serial load resistors R and R2 in each of the collector leads of the transistors Υ- and Tg. Exepting the transistors T3 and T4, the oscillator so far described operates identically to that described in relation to Figure 2 and would suffer similar defects. In accordance with the present invention, the transistors T3 and T 4 are included in the collector leads of the respective transistors T j and T2. Transistor T 4 has its base biased by an applied voltage VREF- Transistor T3 has its base driven by a feedback loop taken from the junction between resistors Rj and R 2 in the collector lead of the output transistor T 7 . The effect of the inclusion of the so-driven transistors T3 and T 4 is to introduce offset and hysteresis into the outputs. As shown in Figure 6 which is a graphical representation of the differential outputs, one output, output A, is substantially identical to the corresponding output shown in Figure 2 although a greater or lesser degree of offset may, if desired be introduced thereto. The other output, output B, that having hysteresis, has its output waveform modified to a greater extent. The modification to the output waveform B caused by the hysteresis is such that it lags slightly behind the unmodified output C (shown dotted) and has a greater amplitude. The increased amplitude is occasioned by a much steeper slope over its linear region as exemplified. The overall effect is that crossovers are displaced towards or at ends of the linear regions so that a spike E on the linear region of one waveform is matched by a corresponding spike F on a non-linear portion of the other waveform and is therefore much less discernable in following stages. In use, it is intended that the oscillator of the present invention should be employed as a reference oscillator forming part of a phase locked loop of a frequency synthesiser. Such an arrangement has utility for example in the tuner stage of a television receiver. The oscillator is usually followed by a reference divider, the output of which is fed to a phase comparator to which is also fed the appropriately divided output of a local oscillator for comparison. Phase errors produce signals which are used to increase or decrease the output frequency of the local oscillator thus forming a phase locked loop. The local oscillator may produce its signal for mixing with a received signal to form an intermediate frequency signal for subsequent processing. The reference oscillator according to the present invention has a greater immunity to spikes and hence to misdivision by the reference divider due to such spikes. Stability of the loop and of the output frequency of the local oscillator is consequently improved. The invention is not confined to the precise details of the foregoing example and variations may be made thereto. For instance, the degree of offset and/or of hysteresis of one output relative to the other may readily be varied by the reference voltage applied to the base of transistor T 4 and by the ratio of the resistances R j and R2 in the collector of transistor T 7 . A feedback loop, to cause the hysteresis may be established from an appropriately loaded collector of the buffer emitter follower transistor Tβ. Whilst the crystal 10 and capacitor 11 have been shown as offchip components, the capacitor 11 at least may be fabricated on chip. The use of NPN transistors throughout facilitates the fabrication of the oscillator on a silicon chip using standard techniques. It will be appreciated that PNP or mixed NPN, PNP transistors may be used in the oscillator of the invention, current sources being replaced by sinks as necessary. Other variations are possible within the scope of the present invention.

Claims: CLAIMS 1. A crystal oscillator comprising a pair of differentially arranged transistors to the bases of which an input signal may be differentially applied, a crystal and a capacitor being connectable between the collector of a first of the transistors and the base of a second of the transistors, the oscillator outputs being provided differentially of the collectors of the first and second transistors, and a feedback loop established by an output of one of the transistors serving to drive a further transistor connected as a load in the collector of the other of the transistors. 2. An oscillator as claimed in claim 1 wherein the oututs are buffered by respective emitter followers and applied differentially to a differential amplifier. 3. An oscillator as claimed in claim 2 comprising a split resistive load in each of the outputs of the differential amplifier from the junction of one of which is taken the drive for the further transistor. 4. A crystal oscillator substantially as hereinbefore described with reference to and as illustrated in Figures 5 and 6 of the accompanying drawings. 5. A television tuner circuit comprising a frequency synthesiser having a local oscillator controlled by a phase locked loop, wherein the phase locked loop includes, as a reference oscillator, a crystal oscillator as claimed in any preceding claim.

Inventors: COWLEY NICHOLAS PAUL, COWLEY, NICHOLAS, PAUL
Applicants: PLESSEY OVERSEAS, PLESSEY OVERSEAS LIMITED
Application year: 1989
Main classification: H03B5
IPC codes: H03B1, H03B5