MEMORY DEVICE

Abstract: A dynamic RAM memory device with DRAM (10) comprises a control unit (22) detecting when memory accesses are required for read, write or refresh. This unit (22) controls a voltage control circuit (26) which provides operating voltage (e.g. +5v) to the DRAM (10) but switches the voltage to a low level (e.g. 0.5v) in intervals between accesses. The low level is such that the current taken by the DRAM (10) is substantially zero.

Description: MEMORY DEVICE This invention relates to a Dynamic RAM (DRAM) memory device and concerns the need for current reduction in such a device. It is necessary to use DRAMs rather than static RAMs in a battery operated portable device for a number of reasons. DRAMs have the advantages that they are cheaper than static RAMs and that they hold more data per device. Cost is a prime consideration and size is a major consideration in a portable device. Therefore DRAMs are a better choice than static RAMs. However DRAMs have the disadvantages that they need to be refreshed and consume more current. Battery life is a major factor and so it is essential to find a method to reduce the current consumption of DRAMs. Dynamic RAMs are semiconductor memory devices that store data by charging up capacitors inside the device. The problem with DRAMs is that this charge on the capacitor gradually leaks away. This means that the data has to be read out of the DRAM at regular intervals and rewritten back into the device to maintain valid data. This reading out and writing back into the memory cells is called "Refresh". The refresh can be accomplished in a number of ways. The simplest method is by normal accesses but unfortunately most software does not access all the memory locations frequently enough, so this method is not satisfactory. The second method is "RAS only Refresh". In this method a RAS pulse is generated as a row address is presented to the address pins of the DRAM. This refreshes all the memory locations in the row pointed at by the row address. The row address is incremented and the next RAS pulse refreshes the next row of data and so on. RAS is the "Row Address Strobe" input to the DRAM. This has to be repeated at regular intervals to maintain valid data. The final and simplest method is to use "CAS before RAS Refresh". This method uses a row address counter inside the chip. A CAS pulse and then an overlapping RAS pulse are issued to the DRAM. CAS is the "Column Address Strobe" input to the DRAM. These two pulses both increment the internal address counter and cause a refresh cycle. This has to be repeated at regular intervals to maintain valid data. The current consumed by a typical DRAM has two components, one static due to bias drains and one due to switching. The current consumed by a typical one Megabit DRAM is up to 60mA for normal operation i.e. accesses taking place, and 50mA for RAS only or CAS before RAS refresh. The standby current for RAS=CAS=Vih is 3mA and the standby current for RAS=CAS=Vcc-0.2v is 1mA. The aim of this invention is to reduce the average of these currents by several orders of magnitude. The invention is defined with particularity in the appended claims. The power consumed by DRAMs can be reduced by a combination of a number of methods; Increase the time between "Refresh Cycles". The device then only consumes the relatively high Refresh Cycle Current for short periods of time at widely spaced intervals. Care has to be taken to make sure that data is not lost due to the leakage of the capacitors that form the memory storage cells if the refresh rate is too slow. Devices can be tested and a safe refresh rate found. Note that the refresh rate is temperature dependant, the hotter the devices, the shorter the time between "refresh cycles" should be. This fact should be taken into account when choosing this time. Decrease the voltage to zero or other suitably low voltage. The low level may be in the range 0 to 1.0 volts, typically 0.5v on the power supply inputs to the DRAM except when there is a Refresh Cycle or an Access Cycle. When there is a Refresh Cycle or an Access Cycle then the voltage is raised to the normal working voltage. When the voltage on the power supply pins to the DRAM is reduced to the low level, the current taken by the DRAM is very low, substantially zero. The voltage is only raised to the normal working voltage of +5v when an access or a refresh is needed. Significant current is only drawn when an access or refresh cycle is in progress and so the average current is reduced. If there are none or very few accesses then this can considerably reduce the power consumed by the DRAM. All the inputs of the DRAMS should be decreased to zero volts immediately after the power supply pin has reached the low level so that current does not leak into the DRAM through the inputs. To ensure correct operation during access or refresh cycles the voltage on the power supply pins to the DRAM must be brought up to +5v before the access or refresh cycle begins and the voltage on the power supply pins to the DRAM must be held at +5v till after the access or refresh cycle has completed. The voltage on the control inputs RAS, CAS, OE, WE (assuming that these are active low) should be brought up from zero to Vcc (+5v) inmediately before the voltage on the power pin is raised, to ensure that the DRAM sees these control lines as inactive when the DRAM powers up to its functional state. The control circuitry has to recognise when an access or refresh is pending and raise the supply voltage a short time before the access or refresh takes place. Once the access or refresh is complete then voltage is reduced to the low level. A further enhancement can be implemented to reduce the potential delay when an access is pending because of the time taken to raise the voltage to the normal working value. This is achieved by only reducing the voltage to the low level after there has been no access for a certain length of time. i.e. a timeout. Therefore if there is one access quickly after another the voltage will already be up at the normal working voltage after the first access and the second access can take place iππediately, and no extra delay will be incured. If there are no accesses for a length of time when the voltage is reduced to the low level and so power is saved. There is a problem with other devices that use cumon lines with the DRAMs. If some of the outputs of these devices are at a logic high and the voltage to the power supply pin to the DRAMs are at zero volts then there can be considerable leakage currents. This can be cured by one of two methods. The outputs of the other devices can be arranged to be low or the DRAMs can be isolated with buffer logic and only connected when active. The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Fig.1 is a block diagram of one esribodiinent of the invention and Fig. 2 shows a portion of Fig. 1 in more detail. Fig. 1 shows a typical ein odiment with conventional DRAM maiory device 10 operatingbetween power supply rails Vcc and Vss = Ov. Vcc is +5v in normal operation. The memory device has address inputs and a data port and a set of conventional control inputs RAS, CAS, WE and (optionally) OE, representing respectively: not row address strobe not column address strobe not write enable not output enable. The address inputs are provided from a system address bus 12 via an address buffer 14 and buffered address bus 16. The data port communicates with the system data bus 18 via a data transceiver 20. The control inputs and control signals for the address buffer 14 and data transceiver 20 are provided by a control and timing unit 22 which is responsive to the system clock C U and signals on system status lines 24, which are primarily taken from pins of the CPU (not shown). As thus far described the system is merely a conventional memory system as embodied in countless personal computers and other CPU-based apparatus. The control and timing unit 22 performs partly conventional functions in dependence upon signals on the system status bus, indicating inter alia when read and write operations are to take place, and controls DRAM refresh. In accordance with the invention it also applies a control signal to a voltage control circuit 26 which switches the Vcc voltage for the DRAM between the low voltage and +5v in the manner indicated above. Fig. 2 shows relevant parts of the circuits 22 and 26 in more detail. In accordance with conventional practice the control and timing unit 22 can be based on a custom gate array which here includes a sub-array 30 detecting when any access to the memory device 10 is called for, whether this access be a read, write or refresh access. The output signal from the sub-array 30 sets a flip-flop 32 to a state indicating "access mode" and also resets a timer 34. This timer can have a delay time of say 15us. When it times out, i.e. when there is no memory access of any kind for 15us, it resets the flip-flop 32 to a state indicating "no-access mode". The flip-flop 32 provides the signal to the voltage control circuit 26, in which +5v is applied to a decoupling capacitor 34 and to a switch formed by complementary FET's 36 and 38 in series with a diode 40. In access mode, the flip-flop 32 turns on the FET 36 and Vcc is pulled up to +5v. In non-access mode the flip-flop 32 turns on the FET 38 and Vcc is pulled down to say 0.5v, determined by the diode 40. The output of the flip-flop 32 is fed back as one of the status input lines 24. The control and timing unit 22 (Fig. 1) uses this status line to switch RAS, CAS, WE, OE low in non-access mode and also to control the address buffer 14 and data transceiver 20 so that the address inputs and data port terminals on the DRAM are low. However the access detect circuit 30 causes RAS, CAS, WE, OE to go high again before Vcc is switched back again to +5v. The switching of Vcc introduces seme current drain due to discharging and recharging of decoupling capacitors connected to the DRAM chips. This can be reduced by grouping refresh cycles in bursts. On the other hand refresh accesses must be carried out with reasonable regularity. It has been found that, if a complete refresh requires 512 refresh accesses (i.e. these are 512 row addresses), grouping the refreshes in bursts of 8 represents a good compromise.

Claims: Claims: 1. A dynamic RAM memory device comprising a control unit (22) detecting when memory accesses are required for read, write or refresh and a voltage control circuit (26) providing operating voltage to the DRAM (10) and so controlled by the control unit (22) as to switch the operating voltage to a low level in which the current taken by the DRAM is substantially zero in intervals between accesses. 2. A dynamic RAM memory device according to claim 1, -wherein the control unit (22) additionally reduces all signal inputs on the DRAM (10) to zero volts when the operating voltage is switched to the low level. 3. A dynamic RAM memory device according to claim 2, wherein the signal inputs include active low control inputs (CAS, RAS, WE, OE) and the control unit (22) switches these inputs high before switching the operating the voltage back from the low level. 4. A dynamic RAM memory device according to claim 1, 2 or 3, wherein refresh accesses are grouped in bursts in intervals during which the operating voltage is maintained at normal operating level and alternating with intervals during which the operating voltage is switched to the low level. 5. A dynamnic RAM memory device according to any of claims 1 to 4, wherein the control unit (22) includes a timer (34) which prevents switching of the operating voltage to the low level until a predetermined time has elapsed without any memory access.

Inventors: SINCLAIR CLIVE MILES, WESTWOOD JAMES, WRIGHT DAVID, SINCLAIR, CLIVE, MILES, WESTWOOD, JAMES, WRIGHT, DAVID
Applicants: CAMBRIDGE COMPUTER, CAMBRIDGE COMPUTER LIMITED
Application year: 1989
Main classification: G11C11
IPC codes: G11C11