Interrupt controller

Abstract: The interrupt controller comprises interrupt level registers (2₀ ... 2 n ) storing interrupt levels corresponding to the interrupt request signals (I₁ ... I n+1 ), respectively, and a priority decision circuit (30) for receiving outputs of the interrupt level registers and selectively outputting the interrupt level signal corresponding to the interrupt request of highest priority.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt controller that lets a microprocessor flexibly process various interrupt requests in the descending order of priorities of the interrupt requests. 2. Description of the Prior Art A microprocessor with an interrupt function generally executes external and internal interrupt requests in the predetermined order of priorities of the interrupt requests. Fig. 1 shows an interrupt controlling system according to a prior art. An interrupt controller 71 outputs an interrupt level signal I to a microprocessor 72 to request the microprocessor to process the interrupt request. If a priority of the interrupt level signal I is lower than an acceptable priority set in an internal register (not shown) of the microprocessor 72, the microprocessor 72 does not process data related to the interrupt level signal I but puts the interrupt request in queue. In this way, once an interrupt level signal corresponding to an interrupt request is outputted from the conventional interrupt controlling system to a microprocessor, this interrupt level signal is queued until the corresponding interrupt request is accepted by the microprocessor. Therefore, if another interrupt request that has a higher priority than that of the queued interrupt request occurs, the latter interrupt request of higher priority cannot be outputted to the microprocessor. Namely, even if the latter interrupt request is accepted by the microprocessor, this interrupt request is forcibly queued because the previously occurred interrupt request has not been accepted by the microprocessor due to -its low priority and queued. SUMMARY OF THE INVENTION To solve such a problem, an object of the present invention is to provide an interrupt controller that lets a microprocessor flexibly execute interrupt requests in the descending order of their priorities in real time. According to the prior art, an interrupt request whose priority is lower than a predetermined priority is not accepted by a microprocessor. According to the present invention there is provided an interrupt controller as set out in claim 1. Namely, an interrupt request of high priority occurring during an unacceptable period of the microprocessor will not be put in queue but flexibly executed by the microprocessor in real time. These and other objects, features and advantages of the present invention will be more apparent from the following description of a preferred embodiment, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing an interrupt controlling system according to a prior art; Fig. 2 is a view showing the principle of an interrupt controller according to the present invention; Fig. 3 is a view showing an interrupt controller according to a first embodiment of the invention; Fig. 4 is a timing chart for explaining operations of the controller of Fig. 3; Fig. 5 is a view showing an interrupt controller according to a second embodiment of the invention; Fig. 6 is a schematic view showing a master interrupt controller shown in Fig. 5; and Fig. 7 is a schematic view showing slave interrupt controllers shown in Fig. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 2 is a view showing the basic principle of an interrupt controller according to the present invention. In the figure, an interrupt controller 11 generates an interrupt level signal I. If the interrupt level signal I is unacceptable by a microprocessor 12, the microprocessor 12 provides the interrupt controller 11 with an interrupt pending signal S to request the interrupt controller 11 to temporarily hold the interrupt request. Fig. 3 is a view showing the details of the interrupt controller 11 of Fig. 2. The interrupt controller 11 comprises interrupt level registers 2 0 to 2 n for holding present interrupt levels corresponding to interrupt request signals I 1 to I n+1 , respectively; a priority decision circuit 30; an interrupt level output updating circuit 40; a gate circuit 50; and an interrupt level output register 60. The interrupt level registers 2 0 to 2 n are activated by the interrupt request signals I 1 to I n+1 to output interrupt levels held in the registers to the priority decision circuit 30. The priority decision circuit 30 decides a level of highest priority among the interrupt levels outputted from the interrupt level registers 2 0 to 2 n and holds the level of highest priority. If no interrupt request is present, the priority decision circuit 30 holds a null value as an interrupt level. When no interrupt pending signal S is outputted from the microprocessor 12 and when no valid interrupt level is set in the interrupt output register 60, the interrupt level output updating circuit 40 outputs a control signal to the gate 50 such that the contents of the priority decision circuit 30 are set in the interrupt level output register 60 through the gate 50. The interrupt output register 60 is designed such that present contents held in the register 60 are nullified when the microprocessor 12 (Fig. 2) outputs the interrupt pending signal S. Operations of the interrupt controller 11 of Fig. 3 will be explained with reference to a timing chart shown in Fig. 4. If an interrupt request signal I 1 is supplied to the interrupt level register 2 0 , the contents of the interrupt level register 2 0 are outputted to the priority decision circuit 30. If there are no other interrupt requests, the priority decision circuit 30 decides that the interrupt level of the interrupt level register 2 0 is the highest priority. Then, an interrupt level signal corresponding to the interrupt request of the register 2 0 is transmitted to the microprocessor 12 through the interrupt level output register 60. While the interrupt level output register 60 is holding the interrupt level of the interrupt level register 2 0 , if another interrupt request signal, for example, I 2 of higher priority than the priority of the interrupt level register 2 1 , the priority decision circuit 30 decides that the contents of the interrupt level register 2 1 shall be outputted as an interrupt level signal. However, the interrupt level output updating circuit 40 does not update the contents of the output register 60, and, therefore, the output register 60 holds the contents of the interrupt level register 2 0 and gives them to the microprocessor 12. If the interrupt level of the interrupt request signal I 1 is not acceptable by the microprocessor 12, the microprocessor 12 does not process the interrupt request. At the same time, the microprocessor 12 sends the interrupt pending signal S to the interrupt controller 11. In the interrupt controller 11, the interrupt pending signal S is given to the interrupt level output updating circuit 40. Then, the circuit 40 provides a control signal to the gate 50 such that the interrupt level signal corresponding to the interrupt request I 2 and outputted from the priority decision circuit 30 is transferred to the interrupt level output register 60 via the gate 50. Therefore, the interrupt level signal corresponding to the interrupt request signal I 2 that has the highest priority at the moment is transferred to the microprocessor 12 from the output register 60. Then, the microprocessor 12 executes the interrupt request. As described in the above, if an interrupt level signal sent by the interrupt level output register 60 has a priority that is lower than an acceptable priority of the microprocessor 12 and thus rejected by the microprocessor 12 and thus rejected by the microprocessor, and, during this period, if the priority decision circuit 30 in the interrupt controller 11 decides that a priority of the following interrupt request is higher than the preceding interrupt request, the interrupt level signal given to the microprocessor and rejected by the microprocessor is nullified and then the following interrupt level signal for the following interrupt request is outputted to the microprocessor 12. Fig. 5 is a view showing an extended interrupt controller according to another embodiment of the invention. In this embodiment, an interrupt controller comprises a master interrupt controller 10 0 and slave interrupt controllers 10 1 to 10 N . The master interrupt controller 10 0 outputs an interrupt level signal to the microprocessor 12. The slave interrupt controllers 10 1 to 10 N output bus interrupt request signals to the master interrupt controller 10 0 via a bus B. Therefore, an interrupt request outputted from any one of the slave interrupt controllers 10 1 to 10 N is outputted to the master interrupt controller 10 0 . Then the master interrupt controller 10 0 outputs the interrupt request to the microprocessor 12. Fig. 6 is a view showing the details of the master interrupt controller 10 0 shown in Fig. 5. The master controller 10 0 comprises interrupt level registers 2 0 ' to 2 n ', a priority decision circuit 30', an interrupt level output updating circuit 40', a gate 50', and an interrupt level output register 60'. The arrangements of the apparatuses shown in Figs. 6 and 3 are identical to each other except that the apparatus of Fig. 6 has the bus B through which bus interrupt request signals are transmitted from the respective slave interrupt controllers 10 1 to 10 N to the priority decision circuit 30'. The bus B consists of the signals which indicate the interrupt requests of each levels. The bus B can transmit the respective interrupt levels independently of each other. With the priority decision circuit 30' of expanded function, the master interrupt controller 10 0 selects one interrupt level of highest priority among the interrupt request signals I 1 to I n-1 provided for the interrupt level registers 2 0 ' to 2 n ' and bus interrupt request signals from the slave interrupt controllers 10 1 to 10 N , and then the master interrupt controller 10 0 outputs the selected one to the microprocessor 12. Fig. 7 shows one of the slave controllers shown in Fig. 5. The slave controller comprises interrupt level registers 2 0 " to 2 n " to which respective interrupt request signals I 1 " to I n-1 " are supplied, and an interrupt level decoder 80. Outputs of the registers 2 0 " to 2 n " are connected to the decoder 80, and an output of the decoder 80 is connected to the bus B through which interrupt request signals are transmitted. Therefore, the contents of the interrupt level registers 2 0 " to 2 n " corresponding to the interrupt request signals I 1 " to I n-1 " are inputted to the level decoder 80, and the decoder 80 outputs interrupt levels corresponding to the interrupt request signals to the master controller 100 via the bus B. As described in the above, according to the present invention, a microprocessor outputs an interrupt pending signal to an interrupt controller if an interrupt level signal given by the interrupt controller is unacceptable by the microprocessor. With the use of the interrupt pending signal, the interrupt controller again outputs an interrupt level signal which is the highest priority at the time to the microprocessor. In this way, an interrupt request of higher priority occurring during the unaccepted period of the interrupt request of lower priority is processible in real time in the microprocessor. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

Claims: An interrupt controller (11) for receiving a plurality of interrupt request signals and outputting an interrupt level signal (I) to a microprocessor (12), comprising: a plurality of interrupt level registers (20, 2n) for receiving the interrupt request signals and outputting signals that indicate relative priorities of the respective interrupt request signals; and a priority decision circuit (30) for receiving output signals of said interrupt level registers and outputting an interrupt level signal corresponding to one output signal of highest priority selected among the output signals; and an interrupt level output register (60) connected to said priority decision circuit for holding and outputting an interrupt level signal corresponding to the output of said priority decision circuit, said interrupt level output register (60) nullifying an interrupt level signal when an interrupt pending signal (S) is received from the microprocessor and holding and outputting anew an interrupt level signal corresponding to a current output of said priority decision circuit. The interrupt controller as claimed in claim 1, further comprising: an interrupt level output updating circuit (40) for receiving the interrupt pending signal from the microprocessor and updating the contents of the interrupt level output register such that the interrupt level output register holds an interrupt level appearing at the moment at the interrupt level signal output of said priority decision circuit. The interrupt controller as claimed in claim 1, wherein the interrupt level output register is connected to said priority decision circuit through a gate circuit (50), and the interrupt level output updating circuit updates the contents of the interrupt level output register by controlling the gate circuit. The interrupt controller as claimed in claim 1, further comprising at least one slave interrupt controller interrupt level signal input (B), wherein said priority decision circuit also receives interrupt level signals from the at least one slave interrupt controller interrupt level signal input (100, 101, 10N) and outputs one interrupt level signal of the highest priority selected among the outputs of said interrupt level registers and of the at least one slave interrupt level signal input.

Inventors: MIYAMORI TAKASHI, MIYAMORI, TAKASHI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G06F13
IPC codes: G06F13, G06F9