Image processing method

Abstract: Image processing method comprising the steps of: generating a shifted image by shifting the original image by predetermined distance; comparing corresponding pixels of said original image and said shifted image and counting the number of corresponding pixels which have the same density value, and, changing said predetermined distance to other values and repeating for each value the comparing and counting step in order to calculate a discordance ratio for various distances.

Description: The present invention relates to an image processing method. A density cooccurrence matrix represents the relationship of densities between two pixels in an image which are remote from each other by predetermined distance. The distance is usually defined as δ(x,y) (coordinate difference x in x direction and coordinate difference y in y direction). Each element in the density cooccurrence matrix represents the number of couples of certain densities. For example, the value of the d 1 th column and d 2 th row of the matrix represents the number of couples of densities d 1 and d 2 . matrix is proposed, in which the summation of the number of couples of densities d 1 and d 2 as well as the number of couples of densities of d 2 and d 1 is stored in the same column and the same row. As far as the inventor knows, there has been disclosed no concrete method for generating the density cooccurrence matrix. If all couples of an image are compared in density, N times comparation is necessary for an image of N pixels. When the image size is 512x512, more than 260 thousand comparations are necessary. This means several minutes of computation time when using a 16-bit personal computer for that purpose. Characteristic parameters, contrast, second moment correlation etc. are usually calculated from the density cooccurrence matrix. Cooccurrence matrices are known e.g from "On using cooccurrence matrices to detect periodicities", A. R. FIGUEIRAS-VIDAL, IEEE ACOUSTICS, SPEECH AND SIGNAL PROCESSING MAGAZINE, Vol ASSP-35, No. 1, January 1987. It is the object of the present invention to provide an image processing method for generating a density co-occurrence matrix with a reduced computational effort. This object is solved by the image processing method of claim 1. In the following a preferred embodiment of the present invention is described referring to the accompanying drawings. Fig. 1 is a block diagram of a circuit used for a first embodiment of the present invention; Fig. 2(a) to (d) show images to be processed; Fig. 3 shows a block diagram of a circuit used for a second embodiment of the present invention; Fig. 4 shows a block diagram of a first embodiment of a counter portion; Fig. 5 shows a second embodiment of the counter portion; Fig. 6 and 7 show timing charts of the second embodiment; Fig. 8 shows a block diagram of a third embodiment of the counter portion; and Fig. 9 shows a timing chart of the third embodiment. Fig. 1 shows a circuit used for the first embodiment of the present invention. In the circuit, two or more frame memories 1 and 2 are connected through a multi-plexer 3 to a comparator 4 and counter portion 5, successively. An output of the multi-plexer 3 is fed back to the frame memories 1 and 2. In the memory 1, an original image to be processed is stored. The original image is represented by Fig. 2(a). When the distance of density cooccurrence matrix is δ(x,y), the original image is shifted by x in x direction and by y in the y direction and stored in the frame memory 2. In Fig. 2, positive x direction is rightward direction and positive y direction is downward. For shifting an image, reading timing from the frame memory 1 and writing timing to the frame memory 2 are shifted. Also any other methods can be applied. The density of each pixel in the original image is successively transmitted to the comparator 4. The density of each pixel in the shifted image is successively transmitted to the counter portion 5, synchronously with the transmission of the density of the original image. In the comparator 4, a density d 0 to be processed is registered. The comparator 4 outputs a signal F only when the density of the pixels in the original image coincides with d 0 . F is called "objective pixel flag" hereinafter. The counter 5 has an address input A and data input D/I. Data stored in a address designated by an address input A is increased by a value inputted from D/I. The objective pixel flag F has a value of "1", which is inputted to D/I of the counter portion 5. It means that the counter 5 counts input times of each density from the shifted image. Therefore, density couples of d 0 and each of all densities are counted. It corresponds to the generation one column or one row of the density concurrent matrix. By changing d 0 to each of all densities, all elements of density cooccurrence matrix can be calculated. Usually the density cooccurrence matrix is generated according to an image diminished in graduation from an original image. In this case, d 0 is changed 15 times. For a process of one column or one row, total data of the frame memories 1 and 2 are inputted one time to the comparator 4 and counter portion 5, respectively. This can be called one scan processing. In 16 graduation image, total processing is performed in 16 scanning time. There are frame memoryies available which read and write 512x512 pixels in 1/60sec.; 0.016sec. From a density cooccurrence matrix, the following characteristics parameters are calculated. Contrast x1(δ): x1(δ)= m n (m-n) 2 Pδ(m,n) Second moment x2(δ): x2(δ)= m n Pδ(m,n) 2 Correlation x3(δ): x3(δ)={ m n mnPδ(m,n)-µmµn}/(δmδn) µm= m m n Pδ(m,n) ........ Mean value of peripheral distribution in m direction; µn= n n m Pδ(m,n) ........ Mean value of peripheral distribution in n direction; σ 2 m= m (m-µn) 2 n Pδ(m,n) ........ Variance of peripheral distribution in m direction; σ 2 n= n (n-µn) 2 m Pδ(m,n) ........ Variance of peripheral distribution in n direction; It will be easily understood from the above formula, that the calculations above are very complex. For evaluating a density cooccurrence matrix without executing complex calculation, a characteristics parameter is invented by the present inventor. For calculating the new parameter, a shifted image is generated, similar to the above processing, by a distance δ(x,y). Fig. 3 shows a circuit for the calculation. The circuit is similar to that in Fig. 1, but is different in that both data from the frame memories 1 and 2 are parallelly inputted to the comparator 4, to be compared. The comparator 4 outputs a comparison signal C. The signal C is "0" when both data coincide with each other, and is "1" when both data are different from each other. The comparison signal C is inputted to the data input D/I of the counter 5 which counts the value of the signal C. A constant value, for example "0", is inputted to the address input A of the counter 5, so the total counted value is stored in one address. The original image in Fig. 2(c) has rough checked pattern with horizontal pitch D2 and vertical pitch D1. On comparing the original image with the shifted image, the discordance ratio of both images has local minimum or becomes "0" when the shifting distance in x direction is a multiple of D2 and/or the shifting distance in y direction is a multiple of D1. In Fig. 2(d), a fine checked image is shown with the pitch of d1 in y direction and d2 in x direction. On comparing the image in Fig. 2(d) with the shifted image thereof, the discordance ratio becomes "0" or local minimum when the shifting distance in x direction is a multiple of d2 and/or the shifting distance in y direction is a multiple of d1. As will be understood from the description above, the period of discordance ratio represents a texture characteristics. This period is independent from the density itself, rather represents the roughness or fineness of the texture. It means that human impression of a texture is quantitatively evaluated. Since the evaluation is performed by more simple calculation than the conventional parameters, the texture analysis is more easily executed. Fig. 4 shows an example of the counter portion 5 in the above circuit. The counter portion 5 consists of a high speed memory 8 and a light computational portion 9 which is connected to the data output Dout of the high speed memory 8. The high speed memory 8 consists of for example a static RAM (random access memory). The output of the light computational portion 9 is fed back through a selector 10 to the data input D/I of the high speed memory 8. The address input A of the counter 5 is connected to the address input Ain of the high speed memory 8. The data input D/I of the counter 5 is inputted as the data D3 of the light computational portion 9. When the high speed memory 8 is in a read mode, the high speed memory 8 outputs data D stored in address D1 which is designated by the address input A. The data D is inputted to the light computational portion 9. The light computational portion can be defined as various computational modes. For the performance as a counter, the light computational portion 9 is defined as an adder. Therefore, D3 is added to D, then the additional result (D3+D) is outputted from the light computational portion 9. The outputted value is inputted through the selector 10 to the data input Din of the high speed memory 8 and storaged in the address D1. Since D3 is "1", data in a address of the high speed memory 8 is increased by "1" in every process cycle. The counter 5 has the same performances as the above, by inputting constant "1" as D3 as well as inputting signal F or C to chip select terminal or chip enable terminal of the high speed memory 8. Fig. 5 shows the second embodiment of the counter. In Fig. 5, the counter consists of the high speed memory 8, the light computational portion 9 connected to the data output of the high speed memory, and the selector 10 is connected to the data input of the high speed memory 8. The output of the light computational portion 9 is transmitted to the input of the selector 10. A multi-plexer 11 and a latch 12 are successively connected between the high speed memory 8 and the light computational portion 9. The output from the high speed memory 8 is transmitted through the multi-plexer 11 and the latch 12 to the light computational portion 9. A latch 13 is connected between the light computational portion 9 and the selector 10. The output of the light computational portion 9 is transmitted through the ratch 13 to the selector 10. The output of the light computational portion 9 is fed through a feed back line F back to the multi-plexer 11. The multi-plexer11 selects data D1 or the output D3 alternatively to output. A latch 14 is connected to another input of the light computational portion 9. Data D4 to be used for the calculation with the data D1 is once held in the latch 14 then inputted to the light computational portion 9. A multi-plexer 15 is connected to the address input of the high speed memory 8. An address signal A0 is inputted directly or through a latch 16 to the multi-plexer 15. The direct address signal A and the address signal A1 through the latch 16 are inputted to a comparator 17. The comparator 17 compares the signals A and A1 so as to output comparison signal COMP1 representing comparison result. Fig. 6 shows timing chart of the pipeline process of the counter portion 5. Read/write enable signal R/W of the high speed memory 8 is changed periodically so as to make the high speed memory 8 read and write mode periodically. The signal R/W is used as a basical signal of the counter 5. The address signal A0 is repeatedly inputted in every read/write cycle (one read cycle and one write cycle) so as to designate one address in every read/write cycle. The latch 16 outputs the signal A1 which is generated by delaying the signal A1 by one read/write cycle. The multiplexer 15 alternatively outputs the signal A0 and A1 in every half of read/write cycle (one read cycle or one write cycle). The output of the multi-plexer 15 is inputted to the address input of the high speed memory. The high speed memory 8 outputs, from the data output Dout, the data in the address designated by A2. When different addresses are designated in every read/write cycle, as shown by the references from AD1 to AD7 in Fig. 6, outputted data D1 is transmitted through the multiplexer 11 and latch 12 to the light computational portion 9, then the computational result D3 is transmitted through the latch 13 and selector 10 to the high speed memory 8. The result D3 is stored in the same address as the address from where D1 is read out. As shown in Fig. 3, in the read/write cycle following to the read cycle when address AD1 is designated, the address AD1 is designated again in the write cycle. Therefore, the computational result D3 is written in the same address as the address from where D1 is read out. When a constant address is repeatedly designated, the first computational result has not yet be written in the second read cycle, in the process timing in Fig. 6. It means that repeated calculation is performed one time in every 2 read/write cycle. For the repeated calculation, the feed back line F is used for feeding the output of the light computational 8 immediately back to the latch 12. Fig. 7 shows a timing chart for the repeated calculation of the same address. In Fig. 7, address AD1 is designated 2 times continuously and another address AD2 is designated at the third cycle, then the address AD1 is designated again at the fourth cycle. From the fifth cycle, the address AD2 is repeatedly designated. The comparator 17 compares addresses A0 and A1 and generates the signal COMP1 of low level when A0 and A1 coincide with each other. COMP1 is inputted as a control signal to the multi-plexer 11. The multi-plexer 11 passes the data from the feed back line F when COMP1 is low level. The data from the multi-plexer is immediately transmitted through the ratch 12 to the light computational portion 9. The light computational portion outputs the computational result at the next cycle. By the first and second designation of AD1, the data in the address AD1 is calculated in the light computational portion 9, for example increased by "1", then the calculation result is fed through feed back loop back to the light computational portion 9. The light computational portion 9 calculates second calculation of the data from the address AD1 and transmits the second calculation result to the address AD1 in the high speed memory 8. By the first designation of AD2, data in the address AD2 is calculated in the light computational portion 9, and the calculation result is written in the address AD2. At the next designation of AD1 (fourth cycle), data in the address AD1 is calculated once in the light computational portion 9, then the calculation result is written in the address AD1. From the fifth cycle, the feed back line F is used again so that the data in the address AD2 is repeatedly calculated, circulating in the feed back loop. As will be understood from the description above, data in the same address can be repeatedly calculated in every read/write cycle by using the feed back line F. Fig. 8 shows the third embodiment of the counter portion in which a dual port memory or other multi-port memory is used as the high speed memory. The multi-port memory has advantages that reading and writing are simultaneously performed. In this embodiment, portions same as or corresponding to that of the second embodiment are designated by the same references as that of the second embodiment. In Fig. 8, the multi-plexer 11 connected to the output of the high speed memory has three inputs. The output of the latch 13 is fed through a feed back line F' back to the multi-plexer 11. The multi-plexer 11 selects one of output D1 from memory, output from the light computational portion 8 and the output from the latch 13, alternatively. Data A0 is directly inputted to the read address input RAin of the memory 8. Data A0 is inputted through latches 18 and 19 successively to the write address input WAin. The signal for WAin is a delayed signal of A0 by two read/write cycle. This delayed signal is called A2 hereinafter. The output of the latch 18 is a delayed signal of A0 by one read/write cycle, which delayed signal is called A1 hereinafer. Signal A0 and A1 are compared in a comparator 20 and signals A0 and A2 are compared in a comparator 21. The comparator 20 and 21 output comparison signals COMP1 and COMP2, respectively. COMP1 and COMP2 are inputted as control signal to the multi-plexer 11. COMP1 becomes low level ("0") when A0 and A1 coincide with each other, otherwise high level ("1"). COMP2 becomes low level ("0") when A0 and A2 coincide with each other, otherwise high level ("1"). In this case, multi-plexer 11 selects data according to COMP1 and COMP2 as shown in Table 1. COMP1 COMP2 Output from multi-plexer 11 0 0 Data from feed back line F 0 1 Same as the above 1 0 Data from feed back line F' 1 1 Data D1 Fig. 9 shows a timing chart of the third embodiment of the counter portion. In Fig. 9, address AD1 is designated in first three cycles, address AD2 is designated in the fourth cycle, address AD1 is designated again in the fifth cycle, address AD3 and AD4 are designated in the sixth and seventh cycle successively. Hereafter, data in address ADi is designated by a reference D(ADi). The calculation result of j times calculation is designated by a reference Dj(ADi). When the second designation of AD1 after the first D(AD1) is held in the ratch 12, COMP1 becomes low level. The calculation result of light computational portion 9 is fed through the feed back line F back to the multi-plexer 11. The calculation result of three times calculation D3(AD1) is outputted from the latch 13. When another address AD2 is designated, COMP1 becomes high level and COMP2 becomes low level. It causes the selection of data from the feed back line F'. As soon as the data D1(AD2) is held in the latch 13, D3(AD1) is fed to the latch 12 and held therein. In the next cycle, D1(AD2) is written in the address AD2, simultaneously D3(AD1) is inputted again to the light computational portion 9. In this embodiment, since the high speed memory has performance of simultaneous reading and writing, basical cycle is half of that of the first embodiment. In the critical timing of repeated designation of the same address, repeated calculation can be executed, as well. When the light computational portion has performances of MAX, MIN and other calculations, maximum extraction, minimum extraction and various calculation can be executed. Since the light computational portion performs in one cycle rather light calculation, the light computational portion can be very fast in processing. Processing in video rate can be easily performed.

Claims: Image processing method comprising the steps of: generating a shifted image by shifting the original image by a predetermined distance; comparing corresponding pixels of said original image and said shifted image and counting the number of corresponding pixels which have a different density value, the total counted value forming a discordance ratio for said predetermined distance, and changing said predetermined distance to other values and repeating for each value the comparing and counting step in order to calculate a discordance ratio for various distances.

Inventors: KUMAGAI RYOHEI, KUMAGAI, RYOHEI
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1989
Main classification: G06T7
IPC codes: G06T7