CORRECTION OF LONG TERM DRIFT AND SHORT TERM FLUCTUATING CORRUPTION OF A SIGNAL

Abstract: An arrangement to remove drift and wow and flutter in a tape recording comprising recording a control signal tone derived from a reference clock (159) in a dedicated control channel or embedded in a signal channel. The control signal on playback (151) is compared to the reference signal in an up/down counter (172) and the difference is used to correct the speed of the tape drive. The drift corrected control tone signal is connected through a programmable RAM delay (154) and a latch (179) to a D/A converter (156). The delayed analogue control signal and the reference signal are limited then connected to phase comparator counter (158) which is triggered by the leading edge of the reference signal and read by the leading edge of the squared control signal to measure the time delay between them as a number of RAM (154) samples (N) and subsamples (n). The measured time delay is used to advance or retard the Read address (155) relative to the Write address in the RAM delay (154) where unit change in the tap address (N) is equal to 20 mu sec in the example. The remaining time delay (0-19 mu sec is connected to a phase delay circuit (178) effective to delay readout from the RAM via the latch (179) in one microsecond intervals in the example.

Description: Correction of Long Tern Drift and Short Ten;, Fluctuating Corru p tion of a Signal The invention relates to signal processing ana inparticular, though not exclusively, to the correction of drift and wow and flutter in signals that have been recorded. When a signal is transmitted through a medium, there may be fluctuating and drift time delays imposed on the signal due to changes in the propagating medium. Such a mediummay have an analogue in a tape recording system where a signal is subjected to delays during recording and playback. Unen making recordings of signals it is impossible to maintain a perfectly constant tape speed because of limitations imposed by mechanical ano environmental conditions. Therewill thereforebe short termvariations (wow and flutter) and also long term variations (drift) in the recorc-eα, and subsequently, played oack signals. Tne short term variations appear as a recognisable frequency modulation on the recorded signals. The maximum deviation of this change in frequency will depend upon the mechanical precisionof the recording systemaswill the frequencyofl-vodulation (rateof variation) . Variation frequencies up to lOIIz are normally referred to as •wow* whilst thoseabovelOIIz arecalled 'flutter 1 . Very slowvariations and steady state errors (long term average speed errors) are called 'drift 1 . These speed induced drift errors are responsible for creating timing inaccuracies during playback and from recording to recording etc. Drift is likewise caused by the limited precision of the mechanical drive but it is also dependent upon the elasticityproperties ofthe tape, tapetensions, the surface properties of the tape, the ambient temperature, air humidity and upon any variations in mains supply. Wow, flutter and drift performances can often be held within acceptable limitswithout resorting to sophisticatedsystems sincethehuman ear isunable todetectsomeshorttermfrequencyvariations (wowandflutter) with the same level of perception over the entire audio frequency range. Thus it ispossible tominimise the apparentwcwand flutter by ensuring that the predominant frequency of variation is not close to 4Hz, the frequency of maximum perception. Men used for recording and playback of data, however, moαern electronic systems canbesusceptible toverysmall frequency, phaseandtime discrepancies. Thus, when recordings are made of particular 'time synchronous' and phasemodulated signals, these signalswill becorruptedby the relatively very much larger phase distortions produced by the wcw and flutter, and the drift will cause time slip and frequency shifting in the playback signal. Tneobject of the invention is toprovidemeans to reduceor overcome short-term and drift time delays experienced by a signal transmitted via a medium such as a recording medium. The invention provides in one form a signal correction system comprising: transmission means to transmit a control reference tone; and receiving means to receive the signal and the reference tone, an including: a) local oscillator means to produce an identical tone to the transmitted control reference tone; b) comparator means to compare the frequency of the mean control tone with the local oscillator tone; c) drift correction means connected to the frequency comparator means to apply a coinron frequency shift to the received signal and the reference tone to reduce to zero thedifference output froi the frequencycomparator; d) a phase coπgparator circuit to compare the phase of the drift- corrected reference tone with the phase of the local oscillator tone; and e) short term fluctuation correction means connected to the phase comparator circuit to apply to the received signal and the drift-corrected reference tone a common phase/time delay to reduce to zero the difference output from the phase comparator. In an alternative form the invention provides a signal correctior system comprising: transmission means to transmit a control reference tone; and receiving means to receive the signal and the reference tone, and including: a) local oscillator means to produce an identical tone to the transmitted control reference tone; b) comparator means to compare the frequency of the mean control tone with the local oscillator tone; c) correction means connected to the frequency comparator means to apply a frequency shift to the local oscillator means to reduce to zero the difference output from the frequency comparator; d) aphase comparator circuit to comparethephaseof the referencetone with the phase of the corrected local oscillator tone; and e) short terra fluctuation correction means connected to tne phase comparator circuit to apply to the received signal and the reference tone a coπuonphase/timedelaytoreducetozerothedifferenceoutput fromthephase comparator. In onearrangement the frequency comparatormeanscomprises acyclic binary counter having an output clocked by a signal derived from the local oscillator. Conveniently the cycling of thebinarycounter isdeterminedby a detector connected to the counter and responsive to apredeterminedbinary number ( tip) to provide a reset signal to the counter. Preferably the local oscillator-derived clock signal is produced by connecting the local oscillator signal to the input of a divide-by-Kp/n, where n is an integer. Conveniently the output from the binary counter is clocked into an output latch circuit and thelatchoutput is connected to aD/Aconverter toproduce an analogue signal representative of the frequency time/drift between the received reference tone and the local oscillator tone. Preferably the received reference tone is bandpass filtered and limited to minimise the effects of fading anddropouts. The drift representativeD/Aoutputsamples may be connected to an active voltage integrator circuit comprising a transconductor and a capacitor. Preferably the drift-corrected reference tone is connected via a fast programmable delay circuit to the phase comparator circuit and in the above arrangements the short term fluctuation correction means preferably comprises theprogrammable delay circuit andavoltagecontrolledoscillator (VCO), the arrangement being such that the voltage output from the phase comparator isconnectedtothe inputof theVCOand theVCOoutput isconnected to tiiedelaycircuit suchthatthephasecomparator error output isminimised. Advantageously limiters are provided in the circuit connections to the inputs of the phase comparator. Preferably the output signal from the VCOis connectedtoaseconddelaycircuit, identical tothe first: thedrift corrected received signal being connected to the input to the second delay circuit and the αrift and short term fluctuation corrected signal being providedattheoutputthereof. Lowpass filtersmaybeprovidedatthe input and output of the second delay circuit. Each delaymay be a digital delay. More than one phase comparator stages of short term fluctuation correction may be provided. In aparticulararrangement a6dB/octavelowpass filter isconnected between the pαase comparator ana tneVCOwnereoythe loop gain of thewow and flutter correction circuit decreases inversely in proportion to tne modulation frequency. This has been used to obtain innerent stability within theclosed loop of an analogue circuit. Adigital iϊ l ent tionr-ey incorporate more advanced teάiniques to allow a higner gain ana greater banαwidth to be useful. Inaparticulararrangement of the invention for reductionofαrift, wow and flutter in a tape recorder a single stable reference oscillator is provided and arranged for connection to the tape recorder such that on recorα a control reference tone is connected toat leastonetaperecorder inputwith the frequency comparator and phase comparator circuits disableα ana on playback the recorded signals to be corrected, together with the recorded reference tone, are connected to the signal correction system. The reference signal maybe provided as a reference embedded ineach input channel of a multi-channel recorder or as a reference in a dedicated reference channel. When applied to a tape recorder, the drift correctionmeans includes a signal connected from the output of the frequency comparator to the tape capstanmotordrivetovarythedrivespeec. Inoneexamplealightdependent resistor may be used to correctly interface witn the recorder. In an alternative arrangement the frequency comparator means comprises an up/ own counter, the received control tone and the local reference tone being connected to respective count down and count up inputs and the output difference signal being connected to a means effective to reduce the to zero the frequency difference between the control tone and the reference tone. The phase time delay for correcting the remaining phase differences between the control and reference tone may advantageously be applied by a digital time delaycircuit comprising in series aprogrammableRAMdelayanoa RAMlatch, and a phase adjusterfor thelatch, the arrangementbeing suchthat digital signal samples are clocked in to theWrite address of theRAMdelayat frequency F and are read out from a programmable Read address to the latch to provide a time delay having incremental value l\,T of 1/F, the clock signal to the RAM latch being delayed by a digitised time having an incremental value /\t in the range 0 to 1/F, to thereoy provide an overall time delay to an accuracy of .At. Advantageously the phase comparator comprises limiter means to square the control signal and the replica reference signal and a counter clocked by the reference signal and read by the squared control signal. Preferably the counter clock frequency is n times the RAH clock frequency F and the phase comparator measures thephasedifference inunits (N) of1/Fand (R) of 1/nF. Conveniently tnere is provided means whereby the digitised phase difference K + R, which may be positive or negative, is modified by conditional change of U such that R always represents a delayed phase difference. Conveniently also, the Read address for the RAM is stored in a Read latch connected to an adder such that it can be adjusted by themodified N. R is then used to set the delay for the RAM latch. The invention will now be described by way of example only with reference to the accompanying Drawings of which: Figure 1 shows a block diagram of an example of the invention applied to the correction of a tape recorder drift, wow and flutter; Figures 2a and 2b illustrate the signal formats for correction of a single wideband channel and for dual 3kHz channels; Figure 3 shows a block diagram of the Figure 1 arrangei-ent applied to a dual 3kHz channel recording system; Figure 4a is a block diagram of a standard frequency measurement circuit; Figure 4b shows a modification of Figure 4a used for drift correction in Figures 1 and 3; Figure 5 is a block diagram of a drift compensation circuit adopting the Figure 4b frequency counter; Figure 6 is a more detailed block diagram of the Figure 5 circuit; Figures 7 and 8 illustrate ablock diagramand detector responsefor awowand flutter circuit; Figure 9 is a block diagram of a wow and flutter correction circuit incorporating the Figure 7 circuit; Figure 10 is a modified Figure 9 circuit using cascaded feedback phase detection circuits; Figure 11 is a grapn showing the predicted wcw and flutter reduction performances for the Figure 9 and 10 arrangements; Figures 12 and 13 are block diagrams of digital delays for use in thewo;; and flutter correction circuits; Figure 14 is a schematic block diagram of an alternative form of the inventionJ Figure 15 is a schematic representation of a digital circuit arrangement of the drift, wow and flutter correction circuit applied to a tape recorder; Figure 16 is a diagram to illustrate the operation of the Figure 15 phase difference measurement circuit; and Figure 17 is a more detailed version of Figure 15 showing the tape recorder speed control and the tape signal correction circuitry. Figure 1 shows a two-channel tape recorder 10 having L and R. inputs 11,12, L andRoutputs 13,14 and a tape drive speedcontrol input15. In this arrangement an input signal to be recorded is connected to the R input12 and simultaneously a stable 5kEs reference signal Rg f r0 π-an oscillator 16 in a drift, wow and flutter correction circuit 17 is connected to the L input 11. On playback, the recorded reference signal T c and input signal S ε are connected to inputs 18,19 to thecorrection system17. Aswill be described in greater detail, the recorded reference signal is compared (110) with the signal from the output 111 of the oscillator 16 to provide: a) an output signal for connection to the speed control input 15 to the tape recorder tochange the tapedrive speed tocorrect theeffect ofcrift in tne outaut channels; and b) a signal for correcting residual frequency fluctuations in the output channels. The corrected output signal S' s is thenprovidedat tne signal output 112 of the correction circuit 17. During a recording the correction circuit 17 is only used to provide the stable 5kHz reference control tone ; the tape speed drift control and the wow and flutter correction circuitry being disabled. Figure 2a illustrates the spectra of recorded signals on the tracks of a 2-track tape recorder. On onetrack the5kHz control tone20 is recorded at a frequency positioned within the bandwidth of the recorded signal S(F) , 21. Also shown in Figure 2a is the response 22 of a 51cKz band pass filter which would generallybe used at the playback output to improve the signal to noise in the control tone channel. The advantage of the Figure 2a arrangement using a αec-icatec reference tone channel or track is that the input signal being recorded can have a frequency response which overlaps the control tone frequency. On the other hand one track must be exclusively assigned for the control tone. A further disadvantage is tiiat phase-shifting errors can exist oetween any two (ormore) recorded tracks. This problem occurs because the tape will *skew' as it passes over the record and playback heaαs. This is generally accepted as an insignificant factor during a recording (anc playback) but it can no;; become the dominant limiting factor if a correction system is employe. (particularly if a cascaded technique is used to reduce wow and flutter tc verysmall levels) . This isbecausethesystemisunasle tocorrect thephase skew errors produced between the control tone track and the signal tracks. Unfortunately, these interchannel phase errors can be much greater than the residual errors after correction. Figure 2b illustrates the frequency spectra in an alternative 2- channel recording systemwith each channel having a signalbandwidthof 3kHz. The right and left recorded signal spectra are indicated by reference numerals 23 and 24, and these are filtered by 3kHz low pass filters 25,2G respectivelybeforeprocessingbya correctioncircuit. In this arrange-rent a control tone 27,28 of 5kHz, ie above the upper frequency limit, is recordec on each channel togetherwith the twochannel signals. Eachchannel canthen be processed separately to correct for drift, wow and flutter. Ultimately, interchannel phase errors will depend onthequality of the tape recorder beingused andtheireffectwilldependupon thedesiredwow and flutter figures to be achieved. If the requiredwowand flutter figures cannotbe achieved using adedicatedcontrol tonechannel it maybenecessary to use an embedded control tone in every recording channel as in Figure 2b. Unfortunately, this can only be achieved with greater electronic complexity andprovided (at all times) that the recorded signal frequencieswillbeless than thecontroltone. Thefrequencyof thecontrol tone should ideallybeas high as possible because higher frequencies have a greater change in deviation frequency impressed upon themdue to drift, wow and flutter. This makes it much easier to detect the highest rates of change (flutter) and reduces the risk of instability in the correction systembecause loop gains can be minimised. If the control tone can have a higher frequency than the signals tobe recorded then the detectioncircuitswill operatewithahigher resolution than the signals it must correct because it will have higner frequency deviations. This optimises the correction process. Tnere may however be special exceptions to this if the signals to be recordednave gaps within their spectra which can be used to place the control tone. Unfortunately it is not possible to use tne maximu frequency (tnat can normally be recorded as a signal) for the control tonebecause 'dropout' and fading has a much greater effect at these frequencies. For this reason the control tone frequency will depend on the performance of the tape recorder beingused. Anycompletedropouts, or deepfades, inthe control tone signal will have a serious effect on the operation of the correction systembecause itwill produce instantaneous phase anddriftdiscontinuities. Fortunately it ishowever possible to compensate forveryshortor rapiddrop-outs andall but thedeepest fades byusing electronic filtering. Thiswill bedescribed later. A modified version of the Figure 1 arrangement adapted for two channel recording as illustrated inFigure 2a is sham inFigure3. Signals to be recorded are connected to inputs 31,32 of the correction circuit 33 where they are first filtered by 3kHz low band pass filters 34,35 and then mixed (36,37) with the 5kHz reference tone from the oscillator 15. Signals from the mixers 36,37 at outputs 30.-3S of the correction circuit 33 are connected to the respective record inputs 12,11 of the tape recorder 10. The tape recorder playback outputs 14,13 are connected to inputs 310,311 of the correction circuit 33. The 5kHz reference tones from the two channels are selected by band pass filters 312,313 and are then connected to inputs to respective flutter correction circuits 314,315. One reference tone (316) is also connected to a drift correction circuit 317 together with the 5kHz output (120) from the oscillator 16 to provide a tape speed correction signal at output 318 of the correction circuit 33 for connection to the tape recorder motor speed control input 15. The 5kHz output (120) from the oscillator 16 is also connected to respective inputs 319,320 of the flutter correction circuits 314,315 wherephase comparison is made with the 5kHz output control signals. Thetwochannel outputs14,13 are also connected directly to the respective inputs 321,322 of the flutter correction circuits 314,315. Afterphase correction the output signals are filtered by 3kHz low pass filters 323,324 and then connected to respective right and left channel outputs of the correction circuit 33. The above arrangement applied to multi-channel recording enables reduction of drift, wow and flutter in even unmeasureable levels. In addition, interchannel 'skew 1 phase errors are automatically removed. Sound recordings maoe with this type of system will therefore reproduce exactly the spatial content of the original sound. Figures4-6 will nowbe referred to for amorecomplete descriptionof the drift correction. The drift correction circuit 317 (Figure 3) determines drift bymeasuring the frequency of a control tone present in one or more playback channels. This measurement is made against a stable frequency reference. Figure 4a shows a standard technique for frequency measurement. The control reference tone (316) after limiting (410) is used to step a binary counter 411 by one count for eachcycle of the input control tone. Every second a 1Hz signal (412) causes the binary count to be transferred to an output data latch store 413 and the binary count is then resetandanewcount started. Thusfrequencymeasurementsareupdated every second with a resolution of 1 in 5000 for a control tone of 5kHz, i.e. an accuracyof± 0.01%. If ahigher resolution is required thecountperiodmust be increased but the error of ± 0.5 cycle will remain the same. For drift measurement it isdesirable tohave infinite resolution, zero error and avery shortmeasurementperiod. Tneseare conflicting requirementswhenusing the existing Figure 4a arrangement. Figure 4b shows a frequency measuring circuitwhichovercomes thisprobia.;. Thecontrol tone (316) is connected to acyclicbinarycounter414whichcounts theinputsignal cycleswithoutbeing- reset. The count is latched to adatalatch415 atamuchhigherclock rateof 50Hz (414) . Thelatchclockingfrequencyandthebinarycyclecountmustbea harmonic ratio of the control tone frequency (5kHz) . Thus where the counter 414 is Divide-by-100 as shewn, thelatchclockfrequency (416) ustbe50Hzor a multiple thereof. The output (417) from the data latch 415 will then automatically provide the frequency difference count between the control tone (316) and thestable referencesource (16) used toproduce the50Kzclock pulses (416) . The resolution is infinite and the counter error is zero and the update rate (50Hz) is very high. Figure 5 illustrates a use of theFigure 4b cyclicfrequency counter in a drift correction circuit 317. Filters (F) oεtween the tape recorder output 13 and the input (316) to the cyclic counter 414 are not shown for convenience. Tne 50Iiz clock pulses for thedatalatch 415 areproduced fro-:. the stable 5klϊz reference 16 bymeans of a divide-by-onehundred circuit 50. The50Hz signals representing the accumulatingbinaryfrequencyerrors (417) at the output of the data latch 415 is converted by a digital-to-analogue converter 51 and an adjustable amplifier 52 into a control voltage signal 53 for connection to a speed control input 15 of the tape capstanmotor 54. The arrangement provides a negative feedback speed control loop such that if the speed ofthe capstanmotor54, andhence thetape 55, is faster than it snoulα be, the control tone frequency (316) from the playback amplifier 56 will increase (i.e.5kHz+ f, wheref isthe frequency increase) . Thisincrease in frequency produces an increasing error count in the cyclic count circuit output 417 and thus a larger output from the D\A converter 51. After appropriate amplification (52) and 'sense' inversion this output is used to reduce the speed of themotor 54. Conversely, if the speed of themotor54 is lowerthan it shouldbethecontrol tonefrequencywilldecrease (5kHz- f) and the feedback loop will then increase the speed until it is correct again. Thus the tape speed is continuously adjusted to maintain a zero frequency difference and a minimised count error between the reference source and the control tone, irrespective of the playback period. This means that there will be no time drift from the start of the recording to the end, relative to absolute time. The maximum time shift error, after initial stabilisation, will normally be less than ± 0.5Hz, i.e. 0.0001 sees for any lengtii of recording. This time error will be reduced to averymuch smaller value by the wow and flutter correction (314, 315) to be described in greater detail. Figure 6 shows the Figure 5 drift correction circuit in greater detail. Tiie control tone (13) from the tape recorder playback output is bandpass filtered (60) to improvethe signal tonoise ratio, thenlimited (61) to remove any amplitude variations and then bandpass filtered to remove harmonics. The output signal S c is then used as input (63) to the drift correction circuit and as input (64) to each wow and flutter correction circuit. Tne function of this filtering and limiting is to remove, as far as possible, fading and dropouts in the control tone signal T c . The input signal (63) to the drift correction circuit is limited oncemore (65) before connection to the oinary counter 414. The cycling of the counter 414 is determined by a detector 66 responsive tobinary100 toproducea reset signal 67 for the counter. Tne 50Hz control tone samples from theD\Aconverter 51 are lav pass filtered (68) and amplified (69) before connection to the feedback loop gain adjustment amplifier 52. The output signal from the amplifier 52 is connected to the input of a light dependent resistor circuit 610, the output of which isconnected to the tapemotor speed control 15 of tne tape recorder. An improvement to the drift correction performance can be obtained if the 1CM pass filter 68 is replaced by a true voltage integrator circuit 611 as also indicated in Figure 6. As sh m the output 612 from the D\A converter 51 is transmitted via a transconαuctor 613/capacitor 614 integrator in place of the resistor 615/capacitor 615 integrator in the low pass filter G . Also sh m inFigure6 a filter 617 is connected to the output of the local oscillator 16 to prσvi e a signal Rg fo use as the recording control signal and for use in the phase correction circuits. Figure 7 shows a simple schematic negative feedback configuration including a phase detector 70 wherein the control tone S c (71) and the reference Rg (72) are compared. The control tone S c (71) passes through a programmable analogue delay device 73 before connection (74) to the phase detector 70. The phase detector output V c (75) has a linear response 80 for phase differences between 0 and 2Iϊ as shorn in Figure 8. V c is amplified (76) and then used tomodulate avoltagecontrolledoscillator (VCO) 77. The VCO 77 provides a clock output signal 78 which varies the signal time delay through the analogue delay device 73. The feedback loop is arranged such that if the instantaneous phase, seen at the detector 70, advances (i.e. an increase in frequency) the VCO 77 frequency is reduced (oy the amplified detector output) and this produces an increased time delay through the analogue delaydevice 73. Conversely reduced frequencies of S c detected by the circuit are increased by the delay device 73. Tne output S c (79) will thus have a reduced frequency deviation (wow and flutter) . The Figure 7 circuit is used as shα-m in Figure 9 to correct the analogue signal output S s (Figure 1) f om the tape recorder. The reference signal Rg (72), and the drift connected control tone Sc (71) delayed by the analogue delaydevice 73 are both limited 90, 91 thenpassed throughdivide- by-two circuits 92,93 before phase difference detection (70). The phase difference signal output 94 is low pass filtered (95) by a 6dB per octave filter before amplification (76) and connection to the VCO (77) . The VCC clock output (96) is connected toasecondprogra rrableanaloguedelaydevice 97, identical to the delay 73 operating on the control tone S c . The second delay97 is placeα in the path of the analogue signal output S s (go) fromthe tape recorder. Before connection to the delay 97 the analogue signal S s is ai-plified (99) and then filteredbya10kHz lavpass filter910. Thewαvand fluttercorrectedoutput S Ξ ~ (911) fromthedelayisfirstfilteredbya101'Iz low pass filter 912 and then amplified (913). An output connection 914 carries the drift, cs. and flutter corrected tone signal S c ' formeasurement ofresidual fluctuationorforcascaded OTandflutter reductionprocessing. Since the circuit shown operates to reduce measured wα-. τ and flutter in the control tone S c , it also reduces wα; and flutter in the analogue recorded signal S s . Since the corrected tone and analogue signals outputs S c » and S≤ ', 914 and911, have the samewowandflutter, nowatagreatlyreducedlevel, the process of w r and flutter reduction can be repeated using the simplified cascaded circuit shown in Figure 10 (with filters, amplifiers and limiters omitted for clarity) . As can readily be seen the reference signal s (72) , thecorrected tonefromthetapeS c « (914) and thecorrectedanaloguerecorded signal S s » (911) areconnected respectively to a second phase detector100, a first delay101 and a seconddelay102. Thephasedetectcr100, delay101and a VCO 103 are arranged in a second feedback loop 104 similar to the first feedback loop 105. The further reduction inwαvandflutterby this circuit results in a double corrected output signal S s " at the output106 oftnedelay 102. At a cost in circuit complexitythedrift, wowand fluttercorrection circuitrymay be made to operate on embedded control signals recorded in each tape recorder, channel. As mentioned earlier, this reduces inter-channel skew effects. It can be sham that the wow and flutter component at the output of a single correction stage will be reduced by a factor: l/(A/f m + i) where A is the loop gain of the circuit and f- i s thewαvand flutter variation frequency. This is because the wcw and flutter feedback loop contains a simple 6dB/ octave filter which decreases tiie loop gain inversely- proportional to the modulation frequency f m . The level of correction will thereforeoe approximately inverselyproportional to thefrequencyof thewo;; and flutter variation. Tne above formula may be applied to a typical measured recorded output where tiie modulation index B = 36, since; B = fc/fi-i, where input frequency variation f c = + 54 and f κ = 1.5Kz. Using a loop gain A of 73, tiie output modulation inαex B', after correction, is given by: B 1 = B (A/f m + 1) = 36 = 0.72 (73 /I.5 + 1) The deviation frequency f c after correction is therefore! l.lllz. For a two stage cascaded correction circuit the overall reduction in ow and flutter is given by: (73 /I.5 + 1)2 In the above example, the output modulation indexwould be 0.015 ana the final output deviation frequency would be ± 0.02Hz. The figures given above have been found to agree with the measured values. Figure11 shows tiie anticipatedperformance ofthecorrection system forsingle (111) and2-stage (112) cascadedconfigurationsovera rangeofwo;/ and fluttervariation frequencies. The reduction figure in Bs is the ratio change between the output modulation index (or frequency deviation) to the input index (or deviation). From the previous example, for a 1.5KZ wα; signal the reduction is aoout 34dB for a singlecorrection system, whilst for 10Hz it is about 18dD. These ratioswould oedoubled for the2-stagecascaαe circuit. Referring again to Figure 9, the 6d£/octave l ; pass filter 95 introduces someundesirablephasedelay/distortionandalimitedloopgainof 73 wasselectedtominimisetheriskofcircuit instability. By implementing the circuit principles shamwith established digital processing techniques a higher loop gain can be achieved without the associated fall off in frequacy. Thesecircuitswouldbemademorestable, morereliable, anowith enhanced performance. In addition the tape motor speec control would De improved Dy digital implementation. Such digital iπplementation will be apparent to those skilled in this art and circuit details are therefore not given. Thedrift, w ;and fluttercorrectionsystemdescribedcanbeusedto dramatically improve the phase, frequency and time keeping (drift) characteristics of any recording process. The accuracy and stability of the correction process depends entirely upon the stability of the referencetone being used during recording and playback. The amount of wrø and flutter correctionwilldependuponthewαvandflutter frequencyofvariation and the loop gainvalue of the system, 'A 1 . Generally, the lαver tiewα;and flutter variation frequency, then the better the correction will be, as sh m in Figure 11. Cascaded systems can be used to provide even better correction characteristicsbut careπustbe taken to ensurethattiiedynamic range isnot reduced by spurious signals produced within tiie analogue delay devices. This however canbe avoiαed if digital techniques are used foranaloguedelay lines. Figures12 and13 showsingleand2-stagedigital delay lines 120, 130 which can replace the analogue delay devices sham in the previous circuits. In both arrangements the audio input signal 121 is sampled at 40kc/s by a16- bit A/D converter 122 and the 16-bit output from the digital delay is reconverted to an analogue audio signal by a D/A converter 123. The single correction stage includes a singledigital 'First inFirst out' (FIFO) delay 120 controlledby adelayclock signal (124) . Tne2-stagecorrectioncircuit includes series connected FIFO delays 131 and 132 controlled by first and second αelay clock signals (133 and 134). This control technique can not onlybeused to upgrade thequalityof existing 'professional' instrument tape recorders but it can also be used to transform the performance of what would normally be unacceptably very poor systems, such as compact (personal) tape recorders. Thishasvery important applicationswhere thecost ofproducing aconsumableminiature, robust, high quality recorder would otherwise be prohibitive. Although specifically designed for recording systems the technique described herein can also have applications in other areas where the signal 'propagating' mediumhas a delaywhich is time variant but which is otherwise non time dispersive. The invention requires correction of tiie drift before phase corrections can be applied, and in the arrangements described drift is corrected by control of the tape capstan drive motor. This control may be direct or for convenience it could be via a light sensitive resistor circuit as shown, depending upon the tape recorder being used. In some tape recorders drift may not be a serious problem and also it may be desirable to control wow and flutter without controlling thecapstandrivemotor. Figure 14 shα;s a possible alternative arrangement for the invention for these cases. The reference signal at output 140 includes components of drift, w ; and flutter. Instead of correcting this reference signal for drift, tins circuit arrangement imposes a similardrift on the local oscillator reference signal to enable a phase comparator circuit to correct for wα; and flutter. Tne output 140 is connected to a counter circuit 141, as inFigure 6, with an output connected to a D A converter 142 by latch control signals from a diviαe-by-hundre circuit 143. The output from the D/A converter 142, is connected via a low pass filter 144 and amplifier 145 to a control input of a 5kHz referenceoscillator146. Thearrangement is suchthatthefrequencyof the oscillator output 147 is locked to the mean frequency of the reference signal at the output 140 of the tape recorder. In similar manner to the previous examples this local reference signal output 147 and the recorded referenceoutput 140 are connected toaphasecomparatorcircuit148 bymeans of which (149, 1410) a delay element in tiie signal output 1411 from tiie tape recorder is a ustedtocompensateforwα;andfluttervariations. Asbefore this approach may be applied to embeαdec recorded reference signals and cascaded phase correction circuits may be used. In tie arrangements thus far described, the output from the tape- recorder has random phase variations superimposed on the signal after correction by the tape speed controller. Correct operation of tiie phase error correctioncircuitsdescribedrequiresthat tiiephasevariations at tiie input to tne delay lines used are unco related with tiie output. This is ensured bymaking the delay long enough. The circuitswork by comparing the phase of the delayoutputwiththephaseofa referencesignal. If theoutput phaselags then tneclockingrateoftiedelayisspeededup forcorrectionana visaversa. At tiie input, hαvever, the effect of speedingup tie clock rate of the delay is to increase the rate of sampling of the signal from the tape- recorder and thus to slow d m the sar.pled signal in tie delay. As these sampleswork through to the output of the delaya further speedingupofclock rate occurs. If the length of the delay is long enough such that input and output are uncorrelated then this phenomenon is not harmful, however, where thereiscorrelationtherecouldbeanuncontrolled rise intheclock rate. A further disadvantage of the described arrangements arises from the use of a low pass filter in converting the output from the phase comparator to a voltage signal forvarying the frequency of avoltage controlled oscillator. This arrangement does not work quickly and so the correction falls with increasing frequency. A modification of the tape recorder circuits, witn tape speed corrected for the sake of clarity, is illustrated in Figures 15 and 16 using digital ciruitry. The speed control and detailed circuit arrangement are shown in Figure 17. A control signal 151 from the tape-recorder 152 is digititally sampled by an analogue to digital converter 153. Tne output of the A/D converter 153 is connected to a variable delay shift register 154 implemented in random access -l-emory (RAID . Control signal samples are read out by a prograisπable tap connection155 sh m centrallypositionedalong the delay 154, tiie tap position therefore determining tiie sample delay. Tiie digital samples are then connected via an output signal latch 179τ_ to a digital to analogue converter (D/A) 156, filtered (157), then connected to one input of a comparator circuit158. Aclock reference signal 159, having the same frequency as tiie recorded control signal, is connected to a second input of the comparator 158. Tne comparator measures the time differences between successive cycles of reference and control signals. These time differences are added to the read address (155) to the delay 154. By tnis means tiie read position of the delay RAM is advanced or retarded with respect to tie write address depending on whether tiie time difference is positive or negative and the delay is varied to reduce tie time differencemeasuredby the comparator 158 to zero. The signal output 1510 fromthe tape-recoroer 152 is connected in similar manner via A/D converter 1511, RAMdelay 1512, RAM read out 1513 via signal latch 179 2 to D/A converter 1514, and filter 1515 to the output 1516. Tne read out address (1513) of delay 1512 is controlled in tne same way as the read out from the control signal delay 154 by the output from thecomparator158. Operationof theRAi1output latches179 and179 2 willbe describedbelα;with reference toFigure17. In this arrangement thecontrol signal 151 and the signal 1510 fra-i the tape-recorder may, for economy, be digitised with different resolution A/D conversions. For example a much higher resolution (14 bits) may be adopted for the signal channel to retain signal fidelity, whereas tiiecontrol signal canuseamuchlcwer resolutionof 8 bits (say). The operation of the comparator 158 canbe appreciatedmore easilyby reference to Figure 16. The reference and control signals Sτ_ and S2 to be compared are limited to produce square waves and the leading edges are used respectively to clock and read a 1MHz counter which enables the time differenceAt tobemeasured toanaccuracyof±1/2μsec. Inoneparticular arrangement using a5kc/s control signal, a2kbitRAHdelay154 isused and the signal is sampled at a rate of 50 kc/s; i.e. the delay 154 is clocked at this rate. Thus about 200 cycles of the control signal are stored in the delay 154. Changing the tap 155 by one position is then equivalent to a delay change of20 isec. The time difference t isdetermined inthefdr (Nx20+ n)jasecwhere Nand n are integers and n is inthe range0 to19jisec. Kis then the number corresponding to thechange of address of the tap155, positive or negative, and n is a fine adjustment delay applied to the output signal latches 179χ and 1792- As shown inFigure17 the tapemotor speedcontrol 171 is effectedby connecting the control signal output 151 fromthe tape recorder tothe "count down" input of an up/down counter 172 and a 50 kHz reference signal from the clock159 isconnectedtothe "countup" input. Thedigital countoutput from the up/d m counter 172, representing the time difference (control cycles) betweenthecontrol signal fromthetaperecorderand the referencesignal, is connected to a digital to analogue converter 173. The analogue output from the D/A converter 173 is then connected to the tape recorder to control the playback tape speed in similar manner to the Figure 5 arrangement. The drift corrected control signal after transmission through the programmableRAMdelay154 isconnectedto the tmeasuringcircuit158 where the phase time difference from the reference signal from clock 159 is measured. The time difference is recorded by two counters: Counter 174, clocked by a5 KHz signal giving thenumber Kof20 usec intervalsandasecond counter 177, clocked by the 50 KHz reference signal, giving the number n corresponding tomicroseconds in the range 0 - 19jisec. The number K inthe binary counter 174 shall be arranged to count the reference clock (derived from159) suchthat thecountnumberwill runfrom-5 (minus5) throughzeroto +5 (plus 5) then reset to -5 and repeat thereafter. In this manner the time difference t in 158 will normally be zero butwill read positive (0 to+5) foran increase intimedelayofcontrol signal, S , andwill recordanegative number (0 to -5) for an advanced time delayofcontrol signal S 2/ relative to reference signal S x . m this fashion the RAM address, 155, will be either advanced or retarded in time if the signal is retarded or advanced respectively and will therefore have all time delays (to 1 μsec accuracy) removed. Thecorrected signalwill thereforealwaysbewithin±1usecof time (referred to reference) and the maximum wα; & flutter time distortion will also bewith±l^isec and thiswill be irrespective of the taperecoroer wα; and flutter deviation or rate of deviation (modulation frequency) . The nur.i>er n is connectedtoaclockphaselatchadjustingcircuit178. Thephase adjuster 178 provides a clock latching output signal C^,, dependent on n, to control the phase delay of tie clock 159 which is used to operate a one sample (8 bits wide) latch 179. Since tiie phase of the control signal may be advanced or retarded in comparison with the reference signal, the value of N (tiienumber of20j:sec intervalsbywhich theRAMdelayaddress155 ischanged) must be adjusted to ensure that n always represents a phase delay. This is achieved by adding to N in an adder 175 a binary1 whenever the desiredphase changeC c for latch179 is greater than the existing latchphasedelay C- This "change ofaddress" output fromadder175 is thenadded tothecurrent RAM tapRead address (held in latch176) ina further adder1710. Theoutput from this adder is then stored in latch176 [using a delayed (157') version of the control tone from filter 157 - to alia; for signal propagationdelays through address 175 and 1710] and provides thenewaddress for the tap155. At start¬ up, the RAM address latch 176 has an address corresponding to the centre address of the RAM 154. As described, the n counter 177 and the binary (-5 to 5) counter 174 arearranged such that the remaindernalways represents adelayfor retarding the 50 kHz clock 159 used to clock signal samples fromthedelay154. Thus if At = -50 _μs, representing the time needed to retard (in time) the control signal, then 1. is set at-2 andnat 10_μs. Thus the read address isdelayedby two additional places away from the RAM write address (Figure 15), representing an increase in RAH delay of 40 μs, and the output latch clock pulses are delayed by n = 10_μs. Where a time advance At = 45 jis (say) is required, the circuitry is arranged such that the binary counter M is increased by 3, i.e. binary 3 is added to the read address and the read tap is moved three places closer (earlier) to the RAM write address (Figure 15) corresponding to an advance of 60jαs. The remainder n is then provided as a delayof15jιs totheoutput latch (179) clockCLwherebythe resultingadvance is 45 μs. The output latch 179 thus provides a means by which tiie signal output can be time corrected in 1 jαsec intervals. Without this latching technique the signals could only be corrected in lusec intervals (signal sampling rate) by altering the read address. To achieve this accuracy otherwise would require a 1MHz clock RAM, 40 kbits long, and anA/D converter operating at 1MHz. This is neither practicable nor affordable. As in the arrangements described previously the comparator 158 is arranged to provide signals for simultaneous adjustment of the phase output latch 179 2 clock CL and the read address for the signal delay 1512. The output signals fromthe delays 154 and 1512 after conversion toanalogueform- arepassed throughanti-sampling filters 157 and 1515 respectively to filter out the sampling frequencies (50 kHz) . The filter 157 must have an impulse responseof less than 200 usecsforotherwisethephase/timecorrectionsmade to the control signals will not have propagated through theRAI-I (154), latch (179), filter (157) and comparator (158) bythetime (200 useclater) thenext correction is to bemade. If thisshouldhappenthe 'system 1 may "recorrect" the sameprevious time errors. This couldthenleadtoeither instabilityor a sustained "ringing" effect in the correction circuit and therefore on the signals. In alternative arrangements the circuitry could be arranged such that an adjustment is first made and thereafter at 400 μs intervals (or multiples of 200jisec where the control tone is 5 KHz giving a period of 200 jisec) rather than every200 ^ μs. Bythis means the impulse response (ringing time) delay of the filter 157 may be allαved to be greater without causing instability.

Claims: Claims 1. A signal correction system co-.prising: transmission means to transmit a control reference tone; and receiving means to receive the signal and the reference tone, and including: a) local oscillator means to produce an identical tone to the transmitted control reference tone; b) comparator means to compare the frequency of the mean control tone with the local oscillator tone; c) drift correction means connected to tie frequency comparator means to apply a common f equency shif to tne received signal an the reference tone to reduce to zero tiie difference output from the frequency comparator; d) a phase comparator circuit to compare tne phase of tiie drift- corrected reference tone with the phase of the local oscillator tone; and e) short term flutuation correction means connected to the phase comparator circuit to apply to tne received signal ana the drift-corrected reference tone a common phase delay to reduce to zero tne difference output from tiie pnase comparator. cause time slip and frequency shifting in the play-^ α; signal. 2. Λ signal correction system comprising: transmission means to transmit a control reference tone; and receiving means to receive the signal and the reference tone, and including: a) local oscillator means to produce an identical tone to the transmitted control reference tone; b) comparator means to compare the frequency of the mean control tone with tiie local oscillator tone; c) correction means connected to the f requency comparator means to apply a frequency shift to tiie local oscillator means to reαuce to zero the difference output from the frequency comparator; d) • a phase comparator circuit to compare thephaseof tne reference tone with the phase of the corrected local oscillator tone; and e) short term flutuation correction means connected to the phase comparator circuit to apply to the received signal and the reference tone a common phase delay to reduce to zero the difference output from the phase comparator. 3. A signal correction system as claimed in claim 1 or 2 wherein the frequencycomparatormeanscomprisesa cyclicbinarycounterhavinganoutput clocked by a signal eriveα fro the local oscillator. 4. A signal correction system as claimed in claim 3 wherein the cycling of the binary counter is determined by a detector connected to the counter and responsive to apredetermined binaryniαi-ber (Li j -,) to provide a resetsignal to the counter. 5. A signal correction system as claimed in claiι» 4 wherein the local oscillator-derived clock signal is produced by connecting tiie local oscillator signal to tiie input of a diviαe-by-l n , where n is an integer. 6. signal correction system as claimed in claim5 wherein the output fro;.; tne binary counter is clocked into an output latch circuit and tiie latcn output is connected to a D/A converter to produce an analogue signal representative of the frequency 7 time drift between the received reference tone and the local oscillator tone. 7. A signal correction system as claimed in anyone preceding claim-wherein the received reference tone isbandpass filtered andlimited to minimise the effects of fading and dropouts. 8. Asignalcorrectionsystemasclaimedinclaim1 oranyoneofclaims3 to7 wherein the drift representative D/A output samples are connected to an active voltage integrator circuit comprising a transconductor and a capacitor. 9. A signal correction system as claimed in ciaim 2 wherein the drift representativeD/Aoutput samples areconnectedto trielocal oscillatormeans - to change tne frequency of oscillation. 10. A signal correction circuit as claimed in any one preceding claim wherein the reference tone is connected via a fast programmable delay circuit to the phase comparator circuit and tie short term fluctuation correction means comprises the programmable delay circuit and a voltage controlled oscillator (VCO) , the arrangement being such that the voltage output from the phase comparator is connected to the input of theVCO and the VCO output is connected to the delay circuit such that the phase comparator error output is minimised. 11. A signal correction circuit as claimed in claim10 wherein li iters are provided in the circuit connections to the inputs of the phase comparator. 12. A signal correction circuit as claimed in claim 10 or 11 wherein the output signal from tiieVCO is connected to a second delay circuit, identical to tie first: the drift corrected received signal being connected to the input to the second delay circuit and the drift and short term fluctuation corrected signal being provided at the output thereof. 13. A signal correction circuit as claimed in claim 12 wherein l ; pass filters are provided at the input and output of the second delay circuit. 14. A signal correction circuit as claimed in claim 12 or 13 wherein each delay is a digital delay. 15. A signal correction circuit as claimed in any one preceding claim wherein more than one phase comparator stages of short term fluctuation correction is provided. 16. A signal correction circuit as claimed in claim 1 or 2 wherein the frequency comparator means comprises an up/dαm counter, the received control tone and the local referencetonebeingconnectedto respectivecount down and count up inputs and theoutputdifference signal being connected to a means effective to reduce to zero the frequency difference between the control tone and the reference tone. 17. A signal correction circuit as claimed in claim 1, 2 or 16 wherein the phase time delay for correcting the remaining phase differences between the control and reference tone is applied by a digital time delay circuit comprising a prograπrnable RAH delay and a series connected RAH latch, and a phase adjuster for the latch, the arrangement being such that digital signal samples are clocked in to theWriteaddress oftheRAMdelayat frequencyF and are read out from a programmable Read address to the latch to provide a time delay having incremental value AT of 1/F, the clock signal to the RAI-Ilatch being delayedbyadigitised timehavingan incrementalvalueAt intherange 0 to 1/F, to thereby provide an overall time delay to an accuracy of At. 18. A signal correction circuit as claimed in claim 17 wherein the phase comparator comprises limiter means to square the control signal and the replica reference signal and a counter responsive to the leading edges ofthe respective squared signals so as to be triggered by the reference signal and read by the control signal. 19. A signal correction circuit as claimed in claim 18 wherein the counter clock frequency is n times the RAHclock frequencyF and thephase comparator measures the phase difference in units (K) of 1/F and (R) of 1/nF. 20. A signal correction circuit as claimed in 19 wherein there is provided meanswhereby the digitised phase difference17+ R, which maybe positive or negative, ismodifiedbyconditional change ofNsuchthat R.always represents a delayed phase difference. 21. A signal correction circuit as clai-med in claim 20 wherein the Read address for theRAI-Iis stored inaReadlatchconnectedtoanadder suchthat it can be adjusted by the modified N and R is used to set the delay for the RAH latch. 22. A signal correction circuit as claimed in any one of claims 16 to 21 whereinthe referencesignal isprovidedas areferenceembedded ineach input channel of amulti-channel recorderor as a reference inadedicatedreference channel. 23. A signal correction circuit as claimed in any one of claims 16 to 22 wherein the drift correction means includes a signal connected from the output of the frequencycomparator tothetapecapstanmotordrivetovarythe drive speed. 24. A signal correction circuit as claimed in claim 23 wherein a light dependent resistor is used to correctly interface between the frequency comparator and the tape capstan motor drive. 25. A signal correction circuit as claimed in any one of claims 10 to 16 wherein a 6dB/octave low pass filter is connected between the phase comparator and theVCOwhereby theloopgainof thewα;andfluttercorrection circuit decreases inversely in proportion to the modulation frequency.

Inventors: WILKINSON ROBERT, WILKINSON, ROBERT
Applicants: SECR DEFENCE BRIT, THE SECRETARY OF STATE FOR DEFENCE IN HER BRITANNI
Application year: 1989
Main classification: G11B20
IPC codes: G11B15, G11B20