Band-gap reference voltage arrangement

Abstract: The invention relates to a band-gap reference-voltage arrangement comprising - a MOS differential amplifier (OA2) having two inputs and one output, - a first bipolar transistor (Q3) whose base emitter path is arranged between one input of the differential amplifier (OA2) and a specific junction point and whose emitter-collector path is arranged in a first current path for carrying a first current, - a second bipolar transistor (Q3) whose base emitter path in series with a resistor (R6) is arranged between the other input of the differential amplifier and said junction point and whose whose emitter-­ collector path is arranged in a second current path for carrying a second current, - means (P1, P2) for supplying said first and second currents through said first and second current paths, - a feedback path for feeding back the signal from the output of the differential amplifier to the first junction point, comprising a third transistor (Q5) whose base-emitter path is arranged between said junction point and the output of the differential amplifier.

Description: The invention relates to a band-gap reference-voltage arrangement comprising a MOS differential amplifier having a first and a second input and an output, a first bipolar transistor whose base-emitter path is arranged between the first input of the differential amplifier and a first junction point and whose emitter-collector path is arranged in a first current path for carrying a first current, a second bipolar transistor whose base-emitter path in series with a first resistor is arranged between the second input of the differential amplifier and the first junction point and whose emitter-collector path is arranged in a second current path for carrying a second current, a series arrangement of a second and a third resistor arranged between a supply voltage terminal and an output terminal of the arrangement for taking off a reference-voltage, a second junction point between the second and the third resistor being coupled to the base of the second transistor, the output of the differential amplifier being coupled to the output terminal of the arrangement, and means for supplying the first and the second current through the first and the second current path, respectively, the first resistor being arranged between the base of the second transistor and the first junction point. Such a band-gap reference-voltage arrangement is described for example, in United States Patent Specification 4,380,706 and 4,287,439, and in PCT application WO 81/02348. For an explanation of the operation of these known circuit arrangements reference is made to the literature cited and to general articles, such as the article "Band-gap Voltage Reference Sources CMOS Technology", Electronisc Letters, 7 January, 1982, Vol. 18, no. 1, pages 24/25. Depending on the specific version these known circuit arrangements have one or more of the following drawbacks: the common-mode input voltage on the inputs of the MOS differential amplifier is frequently such that the MOS transistors in this amplifier have to operate in their triode region, which may result in an unbalance in the differential amplifier and loss of gain, so that the performance of the entire band-gap reference-voltage arrangement deteriorates, the required chip area for the resistors in the arrangement is generally found to be considerable, the MOS differential amplifier is afflicted with offset caused by mismatching of components in the arrangement. It is the object of the invention to eliminate these drawbacks at least partly. In a band-gap reference-voltage arrangement of the type defined in the opening paragraph this object is achieved in that the first junction point by means of a base-emitter path of a third transistor is coupled to one end of the series arrangement of the second and the third resistor. In a circuit arrangement having these characteristic features the voltage difference between the common-mode input voltage of the differential amplifier and the supply voltage on the voltage terminal connected to the series arrangement of the second and the third resistor is larger in comparison with known arrangements. Thus it is avoided that the MOS transistors in the differential amplifier have to operate in their triode regions. The gain factor of the differential amplifier can therefore be high enough to ensure a correct operation of the arrangement. Moreover, in an arrangement having these characteristic features the chip area occupied by the resistors can be reduced substantially. A first embodiment of a band-gap reference-voltage arrangement in accordance with the invention is characterized in that the base of the third transistor is coupled to the output terminal of the arrangement. In this case the reference-voltage is supplied relative to the positive supply voltage. A second embodiment of a band-gap reference-voltage arrangement in accordance with the invention may be characterized in that the base of the third transistor is coupled to a further supply voltage terminal. This reference-voltage is supplied relative to the negative supply voltage. A suitable embodiment of the band-gap reference-voltage arrangement in accordance with the invention is characterized in that the first and the second transistors are replaced by a first and a second array of transistors, the number of transistors in the first and the second array being equal and the transistors in the first and the second array being interconnected in such a way that each transistor has its collector-emitter path arranged in a current path for carrying the first and the second current, respectively, and has its base connected to an emitter of a next transistor, the emitter of the last transistor in the first and the second array being connected to a respective input of the differential amplifier, and the base of a first transistor in the first and the second array being connected to the first junction point and to the first resistor, respectively. By replacing the first and the second resistor by an array of transistors the offset voltage between the inputs of the differential amplifier as a result of the non-identical first and second transistor transistor is reduced. If a substantial reduction of the offset effect is required it is preferred to include a comparatively large number of transistors in each array. The offset effect decreases as the number of transistors increases. However, the number of transistors in both arrays should not be so large that the voltage across them becomes larger than half the supply voltage, because otherwise the advantage of an improved common-mode setting will diminish. If the reference-voltage is taken off relative to the positive supply voltage the improvement of the common-mode input voltage of the differential amplifier may be less pronounced, depending on the value of the output voltage, than in the case that both arrays comprise only a single transistor, but on the otherhand the influence of the offset caused by mismatching of components is reduced substantially. In that case a satisfactory compromise, which enables both an improvement of the common-mode input voltage and an improvement of the offset effect to be achieved, is obtained if the number of transistors in the first and second array is two. The invention will now be described in more detail, by way of example, with reference to the accompanying Figures. Figure 1 by way of comparison shows an arrangement known per se , in which the MOS transistors of the differential amplifier have to operate in the in triode regions and in which in the case of integration a substantial portion of the chip area is occupied the resistors. Figure 2 shows diagrammatically the principal components of the differential amplifier. Figure 3 shows a first embodiment of an arrangement in accordance with the invention. Figure 4 shows an embodiment of an arrangement as shown in Figure 3, employing two arrays comprising two transistors each. Figure 5 shows a second embodiment of the arrangement in accordance with the invention, which also utilizes transistor arrays. The circuit arrangement shown in Figure 1 comprises a MOS differential amplifier OA1, the transistors Q1 and Q2 and the resistors R1 to R5. The transistor Q1 is connected to the power supply V DD in series with the resistor R3. The transistor Q2 in series with the resistors R1 and R2 is connected to the power supply V DD . The bases of the two transistors Q1 and Q2 are interconnected and are driven by the voltage on the junction point of the series arrangement of the resistors R4 and R5, which is arranged between the power supply V DD and the output terminal on which the output voltage V out is available. The inputs of the differential amplifier are respectively connected to the junction point between Q1 and R3 and the junction point between R1 and R2. The output of the differential amplifier is connected to the output terminal V out . The collectors of the two transistors Q1, Q2 are connected to the negative supply voltage, for example earth, if required via further components, not shown, which may form part of a further circuit utilizing the reference-voltage to be generated. In the simplest case the two collectors are connected directly to the aid negative supply voltage. In this circuit arrangement the voltage on the bases of the transistors Q2, Q1 is equal to the positive supply voltage V DD minus the band-gap reference-voltage of approximately 1.3 V. The common-mode input voltage of the differential amplifier OA1 is then equal to V DD - 1.3 V + V BEQ1 ≈ V DD - 0.7 V , which is too high, so that the MOS transistors in the differential amplifier OA1 have to operate in their triode regions. As a result of this the gain of the differential amplifier is comparatively small, which has an adverse effect on the correct operation of the arrangement. Figure 2 shows diagrammatically the principal components of the differential amplifier, i.e. the MOS transistors P8 to P11. The two transistors P10 and P11 constitute a current mirror for supplying currents to the input transistors P8 and P9, which are connected to the two inputs IN1 and IN2. The transistor P12 provides the current setting and is controlled by the bias voltage V bias . The output signal is then available on the output out. For further details of such a MOS differential amplifier reference is made to the literature well-known to those skilled in the art. By way of example reference is made to the article "An integrated Single Chip PCM Voice codec with filters", IEEE Journal of Solid State Circuits, Vol. Se-16, no. 4, August, 1981, page 330, Figure 13. Figure 3 shows a first embodiment of a circuit arrangement in accordance with the invention in which the common-mode input voltage of the differential amplifier is at a lower voltage level relative to the positive supply voltage V DD than in the arrangement shown in Figure 1. This arrangement again comprises the MOS differential amplifier OA2, the bipolar transistors Q3, Q4, Q5, the resistors R6, R7, R8, and the MOS transistors P1, P2 and P3. The transistors P1 and P2 together with the current source transistor P3 are arranged in a current mirror circuit and are connected to the power supply voltage V DD . Further, the transistors P1, P2 and P3 are dimensioned in such a way that for a predetermined current through P3 a desired first current flows through P1 and a desired second current through P2. P1 is arranged in series with Q3, so that the first current also flows through Q3 and P2 is arranged in series with Q4 so that the second current also flows through Q4. The junction point between P1 and Q3 is connected to one input of the differential amplifier OA2 and the junction point between P2 and Q4 is connected to the other input of the differential amplifier OA2. The bases of the transistors Q3 and Q4 are each connected to a terminal of the resistor R6. Moreover, the base of Q3 is connected to the emitter of Q5 whose base is driven by the output of the differential amplifier OA2. The base of Q5 is further connected to the resistor R7, which is arranged in series with the resistor R8 between the power supply V DD and the output junction point on which the output voltage V out is available. The junction point between R7 and R8 is connected to the base of Q4. The collectors of the transistors Q3, Q4, Q5 are connected to the negative supply voltage (for example earth) either directly of via component of the circuit of which the reference arrangement forms part. The currents through the transistors Q3 and Q4 and the appropriate dimensioning of Q4 ensure that different base emitter voltages ΔV BE are produced across the two transistors. The difference between the two base emitter voltages ΔV BE appears across the resistor R6. By driving the transistor Q₅ the operational amplifier OA2 tends to influence the current through R6 in such a way that a balanced situation is obtained in which the arrangement in a manner known per se can function as a band-gap reference-voltage arrangement. However, the difference with the known arrangement resides in the fact that in the present arrangement the common-mode input voltage appears on the inputs of the differential amplifier OA2. As will be apparent from Figure 3, the common-mode input voltage V cm for a choice of V out = 2.8 V which is determined by the resistance value of the resistors R7 and R8 will be equal to The above numerical example show that the common-mode input voltage of the differential amplifier in the arrangement shown in Figure 3 in comparison with the situation in Figure 1 is reduced substantially relative to the positive supply voltage V DD . An additional though not in significant advantage is that the overall resistance in the arrangement shown in Figure 3 is reduced considerably. For the same power supply current of 12.2 µA as in Figures 1 and 3 the overall resistance required in the arrangement as shown in Figure 3 is only 46% of the overall resistance in the arrangement shown in Figure 1. This results in a corresponding reduction in chip area. Figure 4 shows a second embodiment of an arrangement in accordance with the invention, which instead of the transistors Q3 and Q4 employs a cascade arrangement comprising the transistors Q6 and Q8 and Q7 and Q9 respectively. Each of said transistors Q6 to Q9 is connected to the power supply line V DD in series with a separate MOS transistor P4 to P7. The MOS transistors P4 to P7 are arranged as a current mirror circuit controlled by the current source transistor P8 in such a way that a first current flows through each of the transistors Q6 and Q8 and a second current flows through each of the transistors Q7 and Q9. For the remainder the arrangement shown in Figure 4 is identical to that of Figure 3, except that the resistors R9, R10 and R11 perform the functions of the resistors R6, R7 and R8 in Figure 2, the transistor Q10 performs the same function as the transistor Q5 in Figure 3, and the differential amplifier OA3 performs the same function as OA2 in Figure 3. In Figure 4 the connections between the collectors of the transistors Q6...Q10 and a fixed potential are not indicated. For the same voltage V out = 2.8 V across the resistors R10 and R11, the common-mode input voltage V cm of the differential amplifier OA3 will now be equal to In comparison with the situation in Figure 1 the common-mode input voltage is still reduced relative to the voltage V DD , although this reduction is smaller than achieved with the embodiment shown in Figure 3. However, the effect of a possible offset in the differential amplifier, caused by mismatching of components is now reduced by a factor of 2. In this respect it is to be noted that now a voltage 2ΔV BE is developed across the resistor R9, i.e. a base emitter differential voltage which is twice as large as the comparable voltage across the resistor R6 in Figure 3. A further reduction of the effect of offset can be achieved by using three or more transistors in each of the cascade arrangements. It will be evident that depending on the magnitude of the voltage across the resistors R10 and R11 this is at the expense of the improvement in common-mode input voltage. However, under specific circumstances it may be preferred to utilize cascade circuits comprising larger numbers of transistors. Figure 5 shows a second embodiment of an arrangement in accordance with the invention, comprising a cascade circuit comprising j transistors. In this embodiment the base of the transistor Q13 is connected to the negative supply voltage in the present earth, and the output of the differential amplifier OA4 is connected to the output terminal. Now this results in a positive reference-voltage V out relative to earth being generated. The arrangement shown in Figure 5 comprises said differential amplifier OA4, the transistors Q11a...Q11c constituting the first array, the transistors Q12a...Q12c constituting the second array, and the transistor Q13. The arrangement further comprises the resistors R12, R13 and R14, which perform the same functions as the resistors R9, R10, R11 in Figure 4. The MOS transistors, which are operated as current source transistors, are not shown separately but are represented diagrammatically as the current sources I1 to I6. Again the further connections between the collectors of the bipolar transistors Q11a...Q11c, Q12a...Q12c, Q13 to a negative supply voltage are not shown. If each cascade circuit comprises j transistors a voltage jΔV BE will be generated across the resistor R12. The output voltage V out of the arrangement can be computed as follows V out = g [V BE (Q13) + n.j.ΔV BE + n.V. os ] where g = 1 + R14/R13 n = 1 + (1/g).(R14/R12) V BE = basis-emitter voltage V os = equivalent input offset voltage of OA4 j = an arbitrary integer, representing the number of transistors in each array. Suitably, j is selected to be as large as possible within the limits imposed by the value of the power-supply voltage V DD . If allowance is made for the base emitter voltage across Q13 the following relationship is valid (j + 1) . V BE < V DD - (voltage drop across the current sources I n ) In practice, j = 4 will be a satisfactory choice for a power supply voltage V DD = 4,5 V. The output voltage V out becomes temperature-independent for T₀ if R14/R13 is selected in such a way that n = [1.2 V - V BE (Q13)]/[j . ΔV BE ] T₀ If j is selected to be as large as possible the effect of V os is reduced. It is to be noted that in this embodiment, in contrast to the embodiment shown in Figure 4, where the level of the common-mode input voltage relative to the positive supply voltage is adversely affected by replacing the first and the second transistor by the two arrays, this replacement has a favourable influence on said relative level. It is obvious that in the embodiment shown in Figure 5 the arrangement may be constructed by means of separate transistors instead of arrays. Further, it is to be noted that in the embodiments shown herein the differential amplifier may be of any other construction than that shown in Figure 2. Finally, it is to be noted that in the embodiments shown herein the transistors may be replaced by transistors of the opposite conductivity type.

Claims: A band-gap reference-voltage arrangement comprising a MOS differential amplifier (OA1; OA2; OA3; OA4) having a first and a second input and an output, a first bipolar transistor (Q1; Q3; Q6, Q8; Q11a, Q11b, Q11c) whose base-emitter path is arranged between the first input of the differential amplifier (OA1; OA2; OA3; OA4) and a first junction point and whose emitter-collector path is arranged in a first current path (Q1, R3; Q3, P1; Q8, P6; Q11c, I5) for carrying a first current, a second bipolar transistor (Q2; Q4; Q7, Q9; Q12a, Q12b, Q12c) whose base-emitter path in series with a first resistor (R1; R6; R9; R12) is arranged between the second input of the differential amplifier (OA1; OA2; OA3; OA4) and the first junction point and whose emitter-collector path is arranged in a second current path (Q2, R2; Q4, P2; Q9, P7; Q12c, I6) for carrying a second current, a series arrangement of a second (R4; R8; R11; R14) and a third (R5; R7; R10; R13) resistor arranged between a supply voltage terminal (VDD; ground) and an output terminal (Vout) of the arrangement for taking off a reference-voltage, a second junction point between the second (R4; R8, R11; R14) and the third (R5; R7; R10; R13) resistor being coupled to the base of the second transistor (Q2; Q4; Q7, Q9; Q12a, Q12b, Q12c), the output of the differential amplifier (OA1; OA2; OA3; OQ4) being coupled to the output terminal (Vout) of the arrangement, and means for supplying the first and the second current through the first (Q1, R3; Q3, P1; Q8, P6; Q11c, I5) and the second (Q2, R2; Q4, P2; Q9, P7; Q12c, I6) current path, respectively, the first resistor (R1; R6; R9; R12) being arranged between the base of the second transistor (Q2; Q4, Q7, Q9; Q12a, Q12b, Q12c) and the first junction point, characterized in that the first junction point by means of a base-emitter path of a third transistor (Q5; Q10; Q13) is coupled to one end of the series arrangement of the second (R4; R8; R11; R14) and the third (R5; R7; R10; R13) resistor. A band-gap reference-voltage arrangement as claimed in Claim 1, characterized in that the base of the third transistor (Q5; Q10) is coupled to the output terminal (Vout) of the arrangement. A band-gap reference-voltage arrangement as claimed in Claim 1, characterized in that the base of the third transistor (Q13) is coupled to a further supply voltage terminal (ground). A band-gap reference-voltage arrangement as claimed in Claim 1, 2 or 3, characterized in that the first (Q1; Q3; Q6, Q8; Q11a, Q11b, Q11c) and the second (Q2; Q4; Q7, Q9; Q12a, Q12b, Q12c) transistor are replaced by a first (Q6, Q8; Q11a, Q11b, Q11c) and a second (Q7, Q9; Q12a, Q12b, Q12c) array of transistors, the number of transistors in the first (Q6, Q8; Q11a, Q11b, Q11c) and the second (Q7, Q9; Q12a, Q12b, Q12c) array being equal and the transistors in the first (Q6, Q8; Q11a, Q11b, Q11c) and the second (Q7, Q9; Q12a, Q12c, Q12c) array being interconnected in such a way that each transistor (Q6, Q8; Q11a, Q11b, Q11c; Q7, Q9; Q12a, Q12b, Q12c) has its collector-emitter path arranged in a current path (Q6, P4; Q7, P5; Q8, P6; Q9, P7; Q11a, I1; Q11b, I2; Q11c, I3; Q12a; I4; Q12b, I5; Q12c, I6) for carrying the first and the second current, respectively, and has its base connected to an emitter of a next transistor, the emitter of the last transistor (Q6, Q7; Q11a, Q12a) in the first (Q6, Q8; Q11a, Q11b, Q11c) and the second (Q7, Q9; Q12a, Q12b, Q12c) array being connected to a respective input of the differential amplifier (OA1; OA2; OA3; OA4), and the base of a first transistor (Q1, Q9; Q11c, Q12c) in the first (Q6, Q8; Q11a, Q11b, Q11c) and the second (Q7, Q9; Q12a, Q12b, Q12c) array being connected to the first junction point and to the first resistor (R1; R6; R9; R12), respectively. A band-gap reference-voltage arrangement as claimed in Claim 4, characterized in that the number of transistors in the first (Q6, Q8) and the second (Q7, Q9) array is two.

Inventors: HOLLE EERKE, HOLLE, EERKE
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1989
Main classification: G05F3
IPC codes: G05F3