Differential cascode current switch (DCCS) logic circuit family with input diodes

Abstract: The present logic circuit family is derived from the conventional DCCS logic circuit family. The logic circuit shown in the attached drawing is a six-input AND/NAND. It includes: a logic tree (41) comprised of bottom, middle, and top stages (44, 45, 46) cascoded and dotted at the tree output nodes (OUT, OUT ) to perform a determined logic function (F, F ). The top stage (46) includes a current switch (49) formed by a pair of input transistors (TX431, TX432) connected in a differential amplifier configura­ tion. The base of one input transistor (TX431) on the left side of the tree is connected to the output of an AND gate, which consists of input diodes (D431, D432, ...) and resistor (RD41). True (IN PHASE) logic input signals (Z41, Z42, ...) are ANDed in this AND gate and a first elementa­ ry output signal, is available at the common emitter node (CN43) of the said differential pair. On the right side, additional input transistors (TX433, ...) are paralleled with the other input transistor (TX432) of the differen­ tial pair, so that the complementary (OUT OF PHASE) input signals ( Z41 , Z42 , ...) that drive the transistors, are ORed to deliver a second elementary output signal, comple­ mentary to said first elementary output signal, on said common emitter node (CN43). Same principle applies at the the first and second levels to build the bottom (44) and middle (45) stages. The present invention allows to increase the number of logical inputs to be applied to a DCCS logic circuit, and in turn, the number of logic functions performed in the logic DCCS tree. As a result, an extended library of DCCS logic circuits may be obtained.

Description: The present invention relates generally to logic circuits and more particularly to powerful combinational N level high cascoding logic tree circuits with embedded supplemental logic functions in the inputs that are capable of processing complex Boolean logic functions with a high number of logic inputs. The cascode current switch (CCS) logic circuit family is derived from the well known Emitter Coupled Logic (ECL) circuit family. ECL circuits are characterized by a systematic usage of non saturated transistors, resulting in high speed performances. Given the obvious power of the ECL logic circuits, the CCS logic circuits are the ideal candidates for being implemented in high end computers. The CCS logic circuit technology has potentially superior power-performance attributes compared to other logic circuit technologies. The cascode structure improves the logic efficiency of the circuits library, in that it allows a great variety of logic functions to be available to the user, but, at the cost of a more complex design system. As a whole, the CCS circuit technology still remains highly desirable because of its fast switching speeds. Cascode type of circuits can be classified in two main logic circuit families the single ended cascode current switch (SECCS) circuit family, which uses accurate reference voltages, and the differential cascode current switch (DCCS) circuit family. Several typical SECCS logic circuits are depicted in an article entitled "Simplified cascode reference generation" published in the IBM Technical Disclosure Bulletin Vol. 30 N° 4 Sept. 1987 pp. 1816-1819. A basic circuit belonging to this family is shown in Fig. 1 of the present application. Circuit 10 is a standard six-input NAND circuit consisting of a central three-level cascode current switch logic tree 11, driving two emitter-follower circuits 12 and 13 to supply the complementary circuit output signals: respectively the IN PHASE and OUT OF PHASE circuit output signals. Logic tree 11 comprises bottom, top, and middle stages 14, 15, 16 dotted at the tree output nodes to perform a determined logic function. Basically, circuit 10 is made of three sets of current switches referenced 17, 18, and 19 mounted in a cascode configuration to form the logic tree 11. Each current switch comprises a pair of input transistors in parallel connected in a differential amplifier configuration with a reference transistor. The bottom stage at the first level comprises input transistors TX111 and TX112 connected in a differential amplifier configuration with reference transistor TX113. Input transistors TX111 and TX112 receive binary logic input signals A11 and A12 respectively, that are applied to the bases of said input transistors. The base of reference transistor TX113 is connected to a reference voltage VR11. At the second level, middle stage 15 comprises input transistors TX121 and TX122 driven by input signals B11 and B12, and reference transistor TX123, whose base is connected to reference voltage VR12. Finally, at third level, top stage 16 comprises input transistors TX131 and TX132 driven by input signals D11 and D12, and reference transistor TX133 whose base is connected to reference voltage VR13. The common collector of transistors TX131 and TX132 is connected to load RCC1. Collector of transistor TX133 is connected to load RCT1. These nodes correspond respectively to the tree output nodes referenced OUT and OUT. The bottom stage is supplied by a constant current I0, determined by a conventional current source comprised of transistor TY1, the base of which is connected to a fixed reference voltage VRR (delivered by a reference voltage generator not shown), and resistor RE. Said constant current I0 given by relation I0 = ((VRR-VBE(TY1))/RE), has to flow either through transistors TX113 or TX111 and/or TX112. As a matter of fact, it flows through the one transistor which receives the highest base voltage. The collector voltage of transistors TX111 or TX112 may drop to a low value as soon as the current flows through input transistors TX111 or TX112. Similar reasoning applies to other levels. The constant current source 10 sets the power that the logic tree 11 will consume in performing its assigned logical function. The logic operation is accomplished through selectively steering the current through an adequate path within the tree to one of the three output summation points at their respective stage that are referenced CN11, CN12 and CN13. These summation points correspond to the common emitter node of a pair of input transistors and the corresponding reference transistor. Current steering is accomplished by applying logic input signals to each input transistors in the tree, that will select the input transistors to be turned ON. The three sets of current switches in circuit 10 are connected so that, to get a low voltage on the OUT node, corresponding to a logical "0", the current has to flow one path only from top to bottom through TX133 or TX123 or TX 113. Circuit 10 further includes one translator stage per output, respectively referenced 12 for the true output (IN PHASE signal) and 13 for the complement output (OUT OF PHASE signal). Translator 12 comprises buffer transistor TY2 connected in an emitter-follower configuration and driven by the signal supplied at node OUT. The true circuit output signal representing the logic function F1 performed by circuit 10, is available at output node T11 or T12. Diode SBD1 is used as a level shifter to shift down the voltage at node T12. Transistor TY3 and resistor RST act as a constant current source for translator 12. Similar construction applies to translator 13 for the complement circuit output signal F1 , that is available at node C11 or C12. Circuit 10 is biased between a first supply voltage, a positive voltage VPP = 5V, and a second supply voltage, the ground GND. As a result, the logic Boolean function that is performed by circuit 10 is therefore F1 = (A11+A12).(B11+B12).(D11+D12). Other functions like extended ORs, Exclusive ORs (XORs), etc... may also be obtained by changing the connections between the different sets of current switches and the number of transistors contained therein. The OAI logic circuit depicted in Fig. 1 is of the single ended type because, only the true binary input logic signals (e.g. A11, A12, B11, ...) are necessary. True input signals are applied to the bases of the input transistors, while the bases of other transistors so called reference transistors, are connected to a reference voltage (VR11, VR12, ...). Circuit 10 comprises three cascode levels and works properly with VPP = 5 V, but it is very doubtful that this circuit would operate satisfactorily with the very low supply voltages, e.g. VPP = 3.4 V, that are used today in advanced computers. If three or more levels are necessary to increase the number of logical- inputs, the conventional SECCS circuit of Fig. 1 would be no longer functional. As a result, the circuit library is limited in that respect. A significant improvement is described in EP-A-320555. Based on the teachings of that disclosure, Fig. 2 of the present application shows a two-two OA/OAI logic circuit referenced 20, with one three-input AND and one two-input AND gates connected to the input transistors. Circuit 20 is derived from the conventional three-level single-ended cascode current switch (3L-SECCS) logic circuit 10 of Fig. 1. Similar/corresponding elements bear similar / corresponding references. With respect to circuit 10 of Fig. 1, two major changes have been implemented in circuit 20 of Fig. 2. First, the transistors composing the first level have been removed, being a potential source of non-functionality, when low supply voltages, e.g. VPP = 3.4 V, are used, as mentioned above. Secondly, the bases of input transistors TX231 and TX232 of the top stage 26 are respectively provided with three and two level shifter devices, referenced SBD 21-22-23 and SBD 24-25 respectively; each level shifter is connected to a logic input signal referenced P21-22-23 and Q21-22, respectively. Preferably, level shifter devices are Schottky Barrier Diodes (SBD'S). Level shifter devices move the voltages towards the more positive voltage VPP. The role of these extra input diodes in combination with respective resistors RD21 and RD22 is to perform an additional AND function on each of these input transistors, thus compensating the loss of the first level when the number of levels is above three. The logic function at the true output of circuit 20 is given by F2 = (B21+B22) (P21.P22.P23 + Q21.Q22). Because connecting input diodes that way, adds more than one level of equivalent logic function, more logical functions can be implemented in one single logic tree. As a result, the circuit library is significantly enhanced. However, although improved, the SECCS logic circuit family, still suffer from some major drawbacks, specific to that technology, that prevents it from being more extensively used. The first drawback is the need for accurate reference voltage generators. Such generators need complex circuitry to attain the desired stability and consume extra silicon surface. In addition, the very high noise sensitivity of SECCS circuits is a problem for their integration in a mixed type of circuit environment such as the BiCMOS. This is due to the high voltage swing necessary to maintain enough noise margin and thus to accept some voltage drops on power supplies and on the reference voltages. This is a severe inconvenience because the BiCMOS technology, that offers the capability to mix bipolar ECL and CMOS FETs circuits on the same chip for optimization of the power-delay product, appears to have a very promising future. Still another drawback of the SECCS circuits is speed, SECCS circuits are not the fastest of the CCS circuit family. In view of all of these inconveniences, it may be worthwhile to use the other type of the CCS logic technology mentioned above: the so called Differential Cascode Current Switch (DCCS) circuit technology, although the latter has also some inherent limitations, that will be discussed thereafter. Differential cascode current switch (DCCS) circuit technology is also well-known to those skilled in the art. Basic principles have been soon disclosed, for example, in an article entitled "Cascode parity circuit" by E.L. Carter et al published in the IBM Technical Disclosure Bulletin Vol. 24 N° 3 August 1981 pp. 1705-1706. More details can be found in US-A-4760289 assigned to the same assignee as of the present invention. DCCS circuits may be easily derived from SECCS circuits, it suffices to remove one input transistor from the said pair and replace the said reference voltage that is applied to the reference transistor, by the appropriate complementary input. As a matter of fact, a conventional 3L-DCCS circuit performing a three-input AND/NAND function directly derived from circuit 10 of Fig. 1, is shown in Fig. 3 of the present application. Circuit 30 has a two branch structure and is typically implemented with NPN transistors and collector output usage. In the first level, bottom stage 34 consists of a current switch 37 comprising two input transistors TX311 and TX312 connected in a differential amplifier configuration, and driven respectively by binary input signals A31 and A31 . Similar construction applies to the second and third stages 35 and 36, each of which also consist of a current switch referenced 38 and 39 respectively. Binary logic input signals B31, B31 and D31, D31 are respectively applied to said second and third stages. Function F3 is given by F3 = A31.B31.D31. DCCS tree 31 is therefore made of three stacked differential pairs of NPN transistor receiving IN PHASE and OUT OF PHASE logic input signals on their respective bases. The emitters or each pair of transistors are tied together to form a common emitter node. These nodes are respectively referenced CN31, CN32 and CN33 for the first, second and third levels respectively and correspond to the summation points of the logic tree. It is a characteristic feature of DCCS circuit 30 to have only two distinct branches at each stage. For example, in the third stage one branch comprises transistor TX331 and resistor RCC3, the other branch comprises transistor TX332 and resistor RCT, with the tree output nodes OUT and OUT respectively connected therebetween. The tree offers only one path for the current IO defined in the lower part of the circuit by a current source comprised of transistor TY1 and resistor RE. It is very important to notice that in DCCS circuit operation, only one transistor of the differential pair is ON, while the other is OFF. DCCS circuits are very high speed circuits because they operate with reduced voltage swings. In addition, they exhibit a relatively large noise immunity, because, the input signal is always compared to its complement. As a result, DCCS circuits are ideal candidates to be merged with CMOS circuits in a BICMOS single semiconductor chip, to speed up the critical data paths therein. However, the conventional DCCS circuits have also some drawbacks which have prevented them from becoming a generalized logic technology so far. For example, the major drawback of circuit 30 is the limited number of logic functions that can be implemented in the logic tree. This becomes more and more acute when low power supply voltages, e.g. 3.4 V, are used, as required for high end computers. With a 3.4 V power supply, only a maximum of three stages can be cascoded to implement circuit 30, to avoid functionality concerns. It is known by those skilled in the art, that the number of inputs in an AND circuit cannot exceeds the number of cascoded levels. If we suppose that the maximum of cascoded elements is three with a 3.4 to 3.6 V power supply, the Boolean function is then limited to three variables. As stated above, the cascode tree is defined by the stacking of three pairs of transistors to form the bottom, the middle and the top stages. Having in mind that only two paths are allowed by a pair of transistors, adding the middle stage offers four paths for the current with still only one path active at a time. Finally, adding the top stage to the structure permits a maximum of eight different path combinations. The conventional DCCS circuit family is thus limited to three-input AND/OR circuits at the maximum. As a consequence, DCCS circuits have a poor logic efficiency because the library of DCCS circuit is not as exhaustive as desired. In addition, the number of applications that can be derived from the DCCS circuit technology is also limited. So there is a real need to date, of improving the conventional DCCS logic circuit technology in terms of logic efficiency, by adding supplemental AND/OR logic functions on the inputs of the circuits, while still keeping its inherent advantages, in particular in terms of speed and CMOS compatibility for BiCMOS integration. Therefore, it is a primary object of the present invention to provide a structure of improved DCCS type logic circuits that are not limited to three levels of cascode due to the 3.4 V - 3.6 V power supplies that are imposed to future bipolar technologies for high end computers. It is another object of the present invention to provide structure of improved DCCS type logic circuits wherein complex Boolean logic functions may be implemented with a high number of logic inputs at a very low cost. Basically, the present invention as claimed provides logic circuits of the DCCS type that aim to solve the above mentioned problem. The present invention is mainly characterized in that an additional XOR circuit is connected to the base of the input transistors on each side of the cascode current switch forming the top stage of the said logic circuits for increased logic power. The novel features believed to be characteristic of this invention are set forth in the appended claims. Ways of carrying out the invention are described in detail below with reference to drawings which illustrate specific embodiments. Fig. 1 shows a conventional three-level single ended cascode current switch (3L-SECCS) circuit of the prior art performing an OA/OAI logic function. Fig. 2 shows a 3L-SECCS logic circuit of an improved type performing a two-two OA/OAI logic functions with one three-input AND and one two-input AND on the input transistors. Fig. 3 shows a conventional three-level differential cascode current switch (3L-DCCS) circuit of the prior art performing a three-input AND/NAND logic function. Fig. 4 shows a novel logic circuit of the improved family performing a six-input AND/NAND logic function with three cascoded two-input AND to illustrate the basic concept leading to the present invention. Fig. 5 shows a four-input Exclusive-OR (XOR) circuit according to a first embodiment of the present invention. Fig. 6 shows a two-bit compare circuit with a design similar to that of the XOR circuit of Fig. 5. Fig. 7 shows the logic diagram of a nine-bit compare circuit bit with four two-bit compare circuits of Fig. 6, to demonstrate the high logic efficiency of the improved family of logic circuits. We will describe first the principles of the new family of DCCS logic circuits provided with input diodes so called Diode Differential Cascode Current Switch (DDCCS) circuits. An example of a basic logic circuit performing an AND/NAND logic function with an high input number count will be given first. Subsequently, a few examples of logic circuits performing different functions and pertaining to the family will be described. They are part of an exhaustive library of logic circuits which can be derived from the said basic circuit. Said basic logic circuit that is referenced 40 in Fig. 4 performs a six-input AND/NAND elementary Boolean function, and is used in order to illustrate the features and operation of the circuit family of the present invention that are described by the reference to Figs. 5 to 7. Basically, circuit 40 is broadly similar to circuit 30 of Fig. 3 to take full benefit of the systematic usage of an emitter-follower from a performance point of view, in order to get a good power-delay product. Circuit 40 is still made of three sets of current switches 47, 48, and 49 mounted in a differential amplifier configuration forming the cascode logic tree 41 and of one output stage per output signal, respectively referenced 42 for the true output and 43 for the complement output. Output stages for the "true" and "complement" output signals are mounted in an emitter-follower configuration, as mentioned above. They act as translators, in order to adjust the logical levels of the circuit output signals and to amplify the output current. Current sources (not represented) are associated to each output stage and to the logic tree The value of the current is selected according to the load, the dotting, and fan-out of circuit 40. Circuit 40 is still biased between VPP = 3.4 V and the ground GND. The invention will be best understood at the light of the circuitry of top stage 46 at the third level. Current switch 49 is comprised of input transistors, TX431 on the one hand, and TX432, TX433 on the other hand, connected in a differential amplifier configuration to form the top stage 46. In fact, only transistors TX431 and TX432 form the basic differential pair of transistors, according to two branches, so that two independent current paths from VPP to common node CN43 are so defined. The first path consists of resistor RCC4 and transistor TX431, with output node OUT coupled therebetween. The second path consists of resistor RCT4 and transistor TX432 with output node OUT coupled therebetween. On the left side of logic tree 41, diodes D431 and D432 so called input diodes, associated with resistor R41, form an AND gate driven by a combination of IN PHASE binary logic input signals Z41 and Z42. The output signal supplied by this AND gate is the logical AND between input signals Z41 and Z42 i.e. Z41.Z42. This output signal is applied to the base of transistor TX431. This output signal is therefore available with that polarity in the common emitter node of transistors TX431, TX432 and TX433 referenced CN43. Still considering the third level, on the right side of logic tree 41, transistors TX432 and TX433 are driven by the OUT OF PHASE signals Z41 and Z42 applied respectively to their bases. The OUT OF PHASE input signals Z41 and Z42 are summed up in node CN 43 through the OR dotting of transistors TX432 and TX433 connected in parallel. As a matter of fact, the elementary logic signal produced by transistors TX432 and TX433 on the common emitter node CN43 is given by Z41 + Z42 (or Z41.Z42 ). It is essential that this signal be the complement of the elementary logic signal, i.e. Z41.Z42, supplied by transistor TX431 to the node CN43 for an adequate operation. As a result, the signal available on the common emitter node CN43 is the sum of these elementary logic signals, i.e. (Z41.Z42) + ( Z41 + Z42 ). The potential at node CN43 is therefore quite constant, the current flows through TX431, when input signals Z41 and Z42 are at the high level, Z41 = Z42 = "1" or through TX432 when Z41 = "0" and/or through transistor TX433 when 242 = "0". On the right side of current switch 49, it may be necessary to shift the signals from other trees (not represented) to tree 41 for performance optimization. This shift is ensured by a diode-resistor combination D41-R42 and D42-R43 respectively for complementary or OUT OF PHASE input signals Z41 and Z42 . If the connections are short and the load light, said complementary input signals can be applied directly on the bases of TX432 and TX433. At the second level, in middle stage 45, a quite similar solution is adopted. On the left side, an AND gate is formed with input diodes D421, D422 and resistor R44, and its output is connected to the base of transistor TX421. The signal that is applied to the base of transistor TX421 is the logical AND of input signals Y41 and Y42. On the right side of the tree, transistors TX422 and TX423 are connected in parallel and are directly driven by complementary input signals Y41 and Y42 . The logic signal in common emitter node CN42 is therefore the sum of the elementary logic signals so produced, i.e. Y41.Y42 + ( Y41 + Y42 ). The above explained concept can still be implemented at the first level, in bottom stage 44. The AND gate is formed by input diodes D411, D412 and resistor R45, while transistors TX411 and TX412 are paralleled to implement the OR dotting function. However, slight modifications may be necessary in some instances for voltage level adjustment. In that respect, a diode D43 is connected in series between the AND gate output and the base of transistor TX411, to have the output signal resulting from the ANDing of input signals X41 and X42, at two VBE's below VPP to avoid saturation problems in translators 42 and 43. A resistor R46 is connected between said base and the ground. The global logic function F4 available at circuit output node T41 (or T42) is given by F4 = X41 . X42 . Y41 . Y42 . Z41 . Z42. Input diodes that are used to improve the logic capability of the logic tree, are made of PN diodes or from diode connected NPN transistors but they can be replaced by Schottky Barrier Diodes (SBDs) as represented in Fig. 4 to further improve the circuit speed. Resistors R42 and R43 are chosen high enough to avoid a signal degradation due to a large Fan-Out of the previous DDCCS circuits driving the input diodes It should be noticed that DDCCS circuit 40 operates with the same small swing signals and with the same high speed as for the traditional DCCS circuit 30 of Fig. 3. In some instances, due to problem of potential saturation, the input diodes must be used only on the second and third levels of the tree 41. Unlike input diodes, others diodes (e.g. SBD1) are used as shifter devices, they aim to ensure high driving capability on the circuit output signals which are always transmitted after an emitter-follower shifter circuit. The improved DDCCS circuit of Fig. 4 exhibits significant advantages when compared to the circuit of Fig. 3. New logic functions have been added on the input transistors at the minor expense of a low-power consumption and small additional delay. The concept may be generalized to have more inputs. For example, to increase the number of inputs at the third level, it suffices to add an input diode, e.g. D433, to the AND gate and the corresponding NPN transistor, e.g. TX434 (not represented), in parallel with transistors TX432 and TX433. Note also that transistors TX432 and TX433 that form an OR function between complementary input signals Z41 and Z42 can be located in previous DDCCS logic trees (not represented), as soon as the appropriate logic function is available at node CN43. Functionality can be assured down to 3.0 V minimum power supply at circuit level. The family may be operated from power supply values above this value, as well. For example, it can be operated from a 5V power supply. However, it is to be noted that power dissipation is proportional to the power supply value, but, compensated by the number of additional logic functions which can be implemented in a single DDCCS tree under 5 V. In addition, coupling several input diodes as shown in Fig. 4, an AND function is added for each top stage, which in turn, increases the complexity of permitted logic functions with an increased number of logic inputs. A tree without said input diodes would perform a three-input AND/NAND as shown in Fig. 3, which is the maximum number of inputs for the 3L-DCCS circuit family. Others advantages include an improvement in density, due to the implementation of more complex functions per book or macro, while still maintaining the high speed of the DCCS type of circuits. The voltage swing and the current source values are related to the VBE forward voltage of transistors (the voltage swing is around 0.5 VBE). It is remarkable to notice that the power-delay product is improved. It is difficult to evaluate this benefit, as it depends on the type of logic circuits or gates which are implemented. The circuit delay must be compared to the delay that would be obtained with other logic families. Innovative circuits may be derived from the basic circuit 40 of Fig. 4, to form an exhaustive library of circuits (or books). Two different embodiments in accordance with the present invention will now be detailed in conjunction with Figs. 5 to 7. As a first example, a four-input Exclusive OR (XOR) circuit 50 is shown on Fig. 5. In a conventional 3L-DCCS circuit technology, a XOR circuit would be limited to three inputs for the same reasons that those given above with regards to the 3L-DCCS circuit of Fig. 3 which performs a three-input AND/NAND function. The novel DDCCS circuit 50 according to the present invention permits to add at least a fourth input. According to the basic principle of operation, the four different combinations of the true and complement of two logic input signals are first ORed by emitter-follower connections of four different pairs of parallel connected NPN transistors. The four different combinations resulting therefrom are complex input signals, that are then selectively ANDed in two two-input AND gates before being applied to two differential pairs of transistors. This is effected in the top stage 56 of the logic tree 51 to perform a two-input XOR. The XOR function between the two other logic input signals, is realized at first and second levels on stages 54 and 55 of circuit 50 as in a conventional DCCS circuit. A detailed description is given below. Turning to the left side of circuit 50, parallel connected NPN transistors TX51 and TX52 driven by input signals Z51 and Z52 supply complex input signal Z51 + Z52 on their common emitter node. Similarly transistors TX53 and TX54 supply input complex signal Z51 + Z52 on their common emitter node. Those complex input signals are ANDed in the two-input AND logic gate comprised of diodes RD531, D532 and resistor R51, before being applied to the bases of transistors TX531 and TX533. Parallel connected NPN transistors TX55 and TX56 and transistors TX57 and TX58 respectively supply complex input signals Z51 + Z52 and Z51 + Z52 on their respective common nodes. Those complex input signals of the mixed type are ANDed in the two-input AND logic gate comprised of diodes D533, D534 and resistor RD52 before being applied to the bases of transistors TX532 and TX534. XOR circuit 50 is therefore comprised of two basic differential pairs of input transistors TX531 and TX532 on the left side, and TX533 and TX534 on the right side of circuit 50. When input signals Z51 and Z52 are equal, transistors TX531 and TX533 are "OFF" because one of the two combinations: Z51 + Z52 or Z51 + Z52 is equal to "0" and both combinations, Z51 + Z52 and Z51 + Z52 are equal to "1", while transistors TX532 and TX534 are "ON" to perform the XOR function. The arrangement of the OR function obtained by the dotting of the emitters driven by the appropriate combination of input signals, ensures that at the third level, only one transistor of each differential pair is "ON" at a time. The circuit of Fig. 5 can even be extended to a five-input XOR circuit with a two-input XOR function performed at the second level, when implemented with the same circuit as depicted at the third level in stage 56. The true circuit output signal available at node OUT is given by F5 = X51 ⊕ Y51 ⊕ Z51 ⊕ Z52. The XOR function between logic input signals X51 and Y51 is realized on first and second levels at stages 54 and 55 as in a conventional DCCS circuit. The output stages that are connected to the tree output nodes are not represented in Fig. 5. Such DDCCS XOR circuits can be used with low power supplies equal to or less than 3 4 V that are required for future technologies to integrate very high speed and very dense circuits for high performance computers. For example, a 18 bit parity tree can be implemented either with six DDCCS circuits (with two DDCCS circuit delays), or with 51 two-input NAND circuits (with 11 two-input NAND delays in a standard TTL/ECL logic, or finally with 9 DCCS circuits (with 3 DCCS circuit delays), should the 3L-DCCS circuits with a limited number of inputs be used. It is clear that the implementation of XOR circuits with standard logic gates requires a large number thereof. For a comparator, the use of DDCCS circuits with input diodes to increase the number of logic inputs reduces power and improves speed of operation. A two-input bit compare circuit is now given as a further example. The two-input bit compare circuit 60 shown in Fig. 6 is structurally and functionally very similar to circuit 50 of Fig. 5. In the present circuit there is only one pair of differential input transistors, say TX631 and TX632. The XOR of input signals Z61 and Z62 is performed at the third level in stage 66 with input diodes D631-632, resistor RD61 on the left side and input diodes D633-634, resistor RD62 on the right side of circuit 60. These diode/resistor combinations are used as "AND" gates, while the emitters of transistors TX631 and TX632 are dotted ensure the "OR" at common emitter node CN63 to sum up the elementary logic functions. The XOR of input signals X61 and Y61 is done as in a classical DCCS circuit at the first and second levels. The AND between the Z61 ⊕ Z62 and X61 ⊕ Y61 complex input signals is obtained by cascoding the pair of differential transistors TX631 and TX632 (which provides (Z61 ⊕ Z62) with the two transistor pairs of the lower stages, in a very similar way as achieved in circuit 50 in Fig. 5. The nine-bit comparator circuit 70 shown in Fig. 7 is built with one five-input AND gate 71, four DDCCS two-bit compare circuits, such as depicted in Fig. 6, referenced 72A to 72D, connected thereto through lead bundle 73 and one extra two-input DDCCS XOR circuit 74. Circuits 72A to 72D are identical to circuit 60 depicted in Fig. 6. Note that circuits 71 and 74 can be merged in the DDCCS logic circuit with two-input diodes on the second level and two input diodes on the third level.

Claims: An exclusive OR (XOR) logic circuit (50) of DCCS type to perform a XOR function and its complement value between IN PHASE (X51 ...) input signals and OUT OF PHASE input signals ( X51 , ...) to generate a circuit output signal (F) and its complement ( F ) at respective circuit output nodes (OUT, OUT ) including a first XOR circuit of a casode current switch type which is driven by first input signals (X51, Y51, X51 , Y51 ) and consists of an upper (55) and a lower (54) stage connected to form a bottom stage, wherein a current source connects the common emitter node of the lower stage (54) to a second supply voltage to supply a constant current (I0) therein; CHARACTERIZED IN THAT a second XOR circuit (TX531 to TX534) of a current switch type forms a top stage (56) that is cascoded and dotted with said bottom stage and consists of a pair of first and second input transistors (TX531, TX534) and a pair of third and fourth input transistors (TX532, TX533) connected in a differential amplifier configuration, so that said first and third input transistors on the one hand and said second and fourth transistors on the other hand form two independent branches and have their emitters tied together to form two common emitter nodes; the collectors of the second and third input transistors on the one hand and those of the first and fourth transistors on the other hand are connected to the respective circuit output nodes (OUT, OUT ); a pair of load resistors (RCT5, RCC5) connects said output nodes (OUT, OUT ) to a first supply voltage (VPP); and in that a third XOR circuit is connected to the second XOR circuit and consists of: a first logic circuit means (D531, D532, RD51, TX51 to TX54) which is connected to the base of said first and fourth input transistors and has a first AND gate (D531, D532, RD51) performing an AND function between two further ORed IN PHASE input signals (Z51 + Z52) and their ORed OUT OF PHASE input signals ( Z51 + Z52 ); and a second logic circuit means (D533, D534, RD52, TX55 to TX58) which is connected to the base of said second and third input transistors and has a second AND gate (D533, D534, RD52) performing an AND function between a first couple of ORed mixed IN PHASE/OUT OF PHASE signals of said further input signals ( Z51 + Z52) and a second couple of mixed IN PHASE/OUT OF PHASE signals of said input signals (Z51 + Z52 ) A two-bit compare logic circuit (60) of a DCCS type to perform a compare function between IN PHASE (X61, ...) input signals and OUT OF PHASE input signals ( X61 , ...) to generate a circuit output signal (F) and its complement value F at the circuit output nodes (OUT, OUT ) including a first XOR circuit of a cascode current switch type which is driven by first input signals (X61, Y61, X61 , Y61 ) and consists of an upper (65) and a lower (64) stage connected to form a bottom stage; wherein a current source connects the common emitter node of the lower stage (64) to a second supply voltage to supply a constant current (I0) therein; CHARACTERIZED IN THAT: an AND circuit (TX631, TX632) of the current switch type forms a top stage (66) that is cascoded and dotted with said bottom stage and consists of a pair of first and second input transistors (TX631, TX632) having their emitters tied together to form a common emitter node; the collectors of these input transistors are connected to the respective circuit output nodes; a pair of load resistors (RCT6, RCC6) connects said output nodes (OUT, OUT ) to a first supply voltage (VPP); and in that a second logic XOR circuit is connected to the AND circuit and consists of: first logic circuit means (D631, D632, RD61, TX61 to TX64) which is connected to the base of said first input transistor and has a first AND gate (D631, D632, RD61) performing an AND function between two further ORed IN PHASE input signals (Z61 + Z62) and their ORed OUT OF PHASE input signals ( Z61 + Z62 ) ; and second logic circuit means (D633, D634, RD62, TX65 to TX68) which is connected to the base of said second input transistor and has a second AND gate (D633, D634, RD62) performing an AND function between a first couple of ORed mixed IN PHASE/OUT OF PHASE signals of said further input signals ( Z61 + Z62) and a second couple of mixed IN PHASE/OUT OF PHASE signals of said further input signals (Z61 + Z62 ). The logic circuit of Claim 1 or 2 wherein said first supply voltage (VPP) is lower than 3.4 V."

Inventors: BOUDON GERARD, BOUDON, GERARD, Boudon, Gérard
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: H03K19
IPC codes: H03K19, H03M1, H03K3