MICROCOMPUTER

Abstract: The microcomputer comprises a ROM for storing a first instruction including a first byte, said first byte, and a second instruction including a second byte of the same code as said first byte of said first instruction; an instruction register (100); and means (14, 15, 16) for loading said second byte of said second instruction onto said instruction register (100) after said first byte of said second instruction has been decoded, and whereby a decode line L is shared among the similar instructions. Therefore, the area occupied by the decode lines L can be reduced on the chip enabling the size of the chip to be reduced. Further, the circuit for testing PLA of the microcomputer deals the microcomputer having PLA that includes an instruction code input unit and a timing signal input unit T, control signal output lines 4, a NAND-type decoder (1) consisting of a plurality of MOSFET's connected in series, a first precharge MOSFET (2) connected between the NAND-type decoder (1) and one potential of the power source, and a second precharge MOSFET (3) connected between the NAND-type decoder (1) and the other potential of the power source. The testing circuit is provided with means (21) which renders the first precharge MOSFET (2) conductive when the PLA is to be tested. Therefore, all of the wirings of the PLA circuit can be tested if the power source current is measured for all timings of the instruction set only, making it possible to shorten the testing time and to improve precision.

Description: TECHNICAL FIELD The present invention relates to a microcomputer comprising a memory for storing a first instruction having a first byte and a second instruction having a first byte and a second byte, an instruction register, a bus for connecting the memory and the instruction register and a decoder being connected to the instruction register for decoding the instruction read from the instruction register and issuing a timing control signal. The microcomputer will be referred to as MC in the following passages. BACKGROUND OF THE INVENTION Microcomputers and central processing units, respectively, for double operation code instructions are known from US 4 236 206 and US 4 346 437. For double code operations the code is latched on its appearance and afterwards decoded in order to process the instruction. As illustrated in Fig. 1, a conventional MC includes a data bus, an instruction register IR, a programmable logic array PLA, a data register D, a stack pointer SP, accumulators A,B, temporary registers TRB, TRC, a programmable counter PC, a ROM, and a RAM. The program counter specifies instructions stored in the ROM, the instructions being sequentially transmitted to the instruction register IR via the data bus. The PLA includes control output lines connected to internal registers and memories, etc., decodes instruction data transmitted from the IR, and delivers control signals such as an EM (enable memory) signal, a WACC (write accumulator) signal, an EROM (enable read only memory) signal, and a WM (write memory) signal. Those control signals are to switch on and off the intemal registers and the memories, and transfer the data stored in the RAM, accumulator, and ROM, etc., onto the data bus or write the data on the data bus in the RAM and accumulator, etc. The ROM stores instruction codes constituting instructions shown in Fig. 2 for example. An instruction "ADD A, #N", which is represented by an instruction code "1010, 1010" or "A, A", means that the contents stored in the accumulator A are added with #N or the contents of the second byte, and then, a result of the addition is stored into the accumulator. An instruction "ADD A, M", which is represented by an instruction code "0110, 0101" or "6, 5", means that the contents stored in the accumulator A are added with the contents stored in the RAM, and then a result of the addition is stored into the accumulator. The PLA 200 includes, as illustrated in Fig. 3 for exampie, a plurality of NAND decoders 1, precharge circuits 2, 3, and a sense amplifier 18. The NAND decoder 1 comprises enhancement FITS indicated by circles (O) and depression FETs indicated by crosses (x). The precharge FET 2 has its one terminal connected to one terminal of the NAND decoder 1 and its other terminal connected to the earth. The precharge FET 3 has its one terminal connected to the other terminal of the NAND decoder 1 and its other terminal connected to a power supply V DD . Those precharge FETs 2, 3 further have their gates connected to precharge signal lines PRC, respectively. In the following, operation of the PLA circuit shown in Fig. 3 will be described with reference to timing charts shown in Figs. 6(a), (b). In a time interval T1 of a timing cycle in an interval M1 of a machine cycle, the control signal EROM opens the output gate of the ROM to fetch out the instruction code stored in the ROM onto the bus and the control signal WIR opens the input gate of the instruction register to store the instruction code on the bus in the instruction register 100. When the instruction code fetched out from the instruction register IR 100 is "A, A", the NAND decoders 1 on decode lines L'1, L'3 become conductive in a machine cycle interval M2 to permit the sense amplifier 18 to input a signal "H" into the AND gate 6. Therefore, in a timing cycle interval T3 the control output signal EACC is generated on a control output signal line 4 via the AND gate 6, and in a timing cycle interval T4 the control output signal WACC is generated. Additionally, when the instruction codes is "6, 5", the AND decoders 1 located on decode lines L'2, L'4 become conductive in a machine cycle interval M2 to permit the sense amplifier 18 to input a signal "H" into the AND gate 6. Therefore, in the timing cycle interval T3 the control output signal ACC is generated on the control output signal line 4, and in a timing cycle interval T4 the control output signal WACC is generated. Here, the control signals such as EROM, WIR, PCUP, and the like illustrated in Fig. 1 are issued from a timing control circuit T/C. Such a conventional PLA circuit however as a problem that all instruction codes must be decoded to generate control signals in need of the execution of the instructions. One instruction code generally requires four decode lines on the average, for example the instruction "A, A" requires the decode lines L'1, L'3, the instruction "6, 5" requires the decode lines L'2, L'4, L'5, ... That is, about 100 instructions require 400 through 600 decode lines in all. If the width of a single decode line of PLA circuit which is formed on a semiconductor chip is assumed to be 10µ m upon integrating the PLA, the PLA has its entire width ranging from 4 to 7 mm and hence occupies a wide areas of the semiconductor chip, causing a problem of its being made large sized. A typical MC includes about output lines 4 of 100 through 200 for the control signals issued from the PLA. However, those control signal output lines 4 are connected to input/output gates of varieties of registers included in the MC but not connected to external output terminals. In view of the drawback of the prior art, the problem is to reduce the absolute number of decode lines keeping the same function as in the prior art. DISCLOSURE OF THE INVENTION The solution of the problem is a microcomputer as characterized in claim 1. Further improvements are disclosed in the dependent claims. A microcomputer includes in general varieties of instructions amounting in total about one hundred, some of which have a very similar format. For example, the foregoing instructions "Add A, #N" and "ADD A, M" are the same instruction of addition, and are different only in that the former allows data to be fetched from "N" or the second byte thereof or the buffer from a memory designated at "M". Such similar instructions very similar as such have almost common formats of control line signals and timing of the same. A microcomputer in accordance with the first embodiment of the invention comprises, in view of a feature of those similar instructions being common in operation timing, a memory for storing a first instruction including a first byte and a second instruction including a first byte and a second byte having the same code as that of the first byte of the first instruction, an instruction register and means for loading the second byte of the second instruction to the instruction register after decoding the first byte of the second instruction. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit block diagram illustrating a typical microcomputer (MC); Fig, 2 is a view illustrating formats of conventional instruction code; Fig. 3 is a circuit block diagram illustrating a conventional programmable logic array; Fig. 4 is a circuit block diagram illustrating a programmable logic array (PLA) of an embodiment according to the present invention; Fig. 5 is a view illustrating formats of instruction codes in the embodiment of Fig. 4; Fig. 6 is a timing chart illustrating the operation of the embodiment of Fig. 4; Fig. 7 is a logic circuit diagram illustrating a sense amplifier for use in the present invention; Fig. 8 is a logic circuit diagram illustrating a delay circuit for use in the present invention. BEST MODE FOR CARRYING OUT THE INVENTION In the following, a first embodiment of the invention will be described with reference to Figs. 4 through 8. Fig. 5 illustrates addition instructions "ADD A, #N" and "ADD A, M", the latter being analogous to the former addition instruction "ADD, A, M" previously described in the prior art. The former addition instruction "ADD A, #N" is not different from the conventional instruction code illustrated in Fig. 2. Against this, a first byte code 11 of a certain addition instruction "ADD A, M" is not different from the conventional one, but a second byte code 12 of the same possessesthe same code as the first byte code 13 of the analogous addition instruction "ADD A, #N". As illustrated in Fig. 4, a decode line L1 is a NAND decoder for a code "6, 5", that is, the addition instruction "Add A, M", which is operated in a machine cycle interval M1. Namely, when the first byte instruction code "6, 5" of the instruction "ADD A, M" is entered into an instruction register 106, the decode line L1 is activated (i.e., to a "L" level) to permit a "H" level signal to be entered into a delay circuit 17 via a sense amplifer 18. Here, the sense amplifier 18 and the delay circuit 17 are arranged as illustrated in Figs. 7 and 8. The delay circuit D issues a control signal WIR in the next timing cycle interval M2, T1 under the control of gates 14, 15, 16, to open an instruction register IR gate for thereby loading the instruction register IR with a second byte code "A, A" from a bus. Simultaneously, a control line signal WTRB is prohibited from being generated. When the decode line L1 decodes the first byte of the instruction as described above, the delay circuit 17, and the gates 14, 15, 16 load the instruction register IR with the second byte of that instruction. A decode line L4 corresponds to the decode line L5 shown in the circuit diagram of the conventional PLA of Fig. 3. It therefore issues a control signal EM in a timing cycle interval M1, T4. Decode lines L2, L3 correspond to L'1, L'3 involved in the conventional PLA circuit of Fig. 3, respectively, which issue a control signal EACC in a timing cycle interval M2, T3 and a control signal WACC in a timing cycle interval M2, T4. Thus the PLA of the embodiment according to the first invention illustrated in Fig. 4 can exhibit the operation timing of control signals illustrated in Fig. 6, as in the conventional PLA shown in Fig. 3. It should here be understood from a comparison of the decode lines in the PLA of Figs. 3 and 4 that the conventional decode lines L'2 and L'4 are not required but with L1 which is inexistent in the conventional case. Decode lines for control signals WTARC and ADD can also be reduced, although not illustrated in the PLA circuit diagram of Fig. 4. The MC includes substantially about 16 groups of analogous instructions such as ADD, ADC, SUB, SEE, OR, AND, FOR, INC, DEC, DIP, CPL, RRC, RLC, SAC, SLC, and the like. In a typical MC operational with about 8 bits, 5 decode lines on the average can be reduced among analogous instructions and about 80 decode lines as a whole can be reduced. Although in the above description the first and second byte instruction codes were shown as being commmon as an illustrative example, a combination of the second and third bytes may also be possible or with a replacement thereof for the machine cycles a combination of second and third machine cycles may be possible, as a matter of course. INDUSTRIAL APPLICABILITY According to the MC of the first invention, as described above, the number of decode lines can be reduced by employing analogous instruction codes as being common. That is, since the second byte of a certain instruction set among analogous instruction sets can intactly utilize a control signal output of the first byte of the certain instruction set being an analogous instruction of that instruction. Accordingly, if there is a decode line only for the first byte of the certain instruction set, then the intact use of that decode line in the analogous instruction enables the analogous instruction to be executed. Thus, the first invention, which employs a certain decode line for other decode lines, can reduce the occupation area of those decode lines on the chip compared with the prior MCs, which include for a different instruction code a corresponding decode line. To be concrete, 400 through 600 decode lines can be reduced by about 80 ones, and the area occupied by the PLA on the whole semiconductor chip area can be reduced by 10 through 20 %. The first invention can thus reduce the chip area greatly, keeping the same function of the device as in the conventional PLA circuit, and assuring very high industrial applicability.

Claims: A microcomputer comprising: a memory (ROM) for storing a first instruction having first byte code and a second instruction having a first byte code and a second byte code; an instruction register (100); a bus (BUS) for connecting said memory (ROM) and the instruction register (100); a decoder (300) being connected to the instruction register (100) for decoding the instruction read from the instruction register (100) and issuing a timing control signal, characterized in that the decoder (300) includes means (14, 15, 16, 17) for loading the second byte code of the second instruction to the instruction register (100) after decoding the first byte code of the second instruction which is read out on the bus (BUS) to said instruction register (100), and the first and second instruction are stored in the memory (ROM) in a way that the second byte of the second instruction has the same code as that of the first byte of the first instruction. Microcomputer according to claim 1, wherein said decoder (300) is a programmable logic array (PLA). Microcomputer according to claim 1 or 2, wherein said decoder (300) has a plurality of decoding lines (L1, L2, L3, L4). Microcomputer according to claim 3, wherein each of the decode lines (L1, L2, L3, L4) has a sense amplifier (18).

Inventors: TANAGAWA KOUJI, TANAGAWA, KOUJI, TANAGAWA, KOUJI, OKI ELECTRIC INDUSTRY CO., LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1989
Main classification: G06F9
IPC codes: G01R31, G06F11, G06F9