Code converter and encoder including the same

Abstract: A code converter includes: extraction means (31) for extracting a reference level from a binary-coded input signal, which is offset at the predetermined voltage level and varies arbitrarily with the same polarity as the voltage level; twos-complement conversion means(32), connected to the extraction means (31),for converting the reference level into a twos-complement value; and creation means (33), connected to said extraction means (31) and twos-complement conversion means(32) for adding an output signal of the twos-complement conversion means (32) and the binary-coded input signal, thereby producing a bipolar binary-coded output signal to which a polarity bit is added.

Description: The present invention relates to a code converter which is used for converting a unipolar binary coded signal into a bipolar binary coded signal, and more particularly, to a device which is intended to curtail the expansion of a circuit on a large scale, and stabilize the operation of the circuit. When a digital signal processing is effected in a digital form such as digital filtering of analog signal inputs, after a conversion from an analog signal to a digital signal has been carried out by an analog-to-digital converter, each sorts of digital processing is effected. In general, a digital signal output from an analog-to-digital converter is output as a unipolar binary coded signal which represents an absolute value of an analog input signal. However, as there are many cases where a bipolar binary-coded signal having polarity information is used to effect a digital signal processing as input information, a code converter is utilized in which an output of an analog-to-digital converter is converted into a bipolar binary-coded signal. In such a type of code converter, an input signal and a reference signal are compared to be divided into a first half cycle and a second half cycle, and after a twos-complement conversion is carried out with respect to one half cycle, the constitution of the converter is such that the resultant signals are combined to form a bipolar binary-coded signal. As a result, the structure of a circuit such as a comparator, and adder-subtracter, a twos-complement computing element and the like always becomes large scale in relation to the quantized accuracy of the input signals, and the problems of increased manufacturing costs still remain. In all kinds of data acquisition apparatus formed by prior-proposed types of code converters, such as an encoder device for producing composite picture signals in a picture processing system, the same increased cost problem occurs. In view of these problems, the present invention has been devised. DE-A-2 636 241 discloses a code converter having the features of the preamble of accompanying claim 1. This code converter is provided for converting a PAM (pulse-amplitude-modulation) input into a PCM signal, particularly for use with speech signals in a telephone system. According to the present invention, there is provided a code converter comprising: extraction means for extracting a reference level from a monopolar binary-coded input signal which is offset at said reference level; conversion means connected to said extraction means, for converting said reference level into a complement value; and adding means, connected to said extraction means and conversion means for adding the output signal of said conversion means and said input signal to produce a bipolar binary-coded output signal, characterised in that: said code converter is provided for use with a said input signal which varies alternately as an offset value of said reference level and which takes the value of said reference level at predetermined intervals; said extraction means performs said extraction in response to an extraction signal synchronized with said predetermined intervals at which said input signal takes the value of said reference level; and said conversion means is a twos-complement conversion means, such that by the addition by said adding means of the output signal of said twos-complement conversion means and said input signal, a polarity bit is included in said bipolar binary-coded output signal. As mentioned above, in the present invention, a reference level (reference voltage) extracted from an input signal is converted into a twos-complement value and then a bipolar binary-coded signal is produced by the addition of the above twos-complement value and the input signal. Therefore, since it is not necessary to discriminate a half cycle of the output signal, it is unnecessary to provide a comparator. Also, since it is preferable to effect conversion processing into the twos-complement value for the reference level only once (it is not necessary to effect the above processing for every quantization unit), this processing is simplified. As a result, as it is intended to decrease the scale of each constituent part, a bipolar binary-coded signal can be produced at the same time. For example, when applied to an encoder, it is noted that the scale of the circuitry of the encoder can be reduced, so it can be realized at a lower cost. Therefore, an embodiment of the present invention may provide a code converter which can convert a monopolar binary-coded signal into a bipolar binary-coded signal without leading to an increase in the scale of the circuitry. A development of the invention can provide an encoder device which contains a code converter as part of its structure. Reference is made, by way of example, to the drawings in which:- Figure 1 is a block diagram showing an example of a prior-proposed code converter; Fig. 2 shows a waveform of an input signal S1 in Fig. 1 in which +3 V is a reference level; Fig. 3 shows a waveform of a quantized digital signal S2 and corresponding binary codes; Fig.4 shows a waveform of a digital signal S6 output from a selector in Fig. 1, having first and second half cycles and corresponding bipolar binary codes; Fig.5 is a block diagram showing a principle of a code converter in accordance with the present invention; Fig.6 is a block diagram showing an encoder which uses the present invention; Fig. 7 is a conceptual diagram showing the operation of a code converter in accordance with the present invention; Fig.s 8 to 12 are diagrams showing a first embodiment of a code converter for 8 bits in accordance with the present invention; Fig. 8 is a block diagram showing the structure of a code converter of the present invention; Fig. 9 is a timing diagram showing the timing characteristics of principal portions of Fig.8; Fig. 10 is a connection diagram showing a concrete structure of an operation circuit in Fig. 8; Fig. 11 is a truth table common to each of FA0 to FA n-1 of the operation circuit 25 in Fig. 8; Fig. 12 is a waveform diagram showing the behaviour of an input signal a i , a bipolar binary coded signal C i and a leading edge timing of R′; Fig. 13 is a diagram showing a bipolar binary-coded signal when the reference level B 10 = 8 in case of 4-bit data (A); Fig. 14 is a diagram showing a bipolar binary-coded signal when the reference level B 10 = 16, in case of 5-bit data (A); Fig. 15 is a diagram showing a bipolar binary-coded signal when the reference level is B 10 = 128, in case of 8-bit data (A); Fig. 16 is a block diagram showing a second embodiment of a code converter in accordance with the present invention when applied to a picture signal encoder device. Before describing the preferred embodiments, a prior proposed code converter will be described with reference to Figures 1 to 4. Figures 1 to 4 are diagrams showing an example of the prior code converter. In Fig. 1, reference numeral 1 denotes an analog-to-digital converter which receives a unipolar analog value of an input signal S1. This input signal S1 is shown in Fig. 2, where the plus 3 V forms the boundary between a first half cycle, i.e., from +3 V to +6 V, and a second half cycle, i.e., from +3 V to 0 V. This +3 V is a reference voltage. The input signal S1 is quantized by a predetermined quantization unit to convert the quantized input signal into a digital signal S2 as shown in Fig. 3. A code converter 2 includes a comparator 3, an adder subtracter 4, a twos-complement calculator 5 and a selector 6 and outputs a digital signal S6 which is made bipolar-binary-coded. The comparator 3 compares a reference voltage REF equivalent to the above-noted + 3 V with a digital signal S2 and then discriminates a first half cycle and a second half cycle. The adder subtracter 4 subtracts a reference voltage REF from the first half cycle S2 and adds a reference voltage REF to the second half cycle S2 to produce a unipolar digital signal S4. The twos-complement calculator 5 produces a complement signal S5 which twos-complement-converts the second half cycle of the digital signal S4. In response to the output of the comparator 3, the selector 6 selects a unipolar digital signal S4 for the first half cycle and selects a complement signal S5 for the second half cycle. In the specification, the term two's complement or complement on two is represented by "twos complement". In Fig. 4, the value of the output voltage at the first half cycle corresponds to the value obtained by subtracting a reference voltage REF (equal to 3 V of a digital signal S2) from an output S2 of A/D converter 1, whereas that at the second half cycle corresponds to the value obtained when a reference voltage REF is added to the output S2 of an A/D converter 1, from the value which is twos-complement-converted. Therefore, a bipolar binary-coded digital signal is output from the code converter 2. And when applied to the input information of various kinds of digital signal processing, a desirable result is attained. Figure 5 is a block diagram showing a principle of a code converter in accordance with the present invention. In Fig. 5, the code converter of the present invention includes an extraction means 31, a twos-complement conversion means 32, and a creation means 33. The extraction means 31 is set to a predetermined voltage level for an offset voltage and the voltage level is extracted as a reference voltage REF to be held, from an input signal which is binary-coded to be able to arbitrarily change a polarity of the voltage level. The twos-complement conversion means 32 converts the extracted reference voltage into a twos-complement value. The output signal of the twos-complement conversion means 32 and the above-noted binary-coded input signal are added to correct the offset voltage and the creation means 33 produces a bipolar binary-coded output signal to which a polarity bit is added. Fig. 6 is a block diagram showing an encoder in accordance with a development of the invention. In Fig. 6, a video signal is input to an analog-to-digital converter 35 to produce a binary-coded signal. The binary-coded signal is input to a code converter 36, which outputs a bipolar binary-coded signal and the output of the code converter 36 is sent to a digital processing unit 37 to digitally process the input signal. The output of the digital processing unit 36 is input to a digital-to-analog converter 38 and then sent to a display unit 39 such as a cathode ray tube. As described above, the encoder device has a conversion circuit which converts a binary-coded signal, such as at least a color difference signal and a luminance signal into a respective bipolar binary-coded signal. The encoder device synthesizes each converted signal to produce a composite picture signal. Thus, the conversion circuit includes the above-noted code converter which does not necessitate a comparator and processing the conversion into a twos-complement is needed only once. As a result, the processing is simplified and the scale of each component is remarkably diminished and the scale of the circuitry in the encoder device is accordingly reduced. Fig. 7 is a functional diagram showing the operation of a code converter in accordance with the present invention. In Fig. 7, a three-bit binary code is input into a latch 41 which receives a sampling timing signal, to produce a reference value. The reference value signal and the three-bit binary code are input to a twos-complement calculation unit 42 to produce a four-bit output with bipolar bits. Figures 8 to 12 are diagrams showing a first embodiment of a code converter in accordance with the present invention applied to a code conversion of eight-bit data. The number of bits is, of course, not limited to eight. In Fig. 8 explaining the structure of a code converter, the code converter 10 includes an input buffer 13, a latch circuit (extraction means) 22, a calculation circuit 25, an output buffer 28, and a timing circuit 29. The input buffer 13 includes two 4-bit flip-flops 11 and 12, the latch circuit 22 includes eight flip-flops 14 to 22, and the calculation circuit 25 includes two 4-bit calculation units 23 and 24. The output buffer 28 includes two 4-bit flip-flops 26 and 27, and the timing circuit 29 synchronizes an extraction timing signal R which is input from outside by means of a clock signal CK to produce a synchronization extraction timing signal R′. In Fig. 8, a i denotes each binary-coded input signal from an external analog-to-digital converter (where i = 1 to 8), b i a reference level signal showing a reference voltage, c i an output signal which is bipolar-binary-coded, XCK a quantized timing signal from outside which is synchronized with a quantized frequency of an input signal a i , and a an external clear signal CLR. Figure 9 is a timing chart of the circuit in Fig. 8. The output of a selector 6 (Fig. 1), flip-flops 11, 12 and calculation unit 23, 24 are shown together with the signals a i , b i and c i . Figure 10 is a connection diagram showing a concrete structure of an operation circuit 25 which is formed by the above-noted two 4-bit calculation units 23 and 24. In Fig. 10, the operation circuit 25 is formed by 1-bit full adders FA 0 to FA n-1 by a bit number of a i . Signals A 0 to A n-1 (that is, a i signals passed through an input buffer 13) are input into each A input of FA 0 to FA n-1 , (that is, a i signals passed through an input buffer 13), and signals B 0 to B n-1 (that is, bi signals from a latch circuit 22) are input into each B terminal. To a CI terminal of FA 0 an "H level" potential (for example, a power source voltage) is normally input as a signal C 0 . An output logic C 0 ′ according to a truth table described later, is obtained from a C 0 terminal of FA 0 and the output logic signal C 0 ′ is input into a CI terminal of the next highest adder, i.e., FA 1 , as a signal C 1 . In the same manner each C 0 terminal from FA 1 to FA n-1 is connected in series to each CI terminal of the next highest adder. The A 0 and B 0 terminals in Fig. 10 corresponds to A 1 and B 1 of the 4-bit calculation unit 24 in Fig. 8, and A n-1 and B n-1 correspond to A 4 and B 4 of the 4-bit calculation unit 23. Fig. 11 is a truth table common to each adder FA 0 to FA n-1 forming the operation circuit 25 in Fig. 8. The operation circuit 25 effects an operational processing of each b i output from the latch circuit 22 (that is, the potential at which a i is latched by a timing of R′ to be held therein and is inverted and output from each XQ terminal) according to the truth table as shown in Fig. 11. The operation circuit 25 effects a first operational processing for converting b i as a reference voltage into a twos-complement value and a second operational processing for adding the operated twos-complement (a twos-complement concerning b i ) and a i value input to each B terminal to zero-correct the reference voltage (i.e., corresponding to the offset value of a i ). The resultant value of such operational processings is output as the bipolar binary-coded output signal, from terminals S 1 to S 4 of the 4-bit operation unit 24 and terminals S 1 to S 4 of the 4-bit operation unit 23. Therefore, the operation circuit 25 together with the latch circuit 22 functions as a twos-complement conversion means and a creation means. In such a structure, when the a i signal from an analog-to-digital converter is input as a variation of potential as shown in Fig. 12, that is, when the a i signal varies alternatively as an offset value of a predetermined potential level, for example, (+128), since the offset value coincides with a build-up timing of R′, the offset value is loaded into each flip-flop 14 to 21 of the latch circuit 22 using this timing. To explain more concretely, the a i signal which is loaded into the input buffer 13 in accordance with a quantized timing signal XCK, is added to each D input of each flip-flop 14 to 21 in the latch circuit 22. Each flip-flop 14 to 21 loads the D input (i.e., a i ) inside by a build-up timing of R′ from the timing circuit 29 to hold it until a leading state of a next R′ and at the same time outputs it from the XQ terminal as the b i value corresponding to the reference voltage. That is to say, the latch circuit 22 is offset at a predetermined voltage level (in this case (+128)) and extracts the voltage level (+128) as the value (b i ) corresponding to the reference voltage from the binary-coded input signal (a i ) which varies arbitrarily (in this case, varies alternatively) with the same polarity as the voltage level (in this case, + side) and holds the value. On the other hand, the a i value loaded into the input buffer 13 is also applied to the A input of the operation circuit 25. The b i signal from the latch circuit 22 is input to the B input of the operation circuit 25 and the operation circuit 25 performs a twos-complement of 2'b i of this b i , adds the a i value applied to the A input and the 2'b i value and then outputs it through the output buffer 28 as a bipolar binary-coded signal C i which makes C 8 a polarity bit (Xp which will be explained later). The above-described operation of the twos-complement of the b i and the reason why this twos-complement (2'b i ) and the a i are added, will be described next. In general, a positive integer X from 0 to 2 n-1 is expressed by the following equation (1) in accordance with a natural binary code {x 1 , x 2 , x 3 ----- x n } of n bits: Now, suppose that natural binary codes A and B of L bits are, respectively, A: {a 1 , a 2 , a 3 ----- a ℓ } B: {b 1 , b 2 , b 3 ----- b ℓ }, A and B are expressed as follows: With regard to A and B, suppose that B is a dynamic value (not a fixed value) and when the operation (A - B) is carried out, it can be effected in the following manner. That is, when a negation of B is expressed by the expression B: { b 1 , b 2 , b 3 ----- b L }, a twos-complement B' on B becomes Since generally (A - B = A + B′), where C(2): binary Xp: a polarity bit Xp = 0 (A ≧ B) Xp = 1 (A < B) Therefore, (C = A - B) is where C(10): decimal The answer C(10) of the operation (A - B) is obtained as a bipolar binary code of a twos-complement representation which makes Xp a polarity bit. The following shows three examples of C required when the bit number of A and the value of B vary, respectively. Fig. 13 shows an example when the reference level (B) is B 10 = 8, in the case of 4-bit data (A). Fig. 14 shows an example when the reference level (B) is B 16 = 16, in the case of 5-bit data (A). Fig. 15 shows an example when the reference level (B) is B 10 = 128, in the case of 8-bit data (A), which corresponds to the embodiment of the present invention. As shown in Fig. 15 concerning an embodiment of the present invention, the value of Ci in the case of a i = (128) becomes {00000000} and when the value a i takes another voltage, for example, a i = (253), the value of C i becomes {01111101}. When the value a i takes still another voltage, for example, a i = (2), the value of C i becomes {10000010}. In this way, the value of C i (which is bipolar binary-coded) with respect to C 0 to C 7 , (when C 7 is X p ) which makes X p a polar bit, can be obtained. Therefore, the converter is improved on and since a conventional twos-complement operational processing of every quantized unit of input signals is not necessary and a comparator for discriminating the polarity is also unnecessary, a simplified code converter can be attained. As a result, and as the reduction of cost is intended to realize, a code converter can be realized which can simply convert a binary-coded signal into a bipolar binary-coded signal. Figure 16 a block diagram showing a second embodiment of a code converter in accordance with the present invention and an example is shown in which a first embodiment of the code converter is applied to a composite picture signal encoder device (especially for the NTSC system) in a digital picture processing system. In Fig. 16, reference numeral 50 denotes an encoder device. The encoder device 50 includes a first, second and third conversion circuits 51, 52, and 53, a black signal generation circuit 54, digital low-pass filters 55 to 57, a encoder circuit 60, a digital band pass filter 61, a Y-BLK addition circuit 62, and a chrominance signal addition circuit 63. The first and second conversion circuits 51 and 52 convert binary-coded color difference (Blue-Yellow) and (Red-Yellow) signals into a respective bipolar binary-coded signal and the conversion circuits 51 and 52 include the code converter 10 of the first embodiment. The second conversion circuit converts a binary-coded luminance signal Y into a bipolar binary-coded signal and includes the code conversion circuit 10. The third conversion circuit 53 includes a level conversion circuit. The black signal generation circuit 54 produces a black signal BLK in accordance with a composite synchronization signal C SYNC . Digital low-pass filters 55, 56 and 57 have a respective predetermined low-pass characteristic in correspondence with the frequencies of signals being passed. The encoder circuit 60 synthesizes two signals (that is, a (B-Y) signal and a (R-Y) signal) to produce a chrominance signal. The digital band pass filter 61 passes a specified frequency and has a predetermined pass characteristic in response to frequency components of a chrominance signal. The Y-BLK addition circuit 62 effects a digital addition of both a bipolar binary-coded Y signal passed through the digital low-pass filter 57 and a BLK signal. The composite picture signal addition circuit 63 digitally add the result of addition in the Y-BLK addition circuit 62 and a chrominance signal passed through the digital band pass filter 61 to produce a composite picture signal. In general, in a color picture processing system according to an NTSC (National Television System Committee) system, the picture information is transmitted by a composite picture signal which synthesizes both two color difference composite signals (B-Y) and (R-Y) and a luminance signal Y and the composite picture signal is produced by a picture processing of original pictures R, G and B output from a television camera. In conventional picture processing, an analog processing is generally used, but it is desired that a transition to digital picture processing be adopted from the point of view of stability of the circuit operation. As for an encoder device effecting these kinds of digital processing, the code converter 2 in Fig. 1 in place of the conversion circuits 51 to 53 in Fig. 16 has been conventionally used, but it is not desirable in terms of cost due to the increase in scale of the circuitry. On the contrary, according to the structure of an embodiment of the present invention, in comparison with a prior proposal (i.e., the code converter 2 in Fig. 1), since the encoder device is formed by the first to third conversion circuits 51 to 53 including a small-scale code converter 10 (as described in the first embodiment), an encoder device can be realized which has high stability and low cost.

Claims: A code converter comprising: extraction means (31,41) for extracting a reference level from a monopolar binary-coded input signal (a i ) which is offset at said reference level; conversion means (32,42) connected to said extraction means (31,41), for converting said reference level into a complement value; and adding means (33), connected to said extraction means (31,41) and conversion means (32,42), for adding the output signal of said conversion means and said input signal (a i ) to produce a bipolar binary-coded output signal (c i ) ; characterised in that: said code converter is provided for use with a said input signal (a i ) which varies alternately as an offset value of said reference level and which takes the value of said reference level at predetermined intervals; said extraction means (31,41) performs said extraction in response to an extraction signal (R') synchronized with said predetermined intervals at which said input signal takes the value of said reference level; and said conversion means (32,42) is a twos-complement conversion means, such that by the addition by said adding means (33) of the output signal of said twos-complement conversion means and said input signal (a i ), a polarity bit is included in said bipolar binary-coded output signal (c i ). A code converter according to claim 1, wherein said extraction means (31,41) comprises: an input buffer (13) for receiving said input signal (a i ) ; and a latch circuit (22) for latching said input signal (a i ) in response to said extraction signal (R'). A code converter according to claim 1, wherein said extraction means (31,41) comprises: an input buffer (13) for receiving said input signal (a i ) ; and a timing circuit (29) for synchronizing an extraction timing signal (R) input from outside by means of a clock signal (CK) to produce said extraction signal (R'). A code converter according to claim 2, wherein said input signal (a i ) is loaded from said input buffer (13) to said latch circuit (22) in response to each leading edge of said extraction signal (R') so as to have the value of said reference value, and is latched therein until the next leading edge of said extraction signal (R'). A code converter according to any preceding claim, wherein said code converter includes an operation circuit (25) which is arranged to receive said reference level (b i ) output from said latch circuit (22) and arranged to perform a first operational processing of converting said reference level (b i ) into a twos-complement signal, and a second operational processing of adding the twos-complement signal of the reference level (b i ) and said input signal (a i ) from an A/D converter to zero-correct said reference level. An encoder (50) used in a digital picture processing system, comprising: first and second conversion circuits (51,52) each including a code converter according to any preceding claim, for converting monopolar binary-coded color difference signals (B-Y, R-Y) into respective bipolar binary-coded signals; an encoding circuit (60) for synthesizing the outputs of the first and second conversion circuits (51,52) into a chrominance signal; a third conversion circuit (53,54,57,62) for processing a luminance signal (Y) by using a composite synchronization signal (C SYNC ) ; and an addition circuit (63) for adding the outputs of the encoding circuit (60) and the third conversion circuit (53,54,57,62) to produce a composite picture signal.

Inventors: ABE MASATO, ASAMI FUMITAKA, ABE, MASATO, ASAMI, FUMITAKA
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H03M7
IPC codes: H04N9, H03M5, H03M7