Information processing apparatus and method

Abstract: An information processing apparatus executes a machine language instruction according to a microprogram controlling method. The apparatus comprises an instruction decoder (14) for decoding the machine language instruction; an operand controller (15) for receiving, from the instruction decoder (14), information about operands that are necessary in executing the machine language instruction, and fetching and holding the operands according to the information; and an instruction executing device (16) generating operand requests to the operand controller (15), obtaining the operands, and executing the machine language instruction under the control of a microprogram. Thus, the apparatus can execute a plurality of machine language instructions that respectively prescribe the same operation to be carried out on the different kinds of operands, under the control of a single microprogram irrespective of the differences of the kinds of the operands.

Description: The present invention relates to an information processing apparatus, and particularly to a microprocessor that operates under the control of a microprogram. Description of the Prior Art Figure 1 is a view schematically showing a construction of a conventional microprocessor based on the microprogram controlling method. The microprocessor processes machine language instructions accompanying plural kinds of operands such as register operands, memory operands and immediate operands. Operation of the microprocessor will be described with reference to the figure. A machine language instruction is input to an instruction decoder 1 from the outside and decoded in the instruction decoder 1 to provide an internal instruction. The internal instruction has an instruction format which is executable in the processor. The internal instruction is output to and stored in an internal instruction register 2. Generally, there are three kinds of operands, i.e., register operand, memory operand and immediate operand. If a source operand is a register, a field SR of the internal instruction register 2 holds the number of the register in a general register set 3. If a destination operand is a register, a field DR of the internal instruction register 2 holds the number of the register in the general register set 3. A field IMM of the internal instruction register 2 is a region for storing numeric data. If an operand is a memory operand, a field MA of the internal instruction register 2 holds the operand address in an external memory 4. A microprogram storing block 5 is a region for storing microprograms for executing internal instructions. Information as to the kind of instruction processing, among the decoding result of the instruction decoder 1 is sent, as a first address of a microprogram to be used, to the microprogram storing block 5. According to the sent address, respective microinstructions that constitute the microprogram are read from the microprogram storing block 5 to execute the internal instruction. The read microinstruction is stored in a microinstruction register 6. The microinstruction held in the microinstruction register 6 is input to a micro-decoder 7. The micro-decoder 7 decodes the microinstruction and, according to a result of the decoding, generates operand requests. According to the operand requests, operands needed for executing the machine language instruction are obtained on a local bus 8. Conventional information processing apparatuses such as the microprocessor explained above have problems to be described below. If the kinds of the operands or the kinds of the combinations of operands are different from each other, different microprograms should be prepared for respective cases even if the same kind of process is carried out. This may increase the number of steps of a microprogram, and push up labor and time necessary for developing the microprograms. Further, the size of the microprogram storing block 5 is increased. And the increased size of the microprogram storing block 5 increases an access time and deteriorate a machine language instruction processing efficiency. In addition, power consumption will be increased. That is, in the case where operand is a register in the general register set 3, a microprogram that carries out the following process is used: the number of the register that is held in the field SR or DR of the internal instruction register 2 is selected by a selector 9 and sent to the general register set 3. According to the sent register number, the register is selected among registers in the general register set 3. Then, the contents of the selected register are output to the local bus 8, or data on the local bus 8 are stored in the selected register. If operand is a source memory operand in the external memory 4, a microprogram that carries out the following process is used: the address that is held in the field MA of the internal instruction register 2 is selected by the selector 9, and the external memory 4 is accessed according to the address to provide data to a memory data register (MDR) 10. The data thus stored in the MDR 10 is output to the local bus 8. If operand is an immediate operand, a microprogram is used to output data stored in the field IMM of the internal instruction register 2 to the local bus 8. In carrying out, for example, the following same adding process, different microprograms should be prepared for respective combinations of operands. That is, if two operands are both register operands, the following two-step microprogram should be prepared: -, YS, ASL, YD, ADL ADD, _, _, ALU, YD, END if one operand is a register operand and the other operand is an immediate operand, the following two-step microprogram should be prepared: -, IMM, ASL, YD, ADL ADD, _, _, ALU, YD, END and if one operand is a memory operand and the other operand is an immediate operand,the following three-step microprogram should be prepared: -, IMM, ASL, MDR, ADL ADD, _, _, ALU, MDR _, _, _, _, _, MW, END The representation YS, ASL, e.g.,in the first microinstruction of the microprogram (1) corresponds to a process of transferring the content of a register whose number is stored in the field SR of the internal instruction register 2 to a register ASL 11 via the local bus 8. The representation YD, ADL corresponds to a process of transferring the content of a register whose number is held in the field DR of the internal instruction register 2 to a register ADL 12 via the local bus 8. The representation ALU, YD in the second microinstruction corresponds to a process of transferring a result of the addition from an ALU 13 to the register whose number is held in the field DR of the internal instruction register 2, via the local bus 8. The above mentioned problems of the conventional devices are overcome by the processor described by H. Matoumoto et al. in "A high performance architecture for variable length instructions" (Systems and Computers in Japan, no. 3, May-June 1985, pages 19-28, Washington DC, USA) which uses a single microprogram for each type of process to be carried out regardless of which type of operands it requires. SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus which can solve the above-mentioned problems of the conventional apparatuses. The apparatus of the present invention is constituted to use a single microprogram for executing plural machine instructions which require the same kind of process to be carried out, but have different kinds of operands, respectively. The apparatus of the present invention remarkably reduces labor of a micro programmer , and has a high processing speed. In order to accomplish the object, an information processing apparatus of the present invention comprises all the features of appended Claim 1. These and other objects, features and advantages of the present invention will be more apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a microprocessor using microprogram controlling method according to a prior art; and Fig. 2 is a block diagram showing a microprocessor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 2 is a block diagram showing a microprocessor according to an embodiment of the present invention. As shown in the figure, the microprocessor of the embodiment comprises an instruction decoding block 14, an operand controlling block 15 and an instruction executing block 16. The instruction decoding block 14 has an instruction decoder 17 and a selector 18. The operand controlling block 15 has four operand information holding means 19(0) to 19(3), a controller 20, a general register set 21, a memory address register (MAR) 22, a selector 23, buffers 24 and 25, an inverter 26, etc. The instruction executing block 16 has a microprogram storing block 27, a microinstruction register 28, a micro-decoder 29, an ASL 30, an ADL 31, an arithmetic-logic unit (ALU) 32, etc. Each of the four operand information holding means 19(0) to 19(3) comprises a 32-bit section AP for holding an operand address, a 32-bit section DP for holding operand data, and a plurality of bits GR, DV, AV, A and W/R for holding information concerning the kinds or the attributes of an operand stored in the operand information holding means. Meanings of the bits GR, DV, AV, A, and W/R will be explained. If a value of the bit GR is 1, the operand information holding means in question is holding information about a register operand and, the section AP is holding the number of the register in the general register set 21. If the value of the bit GR is 0, the operand information holding means in question is holding information about a memory operand or an immediate operand. If a value of the bit DV is 1, the section DP of the operand information holding means in question is effectively holding data of the operand. If the value of the bit DV is 0, the section DP is not holding the data effectively. If a value of the bit AV is 1, the section AP of the operand information holding means in question is effectively holding an address in an external memory 33 or a register number in the general register set 21, of the operand. If the value of the bit AV is 0, the section AP is not holding such data effectively. If a value of the bit A is 1, access to the external memory 33 is requested in processing the operand held in the operand information holding means in question. If the value of the bit A is 0, there is no such an access request. If a value of the bit W/R is 1, the operand to be held in the operand information holding means in question is to be read from the external memory 33. If the value of the bit W/R is 0, the operand held in the operand information holding means in question is to be written to the external memory 33. The contents of the bits W/R, A, GR, AP and DP are set by the instruction decoder 17. Content of the section AP is set through the selector 18. Operation of the microprocessor of the embodiment with the above-mentioned composition will be described. A machine language instruction is read out of the external memory 33, input to the instruction decoder 17 and decoded in the decoder 17. Among the results of the decoding, data of operands used in processing the machine language instruction are sent to the operand controlling block 15. Information 101, among the results of the decoding by the instruction decoder 17, concerning the kind of the process is sent to the microprogram storing block 27. The information 101 indicates the address of the microprogram, in the microprogram storing block 27, to be used for executing the machine language instruction. The operands to be used in executing a machine language instruction fall among three kinds, i.e., memory operand, register operand and immediate operand. The operand controlling block 15 stores the operands to be used in the execution of the machine language instruction which has been input in the instruction decoder 17, among the operand information holding means 19(0) to 19(3), irrespective of the kinds of the operands. The operand information holding means which are not in use at that time are sequentially selected from the four operand information holding means to store the respective operand information. The selector 23 stores information about the sequence of the selection. The machine language instruction is executed according to a pipeline process. Usually, when a machine language instruction is decoded by the instruction decoder 17 and the result of the decoding is about to be stored among the operand information holding means 19(0) to 19(3), several ones of the operand information holding means are already in use to hold operand data of machine language instructions which have been decoded before and are being executed at the moment. Operands which are needed in executing a machine language instruction are obtained on a local bus 34 by sending a selecting signal 102 for selecting operand information holding means from the instruction executing block 16 to the operand controlling block 15, irrespective of the kinds of the operands. Among the decoded results, result 103 is an information that indicates whether or not the operand is a register in the general register set 21. The information 103 is set in the bit GR of the operand information holding means selected for holding data of the operand. If the operand is a register in the general register set 21, register number IGR of the register in the general register set 21 is selected among the decoded results by the selector 18 and set in the 32-bit operand address storing section AP of the selected operand information holding means. If the operand is a memory operand in the external memory 33, information about the operand address (111) in the external memory 33 is input in the selector 18 via an OBUS 35. Then, the address is selected by the selector 18 and stored in the section AP of the selected operand information holding means. Namely, an output 104 of the selector 18 indicates an address of the operand in the external memory 33, or a register number in the general register set 21. When a data is set in the section AP of an operand information holding means, a value 1 is simultaneously set in the bit AV of the operand information holding means by the instruction decoder 17. At this time, if the operand is a memory operand requiring access to the external memory 33, a value 1 is set in the bit A of the operand information holding means by a signal 105. If the operand is an immediate operand, immediate data (Imm) 106 among the decoded results is set in the 32-bit operand data storing section DP of the operand information holding means via the OBUS. And a value 1 is set in the bit DV. In this way, the decoded results are set among the operand information holding means. Then, the controller 20 operates as described below and judges whether or not the machine language instruction decoded in the instruction decoder 17 uses a memory operand. If it uses a memory operand, the memory operand is fetched. The controller 20 checks the bits A and W/R of the operand information holding means which have been selected newly to store the data from the instruction decoder 17 . If the value of the bit A of an operand information holding means is 1 and the value of the bit W/R of the same is 1, the controller 20 judges that there is a reading request to the memory and fetches the memory operand. Namely, the controller 20 outputs an address strobe signal 107 and starts memory access according to the operand address transferred to the MAR 22 from the section AP of the operand information holding means. Memory data that was thus read from the external memory 33 is stored in the section DP of the operand information holding means. At the same time, the bit DV is set to 1 and the bit A to 0. By virtue of the four operand information holding means 19(0) to 19(3), a microinstruction can get the requiring operands only by sending a selecting signal 102 for selecting operand information holding means to the operand controlling block 15. After the input of the selecting signal 102, irrespective of the kinds of the operands, the operand controlling block 15 outputs operands required by the microinstruction to the local bus 34. Similarly, only by sending the selecting signal 102 for selecting the operand information holding means to the operand controlling block 15, a result of execution of the microinstruction is stored in a correct area, whether it may be an area in the external memory 33 or a register of the general register set 21. Namely, upon the reception of the source operand request from the microinstruction held in the microdecoder 29, the operand controlling block 15 selects one of the operand information holding means according to the selecting signal 102. The selection is carried out by the selector 23 in the operand controlling block 15. A value of the signal 102 for selecting an operand information holding means sent from the microinstruction in the micro-decoder 29 is determined depending only on the kind of the process and what order the selecting signal 102 occupies among such selecting signals that are generated in the execution of the microprogram corresponding to the machine language instruction, and it does not directly specify one of the operand information holding means. Namely, to which operand information holding means corresponds the indirect specification of the microinstruction depends on the storing order of respective operand information that have been obtained by decoding the machine language instruction, among the four operand information holding means 19(0) to 19(3). The selector 23 stores information about the storing order, and it selects based on this information, the operand information holding means that corresponds to the indirect specification from the microinstruction. From the operand information holding means thus selected, the operand required by the microinstruction is output to on the local bus 34. Namely, when the information held in the selected operand information holding means relates to an external memory operand or an immediate operand, a value of the bit GR of the selected operand information holding means is 0 so that the gate 24 is closed and the gate 25 opened. Through the gate 25, the contents of the section DP of the selected operand information holding means, that is, the external memory operand or the immediate operand, in this case, is obtained on the local bus 34. If the information held by the selected operand information holding means relates to a register operand, the bit GR of the selected operand information holding means has the value 1 so that the gate 24 is opened and the gate 25 closed in this case. Through the gate 24, the content of a register which has been selected among the general register set 21 according to the register number information stored in the section AP of the selected operand information holding means, is output to the local bus 34. In this case, the value 1 of the bit GR is used as a signal 108 to start the above-mentioned selection of a register. With the above-mentioned arrangement and control, a microinstruction can carry out its process on operands without concerning the kinds of the operands. In other words, to execute a plurality of machine language instructions which correspond to the same kind of process but use different kinds of operands respectively, only one microprogram is sufficient to be prepared. This will be explained with reference to an example of carrying out an adding process similar to the one explained in connection with the prior art. In the microprocessor according to the embodiment of the present invention, the adding processes on different kinds of operands are carried out by one microprogram comprising the following two microinstructions: -, DP1, ASL, DP2, ADL ADD, _, _, ALU, DP2, END In the process defined by the micro program (4), sum of a source operand held in the section DP of an operand information holding means specified indirectly by DP1 and source operand held in the section DP of an operand information holding means specified indirectly by DP2 is operated in the ALU 32, and the result of the summation is stored in the section DP of the operand information holding means specified indirectly by DP2. The operands are indirectly specified by the names DP1 and DP2, and there is no representation which is dependent of the kind of an operand. Therefore, irrespective of the kinds of operands, the above-mentioned microprogram can carry out the adding process. And a result of a process is set in a due area as described below. For example, according to the microinstruction in the second line of the adding process (4) mentioned in the above, a result of the operation in the ALU 32 is stored in the section DP2 of the operand information holding means designated by DP2. Further, if the bit A of the operand information holding means designated by DP2 is 1, the result is stored in a memory cell whose address is set in the section AP of the same operand information holding means. While, if the bit GR of the operand information holding means designated by DP2 is 1, the result is stored in a register in the general register set 21 whose number is set in the section AP of the same operand information holding means. When the bit GR of the operand information holding means designated by DP2 is 1, the general register set 21 is specified by the signal 108 so that the result from the ALU 32 is passed through the local bus 34 and set in a register which is specified by signal 109 from the section AP of the operand information holding means. The signal 109 indicates a number of a register in the general register set 21. After the completion of the execution of a microprogram, the controller 20 checks the bits A and W/R of the operand information holding means which are in use for holding operand data of the machine language instruction under execution controlled by the microprogram. And if there is an operand information holding means in which the bit A has the value 1 and the bit W/R has the value 0, the controller 20 generates an address strobe signal 107 to write a value set in the section DP of the operand information holding means in a destination region of the memory 33, using a value set in the section AP as an access address to the external memory 33. In this way, by providing the operand controlling block with a controller, a predetermined number of the operand information holding means, etc., the instruction executing block is no longer needed to concern the kinds of operands. Namely, the operands controlling block acts as a buffer to prevent the instruction executing block from being influenced by the difference of the kinds of operands. Therefore, a plurality of machine language instructions differing only in the kinds of operands used by them can be executed by a common microprogram, thus the total size of microprograms is remarkably reduced compared to the prior art technique. In addition, labor of a microprogramer can greatly be reduced, and an area of a ROM for storing microprograms can also be reduced. As a result, power consumption is reduced, an access time to the ROM is reduced and a processing speed is improved. Although the embodiment has used four operand information holding means, the number is generally determined according to the maximum number of operands to be used for one machine language instruction and processability. Namely, it will be useless to provide the operand information holding means in the number more than necessity. However, if it is too few, troubles such as the deterioration of process efficiency or the processing impossibility may occur. Therefore, an optimum number, in the meaning described above, of the operand information holding means shall be provided. This number can be easily obtained, e.g., by a simulation. While the invention has been described in its preferred embodiment, it is to be understood that the words that have been used are words of description rather than limitation and that various changes and modifications may be made within the purview of the appended claims. For example, it is possible to prepare in each operand information holding means, two address parts for holding memory address and register number, respectively.

Claims: An apparatus for executing instructions comprising: an instruction decoder (14) for decoding a machine language instruction in sequence to generate decoded signals; a microprogram storing block (27) connected to said instruction decoder (14) for storing microprograms and outputting microinstructions in sequence in accordance with said decoded signal; a microinstruction register (28) connected to said microprogram storing block (27) for holding microinstructions; a micro-decoder (29) connected to said microinstruction register (28) for decoding a microinstruction in sequence in order to generate control signals for executing said microprograms; an arithmetic logic unit (32) connected to local buses (34) for executing microinstructions by the use of operand provided on said local buses (34) in accordance with the microinstruction being executed; said apparatus characterized in that said instruction decoder generates said decoded signal comprising a first decoded signal consisting of information about a plurality of operands and a second decoded signal indicative of a microprogram executable using said operands which can be obtained in accordance with said information, said information including either an immediate operand, or an operand address or a register number; and in that said apparatus comprises an operand information holding means (19(0) - 19(3)) is connected to said instruction decoder for receiving and storing said information about operands from said instruction decoder, said operand information holding means (19(0) - 19(3)) being capable of storing items of said information about a plurality of operands including an immediate operand and an address of a memory at the same time; a controller (20) is connected to said operand information holding means (19(0) - 19(3)) for providing operands on said local buses (34) by the use of said information; and a selector (23) is connected to said operand information holding means (19(0) - 19(3)) and said micro-decoder (29) for receiving a control signal from said micro-decoder (29) and controlling said operand information holding means (19(0) - 19(3)) to selectively output to said controller (20) the items of said information for executing the microinstructions decoded by said micro-decoder (29). The apparatus as claimed in claim 1, wherein sais operand information holding means (19(0) - 19(3)) stores a first information bit, for each item of said information, indicative of whether a corresponding operand is stored in a general register. The apparatus as claimed in claim 1, wherein said operand information holding means (19(0) - 19(3)) stores a second information bit, for each item of said information, indicative of whether the item of said information contains a valuable operand. The apparatus as claimed in claim 1, wherein said operand information holding means (19(0) - 19(3)) stores a third information bit, for each item of said information, indicative of whether the item of said information contains a valuable address of a corresponding operand. The apparatus as claimed in claim 1, wherein said operand information holding means (19(0) - 19(3)) stores a first information bit, for each item of said information, indicative of whether a corresponding operand is stored in an external memory.

Inventors: NAGATA MIYUKI, UTSUMI TOHRU, NAGATA, MIYUKI, UTSUMI, TOHRU
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G06F9
IPC codes: G06F9