Method of forming of an integrated circuit chip packaging structure

Abstract: An integrated circuit chip packaging structure com­ prising a substrate (10), preferably a semiconductor base substrate, a conductive layer (20) on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls (36) and gold bumps (34) connected to said conductive layer in said regions of said conductive layer, and a solder stop layer (22) on said conductive layer at least around said solder balls. The conductive layer further comprises wiring lines (30). Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus one metallization layer is pre­ vented. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus packaging of VLSI circuits is improved.

Description: The present invention relates to the packaging of electronic components on a carrier, preferably on a silicon carrier, and particularly to an integrated circuit chip packaging structure which comprises on a substrate different terminals for different packaging or connection techniques. Modern integrated circuit chips comprise a plurality of input and output terminals (I/O) which have to be arranged on the limited plane of the chip size. This increasing plurality of I/O terminals must be connected to surrounding electronic components. Commonly the chips are directly connected to other chips or electronic components or are arranged on a chip carrier or a substrate which comprises wiring lines for interconnecting the chips. The chip packaging structure of the present invention utilizes a multilayer substrate having several conductive planes separated by insulating layers. The substrates can be made of ceramic or silicon. Silicon carriers are preferred because of the similar manufacturing techniques in the chip production. Further, the thermal expansion coefficients are equal. A silicon substrate is disclosed in EP-A2-0 246 458 with further prior art references. A well known technique for connecting the chip to a carrier is the controlled collapse chip connection (C-4) technique which allows a plurality of I/Os close together. This technique is disclosed in the fundamental patents US-A-3 401 126 and US-A-3 429 040. For the application of this technique the corresponding terminals of the carrier have to be precisely prepared with a contact layer which limits the size of the contact ball (ball limiting layer) and provides sufficient contact with the terminals of the carrier. Additionally, a solder stop layer can be necessary if the terminal is connected to wiring lines on the surface of the substrate. Commonly the substrate comprises one additional metallization plane which only serves for the connection of the chip by the C-4 technique. Another well-known technique for packaging chips or carriers is the tape automated bonding (TAB) technique. TAB packaging involves the use of a web of material, generally called a carrier tape, to carry electrically conductive leads which provide connections between the chip and the outside world. An inner cluster of the conductive leads is bonded to the connecting pads of the chips or the substrate. The outer cluster is severed from the tape, and the outer leads of the tape/chip or tape/carrier combination, respectively, are bonded to conductive pads residing on an underlying circuit board. This method as well as the wire-bonding technique allows no such plurality of I/Os as the C-4 technique. Both techniques imply a bump which is usually made of gold or of gold/copper and formed on the integrated circuits or on the carriers. There are several processes just for the purpose of forming these bumps on conductors, and they are well known to those skilled in the art. The bumps are relatively thick in comparison with usual layer dimensions. Further, the bumps need a contact layer for the connection with the metallization plane in the chip or carrier. The bumps are deposited by an electro-plating process, which requires an uninterrupted conductive layer over the carrier surface for uniform current distribution during electro-plating. It is called seed layer. This technique is disclosed in the "Microelectronics Packaging Handbook", Tumula et al, 1988, van Nostrand & Reinhold Verlag (page 409 ff.). IBM Technical Disclosure Bulletin, vol. 25, no. 4, September 1982, p. 1952 discloses the use of photo-definable polyimide as a thin film solder dam when bonding integrated circuit chips with solder balls at the output pads to beam tape. IBM Technical Disclosure Bulletin, vol. 18, no. 10, March 1976, p. 3477 describes a technique for applying solder balls as small as 1/2 mil to a plastic substrate. The substrate is then bonded to a silicon device chip by low-temperature solder reflow bonding. In order to allow the packaging of integrated circuit chips having a high density of I/Os and to reduce manufacturing costs, carriers, preferably silicon carriers, comprising terminals for C-4 connections and TAB or wire-bonding connections are necessary. Thus, the invention as claimed solves the problem of providing an integrated circuit chip packaging structure and a method for manufacturing such a structure with high accuracy and a minimum of manu-facturing steps. Accordingly, the method of the invention is applied to a substrate which comprises at least wiring layers and insulating layers. Further, the surface of the substrate comprises a pattern of terminal vias arranged in an insulating layer and connected at least to one of the wiring layers. The substrate is well known in the art and may further comprise semiconductor layers in the case of a silicon carrier. Another kind of substrates serving as carrier are the well known ceramic substrates usually containing a plurality of wiring planes which interconnect the chips arranged on the carrier, and the chips with the outside world. Both substrates comprise on the surface terminals to be connected with one or more chips. These terminals are separated from each other by an insulating layer which additionally protects the layers below. Usually the terminals are manufactured by removing the insulating layer in the area of the terminals in order to expose conductive metal arranged below the insulating layer and to provide terminal vias. This way is advantageous for the present invention but other methods known in the art are possible to provide the terminals. On the surface of the substrate a conductive barrier layer is deposited which adheres on the surface, prevents oxidation and diffusion, and improves the contact and conduct capability it serves both as a barrier layer against the metal pads and a seed layer for electro-plating. This can be done by successively depositing chrome, copper and gold as known to a person skilled in the art. After the deposition of a polymeric layer on the conductive barrier layer a pattern of terminal vias corresponding to the pattern on the surface of the substrate is lithographically formed in this polymeric layer. This step can be realized with the same mask as the forming of the terminal vias in the insulating layer of the substrate. Thus, if the terminals of the substrate are processed as described above, no additional mask for the next lithograghical step is necessary. After this step the conductive barrier layer in the area of the terminals is exposed. In the following, after depositing a photoresist layer over the patterned polymeric layer a pattern is lithographically formed in said photoresist layer for the formation of board connection terminals and chip connection terminals. This pattern corresponds to the pattern of terminal vias in said polymeric layer on the surface of the substrate. The board connection terminals serve for the connection of the substrate with the outside world, e.g. a printed circuit board, and comprise a framing of photoresist layer surrounding the area where board connection terminals care to be formed. The framing can have a circular, rectangular or any other appropriate shape. The chip connection terminals which serve for connecting the substrate with a corresponding chip are defined by a cover of photoresist layer in the area of the terminals. After this step in the area of the board connection terminals the conductive barrier layer is exposed and surrounded by a photoresist layer framing, and in the area of the chip connection terminals the conductive barrier layer is covered by photoresist. Subsequently, the chip connection terminals are completed by growing bumps, preferably gold bumps, on the exposed barrier layer inside the framing. A common method for providing gold bumps having a sufficient extension is electro-plating. The framing around the exposed barrier layer serves for forming and providing a mushroomlike shape of the bumps. In the next step the exposed photopolymeric layer and the barrier layer are removed by well known processes, and the board connection terminals and the chip connection terminal are thus formed. With the removing of the barrier layer a part of the photoresist layer can be additionally removed, thus providing a photoresist layer with a reduced thickness. Additionally, according to another feature of the invention an interconnect wiring is lithographically formed in the photopolymeric layer. This wiring is lithographically formed together with the terminals and handled corresponding to the chip connection terminals. Thus, after the final removal wiring lines remain with a polymeric layer as a protection layer on the barrier layer which serve as conductors. Surprisingly, the method according to the invention combines C-4 and TAB technology on a carrier or substrate. Advantageously, the process steps are simplified and minimized. A further advantage is the application of lithographical steps. Thus, glass masks are used which additionally allow the employment of the invention on wafers having a diameter of 200 mm or more. It is still another advantage of the invention that only two different masks for providing the structure are used. Additionally, the first mask can be previously used in the manufacture of the substrate. Another advantage is the use of the barrier layer as a wiring layer which reduces the metal layers in the substrate without decreasing the density or the electrical behaviour. Surprisingly, only one layer, the barrier layer, is able to serve as a ball limiting layer, contact layer, wiring layer and seed layer for electro-plating. The invention is further applicable to chips, silicon carriers or ceramic carriers all serving as a substrate for the use of the invention. For a better understanding of the present invention, together with further objects and advantages, a preferred embodiment of the invention is described in the following with reference to the accompanying drawings which depict the sequence of steps by a cross-section of a part of the structure. Fig. 1 shows a part of a silicon carrier as a substrate 10 which comprises an insulating layer 12, e.g. polyimide, and a plurality of contact pads 14 of an metal layer. The surface of the contact pads 14 is formed as terminal vias 16, 18 in the insulating layer 12. The surface of the contact pads 14 and the insulating layer 12 forms the surface of the substrate 10 on which a conductive barrier layer 20 is deposited. For making the barrier-seed layer, respectively it is well known in the art to deposit chrome, copper and gold in this order by vaporization techniques. The deposition takes place over the complete wafer. In Fig. 2 a polymeric layer 22 of polyimide is arranged over the conductive barrier-seed layer 20 and removed by a lithographical process in the areas of the terminal vias. The thickness of the polyimide layer 22 is in the range of 0.7 to 1 µm. For masking the terminal vias the same mask which was used by forming terminal vias 16, 18 in the insulating layer 12 can be utilized. After the exposure of the barrier layer 20 on the surface of the contact pads 14 of terminal vias 16, 18 a photoresist layer 24 having a thickness in the range of about 6 to 10 µm is deposited over the complete wafer. Fig. 3 shows the photoresist layer after board connection terminals 26, chip connection terminals 28, and wiring lines 30 have been lithographically formed. The board connection terminals 26 comprise a framing 32 of photoresist layer 24 which surrounds an area of exposed barrier layer 20. The framing 32 is necessary to influence the growing of bumps 34 on the barrier layer 20 in the area of the board connection terminal 26 and gives the bump a mushroomlike form as depicted in Fig. 4. The chip connection terminals 28 as well as the wiring lines 30 comprise a cover of photoresist layer 24. The bumps 34 of Fig. 4 are of gold and deposited by electro-plating. In Fig. 5 the polyimide layer 22 and the barrier layer 20 are removed in the areas where these layers are not covered by the photoresist layer 24. With the removing of the polyimide layer 22 by a reactive ion etching process a part of the photoresist layer 24 is removed as well. As the photoresist layer 24 is much higher than the polyimide layer 22 the residue of the photoresist layer 24 serves for the subsequent wet etching process of the barrier layer 20 which exposes the surface of the insulating layer 12. Fig. 6 depicts the board connection terminal 26, the chip connection terminal 28, and the wiring line 30 after the final removing of the photoresist layer 24 by processes known in the art. The barrier layer 20 remains in the area of the terminals 26, 28 as a framing which serves at least in the area of the chip connection terminal 28 as a solder stop for the solder ball 36 which together with the chip is connected to the substrate by the C-4 technique. The barrier layer remains on the wiring line 30 as a protection layer.

Claims: A method of forming an integrated circuit chip packaging structure on a substrate (10) comprising at least wiring layers and insulation layers, and wherein the surface of said substrate comprises a pattern of terminal means (14) arranged in an insulating layer (12) and connected at least to one of said wiring layers, said method comprising the following steps in the following order: A. depositing a conductive barrier layer (20) on said substrate, which serves also as a seed layer for electroplating; B. depositing a polymeric layer (22) on said conductive barrier layer; C. forming a pattern of terminal vias (16, 18) in said polymeric layer that corresponds to said pattern of terminal means by lithographically defining said pattern of terminal vias and removing said polymeric layer in the area above said pattern of terminal means; D. depositing a photoresist layer (24) over said patterned polymeric layer; E. lithographically forming a pattern in said photoresist layer for the formation of board connection terminals (26) and chip connection terminals (28) corresponding to said pattern of terminal vias in said polymeric layer by forming a framing (32) of said photoresist layer surrounding the area where board connection terminals are to be formed and a cover of said photoresist above the area said chip connection terminals are to be formed; F. growing bumps (34) on said conductive barrier layer inside said framing by electroplating; G. forming said board connection terminals and said chip connection terminal after removing the exposed regions of said polymeric layer and said conductive barrier layer; H. finally removing the residue of said photoresist layer. The method of claim 1 wherein the lithographically forming step E further comprises forming a pattern in said photoresist above said insulating layer (12) for the formation of an interconnect wiring (30) and the removal of the exposed regions of said polymeric layer and said conductive barrier layer in step G forms said interconnect wiring. The method of claim 1 or claim 2 wherein said conductive barrier layer (20) is made by successively depositing chrome, copper and gold. The method of any one of the preceding claims 1 to 3 wherein said polymeric (22) layer comprises polyimide.

Inventors: GANSAUGE PETER DR, KREUTER VOLKER DIPL-ING, SCHETTLER HELMUT DIPL-ING, GANSAUGE, PETER, DR., KREUTER, VOLKER, DIPL.-ING., SCHETTLER, HELMUT, DIPL.-ING.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: H01L21
IPC codes: H01L21, H05K3, H05K1