Format converting circuit for numeric data

Abstract: A format converting circuit for numeric data comprises an operation unit (9) which operates according to a mode decision signal to output an input data as it is or a two's complement of the input data; a storage device (11) which stores a positive or negative sign data to be read out and is reset by an initializing signal to a positive data storing state; and a control circuit (13) which operates in two conversion modes. One of the modes is a signed-to-unsigned conversion mode in which the control circuit (13) controls the operation unit (9) with the mode decision signal such that, if a sign bit of the input data is 0, the operation unit (9) outputs the data as it is while, if the sign bit is 1, the operation unit (9) outputs a two's complement of the input data. At the same time, the control circuit (13) inverts the data stored in the storage device if the above-mentioned sign bit is 1. The other mode is an unsigned-to-signed conversion mode in which the control circuit (13) controls the operation unit (9) with the mode decision signal such that, if the data stored in the storage device (11) is positive, the operation unit (9) outputs the input data as it is while, if the data stored in the storage device (11) is negative, the operation unit (9) outputs a two's complement of the input data.

Description: FORMAT CONVERTING CIRCUIT FOR NUMERIC DATA The present invention relates to a logic circuit for converting the format of numeric data, and particularly to a format converting circuit for converting unsigned numeric data into signed numeric data and signed numeric data into unsigned numeric data, as described in the precharacterizing part of claim 1. Generally, the multiplication or the division of signed numbers (the most significant bit of each of the signed numbers represents a sign, and a negative number is represented with a two's complement of the number) is carried out by converting the signed numbers into unsigned numbers (absolute values). An unsigned result of the multiplication or the division is converted into a signed number according to a decision rule. Fig. 1 shows an example of the conversion. If a multiplier and a multiplicand in a multiplication operation have the same sign, the sign of a product of the multiplication will be positive and, if they have different signs, it will be negative. Therefore, in converting an unsigned product into a signed number, it is necessary only to see whether or not a multiplier and a multiplicand have the same sign. On the other hand, the signs of a quotient and a remainder in a division operation are determined according to separate rules as shown in Fig. 2. Therefore, in converting an unsigned quotient and an unsigned remainder into signed numbers, it is necessary to see not only whether or not the signs of a divisor and a dividend are the same but also what the sign of the dividend is. To cope with them, a conventional converting circuit shown in Fig. 3 uses two flip-flop circuits 1 and 3 for storing the signs of numeric data shown in Fig. 2. In converting a signed number into an unsigned number with this circuit, a conversion mode instruction signal is given to a control circuit 7 to specify a signed-to-unsigned conversion mode. Under this mode, if a sign bit of the signed number is 0, an adder 5 outputs the number as it is while, if the sign bit is 1, the adder 5 calculates and outputs a two's complement of the number. In addition, the sign bits of numeric data are stored in the flip-flops 1 or 3, according to the conversion mode instruction signal. In converting an unsigned operation result into a signed number, the conversion mode instruction signal instructs the control circuit 7 to specify an unsigned-to-signed conversion mode as well as informing the control circuit 7 of whether the unsigned operation result is a quotient (or a product) or a remainder. If it is the quotient (or the product), an exclusive OR of sign bits stored in the flip-flops 1 and 3 determines an operation mode of the adder 5. Namely, if the exclusive OR is 0, the adder 5 outputs the quotient (or the product) as it is and, if it is 1, the adder 5 outputs a two's complement of the quotient (or the product). If it is the remainder, a sign bit (indicating the sign of a dividend) stored in the flip-flop 3 determines an operation mode of the adder 5. If the sign bit is 0, the adder 5 outputs the remainder as it is and, if it is 1, the adder 5 outputs a two's complement of the remainder. As described in the above, the conventional converting circuit stores the signs of two numeric data separately, and uses them to determine the sign of an operation result. Due to this, the conventional circuit has drawbacks mentioned below. Two flip-flops shall be arranged to store the sign bits of two input data, respectively. In converting signed numbers into unsigned numbers, it is necessary to distinguish two numeric data from each other and store the sign bits of them in corresponding flip-flops. In converting an unsigned number into a signed number, it is necessary to specify whether the unsigned number is a quotient (or a product) or a remainder to determine the sign thereof. Therefore, two signal lines must be prepared for sending conversion mode instruction signals, which complicates a control circuit. Further, in controlling the control circuit with a microinstruction, at least two bits in an operation code field of the microinstruction are needed. A method of division using two's complement numbers is disclosed in COMPUTER DESIGN, Vol. 11, No. 5, May 1972, pages 115-121, "2's Complement Arithmetic Operations". In this article it is stated that the special nature of the sign bit cannot be ignored and an example of two's complement division has been given. However, the handling of the sign bit during converting to and from two's complement is not discussed. JP-A-61201330 describes a divider having a ROM, an inverter, an adder and a multiplier. The reciprocal of a divisor is calculated in the ROM and is output to the adder which is supplied with the inverted sign bit of the dividend. The adder provides an output so that the sign of the reminder of the division result is the same as the sign of the divisor to be obtained. The division result is obtained at the output of a multiplier which receives the output of the adder as well as the dividend. However, the adder processes only the output of the ROM and the sign bit of the dividend but not the dividend itself. The object underlying the present invention is to provide a format converting circuit for numeric data which has a simple constitution compared to that of a convential circuit. In order to accomplish this object the present invention provides a format converting circuit for numeric data as defined in claim 1. The format converting circuit of numeric data according to the present invention with the above-mentioned arrangement has advantages mentioned below. In converting signed numbers into unsigned numbers, a positive sign data is stored in the storage means if an exclusive OR of the sign bits of two numeric data is 0 (i.e., the sign bits are equal to each other), while a negative sign data is stored in the storage means if the exclusive OR of the sign bits is 1 (i.e., the sign bits are different from each other). Therefore, only one flip-flop for storing the sign bits is needed. In converting signed numbers into unsigned numbers, two numeric data are not needed to be distinguished from each other. In addition, in converting an unsigned number into a signed number, it is not necessary to designate whether an input data is a quotient (or a product) or a remainder. Therefore, only one line for the conversion mode instruction signed is needed in selecting an operation mode. Further, a control circuit will be simplified. These and other objects, features and advantages of the present invention will be more apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an example of converting signed numbers into unsigned numbers and converting unsigned numbers into signed numbers; Fig. 2 is a view showing relations between the signs of quotients and remainders and the signs of divisors and dividends; Fig. 3 is a format converting circuit of numeric data according to a prior art; Fig. 4 is a view showing the constitution of a format converting circuit of numeric data according to an embodiment of the present invention. Fig. 5 is a timing chart showing the converting operation of the converting circuit of Fig. 4, in finding a quotient of division; Fig. 6 is a timing chart showing the converting operation of the converting circuit of Fig. 4, in finding a remainder of division; Fig. 7 is a table showing values to be stored in a flip-flop at respective clock cycles of the converting operation shown in Fig. 5; Fig. 8 is a table showing values to be stored in the flip-flop at respective clock cycles of the converting operation shown in Fig. 6; Fig. 9 is a view showing another embodiment of the present invention in which an arithmetic logic operation unit is used instead of an adder adopted in the embodiment of Fig. 4; and Fig. 10 is a view showing still another embodiment of the present invention in which a microinstruction is used instead of a conversion mode instruction signal of Fig. 4 to control a control circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 4 is a view showing a format converting circuit of numeric data according to an embodiment of the present invention. The format converting circuit has an adder 9. The adder 9 operates according to a mode decision signal from a control circuit 13 to output an input number as it is (a through mode) or to output a two's complement of the input number (a complement mode). A flip-flop 11 stores a sign data from the control circuit 13, and latches an input signal in synchronism with a clock signal. The flip-flop circuit 11 is reset to 0 by an initializing signal. The control circuit 13 is put, according to a conversion mode instruction signal, in a signed-to-unsigned conversion mode or to an unsigned-to-signed conversion mode. Under the signed-to-unsigned conversion mode, the control circuit 13 puts the adder 9 in the through mode if the sign bit of a numeric data inputted to the adder 9 is 0, and puts the adder 9 in the complement mode if the sign bit is 1. At the same time, the control circuit 13 finds an exclusive OR of the sign bit of the input data with respect to a sign data stored in the flip-flop 11, and transfers the exclusive OR to the flip-flop 11. Therefore, if the sign of the input data is 0, the value of the flip-flop 11 will not be changed and, if the sign bit of the input data is 1, the value of the flip-flop 11 will be inverted. In the unsigned-to-signed conversion mode, the control circuit 13 puts the adder 9 in the through mode to pass an input numeric data as it is if a value stored in the flip-flop 11 is 0, and puts the adder 9 in the complement mode to output a tow's complement of the input data if the value of the flip-flop 11 is 1. How this converting circuit converts signed operation data into unsigned numbers, and an unsigned operation result into a signed number will be explained. Fig. 5 is a timing chart in finding a quotient of division, and Fig. 7 shows values to be stored in the flip-flop 11 at respective cycles of the converting operation. In a first clock cycle 1 ○, an initializing signal is set to HIGH to reset the flip-flop 11 to 0 as shown in a column 1 ○ of the table of Fig. 7. In the next clock cycle 2 ○, a conversion mode instruction signal specifying the signed-to-unsigned conversion mode is sent to the control circuit 13, and a numeric data of divisor is inputted to the adder 9. According to the above-mentioned function of the control circuit 13, the input numeric data is outputted as it is from the adder 9 if a sign bit of the inputted data is 0, and a two's complement of the inputted numeric data is outputted from the adder 9 if the sign bit is 1. At the same time, if the sign bit is 0, a status of the flip-flop 11 will not be changed while, if the sign bit is 1, the status of the flip-flop 11 will be inverted. Namely, as shown in a column 2 ○ of the table of Fig. 7, the flip-flop 11 will be 1 if the sign bit of the divisor is negative. In the next clock cycle 3 ○, a dividend is inputted. Similar to the case of the divisor, the inputted number is outputted as it is if a sign bit of the inputted number is 0, and a two's complement of the inputted number is outputted if the sign bit is 1. Further, if the sign bit is 0, the status of the flip-flop 11 will not be changed while, if the sign bit is 1, the status of the flip-flop 11 will be inverted. As a result, as shown in a column 3 ○ of Fig. 7, the flip-flop 11 will be 0 if the divisor and dividend have the same sign, and the flip-flop 11 will be 1 if the divisor and dividend have different signs, respectively. Namely, an exclusive OR of the sign bits of the divisor and dividend is stored in the flip-flop 11. After the signed divisor and dividend are converted into unsigned numbers, the conversion mode instruction signal is set to LOW in the next clock cycle 4 ○ to put the converting circuit in the unsigned-to-signed conversion mode. During this clock cycle, a division operation is executed according to the unsigned divisor and dividend. Then, an unsigned quotient is inputted in the next cycle 5 ○. The inputted quotient is outputted as it is if the status of the flip-flop 11 is 0, while a two's complement of the inputted quotient is outputted if the status of the flip-flop 11 is 1, thus converting the quotient into a signed number. Next, a way for finding a remainder will be explained. The converting circuit is put in the signed-to-unsigned conversion mode in a clock cycle 5 ○ shown in Fig. 6, and a signed divisor is inputted for a second time. If the sign bit of the divisor is 0, a value stored in the flip-flop 11 will not be changed while, if the sign bit is 1, the value in the flip-flop 11 will be inverted. As a result, as shown in a column 5 of Fig. 7, the value of the flip-flop 11 will be equal to a value of the sign bit of a dividend. According to the value of the sign bit, the divisor is outputted as it is, or a two's complement of the divisor data is outputted. However, the outputted data is ignored. In the next clock cycle 6 ○, the converting circuit is put in the unsigned-to-signed conversion mode, and an unsigned remainder is inputted. Similar to the case of the quotient, the inputted remainder is outputted as it is if the value of the flip-flop 11 is 0 and, if the flip-flop is 1, a two's complement of the remainder is outputted. Although the conversion operation for finding only a quotient or a remainder has been explained, both the quotient and remainder can be found by continuously executing the conversion operation on the quotient and remainder to consecutively convert the unsigned quotient and remainder into signed numbers. A conversion operation related to multiplication can be executed in a manner similar to that of finding a quotient of division. In the above embodiment, an adder has been used to output an input signal of n bits as it is, or to output a two's complement of the input signal. This adder may be replaced with another device, if the device has the same function as that of the adder. For example, as shown in Fig. 9, a standard arithmetic logic operation unit (ALU) which executes arithmetic and logic operation with respect to a plurality of input data may be used. The control circuit 13 may be controlled with a microprogram such that the conversion mode instruction signal is given to the control circuit 13 as a code of an operation field of a microinstruction, as shown in Fig. 10. In this case, the code of the operation field will be satisfactory if it can specify the two converting operations, i.e., the signed-to-unsigned and unsigned-to-signed conversion operations so that the operation field code is needed to have only one bit.

Claims: A circuit for converting a format of numeric data, comprising: operation means (9) for outputting an input numeric data either as it is or as a two's complement of the input numeric data according to the state of a mode decision signal; storage means (11) for storing a positive or negative sign data to be read out, control means (13) having two operation modes, one of the operation modes being a signed-to-unsigned conversion mode under which said control means (13) controls said operation means (9) via the mode decision signal such that, if an input sign bit of the input numeric data is 0, said operation means (9) outputs the input numeric data as it is while, if the input sign bit is 1, said operation means (9) calculates and outputs a two's complement of the input numeric data, the other of the two operation modes being an unsigned-to-signed conversion mode under which said control means (13) controls said operation means (9) via the mode decision signal such that, if the sign data stored in said storage means (11) is positive, said operation means (9) outputs the input numeric data as it is while, if the sign data stored in said storage means (11) is negative, said operation means (9) outputs a two's complement of the input numeric data; characterized , in that, before conversion of the input numeric data, said storage means (11) is reset by an initializing signal to a state storing positive sign data; and in that in the signed-to-unsigned conversion mode with the input sign bit being 1, said control means (13) inverts the sign data stored in said storage means (11). A circuit as claimed in claim 1, characterized, in that said control means (13) is firstly put into the signed-to-unsigned conversion mode in order to input a signed multiplier, a signed multiplicand or a signed dividend to said operation means (9) and to convert the signed multiplier, multiplicand or dividend into an unsigned number. A circuit as claimed in claim 1 or 2, characterized, in that said control means (13) is firstly put into the unsigned-to-signed conversion mode in order to input an unsigned quotient or an unsigned product to said operation means (9) and to convert the unsigned quotient or product into a signed number. A circuit as claimed in claim 1, 2 or 3, characterized, in that said control means (13) is firstly put into the signed-to-unsigned conversion mode in order to input a signed divisor to said operation means (9), then in the unsigned-to-signed conversion mode in order to input an unsigned remainder to said operation means (9) and to convert the unsigned remainder. The circuit as claimed in claim 1, characterized, in that said operation means (9) is an adder (9) having an input of N bits and an output of N bits. The circuit as claimed in claim 1, characterized, in that said storage means (11) is a flip-flop circuit (11). The circuit as claimed in claim 1, characterized, in that said operation means (9) is an arithmetic logic operation means (9) capable of executing arithmetic and logic operations with respect to a plurality of input data. The circuit as claimed in claim 1, characterized, in that said control means (13) is put in the unsigned-to-signed conversion mode or in the signed-to-unsigned conversion mode according to a conversion mode instruction signal to be sent through a single line. The circuit as claimed in claim 1, characterized in that said control means (13) is put in the unsigned-to-signed conversion mode or in the signed-to-unsigned conversion mode according to a microinstruction operation code.

Inventors: FUNYU MASAMI, FUNYU, MASAMI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G06F5
IPC codes: G06F7, G06F9, G06F5