Semiconductor memory device having a serial access memory

Abstract: A semiconductor memory device includes a RAM (40) and a serial access memory (SAM) (41). The SAM includes an address counter which generates a slave address (SAD) and a master address (MAD). The slave address precedes the master address by half the period of a serial access strobe signal (SAS). A redundancy decision is made by comparing the slave address with a redundancy address. When the master address is supplied to a data register provided in the SAM, the decision result is available. That is, the SAM can be accessed immediately after the master address is supplied thereto.

Description: The present invention generally relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a serial access memory. Generally, an image memory used in the field of image processing has two ports: a random port and a serial port. The random port is connected to a central processing unit (hereinafter simply referred to as a CPU), and the serial port is connected to a display device such as a cathode-ray tube display device. The access speed at the serial port is desired to be as fast as possible since it directly influences the image displaying speed. Particularly, there is a need to use a higher-access speed image memory as an image memory used for high-speed image processing for drawing pictures at high speeds. Referring to FIG.1, there is illustrated a conventional semiconductor memory device having a serial access memory. Referring to FIG.1, a semiconductor memory device 1 includes a random access memory (hereinafter simply referred to as a RAM) 2, and a serial access memory (hereinafter simply referred to as a SAM) 3. The RAM 2 includes memory cells located at intersecting points where word lines and bit lines intersect. One of the word lines is selected by a row address supplied from an external device such as a CPU, and one of the bit lines is selected by a column address supplied therefrom. The SAM 3 is made up of an address counter 3a, a redundancy decision circuit 3b, a data register 3c, and an input/output buffer 3d. The address counter 3a inputs, as an initial address value for serial access, the column address in synchronism with a rise of a serial access strobe signal SAS, and generates a corresponding serial access address SA AD . The redundancy decision circuit 3b compares the serial access address SA AD with a predetermined redundancy address, and outputs a redundancy switching signal SOM when the compared addresses are identical to each other. The data register 3c has storage (register) cells and redundancy cells amounting to one line of the RAM 2. The storage cells are accessed one by one in series in synchronism with the redundancy address SA AD . When the redundancy switching signal SOM is supplied to the data register 3c, the redundancy cells are accessed. The serial input/output buffer 3d connects the data register 3c and an input/output terminal 4 bidirectionally. However, the conventional device as shown in FIG.1 presents the following disadvantages. The address counter 3a inputs the column address labelled C AD in synchronism with a rise of the serial access strobe signal SAS, as shown in FIG.3(B). In other words, a timing with which the column address is input corresponds to the rise of the serial access strobe signal SAS. Then the address counter 3a outputs the serial access address SA AD , and then the redundancy decision circuit 3b outputs the redundancy switching signal SOM to the data register 3c. Thus, the serial access speed of the device is not so high. It is inevitable that a large storage capacity memory device is configured so as to have a redundancy structure and therefore a redundancy decision procedure is necessarily required. In the redundancy decision procedure, an address for cells requested to be accessed is compared with the redundancy address which is programmed information indicative of defective cells, and a decision is made based on whether both the addresses are the same. It is noted that the above-mentioned redundancy decision procedure cannot be done until the address of cells requested for accessing, that is, the serial access address SA AD is settled. In the above-mentioned manner, the serial access cannot be done until the serial access address SA AD is settled and then the redundancy decision procedure is executed. Even when the length of a period of the serial access strobe signal SAS is reduced in order to speed up the serial access, there is a limit on the possible reduction due to a time necessary for the settlement of the serial access address SA AD and the redundancy decision procedure. The above description holds true for an alternative in which the column address C AD is input in the address counter 3a in synchronism with a fall of the serial access strobe signal SAS. Accordingly, it is desirable to provide an improved semiconductor memory device having a serial access memory in which the aforementioned disadvantages are eliminated. An embodiment of the present invention may provide a higher-speed semiconductor memory device having a serial access memory in which serial access is done immediately after the serial access signal falls or rises or, in other words, the column address is input in the address counter so that the length of a period of the serial access signal can be reduced and serial access speed can be increased. According to the present invention, there is provided a semiconductor memory device including:- a plurality of memory cells, a plurality of redundancy memory cells for replacing defective ones of said memory cells, and a serial access memory comprising a data register means having a plurality of data registers for storing data composed of a plurality of bits to be output in serial form, selecting means for sequentially designating said plurality of data registers and sequentially outputting said plurality of bits, and a redundancy register which can replace one of said plurality of data registers; first address generating means, for sequentially generating a first said serial access address; redundancy decision means for determining whether said first serial access address generated by said first address generating means coincides with an address indicative of one of said redundancy memory cells; output means, coupled to said selecting means for outputting said data stored in said redundancy register in place of data stored in said data register means when said redundancy decision means detects a coincidence of addresses; and second address generating means, coupled to said first address generating means and arranged to sequentially generate a second serial access address, delayed with respect to said first serial access address, and which is supplied to said selecting means. Reference is made, by way of example, to the accompanying drawings, in which:- Fig. 1 is a block diagram of a conventional semiconductor memory device having a serial access memory; Fig. 2 is a block diagram of the principle of the present invention; Fig. 3 is a timing chart of signals observed in the configuration shown in Fig. 2 and the conventional device shown in Fig. 1; Fig. 4 is a block diagram of a fundamental structure of the invention which handles a plurality of address bits; Fig. 5 is a timing chart of signals observed in the configuration shown in Fig. 4; Fig. 6 is a block diagram of a fundamental structure of the present invention where an address signal is divided into groups each consisting of bits; Fig. 7 is a timing chart of signals observed in the configuration shown in Fig. 6; Fig. 8 is a block diagram of the entire structure of a semiconductor memory device according to a preferred embodiment of the present invention; Fig. 9 is a block diagram of a decoder, a data register and a peripheral circuit thereof; Fig. 10 is a circuit diagram of an address counter used in the embodiment shown in Fig. 8; FIG.11 is a circuit diagram of a flip-flop used in the address counter shown in FIG.10; and FIG.12 is a circuit diagram of a redundancy decision circuit and a gate and latch circuit used in the embodiment shown in FIG.8. A description is given of the principle of the present invention with reference to FIG.2. The configuration shown in FIG.2 corresponds to a serial access memory provided in a semiconductor memory device according to the present invention. The illustrated configuration includes a first counter 10, a second counter 11, a redundancy decision circuit 12, and a gate and latch circuit 13. The first counter 10 is supplied with a column address C AD , an initial counter address setting signal SAT, and an inverted serial access strobe signal SAS . The signal SAT is supplied from an external device such as a CPU. The inverted serial access strobe signal SAS is generated in the semiconductor memory device, and is 180 degrees out of phase with the serial access strobe signal SAS which is supplied to the second counter 11 and the gate and latch circuit 13. The signal SAS rises at the same time as the signal SAS falls or vice versa. The first and second counters 10 and 11 configure a master-slave type flip-flop in which the first and second counters 10 and 11 serve as a master counter and a slave counter, respectively. When the inverted serial access strobe signal SAS rises while the initial counter address setting signal SAT is "H", the first counter 10 inputs the column address C AD therein as the initial address. The input column address is output to the second counter 11 as a slave address signal SAD. The second counter 11 inputs the slave address signal SAD in synchronism with the rise of the serial access strobe signal SAS, and then outputs the slave address signal SAD as a master address signal MAD. As will be described later, the slave address SAD precedes the master address MAD by half the period of the serial access strobe signal SAS. The first counter 10 counts up the column address C AD and outputs the slave address signal SAD each time the inverted serial address strobe signal SAS rises. Referring to a timing chart of FIG.3(A), the slave address signal SAD derived from the first counter 10 is renewed each time the inverted serial access strobe signal SAS rises, that is, each time the serial access strobe signal SAS falls. The master address MAD derived from the second counter 11 is renewed each time the serial access strobe signal SAS rises. The redundancy decision circuit 12 makes a decision on redundancy on the basis of the slave address SAD and the redundancy address supplied from a read only memory (not shown in FIG.2) provided in the semiconductor memory device. The redundancy decision procedure is started before the serial access strobe signal SAS rises. The redundancy decision circuit 12 outputs a signal SA which indicates the decision result when both the input addresses are the same. When the serial access strobe signal SAS rises, the gate and latch circuit 13 is made open whereby it passes the signal SA as the redundancy switching signal SOM. At almost the same time, the master address MAD is output from the second counter 11. When a data register corresponding to the data register 3c shown in FIG.1 is being accessed by the master address MAD and the redundancy switching signal SOM is being output, one of the redundancy cells provided in the data register is selected and the serial access to the selected redundancy cell is executed. Thus, the serial access is started immediately after the master address MAD and the serial access strobe signal SAS are supplied to the data register. As a result, it is possible to reduce the period of the serial access strobe signal SAS so that the serial access speed can be increased. In the case of FIG.3A, it should be appreciated that the decision result SA for the address ′n′ is obtained by almost a half of the period than the master address MAD corresponding to the address SA AD is incremented to the address ′n′, and the redundancy switching signal SOM (the decision result) is obtained at almost the same time as the master address MAD is changed to the address ′n′. As a result, as shown in FIG.3, the serial access speed is Δt faster than the serial access speed of the conventional device per once addressing. FIG.4 is a block diagram of a serial access memory in which the column address C AD consists of n bits. Referring to FIG.4, an address counter 20 is made up of n pairs of the first and second counters 10 and 11. That is, a pair of the first and second counters 10 and 11 is provided for each of the n bits. The address counter 20 outputs the serial access strobe signal SAD consisting of n bits and the master address MAD consisting of n bits. A clock generator 21 generates a clock signal  having the same timing as the serial access strobe signal SAS, and a clock signal  obtained by inverting the clock signal . As shown in FIG.5, the slave address SAD consisting of n bits is output in synchronism with the rise of the clock signal  , that is, the fall of the serial access strobe signal SAS. The master address MAD consisting of n bits is output in synchronism with the rise of the clock signal , that is, the rise of the serial access strobe signal SAS. Thus, it is possible to start a necessary internal operation including the redundancy decision procedure before the serial access strobe signal SAS rises. As a result, it is possible to reduce the period of the serial access strobe signal SAS and thus speed up accessing. In the aforementioned operation, the master address MAD to be supplied to the data register is settled in synchronism with each rise of the serial access strobe signal SAS. Alternatively, it is possible to supply the master address MAD to the data register in synchronism with each fall of the serial access strobe signal SAS. In some of conventional memory devices, the column address (initial setting address) supplied to the serial access memory is predecoded by a column decoder provided on the side of the RAM, and is divided into groups. A configuration shown in FIG.6 is suitable for such cases. Referring to FIG.6, an address counter 30 includes a group-A counter 30a for low-order address bits and a group-B counter 30b for high-order address bits. That is, the column address is divided into two groups of group A and group B. The number of groups is not limited to two. The group-A counter 30a includes master-slave type flip-flops 31a - 31n which amount to the number of bits contained in the group A, and a carry circuit 32 which outputs a carry Q A in response to a master output supplied from the flip-flop 31n. A letter ′M′ denotes a master part, and a letter ′S′ denotes a slave part. The group-B counter 30b includes master-slave type flip-flops 33a - 33m amounting to the number of bits contained in the group B. A shift clock generator 34 relates to the group A, and generates a clock signal ₁ with the same timing as the serial access strobe signal SAS, and a clock signal  ₁ which is an inverted signal of the signal SAS. A shift clock generator 35 relates to the group B, and generates a clock signal ₁ with the same timing as the serial access strobe signal SAS and a clock signal  ₁ which is an inverted signal of the signal SAS each time the carry Q A is supplied from the carry circuit 32. A redundancy decision circuit 36 is provided with the bits supplied from the slave part of the flip-flops 31a -31n, and a group-A redundancy address supplied from a ROM (not shown) provided in the memory device. A redundancy decision circuit 37 is provided with the bits supplied from the slave part of the flip-flops 33a -33m, and a group-B redundancy address supplied from the ROM. The decision results AG and BG which are derived from the redundancy decision circuits 36 and 37, respectively, are supplied to a gate and latch circuit 38, which outputs the redundancy switching signal SOM based on the results AG and BG when the serial access strobe signal SAS rises. Referring to FIG.7, the slave address SAD related to the group A is renewed each time the clock signal  ₁ rises, that is, the serial access strobe signal SAS falls. The master address MAD related to the group A is renewed each time the clock signal ₁ rises, that is, the serial access strobe signal SAS rises. When the group-A counter 30a makes a round of counting, the carry circuit 32 outputs the carry Q A . In response to the carry Q A , the slave address SAD related to the group B is renewed when the clock signal  ₂ rises, that is, when the serial access strobe signal SAS falls, and the master address MAD related to the group B is renewed when the clock signal ₂ rises, that is, the serial access strobe signal SAS rises. FIG.8 is a diagram of the entire structure of a semiconductor memory device according to a preferred embodiment of the present invention. Referring to FIG.8, the memory device includes a RAM 40 and a SAM (serial access memory) 41. The RAM 40 is configured as follows. The RAM 40 is supplied with an external address signal which has been multiplexed. An address buffer 42 receives the external address signal and separately outputs a row address signal and a column address signal. A row decoder 44 decodes the row address signal, and selects one word line from among a plurality of word lines provided in a memory cell array 43 where a plurality of memory cells MC are arranged in an array. Some of the memory cells are redundancy cells located at a predetermined area in the memory cell array 43. The redundancy cells are replaceable with defective cells in the memory cell array 43. A column decoder 45 decodes the column address signal, and selects one bit line out of a plurality of bit lines in the memory cell array 43. A sense amplifier and I/O gate 46 amplifies the potential of the selected bit line, and performs data reading and writing. An input/output buffer 48 is interposed between a random input/output terminal 47 and the sense amplifier and I/O gate 46 and passes parallel data in the bidirection. A clock generator 49a is supplied from an external device such as a CPU with a row address strobe signal RAS , a column address strobe signal CAS , a write enable signal WE , and a transfer signal TR . The transfer signal TR instructs the RAM 40 and the SAM 41 to operate in synchronism with each other. The clock generator 49a generates the initial counter address setting signal SAT, which is supplied to a clock generator 49b related to the serial access memory 41. Further, the clock generator 49a generates various control signals, which are supplied to a RAM port 57 coupled to the terminal 47. On the other hand, the serial access memory (SAM) 41 is configured as follows. The clock generator 49b receives the initial counter address setting signal SAT from the clock generator 49a and the serial access strobe signal supplied from the CPU for example, and generates the following clock signals. That is, the clock generator 49b generates a clock signal  SAT of the same timing as the initial counter address setting signal SAT, a clock signal  SAT which is an inverted signal of the signal SAT, a clock signal  SAS having the same timing as the serial access strobe signal SAS, and a clock signal  SAS which is an inverted signal of the signal SAS. An address counter 50 receives the column address signal and all the clock signals supplied from the clock generator 49b, and outputs the slave address SAD and the master address MAD. A redundancy decision circuit 51 compares the slave address signal SAD with a redundancy address signal supplied from a read only memory (ROM) 49c, and outputs a redundancy decision signal S H . The redundancy address signal indicates the redundancy cells provided in the memory cell array 43. A gate and latch circuit 52 temporarily stores the redundancy decision circuit S H , and outputs the same as the redundancy switching signal SOM to a decoder 54. The decoder 54 consists of first and second decoders 54a and 54b as shown in FIG.9. When the redundancy switching signal SOM is inactive, the first decoder 54a is selected. On the other hand, when the redundancy switching signal SOM is active, the second decoder 54b is selected. Each bit of the decoder output is supplied with the gates of two MOS transistors T1 and T2, which are coupled to corresponding signal lines of a bus 58. A data register 53 has a storage capacity equal to one line of the memory cell array 43, and includes a group 53a of register cells and a group 53b of redundancy register cells, each of which is coupled to a corresponding pair of MOS transistors such as T1 and T2. The redundancy register cells are coupled to the corresponding redundancy cells provided in the memory cell array 43. The decoder 54 selects one of the register cells on the basis of the supplied master address MAD. The data register 53 is connected to the bit lines of the memory cell array 43. Turning to FIG.8, a serial input/output buffer 56 is interposed between a serial input/output terminal 55 coupled to an external data line (not shown) and the data register 53, and passes serial data in the bidirection. FIG.10 is a circuit diagram of the address counter 50. The address counter 50 is made up of master-slave type flip-flops FF₀ - FF n which amount to the number of bits of the column address signal. FIG.11 is a circuit diagram of the master-slave type flip-flop FF₀. Each of the other flip-flops FF₁ - FF n is configured in the same manner as the flip-flop FF₀. A slave part S of the flip-flop FF₀ includes a first gate 64, a second gate 71 and a slave-side flip-flop 80. The first gate 64 is made up of two P-channel MOS transistors 60, 61, and two N-channel MOS transistors 62, 63, which are totem pole connected. The second gate 71 is made up of three P-channel MOS transistors 65, 66 and 67, and three N-channel MOS transistors 68, 69 and 70, which are totem pole connected. The slave-side flip-flop 80 is made up of four P-channel MOS transistors 72, 73, 74 and 75, and four N-channel MOS transistors 76, 77, 78 and 79. The first gate 64 inputs a bit A₀ of the column address signal when the clock signal  SAT is "L (low)" and the clock signal  SAT is "H (high)". The slave-side flip-flop 80 latches the input address bit A₀ when the clock signal  SAS switches from "H" to "L" (in other words, the clock signal  SAS switches from "L" to "H"), that is, when the serial access strobe signal SAS falls.. Then the slave-side flip-flop 80 outputs the latched bit A₀ as a bit A₀′ (SAD) to a master part M of the flip-flop FF₀ and the redundancy decision circuit 51 shown in FIG.8. The master part M includes a first gate 85, and a master-side flip-flop 92. The first gate 85 is made up of two P-channel MOS transistors 81, 82, and two N-channel MOS transistors 83, 84, which are totem pole connected. The master-side flip-flop 92 is made up of three P-channel MOS transistors 86, 87 and 88, and three N-channel MOS transistors 89, 90 and 91. The master-side flip-flop 92 latches the bit A₀ from the slave part S, when the clock signal  SAS changes from "L" to "H" (in other words, the clock signal  SAS changes from "H" to "L"), that is, when the the serial access strobe signal SAS rises. Then the master-side flip-flop 92 outputs the latched bit A₀′ as a bit A₀″ (MAD) to the decoder 54 (FIG.8). FIG.12 is a circuit diagram of the redundancy decision circuit 51 and the gate and latch circuit 52. The redundancy decision circuit 51 n exclusive-NOR gates EN₁ - EN n , a single n-input NAND gate 93. The redundancy decision circuit 51 compares the slave address SAD (A₀′ - A n ′) with the redundancy address (fuse address F₀ - F n ) supplied from the ROM 49c. When both the addresses are the same as each other, the redundancy decision circuit 51 outputs the redundancy decision signal S H . The gate and latch circuit 52 includes a first gate 98, a flip-flop 105 and an output inverter gate 108. The first gate 98 is made up of two P-channel transistors 94, 95 and two N-channel transistors 96, 97, which are totem pole connected. The flip-flop 105 is made up of three P-channel MOS transistors 99, 100 and 101, and three N-channel MOS transistors 102, 103 and 104. The output inverter gate 108 is made up of a P-channel MOS transistor 106 and an N-channel MOS transistor 107. The gate and latch circuit 52 latches the redundancy decision signal SH from the redundancy decision circuit 51 when the clock signal  SAS changes from "L" to "H" (or the clock signal  SAS changes "H" to "L"), that is, when the serial access strobe signal SAS rises. Then the redundancy decision circuit 52 outputs, as the redundancy switching signal SOM, the latched signal SH to the decoder 54 shown in FIG.8. A description is given of an operation of the embodiment. When the serial access to the SAM 41 is requested, the initial counter address setting signal SAT is set to "L". Thereby, the clock signal  SAT is switched to "L" and the clock signal  SAT is switched to "H". Thus, the flip-flops FF₀ - FF n shown in FIG.10 input the column address bits (A₀ -A n ) as the initial address value. The slave part of the address counter 50 latches the address bits A₀ -A n in synchronism with a fall of the serial access strobe signal SAS, and simultaneously outputs the slave address SAD (A₀′ - A n ′). The address counter 50 latches the slave address SAD on the master side thereof when the serial access strobe signal SAS rises, and simultaneously outputs the master address MAD (A₀″ -A n ″). The redundancy decision circuit 51 determines whether the slave address SAD supplied from the address counter 50 coincides with the redundancy address F₀ -F n . The redundancy decision signal S H indicative of the comparison result is supplied to the gate and latch circuit 52, which latches the result S H when the serial access strobe signal SAS rises, and outputs the same as the redundancy switching signal SOM. In the aforementioned manner, it is possible to start the internal operation such as address setting for the redundancy decision procedure and the redundancy decision procedure from the fall (rise) of the serial access strobe signal SAS and to complete the same when the signal SAS rises (falls). Thus, the serial access operation can be started when the serial access strobe signal SAS rises (falls). This means that the length of a period of the serial access strobe signal SAS can be reduced and thus the access speed can be increased. The present invention is not limited to the aforementioned embodiments, and variations and modifications may be made without departing from the scope of the present invention.

Claims: A semiconductor memory device including:- a plurality of memory cells (MC), a plurality of redundancy memory cells for replacing defective ones of said memory cells (MC), and a serial access memory comprising a data register means (53a) having a plurality of data registers for storing data composed of a plurality of bits to be output in serial form, selecting means (54) for sequentially designating said plurality of data registers and sequentially outputting said plurality of bits, and a redundancy register (53b) which can replace one of said plurality of data registers; first address generating means (10, 50, 30a) for sequentially generating a first said serial access address (SAD); redundancy decision means (12, 51, 36, 37) for determining whether said first serial access address (SAD) generated by said first address generating means coincides with an address indicative of one of said redundancy memory cells; output means (13, 38, 52), coupled to said selecting means for outputting said data stored in said redundancy register in place of data stored in said data register means when said redundancy decision means detects a coincidence of addresses; and second address generating means (11, 50, 30b), coupled to said first address generating means (10, 50, 30a) and arranged to sequentially generate a second serial access address (MAD), delayed with respect to said first serial access address (SAD), and which is supplied to said selecting means (54). A semiconductor memory device as claimed in claim 1, further comprising:- a random access memory (40) including random access read/write means (42, 44, 45, 46, 48) for writing data and reading data into and from said memory cells on the basis of address information supplied from an external device, and coupled to said serial access memory; wherein said data register means (53a) is arranged to store data to be written into or read from said random access memory and to be input from or output to an external signal line in serial form; wherein said first address generating means (10, 50) generates said first serial access address (SAD) starting from an initial address supplied from an external device; wherein said second address generating means (11, 50), receives said first serial access address and generates said second serial access address (MAD) therefrom for supply to said selecting means, said first serial access address (SAD) having the same contents as said second serial access address (MAD) and preceding said second serial access address by a predetermined time; wherein when said second serial access address (MAD) is supplied to said selecting means (54), said data is input in or output from said data register means in series. A semiconductor memory device as claimed in claim 2, wherein said first address generating means (10, 50) includes first counter means (10) for inputting said initial address supplied from the external device in synchronism with a first edge of a pulse signal (SAS) supplied from the external device and for incrementing said first serial access address (SAD) in synchronism with subsequent first edges of said pulse signal, and said second address generating means (11, 50) includes second counter means (11) for outputting said second serial access address (MAD) in synchronism with a second edge of said pulse signal (SAS) following said first edge thereof so that said predetermined time is the difference in time between the first edge and the subsequent second edge of said pulse signal. A semiconductor memory device as claimed in claim 3, wherein said first serial access address (SAD) precedes said second serial access address (MAD) by a half of one period of said pulse signal (SAS). A semiconductor memory device as claimed in claim 3 or claim 4, wherein said output means (13, 38, 52) includes gate and latch means (13, 52) for inputting the comparison result (SA, S H ) from said redundancy decision means and outputting the same as a redundancy switching signal (SOM) in synchronism with the second edge of said pulse signal (SAS). A semiconductor memory device as claimed in claim 5, wherein said gate and latch means (13, 52) outputs said redundancy switching signal during one period of said pulse signal (SAS) from said second edge thereof. A semiconductor memory device as claimed in any preceding claim, further comprising clock generating means (49b) for generating first and second clock pulses (,  ;  SAS ,  SAS ) which are 180 degrees out of phase with each other, and said first and second address generating means (10, 50; 11, 50) generate said first and second serial access addresses in synchronism with said first and second clock pulses, respectively. A semiconductor memory device as claimed in claim 7, wherein said first address generating means (10, 50) includes a slave flip-flop (FF₀ - FF n ) controlled by said first and second clock signals, and said second address generating means (11, 50) includes a master flip-flop (FF₀ - FF n ) controlled by said first and second clock signals. A semiconductor memory device as claimed in claim 8, wherein said slave flip-flop (FF₀ - FF n ) provided in said first address generating means is connected to said master flip-flop (FF₀ - FF n ) provided in said second address generating means. A semiconductor memory device as claimed in claim 8 or 9, wherein said first address generating means (10, 50) includes a plurality of said slave flip-flops corresponding to the number of bits forming said first serial access address, and said second address generating means (11, 50) includes a plurality of said master flip-flops corresponding to the number of bits forming said second serial access address. A semiconductor memory device as claimed in any one of claims 1 to 9, wherein said redundancy decision means includes logic gate means (EN₁ - EN n , 93) for comparing bits of said first serial access address with corresponding bits of said redundancy address and for outputting the comparison result (S H ). A semiconductor memory device as claimed in claim 11, wherein said logic gate means includes exclusive-NOR gates (EN₁ - EN n ) provided for the respective bits to be compared, and a NAND gate (93) which receives output signals of said exclusive-NOR gates and outputs the comparison result (S H ). A semiconductor memory device as claimed in any preceding claim, further comprising generating means (49a) for generating an indication signal (SAT), wherein said first address generating means (10, 50) generates said first serial access address (SAD), starting from an initial address supplied from an external device, upon receipt of said indication signal. A semiconductor memory device as claimed in claim 2 or any of claims 3 to 13 as appended thereto, wherein said initial address corresponds to a column address (C AD ) to be supplied to said random access memory (40). A semiconductor memory device as claimed in any preceding claim, further comprising a read-only memory (49c) which stores said redundancy address. A semiconductor memory device claimed in any preceding claim, wherein said semiconductor memory device is an image memory device which handles image data. A semiconductor memory device as claimed in claim 2, or any of claims 3 to 16 as appended thereto, wherein the first edge of said pulse signal (SAS) is a falling edge and the second edge thereof is a rising edge. A semiconductor memory device as claimed in any preceding claim, wherein:- address information is divided into groups (A, B) each composed of a predetermined number of address bits; said data register means includes a first group (53a) of register cells and a second group (53b) of redundancy cells; a said first address generating means (30a) is provided for each of said groups of address bits respectively, for generating a part of said first serial access address (SAD) starting from an initial address for the respective group of address bits supplied from an external device; a said second address generating means (30b) is provided for each of said groups of address bits respectively, and coupled to the corresponding first address generating means, for inputting the corresponding part of said first serial access address (SAD) and generating a part of said second serial access address (MAD) to be supplied to said selecting means, said first serial access address having the same contents as said second serial access address and preceding said second serial access address by a predetermined time; a said redundancy decision means (36, 37) is provided for each of said groups of address bits respectively, and coupled to said first address generating means for determining whether each part of said first serial access address is the same as a corresponding part of a redundancy address; and said selecting means (54), coupled to said redundancy decision means, selects one of said first and second groups (53a, 53b) of said data register means on the basis of the comparison results (AG, BG) supplied from said redundancy decision means.

Inventors: NOGUCHI MASAAKI, OGAWA HIROAKI, NOGUCHI, MASAAKI, OGAWA, HIROAKI
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1989
Main classification: G11C7
IPC codes: G11C29, G11C7, G11C11