Circuit for generating discrimination level voltage

Abstract: A circuit for generating a discrimination level voltage which is used as a reference voltage to discriminate between two logic levels adjacent to each other in input signals which generally can be in a state corresponding to one of a plurality of different logic levels. The frequency at which the levels of the input signals lie in the upper half of the vicinity of the discrimination level and the frequency at which the levels of the input signals lie in the lower half of the vicinity of the discrimination level are compared, and the discrimination level is controlled so that the above two frequencies are the same.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention relates to a circuit for generating a discrimination level voltage which is used as a reference voltage to discriminate between two logic levels adjacent to each other in input signals which can be generally in a state corresponding to one of a plurality of different logic levels. Generally, in the field of digital systems, more particularly, in digital communication technology, digital signals can be in a state corresponding to one of two or more predetermined discrete levels, e.g., two-state signals can be in a high level state (hereinafter called H level) or in a low level state (hereinafter called L level). When digital signals as mentioned above are output from one unit and received by another unit, sometimes it is necessary to recognize the level (or state) of the received signal, for example, in regenerative repeaters located along transmission lines on which digital signals are transmitted, digital signals transmitted on a transmission line and received in the regenerative repeaters are amplified, reshaped, retimed, and retransmitted on the transmission line. To retransmit the received digital signals, the repeaters must know the level of each received signal, i.e., at which level each output signal should be sent out as a regenerated digital signal. For recognizing the level (or state) of the received signal, (level) discrimination circuits are provided, for example, in the regenerative repeaters or the other communication system able to receive a digital signal. A discrimination circuit generally comprises a circuit for generating a discrimination level voltage (V ref ), and the discrimination level voltage (V ref ) is used to discriminate between different levels of input signals, for example, in two-state systems, to discriminate between a high level and a low level, i.e., a discrimination circuit outputs a high level signal when the voltage of an input signal is higher than the discrimination level voltage (V ref ), and outputs a low level signal when the voltage of an input signal is lower than the discrimination level voltage (V ref ). A level of a digital signal (electric signal or optical signal), however, fluctuates in accordance with fluctuations of temperature and environmental conditions, and varies with deterioration due to age of the system at which the digital signal is generated and transmitted. Further, noise contributes to the fluctuation and variation of the level of the digital signal, when superposed on the signal, and this also varies with the temperature and environmental conditions, and deterioration due to age. In particular, a digital signal transmitted over a long transmission line is greatly affected by the fluctuation and variations due to the above conditions, i.e., input signals or repeaters which are generally located along a long transmission line, may be greatly fluctuated (varied) due to the fluctuations and variations of the above conditions. Since the fluctuation of the levels of digital input signals causes a high error rate when discriminating between different levels of the input signals in a discrimination circuit, there is a great demand to minimize the affect of the above fluctuations of input signal levels in a discrimination circuit, and accordingly, to improve the reliability of the discrimination circuit, in addition to a general demand for a reduction of costs. In particular, when used in regenerative repeaters, since the regenerative repeaters are located such that a technician can not obtain access thereto, there is a further demand that a level adjustment or another regulating operation after the repeaters are installed, be eliminated. (2) Description of the Related Art In the prior art, to conpensate the affect of temperature fluctuations, a temperature compensation circuit is provided in the circuit for generating a discrimination level voltage. This compensation circuit, for example, comprises a resistor having a value which varies in accordance with an ambient temperature, and the discrimination level voltage is obtained from the voltage between the terminals of the resistor, so that the discrimination level voltage can be used to realize an optimum discrimination of different levels of input signals having levels which have been varied due to changes in the ambient temperature. In the above method using a temperature compensation circuit, however, a compensation for a fluctuation factor other than the temperature fluctuation is impossible, and a cumbersome operation of adjusting the initial discrimination level in each circuit for generating a discrimination level voltage must be carried out in accordance with the conditions at the location of the discrimination circuit to which the discrimination level voltage is supplied, and this causes an increase of the manufacturing costs. Another method of decreasing the error rate in the discrimination of the level of the input signals in the prior art is to increase a system margin, i.e., to increase a noise margin, in a stage before the discrimination circuit, but, it is very expensive to provide a construction for increasing a system margin, e. g., for increasing gains in amplifiers, and the effect of this method is not satisfactory because fluctuation factors other than the fluctuation due to the superposing of noise in the stage where the system margin is increased, are not removed. A third method of controlling the discrimination level voltage to be supplied to the discrimination circuit in the prior art is to use a data format which periodically includes one or more predetermined bits in transmitted data, and detects the occurrence of errors by recognizing the predetermined bits using the discrimination level voltage, such as "H"→"L" (errors by recognizing a high level signal as a low level signal), and "L"→"H" (errors by recognizing a low level signal as a high level signal), and the discrimination level is controlled based on the result of the detection of the occurrence of errors. For example, an mBIC code method is known wherein m is a natural number, e.g., when m=10, this is called a 10BIC method. Here, a redundancy bit is inserted into each ten original data bits (i.e., herein the data transfer rate is changed by 11/10 times) to form a block consisting of ten original data bits (1st∼10th bit in the above block), and one redundancy bit, and the redundancy bit (eleventh bit in the above block) is set as an inverted value of a predetermined one bit in the original data, e.g., a bit just before each redundancy bit (the tenth bit in each original ten data bits). Accordingly, the occurrence of errors can be recognized by monitoring the above tenth and eleventh bits in each block. In the above third method, however, a limitation is added to the data format, and the data transfer rate must be changed to periodically insert the above predetermined bits in the original transmitted data, and further, an additional construction for periodically detecting the above occurrence of errors, becomes necessary. WO-A-8 102 653 discloses a circuit which controls the discrimination voltage by means of a correction signal derived from a comparison of the actual difference between the sliced signal and its complement with the statistically expected value of the dirrerence between the signal and its complement. SUMMARY OF THE INVENTION The object of the present invention is to provide a circuit for generating a discrimination level voltage, which operates independently of data format, requires no manual adjustment, and provides an optimum discrimination level regardless of the level fluctuation of an input signal or the cause thereof. Therefore, according to the present invention, there is provided a circuit for generating a discrimination level voltage which is used as a reference voltage to discriminate between two logic levels adjacent to each other in input signals which can be generally in a state corresponding to one of a plurality of different logic levels, comprising: a discrimination level voltage generating means for generating the discrimination level voltage; an offset reference level generating means for generating a plus offset reference level which is higher than the discrimination level by a predetermined offset value, and a minus offset reference level which is lower than the discrimination level by the predetermined offset value; a first eye aperture input detecting means for detecting that a voltage of the input signal lies between the discrimination level and the plus offset reference level; a second eye aperture input detecting means for detecting that a voltage of the input signal lies between the discrimination level and the minus offset reference level; and a level control means for simultaneously controlling the output voltages by the discrimination level voltage generating means and the offset reference level generating means, so that the frequencies of the detections by the first eye aperture input detecting means and the second eye aperture input detecting means are the same. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1A shows an example of a frequency distribution of input signal voltages; Figure 1B shows an example of noise superposed on HIGH and LOW level signals; Figure 2 shows a basic construction of the present invention; Figure 3A shows an example of the shifted distribution 100 of voltages of input signals representing the HIGH level; Figure 3B shows an example of the result of a shifting of the discrimination level voltage corresponding to the shifted distribution 100 in Fig. 3A, according to the present invention; Figure 4A shows an example of the shifted distribution 110 of voltages of input signals representing the LOW level; Figure 4B shows an example of the result of a shifting of the discrimination level voltage corresponding to the shifted distribution 110 in Fig. 4A, according to the present invention; Figure 5 shows the construction of the first and second embodiments of the present invention; Figure 6 shows the construction of an example of the main discrimination circuit 11, or the first or second sub-discrimination circuit 10 or 12; Figure 7 shows an exclusive OR circuit 53; Figure 8 shows an input-output relationship and a timing of the exclusive OR circuit 53 in Fig . 7; Figures 9, 10, 11, and 12 each show a concrete example of the difference obtaining means; Figure 13 shows the construction of an example of the reference level generating means 16 in Fig. 5; and Figure 14 shows a digital-to-analog converter. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1A shows an example of a frequency distribution of input signal voltages. In Fig. 1A, "HIGH" and "LOW" each denote logic levels without level fluctuation, which levels equal the output levels of the discrimination circuit to which the discrimination level voltage obtained by the circuit for generating a discrimination level voltage according to the present invention is supplied. The logic levels denotes by "HIGH" and "LOW" are generally two logic levels adjacent to each other in input signals which can be in a state corresponding to one of a plurality of different logic levels, for example, a high level and a low level in two-state signals. Figure 1B shows an example of noise superposed on the HIGH and LOW level signals, and mainly it is superposing which causes the distribution of the input signals which represent the HIGH or LOW level signal to show an almost Gaussian shape, as shown in Fig. 1A. In Fig. 1A, reference numeral 100 denotes a frequency distribution of input signal voltages, which represent the HIGH level signal, and 110 denotes a frequency distribution of input signal voltages, which represent the LOW level signal. Further, in Fig. 1A, in a range of input signal voltages between the HIGH and LOW levels, the abovementioned two distributions 100 and 110 overlap, and in this voltage range, the actual frequency distribution of the input signal voltage is a summation of the two frequency distributions 100 and 110, as shown by a dashed line and denoted by 120 in Fig. 1A. As shown in Fig. 1A, in the abovementioned range of voltage between the peaks of the two distributions 100 and 110, the frequency of the summation 120 is much smaller than the frequency in the vicinity of the peaks of the two Gaussian shapes 100 and 110, and therefore, this range of voltage between the peaks where the frequency of signal input is much smaller than the frequency in the vicinity of the peaks, is generally called "eye aperture" or "eye opening". Since, in the abovementioned voltage range where the above summation 120 is small, i.e., in the eye aperture range, the frequency of each of the two distributions 100 and 110 is also small, and therefore, when the discrimination level voltage is set in this range, particularly, when the discrimination level voltage is set so that the vicinity of the discrimination level voltage is included in the eye aperture range, the error rate when discriminating the levels of input digital signals can be reduced. In particular, in two-state signals, the frequency of occurrence of signals inputs representing the high level and the frequency of occurrence of signal inputs representing the LOW level are usually made as equal as possible, to prevent a deviation of a direct current level on a transmission line and a lack of timing information due to successive signals having the same value. Therefore, in two-state signals, the total frequency of occurrence of input signals representing the HIGH level and the total frequency of occurrence of input signals representing the LOW level are usually almost the same. In the above case, as understood from Fig. 1A, in an upper half range of the eye aperture range, in practice , the frequency of receiving input signals representing the HIGH level is larger than the frequency of receiving input signals representing the LOW level, and in a lower half range of the eye aperture range, in practice, the frequency of receiving input signals representing the LOW level is larger than the frequency of receiving input signals representing the HIGH level, and therefore, when the discrimination level is set at the center voltage of the eye aperture range, which can be defined as a voltage whereat the frequency of receiving input signals representing the HIGH level equals the frequency of receiving input signals representing the LOW level, the error rate when recognizing the input signals, i.e., the sum of the frequency of recognizing an input signal representing the HIGH level as a LOW level signal, and the frequency of recognizing an input signal representing the LOW level as a HIGH level signal, is minimized. To realize the abovementioned conditions for reducing or minimizing the error rate, a circuit for generating a discrimination level voltage according to the present invention, and having the following construction, is provided. Figure 2 shows, as a basic construction of the present invention, a construction of a circuit for generating a discrimination level voltage V ref which is used as a reference voltage to discriminate between two logic levels HIGH and LOW adjacent to each other in input signals which can be generally in a state corresponding to one of a plurality of different logic levels. In Fig. 2, reference numeral 1 denotes a first eye aperture input detecting means, 2 denotes a second eye aperture input detecting means, 3 denotes a level control means, 4 denotes a discrimination level voltage generating means, and 5 denotes an offset reference level generating means. The discrimination level voltage generating means 4 generates the discrimination level voltage V ref . The offset reference level generating means 5 generates a plus offset reference level V ref + ΔV which is higher than the discrimination level V ref by a predetermined offset value ΔV, and a minus offset reference level V ref - ΔV which is lower than the discrimination level V ref by the predetermined offset value ΔV. The first eye aperture input detecting means 1 detects that a voltage of the input signal is between the discrimination level V ref and the plus offset reference level V ref + ΔV. The second eye aperture input detecting means 2 detects that a voltage of the input signal is between the discrimination level V ref and the minus offset reference level V ref - ΔV. The level control means 3 controls output voltages of the discrimination level voltage generating means 4 and the offset reference level generating means 5, so that the frequencies of the detections in the first eye aperture input detecting means 1 and the second eye aperture input detecting means 2 are the same. According to the present invention, if the distribution 100 of voltages of input signals representing the HIGH level has been shifted down from the HIGH level, as shown in Fig. 3A, the frequency of the detections in the first eye aperture input detecting means 1 is shown as an area of the region "A", and the frequency of the detections in the second eye aperture input detecting means 2 is shown as an area of the region "B" in Fig. 3A. Due to the above down shift of the distribution 100, the position of the discrimination level V ref relative to the positions of the two distributions 100 and 110 is deviated toward the distributions 100, and therefore, the area "A" becomes larger than the area "B", i.e., the frequency of the detections in the first eye aperture input detecting means 1 becomes larger than the frequency of the detections in the second eye aperture input detecting means 2. Corresponding to the above difference between the frequencies of the detections in the first eye aperture input detecting means 1 and the second eye aperture input detecting means 2, the level control means 3 controls voltages output by the discrimination level voltage generating means 4 and the offset reference level generating means 5, so that the frequencies of the detections in the first eye aperture input detecting means 1 and the second eye aperture input detecting means 2 are the same, i.e., in this case, the level control means 3 controls the discrimination level voltage generating means 4 and the offset reference level generating means 5 to down shift the output voltages V ref , V ref + ΔV, V ref - ΔV to V ref ′ , V ref ′ + ΔV′ , V ref ′ - ΔV′ as shown in Fig. 3B, corresponding to the above difference of the frequencies, i.e., corresponding to the voltage shift of the distribution 100, so that the area "A" becomes equal to the area "B" as shown in Fig. 3B, i.e., the frequency of the detections in the first eye aperture input detecting means 1 becomes equal to the frequency of the detections in the second eye aperture input detecting means 2. If the distribution 110 of voltages of input signals representing the LOW level has been shifted up from the LOW level, as shown in Fig. 4A, the position of the discrimination level V ref relative to the positions of the two distributions 100 and 110 is deviated toward the distributions 110, and therefore, the area "B" becomes larger than the area "A", i.e., the frequency of the detections in the second eye aperture input detecting means 2 becomes larger than the frequency of the detections in the first eye aperture input detecting means 1. Corresponding to the above difference between the frequencies of the detections in the first eye aperture input detecting means 1 and the second eye aperture input detecting means 2, the level control means 3 controls the discrimination level voltage generating means 4 and the offset reference level generating means 5, to up shift the output voltages V ref , V ref + ΔV, V ref - ΔV to V ref ′ , V ref ′ + ΔV′ , V ref ′ - ΔV ' as shown in Fig. 4B, corresponding to the above difference of the frequencies, i.e., corresponding to the voltage shift of the distribution 110, so that the area "A" becomes equal to the area "B" as shown in Fig. 4B, i.e., the frequency of the detections in the first eye aperture input detecting means 1 becomes equal to the frequency of the detections in the second eye aperture input detecting means 2. As mentioned above, according to the present invention, the deviation of the position of the discrimination level V ref relative to the positions of the two distributions 100 and 110 is detected as the difference between the frequency at which the levels of the input signals lie in the upper half of the vicinity of the discrimination level and the frequency that the levels of the input signals lie in the lower half of the vicinity of the discrimination level, and the discrimination level is controlled so that the above difference becomes zero, i.e., the deviation of the position of the discrimination level V ref relative to the positions of the two distributions 100 and 110 is made zero. Therefore, generally, an error rate when discriminating between different levels of input signals can be reduced regardless of the type of fluctuation of the levels of the input signals, without a manual adjustment, and in particular, in the case of two-state signals, and when the frequency of occurrence of input signals representing the HIGH level and the frequency of occurrence of input signals representing the LOW level can be deemed to be almost the same, the error rate can be further reduced. Figure 5 shows the construction of the first and second embodiments of the present invention. In Fig. 5, reference number 10 denotes a first sub-discriminating circuit, 11 denotes a main discrimination circuit, 12 denotes a second sub-discrimination circuit, 13 denotes a first discord detection circuit, 14 denotes a second discord detection circuit, 15 denotes a control signal generating circuit, and 16 denotes a reference level generating circuit. The main discrimination circuit 11 discriminates between different logic levels of digital input signals, and component parts other than the main discrimination circuit 11 in Fig. 5 constitute the first and second embodiments of the present invention. The reference level generating circuit 16 generates a discrimination level voltage V ref , a plus offset reference level V ref +ΔV, and a minus offset reference level V ref -ΔV. The discrimination level voltage V ref is supplied to the discrimination circuit, and is used as a reference voltage to discriminate between different levels of input signals. The plus offset reference level V ref +ΔV is higher than the discrimination level V ref by a predetermined offset value ΔV, and the minus offset reference level V ref -ΔV is lower than the discrimination level V ref by the predetermined offset value ΔV. Namely, the reference level generating circuit 16 corresponds to the aforementioned discrimination level voltage generating means 4 and the aforementioned offset reference level generating means 5 in Fig. 2. The first sub-discrimination circuit 10 compares the digital input signal with the plus offset reference level V ref +ΔV, and outputs a high level signal or a low level signal respectively, according to whether a level of the input digtal signal is higher or lower than the plus offset reference level V ref + ΔV, and the second sub-discrimination circuit 12 compares the digital input signal V ref with the minus offset reference level V ref -ΔV, and outputs a high level signal or a low level signal respectively, according to whether a level of the input signal is higher or lower than the minus offset reference level V ref - ΔV. In the first embodiment of the present invention, the first discord detection circuit 13 detects a discord between the output of the first sub-discrimination circuit 10 and the digital input signal (which is the object of level discrimination in the discrimination circuit 11), and similarly, the second discord detection circuit 14 detects a discord between the output of the second sub-discrimination circuit 12 and the digital input signal. In the second embodiment of the present invention, the first discord detection circuit 13 detects a discord between the output of the first sub-discrimination circuit 10 and the discrimination result obtained by comparing the digital input signal with the discrimination level (the output of the main discrimination circuit 11), and the second discord detection circuit 14 detects a discord between the output of the second sub-discrimination circuit 12 and the discrimination result obtained by comparing the digital input signal with the discrimination level (the output of the main discrimination circuit 11). The control signal generating circuit 15 realizes the level control means 3 in Fig. 2, and the control signal generating circuit 15 functions as a difference obtaining means, and obtains a difference between the frequencies of the detections in the first and second eye aperture input detecting means 1 and 2, i.e., the frequencies of the detections in the first and second discord detection circuits 13 and 14, and controls the output of the reference level generating means 16, i.e., the discrimination level voltage V ref , the plus offset reference level V ref + ΔV, and the minus offset reference level V ref -ΔV, so that the frequencies of the detections in the first and second discord detection circuits 13 and 14, are the same. Namely, the control signal generating circuit 15 causes the reference level generating circuit 16 to raise or lower the output voltage V ref (and accordingly, the plus offset reference level V ref + ΔV and the minus offset reference level V ref -ΔV) according to the difference between the frequency of the detections in the first discord detection circuit 13 and the frequency of the detections in the second discord detection circuit 14. The first sub-discrimination circuit 10 and the first discord detection circuit 13 realize the first eye aperture input detecting means 1 in Fig. 2, and the second sub-discrimination circuit 12 and the second discord detection circuit 14 realize the second eye aperture input detecting means 2 in Fig. 2. Figure 6 shows the construction of an example of the main discrimination circuit 11, or the first or second sub-discrimination circuit 10 or 12. In Fig. 6, reference numeral 51 denotes a comparator, and 51 denotes a D-type flip-flop circuit. As a reference input of the comparator 51, the aforementioned discrimination level voltage V ref is input to the main discrimination circuit 11, the aforementioned plus offset reference level V ref + ΔV is input to the first sub-discrimination circuit 10, and the aforementioned minus offset reference level V ref -ΔV is input to the second sub-discrimination circuit 12. As an object of the comparison with the reference input, the aforementioned digital input signal is input in all of the cases to the main discrimination circuit 11, the first sub-discrimination circuit 10, and the second sub-discrimination circuit 12. In each of the above cases, the output of the comparator 51 is held in the D-type flip-flop circuit 52 in the timing of each bit input of the digital input signal. Each of the first and second discord detection circuits 13 and 14 can be realized by an exclusive OR circurt 53 as shown in Figure 7. Figure 8 shows an input-output relationship and a timing of the exclusive OR circuit 53 in Fig. 7. As shown in Fig. 8, when a discord appears between the output of the first or second sub-discrimination circuit 10 or 12 and the output of the main discrimination circuit 11 in the second embodiment (or when a discord appears between the output of the first or second sub-discrimination circuit 10 or 12 and the aforementioned digital input signal in the first embodiment), the first or second discord detection circuit 13 or 14 outputs an effective pulse signal. Figures 9, 10, and 11 each show a concrete example of the aforementioned difference obtaining means. In Fig. 9, reference numerals 60 and 61 denote first and second counters, and 62 denotes a subtractor. The counter 60 counts the effective pulse signals from the first discord detection circuit 13 as mentioned above, and similarly, the counter 61 counts the effective pulse signals from the second discord detection circuit 14. The difference between the count outputs of the counters 60 and 61 is obtained in the subtractor 62 at a predetermined interval, for example, every one second. The counters 60 and 61 are reset before at least one of same overflows. In Fig. 10, the construction similar to Fig. 9 is realized by an up-down counter 63 having a count-up input terminal and a count-down input terminal; the count of which counter is incremented at the timing of an input of a new effective pulse from the count-up input and is decremented at the timing of an input of a new effective pulse from the count-down input. Therefore, when the output of the first discord detection circuit 13 is applied to the count-up input, and the output of the second discord detection circuit 14 is applied to the count-down input, the up-down counter 63 outputs the difference between the outputs of the first and second discord detection circuits 13 and 14. In the construction of the Fig. 10, a reset operation of the counter 63 is not necessary. In Fig. 11, reference numerals 64 and 65 denote first and second counters, 66 denotes a subtractor, 67 denotes an adder, and 68 denotes a D-type flip-flop circuit. Similar to the construction of the Fig. 9, the counter 64 counts the effective pulse signals from the first discord detection circuit 13 as mentioned above, and the counter 65 counts the effective pulse signals from the second discord detection circuit 14. The difference between the count outputs of the counters 64 and 65 is obtained in the subtractor 66 at a predetermined interval, for example, every one second, and then the output of the subtractor 66 is applied to the adder 67 and is added to the output of the D-type flip-flop circuit 68 in the adder 67. The D-type flip-flop circuit 68 holds the output of the adder 67 at each predetermined time, i.e., the output of the D-type flip-flop circuit 68 is renewed by the output of the adder 67 at each predetermined time. The counters 64 and 65 also must be reset before one of same overflows, but in this construction, the past data of the difference of the frequencies of the detections in the first and second discord detection circuits 13 and 14 is stored in the D-type flip-flop circuit 68, and is reflected in the output of the construction of Fig. 11 through the adding operation in the adder 67. Although the up-down counters available on the market tend to operate rather slowly, compared with the simple counters, a function similar to the construction of Fig. 10 can be realized by the construction of Fig. 11, with a faster operation speed. Figure 12 also shows another concrete example of the aforementioned difference obtaining means. In Fig. 12, reference numerals 71 and 72 denote first and second accumulation means, for example, capacitors, and 73 denotes a differential amplifier. Each of the outputs of the first and second discord detection circuits 13 and 14 is applied to the corresponding one of two input terminals INPUT1 and INPUT2, and the charges generated by the aforementioned effective (high voltage) pulses are accumulated in the corresponding one of the capacitors 71 and 72. Accordingly, the voltage between the own terminals of each capacitor is almost proportional to the number of effective pulses input from the corresponding input terminal, i.e., the frequency of the detections in the corresponding discord detection circuit. The analog voltage in proportion to the difference between the voltages accumulated at the capacitors 71 and 72 is obtained by the differential amplifier 73. Each of the outputs obtained in the constructions of Figs. 9, 10, 11, and 12 corresponds to the control output from the level control means 3 in Fig. 2. Figure 13 shows the construction of an example of the reference level generating means 16 in Fig. 5. In Fig. 13, reference numeral 75 denotes a linear amplifier, 76 denotes a transistor, 77 denotes a diode, and 78, 79, 80, and 81 denote resistors. The amplifier 75 is constructed by a differential amplifier, and a reference voltage is applied to one of the two input terminals of the amplifier 75 and the aforementioned control output of the level control means 3, i.e., the output of the control signal generating means 15 is applied to the other input of the differential amplifier 75, and thus, the control output is amplified in the amplifier 75, and then applied to the base terminal of the transistor 76. The collector terminal of the transistor 76 is connected to a high voltage source, and the emitter terminal of the transistor 76 is connected to one terminal of a series connection of the diode 77 and the resistor 78, 79, 80, and 81, where the other terminal of the series connection is connected to the earth level. By the above construction, the current flowing in the transistor 76, i.e., the current flows in each of the resistors 78, 79, 80, and 81, is controlled by the base voltage of the transistor 76, i.e., the control output of the level control means 3. As the input of the construction of Fig. 13 is an analog signal, the analog output of the construction of Fig. 12 can be applied to the input terminal of the construction of Fig. 13, but each of the outputs in the construction of Fig. 9, 10, and 11, as digital data, must be connverted to the analog voltage before applied to the construction of Fig. 13, by, for example, a digital-to-analog converter as shown in Figure 14. In particular, if the possibility of occurrence of an error is very low, i.e., the frequency of the detections in the first or second discord detection means 13 or 14 is very low, for example, if the possibility is about 1×10⁻⁸, it is impossible to detect the difference of the frequencies by the construction of Fig. 12, and therefore, in such a case, the constructions using counters as shown in Figs. 9, 10, and 11, are effective.

Claims: A circuit for generating a discrimination level voltage which is used as a reference voltage to discriminate between two logic levels adjacent to each other in input signals which can be generally in a state corresponding to one of a plurality of different logic levels, comprising: a discrimination level voltage generating means (4) for generating said discrimination level voltage; an offset reference level generating means (5) for generating a plus offset reference level which is higher than said discrimination level by a predetermined offset value, and a minus offset reference level which is lower than said discrimination level by said predetermined offset value; a first eye aperture input detecting means (1) for detecting that a voltage of said input signal is between said discrimination level and said plus offset reference level; a second eye aperture input detecting means (2) for detecting that a voltage of said input signal is between said discrimination level and said minus offset reference level; and a level control means (3) for simultaneously controlling the voltages output by said discrimination level voltage generating means (4) and said offset reference level generating means (5), so that the frequencies of said detections in said first eye aperture input detecting means (1) and said second eye aperture input detecting means (2) are the same. A circuit for generating a discrimination level voltage according to claim 1, wherein: said input signal is a two-value signal; said first eye aperture input detecting means (1) comprises a first sub-discrimination circuit (10) which compares said input signal with said plus offset reference level and outputs a high level signal or a low level signal respectively according to whether a level of said input signal is higher or lower than said plus offset reference level, and a first discord detection circuit (13) which detects a discord between the output of said first sub-discrimination circuit (10) and said input signal as a two-value signal; and said second eye aperture input detecting means (2) comprises a second sub-discrimination circuit (12) which compares said input signal with said minus offset reference level and outputs a high level signal or a low level signal respectively according to whether a level of said input signal is higher or lower than said minus offset reference level, and a second discord detection circuit (14) which detects a discord between the output of said second sub-discrimination circuit (12) and said input signal as a two-value signal. A circuit for generating a discrimination level voltage according to claim 1, wherein: said first eye aperture input detecting means (1) comprises a first sub-discrimination circuit (10) which compares said input signal with said plus offset reference level and outputs a high level signal or a low level signal respectively according to whether a level of said input signal is higher or lower than said plus offset reference level, and a first discord detection circuit (13) which detects a discord between the output of said first sub-discrimination circuit (10) and a discrimination result obtained by comparing said input signal with said discrimination level; and said second eye aperture input detecting means (2) comprises a second sub-discrimination circuit (12) which compares said input signal with said minus offset reference level and outputs a high level signal or a low level signal respectively according to whether a level of said input signal is higher or lower than said minus offset reference level, and a second discord detection circuit (14) which detects a discord between the output of said second sub-discrimination circuit (12) and said discrimination result obtained by comparing said input signal with said discrimination level. A circuit for generating a discrimination level voltage according to claim 1, wherein: said level control means (3) comprises a difference obtaining means which obtains a difference between said frequencies of said detections in said first and second eye aperture input detecting means (1, 2). A circuit for generating a discrimination level voltage according to claim 4, wherein: said difference obtaining means comprises first and second counters (60, 61) which count said frequency of said detections in each of said first and second eye aperture input detecting means (1, 2), respectively, and a subtracting means (62) which obtains a difference between the outputs of both of said first and second counters (60, 61) for said first and second eye aperture input detecting means (1, 2). A circuit for generating a discrimination level voltage according to claim 4, wherein: said difference obtaining means comprises an up-down counter (63) which increments or decrements an own count respectively corresponding to said detection in said first or second eye aperture detecting means (1, 2). A circuit for generating a discrimination level voltage according to claim 4, wherein: said difference obtaining means comprises: first and second counters (64, 65) which count said frequencies of said detections in each of said first and second eye aperture input detecting means (1, 2), respectively; a subtracting means (66) which obtains a difference between the outputs of both of said first and second counters (60, 61) for said first and second eye aperture input detecting means (1, 2); an output register (68) which temporarily registers an output of said difference obtaining means; and an adding means which obtains a summation of the outputs of said subtracting means (66) and said output register (68), and registers said summation in said output register (68). A circuit for generating a discrimination level voltage according to claim 4, wherein: said difference obtaining means comprises: first and second accumulating means (71, 72) each of which accumulates said frequencies of the detections in the corresponding one of said first and second eye aperture input detecting means (1, 2), as an analog value of a voltage, respectively; and a differential amplifier (73) which amplifies a difference between the outputs of both of said first and second accumulating means (71, 72) to obtain an output of said level control means (3).

Inventors: KAWAI MASAAKI, OHTSUKA TOMOYUKI, WATANABE HISAKO, KAWAI, MASAAKI, OHTSUKA, TOMOYUKI, WATANABE, HISAKO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H03K5
IPC codes: H03M5, H04L1, G01R19, H03K5, H04L25