Multiple reuse of an FM band

Abstract: A signal receiving system (10) for receiving messages from each of several unequal amplitude FM carriers (v i (t)) occupying the same portion of the frequency band. The capture effect associated with conventional frequency demodulators is utilized in a series of successively coupled phase lock loops (PLL₁, PLL₂, PLL₃, ..., PLL N ) to provide demodulation of all of several FM carrier signals including weaker carrier signals in the presence of dominant carrier signals. A phase lock loop demodulator (PLL₁) provides a demodulated signal representing the information contained in the most dominant carrier signal input to the phase lock loop (PLL₁). The phase lock loop (PLL₁ also provides a signal (Y i (t)) which is a replica of the most dominant carrier signal in the input. The input signal (V i (t)) is also delayed in a delay circuit (105) and input into an input port of an output circuit (106). The replica signal (Y i (t)) is also coupled to an input port of the output circuit (106). The output circuit (106) produces an output signal (Z i (t)) which is identical to the input signal (V i (t)) except that the most dominant carrier signal is suppressed. The output signal (Z i (t)) is then coupled to a successive phase lock loop (PLL₂) and delay circuit (115).

Description: This invention relates generally to frequency modulation (FM) radio systems, more particularly, systems for receiving all desired broadcast messages from multiple FM carriers of unequal amplitude. In addition, an inherent feature of the present invention is that all suppressed signals, both carrier and modulation, are recoverable to substantially the same extent. In a conventional frequency modulation (FM) radio receiver, the demodulator circuit suppresses weaker FM signals. The receiver is said to be captured by the strongest signal and all presently known FM demodulators exhibit this "capture effect." Capture effect, a weak-signal-suppression characteristic, is a well known property of frequency modulation theory. The prior art includes work by E. J. Baghdady as described in "Signal Cancellation Techniques for Capturing the Weaker of Two Co-Channel FM Signals", Electro-Magnetic Wave Propagation, 1960, pages 183-207, Academic Press. Two signal cancellation techniques were discussed, namely, (1) dynamic trapping and (2) feed-forward. Dynamic trapping attempts to reduce the amplitude of the stronger signal by tuning an electrical bandpass filter. The filter reduces the signal strength of the stronger signal so that it becomes the weaker signal. A conventional demodulator is then used to recover the message from its dominant input, which was originally the weaker desired signal. The theoretical performance of the dynamic trapping technique is uncertain, since it appears to require that the concepts of instantaneous frequency and Fourier transform frequency be equated. Therefore, Baghdady relies on experimental results. The feed-forward technique uses signal suppression provided by narrow band limiters. Such limiters are also difficult to analyze mathematically and again, Baghdady relies on experimental results for supporting this technique. By the very principles of their operation, neither dynamic trapping nor feed-forward tend to function as intended when the instantaneous frequency of the applied FM signals are equal or approximately equal. The prior art also includes U.S. Patents Nos. 3,226,646 to Ludwig, 3,753,123 to Carpenter, et al, and 4,739,518 to Bickley et al. All of these references attempt to recover information from a weaker signal in the presence of one or more stronger signals by signal cancellation and related filtering techniques. In Ludwig a cancellation bridge is used for cancellation of interfering signals and employs a strong signal tracking filter for isolating the interference. The tracking filter incorporates a high signal capture-type demodulator, which provides an instantaneous analog signal for controlling coincidence of the instantaneous center frequency of an electronically tunable filter with the frequency of the undesired stronger signal. Only one output, namely the demodulated weaker signal, is obtained. Again, the concepts of instantaneous frequency and Fourier transform frequency are equated to explain the operation. Carpenter et al describes a system for subtracting unwanted signals from input signals to provide error signals at the output. This reference also teaches use of a phase-locked loop (PLL) in signal extraction means for producing an estimate signal, which includes any incidental amplitude variations of the carrier signal, and which is vectorially subtracted from the input signal. More than one estimate signal may be derived for vector subtraction and, since each extractor remains locked on its own signal, the effect of removing one or more input signals 10 by such subtraction has little or no effect on the remaining signals. Cancellation only of undesired signals is provided. Finally, in Bickley et al the capture effect of a limiter is used to detect a desired signal received with an interfering signal at nearly the same frequency as the desired signal but at significantly greater amplitude. In the described system, a gain-controlled amplifier provides a constant amplitude signal having the amplitude of the interfering signal portion equal to the amplitude of the interfering signal portion produced by the limiter. The constant amplitude and limiter signals combine through a subtraction operation to effectively cancel the interfering signal while causing only small attenuation of the desired signal. Again, only suppression of undesired signals is described. None of these references apparently appreciate other advantages and uses of capture effect of FM demodulators. In addition, while Carpenter et al utilize a phase-locked loop (PLL) in extracting signals from input signals, none of the references appreciate other advantages and uses of phase-locked loop technology for discriminating more than one signal component of the input signal. According to the present invention, there is provided a signal receiving system for receiving an input signal having a plurality of modulated carrier signals included therein, said system characterized by: first demodulator means for receiving the input signal, for producing a signal representing the demodulated message of the most dominant carrier signal of said input signal, and for producing a replica signal of said dominant carrier signal; delay means coupled to the demodulator means for receiving the input signal, and for producing a first signal identical to said input signal except that said first signal is selectively delayed with respect to said input signal; output means, coupled to the delay means and to the demodulator means, for receiving and combining said first signal produced by said delay means and said replica signal produced by said demodulator means, and for producing an output signal representing the input signal with the most dominant carrier suppressed; and second demodulator means coupled to said output means for receiving the output signal produced thereby, for producing a signal representing the demodulated message of the second most dominant carrier of said input signal, and for producing a replica signal of said second most dominant carrier signal. The present invention further provides a method for receiving an input signal having a plurality of modulated carrier signals included therein, said method characterised by the steps of: producing a signal representing the demodulated message of the most dominant carrier signal of said input signal; producing a replica signal of the most dominant carrier signal; producing a first signal identical to said input signal except that said first signal is selectively delayed with respect to said input signal; combining said replica and said first signals to produce an output signal representing the input signal with the most dominant carrier suppressed; and producing from the output signal a signal representing the demodulated message of the second most dominant carrier signal of said input signal. It should be noted that the documents US-A-3 873 931 and IEEE Transactions on Communications, vol. COM. 25, no. 12, December 1977, pages 1480-1485; T. S. Sundresh et al.: "Maximum A Posteriori Estimator for Suppression of Interchannel Interference in FM Receivers" both disclose signal receiving systems for demodulating at least two FM signals contained in a composite signal. Both systems are however cross-coupled employing a frequency feedback design whereby on phase-locked loop controls the input to the other phase-locked loop and vice versa. In the present invention there is no cross-coupling between the demodulation circuits. In the present invention, capture effect associated with frequency demodulators is used in cooperation with phase-locked loops in a new demodulator to provide improved demodulation of all of several FM carriers including weaker signals in the presence of dominant carriers. A frequency demodulator converts the instantaneous frequency of the applied signal to a voltage. When the sum of two or more signals is present at the input to the demodulator of the present invention, the output voltage m o (t), is proportional to the instantaneous frequency of the dominant portion of the input signal. Thus, the dominant signal is said to capture the demodulator. When m o (t) is used to frequency modulate another sinusoid, then a replica of the original dominant signal is created in the receiver. The replica signal is now isolated from the other weaker receiver input signals and can be subtracted from the composite input to effectively suppress the dominant signal. After subtraction, weaker carriers of the input signal remain. The remaining signal then can be successively demodulated in the same way virtually as many times as desired for demodulation of as many component carriers of the input signal as desired. For effective cancellation using the present invention, the carrier frequency and the extent of modulation of the replica signal must be substantially the same as the dominant signal. In practice, it is not possible to achieve this condition using a conventional signal source and frequency modulator. However, by using a voltage-controlled oscillator (VCO) in a PLL, near exact replication of the dominant signal is possible. Thus, when the phase-locked loop is operated as a frequency demodulator, the output of the VCO is the replica of the dominant input signal to be cancelled. Recovery of weaker signal information is inherent in the design of a signal receiving system constructed according to the principles of the present invention. A plurality of output signals representing the messages contained in the modulation of a succession of dominant input signals, derived from remaining components of the original input signal in descending order of dominance, is obtainable from each phase-locked loop demodulator comprising the signal receiving system of the present invention. Consequently, this invention makes possible multiple reuse of FM bands, that is, several FM carriers having unrelated messages can coexist in the same frequency band with all or selected messages being recoverable by application of this invention. The present invention permits and includes the concept of power division multiplexing whereby a number of messages (customers) share transmitter power with each other using the same frequency band simultaneously. This concept is consistent with other well understood and implemented techniques such as time division multiplexing and frequency division multiplexing. Embodiments of the invention will now be described with reference to the drawings in which : Figure 1 is a block diagram of a signal receiving system constructed according to the principles of the present invention, Figure 2 is a block diagram of the variable delay employed in the system of Figure 1, Figure 3 is a block diagram of the variable-gain difference amplifier employed in the system of Figure 1, and Figure 4 is a block diagram of the PLL employed in the system of Figure 1. Referring to Figure 1, signal receiving system 10 comprises a plurality of PLL demodulators, each of which includes a mixer, lowpass filter (LPF) and VCO. The system further includes pluralities of variable delays and variable-gain difference amplifiers coupled, respectively, to each of the phase-locked loop demodulators as shown and further described elsewhere in this specification. With the continuing reference to Figure 1, input signal V i (t) is assumed to include many FM carrier signals of various strengths and will be described in more detail elsewhere in this specification. The receiving system of the present invention may be connected to the front end, i.e. radio frequency (RF) antenna, RF amplifier, mixer and intermediate frequency (IF) amplifier, of any conventional superheterodyne radio receiver. In such systems, the mixer down converts received RF energy into a received IF signal. Typically, the received IF signal preserves the signal-to interference ratio of the received RF energy, and the frequencies of the desired as well as interfering signals. Thus, frequency components of the RF energy are preserved in the IF signals. Phase-locked loop 11 (also referred to as PLL₁) comprises mixer 102, LPF 103 and VCO 104. One input of mixer 102 is coupled to the input signal V i (t). The output of mixer 102 is coupled to the input of LPF 103. The output of LPF 103 is coupled to the input of VCO 104 and produces message information m₁(t) demodulated from the most dominant FM signal. The output of VCO 104 is applied to another input of mixer 102 and to the input of difference amplifier 106. PLL₂, PLL₃ . . . PLL n are essentially the same circuits as that just described for PLL₁. The input signal is also applied to the input of variable delay 105. The outputs of delay 105 and VCO 104 are applied to the inputs of variable-gain difference amplifier 106. The output of amplifier 106 comprises input signal V i (t) with the most dominant carrier suppressed. Demodulation of the most dominant carrier of the output signal from amplifier 106 is provided by PLL₂. It should be noted that the most dominant carrier of the output signal from amplifier 106 is, typically, the second most dominant carrier of input signal V i (t). Since PLL₃ is substantially the same as PLL₁ and PLL₂, demodulation of the third most dominant carrier of input signal V i (t) is provided by PLL₃. The input of PLL₃ is coupled to the output of variable-gain amplifier 116. One input of variable gain amplifier 116 is coupled to the output of the VCO forming a part of PLL₂ (shown). The other input of difference amplifier 116 is coupled to the output of variable-gain amplifier 106 via delay 115. Again, the output signal from variable-gain amplifier 116 is the input signal V i (t) with the first two most dominant carriers suppressed. To the extent that the strength of the individual carriers of input signal V i (t) permit, any number of individual demodulations of the carriers of V i (t) can be obtained as each such carrier becomes dominant in later stages of the receiving system of the present invention. Thus, recovery of the information contained in the modulation of all carriers of V i (t), in descending order of dominance, is obtained. Variable delay 105 may also be merely a variable-phase shift circuit for appropriately adjusting the phase of the output from the previous stage of receiving system 10 for coherence with the output of VCO 104. Delay 105 may use operational amplifier circuit techniques in order to alter the signal phase in a precise and predictable manner. Thus, variable delay 105 may include four (4) LM-318 operational amplifier stages, where each stage has the possibility of continuously variable phase change from 0 to 90°, as shown in Figure 2. Alternatively variable delay 105 may comprise circuits or systems creating delay directly (e.g., switched capacitor filters). Variable-gain difference amplifier 107 may be any circuit suitable for combining a signal having the same amplitude and frequency as one component of another signal. Such circuits are well known and may include an LM-318 operational amplifier con figured as shown in Figure 3. Phase-locked loops, PLL₁ . . . PLL n , are conventional, each consisting of such well known components as a mixer, a lowpass filter and a reference voltage-controlled oscillator for producing a reference or replica signal. Typically, all of the components of a PLL are integrated as a single semiconductor product, such as part number 562, manufactured by Signetics, Inc., which may be used in the present invention as shown in Figure 4. When the VCO follows the frequency change of V i (t), the VCO output is the frequency of the dominant component of V i (t) because of capture effect. Input signal V i (t) is given by the following relation: V i (t) = B₁cos[ω₁t + o ∫ t m₁(a)da] +B₂cos[(ω₁ + ε₂)t + o ∫ t m₂(a)da] , , , +B n cos[(ω₁+ ε n )t + o ∫ t m n (a)da] If s₁(t) = B₁cos[ω₁t + o ∫ t m(a)da], the most dominant signal component of V i (t), and j₂(t) = B₂cos[(ω₁ + ε₂)t + o ∫ t m₂(a)da] +B₃cos[(ω₁ + ε₃)t + o ∫ t m₃(a)da] , , , +B n cos[(ω₁ + ε n )t + o ∫ t m n (a)da], remaining successively dominant signal components of V i (t), = s₂(t) + s₃(t) + --- + s n (t) then, V i (t) = s₁(t) + j₂(t). Modulation components, m₁ . . . m n , are arbitrary. Carrier frequencies, f₁, f₂ . . . f n where f k = ω₁ + ε k 2π Hz are typically in the same band. If all other components of V i (t), namely j₂(t), individually do not exceed in amplitude the carrier signal s₁(t), then the output x₁(t) of PLL₁ is equal to m₁(t) because of the capture effect of the first demodulator. Since message m₁(t) is recovered from the dominant carrier of V i (t), and since VCO 104 is a frequency modulator itself being modulated by m₁(t), then y₁(t) of Figure 1 is a replica of the dominant carrier of V i (t). Referring again to Figure 1, the delays and variable-gain 20 summers are adjusted to minimize the level of previously dominant signals present at the input of the PLL of interest. Owing to the capture effect of subsequent FM demodulator stages, complete suppression of the undesired signal components is unnecessary; i.e., it is not necessary that z k (t) equals j k (t) where z k (t) is a signal in which s k+1 (t) is the dominant component. Rather, it is only necessary that the level of S k+1 (t) merely exceed the level of all other signal components of j k (t) where k is any integer in the range 1, 2, . . . n, in order to recover information from any component of V i (t). The present invention also incorporates power division multiplexing whereby a number of messages (customers) share transmitter power with each other using the same frequency band simultaneously. This concept is consistent with other well understood and implemented techniques such as time division multiplexing and frequency division multiplexing. With reference to Figure 1, the average power of V i (t) is distributed among its components s₁(t), s₂(t), --- s N (t). The greater share of this total average power arises from s₁(t) because it is the dominant signal. Likewise, the average power of s j (t) exceeds that of s j+1 (t) where j=0,1,2,3, --, N. In this manner, the total average power is allocated to the various components of V i (t) or multiplexed among the various messages in that assigned FM band all of which is being used by each customer. Since a power lever is assigned to each user, the result is power division multiplexing in the same sense that frequency band assignment to each user is frequency division multiplexing and time slot assignment to each user is time division multiplexing. While the present invention has been particularly shown and described with respect to a preferred embodiment thereof, it should be understood by those skilled in the art that changes in form and detail may be made without exceeding the scope of the appended claims. In particular, for example, this invention may be used for phase modulated carriers as well as for FM carriers.

Claims: Signal receiving system for receiving an input signal having a plurality of modulated carrier signals included therein, said system characterized by: first demodulator means (PLL₁) for receiving the input signal, for producing a signal representing the demodulated message of the most dominant carrier signal of said input signal, and for producing a replica signal of said dominant carrier signal; delay means (105) coupled to the demodulator means (PLL₁) for receiving the input signal, and for producing a first signal identical to said input signal except that said first signal is selectively delayed with respect to said input signal; output means (106), coupled to the delay means (105) and to the demodulator means (PLL₁), for receiving and combining said first signal produced by said delay means (106) and said replica signal produced by said demodulator means (PLL₁), and for producing an output signal representing the input signal with the most dominant carrier suppressed; and second demodulator means (PLL₂) coupled to said output means (106) for receiving the output signal produced thereby, for producing a signal representing the demodulated message of the second most dominant carrier of said input signal, and for producing a replica signal of said second most dominant carrier signal. A signal receiving system as in Claim 1 characterized by: a plurality of demodulator means (PLL₁, PLL₂, PLL₃, ..., PLL N ) each for producing a signal representing the demodulated message of the next successively dominant carrier signal in said input signals, and for producing a replica signal of said next successively dominant carrier signals; a plurality of output means (105, 115, 15); and a plurality of delay means (105, 115, 15) having an input each respectively coupled to the output of one of said output means (106, 116, 16) for producing first signals identical to signals received therefrom selectively delayed with respect to said received signals; each of said plurality of output means (106, 116, 16) being coupled to one of said demodulator means (PLL₁, PLL₂, PLL₃, ..., PLL N ) and one of said delay means (106, 116, 116) for receiving and combining said first and said replica signals produced thereby, and for producing a plurality of output signals, each of said output signals having the next successively dominant carrier signal of said input signal suppressed. A method for receiving an input signal having a plurality of modulated carrier signals included therein, said method characterized by the steps of: producing a signal representing the demodulated message of the most dominant carrier signal of said input signal; producing a replica signal of the most dominant carrier signal; producing a first signal identical to said input signal except that said first signal is selectively delayed with respect to said input signal; combining said replica and said first signals to produce an output signal representing the input signal with the most dominant carrier suppressed; and producing from the output signal a signal representing the demodulated message of the second most dominant carrier signal of said input signal. The method as in Claim 3 characterized by the additional steps of: producing a plurality of signals representing the demodulated message of the next successively dominant carrier signal in said input signal; producing a plurality of replica signals of the next successively dominant carrier signals; producing a plurality of first signals identical to said input signal with the immediately preceding dominant signals suppressed, said first signals being selectively delayed with respect thereto; and combining said pluralities of replica and first signals to produce a plurality of output signals, each of said output signals having the next successively dominant carrier signal of said input signal suppressed. A signal receiving system as in claim 1 characterised by: the first demodulator means (PLL₁) being a first phase lock loop means (PLL₁) for receiving said input signal, said first phase lock loop means (PLL₁) for generating a first signal representing the demodulated message of the most dominant carrier signal of said input signal and for generating a first replica signal of said most dominant carrier signal; the delay means (105) coupled to said first phase lock loop means (PLL₁) for receiving said input signal, said delay means (105) for producing a delayed signal identical to said input signal, said delayed signal being selectively delayed with respect to said input signal; and the output means (106) coupled to said delay means (105) and to said first phase lock loop means (PLL₁) for receiving and combining said delayed signal produced by said delay means (105) and said first replica signal generated by said first phase lock loop means (PLL₁), said output means (106) for producing an output signal representing said input signal having said most dominant carrier signal suppressed; the second demodulator means (PLL₂) being a second phase lock loop means (PLL₂) coupled to said output means for receiving said output signal produced thereby and for generating a second signal representing the demodulated message of the second most dominant carrier signal of said input signal and for producing a second replica signal of said second most dominant carrier signal. The signal receiving system as in Claim 5 characterized in that said first phase lock loop means (PLL₁) comprises: mixer means (102) having first and second input ports, said input signal coupled to said first input port and said first replica signal coupled to said second input port, said mixer means (102) combining said input signal and said replica signal for producing signals representing the sum and the difference of said input and first replica signals; lowpass filter means (103) coupled to said mixer means (102) for receiving and filtering said signals produced by said mixer means (102) and for producing said first signal representing said demodulated message of said most dominant carrier signal; and oscillator means (104) coupled to said lowpass filter means (103) for generating a signal having a frequency substantially equal to the frequency of said most dominant carrier signal, said oscillator means (104) responsive to said first signal for modulating said signal for producing said first replica signal of said most dominant carrier signal. The signal receiving system as in Claim 6 characterized in that said oscillator means (104) comprises a voltage controlled oscillator. The signal receiving system as in one of the preceding Claims characterized in that said second phase lock loop means (PLL₂) comprises substantially identical components as said first phase lock loop means (PLL₁), said second phase lock loop means (PLL₂) being tuned to lock at the frequency of said second most dominant carrier signal. The signal receiving means as in one of the preceding Claims characterized in that said delay means (105) comprises a plurality of amplifier stages, each said amplifier stage providing selectable continuously variable phase change over a predetermined range. The signal receiving means as in as in one of the preceding Claims characterized in that said output means (106) comprises a variable gain differential amplifier having a first input port coupled to said delay means (105) for receiving said delayed signal and a second input port coupled to said first phase lock loop means (PLL₁) for receiving said first replica signal, said differential amplifier combining said delayed signal and said first replica signal for producing said output signal, said output signal representing said input signal with said most dominant carrier signal suppressed. A signal receiving system as in Claim 5 characterized by: a plurality of successive phase lock loop means (PLL₁, PLL₂, PLL₃, ..., PLL N ) each of said successive phase lock loop means tuned to the frequency of the next successive dominant carrier signal of said input signal, each of said successive phase lock loop means for generating a signal representing the demodulated message of the next successive most dominant carrier signal in said input signal and generating a replica signal of said next successive most dominant carrier signal: a plurality of successive output means (106, 116, 16), each said successive output means (106, 116, 16) having a first input coupled to an immediately preceding phase lock loop means and an output port coupled to a next successive phase lock means, each said output means for producing an output signal having said next successive dominant carrier signal suppressed; a plurality of successive delay means (105, 115, 15), each of said successive delay means (105, 115, 15) coupled between said output port of an immediately preceding output means and a second input port of a next successive output means, said delay means (105, 115, 15) for receiving said output signal produced by the immediately preceding output means and producing a delayed signal identical to said output signal and being selectively delayed with respect to said output signal, said delay signal coupled to said second input port of said next successive output means. Apparatus as in one of the preceding Claims characterized in that said first replica signal is given by the relation: Apparatus as in one of the preceding Claims characterized in that said first signal as given by the relation: A signal receiving system as in claim 1 for receiving a plurality of power division multiplexed, modulated carrier signals, said system characterised by: a plurality of demodulator means (PLL ₁ , PLL ₂ , PLL ₃ , ..., PLL N ) for producing a plurality of signals representing the demodulated message of the most dominant carrier signal received by each of said plurality of demodulator means (PLL ₁ , PLL ₂ , PLL ₃ , ..., PLL N ) and for producing a plurality of replica signals representative of said most dominant carrier signals; a plurality of output means (106, 116, 16); a plurality of delay means (105, 115, 15) each having an input, each respectively coupled to an output of one of said output means (106, 116, 16) for producing first signals identical to signals received therefrom selectively delayed with respect to said received signals; and each of said plurality of output means (106, 116, 16) being coupled to one of said demodulator means (PLL ₁ ,PLL ₂ , PLL ₃ , ..., PLL N ) and to one of said delay means (106, 116, 16) for receiving and combining said first signals and said replica signals produced thereby and for producing a plurality of output signals, each of said signals having the next successively dominant carrier signal of said input signal suppressed.

Inventors: MYERS GLEN A, MYERS, GLEN A.
Applicants: MYERS GLEN A, MYERS, GLEN A.
Application year: 1989
Main classification: H03D3
IPC codes: H03D3, H04J1