Optical memory circuit

Abstract: An optical memory circuit comprises two photodetectors, and an intermediate signal conductor for connecting the two photodetectors, wherein the two photodetectors and the signal conductor are connected in series in a closed circuit, and the signal conductor has such capacitance that a time constant of a potential of the signal conductor has such a large value as allows charges to be stored in the signal conductor when an optical write signal is incident on one photodetector whereas allows stored charges to be released from the signal conductor when an optical read signal is incident on the other photodetector.

Description: The present invention relates to a memory circuit having the features of the generic clause of Claim 1. Such a memory circuit is known from GB-A-2 185 165. In general, conventional semiconductor memory circuits employ transistors in each of the writing, memory and reading sections. If it is necessary to design an optical memory circuit that performs a reading and a writing operation with an optical signal, common practice is to couple a photodetector to each of the read signal and write signal input terminals in a conventional memory circuit composed of transistors. A problem with this approach is that since the memory circuit section is of a conventional type which uses transistors, the writing and reading speed are limited by the operating time of the transistor, thus making it impossible to fully exploit the advantage of using input optical signals which permit high-speed operation. It is, therefore, the object of the present invention to provide an optical memory circuit using input optical signals which permits high-speed operation. This object is solved by an optical memory circuit having the features of Claim 1. Preferred embodiments are disclosed in the dependent Claims. When light is incident on one of the two photodetectors, carriers are activated by photoelectric conversion and charges are stored in the intermediate signal conductor. Those charges are held in the intermediate signal conductor until light is incident on the other photodetector, whereupon it becomes conducting and the stored charges are released. Other and further objects, features and advantages of the invention will appear more fully from the following description taken in connection with the accompanying drawings. Fig. 1 is a circuit diagram showing an embodiment of the present invention; Fig. 2 is a perspective view showing an integrated circuit device that incorporates the above embodiment of the present invention. Fig. 1 is a circuit diagram showing an embodiment of the present invention. Shown by 1 and 2 are photodetectors for write and read modes, respectively. Each of the photodetectors 1 and 2 comprises two spaced Schottky electrodes that are disposed to face each other on a semiconductor substrate in a symmetric way. These photodetectors operate so that they become conducting only when a predetermined amount of light is incident thereon. For details of the construction of these photodetectors 1 and 2, see "Metal-Semiconductor-Metal Photodetector for High-Speed Optoelectronic Circuits" by T. Sugeta, T. Urisu, S. Sakata and Y. Mizushima in Jpn. J. of Appl. Phys., 19(1980) Supplement 19-1, pp. 459-464. The symbol marks used for the photodetectors 1 and 2 in Fig. 1 were originally conceived by the present inventors. One end of the photodetector 1 is connected to the positive electrode of a bias voltage source 3 having its negative electrode grounded. The other end of the photodetector 1 is connected to one end of the photodetector 2 via a signal conductor 7. A resetting switch 4, having one end grounded, is connected at the other end to the middle point of the signal conductor 7. The other end of the photodetector 2 is connected both to a load resistance 5, having one end grounded, and to an output terminal 6. The circuit shown in Fig. 1 will operate as follows. Because each photodetector in the circuit comprises a pair of symmetric Schottky electrodes, which is operable at either polarity of electrical bias, the polarity of the output signal is selective based on the polarity of the photodetectors. Thus, the output polarity can be changed, if desired. As long as an optical write signal S W is incident on the photodetector 1, the latter remains conducting and the potential of the signal conductor 7 is raised to a level equal to the potential of the bias voltage source 3. Thereafter, in response to a decrease in the write signal S W , the photodetector 1 becomes non-conducting and the voltage at that time is held in the signal conductor 7. If, under this condition, an optical read signal S R is incident on the photodetector 2, the latter becomes conducting and a current flows through the load resistance 5, thereby producing a signal at the output terminal 6. No output signal will be produced unless a potential has built up in the signal conductor 7 when read signal S R is incident on the photodetector 2. Thus, in the circuit being described, the signal conductor 7 is normally held at high impedance or floating potential to realize a 1-bit memory circuit. The resetting switch 4 is an optional element and may be employed, for instance, to initialize the state of memory. If necessary, a switching element incorporating a bias source may be used as the resetting switch 4 and specific examples of such element are a transistor that operates on a gate electric signal and a photodetector that operates on an optical signal. These switching elements may be replaced by a CR element having a large time constant. In this latter case, memory is held within an operating range effectively defined by the time constant. As described above, a potential storing function is realized by making the time constant of the signal conductor 7 substantially long, and in order to reset it at substantially long time constant, a transistor, etc. may be used. Fig. 2 is a perspective view showing an optical memory circuit device in which the circuit shown in Fig. 1 is actually integrated monolithically. In Fig. 2, the elements which are the same as those shown in Fig. 1 are identified by like numerals or symbols. A semiconductor substrate shown by reference numeral 11 is made of a semiconductor material such as Si or GaAs. There are provided on the surface of the semiconductor substrate 11 a photodetector 1 for write mode, a photodetector 2 for read mode, a resetting switch 4, a load resistance 5, signal conductors 7 - 9, and a grounding conductor 10. The grounding conductor 10 taken together with the signal conductors 7 - 9 form a strip line. An insulating thin film is provided between the semiconductor substrate 11 and each of the signal conductors 7 - 9 and the grounding conductor 10 except in the areas where the photodetectors 1 and 2, resetting switch 4 and load resistance 5 are formed. The photodetector 1 is formed of two Schottky junctions between the edges of the signal conductors 7 and 8 and the semiconductor substrate 11. The photodetector 2 is formed of two Schottky junctions between the edges of the signal conductors 7 and 9 and the semiconductor substrate 11. In both cases, the surface of the semiconductor substrate between the two Schottky junctions serves as a light-receiving surface. The resetting switch 4 is also constructed as a photodetector having a similar design to the photodetectors 1 and 2, that is, two Schottky junctions are formed between the edges of the signal conductor 7 and grounding conductor 10 and the semiconductor substrate 11. The load resistance 5 is a n⁺ high-density-doped region formed by doping impurities in the surface region of the semiconductor substrate 11, and opposite ends of this resistance 5 are connected to the signal conductor 9 and the grounding conductor 10. The signal conductor 8 is connected to an external bias voltage source 3 whereas the signal conductor 9 is connected to the output terminal 6. The circuit system shown in Fig. 2 will operate as follows. When an optical write signal S W is supplied to the photodetector 1, a potential of the signal conductor 7 is raised to a level equal to the potential of the bias voltage source 3. In response to a decrease in the incident write signal S W the potential at that time is held in the signal conductor 7. Thereafter, when an optical read signal S R is supplied to the photodetector 2, a current flows through the load resistance 5 and a signal is produced at the output terminal 6. When an optical reset signal S RT is incident on the photodetector 4 which is a resetting switch, the potential of the signal conductor 7 is erased to reset the overall circuit. Other designs may of course be employed to construct photodetectors, such as by forming a Schottky electrode by arranging two ohmic electrodes in a symmetric way. In the embodiment shown in Fig. 2, the load resistance 5 is formed by doping impurities into the semiconductor substrate. It should, however, be noted that this is not the only method of forming the load resistance 5 and that a film resistor may be employed. In the embodiment shown in Fig. 1 and 2, the photodetector 1 is connected to the positive electrode of the bias voltage source 3 but the device operation is in no way dependent upon the polarity of the bias voltage. As will be understood from the foregoing description, the optical memory circuit of the present invention has the advantage that it is capable of performing a memory operation on optical input signals with a simple configuration in which two photodetectors are connected in series by an intermediate signal conductor which has a time constant of potential set to an appropriately large value. In addition, the optical memory circuit of the present invention which does not use any slow active devices such as a transistor is capable of very fast memory operation. This would be a great benefit to optical wiring which is becoming popular as a means for increasing the operating speed of computers, because, with this invention, data storage processing can be accomplished with the high-speed characteristic of light being utilized to the fullest extent.

Claims: An optical memory circuit comprising a semiconductor substrate (11), two photodetectors (1,2) formed symmetrically on said semiconductor substrate (11), an intermediate signal conductor (7) connecting said photodetectors, and a bias voltage means (3) connected to one of said photodetectors (1,2) for providing a bias voltage, said photodetectors (1,2) and said intermediate signal conductor (7) being connected in series in a closed circuit, and said intermediate signal conductor (7) being provided with a predetermined potential and having a capacitance with a predetermined time constant such that charges are stored in said intermediate signal conductor (7) when a light signal is incident on one of said photodetectors (1,2) and said stored charges are released from said intermediate signal conductor (7) when said light signal is incident on the other one of said photodetectors (1,2) characterized in that each of said two photodetectors (1,2) is operable at a bias of either polarity and comprises two Schottky diodes facing each other and said bias voltage means (3) provides a bias voltage of either polarity to said intermediate signal conductor (7) through one of said photodetectors (1,2). The optical memory circuit of Claim 1 characterized in that it comprises a resetting switch (4), connected to said intermediate signal conductor (7), for resetting said predetermined potential of said intermediate signal conductor (7). The optical memory circuit of Claim 1 or 2 characterized in that said two photodetectors (1,2) and said intermediate signal conductor (7) are formed monolithically on said semiconductor substrate (11). The optical memory circuit of any of the Claims 1 to 3 characterized in that a load resistance (5) is connected to one of said photodetectors (1,2) and is formed on said semiconductor substrate (11). The optical memory circuit of any of the Claims 1 to 4 characterized in that said optical memory circuit is in the form of a strip line.

Inventors: HIROHATA TORU, IIDA TAKASHI, KAN HIROFUMI, MIZUSHIMA YOSHIHIKO, NAKAJIMA KAZUTOSHI, SUGIMOTO KENICHI, WARASHINA YOSHIHISA, HIROHATA, TORU, IIDA, TAKASHI, KAN, HIROFUMI, MIZUSHIMA, YOSHIHIKO, NAKAJIMA, KAZUTOSHI, SUGIMOTO, KENICHI, WARASHINA, YOSHIHISA
Applicants: HAMAMATSU PHOTONICS KK, HAMAMATSU PHOTONICS K.K.
Application year: 1989
Main classification: G11C11
IPC codes: G11C11, G11C7