SYNCHRONOUS LOGIC NETWORK WITH TRANSFER SIGNAL CONTROL

Abstract: In a logic network consisting of a number of cascode connected modules (TF) for processing digital signals, carry signals which propagate as a ripple signal from one module to another often represent a serious limitation as regards the magnitude of the clock frequency when it is demanded that signal outputs of the modules must be in a steady, desirable state when a clock pulse occurs. In the logic network in accordance with the invention the transport means for the carry signals comprise storage elements (DF) which are controlled by clock pulses so that the ripple signal caused by the delay of carry signals is distributed between a number of clock pulse periods, i.e. a ripple path for the carry signals is subdivided into two (three, four...) parts so that the period of time during which a ripple signal occurs is reduced by a factor two (three, four...).

Description: Synchronous logic network with transfer signal control, The invention relates to a logic network which is composed of m cascode-connected (not necessarily identical) logic modules for processing digital signals, where m is larger than or equal to 8 and where the operation of a logic module i is dependent of at least one carry signal which is generated in at least one of the modules 1, 2, ..., i-1 preceding the module i or in at least one of the modules i+1, i+2, ..., m succeeding the module i, there being provided transport means for transporting the at least one carry signal. A network of this kind, consisting of several modules, is known from United States Patent Specification No. 4,679,216. The Patent describes a synchronous counter which is composed of a number of cascode- connected jk flipflops which all receive a clock signal ck. In order to increase the counting speed of this synchronous counter, the outputs of the flipflops preceding a flipflop are connected to the input thereof via a logic AND-gate. Such a step ensures that a carry signal, arising due to a counting operation performed by a flipflop and occurring at its output need, not first activate a succession of flipflops in order to activate ultimately a flipflop situated further in the cascode connection. If the logic AND-gates were not used, the carry signal would have to propagate itself as a ripple signal through the cascode connection of the flipflops. Therefore, activation of a flipflop at the end of the cascode connection would be delayed by a number of response times equal to the number of preceding flipflops. The foregoing means that all outputs of the flipflop circuits are in a steady, desired state only after the ripple signal has reached the last flipflop in the series connection. It is only after this desired state has been reached that a next counting pulse may be applied in order to make the cascode connection of flipflop circuits perform a next counting operation. Tolerating a ripple signal in a logic network of modules in order to perform a further operation in a subsequent module in dependence of an operation executed in a preceding module substantially limits the operating speed of the logic network and hence also limits a clock pulse frequency when such a network is used in a synchronously operating digital signal processing system. In order to maintain a high speed of operation (= counting speed), according to said United States Patent the outputs of each preceding flipflop are connected to the input of a subsequent fliplfop via a logic gate circuit, so that the last flipflop in the cascode connection is activated as if it were simultaneously with the preceding flipflops. It has been found that this step is very effective and results in a counter circuit which is capable of counting pulses at a very high speed. However, if such a counter consists of a very large number of cascode-connected flipflops, the gate circuit to be added for each flipflop is also very extensive. The gate circuit ultimately appears to be a drawback because it becomes very extensive for the last flipflops of the row; this is objectionable because each bit to be added to the counting capacity requires an increasingly larger integration surface area on a semiconductor substrate with respect to the counting flipflop, so that it increasingly tends to limit the counting speed of the counter, because a logic gate is slower as its number of inputs increases. It is the object of the invention to provide a logic network consisting of a plurality of cascode-connected logic modules in which no extensive logic gate circuits are required for the processing of the higher-order bits and in which the occurrence of ripple signals is tolerated without substantial limitations being imposed as regards a clock pulse frequency by the logic network. To achieve this, a network in accordance with the invention is characterized in that the transport means comprise a cascode connection of logic elements which constitute a ripple signal path and also comprise at least one storage element, the ripple signal path being subdivided into at least two parts, a respective storage element being arranged between said parts in order to block a ripple signal which is generated by a change of the logic state of the logic network, and to conduct the ripple signal to the part of the ripple path which is connected to the output of the storage element when a next clock pulse signal is received. By adding storage elements to the transport means so that, for example after the appearance of a clock pulse for the control of the logic modules a ripple signal is blocked after having partly traversed the ripple path, a steady state is always realised despite the tolerating of transfer means in which carry signals propagate from one module to another as a ripple signal with delays so that the logic network is suitable for use in a system synchronised by means of clock pulses. The clock frequency is substantially higher than in a network in which the carry signal propagates without obstruction as a ripple signal through all parts of the transfer means. An embodiment of a logic network in accordance with the invention is characterized in that the logic modules comprise a series of series-connected flipflop circuits which constitute an asynchronous counter, the at least one storage element being arranged between two parts of the series connection, the frequency of pulses to be applied to the asynchronous counter being equal to or lower than the frequency of the clock signal, the output of a flipflop which is the last one in a part of the series connection, which output is connected to the input of the storage element, having a stable state when the clock signal occurs. This step increases the counting speed of the asynchronous counter and also enables the use of the asynchronous counter in a digital system synchronised by means of clock pulses. A preferred embodiment of a logic network in accordance with the invention is characterized in that the logic modules comprise a series connection of counting flipflop circuits which are controlled by means of the clock signal, the transport means comprising a series gate connection of a number of gate circuits, an input of each gate circuit being connected to an output of a counting flipflop circuit, a further input being connected to the output of a preceding gate circuit either directly or via a storage element. By the addition of a minimum number of components the maximum counting frequency of a synchronous counter is substantially increased. A carry signal in the sense of the invention can propagate from components which process the least-significant bits to components which process the more significant bits but also vice versa. A simple example in this respect is a comparator which compares multi- bit words and in which the comparison of two bits of the same significance can generate a carry signal which propagates optionally in the direction of the lower-order bits or in the direction of the higher- order bits (for example, in order to obtain a comparison result more quickly) . The invention will be described in detail hereinafter with reference to a diagrammatic drawing; therein Fig. 1 shows an asynchronous counter in accordance with the invention, Fig. 2 shows a synchronous counter in accordance with the invention, and Fig. 3 shows a flipflop circuit used in the counter shown in Fig. 2. Fig. 1 shows an asynchronous counter in accordance with the invention. This counter comprises a number of cascode-connected flipflops FF1, FF2, ..., FFN and a second number of cascode-connected flipflops FF21, FF22, ..., FF2H. Each of said flipflops may be a toggle- connected flipflop, the inverted output being connected to the toggle input of the next flipflop. The non-inverted outputs 11, 12, ..., Q1N of the flipflops together form a first part of the outputs of the counter and the non-inverted outputs 21, Q22, ..., Q2M of the flipflops FF2 ' 1, FF22, ..., FF2M constitute a second part of the outputs. The inverted output of the flipflop FFN is connected to the D-input of a D- flipflop DFF, the non-inverted output of which is connected to the toggle input of the flipflop FF21. A clock signal clkl is applied to the clock input c of the flipflop DFF. The counter shown in Fig. 1 is a conventional asynchronous counter whereto a D-flipflop DFF has been added. The function of the D-flipflop DFF will be described hereinafter. For a proper explanation of the foregoing it is assumed hereinafter that the D-flipflop DFF is absent. When counting pulses are applied to the input P of the flipflop FF1, after every second pulse on the input P a signal will appear on the inverted output of FF1 for control of the flipflop FF2. Depending on the state of the flipflops FF2 to FFN and the flipflops FF21 to FF2M, said carry signal will propagate more or less far in the cascode-connected flipflops as a ripple signal. Evidently, such propagation of the carry signal will require some time. This time will be longer as more flipflops are connected in cascode. If it is assumed that each flipflop causes a delay Δt, in the worst case, after the appearance of a pulse on the input P, each output signal Q11 to Q2M will be stable and have a new logic state after a delay amounting to NΔ t+M.Δt. Therefore, when the next pulse appears on the input P the outputs of the asynchronous counter will be stable only if the data transport between the flipflops occurs within a pulse period T > N.Δt + M.Δt on the input P. Consequently, as the number of cascode-connected flipflops increases, the counting frequency decreases. In accordance with the invention, in the casecode connection of the flipflops a storage element is added to the transport means which are formed by the connections between the flipflop circuits in Fig. 1. The storage element is a D-flipflop DFF which is controlled by a clock signal so that, when the next pulse P occurs, the carry signal which has passed through the counters FF1 to FFN is taken over by the D-flipflop DFF. Therefore, when the next pulse appears on the input P, all outputs Q11 to Q1N and the outputs Q21 to Q2M are stable. However, it is to be noted that the preceding pulse on the input P has not yet been taken into account for the counter position of the flipflops FF21 to FF2M. It can be deduced from the logic state of the flipflop DFF, however, that another pulse is yet to be taken into account in the logic states of the flipflops FF21 to FF2M. When the next clock signal appears on the input clkl of the flipflop DFF, a carry signal will be taken over from the flipflop FFN for supply to the cascode connection of the flipflops FF21 to FF2 . The asynchronous counter shown in Fig.1 is rendered suitable for use in a synchronously operating digital system by the addition of the flipflop DFF. This is because the asynchronous counter always has a stable state at given, fixed instants due to the use of this flipflop. Furthermore, the use of the flipflop DFF substantially, increases the maximum clock frequency of the pulses to be applied to the input P. When the flipflop DFF is arranged exactly in the centre of a cascode connection of a number of flipflops as shown in Fig. 1, i.e. so that the flipflop DFF is preceded and succeeded by the same number of further cascode-connected flipflops, the maximum clock frequency for the asynchronous counter will be increased by roughly a factor 2. It will be evident that, when an asynchronous counter is divided into three or four parts, a flipflop DFF as shown in Fig. 1 being inserted each time between the various parts, the clock frequency is increased by roughly a factor three or four, respectively. The pulses to be applied to the counting input P of the asynchronous counter shown in Fig. 1 may be conditioned with the clock signal to be applied to the D-flipflop DFF. The pulse signals to be counted could be applied to the first counting flipflop FF1 via an AND- gate, a second input of which also receives the clock signal to be applied to the D-flipflop DFF. However, it suffices when the relationship between the pulses on the P-input and the clock pulses clkl is such that the outputs of the flipflops FF1 to FFN have a stable state when the D-flipflop DFF receives a clock signal clkl . Fig. 2 shows a synchronous counter in accordance with the invention which can act as an address generator for a semiconductor memory. The counter comprises a number of counting flipflops TFO, TF1, ... TF14 and a number of AND-gates EE1, EE2, EE3 to EE14 and a further number of AND-gates TE3, TE4 to EH. The counter shown in Fig. 2 comprises an input I which is connected to the input of the counting flipflop TFO and also to an input of the AND-gates EE1 and EE2. The output of the counting flipflopf TFO is connected to a further input of the AND-gate EE1 as well as to a further input of the AND-gate EE2. The output of the counting flipflop TFO forms an address bit A0. The output of the AND-gate EE1 is connected to the input of the second counting flipflop TF1. The output of the counting flipflop TF1 orms the address bit A1 and is also connected to the third input of the AND-gate EE2. The output of the AND-gate EE2 is connected to an input of the counting flipflop TF2 and to an enable line EP whereto all further AND-gates EE3, EE4 etc. to EE1 are connected by way of a first input. The output of the counting flipflop TF2 forms the address bit A2 and a carry signal ET for the next counting flipflop TF3. This carry signal ET is applied, via the AND-gate EE3, to the input of the counting flipflop TF3. The circuit has such a regular construction that the output of the counting flipflop TFi forms the address bit Ai. Furthermore, the output of the counting flipflop TFi is connected, via a carry AND-gate TEi and an enable AND- gate EEi+1, to the input of the counting flipflop TFi+1. In this circuit the variable i can assume the values 3, 4, ... to 14. It is to be noted that not all outputs of the carry AND-gates TEi of the transport means are directly connected to the inputs of the carry gate TEi+1. As appears from the Figure, the output signal of the carry AND-gate TE5 is applied, via a storage element in the form of a flipflop DF1, to the carry AND- gate TE6. Similarly, the output of the AND-gate TE8 is applied, via a similar storage element, i.e. the flipflop DF2, to the AND-gate TE9 and the output of the AND-gate TE11 is applied, via a similar storage element, i.e. the flipflop DF3, to the input of the AND-gate TE12. The flipflop circuits used in Fig. 2, i.e. the counting flipflops TFO to TF14, will be described in detail hereinafter with reference to Fig. 3. The operation of the synchronous counter shown in Fig. 2 is as follows. The flipflops used in Fig. 2 all receive a clock signal elk. The counter flipflops TFO to TF14 are so-called toggle flipflops, the pipeline flipflops DF1, DF2 and DF3 being so-called D-flipflops. For as long as the input signal on the input i is high, the logic value of the output of the flipflop TFO will change in response to each clock pulse. The flipflop TFO, therefore, is a one-bit counter. The combination of the flipflops TFO, TF1, TF2 and the AND-gates EE1 and EE2 constitutes an eight-bit counter. The input I is connected, either directly or via a single AND-gate EE1 or EE2, to the inputs of the flipflop TFO, TF1 and TF2, so that the counting operations in these flipflops take place substantially in parallel. A counting flipflop TFi (where i = 3, 4, 5, 6) will change the logic value of its output signal when a clock signal is received if the output signal of the AND-gate EEi is logic high. The output signal of the AND-gate EE2 should then be logic high, the output signals of the preceding counting flipflops TF3, ..., TFi-1 should also be logic high, like the output of the counting flipflop TF2. This is because the output of the AND-gate EE2 is applied to all AND-gates EE3 to EE14, like the output signal of the counting flipflop TF2, be it that the latter signal is applied, via the series connection of the AND-gates TE3, TE4 etc. to the relevant AND-gates EE4, EE5 etc. In the worst case, via the transport means which all comprise AND-gates, a carry signal would propagate via the series connection of the AND-gates TE3 to TE14 if no D-flipflops DF1, DF2, DF3 were included in this series connection. In order to preclude the occurrence of undesirable logic states on the counting outputs A0 to A14 in response to a next clock pulse, a next clock signal should occur only after the output signal of the counting flipflop TF2 has traversed all AND-gates TE3 to TE14. This substantially limits the counting speed of the synchronous counter. However, a carry signal which traverses the AND- gates TE3, TE4, TE5 as a ripple signal is now taken over by the D- flipflop DF1 in response to the next clock signal, and is only subsequently applied to the following AND-gates TE6, TE7 etc. In response to the subsequent clock signal the carry signal is stored in the D-flipflop DF2 so that it is only subsequently applied to the subsequent AND-gates TE9 to TE11 etc. As a result of the addition of storage elements in the form of D-flipflops DF1, DF2 and DF3 to the transport means, a steady, desirable logic state is always ensured on the address output terminals AO to A1 , despite the high frequency of a clock signal. As a result of the described step the delay incurred by carry signals while traversing the AND-gates TE3 to TE14 is distributed over a number of clock periods. This enables a high clock frequency. Various groups can be distinguished in the counter shown in Fig. 2. A first group actually operates in parallel and comprises the counting flipflops TFO, TF1 and TF2 which, having only one gate delay, hardly influence the counting speed. A second part concerns a series connection of a number of counting flipflops TF3 to TF14 and a number of AND-gates TE3 to TE14 via which a carry signal must propagate. A carry signal is admitted to a next counting flipflop TFi via a gate EEi by an enable signal on the enable line EP, which enable signal is applied in parallel to all access AND-gates EE3 to EE14. The construction of the synchronous counter shown has the following consequences. The counter itself is very well suitable for use in a synchronous timing organisation. A very high counting frequency equal to the clock frequency can be achieved for as long as the delay incurred by the carry signals in the various parts TE3, 4, 5 and DF1, EE3, 4, 5 6; TE6, 7, 8 and DF2, EE7, 8, 9; TE9, 10, 11 and DF3, EE10, 11, 12 of the transport means is less than the clock pulse period. Apart from the series connection of the counting flipflops TFi, hardly any further hardware in the form of logic gates and further flipflops is required and the number of interconnections is limited. Consequently, the counter can be extended so as to form a counter for a larger number of bits. The various parts of the counter, to be distinguished as the parallel part and the serial part which are separated from one another by the pipeline flipflops DF1, DF2, DF3, always contain a correct counting code. It can be simply indicated that a counter has reached its full count and hence enters an overflow state. The pipeline flipflops DF1, DF2, DF3 do not require reset facilities. The counting procedure can be stopped as desired and can be subsequently resumed without any problems. The counting direction can be reversed without problems, as will be described hereinafter, and the setting of an arbitrary counting position of the counter must be followed by a waiting period amounting to a number of clock periods equal to the number of pipeline flipflops, in this case DF1 to DF3. This condition is not applicable when the new position of the counter implies that the modules of the first group, whose carry signal is generated after the second group, start in the very first state of the counting cycle. This is because the enable signal EP dominates the serial transport in the serial group. The number of flipflops in the parallel part should be such that the counting cycle of the parallel part is larger than or equal to the number of the pipeline flipflops DF of the transport means. Fig. 3 shows a flipflop TFi of Fig. 2. This flipflop TFi comprises a first EXCLUSIVE-OR gate E01, a second EXCLUSIVE-OR gate E02 and a D-flipflop DF. A first input of the EXCLUSIVE-OR gate E01 constitutes the input of the flipflop TFi. The output of the EXCLUSIVE- OR.gate E01 is connected to the D-input of the flipflop DF. The output of the flipflop DF is connected to a first input of the EXCLUSIVE-OR gate E02 and also to the second input of the EXCLUSIVE-OR gate E01. The flipflop DF shown forms, together with the EXCLUSIVE-OR gate E01, a flipflop which is connected as a toggle. The output of the EXCLUSIVE-OR gate E02 constitutes the output of the flipflop TFi. The second input of the EXCLUSIVE-OR gate E02 determines the counting direction of the synchronous counter shown in Fig. 2. This second input of the EXCLUSIVE- OR gate E02 of the flipflop TFi, of course, is connected to inputs of the EXCLUSIVE-OR gates E02 of the other flipflops TFi of the counter shown in Fig. 2. For the described embodiments use is made of asynchronous and synchronous counting circuits for the purpose of illustration of the invention. However, the invention can also be used in logic circuits in which operations other than counting operations are performed, for example, addition and multiplication operations (parallel adders, multipliers, etc.). When the invention is used in such circuits, the effective speed of operation will be lower than the maximum speed that can be achieved by means of the clock pulse frequency. However, the effective speed of operation will be substantially higher than a speed of operation to be achieved in, for example a parallel adder in which carry signals can propagate through all adder modules as a ripple signal. An adder circuit in accordance with the invention could be organised as follows. The parallel adder could perform an addition in three steps under the control of clock pulses, a first part of the adder adding two groups (for example, having a width of 8 bits) of least- significant bits and comprising transport means for the propagation of carry signals. The duration of propagation of the carry signals should be shorter than the inverse of the clock pulse frequency. A carry signal, if any, to be assigned to a more-significant bit is stored in a storage element in response to a next clock pulse; this element applies the carry signal to the transport means of a second part of the adder. In response to said next clock signal, two groups of bits having a higher significance are also added in the second part (for example, bits 9 to 16 of words having a width of 24 bits). Similarly, a carry signal, if any, generated in the second part of the adder is applied to a third part of the adder in response to the subsequent clock pulse, which third part adds the groups of most-significant bits. The foregoing illustrates that a stable, desired state always occurs on the outputs of the three parts, but that the complete result of the addition becomes available only after the third clock pulse. However, in the case of cumulative addition the first part of the adder can already add a part of a next 24 bit word to its content, the second part of the adder adding the central part of the preceding word to be added. This pipeline effect increases the effective speed of operation again.

Claims: Claims : 1. A logic network which is composed of m cascode-connected (not necessarily identical) logic modules for processing digital signals, where m is larger than or equal to 8 and where the operation of a logic module i is dependent of at least one carry signal which is generated in at least one of the modules 1, 2, ..., i-1 preceding the module i or in at least one of the modules i+1, i+2, ..., m succeeding the module i, there being provided transport means for transporting the at least one carry signal, characterized in that the transport means comprise a cascode connection of logic elements which constitute a ripple signal path and also comprise at least one storage element, the ripple signal path being subdivided into at least two parts, a respective storage element being arranged between said parts in order to block a ripple signal which is generated by a change in the logic state of the logic network, and to conduct the ripple signal to the part of the ripple path which is connected to the output of the storage element when a next clock pulse signal is received. 2. A logic network as claimed in Claim 1 , characterized in that the at least one storage element is a flipflop circuit controlled by means of clock pulse signals. 3. A logic network as claimed in Claim 2, characterized in that the logic modules comprise a series of series connected flipflop circuits which constitute an asynchronous counter, the at least one storage element being arranged between two parts of the series connection, the frequency of pulses to be applied to the asynchronous counter being equal to or lower than the frequency of the clock signal, the output of a flipflop which is the last one in a part of the series connection, which output is connected to the input of the storage element, having a stable state when the clock signal occurs. 4. A logic network as claimed in Claim 2, characterized in that the logic modules comprise a series connection of counting flipflop circuits which are controlled by means of the clock signal, the transport means comprising a series gate connection of a number of gate circuits, an input of each gate circuit being connected to an output of a counting flipflop circuit, a further input being connected to the output of a preceding gate circuit either directly or via a storage element. 5. A logic network as claimed in Claim 4, characterized in that the output of a counting flipflop is connected, via a gate circuit of the series gate connection and via a further gate circuit, to a next counting flipflop arranged in the series connection, a second input of said further gate circuits being connected to the input of the counting flipflop circuit whose output is connected to the first gate of the series gate connection of gate circuits. 6. A logic network as claimed in Claim 5 r characterized in that the logic gate circuits perform an AND function. 7. A logic network as claimed in Claim 4, 5 or 6, characterized in that each counting flipflop circuit comprises a toggle flipflop and an EXCLUSIVE-OR gate, an input of the toggle flipflop constituting the input of the counting flipflop, the output of the EXCLUSIVE-OR gate constituting the output of the counting flipflop and the output of the toggle flipflop being connected to an input of the EXCLUSIVE-OR gate, all second inputs of the EXCLUSIVE-OR gates being interconnected.

Inventors: DEKKER ROBERTUS WILHELMUS CORN, THIJSSEN ALOYSIUS PETRUS, VINK HENDRIK ADRIANUS, DEKKER, ROBERTUS, WILHELMUS, CORNELIS, THIJSSEN, ALOYSIUS, PETRUS, VINK, HENDRIK, ADRIANUS
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1989
Main classification: H03K23
IPC codes: H03K23