Metal insulator semiconductor type dynamic random access memory device

Abstract: A dynamic random access memory device includes a substrate (11), a plurality of paris of sources (21, 32) and drains (25) of transistors formed in the substrate and located within an area defined by field oxidation films (29) formed on the substrate. Gate electrodes (24) are formed on gate oxidation films (32) formed on the substrate and located between the pairs of sources and drains. The gate electrodes extend in a first direction (Y) perpendicular to the direction of a channel formed between the paired source and drain. A plurality of word lines (22) are formed on the field oxidation films and extend in a second direction (X) identical to the direction of the channel. The word lines are integrally formed with the gate electrodes (24). A plurality of bit lines (21) are formed in the substrate and include the sources as portions thereof. The bit lines extend in the first direction perpendicular to the direction of the channel. An insulating film (30) covers the word lines and the gate electrodes, and includes contact holes. A plurality of storage capacitors (26, 27, 28) each make connect with related one of the drains through related one of the contact holes formed in the insulating film. Each of the storage capacitors includes a storage electrode (26) extending above related one of the gate electrodes, related one of the word lines and the field oxidation films, a dielectric film (28) surrounding the storage electrode, and an opposed electrode (27) so as to cover the dielectric film.

Description: The present invention generally relates to a metal insulator semiconductor type memory device, and particularly to a metal insulator semiconductor type dynamic random access memory device having stacked capacitor type memory cells. More particularly, the present invention relates to improvements on the structure and layout (arrangement) of memory cells. A one-transistor one-capacitor type memory cell is widely used as a memory cell of a metal insulator semiconductor type dynamic random access memory (hereafter simply referred to as a MIS type DRAM or just DRAM). Currently, a 1-Mbit DRAM and a 4-Mbit DRAM are available. It is required to reduce the cell size per one bit to achieve the integration density equal to or more than 1 Mbits. A trench type memory cell and a stacked capacitor type memory cell have been proposed in order to reduce the cell size per one bit. A trench type memory cell is a cell in which a capacitor, which is a structural element of a memory cell, is formed in a silicon substrate. A stacked capacitor type memory cell is a cell in which a capacitor is formed above a silicon substrate. Referring to FIG.1, there is illustrated the structure of a conventional DRAM. The illustrated DRAM includes a memory cell array 1, which is made up of a plurality of memory cells arranged in a matrix form. The DRAM includes an address buffer 2, a row decoder 3, a column decoder 4, a sense amplifier 5, and a data output buffer 6. Those elements form peripheral circuits of the memory cell array 1. In the illustrated DRAM, it is not reasonable that we try to enhance the integration density of the illustrated DRAM at the expense of electrical characteristics of memory cells. Similarly, it is not reasonable that we try to improve electrical characteristics of memory cells at the expense of the integration density. This means that we should research and develop DRAM devices by taking account of not only the memory cell array 1 but also the peripheral circuits such as the row decoder 3, column decoder 4 and the sense amplifier 5. FIGS.2A and 2B illustrate equivalent circuits each showing the connection between the sense amplifier 5 and the memory cell array 1. FIG.2A relates to the folded bit line type, and FIG.2B relates to the open bit line type. In FIGS.2A and 2B, MC is a memory cell formed in the memory cell array 1, and S/A is a sense amplifier which is formed in the sense amplifier 5 and is provided for each pair of bit lines BL and BL . As shown, bit lines BL ( BL ) and word lines WL in conventional MIS type DRAMs are arranged so as to form a mesh. One memory cell MC is provided at an intersection of one bit line BL ( BL ) and one word line WL. The folded bit line type DRAM has a pair of bit lines BL and BL which are folded at an associated sense arrplifier S/A and which extend in parallel. The open bit line type DRAM has a pair of bit lines BL and BL which extend respectively opposite directions from an associated sense amplifier S/A. Generally, the sense amplifier S/A includes two transistors forming a flip-flop with respect to a pair of bit lines BL and BL . On the other hand, the row decoder 3 includes one transistor for one word line WL. Therefore, the size of the sense amplifier 5 is necessarily larger than the size of the row decoder 3, and thus the design of the sense amplifier 5 is complicated. The bit line pitch (the distance between adjacent bit lines) must match the sense amplifier pitch (the distance between adjacent sense amplifiers S/A). Such matching is achieved in the folded bit line type with ease, as compared with the open bit line type. This will be seen from FIG.2A. That is, one sense amplifier S/A is arranged in the space occupied by two bit lines BL1 and BL2 ( BL1 and BL2 ). On the other hand, in the open bit line type, one sense amplifier S/A must be positioned within a single pitch of the bit lines. Therefore, as the size of the memory cells MC are reduced it becomes difficult to form one sense amplifier S/A within that single pitch of the bit lines. This means that the bit line pitch must be selected based on the size of the sense amplifiers S/A. In other words, the size of DRAM devices greatly depends on the size of the sense amplifiers S/A (not the size of memory cells MC). If it becomes possible to match the sense amplifier pitch and the bit line pitch without increasing the entire size of the memory cell array 1, an increased integration density can be obtained. This can also provide a higher freedom in the design of peripheral circuits. The inventor knows some proposals for overcoming the above-mentioned problems. For example, the following paper discloses an improved open bit line type memory cell configuration: M. Koyanagi et al. "Novel High Density Stacked Capacitor MOS RAM", Japn. J. Appl. Phys. Vol.18 (1979), Supplement 18-1, PP.35-42. FIG.3A is a plan view of a memory cell configuration disclosed in the above-mentioned paper, and FIG.3B is a sectional view taken along lines III B -III B . The memory cell includes sources 201, drains 202, storage electrodes 203, opposed electrodes 204, insulating (dielectric) films 205, contact holes 206, bit lines 211, and word lines 212. The illustrated structure employs the above-mentioned stacked capacitor type memory cells. Although the proposed structure provides a field effect transistor (FET) of a reduced size, it is too small to match the sense amplifier pitch and the bit line pitch. In other words, the element density of a memory device greatly depends on the size of the sense amplifiers, as compared with the size of the memory cells. Another improvement has been proposed in Japanese Laid-Open Patent Application No. 61-183955. This proposal intends to enhance the integration density by improving the arrangement (layout) of peripheral circuits. In the proposal, bit lines extending in opposite directions from a sense amplifier are arranged in an interdigital arrangement. With this arrangement, the sense amplifier pitch is doubled. However, an increased density of memory cells is not expected. Generally, it is desired that the capacitance value of a capacitor of a memory cell is as large as possible. This is because a large cell capacitance stabilizes the operation of the memory cell and provides increased immunity to soft errors. For these reasons, it is desired to efficiently and effectively utilize an area assigned to a memory cell. However, in the configuration of FIG.3B, bit lines 211 are formed after forming storage electrodes 203. This makes it difficult to efficiently and effectively utilize the area assigned to memory cells. Another stacked-type capacitor memory cell, disclosed in IBM Technical Disclosure Bulletin Vol. 15, No. 12, May 1973, pages 3585-3586, includes an FET transistor having a source and a drain formed in a substrate and also having, between the source and drain, a gate electrode which extends perpendicularly to the direction of the transistor channel. The gate electrode is formed as part of a first polysilicon layer which is spaced from the substrate by an insulation layer. A storage electrode of the cell is formed from a second polysilicon layer, formed above the first polysilicon layer and separated therefrom by an oxide layer, which has a portion that contacts the transistor drain via a contact hole formed in the oxide and insulation layers. A part of the storage electrode overlies the FET transistor to obtain high integration density. A dielectric film covers the storage electrode and a metal layer, serving as an opposed electrode, covers the dielectric film. A different stacked-type capacitor memory cell is disclosed in EP-A-0191612, in which the bit lines extend, in the direction of the transistor channels, entirely above the storage capacitors, making contact with the transistor sources via contact holes. A DRAM disclosed in US 3387286, on the other hand, has buried bit lines, portions of which serve as sources of the FET transistors of the different memory cells. Word lines extend perpendicularly to the bit lines and have laterally-projecting portions, perpendicular to the word lines, that serve as gate electrodes of the FET transistors. However, in this DRAM the storage capacitors are of the planar type, rather than the stacked type. According to the present invention there is provided a dynamic random access memory device including: a substrate; a plurality of FET transistors arrayed at a main face of the substrate in the form of a matrix, each transistor being located in an area delimited by portions of a field oxidation layer, formed at the said main face, and having a source and a drain formed in the said substrate and also having, between the source and drain, a gate electrode formed on a gate oxide film which is formed on the said main face and separates the gate electrode from the substrate, the respective source-drain channels of the transistors all extending in a first direction; a plurality of word lines formed on the said field oxidation layer and extending longitudinally in the said first direction, the word lines being arranged such that portions thereof which overlie the said respective source-drain channels of the transistors serve as the respective gate electrodes of the transistors, and having contact holes in register with respective drains of the transistors; a plurality of bit lines extending longitudinally in a second direction perpendicular to the said first direction, each of the transistor sources being connected to one of the bit lines, and the spacing between adjacent bit lines being greater than the spacing between adjacent word lines; an insulating film formed over the said word lines and also extending over sidewalls of the said word lines bounding the said contact holes and over parts of the said drains within those contact holes; a plurality of storage capacitors, each including a storage electrode which extends, in the said first direction, substantially from one bit line to the next and which contacts an associated one of the transistor drains via one of the said contact holes and which has parts that extend above the word line having that contact hole and above the said field oxidation layer, and each also including a dielectric film covering the said storage electrode; and an opposed electrode covering the respective dielectric films of the said storage capacitors. In such a device the bit line pitch can be increased without increasing the size of the memory cell matrix, and matching of the bit line and sense amplifier pitches can be achieved. In a device embodying the present invention the bit lines may be formed in the substrate at the said main face thereof, portions of the bit lines serving as the sources of the transistors. Alternatively, the bit lines may be formed on the said insulating film, that film having contact holes in register with respective sources of the transistors, through which holes the bit lines contact the sources. Reference will now be made, by way of example, to the accompanying drawings, in which: FIG.1 is a schematic block diagram of a dynamic random access memory (DRAM); FIGS.2A and 2B are views illustrating respectively two different possible ways of connecting sense amplifiers and bit lines in a DRAM; FIG.3A is a plan view of parts of a conventional DRAM; FIG.3B is a sectional view taken along lines III B -III B shown in FIG.3A; FIG.4A is a plan view of parts of a DRAM not embodying the present invention; FIGS.4B and 4C are sectional views taken along lines IV B -IV B and IV C -IV C shown in FIG.4A, respectively; FIGS.5A through 5E are sectional views, taken along the lines IV B -IV B shown in FIG.4A, at different stages in a manufacturing process for the Figure 4 DRAM; FIG.6A is a plan view of parts of a DRAM according to a first embodiment of the present invention; FIGS.6B and 6C are sectional views taken along lines VI B -VI B and VI C -VI C shown in FIG.6A; FIGS.7A through 7E are sectional views, taken along the lines VI B -VI B shown in FIG.6A, at different stages in a manufacturing process for the Figure 6 DRAM; FIGS.8A through 8E are sectional views, taken along the lines VI C -VI C shown in FIG.6A, at the different stages in the Figure 7 process; FIG.9A is a plan view of parts of another DRAM not embodying the present invention; FIG.9B is a sectional view taken along lines IX B -XI B shown in FIG.9A; FIG.9C is a sectional view taken along lines IX C -IX C shown in FIG.9A; FIGS.10A through 10F are sectional views taken along the lines IX B -IX B shown in FIG.9A, at different stages in a manufacturing process for the Figure 9 DRAM; FIG.11A is a plan view of parts of a DRAM according to a second embodiment of the present invention; FIG.11B is a sectional view taken along lines XI B -XI B shown in FIG.11A; FIGS.12A through 12G are sectional views,taken along the lines XI B -XI B shown in FIG.11A , at different stages in a manufacturing process for the Figure 11 DRAM: FIGS.13A and 13B are sectional views illustrating alternative manufacturing steps that can be used in the process shown in FIGS.12A through 12G; FIG.14 is a table presenting exemplary parameter values for the first and second embodiments, and also for the DRAMs of Figs. 4 and 9 and for conventional open bit line and folded bit line types; FIG.15A is an enlarged schematic plan view illustrating dimensions of a memory cell used in the DRAM of Figure 4; FIG.15B is an enlarged schematic plan view illustrating dimensions of a memory cell used in the first embodiment of the present invention; FIG.15C is an enlarged schematic plan view illustrating dimensions of a memory cell used in the DRAM of Figure 9; FIG.15D is an enlarged schematic plan view illustrating dimensions of a memory cell used in the second embodiment of the present invention; FIG.15E is an enlarged schematic plan view illustrating dimensions of a memory cell used in a conventional folded bit line type DRAM; and FIG.15F is an enlarged schematic plan view illustrating dimensions of a memory cell used in a conventional open bit line type DRAM. A description is first given with reference to Figs. 4A through 4C of a DRAM which does not embody the present invention but which none the less has features of its structure and method of production in common with embodiments of the present invention, the description of which features will be of assistance in understanding the embodiments of the present invention. The DRAM device illustrated in Figures 4A to 4C includes a semiconductor substrate 11 such as a p-type silicon substrate, bit lines (BL) 21, word lines (WL) 22, contact holes 23, gates 24, drains 25, storage electrodes 26, an opposed electrode 27, insulating layers 28, field oxidation layers 29, and insulating films 30. As will be described later, the bit lines 21 partially include sources. The channel of a transistor in the Figures 4A to 4C DRAM extends in the same direction (X direction) as that in the conventional DRAM device shown in FIGS.3A and 3B. However, in the DRAM of Figures 4A to 4C, unlike in the conventional DRAM device shown in FIGS.3A and 3B, the bit lines 21 extend in the Y direction and the word lines 22 extend in the X direction. That is, the bit lines 21 extend in the direction perpendicular to the direction of the channel of a transistor, and the word lines 22 extend in the same direction as the channel. On the other hand, the bit lines BL of the conventional DRAM device of Figures 3A and 3B extend in the X direction, and the word lines WL extend in the Y direction. In the DRAM of Figures 4A to 4C, the bit line pitch is larger than the word line pitch. As a result of this arrangement, it is possible to match the bit lines 21 and the arrangement of peripheral circuits such as a sense amplifier. Essential features of the Figures 4A to 4C DRAM in addition to the above-mentioned feature are as follows. First, in FIG.4A, opposed ends of each of the storage electrodes 26 extend up to the vicinity of the bit lines 21. This means that the storage electrode 26 utilizes the cell area efficiently and effectively. Secondly, as is clearly shown in FIG.4B, the bit lines 21 are formed in the semiconductor substrate 11. That is, the bit lines 21 are formed by buried layers. Further, the bit lines 21 have portions which function as sources of transistors for transferring data. Each of the bit lines 21 is alternatively connected to the sources of the transistors arranged on both the side of the bit line 21. The drains 25 are formed at the same time as the sources or bit lines 21. The gates 24 are formed on a gate oxidation film provided on the semiconductor substrate 11. The gates 24 and the word lines 22 are integrally formed of a conductive material such as impurity-doped polysilicon, or conductive polysilicon. The gates 24 extend in the Y direction from the word lines 22. The storage electrodes 26 are electrically coupled to the corresponding drains 25. The storage electrodes 26 form storage (stacked) capacitors together with the insulating films 28 and the opposed electrode 27, which covers the entire device surface. The field oxidation films 29 define element regions (active regions). The insulating layers 30 electrically separate the storage electrodes 26 from the gate electrodes 22 and the active regions. It is noted that in FIG.3B, the bit line 211 formed above the storage electrodes 203 has an elevational portion which makes contact with the source 201. Therefore, it is impossible to greatly spread a wing of the storage electrode 203 above the transfer transistor. In Figure 4, on the other hand, the bit lines 21 are formed in the substrate, and therefore it is possible to greatly extend the storage electrodes 26 up to the vicinity of the bit lines 21. Therefore, the cell area measured in the X-Y plane is efficiently and effectively utilized with less wasteful area. This presents an increased capacitance value of the storage capacitor, and greatly contributes to the stabilization of the DRAM memory operation and an improvement on immunity to soft errors. Sense amplifiers (not shown) are arranged in the X direction. A description is given of a method for producing the above-mentioned DRAM device with reference to FIGS.5A through 5E. It is noted that materials and dimensions described below are just examples and may be replaced with different materials and dimensions known by those skilled in the semiconductor field. FIGS.5A through 5E relate to sectional views along the lines IV B -IV B observed at different manufacturing steps. Referring to FIG.5A, the field oxidation films 29 made of silicon dioxide (SiO₂) are formed on the p-type silicon substrate 11 by a conventional selective oxidation process. Then, an n⁺-type layer serving as one bit line 21 is formed in the silicon substrate 11 by a selective ion injection process in which arsenic (As) ions are introduced with a dose of 4 x 10¹⁵ cm⁻² and an injection energy of 60 keV. It is noted that the bit line 21 extends in the Y direction and includes a portion serving as a source. Of course, a conventional mask process and photolithography process are carried out for forming the bit lines 21. Next, as shown in FIG.5B, the gate oxidation film 31 is formed on the silicon substrate 11 by a conventional thermal oxidation process. Thereafter, by a chemical vapor deposition (CVD) process, a polysilicon layer is deposited to a thickness of 1000 angstroms (1 angstrom = 0.1 nm), and subsequently a tungsten silicide (WSi) layer is deposited to a thickness of 1500 angstroms. Then the two stacked layers are patterned by a photolithography process to thereby form the word lines 22 which extend in the X direction, and the gate electrodes 24 extend in the Y direction. Then, as shown in FIG.5C, the source 21 and drain 25 are formed in the silicon substrate 11 by a selective ion injection process in which arsenic ions are introduced into the silicon substrate 11 with a dose of 1 x 10¹⁵ cm⁻² and an acceleration voltage of 60 keV. In this ion injection process, an n⁺-type layer 32 is formed, which is a part of the source including the n⁺-type layer 21. It is noted the source 21 and drain 25 are self-aligned with respect to the gate 24. The impurity density values of the source 21 and drain 25 are lower than the impurity density of the gate 24. Thereafter, as shown in FIG.5D, the insulating film 30 having a thickness of 1000 angstroms is formed on the entire surface of the silicon substrate 11 by the CVD process, and is then subjected to a patterning process. Thereafter, by a reactive etching process, a contact hole 39 is formed in the insulating film 30 and the gate oxidation film 31 so that the drain 25 is partially exposed. Then, a polysilicon film is deposited to a thickness of 1000 angstroms by the CVD process, and is then subjected to a selective ion injection process where arsenic ions are introduced therein with a dose of 1 x 10¹⁵ cm⁻² and an acceleration voltage of 50 keV. Thereby, the polysilicon film is provided with the n⁺-type conductivity. Thereafter, the storage electrodes 26 are formed from the polysilicon film by the photolithography process. After that, as shown in FIG.5E, the exposed surfaces of the storage electrodes 26 are subjected to a thermal oxidation process so that an insulating film (dielectric film) 28 of a thickness of 100 angstroms is deposited the exposed surface of each of the storage electrodes 26. Then, a polysilicon film is deposited to a thickness of 1000 angstroms by the CVD process. Then, phosphorus oxychloride (POCl₃) is thermally diffused into the above-mentioned polysilicon film. Thereby, the opposed electrode 27 is formed. It is noted that a patterning process is not required to form the opposed electrode 27. Finally, a well-known process is carried out in order to complete an element and prevent the surface of the device from being activated by the deposition of a passivation film, for example. A description is now given of a first embodiment of the present invention with reference to FIGS.6A through 6C. Bit lines 51 are impurity-diffused layers formed in a semiconductor substrate 50 such as a p-type silicon substrate, and each bit line has portions serving as sources of transistors. Word lines 52 are impurity-diffused layers formed in the semiconductor substrate 50. The word lines 52 have portions serving as gates of transistors, and are formed above the transistors. It can be seen from FIGS.6B and 6C that the word lines 52 are electrically insulated from gate oxidation films 62 and field oxidation films 59. Top surfaces of the word lines 52 are covered by an insulating film 60. Contact holes 53 are formed in each of the word lines 52 so as to partially expose drains 55. The sidewall of each of the contact holes 53 is covered with the insulating film 60. A storage electrode 56 is provided in the contact hole 53, and makes contact with the related drain 55. As is shown in FIG.6C, since each word line 52 is wider than the diameter of each contact hole 53, the word line 52 is prevented from being electrically disconnected even after forming the contact holes 53. Storage electrodes 56 are provided on the insulating film 60 and are spread in a maximum of the permitted cell area. The storage electrodes 56 form capacitors together with insulating films 58 and an opposed electrode 57. The first embodiment has the following features. First, the storage electrodes 56 are self-aligned with respect to the word lines 52 and make contact with the related drains 55. Secondly, the word lines 52 extending in the X direction are laid above the transistors for transferring data. With this arrangement, the word line pitch can be further reduced as compared with the DRAM OF Figures 4A to 4C. Correspondingly, it becomes possible to further reduce the area of each memory cell and increase the element density. The width of each of the word lines 52 is almost the same as that of each of the storage electrode 56. Moreover, it should be appreciated that in addition to the above-mentioned features, the first embodiment has the essential feature of the DRAM OF Figures 4A to 4C that the bit line pitch is larger than the word line pitch. Thereby, the memory cells of the first embodiment match the peripheral circuits. It is noted that in the DRAM of Figures 4A to 4C, the word lines 22 are not located above the transfer transistors but arranged between the transistors. A description is given of a method of producing the first embodiment with reference to FIGS.7A through 7E and FIGS.8A through 8E. FIGS.7A through 7E are sectional views which are taken along the lines VI B -VI B shown in FIG.6A and are observed at different manufacturing steps. FIGS.8A through 8E are sectional views which are taken along the lines VI C -VI C shown in FIG.6A and are observed at different manufacturing steps. Referring to FIGS.7A and 8A, the field oxidation films 59 are formed on the p-type silicon substrate 50. Then, an n⁺-type diffusion layer 54 serving as a bit line and including portions of the sources, and an n⁺-type diffusion layer 55 serving as drains 55 are formed in the silicon substrate 50 by the selective ion injection process. Next, as shown in FIGS.7B and 8B, a gate oxidation film 62 is formed on the silicon substrate 50 by thermal oxidation. Subsequently, the word line 52 which also serves as a gate electrode, is formed. Then, as shown in FIGS.7C and 8C, a silicon dioxide film 60 is deposited and is then etched by the reactive ion etching process so as to form the contact hole 53, which penetrates the silicon dioxide film 60 and the gate oxidation film 62. Thereafter, in FIGS.7D and 8D, a thermal oxidation film having a thickness of 200 angstroms is formed on the exposed surface of the drain 53 and the entire surface of the silicon substrate 50. Further, an oxidation film made of silicon dioxide is deposited to a thickness of 1000 angstroms by the CVD process. Thereafter, the latter oxidation film is subjected to reactive ion etching. Thereby, an oxidation film 63 is left around the sidewall of the contact hole 53. In the following description, the oxidation films 60 and 63 are simply referred to as the oxidation film 60. Then, as shown in FIGS.7E and 8E, the storage electrode 56 is formed in the same way as the storage electrode 26 of the DRAM of Figures 4A to 4C. Thereafter, the dielectric film 58 and the opposed electrode 57 are sequentially formed as in the case of the DRAM of Figures 4A to 4C. A description is now given with reference to Figs. 9A through 9C of another DRAM not embodying the present invention. The explanation given below of the features of this DRAM will also be useful in understanding embodiments of the present invention. The DRAM of Figures 9A to 9C includes a p-type silicon substrate 80, bit lines 81, word lines 82, sources 84, drains 85, and gate electrodes 92. The drains 85 are electrically coupled with related storage electrodes 86 through related contact holes 83, and form storage capacitors together with dielectric films 88 and an opposed electrode 87. Reference numerals 88, 89, 90 and 91 indicate insulating films. The Figures 9A to 9C DRAM has an essential feature that the bit lines 81 are formed by conductive films laid on the insulating film 90, and are in contact with the related sources 81. The arrangement of the bit lines 81 contributes to a decrease of the area of a p-n junction formed in the semiconductor substrate 80, as compared with the Figures 4A to 4C DRAM and with the first embodiment, and therefore α particles induced soft errors can effectively be suppressed. A description is given of a method of manufacturing the DRAM of Figures 9A to 9C with reference to FIGS.10A through 10F illustrating cross sections, which are observed at different manufacturing steps. Referring to FIG.10A, field insulation films 89 are formed on the p-type silicon substrate 80, and then a gate oxidation film 93 is formed thereon. Thereafter, by the same process as that shown in FIG.5B, the word lines 82 and gate electrodes 92 are formed on the field oxidation films 89 and the gate oxidation films 93. The word lines 82 also serve as the gate electrodes 92. Next, as shown in FIG.10B, the source 84 and drain 85 are formed in the silicon substrate 80 by the selective ion injection process. Then, as shown in FIG.10C, the silicon oxidation film 90 is formed on the entire surface, and a contact hole 83′ is formed in the silicon dioxide film 90 and the gate oxidation film 93 so that the source 84 is partially exposed. Thereafter, in FIG.10D, a conductive polysilicon layer of a thickness of 500 angstroms is deposited on the entire surface, and then a tungsten silicide (WSi) layer of a thickness of 1500 angstroms is deposited thereon. Then, the stacked layers are patterned so as to form the bit line 81. Then, as shown in FIG.10E, the insulating film 91 made of silicon dioxide is deposited to a thickness of 1000 angstroms by CVD. Subsequently, the contact hole 83 is formed so as to penetrate the insulating films 91, 90 and the gate oxidation film 93 so that the drain 85 is partially exposed through the contact hole 83. Thereafter, as shown in FIG.10F, the storage electrode 86 is formed by CVD and photolithography. The following steps are the same as those used in a conventional method. The word lines 82 of the DRAM of Figures 9A to 9C extend in the X direction between neighboring transistors arranged in the Y direction. Alternatively, it is possible to arrange the word lines 82 so as to extend above the transistors in the same way as the word lines 52 of the first embodiment. The DRAM of Figures 9A to 9C provides almost the same advantages as the first embodiment in addition to the above-mentioned feature. A description is given of a second embodiment of the present invention with reference to FIGS. 11A and 11B. The second embodiment is distinguished from the DRAM of Figures 9A to 9C in that bit lines and storage electrodes of the second embodiment are self-aligned with respect to word lines, and are in contact with sources and drains of transistors, respectively. As is illustrated in FIGS.11A and 11B, the second embodiment includes a semiconductor substrate 121 such as a p-type silicon substrate, bit lines 111, word lines 112, contact holes 113, sources 114, drains 115, storage electrodes 116, an opposed electrode 117, insulating layers 118, field oxidation layers 119, and a storage electrode leading layer 133. The bit lines 111 extend in the X direction, and the word lines 112 extend in the Y direction and are laid above transistors. Therefore, the bit lines 111 and the word lines 112 match the peripheral circuits such as a sense amplifier and a row decoder. The bit lines 111 are in contact with related sources 114 through contact holes 129. The remaining portions of the bit lines 111 are laid on an insulating layer 128, which covers the word lines 112. The above-mentioned structure of the bit lines 111 is the same as that of the bit lines 81 of the DRAM of Figures 9A to 9C. Therefore, α particles-induced soft errors can effectively be suppressed. Each of the storage electrode 116 makes contact with the related storage electrode leading layer 133. Opposed ends of the storage electrode 116 extend up to ends of the bit lines 111. The width of each of the word lines 112 is almost the same as that of each of the storage electrodes 116. Therefore, the cell area is effectively and efficiently utilized. A description is given of a method of producing the second embodiment with reference to FIGS.12A through 12G, which illustrate cross sections taken along the lines XI-XI shown in FIG.11A observed at different manufacturing steps. Referring to FIG.12A, the field oxidation layers 119 are formed on the silicon substrate 121 by the conventional selective oxidation process. Then, the source 114 and the drain 115 are formed in the silicon substrate 121 by the selective ion injection process. The source 114 and drain 115 are formed by n⁺-type impurity diffused layers. Then, as shown in FIG.12B, a gate oxidation film 124 is formed in the thermal oxidation process. Thereafter, the word lines 112 which also serve as gate electrodes, are formed. In FIG.12C, the insulating film 128 such as a silicon dioxide film is deposited to a thickness of 1000 angstroms by CVD. Then the contact holes 129 and 130 are formed so as to penetrate the insulating film 128, the word line 112 and the gate oxidation film 124 so that the source 114 and drain 115 are partially exposed through the contact holes 129 and 130, respectively. Alternatively, the source 114 and drain 115 may be formed by introducing impurities through the contact holes 129 and 130. In this case, the production step of FIG.12A is not carried out. Then, as shown in FIG.12D, a thermal oxidation film of a thickness of 200 angstroms is deposited on the exposed surface of the source and drain 114 and 115 as well as the entire device surface. Subsequently, an oxidation film is deposited to a thickness of 1000 angstroms by the CVD process. Thereafter, the stacked oxidation films are subjected to reactive ion etching. Thereby, an oxidation film 131 is formed which covers a sidewall forming each of the contact holes 129 and 130, and a part of each of the source 114 and drain 115. In FIG.12E, in the same way as the step of FIGS.7D and 8D, the bit line 111 and the storage electrode leading layer 133 are self-aligned with respect to the word line 112 by CVD so as to make contact with the source 114 and the drain 115, respectively. In FIG.12F, an insulating layer 134 formed by an oxidation layer is formed on the entire surface of the device by CVD. Thereafter, a contact hole 141 is formed in the insulating layer 134 in the same way as the step of FIGS.7D, 7E, 8D and 8E. Then, a polysilicon film is grown by CVD, and is then patterned so as to form the storage electrode 116. Then, a dielectric film (118) is formed around the exposed surface of the storage electrode 116 by the thermal oxidation process. Finally, the opposed electrode 117 is formed so as to cover the entire surface of the device. Alternatively, as shown in FIG.13A, a dielectric film 142 is formed on the entire surface by the thermal oxidation process after performing the step of FIG.12E. In this case, the storage electrode leading layer 133 serves as a storage electrode itself. Then, a polysilicon film is grown on the entire surface, and is then patterned so as to form an opposed electrode 143. FIG.14 illustrates respective examples of the sense amplifier pitch, word line pitch, cell area and the ratio of the storage electrode area to the cell area with respect to devices which are fabricated based on the first and second embodiments of the present invention, as well as on the DRAM devices of Figures 4A to 4C and Figures 9A to 9C and the conventional open bit line type. Parameter values for the conventional folded bit line type are illustrated for reference. It can be seen from FIG.14 that in each of the first and second embodiments (and in the DRAM devices of Figs. 4 and 9) the sense amplifier pitch is larger than the word line pitch, and therefore the bit lines match the peripheral circuits. It is noted that the sense amplifier pitch obtained in the conventional open bit line type is a little larger than the word line pitch. This is because the bit line pitch is set larger in order to match the minimum size of sense amplifier which is obtainable with production precision currently available. In the DRAM of Figures 4A to 4C, although the sense amplifier pitch and the storage electrode area are larger than those in the conventional open bit line type, the utility efficiency of cell area is enhanced. As a result, the cell area formed in the DRAM of Figures 4A to 4C is smaller than that for the conventional open bit line type. In the first and second embodiments, the cell area is approximately half that for the conventional type; nevertheless it becomes possible to obtain the same sense amplifier pitch as that for the conventional type. Additionally, the cell area obtained in the first and second embodiments is smaller than that for the conventional folded line type; nevertheless the utility efficiency of cell area is high. Therefore, the storage electrode area is larger than the folded bit line type. This means a large amount of capacitance is obtained when the sense amplifier pitch is set approximately equal to that for the folded bit line type. In the DRAM of Figures 9A to 9C, the utility efficiency of cell area is the highest. Further, the cell amplifier pitch and the storage electrode area are larger than those for the conventional open bit line type, and the cell area is smaller than that for the conventional type. Moreover, when the sense amplifier pitch in the DRAM of Figures 9A to 9C is set approximately equal to that for the conventional folded bit line type, the storage electrode area can be doubled. The parameter values shown in FIG.14 are obtained as follows. FIGS.15A through 15D are partially enlarged views which two-dimensionally illustrate the structure of respective cells of the DRAM devices of Figures 4A to 4C, Figures 6A to 6C (first embodiment), Figures 9A to 9C, and Figures 11A to 11B (second embodiment) respectively. FIGS.15E and 15F are partially enlarged views which two-dimensionally illustrate the structure of respective cells of the conventional folded bit line type and the open bit line type, respectively. In these figures, an area surrounded by a broken line is a storage electrode. Also in FIGS.15A through 15F, 'a' is the minimum pattern width available in photolithography, 'b' is a margin defined by taking account of positional errors which may occur when depositing a mask film, 'c' is a margin defined by taking account of short-circuit which may occur in a conductive layer, and 'd' is a bird's beak which may occur in a selective oxidation process. In each of FIGS.15A through 15F, there are written the sense amplifier pitch [p(S/A)], word line pitch [p(WL)], and the storage electrode area (s). In FIG.15F, the sense amplifier pitch p(S/A) is set equal to 4a + 2c, which is the minimum size. The values shown in FIG.14 are obtained assuming that a = 0.7 µm, b = 0.3 µm, c = 0.45 µm and d = 0.15 µm. In FIG.15A, the sense amplifier pitch p(S/A) is equal to 4a + b + c + 2d, the word line pitch p(WL) is equal to 3a + b + c, and the storage electrode area (s) is equal to (3a + b + c + 2d)(2a + b +c). In FIG.15B, the sense amplifier pitch p(S/A) is equal to 4a + 2b + 2d, the word line pitch p(WL) is equal to 2(a + b), and the storage electrode area (s) is equal to (3a + 2b + 2d)(a + 2b). In FIG.15C, the sense amplifier pitch p(S/A) is equal to 4a + 2c + 2d, the word line pitch p(WL) is equal to 3a + b + c, and the storage electrode area (s) is equal to (3a + 2c + 2d)(2a + b + c). In FIG.15D, the sense amplifier pitch p(S/A) is equal to 4a + 2b + 2d, the word line pitch p(WL) is equal to 2(a + b), and the storage electrode area (s) is equal to (3a + 2b + 2d)(a + 2b). In FIG.15E, the sense amplifier pitch p(S/A) is equal to 4(a +b), the word line pitch p(WL) is equal to (4a +3c)/2, and the storage electrode area (s) is equal to (a + 2b)(3a + 2c - b). In FIG.15F, the sense amplifier pitch p(S/A) is equal to 2(a + b) to 4a + 2c depending on layout of sense amplifier, the word line pitch p(WL) is equal to 3a + b + 2c, and the storage electrode area (s) is equal to (3a + 2c)(2a + c). The present invention is not limited to the aforementioned embodiments, and variations and modifications may be made without departing from the scope of the present invention which is defined by the claims. For example, in the first and second embodiments, one bit line is alternately coupled to sources arranged on both sides thereof. Alternatively, one bit line may be coupled to sources arrange on the same side thereof. Transistors in each of the first and second embodiments, are n-channel field effect transistors. Alternatively, p-channel transistors can be formed in the same way.

Claims: A dynamic random access memory device including: a substrate (50;121); a plurality of FET transistors arrayed at a main face of the substrate in the form of a matrix, each transistor being located in an area delimited by portions of a field oxidation layer (59;119), formed at the said main face, and having a source (51;114) and a drain (55;115) formed in the said substrate and also having, between the source and drain, a gate electrode (52;112) formed on a gate oxide film (62;124) which is formed on the said main face and separates the gate electrode from the substrate, the respective source-drain channels of the transistors all extending in a first direction (X); a plurality of word lines (52;112) formed on the said field oxidation layer (59;119) and extending longitudinally in the said first direction (X), the word lines being arranged such that portions thereof which overlie the said respective source-drain channels of the transistors serve as the respective gate electrodes of the transistors, and having contact holes (53;130) in register with respective drains of the transistors; a plurality of bit lines (51;111) extending longitudinally in a second direction (Y) perpendicular to the said first direction (X), each of the transistor sources being connected to one of the bit lines, and the spacing between adjacent bit lines being greater than the spacing between adjacent word lines; an insulating film (60;128) formed over the said word lines and also extending over sidewalls of the said word lines bounding the said contact holes and over parts of the said drains within those contact holes; a plurality of storage capacitors, each including a storage electrode (56;133,116) which extends, in the said first direction (X), substantially from one bit line to the next and which contacts an associated one of the transistor drains via one of the said contact holes and which has parts that extend above the word line having that contact hole and above the said field oxidation layer (59;119), and each also including a dielectric film (58;118) covering the said storage electrode; and an opposed electrode (57;117) covering the respective dielectric films of the said storage capacitors. A device as claimed in claim 1, wherein the said word lines (52;112) are wider, measured in the said second (Y) direction, than the said contact holes (53;130). A device as claimed in claim 1 or 2, wherein the said storage capacitors are substantially equal in said storage in the said second (Y) direction, to the said word lines (52;112). A device as claimed in any one of claims 1 to 3, wherein portions (63;131) of the said insulating film (60;128) that extend over the said sidewalls of the said word lines (52;112) within the said contact holes (53;130) are formed by a reactive ion etching process. A device as claimed in any one of claims 1 to 4, wherein the said storage electrode (56) is self-aligned with respect to its associated word line (52). A device as claimed in any one of claims 1 to 4, 30 wherein the said storage electrode (133,116) includes a connection portion (133), which contacts the drain (115), and an electrode portion (116) extending above the said connection portion in contact therewith. A device as claimed in claim 6, wherein the said 35 connection portion (133) is self-aligned with respect to the word line (112) associated with the storage electrode concerned. A device as claimed in any preceding claim, wherein the said bit lines (51) are formed in the said substrate (50) at the said main face thereof, portions of the said bit lines serving as the said sources of the transistors. A device as claimed in any one of claims 1 to 7, wherein the said bit lines are formed on the said insulating film (128), that film having contact holes (129) in register with respective sources (114) of the transistors, through which holes the bit lines contact the said sources. A device as claimed in any preceding claim, further including a plurality of sense amplifiers (S/A), each connected for amplifying a potential difference between a pair of associated bit lines, which sense amplifiers are arrayed one after another in the said first (X) direction. A device as claimed in any preceding claim, wherein successive transistors that are connected to a given bit line are located on alternate sides of the bit line.

Inventors: EMA TAIJI, EMA, TAIJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H01L27
IPC codes: H01L21, H01L27