Single-chip microcomputer including EPROM therein

Abstract: A single-chip microcomputer includes therein an EPROM including a specific cell of the EPROM storing an item of information for discrimination of a memory space. When a reset signal is applied for initializing the single-chip microcomputer, the specific cell of the EPROM is selected and read out, and further latched in a latch circuit. On the basis of the content of the latch circuit, the single-chip microcomputer discriminates and sets a boundary between an internal memory and an external memory in a programmed operation.

Description: Background of the Invention Field of the invention The present invention relates to a single-chip microcomputer, and more specifically to a single-chip microcomputer including therein an erasable programmable read only memory (called "EPROM" in the specification) which can be written, read and erased. Description of related art In general, a single-chip microcomputer has included a central processing unit for executing a data processing, a memory section for storing programs and data, and an input/output section for performing a data transfer between the microcomputer and an external device, the central processing unit, the memory section and the input/output section being assembled on a single integrated circuit chip. This type of microcomputer, which is one of stored program controlled apparatuses, can execute different processings by changing a program, and therefore, has been widely used as a control device in various fields. However, a program memory and a data memory have to have different capacities required dependently upon application systems and processings to be executed. Therefore, different microcomputers which have the central processing unit and the input/output section of the same functions but which include a different capacity of memory, have been now developed and manufactured. On the other hand, with a recent developed integrated circuit technology, single-chip microcomputers including an EPROM as a program memory have appeared, in addition to those which include a read only memory having a program permanently built in during its manufacture in accordance with a specially created pattern or mask (called "mask ROM" hereinafter). The single-chip microcomputer including the EPROM therein is advantageous in that even after the single-chip microcomputer is assembled in a package and put in a finished condition as an integrated circuit, a program can be written to the EPROM of the single-chip microcomputer. Therefore, since the single-chip microcomputer can shorten a time required from a design of a program until an actual operation of the system, the single-chip microcomputer has been widely utilized for a program evaluation in the course of system development and for a small-amount production. In the case of utilizing the single-chip microcomputer including the EPROM therein for the purpose of evaluating a program to be used in a apparatus including a mask ROM therein, it is in some cases that a completely equivalent evaluation cannot be executed because of difference in memory capacity between the EPROM and the mark ROM. For example, in a system having a function of discriminating a space of a program memory and fetching an instruction from an external memory if an accessed memory space is not within the memory included in the single-chip microcomputer, if the memory capacity is different between the microcomputer having the EPROM and the microcomputer having the mask ROM, a boundary between the internal memory and the external memory in the microcomputer having the EPROM is also different from the internal/external memory boundary in the microcomputer having the mask ROM, and therefore, a memory space from which an instruction is read is also different. In addition, if an internal data memory has a different capacity, a memory access to a memory space corresponding to a memory having a small memory capacity can be equivalently executed, but data stored in a memory space having a large memory capacity becomes different. Accordingly, in order to evaluate a program by using a system having a different memory capacity, it is necessary to design the program taking the difference in consideration, and to check whether or not there is access to a memory space which does not actually exist. Because of the above mentioned circumstance, a device including an EPROM, completely equivalent to a device including a mask ROM, has been required. At present, however, the amount of use of devices including the EPROM is one-tenth or less of the amount of use of devices including the mask ROM. Therefore, it would be very expensive and not so economic to develop and manufacture a system including therein a number of EPROMs corresponding to different memory capacities. EP-A-0 255 414 discloses a storage protection circuit which enables the control of the access to different storage areas of an EPROM and contains two EPROM cells which are controlled by a selector circuit and programmed by a PLA. Summary of the Invention Accordingly, it is an object of the present invention to provide a single-chip microcomputer having an EPROM therein, which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a single-chip microcomputer having a single EPROM therein, but capable of executing an operation equivalent to that of a device having a different capacity of memory, thereby to reduce a load for a program development. The above and other objects of the present invention are achieved in accordance with the present invention by a single-chip microcomputer as claimed in claim 1. With the above mentioned arrangement of the single-chip microcomputer, the EPROM included in the single-chip microcomputer has a fixed memory capacity, but since there is provided the means for changing the boundary between the internal memory and the external memory, so that the single-chip microcomputer can execute an operation equivalent to that of a device having an internal memory capacity smaller than the EPROM of the single-chip microcomputer. In addition, since the information for discrimination of a memory space is stored in the EPROM and the boundary between the internal memory and the external memory is controlled on the basis of the information stored in the EPROM, it is possible to set a desired memory capacity after the single-chip microcomputer has been put in a finished condition as an integrated circuit. Furthermore, the information for discrimination of a memory space stored in the EPROM will be maintained even after power-off. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram of a first embodiment of the single-chip microcomputer in accordance with the prevent invention; Figure 2 is a block diagram of the program memory in the single chip microcomputer shown in Figure 1; Figure 3 is a block diagram of a second embodiment of the single chip microcomputer in accordance with the present invention; and Figure 4 is a block diagram illustrating the data memory space control in the single-chip microcomputer shown in Figure 3. Description of the Preferred embodiments Referring to Figure 1, there is shown a block diagram of a first embodiment of the single-chip microcomputer in accordance with the present invention. The single-chip microcomputer, generally indicated by Reference Numeral 10, mainly comprises a central processing unit (CPU) 12 for executing a data processing and for controlling the whole of the microcomputer, a data memory 14 for storing data, a program memory 16 for storing programs, an input port 18 for receiving data from an external device (not shown), for example an external memory, an output port 20 for outputting data to an external device (not shown), for example an external memory, and a clock generator 22 for generating and supplying an internal clock through a line 24 to the CPU 12, the data memory 14, the program memory 16, the input port 18 and the output port 20. In addition, the circuits excluding the clock generator 22 are coupled to an internal bus 26, so that data and addresses are transferred among these circuits through the internal bus 26. A reset signal RESET is supplied to the CPU 12 and the program memory 16 through a line 28. In the shown embodiment, an item of information for discrimination of a memory space is supplied from an external device and written to a specific cell of the program memory 16. At the time of initializing responding to for example the reset signal RESET, a content of the specific cell of the program memory is read and latched in a latch circuit not shown in Figure 1. A boundary between an internal memory and an external memory is set or changed on the basis of the content of the latch circuit. In an operation after the resetting, the microcomputer 10 operates to automatically switch a memory access between the internal memory and the external memory in accordance with the set boundary between the internal memory and the external memory. Thus, the shown single-chip microcomputer can execute an operation equivalent to a single-chip microcomputer having a mask ROM of a desired memory capacity. In order to realize the above mentioned operation, the program memory 16 is constructed as shown in Figure 2. Specifically, the program memory 16 includes a plurality of memory cell matrix blocks 30, and an X-decoder 32 and a Y-decoder 34 coupled to receive an address from an address bus 36 included in the internal bus 26. Outputs of the X-decoder 32 are connected to corresponding columns of the memory cell matrix blocks 30 through an AND gate 38 or an OR gate 40. Outputs of the Y-decoder 34 are connected through an AND gate 42 or an OR gate 44 to corresponding transfer gates 46 which are coupled between corresponding rows of the memory cell matrix blocks 30 and associated sense amplifier and write circuits 48. The sense amplifier and write circuits 48 are coupled to a data bus buffer 50, which is coupled to a data bus 52 included in the internal bus 26. One of the sense amplifier/write circuits 48 is also connected to an input D of a latch circuit 53, which has a gate control input G connected to receive the reset signal RESET. An output Q of the latch circuit 53 is connected to one input of an AND gate 54, which is connected at its other input to a third significant bit 56 of the address bus 36. An output of the AND gate 54 is connected to one input of a three-input OR gate 58, the other inputs of which are connected to receive the most significant bit 60 and a next significant bit 62 of the address bus 36. An output of the OR gate 58 is supplied through an inverter 64 to the data bus buffer 50. Furthermore, the reset signal RESET is supplied to the OR gates 40 and 44 and an inverter 66, and an output of the inverter 66 is connected to all the AND gates 38 and 42 associated to the X-decoder 32 and the Y-decoder 34. Now, an operation will be explained in the case that a one-bit within the program memory gives information for discrimination of a memory boundary. Therefore, assume that an item of information for discrimination of memory space is stored in a EPROM cell 68 which is connected to the OR gate 40 and is also connected to the transfer gate 46 controlled by the output of the OR gate 44. The writing of the EPROM cell 68 can be performed in a well known manner by supplying an address onto the address bus 36 and data to the data bus 52, and therefore, a detailed explanation will be omitted. In general, an address on the address bus 36 is decoded by the X-decoder 32 and the Y-decoder 34, and one EPROM cell is selected by the X-decoder 32 and the Y-decoder 34. A content stored in the selected EPROM cell is supplied through the sense amplifier and write circuit 48 to the data bus buffer 50, and further to the data bus 52. In almost cases, before a program is executed, the overall system js initialized. In the shown embodiment, the initialization is triggered by bringing the reset signal RESET to a high level. If the reset signal RESET is brought to the high level, the outputs of the OR gates 40 and 44 are also brought to the high level regardless of a content of the address bus 36, and on the other hand, the output of the inverter 66 is brought to a low level, so that all the outputs of the logic gates receiving the outputs of the X-decoder 32 and the Y-decoder 34 excluding the OR gates 40 and 44 are brought to the low level. As a result, the specific EPROM cell 68 is selected without exception at the time of resetting. A content of the selected specific EPROM cell 68 is supplied through the sense amplifier and write circuit 48 to the data bus buffer 50 and also latched in the latch circuit 53 since the gate control input G of the latch circuit 53 is at this time at the high level by the reset signal RESET. After the initialization is completed and the reset signal RESET is brought to the low level, the execution of the program is started. When the reset signal RESET is brought to the low level, the gate of the latch circuit 53 is closed, and therefore, the content of the latch circuit no longer changes. On the other hand, all the AND gates 38 and 42 are opened, so that the outputs of the X-decoder 32 and the Y-decoder 34 are outputted to the memory cell matrix and the associated transfer gate array as they are. If the output of the latch circuit 53 is at the low level, the output of the AND gate 54 is also at the low level. Therefore, if at least one of the most significant bit 60 and the next significant bit 62 of the address bus 36 is at the high level, the output of the OR gate 58 is brought to the high level, and accordingly, the output of the inverter 64 is brought to the low level. As result, the data bus buffer 50 is inhibited to output the content of the EPROM to the data bus 52. On the other hand, if the output of the latch circuit 53 is at the high level, the inverter 64 outputs the low level signal to the data bus buffer 50, similarly to the case in which anyone of the most significant bit 60, the next significant bit 62 and the third significant bit 56 of the address bus 36 is at the high level. In other words, it is inhibited to output the content of the EPROM through the data bus buffer 50 to the data bus 52, regardless of the most significant bit 60, the next significant bit 62 and the third significant bit 56 of the address bus 36. Thus, if the microcomputer is controlled to fetch data from an external memory when the output of the OR gate 58 is at the high level, it is possible to discriminate that the access space is external when the output of the OR gate 58 is at the high level, and internal the output of the OR gate 58 is at the low level. For example, assume that the address bus 38 is composed of 8 bits. In this case, if the output of the latch circuit 53 is at the low level, it is discriminated that addresses 00 H to 3F H (suffix "H" indicates a hexadecimal notation) all having two most significant bits of the low level are within an internal memory space, and addresses 40 H to FF H are within an external memory space. On the other hand, if the output of the latch circuit 53 is at the high level, it is discriminated that addresses 00 H to 1F H all having three most significant bits of the low level are within an internal memory space, and addresses 20 H to FF H are within an external memory space. As seen from the above, the first embodiment is such that, at the time of resetting, the specific EPROM cell is selected and read out and the read-out data is latched in the latch circuit, and after the completion of the resetting operation, the size of the internal memory space to be used is determined on the basis of the content of the latch circuit. Therefore, the first embodiment of the single-chip microcomputer can execute an operation equivalent to a microcomputer having a desired capacity of memory. The above mentioned embodiment is such that the boundary between the internal memory space and the external memory space is determined on the basis of the information stored in only one specific EPROM cell. However, if information concerning the boundary between the internal memory space and the external memory is stored in a plurality of specific EPROM cells, and if a corresponding number of latch circuits 53A similar to the latch circuit 53 are provided in combination with logic gate circuits (not shown) are coupled to the address bus and the latch circuits, it is possible to set or change a plurality of boundaries between the internal memory space and the external memory space. Referring to Figure 3, there is shown a block diagram of the second embodiment of the single-chip microcomputer in accordance with the present invention. In Figure 3, elements similar or corresponding to those shown in Figures 1 and 2 are given the same Reference Numerals. The CPU 12 includes an address generator 70, which is coupled to output an address to the address bus 36 in response to the reset signal RESET supplied through an inverter 72. The output of the inverter 72 is also supplied to an counter 74 as a clear signal. A content of the counter 72 is outputted to the address bus 36 through a bus buffer 76, which is controlled by the reset signal RESET. In addition, the address bus 36 is coupled to a decoder 78. This decoder decodes an address on the address bus and operates to generate a signal 80 of the high level when an address storing information for determining a program memory space is detected, and a signal 82 of the high level when an address storing information for determining a data memory space is detected. These signals 80 and 82 are supplied to two AND gates 84 and 86, respectively, which are also connected to receive the reset signal RESET. Outputs of the AND gates 84 and 86 are connected to a gate control input of a pair of latch circuits 88 and 90, respectively. A data input of each of the latch circuits 88 and 90 is coupled to the data bus 52. An output of the latch 88 is coupled to a space discriminator 92, which controls the sense amplifier and bus buffer 94 associated to the EPROM cell array. The embodiment shown in Figure 3 operates as follows: When a program is executed, if the reset signal RESET is brought to a low level, the output of the inverter 72 is brought to the high level so as to clear the counter 74 and to cause the address generator 70 to output an address of the EPROM. The generated address is outputted onto the address bus 36 and decoded by the X-decoder 32 and the Y-decoder 34, so that the content of the EPROM cell designated by the generated address is read out and outputted to the data bus 52 through the sense amplifier and bus buffer 94. Thereafter, if the reset signal RESET is brought to the high level for the purpose of initialization, the output of the inverter 72 is brought to the low level, the address output from the address generator 70 is inhibited, and the counter 74 starts its counting operation. When the reset signal RESET is maintained at the high level, the output of the counter 74 is supplied to the address bus through the bus buffer 76. As a result, a content or data of the EPROM designated by the address sequentially incremented (or decremented) by the counter 72 is sequentially read out and outputted to the data bus 52. As mentioned above, when an address which stores information for determining a program memory space is outputted onto the address bus 36, the decoder 78 generates the signal 80 of the high level. When an address which stores information for determining a data memory space is outputted onto the address bus 36, the decoder 78 generates the signal 82 of the high level. Since the reset signal RESET is at the high level, the signals 84 and 86 of the high level outputted from the decoder 78 are supplied to the latch circuits 88 and 90, respectively. Thus, when the signal 80 becomes the high level, the information for determining the program memory space, which is outputted on the data bus 52, is latched into the latch circuit 88. When the signal 82 becomes the high level, the information for determining the data memory space, which is also outputted on the data bus 52, is latched into the latch circuit 90. On the basis of the information held in the latch circuit 88, the space discriminator 92 discriminates the program memory space, and controls the sense amplifier and bus buffer 94 after the reset operation has been completed, in such a manner that the EPROM other than a portion corresponding to the set program memory space is inhibited to be read. On the other hand, the content of the latch 90 is supplied to a circuit (not shown) for controlling the data memory space, so that a space used as a data memory is discriminated. Turning to Figure 4, there is shown one example of the circuit which receives the output of the latch circuit 90 and operates to control the data memory space. In the shown circuit, a random access memory (RAM) 96 includes an address decoder 96A coupled to the address bus 36 and a sense amplifier and read/write buffer 96B coupled to the data bus 52. The most significant bit 98 and a next significant bit 100 of the address bus 36 are coupled to the address decoder 96A through AND gates 102 and 104, respectively, which are respectively coupled to receive signals corresponding to the output of the latch circuit 90 which determines the data memory space. When both of the signals 106 and 108 are at the high level, it is allowed to access anywhere of the overall RAM 96. When the signals 106 and 108 are at the low level and at the high level, respectively, it is allowed to access only a half of the overall RAM 96, since the output of the AND gate 102 is fixed to the low level so that an access to addresses having the most significant bit of "1" is inhibited. In addition, when both of the signals 106 and 108 are at the low level, it is allowed to access only one-fourth of the overall RAM 96, since the outputs of the AND gates 102 and 104 are fixed to the low level so that an access to addresses having the most or next significant bit of "1" is inhibited. In the above mentioned embodiment, the information for determining the memory space is transferred from the EPROM through the data bus, and a required information is selectively latched. Accordingly, even in the case in which each memory has a large memory area, and a program memory is far separate from a data memory, the information for determining the memory space is latched at a desired position so as to be used for control of the memory space.

Claims: A single-chip microcomputer (10) comprising an erasable programmable read only memory cell matrix (30) including a specific cell (68) storing an item of information for the discrimination of a memory space characterized in that the single-chip microcomputer comprises: an address bus (36) and a data bus (52), to which the erasable programmable read only memory cell matrix (30) is coupled, means (70) for supplying an address to the address bus (36), decoder means (78) coupled to the address bus (36) for generating a signal (80, 82) when there is detected an address of the specific cell (68) storing the item of information for discrimination of the memory space, latch means (88, 90) coupled to the data bus (52) for latching the item of information for discrimination of the memory space read out on the data bus (52) from the memory cell matrix (30), in response to a reset signal when the signal (80, 82) is generated by the decoder means (78), and means (92, 102, 104) coupled to the latch means (88, 90) so as to define a boundary between an internal memory (96) and an external memory on the basis of the item of information for discrimination of the memory space latched in the latch means (88, 90). A single-chip microcomputer (10) claimed in Claim 1 wherein the memory boundary defining means (92, 102, 104) are composed of a space discriminator (92) coupled to the latch means (88, 90) and associated to the memory cell matrix (30) for defining a memory space to be accessed within the memory cell matrix(30). A single-chip microcomputer (10) claimed in Claim 1 wherein the memory boundary defining means (92, 102, 104) includes a logic circuit (102, 104) coupled between the address bus (36) and a data memory (96, 96A, 96B) so as to selectively mask at least one bit of an address supplied from the address bus (36) to the data memory (96, 96A, 96B), on the basis of the item of information for discrimination of the memory space latched in the latch means (88, 90), so that a memory space to be accessed is defined within the data memory (96, 96A, 96B). A single-chip microcomputer (10) claimed in claim 1 comprising an erasable programmable read only memory cell matrix (30) including a specific cell (68) storing an item of information for discrimination of a memory space, decoder means (32, 34) coupled to the address bus (36) and to the memory cell matrix (30) for writing an accessible condition into a memory cell designated by an address on the address bus (36), read means (48) coupled to the memory cell matrix (30) for reading and outputting a content stored in the memory cell into which the accessible condition was written, buffer means (50) coupled to the read means (48) and the data bus (52) so as to output data outputted from the read means (48) to the data bus (52), latch means (53, 53A) coupled to the read means (48) for latching the data outputted from the read means (48), logic means (54, 58) coupled to receive the content of the latch means (53, 53A) and at least one selected bit (56, 60, 62) of the address bus (36) and for outputting a control signal to the buffer means (50), and control means (32, 34, 38, 40, 42, 44, 66) having gate means (38, 40, 42, 44) coupled between the decoder means (32, 34) and the memory cell matrix (30) and receiving the reset signal, the control means (32, 34, 38, 40, 42, 44, 66) operating in such a manner that when the reset signal is indicative of a reset operation, the control means (32, 34, 38, 40, 42, 44, 66) controls the gate means (38, 40, 42, 44) so as to cause it to bring only the specific cell (68) into the accessible condition, and to cause the latch means (53, 53A) to latch the information stored in the specific cell (68) and outputted through the read means (48), and when the reset signal becomes not indicative of a reset operation, the control means (32, 34, 38, 40, 42, 44, 66) controls the gate means (38, 40, 42, 44) so as to cause it to pass outputs of the decoder means (32, 34) to the memory cell matrix (30) as they are, and to control the latch means (53, 53A) to maintain the latched information as it is, whereby when the content of the latch means (53, 53A) is in a first logic level, the logic means (54, 58, 64) outputs the control signal to the buffer means (50) so as to inhibit the output of the read means (48) to the data bus (52) regardless of the one selected bit (56, 60, 62) of the address bus (36), and when the content of the latch means (53, 53A) is in a second logic level opposite to the first logic condition, the logic means (54, 58, 64) outputs the control signal to the buffer means (50) so as to inhibit the output of the read means (48) to the data bus (52) in accordance with the one selected bit (56, 60, 62) of the address bus (36). A single-chip microcomputer (10) claimed in Claim 4 wherein the gate means (38, 40, 42, 44, 66) include an OR gate (40, 44) having an output connected to the specific cell (68), a first input connected to an corresponding output of the decoder means (32, 34) and a second input connected to receive the reset signal, and a plurality of AND gates (38, 42) each having a first input connected to a corresponding one of outputs of the decoder means (32, 34) excluding the output connected to the first input of the OR gate (40, 44), a second input connected to receive the reset signal through an inverter (66), and an output connected to a corresponding cell of the memory cell matrix (30). A single-chip microcomputer (10) claimed in Claim 4 wherein the logic means (54, 64) includes an AND gate (54) having a first input connected to the output of the latch means (53) and a second input connected to receive the selected bit (56) of the address bus (36), and an inverter (64) having an input connected to an output of the AND gate (54) and an output connected to the buffer means (50). A single-chip microcomputer (10) claimed in Claim 4 wherein the logic means (54, 58, 64) includes an AND (54) gate having a first input connected to the output of the latch means (53) and a second input connected to receive a third most significant bit (56) of the address bus (36), an OR gate (58) connected to receive the most and second significant bits (60 and 62) of the address bus (36) and an output of the AND gate (54), and an inverter (64) having an input connected to an output of the OR gate (58) and an output connected to the buffer means (50).

Inventors: SAITO MIKIO, SAITO, MIKIO, SAITO, MIKIO C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: G06F12
IPC codes: G06F12, G06F15