Method of manufacturing a conductivity modulation MOS semiconductor power device (Himos)

Abstract: In an insulated gate bipolar transistor, the pin n+ buffer layer is achieved by first growing a thin p- epilayer on the p++ anode layer, then ion implanting or predepositing the n dopant, and finally diffusing it.

Description: This invention concerns a method for manufacturing a conductivity modulation MOS power device (HIMOS device) and the devices obtained thereby. In HIMOS transistors, the limitations of the conventional type MOS power devices, deriving from the high resistance of the drain epitaxial region, are overcome by modulating the conductivity of the drain region by injecting minority carriers of a junction (P-N or N-P depending on whether it is an N-channel or a P-channel HIMOS) in series with the drain. In order to make it less probable that the intrinsic parasitic thyristor of the structure itself be activated, a thin (N+ type or P+ type, respectively) epitaxial buffer layer is often provided between the substrate (P+ or N+) and the epitaxial layer (N- or P-) constituting the aforesaid junction, so as to increase the amount of charge of the aforesaid epitaxial layer (N- or P-). See, e.g., IEEE Electron Device Letters, vol. EDL-6, No.5. May 1985, "Modeling the turn-off characteristics of the bipolar-mode transistor", edited by S. Kuo et al. See also IEEE Electron Device Letters, vol. EDL-5, No.11, November 1984, pages 437-439. It is not possible, however, with the epitaxial technique to create the buffer layer with concentrations of donant higher than 10¹⁶ atoms/cm³: this greatly limits the efficiency of the aforesaid buffer layer. The invention makes it possible to create a buffer layer with considerably higher concentrations of dopant than those which can be obtained by epitaxial growth, with the dual effect of protecting the device from the possibility of the parasitic thyristor being activated and of considerably reducing the HIMOS transistor turn-off time. This is achieved with a method of manufacturing as defined in claim 1. The manufacturing method according to the invention comprises, for the purpose of creating the aforesaid buffer layer, the following phases: epitaxial growth, on the aforesaid substrate, of a thin semiconductor layer of the same type of conductivity as the substrate itself; ion implantation or deposition, in the aforesaid thin layer, of dopant of the type N or P required for creating the buffer layer, followed by subsequent diffusion. The features of the invention will be more clearly evident from the following description and accompanying drawings of a non-restrictive embodiment in which: Fig.1a: shows the structure of a conventional type HIMOS power transistor; Fig.1b: shows the equivalent circuit of the structure of Fig. 1a; Fig. 2: shows the structure of a HIMOS transistor with an epitaxial buffer layer; Figs.3a - 3e: show a schematic representation of a structure, during the various phases of the manufacturing process according to the invention; Fig.3f: shows the structure of a HIMOS transistor at the end of the manufacturing process according to the invention; Figs.4a and 4b: show curves illustrating the concentrations of dopant in the buffer layer that can be obtained, respectively with the conventional method and with the method according to the invention. Fig.1a shows the structure of a conventional type N-channel HIMOS power transistor. According to this structure the conductivity of the drain region is modulated by injecting minority carriers in the P-N junction, in series with the drain, consisting of the substrate P+ and the overlying epitaxial layer N-. Fig.1b shows the equivalent circuit of the structure of Fig.1a and, in particular, the intrinsic parasitic thyristor of the structure itself. This parasitic thyristor is activated whenever the sum of the common-based current gains α n + α p of the two transistors npn and pnp (with α n = α npn and α p = α pnp ) reaches value 1. Consequently to avoid activating the parasitic thyristor it must be (α n + α p ) < 1 . In practice, it is necessary to ensure that this condition is complied with by reducing the α p value as much as possible. Since the current gain α is a function both of the thickness and of the concentration of basic dopant (in the sense that when each of these magnitudes is increased the gain decreases), one of the most widely used solutions is that of adding a thin epitaxial layer ("buffer") N+ between the substrate P+ and the epitaxial layer N- (as shown in the structure of Fig. 2), so as to increase the amount of charge in the epitaxial region N- which is the base of the transistor pnp (in Fig. 2 the base of the transistor pnp consists of the epitaxial buffer layer N+ together with the epitaxial layer N-) thus obtaining a considerable reduction of α p . The lowering of α p , equivalent to a decrease in the amount of minority charges (holes) injected from the substrate P+ and stored in the region N- during the conduction phase, also involves a considerable reduction in the turn-off times of the devices shown in Fig.2 due to the smaller quantity of holes to be recombined. The known technique for creating the structure of Fig.2 is that of sequentially growing the buffer layer N+ and the overlying region N- on the substrate P+ by the epitaxial technique and then proceeding to manufacture the device. It is not possible, however, with the epitaxial technique to create the buffer layer with a concentration of more than 10¹⁶ atoms/cm³, either for N-type or for P-type dopants. This shows the limited efficiency of this solution. On the contrary, with the solution proposed by the invention it is possible to create a buffer layer with a much higher concentration of dopant than is possible with epitaxial growth, thus obtaining a more drastic reduction both of α p and of turn-off times of the device. The technique used for creating the buffer layer according to the invention is illustrated by the example shown in Figs.3a-3e, which schematically represent the structure of a device during the various phases of its manufacturing process. The process starts with a substrate 1 of silicon P++(100) having a resistivity of 15-20 mohm·cm ( Fig.3a ), on which is epitaxially grown a thin layer 4 of approximately 15 µm of P-type silicon (boron doped) having a resistivity of 25 ohm·cm ( Fig.3b ). A dose of 5·10¹⁴ atoms/cm² of antimony is implanted on this epitaxial layer ( Fig.3c ) and then the dopant Sb is diffused at a temperature T=1150 °C for two hours in order to form the layer N+ smaller in thickness than the first epitaxial layer grown ( Fig.3d ). At this point the second epitaxial growth of the N-type layer 3 is carried out, with resistivity and thickness determined by the voltage BV DSS of the device to be produced ( Fig.3e ). In the manufacturing sequence (passage from Fig.3d to Fig.3e) the residual P-type thin layer (not essential for the purposes of the invention) is completely absorbed by the out-diffusion of the boron of the substrate, with consequent complete formation of the buffer layer 2. Once the N-type layer 3 has been formed, the manufacturing process is exactly the same as that of any other MOS power device. The structure of the finished device is as shown in Fig.3f . It should be pointed out that the first epitaxial layer P (grown directly on the substrate P++) serves the purpose of buffering the out-diffusion of the boron of the substrate, since if the implantation were to be carried out directly on the substrate P++, during the subsequent high temperature thermal processes the boron in the substrate would spread towards the epitaxial layer and cause the buffer N+ to disappear, because the concentration of boron would exceed the concentration of antimony. Figs.4a and 4b refer, respectively, to a HIMOS device produced according to the known technique and a similar device produced according to the invention, and enable a comparison to be made between the doping obtainable with the conventional process and with the process according to the invention. They show the considerable increase in the concentration of dopant in the "buffer" layer made possible by the latter process. According to a further embodiment of the invention, the first epitaxial growth P on the substrate P++ (Fig.3b) is followed by the predeposition, instead of implantation, of the dopant antimony and the subsequent diffusion of the latter, reobtaining the structure of Fig.3d; the rest of the process remains unchanged. It is, of course, possible to use arsenic or phosphorus in place of antimony, both in the ion implantation and in the predeposition. It is also obvious that the previously described process can also be used for P-channel HIMOS devices, starting from a substrate N and reversing the type of conductivity of all the susequent regions of Fig.3. With respect to the conventional process of Fig.2, the process according to the previously described invention not only offers the advantages of greater safety against the danger of activating the parasitic thyristor and of reducing the turn-off times, but also the following advantages: the first epitaxial layer grown on the substrate P++ is of the P type (Fig. 3b) and not of N type, thus preventing the occurrence of autodoping (consisting in evaporation of the dopant of the substrate with consequent undesirable incorporation in the epitaxial layer); the quantity of dopant in the layer N+ (buffer) is more easily controlled with the ion implantation technique rather than with that of epitaxial growth, which has a dispersion of 8% both on the resistivity and on the thickness, resulting in a more precise optimization of the layer N+.

Claims: Method of manufacturing an N-channel or P-channel conductivity modulation MOS semiconductor power device, in which the conductivity of the drain region is modulated by the injection of minority carriers of a P-N or N-P junction in series with the drain, said junction comprising a P+ type or N+ type semiconductor substrate (1) over which lie in sequence an N+ type or P+ type thin buffer layer (2) and an N- type or P- type epitaxial layer (3), whereby the formation of the aforesaid buffer layer (2) involves carrying out the following phases in sequence: epitaxial growth of a thin P type or N type semiconductor layer (4) on the aforesaid semiconductor substrate (1); ion implantation or deposition of N type or P type dopant in the aforesaid thin semiconductor layer (4); diffusion of the aforesaid dopant at a sufficient temperature and for a sufficient length of time to enable the formation of an N+ or P+ layer; said phases being followed by the epitaxial growth of the aforesaid N- type or P- type layer (3). Manufacturing method as claimed in claim 1, characterized by the fact that the temperature and the time at which the aforesaid diffusion of the donant in the aforementioned thin semiconductor layer (4) occurs are controlled so that the thickness of the abovementioned resulting N+ or P+ layer is smaller than the original thickness of the aforesaid thin layer (4).

Inventors: MUSUMECI SALVATORE, RONSISVALLE CESARE, MUSUMECI, SALVATORE, RONSISVALLE, CESARE
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1989
Main classification: H01L21
IPC codes: H01L29, H01L21