Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate (1) lines of source and drain (2, 3) parallel and alternated one to another, floating gate areas (8) interposed in a checkerboard pattern between said source and drain lines and control gate lines (12) parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric (10) and aligned with respect to said floating gate areas. Field oxide areas (6) are provided for, formed on the substrate between one and the other of said control gate lines (12) and side fins (9, 13) of the floating gate areas (8) and of the control gate lines (12) superimposed over said field oxide areas (6).

Description: The present invention relates to a matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio, together with a process for its manufacture. Matrices of EPROM memory cells are known having a so-called "tablecloth" structure with source and drain lines parallel and alternated one to another on a semiconductor substrate, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. The tablecloth structures have the favourable distinction of ensuring very high levels of integration (from 4 to 16 Mbit) maintaining topographical layout rules which are accessibile with the current technology. Moreover, they allow the substantial reduction of the number of drain contacts in the matrix area (about 1/8th or 1/16th with respect to standard EPROM matrices) with appreciable benefits from the point of view of defectiveness. Several tablecloth structures have so far been put forward, particularly in US-A- 4 792 925 and in EP-A- 0 352 830. The first of such structures provides for the non-usage of field oxide for matrix insulation. It is in fact possible, starting from a flat active area, to insulate from one another the cells and the source and drain lines (constituting the "bit lines") by means of insulation systems of the P⁺ type, followed by the deposition of layers of dielectric materials and their subsequent planarization. The greatest problem of this structure is represented by the low capacitative coupling between the control gate and the floating gate of each cell. In fact, the coupling area between the gates is practically identical to that between the floating gate and the substrate, so that, if similar thicknesses of oxide are used, the capacitative ratio is seen to assume a value near 0.5, that is lower than that of standard EPROM cells (normally between 0.6 and 0.7). This is too low a value for the cell to have good writing characteristics. Under these conditions the capacitative contribution due to the coupling of the floating gate towards the drain becomes heavier. The memory is consequently very sensitive to the so-called drain turn-on phenomenon, a parasitic phenomenon which can lead to soft-erasure phenomena of non-selected cells and in any case to the worsening of the writing characteristics. The second structure mentioned above provides for the presence, in various configurations, of islands of field oxide in the matrix area. This allows the attainment of larger capacitative couplings between the floating gate and the control gate but at the expense of a greater complexity of accomplishment (high number of masks) and/or of a lower degree of obtainable integration. US-A-4 387 447 discloses an EPROM memory array comprising non-aligned control gates and floating gates which overlap field oxide areas. US-A-4 258 466 discloses a tablecloth structure according to the preamble of claim 1. The object of the present invention is to accomplish a matrix of EPROM memory cells with a tablecloth structure, having an improved capacitative ratio without suffering from simultaneous drawbacks in terms of structural complexity or degree of integration. According to the invention such object is attained with a matrix of EPROM memory cells as defined in claim 1. Processes for the manufacture of a matrix of EPROM memory cells are defined in claims 1 and 2. Put into other words, the present invention provides for areas of superimposition between the floating and the control gates and the areas of the field oxide, whereby it is possible to obtain a higher capacitative coupling between the two gates and thus an improved cell capacitative ratio. At the same time the matrix structure remains simple, similar to that of the original tablecloth structure, and the degree of integration remains consequently high. A possible embodiment of the present invention is illustrated as a non-limiting example, together with the corresponding manufacturing process, in the enclosed drawings, wherein: Fig. 1 shows a plan view of a portion of a matrix of EPROM memory cells with a tablecloth pattern according to the present invention; Fig. 2 shows said matrix portion in a cross-sectional view taken along the line II-II of Fig. 1; Fig. 3 shows said matrix portion in a cross-sectional view taken along the line III-III of Fig. 1; Fig. 4 shows said matrix portion in a cross-sectional view taken along the line IV-IV of Fig. 1; Fig. 5 shows a perspective cross-sectional view taken along the plane of Fig. 2 of a row of memory cells included in the matrix portion of Fig. 1; Fig.s 6 and 7 are plan views of the type of Fig. 1, which show some of the stages of the process according to the invention for the manufacture of a matrix of EPROM memory cells with a tablecloth pattern similar to that illustrated in Fig.s 1 to 5; Fig.s 8 to 11 are cross-sectional views of the type of Fig. 3, which show further stages of the above process. The matrix of EPROM memory cells with a tablecloth pattern illustrated in Fig.s 1 to 5 comprises a semiconductor substrate 1, in particular of silicon, on whose surface there are obtained by diffusion of N⁺ dope parallel lines of source 2 and drain 3 alternated one to another (Fig.s 1, 3 and 4). Between one and the other of said source and drain lines 2, 3 (constituting the so-called "bit-lines") there are defined active areas 4 coated with gate oxide 5, spaced with field oxide areas 6 superimposed over corresponding insulation diffusions 7 of the type P⁺ of the substrate (Fig.s 1, 2 and 5). Over the active areas 4 there are superimposed respective floating gate areas 8, say of polysilicon, having side fins 9 superimposed over corresponding side portions of the adjacent field oxide areas 6 (Fig. 2). Over the floating gate areas 8 there are superimposed and aligned a layer of dielectric 10, a layer of polysilicon 11 acting as a barrier to planarization and lastly control gate lines (or word lines) 12, say of polysilicon or silicide or polycide, parallel to one another and perpendicular to the source and drain lines 2, 3 (Fig.s 1 and 3) and also provided with side fins 13 superimposed over the fins 9 of the floating gate areas 8 and thus over the field oxide areas 6. As shown in Fig.s 3 and 5, on the sides of each set 9, 10, 11 there are formed on the source and drain lines 2, 3 two so-called oxide "spacers" 14 and the remaining area over the same lines 2, 3 is coated with a dielectric layer (oxide which has been deposited or TEOS) 15, suitably planarized. The matrix is thus comprised of a plurality of EPROM memory cells arranged in a tablecloth pattern, each of which is conformed in a manner similar to that indicated with 16 in Fig.s 1 and 2, that is, it has a floating gate area 8 interposed between two adjacent source 2 and drain 3 lines and a control gate line 12 perpendicular to the above lines 2 and 3, the two gates 12 and 8 having respective side fins 13 and 9 superimposed one over the other and over side portions of the field oxide areas 6. Such superimposition, as can be seen from Fig. 5 as well, causes an increase in the capacitative coupling between the two gates (direct function of the area of reciprocal superimposition and inverse function of the thickness of the interposed dielectric) with respect to that between floating gate and substrate, which is subjected to the reducing effect of the presence of thick portions of field oxide, which are aligned with the floating gate areas 8 and the source and drain lines 2,3 in a direction perpendicular to the control gate lines 12. Consequently, the capacitative ratio increases as desired. At the same time the structure remains as simple as that of the original tablecloth-pattern matrix, maintains a good level of compactness and its degree of integration is correspondingly high. An advantageous process for the manufacture of the tablecloth matrix of Fig.s 1 to 5 will now be described with reference to Fig.s 6 to 11. Over a silicon substrate 1 with a P-type doping there are defined with conventional techniques strips of active areas 4 alternated with parallel bars of field oxide 6 superimposed over corresponding insulation diffusions 7 of the type P⁺, thus obtaining the structure illustrated in a plan view in Fig. 6. The thickness of the oxide bars 6 ranges preferably from 1000 to 5000 Å (Ångstrom). Over the entire surface there is then made to grow a layer of gate oxide 5, having thickness preferably ranging between 100 and 300 Å, on which there is then deposited a layer of polysilicon 8, preferably having a thickness ranging from 1000 to 3000 Å, to constitute the floating gate areas. The layer of polysilicon 8 is subsequently subjected to an N-type doping and on it there is deposited or made to grow a dielectric layer 10 (oxide or O.N.O.), preferably having a thickness ranging from 100 to 300 Å, and there is then deposited a layer of polysilicon 11, acting as a barrier to planarization, preferably having a thickness ranging from 500 to 3000 Å. By means of lithographic definition with a first gate mask the anisotropic removal of portions of the polysilicon barrier 11, of the dielectric 10 and of the polysilicon 8 is then carried out, as well as the autoaligned removal of portions of the field oxide 6, obtaining at last the structure shown in Fig. 7, where at the sides of floating gate strips 8 there are uncovered alternating strips of substrate 1, which, after growth of thermal oxide 17 (Fig. 8) for closing the cells and suitable application of N⁺-type dope, are made to become source and drain lines 2 and 3. There follows the laying (Fig. 8) of a dielectric layer 14 (say, of oxide from TEOS), preferably having a thickness ranging from 1000 to 4000 Å, from which, by means of anisotropic removal, spacers are obtained located at the two sides of each cell (Fig. 9). There is subsequently deposited a thick dielectric layer 15 (say, of oxide from TEOS), preferably having a thickness ranging from 3000 to 6000 Å, and, by the application of planarizing material 18 (Fig. 10), the planarization of the dielectric layer 15 is executed until the layer of polysilicon barrier 11 (Fig. 11) is uncovered, using for this purpose any known planarization technique. Lastly, the deposit is carried out of a layer of polysilicon or silicide or polycide (12), preferably having a thickness ranging from 2000 to 6000 Å, and by lithographic definition with a second gate mask, the removal of portions of the upper layers 12 and 11 is executed and then the autoaligned removal of portions of the underlying layers 10 and 8 until it stops on the field oxide 6 and on the deposited dielectric 17. There is thus obtained the structure illustrated in Fig.s 1 to 5. From this point on, all the most widely-different means for the accomplishment of the contact/final interconnection part may be adopted. Naturally the described process may be subjected to many modifications without altering the nature of its essential spirit, which will later be summarized in the claims. In particular, the modifications may refer to the several oxidations, as well as to the accomplishment of the insulations and whatever else. For example, the spacers 14 may be missing. An alternative process can, say, provide that, after the growth of gate oxide 5, the deposition be executed of the layer of floating gate 8 and then the autoaligned removal be carried out of portions of floating gate 8 and of field oxide 6 and that after the formation of the source 2 and drain 3 lines the deposition and planarization be executed of the layer of thick dielectric material 15 over the source (2) and drain (3) lines and the deposition of the dielectric layer 10 and of the layer of polysilicide barrier (11). This alternative process renders the planarization stage less critical, but, at the same time, the lateral diffusion of the source and drain application becomes more critical, as it is carried out before the heat treatment for the dielectric growth between the two gates.

Claims: Matrix of EPROM memory cells with a tablecloth structure, comprising a semiconductor substrate (1), source lines (2) and drain lines (3) parallel to and alternated with one another on said substrate (1), floating gate areas (8) interposed in a checkerboard pattern between said source lines (2) and said drain lines (3), control gate lines (12) parallel to one another and perpendicular to said source and drain lines (2, 3) and superimposed to and aligned with said floating gate areas (8) with an intermediate dielectric layer (10) being interposed therebetween, and field oxide areas (6) formed on said substrate (1) in spaces between said source and drain lines (2, 3) and between said control gate lines (12) and extending below lateral portions of the floating gate areas (8) and superimposed portions of said dielectric layer (10) and said control gate lines (12) so as to provide each floating gate area (8) and corresponding control gate line (12) with a pair of symmetrical lateral fins (9, 13) superimposed over respective field oxide areas (6), characterized in that said field oxide areas (6) are laterally aligned with said floating gate areas (8) and said source and drain lines (2, 3) in directions perpendicular to said control gate lines (12). Process for the manufacture of a matrix of EPROM memory cells with a tablecloth structure, characterized in that it comprises the following stages in succession: a) definition of strips of active areas (4) alternated with parallel bars of field oxide (6) on a semiconductor substrate; b) growth of gate oxide (5); c) deposition of a floating gate layer (8), then of a dielectric layer (10) and then of a barrier polysilicon layer (11); d) autoaligned removal of portions of the barrier layer (11), of the dielectric layer (10), of the floating gate layer (8) and of the field oxide (6) to form parallel strips which are perpendicular to said field oxide bars (6) for the definition of uncovered strips of substrate at the sides of said parallel strips; e) implantation of dope in said uncovered strips for the formation of source (2) and drain (3) lines; f) deposition and planarization of a layer of thick dielectric material (15) over said source (2) and drain (3) lines; g) deposition of a control gate layer (12); h) removal of portions of said control gate layer (12) and of said parallel strips of floating gate (8), dielectric layer (10) and barrier layer (11) down to said field oxide (6) for the definition of EPROM memory cells arranged in a checkerboard pattern at the intersection of said source (2) and drain (3) lines with control gate lines (12) resulting from the removal of portions of said control gate layer. Process for the manufacture of a matrix of EPROM memory cells with a tablecloth structure, characterized in that it comprises the following stages in succession: a) definition of strips of active areas (4) alternated with parallel bars of field oxide (6) on a semiconductor substrate; b) growth of gate oxide (5); c) deposition of a floating gate layer (8); d) autoaligned removal of portions of the floating gate (8) and of the field oxide (6) to form parallel strips which are perpendicular to said field oxide bars (6) for the definition of uncovered strips of substrate at the sides of said parallel strips; e) implantation of dope in said uncovered strips for the formation of source (2) and drain (3) lines; f) deposition and planarization of a layer of thick dielectric material (15) over said source (2) and drain (3) lines; g) deposition of a dielectric layer (10) and of a barrier polysilicon layer (11); h) deposition of a control gate layer (12); i) removal of portions of said control gate layer (12) and of said parallel strips of barrier layer (11), dielectric layer (10) and floating gate layer (8) down to said field oxide (6) for the definition of EPROM memory cells arranged in a checkerboard pattern at the intersection of said source (2) and drain (3) lines with control gate lines (12) resulting from the removal of portions of said control gate layer.

Inventors: BELLEZZA ORIO, BELLEZZA, ORIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1989
Main classification: G11C16
IPC codes: H01L27, H01L21, H01L29