Nand gate circuits

Abstract: A NAND gate circuit, which can be used for a decoder circuit, includes a high potential voltage source (V cc ), an output terminal (V OUT ), a load element (T₁) connected between the high potential voltage source (V CC ) and the output terminal (V OUT ), and a driving circuit serially connected between the output terminal (V OUT ) and a low potential voltage source (V ss ) and comprising a plurality of serially-arranged driving transistors (T₂,T₃,T₄,T₅,T₆), respective input signals (a,b,c,d,e) being applied to the transistor gates. At least one of the transistors of the driving circuit has a driving performance different from at least one other transistor of the driving circuit, whereby improvements are attainable as regards erroneous operation of the NAND gate circuit, when subject to noise, by virtue of improved uniformity of the input threshold voltage for different combinations of input signals.

Description: The present invention relates to NAND gate circuits, for example for use in decoder circuits provided in semiconductor memory devices. Figure 1(A) shows an ordinary conventional decoder circuit and in Fig. 1 V cc is a source voltage, for example 5 V, while V ss is a ground potential (0 V). A transistor T₁ used for a load means, for example, an N channel depletion type MOS transistor, and driving transistors T₂ and T₃ , for example, N channel enhancement type MOS transistors used as a driving circuit, are provided. In this NAND gate circuit, both an input a to the transistor T₂ and an input b to the transistor T₃ are binary signals and the transistors T₂ and T₃ are of the same type. In the circuit, when, for example, the voltage of the input a is fixed at 5 V and the voltage of input b is increased from 0 V to 5 V or decreased from 5 V to 0 V, the output voltage V OUT changes from a voltage of nearly 5 V to nearly 0 V or from nearly 0 V to nearly 5 V. Therefore, if, in the above example, it is desired that when an input voltage exceeds 2 V, the level of the voltage should be discriminated as "H", and when the voltage is lower than 2 V, it should be discriminated as "L", the output level of the NAND gate circuit should change from "H" to "L" when the voltage of the input b reaches 2V as it is increased from 0 V to 5 V. The same should desirably apply when the voltage of the input a is varied in the same way as above. The input voltage at which the level of the output voltage of the NAND gate circuit changes from "H" to "L" or vice versa is called the input threshold voltage of the NAND gate circuit. In a NAND gate circuit, however, the input threshold voltage changes depending upon the respective values of the input voltages applied to the inputs a and b at any one time. Namely, the input threshold voltage of the NAND gate circuit differs as shown in Fig. 1(B), in three ways depending on whether the input voltage b was changed while the input voltage a was fixed at 5 V (only the input voltage b was changed) as shown by a curve (2) in Fig. 1(B), the input voltage a was changed while the input voltage b was fixed at 5 V (only the input voltage a was changed) as shown by a curve (1) in Fig. 1(B), or both the input voltages a and b were simultaneously changed (both the input voltages a and b are changed) as shown by a curve (3) in Fig. 1(B). For example, the input threshold voltage of the NAND gate circuit obtained when only the input voltage b is changed and the input voltage a is fixed at 5 V is 1.5 V, the input threshold voltage obtained when the input voltage a is changed and the input voltage b is fixed at 5 V is 2.0 V, and the input threshold voltage obtained when both the input voltages a and b are simultaneously changed is 2.5 V. The reasons why this happens is such a conventional NAND gate circuit are as follows. In the case when the input voltage b is changed while the input voltage a is fixed at 5 V, the source voltage of the transistor T₃ is V ss , i.e. 0 V. When the input voltage a is changed while the input voltage b is fixed at 5 V, the drain voltage of the transistor T₃ is initially above 0 V due to the transistor T₃ being ON, enabling current to flow therein. The source voltage of the transistor T₂ is thus initially also above V ss , i.e. 0 V since the drain voltage of the transistor T₃ corresponds to the source voltage of the transistor T₂. Therefore, there is a "back gate effect" in which a threshold voltage V th of a transistor is increased when the source voltage thereof becomes higher than the substrate voltage. Also, the gate-source voltage of the transistor T₂ is reduced at that time. Therefore, the output of the NAND gate circuit cannot be changed unless a relatively high voltage is applied to the input a of the transistor T₂. This means that, in this situation, the load T₁ of this circuit cannot be driven when the gate voltage of the transistor T₂ is relatively high. In the case when both input voltages are changed together, the threshold voltage of the NAND gate circuit will be substantially increased since the total current driving performance of each transistor T₂ and T₃ is weakened compared with the performance obtained in the situation in which one of the input voltages a and b is fixed at 5 V. As explained above, when the threshold voltage of the NAND gate circuit changes according to the combination of the input voltages applied to the input terminals of the circuit, a problem arises in that the noise immunity, i.e. the immunity to noise, for a particular signal input to a certain transistor can become different from the others and the total noise immunity can deteriorate accordingly. This situation will be explained more specifically with respect to Fig. 1(B). The transistors used in the NAND gate circuit may have the following characteristics, for example. The transistors T₂ and T₃ have a threshold voltage V th of 0.6 V, a gate oxide film thickness of 350 Å, a gate width of 50 µm, and a gate length of 2 µm, while the transistor T₁ has a threshold voltage V th of -3.5 V, a gate oxide film thickness of 350 Å, a gate width of 20 µm, and a gate length of 5 µm. As shown in Fig. 1(B), when the NAND gate circuit is operated at voltage V cc of 5 V, the input threshold voltages are 2.15 V, 1.95 V and 2.45 V in the cases when the input voltage a alone is changed, the input voltage b alone is changed and both the input voltages a and b are simultaneously changed, respectively. The curves (1), (2), and (3) show respective input-output characteristics of the NAND gate circuit in the above-mentioned three cases. When the input threshold voltage of the NAND gate circuit differs between different inputs to the circuit, the immunity to noise in the input voltages will become different, and thus the overall noise immunity of the circuit will detoriorate. For example, as apparent from the curve (3), if the input voltages a and b are nominally both V cc = 5 V, the NAND gate circuit outputs a voltage having a level of "H" instead of "L" when noise is added to any one of the input signals to reduce the input signal voltage level below 2.55 V. While, if the input voltage a is set at V cc = 5 V and the input voltage b is set at V ss = 0 V, the NAND gate circuit outputs a voltage having a level of "L" instead of "H" when noise is added to the input signals to increase the input signal voltage level over 1.95 V. This means that the noise immunity for the input voltage of the NAND gate circuit is 2.55 V for voltage descending from V cc and 1.95 V for voltage increasing from V ss . Thus a poor noise immunity is obtained and a problem arises of deterioration of the overall noise immunity. If more driving transistors are connected in series in the driving circuit in the NAND gate circuit, noise immunity can deteriorate still further. There is thus a significant problem in a decoder circuit including an NAND gate circuit when there are more than five transistors serially arranged, in that the conventional NAND gate circuit has poor noise immunity. Such a NAND gate circuit will frequently operate erroneously with respect to the signals input to the gates of the driving transistors of the driving circuit. Since the NAND gate circuit is generally used for a main circuit of a decoder connected to a memory cell array in a memory device, when the NAND gate circuit erroneously operates due to noise added to the signals, input to the gates of the driving transistors, the erroneous information generated from the NAND gate circuit, i.e., decoder, significantly affects the memory cell array or the like in the memory device, causing erroneous information to be output from the memory device. How the erroneous operation in a NAND gate circuit, i.e., decoder, affects a semiconductor memory device will be explained with reference to Figs. 2 to 5. One type of decoder including a NAND gate circuit has a circuit construction as shown in Fig. 2, and is known from Japanese Unexamined Patent Publication (Kokai) No. 61-45496. Referring first to Fig. 2, in a decoder circuit consisting of NAND gate circuit, a voltage source V PPI can be internally switched to two different voltage levels such as a low voltage of about 5 V (referred to as V cc hereinafter) in a reading mode and a high voltage of about 12.5 V (referred to as V PP hereinafter) in a writing mode. The decoder includes a decoder circuit and a CMOS inverter (IV). In the decoder circuit, i.e., a NAND gate circuit, an N-channel depletion type MOS transistor T₁ and N-channel enhancement type MOS transistors T₂ to T₅ are provided. In the inverter, an N-channel enhancement type MOS transistor T₇ and a P channel enhancement type MOS transistor T₆ are provided. As apparent from Fig. 2, the NAND gate circuit consists of the transistor T₁ as a load means and the transistors T₂ to T₅ as a driving circuit. The output N₁ which drives the CMOS inverter (IV) consists of the transistors T₆ and T₇. An output of the CMOS inverter (IV) connects to a word line (WL). A memory cell transistor MC is provided at each cross point of the word line (WL) and bit lines BL₀ , BL₁ , BL₂ ·····. Input address signals a to d are applied to the gates of the driving transistors T₂ to T₅ , respectively. In a stable condition, these input address signals selectively are at either the V cc level (logic "1") or V ss level (logic "0", usually denoting ground level, i.e., 0 V). When all the voltage levels of the input address signals a to d are V cc , the node N₁ (output of the decoder circuit) is reduced nearly to V ss , i.e., 0 V, regardless of whether the decoder source voltage V PPI is V cc or V PP . Thus, the node N₂ , i.e., the output voltage of the inverter is increased to V PPI . If one or more of the input address signals a to d is V ss , the output N₁ of the decoder circuit (DEC) is increased to V PPI . Thus, the output of the inverter N₂ is reduced to V ss , i.e., 0 V. Here, the input address signals a to d are derived from, for example, the outputs of an address buffer circuit in which the address signals applied externally thereto are subjected to a waveform shaping operation inside the chip. In a conventional semiconductor memory device, when the decoder erroneously operates, erroneous information is transferred to a memory cell array and eventually incorrect information is output from the memory device. Generally speaking, as shown in Fig. 3, address signal inputs externally provided are applied to the input terminal of a buffer circuit with a waveform as shown in Fig. 3(a), are subjected to a waveform shaping operation, and are output to the input terminals of the decoder circuit with a waveform as shown in Fig. 3(b). In this situation, suppose that when a noise Y is added to the address signal as shown in Fig. 3(a), the output signal of the address buffer inherently has the abnormal signal portion X and X′ in response to the noise portion Y as shown in Fig. 3(b). Then, when the output signal of the address buffer including such an abnormal signal portion X is input to the decoder circuit, the decoder will erroneously operate depending upon the level of the abnormal signal portion and the level of the threshold set for the decoder circuit. If the level of the abnormal signal portion is higher or lower than the threshold level set for the decoder circuit, the decoder circuit will erroneously operate and output a erroneous signal information Z to the word line WL as shown in Fig. 3(c). More specifically, when the decoder circuit is set to that, as shown in Fig. 4, outputs of the address buffer having the "H" level are applied to the gates a , b , c of the transistors T₂ to T₄ , the output thereof of the "L" level is applied to the gate d of the driving transistor T₅ of the driving circuit of the decoder circuit, the input threshold voltage is set at 1.5 V. Accordingly, in this situation, the output V OUT at the node N₁ of the decoder circuit is at the "H" level and thus the output at the node N₂ of the inverter is at the "L" level, as shown in Fig. 4. Now, suppose that when an abnormal signal portion X having a level exceeding 1.5 V is instantly applied to the input terminal d , the level of the output V OUT of the decoder circuit is instantly switched to the "L" level instead of being the "H" level naturally, whereby the level of the output of the inverter is also instantly switched to the "H" level instead of being the "L" level naturally. Therefore, in this situation, the word line WL connected to this decoder is a non-selected word line and thereby the signal level thereof inherently is "L", although the level of the word line will be increased from the level of 0 V to form an abnormal signal portion z as shown in Fig. 3(c) so as to mistakenly read or write information from or into a certain memory cell. While, when the duration of such an abnormal signal portion is remarkably short, such a signal does not affect the circuits arranged downstream of the circuit concerned so much, although, when the duration is relatively long, the effect is considerable. In a memory cell array used in a semiconductor memory device, a plurality of pairs of resistors and capacitors are serially arranged therein. An equivalent circuit thereof can be drawn as shown in Fig. 5. Therefore, a signal output from an inventor including an abnormal signal level will be delayed and the duration of the abnormal signal portion will be prolonged due to the existence of the plurality of time constants created by CR. When such a prolonged signal portion p is output to the sense amplifier, the sense amplifier will necessarily read erroneous data p with a threshold level V L for a period t as shown in Fig. 9. To avoid such erroneous operation of the decoder circuit and thus also the semiconductor memory device due to such deterioration of the overall noise immunity, it has been proposed to construct an address buffer circuit which will not respond to noise so sharply, but it is very difficult to completely prevent such problems by such a method. As explained above, in a conventional NAND gate circuit, even if the NAND gate circuit is composed of a plurality of transistors as a driving circuit, all of which have the same current driving performance, i.e., all of the transistors have the same characteristics and the same power, the input threshold voltage of the NAND gate circuit differs depending upon the input-condition of the input signals and thus the overall noise immunity is deteriorated and erroneous operation of the NAND gate circuit frequently occurs. According to the present invention there is provided NAND gate circuitry including: a load device connected between a first power supply line and an output terminal of the circuitry; a driver circuit, connected between a second power supply line and the said output terminal and comprising a plurality of transistors connected together in series, respective gates of the transistors being connected to respective logic input nodes of the circuitry; characterised in that the current driving performance of one of the said transistors is higher than the current driving performance of a second transistor of the said plurality, which second transistor is connected between the said one transistor and the said second power supply line, thereby to reduce variation between the respective input threshold voltages of the different input nodes of the circuitry. Such a NAND gate circuit has improved immunity to noise, because such variation of the input threshold voltage according to the combination of input signals applied thereto is reduced. Such a circuit embodying the present invention may be advantageously employed in a decoder circuit within a semiconductor memory device to enable the device to operate accurately both in the writing mode and the reading mode even when noise is added to the input signals. Reference will now be made by way of example, to the accompanying drawings, in which: Figure 1(A) shows a conventional NAND gate circuit; Fig. 1(B) is a graph showing the input-output curve of an input threshold voltage of the conventional NAND gate circuit; Fig. 2 is a diagram of an example of a conventional semiconductor memory device with a decoder circuit composed of NAND gate circuit; Figures 3(A), 3(B) and 3(C) are waveforms of an address signal input to an address buffer, an output signal from the address buffer, and a voltage level of a word line in a conventional semiconductor memory device, respectively; Fig. 4 is a block diagram of a decoder of a conventional semiconductor memory device showing one situation thereof as an example; Fig.5 is an equivalent circuit of one of the word lines in a memory cell array; Fig. 6 is a block diagram of a semiconductor memory device in which a NAND gate circuit embodying the present invention is used as a main part of a decoder circuit; Fig. 7(A) shows an embodiment of the NAND gate circuit of the present invention; Fig. 7(B) is a graph showing the input-output curve of an input threshold voltage of the NAND gate circuit shown in Fig. 7(A); Fig. 8(A) shows another embodiment of the NAND gate circuit of the present invention; Fig. 8(B) is a graph showing the input-output curve of an input threshold voltage of the NAND gate circuit shown in Fig. 8(A); Fig. 9 is chart illustrating the condition when a sense amplifier reads erroneous date on a signal taken out from a memory cell. The overall construction of a semiconductor memory device employing a NAND gate circuit embodying the present invention as a decoder circuit is shown in Figure 6. The semiconductor memory device includes a row address buffer 31, a row decoder 32, a memory cell array 36, a column address buffer 33, a column decoder 34, and a switching circuit 41 for setting the decoder voltage at V PP in the writing mode and at V cc in the reading mode. To an output terminal N₃ of the memory cell array 36, a sense amplifier 37, an output buffer 38, a date-in buffer (D IN buffer) 39, and a writing circuit 40 are connected. In this device, the address signals for word lines of the memory cell array are input to the terminal d₁ , d₂ ... d n of the row address buffer 31 to perform the waveform shaping. The outputs therefrom are applied to the input terminals a , b , c and d of the row decoder 32, for example. In Fig. 6., the NAND gate circuit for the decoder circuit comprises a plurality of the transistors, for example, one transistor for a load transistor and four transistors as driving transistors used as a driving circuit, as shown in Fig. 2. It is also, however, possible to use two and five transistors as shown in Figs. 7(A) and 8(A). The input terminals a to d of the row decoder in Fig. 6 correspond to the input terminals a and d of the driving transistors T₂ to T₅ provided in the NAND gate circuit as shown in Figs. 2. The row decoder 32 includes a load means T₁. A decoder circuit including the NAND gate circuit includes a plurality of serially arranged driving transistors T₂ to T₅ as a driving circuit, and an inverter circuit IV. As explained above, the driving transistors consisting the NAND gate circuit are characterized in that at least one has a driving performance different from the others. The output of the decoder circuit 32 is applied to the word line WL to select one. The word lines WL are part of a memory cell array 36 in which a plurality of memory cells MC are provided at cross points between the word lines WL and the bit lines BL as shown in Fig. 2. The semiconductor device may be an EPROM, EEPROM, or the like. The address signals for the bit lines BL of the memory cell array are input to the terminals c₁ , c₂ ... c n of the column address buffer 33. The outputs are applied to the column decoder 34 in the same manner as explained above. The output of the decoder circuit 34 is applied to the bit lines BL₁ , BL₂ , ... BL n to select a certain bit line through a transistor. As shown in Figure 6, the semiconductor memory device is provided with a voltage switching circuit 41 to switch the decoder source voltage from a high level V PP to a low level V cc or vice versa in accordance with the reading mode or the writing mode. The resultant voltage is applied to the decoder source voltage terminal V PPI as shown in Figure 2 in the row decoder 32. In the reading mode, the signal voltage output from the input and output terminal N₃ of the memory cell array 36 is applied to the sense amplifier 37 to read them. The output from the data input-output terminal T(I/O) goes through an output buffer circuit 38. In the writing mode, the data to be written is input to the data-in buffer circuit 39 through the data input-output terminal T(I/O). The output from the data-in buffer circuit 39 is input to the input-output terminal N₃ of the memory cell array 36 through the writing circuit 40. In the present invention, the load element T₁ may be constructed by a transistor or a resistor. A NAND gate circuit embodying the present invention comprises a plurality of driving transistors, each of which has a sufficiently large current driving characteristic compared with the load element for driving. The number of driving transistors used in the NAND gate circuit may be more than two and can be determined as desired in accordance with the object of the circuit used. For example, when it is used as a decoder, five or six transistors are commonly used. Generally, regarding the NAND gate circuit, in order to prevent erroneous operation due to a variation of the input signals, it is preferable that the switching point of an input voltage (explained with reference to Fig. 1 (B)) be approximately constant at a level of, for example, V cc /2. A NAND gate circuit embodying the present invention has an input threshold voltage which exhibits acceptably low variation for all combinations of input signals. This keeps the circuit from operating erroneously in response to noise. The respective current driving performances of the driving transistors are adjusted so that the current driving performance, i.e. current driving characteristic , of a transistor or a group of transistors in the driving circuit of the NAND gate circuit and arranged closer to the high potential voltage side is larger than that of a transistor or a group of transistors arranged closer to the low potential voltage side. More specifically, in an embodiment of the present invention having two driving transistors, as shown in Fig. 7(A), the current driving performance of the second transistor T₃ connected between the first transistor T₂ and a source wire of the low potential voltage side is lower than that of the first transistor T₂ arranged closest to the output terminal N₁. Further, when the NAND gate circuit includes third, fourth and fifth transistors, it is preferable that the farther the transistor from the first driving transistor in the direction of the low potential voltage side, the smaller the current driving performance of the driving transistor. The plurality of the driving transistors may be classified into a plurality of groups and the transistors belonging to a group arranged closer to the low potential source than another group may have a smaller current driving performance than the transistors belonging to the other group. Thus, in designing a NAND gate circuit embodying the present invention, the current driving performance of each of the driving transistors of the circuit is chosen so that each transistor or each of the groups of the transistors has a different current driving performance. Therefore, the input threshold voltages of the NAND gate circuit can be fixed at nearly the same value or at closely approximating values for all combinations of the input signals used in the NAND gate circuit, for example, where the gate input voltage to a certain driving transistor is changed, while the gate input voltages to the rest of the driving transistors are set at a fixed voltage of 5 V or where all gate input voltages to all the gates of the driving transistors are simultaneously changed. To improve the overall noise immunity of the NAND gate circuit, it is preferable that the input threshold voltage be set to a value the same as close to a half of the source voltage (V cc /2). In accordance with the technical concept of varying the current driving characteristic of the driving transistors, whilst the conventional NAND gate circuit of Figure 1(A) uses two driving transistors T₂ and T₃, each having an input threshold voltage V th of 0.6 V, an embodiment of the present invention uses a driving transistor T₂ having V th of 0.6 V and a driving transistor T₃ having a V th of 0.8V. There are several methods for varying the driving performance of the driving transistors. The first is to adjust one or both of the channel length (L) or an channel width (W) of the transistors, in another words, the ratio thereof (W/L). The second is to change the input threshold voltage V th of the transistor by varying the concentration of impurities of a substrate by ion implantation or by varying the film thickness of the gate oxide film of the transistor. The first method is more advantageous than varying the V th from the manufacturing process point of view. In the present invention, all of the driving transistors used as the driving circuit may be of the same type. The extent of the adjustment can be freely determined depending upon the amount of the load, the source voltage the input voltage and the number of the transistors used, and the like. The NAND gate circuit can be used effectively as a decoder circuit required to have a large noise immunity, particularly in a semiconductor memory device. In another embodiment, five or six driving transistors are used as shown in Fig. 8(A). The driving performance of the driving transistors may be varied by the manner explained above, although it is not preferable to give each driving transistor a different V th . Accordingly, as mentioned above, the driving transistors may be classified into a plurality of groups and a different V th set out for each group. That is, all of the transistors belonging to one group will have the same driving performance, which is different from that of the transistors belonging to other group. More specifically, the closer to the low potential side source wire (V ss ) the group is arranged, the smaller the driving performance the transistors of the group should possess. As stated above, the current driving characteristics of the driving transistors used in the NAND gate circuit are made different. Driving transistors wherein current can easily flow are given a small driving performance while driving transistors wherein current cannot easily flow are given a large driving performance. Any number of groups may be used and it is not necessary that each group have the same number of transistors. Therefore, the range of variation of the input threshold voltage of the NAND gate circuit can be reduced and the input threshold voltages obtained under different conditions made nearly the same value. It is possible to set the central value of the input threshold voltage at or near to a value of a half of the source voltage (V cc /2). Therefore, even when noise is added to an input signal voltage or when the input signal is in an intermediate transition condition, the NAND gate circuit can operate accurately without any erroneous operation. The above explanation was made referring to transistors of one type of conductivity in the NAND gate circuit, as an example, but the opposite type thereof may be used. Also, the decoder source voltage V PPI and V cc may be either an external source voltage or internal source voltage. Further, the NAND gate circuit was explained in terms of use as a row decoder circuit as shown in Fig. 6, but can also be used as a column decoder. More specific embodiments of the present invention will be explained below. Figure 7(A) shows a circuit diagram of a NAND gate circuit embodying the present invention. In Fig. 7(A), the NAND gate circuit is provided with a source voltage V cc , a ground voltage V ss i.e., 0 V, an N-channel depletion type load transistor T₁ , and the N-channel enhancement type transistors T₂ and T₃ with different input threshold voltages. The V th of the transistor T₃ is set at 0.8 V, while the V th of the transistor T₂ is set out at 0.6 V, i.e., the V th of the transistor T₃ is higher than that of the transistor T₂. Due to this, the input threshold voltage of the NAND gate circuit can be made nearly the same value for all combinations of input signals given to input terminals a and b . In this embodiment, when the NAND gate circuit is operated at V cc = 5 V, for example, as shown in Fig. 7(B), the input threshold voltage of the NAND gate circuit is 2.15 V when the input voltage applied to one of the input terminals a or b is changed and the input voltage of the other input terminal is fixed. The input threshold voltage is 2.5 V when both the input voltages to the input terminals a and b are simultaneously changed. Accordingly, a noise margin of 2.50 V is provided when descending from V cc and one of 2.15 V when rising from V ss . Therefore, the NAND gate circuit of Fig. 7(A) possesses a greater overall noise resistance than the comparable conventional NAND gate circuit of Figure 1(A). Figure 8(A) shows a further NAND gate circuit embodying the invention having five input terminals provided with five driving transistors. The variation in input-output characteristics of a conventional NAND gate circuit including five identical driving transistors, connected exactly as shown in Fig.8(A), will be explained. In the conventional NAND gate circuit, all of the driving transistors T₂ to T₆ have the same driving performance. Assume, the transistors T₂ and T₆ each have a V th of 0.6 V, a thickness of a gate oxide film of 350 Å, a gate width of 50 µm, and a gate length of 2 µm, while the transistor T₁ has a V th of -3.5 V, a thickness of a gate oxide film of 350 Å, a gate width of 8 µm, and a gate length of 5 µm. Figure 8(B) is a graph of the input-output curve of the conventional NAND gate circuit. The curves (1) to (6) are obtained when the NAND gate circuit is operated at a V cc of 5 V. Curve (1) was obtained when all of the inputs a to e were varied. Curve (2) was obtained when only the input a was varied, while the inputs b to e were fixed at V cc . Curve (3) was obtained when only the input b was varied, while the inputs a and c to e were fixed at V cc . Curve (4) was obtained when only the input c was varied, while the inputs a , b , d and e were fixed at V cc . Curve (5) was obtained when only the input d was varied, while the inputs a to c and e were fixed at V cc . Curve (6) was obtained when only the input e was varied, while the inputs a to d were fixed at V cc . As apparent from Fig. 8(B), the lowest input threshold voltage of the NAND gate circuit is 1.40 V, obtained when only the input e was only varied, while the highest thereof is 2.40 V, obtained when all of these inputs a to e were changed. Figure 8(C) shows the input-output curves of the NAND gate circuit of Fig. 8(A). In the NAND gate circuit of Fig. 8(A), the five transistors T₂ to T₆ are divided into two groups, one composed of two transistors T₂ and T₃ and the other of three transistors T₄ , T₅ , and T₆. Each transistor belonging to the former group has a V th of 0.6 V, while each of the latter group has a V th of 0.8 V. As shown in Fig. 8(C), the lowest input threshold voltage of the NAND gate circuit is 1.65 V, obtained when only the input e was varied, while the highest input threshold voltage was 2.45 V, obtained when all of the inputs a to e were simultaneously varied. Thus, the noise immunity of the NAND gate circuit of Fig. 8(A) can be greater than the above-discussed conventional 5-input NAND gate cirucit. Note that, in Figs. 8(B) and 8(C), only six input-output characteristic curves are indicated, which were obtained under six different input conditions as explained above, many other such curves can be drawn which can be obtained under other conditions, for example, when the input voltages a and b are varied while the rest are fixed or the input voltages a , c , and e are varied and the input voltages b and d are fixed. As explained above a NAND gate circuit embodying the present invention can provide improved overall noise immunity since the input threshold voltages of the NAND gate circuit obtained for all combinations of the input signals can be set at nearly the same value. Such a NAND gate circuit is less prone to operate erroneously under noisy input conditions, so erroneous operation of a memory cell array connected to the NAND gate in a semiconductor memory, for example, caused by noise can also effectively be prevented.

Claims: NAND gate circuitry including: a load device (T₁) connected between a first power supply line (V cc ) and an output terminal (V OUT ) of the circuitry; a driver circuit (T₂, T₃), connected between a second power supply line (V ss ) and the said output terminal and comprising a plurality of transistors connected together in series, respective gates of the transistors being connected to respective logic input nodes of the circuitry; characterised in that the current driving performance of one of the said transistors (T₂) is higher than the current driving performance of a second transistor (T₃) of the said plurality, which second transistor is connected between the said one transistor and the said second power supply line, thereby to reduce variation between the respective input threshold voltages of the different logic input nodes of the circuitry. NAND gate circuitry as claimed in claim 1, wherein the said one transistor (T₂) is the transistor in the said series which is closest to the said output terminal (V OUT ). NAND gate circuitry as claimed in claim 1 or 2, wherein all the transistors in the said series have different respective current driving performances, the current driving performances of the transistors increasing along the series in the direction from the said second power supply line (V ss ) towards the said output terminal (V OUT ). NAND gate circuitry as claimed in claim 1 or 2, wherein at least two successive transistors in the said series have the same current driving performance. NAND gate circuitry as claimed in any preceding claim, wherein the differences in current driving performance of the transistors of the said series are obtained by varying the respective channel width-length ratios (W/L) of the transistors amongst the different transistors of the said series. NAND gate circuitry as claimed in any one of claims 1 to 4, wherein the differences in current driving performance of the transistors of the said series are obtained by varying the concentration of impurities in the respective channel regions of the transistors amongst the different transistors of the said series. NAND gate circuitry as claimed in any one of claims 1 to 4, wherein the differences in current driving performance of the transistors of the said series are obtained by varying the thickness of the respective gate oxide films of the transistors amongst the different transistors of the said series. A semiconductor memory device having a decoder circuit including NAND gate circuitry as claimed in any preceding claim.

Inventors: YOSHIDA MASANOBU, YOSHIDA, MASANOBU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H03K19
IPC codes: H03K19, H03K17