An integrated circuit for an electronic timepiece

Abstract: An integrated circuit for an electronic time piece comprises a non-volatile semi-conductor memory (8) for storing control data for use in controlling the functioning of the electronic time piece. The integrated circuit further comprises reference data supply means (9) for supplying reference data representing the same functions as the control data, and means (10 to 15) for generating an output for testing purposes based on the reference data.

Description: The present invention relates to an integrated circuit (hereinafter referred to as an IC) for an electronic time piece, and more particularly, to an IC incorporating a non-volatile semi-conductor memory (hereinafter referred to as an EPROM) designed to control the operation of an electronic time piece. The invention also relates to an electronic time piece including such an IC. A conventional IC for an electronic time piece having an EPROM has required testing, by writing data to and erasing data from the EPROM, every time a check needs to be made as to whether the IC functions in accordance with the data stored in the EPROM. A known arrangement in which an EPROM is incorporated in an IC and in which the data stored therein is utilised for controlling the function of an electronic time piece has the advantage not only of making the IC multi-functional but also of enabling it to be put to a wide use. When an IC is provided with a plurality of EPROMs, however, every combination of them has to be tested. The disadvantage of this is that the time required for such testing is extremely long if all the combinations are properly tested, because it takes so much time to write data to and erase data from each EPROM. For this reason, electronic time pieces provided with such ICs have suffered from high production costs, resulting from the expensive testing of the ICs and the reduced production yield. This is especially aggravated when an EPROM of an ultra-violet ray erase type is incorporated in an IC because the erase time for such an EPROM is particularly prolonged. Accordingly, it is an object of the present invention to provide a high quality, multi-functional IC for an electronic time piece, which can be tested within a shorter time. In accordance with the present invention, there is provided an integrated circuit for an electronic time piece, comprising a non-volatile semi-conductor memory for storing data for use in controlling a plurality of functions of the timepiece, reference data holding means for holding reference data for use in controlling the functions of the timepiece, selecting means for selecting control data from the storing memory for normal operation of the timepiece or reference data from the holding means for testing purposes, means for generating an output based upon the data received from the selecting means and test clock signal generating means for generating test clock signals to change the output of the holding means and the reference data selected therefrom, characterised in that the storing memory is of the EPROM type, the holding means is of the EPROM type, and there is provided a test mode of the integrated circuit in which the functioning of the integrated circuit is confirmed by changing the reference data held by the holding means in accordance with the test clock signals (TCLROM) from a terminal of the test clock signals generating means and selecting such data for output at the timing of the control data instead of using the control data produced from the storing memory, so that correct functioning of the integrated circuit can be confirmed without erasing the data in the storing memory. With this arrangement, the functioning of the IC can be tested without re-writing the control data stored in the EPROM and so the testing time can be significantly shortened. Consequently, the use of such an IC makes it possible to provide an inexpensive, high performance electronic time piece, which is immune from the problems of the prior art. The non-volatile semi-conductor memory may be of an ultra-violet ray erase type. In an article entitled "A 1.5V ONLY EEPROM BASED ON FOWLER-NORDHEIM EMISSION DESIGN, TECHNOLOGY AND APPLICATIONS" by Bernard Gerber in International Congress of Chronometry Proceedings, Besancon, 4-6th October 1984, Vol. 1, Congress XI, Session III, Communication 3, Pages 17 to 21, is described a CMOS process by which digital and analog circuits are produced, including non-volatile memories programmable from a 1.5 Volt power supply. An article on pages 1 to 7 of I.E.E.E. Electro Vol. 8 (1983) New York, USA, by John Birkner, Vincent Coli and Frank Lee, entitled "NEW PROM ARCHITECTURE SIMPLIFIES MICROPROGRAMMING", discloses a board carrying a PROM, a multiplexer and a shadow register. No reference to the possibility of using the board in a timepiece is made. Control programs are stored in a PROM to instruct a system to perform various functions, and it is proposed to turn a sequential circuit into a non-sequential circuit in order to perform some diagnostics. Diagnostic data in the shadow register can be shifted into the circuitry to generate output for testing based upon the reference data so stored. US-A-4538923 discloses a test circuit for a watch integrated circuit capable of setting an operating mode with the operations of a plurality of switches. The circuit has a ROM for deciding the next operating mode in response to the outputs of the switching circuit including the outputs of the switches and the outputs of flip flops for holding the present operating mode. A signal for a test terminal sets an initial state and provides the predetermined data instead of the outputs of the flip flops from the ROM so that an operator can set an arbitrary operating mode readily in a short time. US-A-4001553 discloses a one chip counter arrangement and high-speed test circuit for an electronic watch clock, comprising separate divider stages interconnected with respect to one another in order to be rapidly tested in a test mode or to be operated in a normal mode of operation, by a minimum number of components taking up a minimal amount of space. JP-A-57139684 discloses a motor driving circuit including a ROM whose mode is controlled by a detector of rotation of the motor. JP-A-58223088 discloses an electronic timepiece with temperature compensation provided from a circuit including a temperature detection circuit, a gradient adjustment circuit and an offset adjustment circuit which fees a frequency correction circuit. US-A-4150536 discloses an electronic timepiece including a reversible stepping motor driven by an increased driving current during high speed time correction when a manually operable external control member is actuated during time correction. DE-A-3031884 discloses a board carrying two integrated circuits, a master and slave, which are connected to one another to give related outputs. JP-A-61045986 discloses a high-precision electronic timepiece having two correcting means, a first one which controls the oscillator by a low-order digit bit data and a second one which controls a frequency dividing circuit by the remaining high order digit bit data. The present invention is described further, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a block diagram illustrating an electronic time piece embodying the present invention; Figure 2 is a timing chart for signals produced by a control signal generating circuit shown in Figure 1; Figure 3 is a circuit diagram illustrating a specific arrangement for a re-set signal generating circuit, a mode counter and a de-coder shown in Figure 1; Figure 4 is a circuit diagram illustrating a specific arrangement for an input/output control circuit shown in Figure 1; Figure 5 is a circuit diagram illustrating a specific arrangement for an EPROM and a data selector shown in Figure 1; Figure 6 is a circuit diagram illustrating a specific arrangement for each of a plurality of write enable blocks shown in Figure 5; Figure 7 is a circuit diagram illustrating a specific arrangement for each of a plurality of ROM blocks shown in Figure 5; Figure 8 is a timing chart for signals produced by a motor driving signal generating circuit shown in Figure 1; Figure 9 is a circuit diagram illustrating part of a specific arrangement for a latch circuit and the motor driving signal generating circuit shown in Figure 1; Figure 10 is a circuit diagram illustrating a specific arrangement for an output control circuit shown in Figure 1; Figure 11 is a timing chart for signals produced by an output de-coder shown in Figure 1; and Figure 12 is a circuit diagram illustrating a specific arrangement of a motor driver and a detection circuit shown in Figure 1. Figure 1 is a block diagram illustrating the circuitry within an analog electronic time piece, which includes an IC 100 having a battery 19 as a power supply, the battery 19 being connected to terminals VDD, VSS of the IC 100. The IC 100 includes components as follows: An oscillation circuit 1 produces an oscillating signal ⊘32K having an oscillation frequency of approximately 32,768 Hz, with a tuning fork crystal resonator 24 having secondary temperature characteristics as a source of oscillation. The tuning fork crystal resonator 24 is connected to terminals G, D of the IC 100. A frequency divider circuit 2 comprises a 1/1024 frequency divider 20 for dividing the frequency of the oscillating signal ⊘32K delivered by the oscillation circuit 1 to produce oscillating signals including a signal ⊘32 having a frequency of 32 Hz, a 1/32 frequency divider 21 for dividing the frequency of the oscillating signal ⊘32 to produce oscillating signals including a signal ⊘1 having a frequency of 1 Hz, a 1/10 frequency divider 22 for dividing the frequency of the oscillating signal ⊘1 to produce an oscillating signal ⊘1/10 having a frequency of 1/10th of a Hz, and a 1/32 frequency divider 23 for dividing the frequency of the oscillating signal ⊘1/10 to produce oscillating signals including a signal ⊘1/320 having a frequency of 1/320th of a Hz. A control signal generating circuit 3 produces from the output of the frequency divider circuit 2 combinations of signals having various frequencies, thereby forming control signals EK1, EK2, EK3, EK4 and ET as illustrated in the timing chart of Figure 2. A re-set signal generating circuit 4, shown in Figure 3 and connected to input terminals T1, RE of the IC 100, comprises N-channel type MOS transistors 401, 402 for pulling terminals T1, RE low, AND gates 403, 404, inverters 405, 406, an OR gate 407, and D-type flip-flops 408, 409, each having a respective re-set terminal R and being arranged, synchronously with the rise of a clock pulse signal applied to a respective terminal C, to transfer to a respective terminal Q a signal applied to a respective terminal D. The terminal T1, and terminals T2, T3 mentioned below are supplied with signals from an IC testing device (not shown). The re-set signal generating circuit 4 supplies an output signal RS, for use in re-setting the frequency divider circuit 2 to its initial state, until a pulse is applied to the terminal T1 after a passage of a period of time lasting 7.8 ms to 15.6 ms following closing of a re-set switch 25, which is inter-locked with a regulating lever for adjusting a time display gear train when the time displayed by the time piece is to be adjusted. The signal RS is also produced on the instant that a pulse is applied to the terminal T1 when the terminal RE is high (i.e. when the re-set switch 25 is closed). The re-set signal generating circuit 4 also supplies an output signal R E for use in re-setting a mode counter 5 when the terminal RE is low (i.e. when the re-set switch 25 is open). The mode counter is also shown in Figure 3 and comprises D-type flip-flops 501 to 504 having respective re-set terminals R and arranged to become active when the signal R E supplied by the re-set signal generating circuit 4 is low (i.e. when the re-set switch 25 is closed) to count the number of pulses supplied to the terminal T1. A de-coder 6, as shown in Figure 3, comprises AND gates 601 to 613, an inverter 614, and OR gates 615 to 621 arranged, in dependence upon the state of the mode counter 5 and the re-set signal RS, to supply the following signals: a mode signal MN representing the fact that the terminal RE is low; mode signals M0 to M11 representing the number of pulses supplied to the terminal T1 after the terminal RE becomes high; and signals M(N, 2, 8 - 11), M(0, 2, 3), M(4 - 11), M(2, 3) and M(3 - 7) produced by the OR gates 615 to 621 in response to the respective mode signals MN, and M1 to M11. In input/output control circuit 7, shown in Figure 4, is connected to input terminals T2, T3 of the IC 100 and the de-coder 6 and comprises N-channel type MOS transistors 701, 702 for pulling down terminal T1, T3, a clock inverter 703, an inverter 704, and AND gates 705 to 707. The input/output control circuit 7 is adapted to receive a data clock signal (TCLROM) for output to an EPROM data counter 9 from the terminal T2 when the signal M(3 - 7) is high; to apply to the terminal T3 a 16 Hz oscillating signal ⊘16 for use in monitoring pace; to receive for output a test clock signal (TCL2K) for use in providing acceleration equivalent to that of a 2,048 Hz oscillating signal ⊘2048 from the frequency divider circuit 2 from the terminal T3 when the signal M(2, 3) is high; and also to receive for output a test clock signal (TCL1/10) equivalent to the 1/10th Hz oscillating signal ⊘1/10 from the frequency divider circuit 2 from the terminal T3 when the signal M(4 - 11) is high. A 10 bit x 4 word EPROM 8 of an ultra-violet ray erase type, as shown in Figure 5, is connected to the de-coder 6 and comprises write enable blocks 801 to 804, NOR gates 805 to 808, ROM blocks 810 to 849, and N-channel type MOS transistors 850 to 859. With the application of approximately -30V at a VDD level to a terminal W of the IC 100, which terminal is connected to the EPROM 8, and when the mode signal M4 is high, reference data ℓ1 to ℓ10 supplied by the EPROM data counter 9 is written to the ROM blocks 810 to 819 as motor driving control data K1. With the application of approximately -30V at the VDD level to the terminal W when the mode signal M5 is high, the reference data ℓ1 to ℓ10 supplied by the EPROM data counter 9 is written to the ROM blocks 820 to 829 as a pace regulating signal K2. With the application of approximately -30V at the VDD level to the terminal W when the mode signal M6 is high, the reference data ℓ1 to ℓ10 supplied by the EPROM data counter 9 is written to the ROM blocks 830 to 839 as data K3 for use in adjusting the inclination of a temperature sensitive oscillator 16. With the application of approximately -30V at the VDD level to the terminal W when the mode signal M7 is high, the reference data ℓ1 to ℓ10 supplied by the EPROM data counter 9 is written to the ROM blocks 840 to 849 as data K4 for use in adjusting the off-setting of the temperature sensitive oscillator 16. When the mode signal M8 or the control signal EK1 becomes high, the data K1 is produced from the ROM blocks 810 to 819. When the mode signal M9 or the control signal EK2 becomes high, the data K2 is produced from the ROM blocks 820 to 829. When the mode signal M10 or the control signal EK3 becomes high, the data K3 is produced from the ROM blocks 830 to 839. When the mode signal M11 or the control signal EK4 becomes high, the data K4 is produced from the ROM blocks 840 to 849. A respective write enable block of the EPROM 8 is shown in greater detail in Figure 6 and is equipped with high voltage withstanding P-channel type MOS transistors 860, 861 and an ordinary P-channel type MOS transistor 862, arranged so as to transmit the high voltage applied to the terminal W to a terminal WR only when the signal applied to a terminal WE is high. A respective ROM block of the EPROM 8 is shown in greater detail in Figure 7 and is equipped with P-channel type MOS transistors 863, 864 for data writing and P-channel type MOS transistors 865, 866 for data calling. When a negative high voltage is applied to the terminal WR while the data signal applied to a terminal W D remains low, hot electrons are injected into the gate 867 of the transistors 863, 866 to turn on the transistor 866 so that the data signal "1" is written. A high data signal is supplied to a terminal OD only when the read signals supplied to a terminal RD becomes low while the data signal "1" remains stored. The EPROM data counter 9 for data writing comprises a 10 bit flip-flop and counts pulses of the data clock signal TCLROM received by a terminal C thereof from the input/output control circuit 7 and simultaneously produces the count value as the reference data ℓ1 to ℓ10. The counter 9 is re-set by the signal RS applied to a terminal R thereof. A data selector 10 is connected to the counter 9 and, as shown in Figure 5, comprises clock inverters 1000 to 1019 and an inverter 1021 arranged so as to select the output data from the EPROM data counter 9 when the mode signal M(N, 2, 8 - 11) is low, whereas it selects the output data K from the EPROM 8 when the mode signal M(N, 2, 8 - 11) is high. A latch circuit 11, comprising 10 D-type latches holds the data delivered by the data selector 10, when the control signal EK1 rises. A motor driving signal generating circuit 12 determines a hand operating period ⊘u, and generates for output a driving pulse P1 at the time of normal operation, a driving pulse P2 when rotation is undetected, an AC magnetic field detecting pulse SP1, and a pulse SP2 when rotation is detected. Figure 9 shows a specific arrangement of the latch circuit 11 and the motor driving signal generating circuit 12 for determining the hand operating period ⊘u and generating the driving pulse P1 at the time of normal operation. Figure 9 illustrates the D-type latches 1101 to 1104 of the circuit 11 and a D-type latch 1201 of the circuit 12, which each hold the data supplied to a terminal D M when a signal is applied to a terminal, and further illustrates components of the circuit 12 comprising AND gates 1202 to 1209, 1211 to 1218 and 1220, OR gates 1210 and 1219, a NOR gate 1221, and inverters 1222 to 1224. Master signals ⊘1KM, ⊘512M, ⊘256M, ⊘128M produced from the respective stages of the frequency divider circuit 2 are used to form hand operating periods ⊘u as shown in Table 1 below and to determine the pulse widths ta for the driving pulse P1 during normal operation as shown in Table 2 below, according to the contents d1, d2, d3, d4 of the data K1 stored in the EPROM 8. The motor driving signal generating circuit 12 also, though the components for this are not specifically shown, determines pulse width tb for the driving pulse P2 when rotation is undetected as shown in Table 3 below, pulse widths tc for the AC magnetic field detecting pulse SP1 as shown in Table 4 below, and pulse widths td for the pulse SP2 when rotation is detected as shown in Table 5 below, according to the contents d5, d6, d7, d8, d9, d10 of the data K1 stored in the EPROM 8. The AC magnetic field detecting pulse SP1 and the rotation detecting pulse SP2 are inhibited on the instant that a rotation detecting signal Dr and an AC magnetic field detecting signal Dm from the motor driver and detection circuit 15 both become high, whereupon the motor driver and detection circuit 15 is caused to stop its detecting operation until the next period. Moreover, the driving pulse P2 supplied during non-rotation is generated only when the rotation detecting signal Dr becomes high (i.e. when the rotation is undetected). An output control circuit 13, as shown in Figure 10, comprises inverters 1301 to 1303, AND gates 1304 to 1318, OR gates 1319 to 1321 and clocked inverters 1322 to 1327. When the mode signal M(0, 2, 3) is high, the output control circuit 13 produces the motor driving pulse P1 as a signal S01 for determining the output state of an output terminal 01 of the motor driver and detection circuit 15 and as a signal S02 for determining the output state of an output terminal 02 thereof. When the mode signal M1 is high, the output control circuit 13 produces a 16 Hz oscillating signal ⊘16 as the signal S01 and the output signal of the temperature sensitive oscillator 16 as the signal S02. When the mode signal M (4 - 11) is high, the output control circuit 13 produces the contents d1, d3, d5, d7, d9 of the data K1 as the signal S01 and the contents d2, d4, d6, d8, d10 of the data K1 as the signal S02, in dependence upon signals ⊘1/20, ⊘1/40, ⊘1/80 produced from the 1/32 frequency divider 23 of the frequency divider circuit 2. An output de-coder 14 de-codes the detection signals SP1, SP2 produced from the motor driving signal generating circuit 12 and delivers them to the motor driver and detection circuit 15 in the form of signals a1 to a6 as shown in the timing chart of Figure 11. The signals SP1, SP2 are given only when the mode signal M(0, 2, 3) is high. The motor driver and detection circuit 15, which is shown in Figure 12, comprises P-channel type MOS transistors 1501, 1503 and N-channel type MOS transistors 1502, 1504 constituting the motor driver part of the circuit 15, rotation detecting resistors 1505, 1506, P-channel type MOS transitors 1507, 1508 for switching the rotation detecting resistors, inverters 1509, 1510, whose outputs become high when a voltage delivered at the time when the AC magnetic field is detected exceeds 0.6V, comparators 1511, 1512, whose outputs become high when a voltage delivered at the time when rotation is detected exceeds the power supply voltage, and OR gates 1513, 1514. The motor driver and detection circuit 15 supplies to its output terminals 01, 02 motor driving pulses for driving a stepping motor included in a display mechanism 26 and further supplies the AC magnetic field detecting signal Dm and the rotation detecting signal Dr in response to detection of the voltage generated at the coil of the stepping motor for controlling supply of the AC magnetic field detecting pulse SP1 and the rotation detecting pulse SP2. The comparators 1511, 1512 are adapted to operate at the time when rotation is detected so that the power consumption is lowered. The temperature sensitive oscillator 16 produces an oscillating signal ⊘se having a frequency f expressed by f = A ϑ + B where ϑ is the temperature, A is the temperature coefficient, which is constant, and B is the value of f at 0°C. A temperature compensating circuit 17 produces fast/slow data dT for use in compensating the secondary temperature characteristics of the resonator 24 connected to the oscillating circuit 1. A description will be given below of a method for forming the fast/slow data dT. The oscillating frequency or pace y of the oscillation circuit 1 relative to the temperature ϑ is approximated by the following equation when the secondary temperature characteristics of the resonator 24 connected to the oscillation circuit 1 are not being compensated: y = -b.(ϑ - ϑt)² + a where a is apex pace, b is a secondary temperature coefficient, and ϑt is apex temperature. From equations (1) and (2) an equation for the pace y relative to the oscillating frequency f of the temperature sensitive oscillator 16, when the secondary temperature characteristics of the resonator 24 are not being compensated, can be derived as follows: y = - β.(f - ft)² + a where β = b/A², and ft is the oscillating frequency of the temperature sensitive oscillator 16 at the apex temperature ϑt. From equation (3), it may be noted that, by compensating the oscillating frequency of the temperature sensitive oscillator 16 by β.(f - ft)² onto the gaining side when it is f , i.e. the slow/fast data dt expressed by dt = [β.(f - ft)²/c] given the minimum resolution of a logical slow/fast circuit 18 is c , should only be supplied to the logical slow/fast circuit 18 to make flat the secondary temperature characteristics of the resonator 24. In this case, [ ] signify conversion to integers. The temperature compensating circuit 17 obtains the inclination adjusting value K3 set by β of equation (4) and the off-set adjusting value K4 set by ft of equation (4) from the EPROM 8 when the control signals EK3, EK4 respectively become high and carries out the inclination and off-set adjustment of the oscillating signal ⊘se produced from the temperature sensitive oscillator 16 using, e.g. the methods disclosed in Japanese Laid Open Patent Publications Nos. 223088/1983 and 47580/1986 in order to output the slow/fast data signal dT expressed by equation (4). The logical slow/fast circuit 18 obtains, from the EPROM 8, the pace adjusting data K2 for compensating the apex pace a of equation (2) when the control signal EK2 is high and sets the 1/1024 frequency divider 20 in the gaining or losing state accordingly and obtains, from the temperature compensating circuit 17, the temperature compensating slow/fast data dT when the control signal dt is high to set the 1/1024 frequency divider 20 in the gaining state determined by dt . The operation of the circuitry shown in Figure 1 will now be described. The IC for the analog electronic time piece embodying the present invention is so arranged that the control of its mode depends on the state of the re-set switch 25 (terminal RE) and the number of pulses applied to the terminal T1 after the re-set switch 25 is closed. While the re-set switch 25 remains open, a normal mode is established and the mode signals MN, M(N, 2, 8-11), M(0, 2, 3) are high. The input/output control circuit 7 produces the 16 Hz oscillating signal ⊘16 to monitor the pace at the terminal T3 and the data selector 10 selects the data stored in the EPROM 8, while the output control circuit 13 selects and delivers the motor driving pulse. When the signal EK1 is produced from the control signal generating circuit 3 in this condition, the motor driving signal control data K1 is produced from the EPROM 8. Simultaneously, the latch circuit 11 receives the value of K1 and a motor driving signal generating circuit 12 determines the hand operating period and produces the motor driving pulses P1 and P2 and the detecting pulses SP1 and SP2 having pulse widths in accordance with the data K1. When the signal EK2 is produced from the control signal generating circuit 3, the pace adjusting data K2 is produced from the EPROM 8 and simultaneously the logical slow/fast circuit 18 obtains the value of K2 to flexibly set the 1/1024 frequency divider 20 in the gaining or losing state determined by K2. When the signals EK3, EK4 are produced from the control signal generating circuit 3, the EPROM 8 outputs the inclination adjusting data K3 and the off-set adjusting data K4 and the temperature compensating circuit 17 obtains the values of K3, K4 and outputs the temperature compensating slow/fast data dT for making the inclination and off-set adjustment. When the control signal generating circuit 3 outputs the signal ET, the logical slow/fast circuit 18 obtains the temperature compensating slow/fast data dT produced by the temperature compensating circuit 17 and sets the 1/1024 frequency divider 20 in the gaining state determined by dT to compensate for the secondary temperature characteristics of the resonator 24. When the re-set switch 25 is closed, the re-set mode is maintained until a pulse is applied to the terminal T1. Then, the signal R E becomes low and the mode counter 5 becomes active, whereas the re-set signal RS becomes high so that the frequency divider circuit 2 is re-set to its initial state. When pulses are applied to the terminal T1 one after another while the re-set switch 25 remains closed, the contents of the mode counter 5 are changed stepwise and the mode is also changed such that the test mode 1 is followed by the test mode 2, the test mode 3, etc. The re-set signal RS becomes high each time that the test mode changes, simultaneously re-setting the frequency divider circuit 2 and the EPROM data counter 9 to the initial state. Consequently, it becomes possible to confirm the function of the time piece, to write data to the EPROM and to confirm the data without restoring the re-set mode by re-closing the switch 25 each time. In the test mode 1, the re-set signal RS is initially low and the frequency divider circuit 2 operates. Subsequently, the mode signal M1 becomes high and the output control circuit 13 selects the 16 Hz oscillating signal ⊘16 as the signal S01 and the output signal ⊘se of the temperature sensitive oscillator 16 as the signal S02. The signals ⊘16, ⊘se are thus applied to the terminals 01, 02 respectively. The function of the logical slow/fast circuit 18 is suspended in this mode and, by monitoring the signal ⊘16, the pace of the time piece at the time the secondary temperature characteristics of the resonator 24 are not being compensated can be measured. Consequently, the constants β and ft of equation (3) can be computed by measuring the time piece pace y and the temperature sensitive oscillation frequency f at three temperature points using the test mode 1. The test mode 2 is a mode in which testing is made to examine whether the IC is functioning properly according to the data K1 to K4 stored in the EPROM 8. The mode signals M(2, 3), M(0, 2, 3), M(N, 2, 8 - 11) become high and the terminal T3 connected to the input/output control circuit 7 functions to receive the accelerating test clock signal TCL2K equivalent to the 2,048 Hz oscillating signal ⊘2K from the frequency divider circuit 2. The data selector 10 selects the data K for output from the EPROM 8, whereas the output control circuit 13 selects the motor driving pulse P1 for supply to the terminals 01, 02. As the mode signals M(2, 3), M(3 - 7), M(0, 2, 3) become high in the test mode 3, the terminal T2 of the input/output control circuit 7 is caused to receive the data clock signal TCLROM for supply to the EPROM data counter 9. Apart from the selection of the data from the EPROM data counter 9 by the data selector 10, the test mode 3 is similar in function to the test mode 2. The data selector 10 is capable of selecting the data from the EPROM data counter 9 separately from the counter 9 counting the data clock signal TCLROM, and so it can voluntarily change its output at the time when the control signals EK1 to EK4 are produced. The function of the IC can thus be confirmed without writing the data K1 to K4 to the EPROM 8. In the test modes 4 to 7, the data K1 to K4 is written to the EPROM 8. The mode signals M(3 - 7), M(4-11) become high, whereas the mode signal M(N, 2, 8 - 11) becomes low. Accordingly, the terminal T2 of the input/ output control circuit 7 functions to receive the data clock signal TCLROM for supply to the EPROM data counter 9, whereas the terminal T3 functions to receive the test clock signal TCL1/10 equivalent to the 1/10 Hz signal ⊘1/10 of the frequency divider circuit 2. The output control circuit 13 selects the output data ℓ1 to ℓ10 (the reference data produced from the EPROM data counter 9) in accordance with the contents of the 1/32 frequency divider 23 (the number of inputs of the test clock signal TCL1/10) and causes the terminals 01, 02 to receive such output data. Consequently, the data that is to be written to the EPROM 8 can be confirmed at the terminals 01, 02 before being written. In the test modes 8 to 11, the data K1 to K4 written to the EPROM 8 is confirmed. Since the mode signals M(4 - 11), M(N, 2, 8 - 11) become high, the terminal T3 of the input/output control circuit 7 functions to receive the test clock signal TCL1/10 equivalent to the 1/10 Hz signal ⊘1/10 of the frequency divider circuit 2, and the output control circuit 13 selects the output data d1 to d10 (the data from the EPROM 8) in accordance with the contents of the 1/32 frequency divider 23 (the number of inputs of the test clock signal TCL1/10) and causes the terminals 01, 02 to receive such output data. As described, the IC for an analog electronic time piece embodying the present invention can be arranged in optimum manner according to the type of time piece by controlling the hand operating period of the stepping motor, the driving pulse width, and the detecting pulse width using the motor driving signal control data K1 written to the EPROM 8. This means that a single IC is capable of controlling several kinds of time piece. Moreover, the IC embodying the present invention is so constructed that, by arranging the storage of the motor driving signal control data K1 in parallel with the storage of the pace adjusting data K2, the inclination adjusting data K3 for the temperature compensation and the off-set adjusting data K4, the wiring can be minimised and a single output line can be placed for common use. The mode counter 5 and the de-coder 6 permit each item of data to be written and confirmed in different modes. The terminal T1, T3, 01, 02, W are provided for common use in the respective modes. These terminals, other than the terminal W, are used simultaneously with the input/output terminals having other functions, which contributes to a saving in the number of pads. The provision of the aforesaid features also helps to minimise increases in IC size. In the test mode 3, the functioning of the IC is confirmed by changing the reference data held by the EPROM data counter 9 in accordance with the test clock signal TCLROM from the terminal T2 and selecting such data for output at the timing of the control signals EK1 to EK4, instead of using the control data K1 to K4 produced from the EPROM 8. Thus, correct functioning of the IC can be confirmed without erasing the data in the EPROM 8 by the irradiation of ultra-violet rays. The reference data ℓ1 to ℓ10 can also be confirmed by monitoring the terminals 01, 02 while supplying the test clock signal TCL1/10 from the terminal T3 in each data writing mode when the control data K1 to K4 is written to the EPROM 8. This prevents writing in errors that may occur because the data is inverted as a result of noise. Consequently, the function of the IC as well as of the time piece itself can be examined by checking the reference data held by the EPROM data counter 9 by means of the reference data output terminals when the control data K is written to the EPROM. Writing in errors in the EPROM can also be prevented by re-setting the reference data when a mis-carriage occurs because of noise. Even in the case of high performance electronic time pieces, the production yield can thus be improved by far. The functioning of an IC for an electronic time piece embodying the present invention can thus be tested by changing the reference data of the EPROM data counter 9 in the test mode 3 without re-writing the control data stored in the EPROM 8. The test time is thus shortened and this makes the IC less expensive. Since every combination of EPROM can be tested, moreover, the quality of the IC is easily improved. The above described effect is particularly beneficial since the erase time is especially long given that the EPROM 8 is of an ultra-violet ray erase type in the case of the described embodiment. The EPROM can therefore be employed in the process of manufacturing ICs for electronic time pieces in general, permitting a further reduction in price. The motor driving signal period and pulse width can freely be selected using the value of the control data K1 stored in the EPROM 8 only by slightly increasing the size of the pad for use in writing the data to the EPROM in the case of the IC for an electronic time piece embodying the present invention. Accordingly, the IC according to the present invention can be used for many kinds of analog electronic time piece. Moreover, ICs can be made more inexpensively as an increased number of them can be produced in a given time through the use of common jigs and testing equipment. The IC according to the present invention is capable of being adapted to almost every motor drive specification and this also contributes to a reduction in time and expense required for developing and designing analog electronic time pieces. Only one kind of IC thus needs to be produced, so that the control expenses therefore can be reduced by employing jigs and testing equipment for common use. The use of such an IC allows an optimum drive specification to be maintained even though there exist variations of the motor characteristics thereby ensuring the production of high quality analog electronic time pieces. The above described effects are further enhanced by arranging the memory blocks for storing the control data K1 in parallel to the memory blocks for storing the control data K2, K3 and K4 for use in controlling the other functions which allows a common data line to be employed. In addition, the control data K1, K2 etc. is written in different individual modes with the terminals needed for the writing being put to common use. The IC is thus hardly increased in size since not only the wiring area but also the number of pads can be reduced.

Claims: An integrated circuit for an electronic timepiece, comprising a non-volatile semiconductor memory (8) for storing control data for use in controlling a plurality of functions of the timepiece, reference data holding means (9) for holding reference data for use in controlling the functions of the timepiece, selecting means (10) for selecting control data from the storing memory (8) for normal operation of the timepiece or reference data from the holding means (9) for testing purposes, means (11 to 15) for generating an output based upon the data received from the selecting means (10) and test clock signal generating means (7) for generating test clock signals (TCLROM) to change the output of the holding means (9) and the reference data selected therefrom, characterised in that the storing memory (8) is of the EPROM type, the holding means (9) is of the EPROM type, and there is provided a test mode of the integrated circuit in which the functioning of the integrated circuit is confirmed by changing the reference data held by the holding means (9) in accordance with the test clock signals (TCLROM) from a terminal (T2) of the test clock signals (TCLROM) generating means (7) and selecting such data for output at the timing of the control data (EK1 - EK4) instead of using the control data (K1 - K4) produced from the storing memory (8), so that correct functioning of the integrated circuit can be confirmed without erasing the data in the storing memory (8). An integrated circuit as claimed in claim 1 characterised in that the storing memory (8) and the holding means (9) are arranged to co-operate with the test clock signals (TCLROM) generating means (7) so that both the reference data and the control data are derived from the test clock signals (TCLROM). An integrated circuit as claimed in claim 2, characterised in that the holding means (9) is arranged to supply the reference data for writing to the storing memory (8) as the control data. An integrated circuit as claimed in any preceding claim, characterised by mode control means (4 to 7) arranged to co-operate with the selecting means (10) to determine the mode of operation of the timepiece. An integrated circuit as claimed in claim 4, characterised in that the mode control means (4 to 7) is arranged to determine whether the timepiece operates in a first test mode, in which the timepiece is made to function in accordance with the control data, or in a second test mode, in which the timepiece is made to function in accordance with the reference data. An integrated circuit as claimed in claim 4 or 5, characterised in that the mode control means (4 to 7) is arranged to determine a normal mode of operation for the timepiece. An integrated circuit as claimed in any preceding claim, characterised in that the control data comprises a first set of data for providing drive information for the timepiece, and at least one further set of data for controlling at least one further function of the timepiece. An integrated circuit as claimed in claim 7, characterised in that the storing memory (8) comprises a first set of storage blocks (810 to 819) for storing the first set of data, and at least one further set of storage blocks (820 to 829; 830 to 839; 840 to 849) arranged in parallel with the first set of storage blocks (810 to 819) for storing at least one further set of control data. An integrated circuit as claimed in claim 7 or 8, when appendant to claim 4, 5 or 6, characterised in that the mode control means (4 to 7) is arranged to determine modes of operation according to each respective set of the control data. An integrated circuit as claimed in any preceding claim, characterised in that the storing memory (8) is of the ultra-violet erase type. An electronic timepiece incorporating an integrated circuit as claimed in any preceding claim.

Inventors: MORIYA TATSUO, MORIYA, TATSUO
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1989
Main classification: G04D7
IPC codes: G04G1, G04D7