Method for making a contact on a semiconductor device and said device

Abstract: The present invention provides a semiconductor device, comprising a substrate (1), a first insulation layer (5) formed on the substrate (1), a first wiring layer (6) formed on the first insulation layer (5), a second insulation layer (7) formed on the first wiring layer and having a contact hole (8), and a third insulation layer (10) formed on the second insulation layer (7), said third insulation layer (10) being in contact with the first wiring layer (6) via the contact hole (8).

Description: The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a method of connecting multi-layered wiring layers. In a semiconductor device using multi-wiring layers, connection of wiring layers is performed in general by making contact holes in an interlayer insulation layer. Figs. 3A and 3B collectively show an example of the conventional contact structure of a MOS type semiconductor device for connecting a first wiring layer formed of polycrystalline silicon, said first wiring layer providing a gate electrode, to a second wiring layer formed of a metal. As seen from Fig. 3A, which is a cross sectional view along the channel region of the MOS transistor, a field oxide layer 2 is selectively formed on the surface of a p-type silicon substrate 1 such that the element region of the MOS transistor is surrounded by the field oxide layer 2. As seen from Fig. 3B, which is a plan view, N⁺-type source and drain regions 3 and 4 are formed apart from each other within the element region with the channel region positioned therebetween. A gate electrode 6 formed of polycrystalline silicon is formed above the channel region with a gate oxide layer 5 interposed therebetween. The gate electrode 6 extends to cover partly the field oxide layer 2 and is covered with an interlayer insulation layer 7 formed of silicon dioxide by CVD. Further, an aluminum wiring layer is formed on the interlayer insulation layer 7. A contact hole 8 is formed in the interlayer insulation layer 7 for bringing the aluminum wiring layer into contact with the gate electrode 6. A reactive ion etching (RIE) is employed for forming the contact hole 8 in accordance with miniaturization of the element. In this case, it is necessary to provide an allowance A in the contact portion of the gate electrode 6 as shown in Fig. 3B in view of the deviation in the mask alignment in the step of PEP (photoetching process) for forming the contact hole. Naturally, the allowance A inhibits miniaturization of the semiconductor device. Where the allowance A is not provided, it is possible for the contact hole 8 to extend beyond the gate electrode 6 because of the deviation in the mask alignment, as shown in Fig. 4. In this case, the field oxide layer 2 is also etched in the step of RIE, with the result that an aluminum wiring 11 is brought into electric contact with the silicon substrate 1. In other words, short-circuiting takes place. EP-A-0 176 010 describes a procedure for improving the continuity of wiring layers when misalignment and overetching occurs therebetween as well as for limiting the contact width of a wiring layer at contact locations to an underlying wiring layer. Due to masking misalignment a part of the insulating layer adjacent to a wiring layer may be etched. An additional insulating layer is deposited over the contact location and anisotropically etched leaving a narrowed exposed contact area. The Article in IBM Technical Disclosure Bulletin, Vol. 25, No. 9, February 1983, pages 4768 - 4772 entitled "Method to Realise Submicrometer-wide Images" by C.G. Jambotkar, an insulating layer is deposited in a recess in a semiconductor substrate. Using anisotropic etching, the semiconductor substrate is exposed at the base of the recess leaving insulating layers on the side walls. An object of the present invention is to provide a semiconductor device having multi-wiring layers formed on a semiconductor substrate, which permits miniaturizing the device and, thus, improving the degree of integration without bringing about short-circuiting between the wiring layers and the semiconductor substrate. According to the present invention, there is provided a semiconductor device according to Claim 1 and a method of manufacturing a semiconductor device according to Claim 5. An allowance is certainly provided in the step of forming the contact hole in view of the deviation in the mask alignment. In the present invention, however, it is possible to minimize the allowance, leading to a miniaturization and an improved degree of integration of the device. To be more specific, deviation of the contact hole may possibly cause the field oxide layer to be etched to form a small groove in the field oxide layer such that the groove extends to reach the substrate. In the present invention, however, the groove, even if formed, is filled with the third insulation layer. It follows that a second wiring layer filling the contact hole is prevented from contacting the substrate, even if the contact hole is positioned beyond the edge of the first wiring layer. The particular construction permits minimizing the allowance of the contact hole, leading to miniaturization and improved integration degree of the semiconductor device. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1C are cross sectional views collectively showing the process of manufacturing a semiconductor device according to one embodiment of the present invention; Fig. 2 is a plan view showing the gist portion of the device shown in Fig. 1; Fig. 3A is a cross sectional view showing a semiconductor device produced by a conventional method; Fig. 3B is a plan view showing a semiconductor device produced by a conventional method; and Fig. 4 is a cross sectional view showing a defect accompanying a semiconductor device produced by a conventional method. A semiconductor device according to one embodiment of the present invention is manufactured as shown in Figs. 1A to 1C. The device shown in these drawings corresponds to the conventional device shown in Fig. 3 and, thus, the reference numerals common with these drawings denote the same members of the device. As shown in Fig. 1A, a field oxide layer 2 is formed on a P-type silicon substrate 1. Then, an N⁺-type source region 3, an N⁺-type drain region 4, and a gate oxide layer 5 are formed as shown in Fig. 2, which is a plan view, followed by forming a gate electrode 6 formed of polycrystalline silicon layer doped with an impurity. Further, an interlayer insulation layer 7 is deposited on the gate electrode 6, followed by forming a contact hole 8 in the insulation layer 7 by an anisotropic etching using a resist pattern. In forming the contact hole 8, an allowance A2 in the width of the contact portion with the gate electrode 6 is set small for miniaturizing the semiconductor device. Thus, if a deviation takes place in the mask alignment, the field insulation layer 2 is also etched near the periphery of the gate electrode 6 so as to form a groove 9 extending downward to reach the substrate 1. In the next step, an insulation layer 10, e.g., a silicon nitride layer or a silicon dioxide layer, is deposited on the entire surface by means of low pressure CVD, as shown in Fig. 1B. If the thickness of the insulation layer 10 is at least half the width of the groove 9, the groove 9 is completely filled with the insulation layer 10. The insulation layer 10 is then removed by an isotropic etching, as shown in Fig. 1C. If the depth of the groove 9 is markedly larger than the width thereof, the insulation layer 10 is left unremoved selectively within the groove 9 in this etching step. Finally, an aluminum layer is formed on the entire surface, followed by patterning the aluminum layer so as to form an aluminum wiring 11. In the embodiment described above, the groove 9 is filled with the insulation layer 10, e.g., a silicon nitride layer, with the result that the short-circuit between the aluminum wiring 11 and the silicon substrate 1 can be prevented. In addition, the allowance A2 in the contact portion of the gate wiring 6 can be diminished, leading to miniaturization and high integration degree of the semiconductor device. The technical idea of the present invention can be applied not only to the semiconductor device described above but also to any type of devices requiring miniaturization and also requiring a measure for preventing short-circuit between the conductor within the contact hole and the semiconductor substrate. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor device, comprising: a semiconductor substrate (1); a first insulating layer (2) formed on the substrate (1); a first wiring layer (6) formed on the first insulating layer (2); a second insulating layer (7) formed on the first wiring layer (6) and having a contact hole (8) the bottom of which is defined by the first wiring layer (6); a second wiring layer (11) filling the contact hole (8) and connected to the first wiring layer (6) via the contact hole (8); characterized by an edge of the contact hole (8) being located at a distance beyond an edge of said first wiring layer (6) due to mask misalignment; an insulating material (10), filling that hole portion (9) formed due to said mask misalignment directly under the bottom of the contact hole (8) and adjacent to the first wiring layer (6), the hole portion (9) passing through the first insulating layer (2) and reaching the substrate (1), for preventing the first and second wiring layers (6, 11) from contacting the substrate (1), wherein the insulating material (10) only extends from the substrate (1) to the bottom of the contact hole (8). The semiconductor device according to claim 1, characterised in that the first insulating layer (2) is a field oxide layer interposed between the substrate (1) and the second insulation layer (7). The semiconductor device according to claim 1, characterized in that the substrate (1) is of P-type. The semiconductor device according to claim 1, characterized in that the insulating material (10) is silicon nitride. A method of manufacturing a semiconductor device, comprising a first step of forming a first insulation layer (2) on a substrate (1); a second step of forming a first wiring layer (6) on the first insulation layer (2); a third step of forming a second insulation layer (7) on the first wiring layer (6); a fourth step of forming a contact hole (8) in the second insulation layer (7) above the first wiring layer (6) ; a fifth step of forming a third insulation layer (10) on the entire surface of the substrate (1) including the contact hole (8); a sixth step of selectively removing the third insulation layer (10) by isotropic etching to leave a portion of the third insulation layer in any hole portion (9) formed due to mask misalignment in the first insulation layer (2) adjacent to the first wiring layer (6) and extending to said semiconductor substrate (1); and a seventh step of forming a second wiring layer (11) to fill said contact hole (8), said portion of the third insulation layer (10) preventing the second wiring layer (11) from contacting the semiconductor substrate (1). The method according to claim 5, wherein the first insulation layer (2) is a field oxide layer interposed between the substrate (1) and the second insulation layer (7). The method according to claim 5, wherein the substrate (1) is of P-type. The method according to claim 5, wherein the first wiring layer (6) is formed by anisotropic etching using a resist pattern. The method according to claim 5, wherein the contact hole (8) is formed by anisotropic etching using a resist pattern. The method according to claim 5, wherein the third insulation layer (10) is a silicon nitride layer formed by low pressure CVD. The method according to claim 5, wherein the third insulation layer (10) has a thickness not smaller than half the width of any said hole portion (9).

Inventors: HIGUCHI TAKAYOSHI C O INTELL P, HIGUCHI, TAKAYOSHI, C/O INTELL. PROP. DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H01L21
IPC codes: H01L21, H01L29