Semiconductor memory device provided with an improved common data line precharge circuit

Abstract: A semiconductor memory device provided with an improved arrangement for precharging a pair of common data lines which are selectively coupled to a pair of bit lines is disclosed. The memory device comprises a plurality of pairs of bit lines, a plurality of sense amplifiers provided for the pairs of bit lines, each of the sense amplifiers amplifying each pair of bit lines to two different potentials, a pair of common data lines, a column selection circuit for electrically connecting one pair of bit lines to the pair of common data lines, a bit line precharge circuit for precharging each pair of bit lines to an intermediate potential of the above two different potentials, and a data line precharge circuit for precharging the pair of common data lines to the intermediate potential.

Description: Field of the Invention: The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device in which a plurality of bit lines and a pair of common data lines are precharged prior to each access operation. Description of the Related Arts: Semiconductor memory devices such as dynamic type memory devices employing the so-called one-transistor memory cells have been widely used in various fields as large capacity memories. A conventional memory device is constructed as follows. A plurality of memory cells are arranged in a matrix form of rows and columns and, a plurality of word lines and a plurality of pairs of bit lines are arranged in the rows and columns, respectively. A plurality of sense amplifiers are provided for the pairs of bit lines, respectively. For performing a column selection, a plurality of transfer gate transistors are coupled between the pairs of bit lines and a pair of common data lines. In operation, the pairs of bit lines and the pair of common data lines are precharged prior to each access operation. After an access operation is initiated, one of word lines is selected and small potential difference is produced between each pair of bit lines. Then, the sense amplifiers are enabled to amplify small potential differences in the respective pairs of bit lines gradually, while one pair of the transfer gate transistors are selectively rendered conductive. As a result, one pair of bit lines are electrically connected to the pair of common data lines, and a read-out signal at the selected pair of bit lines is transmitted to the pair of common data lines. Since each pair of bit lines have been precharged approximately at an intermediate voltage of 1/2 Vcc (Vcc: a value of power voltage), the levels of each pair of bit lines are near the intermediate voltage with a small signal difference before completion of amplification operation by the sense amplifiers. While the pair of common data lines are precharged to the power voltage Vcc. Therefore, at the time when the selected pair of bit lines are electrically connected to the pair common data lines, large amount of electric charges flow into the selected pair of bit lines from the pair of common data lines to affect the potentials of the selected pair of bit lines. Particularly, in the case where the selected pair of transfer gate transistors have different values of effective conductive-resistances, the electrical charges at the pair of common data lines are flown unequally into the selected pair of bit lines. In this case, if one of the selected pair of bit lines assumes a relatively high potential and connected to one transfer gate transistor having a relatively large conductive-resistance while the other bit line assumes a relatively low potential and connected to the other transfer gate transistor having a relatively small conductive-resistance, the above one bit line and the other bit line would erroneously take low and high levels, respectively by electric charges flown unequally thereinto if the selected pair of transfer gate transistors are rendered conductive before the completion of the amplifying operation by the sense amplifiers. Thus, the disadvantage of the conventional memory device is that data stored in the memory cell may be destroyed upon a reading operation. An example of an arrangement, in which the data lines are precharged to Vcc/2, is shown in EP-A-0 261 609. SUMMARY OF THE PRESENT INVENTION It is an object of the present invention to provide a semiconductor memory device which has an improved precharge arrangement. A semiconductor memory device according to the present invention is specified in Claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with rhe accompanying drawings, wherein: Fig. 1 is a schematic block diagram showing a semiconductor memory device in the prior art; Fig. 2 is a timing diagram showing a normal operation of the memory device of Fig. 1; Fig. 3 is a timing diagram showing an erroneous operation of the memory device of Fig. 1; Fig. 4 is a schematic block diagram of the memory device according to one embodiment of the present invention; Fig. 5 is a timing diagram showing an operation of the memory device of Fig. 4; Fig. 6 is a schematic block diagram of a memory device according to another embodiment of the present invention; and Fig. 7 is a timing diagram showing an operation of the memory device of Fig. 6. DETAILED DESCRIPTION OF THE INVENTION Description of the Prior Art: With reference to Fig. 1, a semiconductor memory device in the prior art will be explained. As shown in Fig. 1, m word lines WL1 - WLm and n pairs of bit lines BL1, BL1 -BLn, BLn are arranged in the form of a matrix of rows and columns. Dynamic type memory cells CL are disposed at the intersections of the word lines and the bit lines in a known way. Bit line balance-precharge circuits BP1 - BPn are disposed at one ends of the respective pairs of the bit lines BL1, BL1 - BLn, BLn , whereas transfer switches YSW1 - YSWn connected to a pair of common data lines DB, DB are disposed at the other ends of the respective pairs of bit lines, as illustrated. Each of the transfer switches YSW1 - YSWn includes N-channel MOS transistors Q₈ and Q₉ and is capable of switching operation for making and breaking the connection electrically between each of the sense amplifiers SA1 - SAn and the data lines in accordance with column selection signals Y₁ - Y n from a column decoder 12. Each of the differential sense amplifiers SA1 - SAn includes P-channel transistors Q₄ and Q₅ and N-channel transistors Q₆ and Q₇ and, is driven by a pair of sense control signals SAP, SAN . The data lines DB, DB are precharged by a balance-precharge circuit 10 having P-channel MOS transistors Q₂₁ and Q₂₂ which are turned on by a low level of a precharge signal  P so that both DB and DB are precharged at a power voltage Vcc. A voltage line HVC provided with a precharge potential of 1/2 Vcc is applied to each of the bit line balance-precharge circuits BP1 - BPn. A row decoder 11 selects one of the word lines WL1 - WLn, and an input/output circuit 13 connected to an I/O terminal I/O is coupled to the pair of data lines DB and DB in a known way. Referring to Fig. 2, the operation of the memory of Fig. 1 will be explained. During a precharge period T P prior to a time point t₁, the precharge signal  P and  P are at a high level and a low level, respectively. Therefore, the transistors Q₁₀ - Q₁₂ of the respective precharge circuits BP1 - BPn are all conductive to precharge the respective pairs of bit lines to the 1/2 Vcc level in response to the high level of  P , while the transistors Q₂₁ and Q₂₂ of the precharge circuit 10 are conductive in response to the low level of  P thereby to precharge the pair of data lines DB and DB at the Vcc level. Then, at t₁, an active period Ta is initiated, and the precharge circuits BP1 - BPn and 10 are disenabled. At a time point t₂, one of the word lines, e.g. WL1 is selected to be a high level. In this case, the memory cell CLs coupled to the selected word line WL1 and the bit line BL1 is selected. Assuming that the memory cell CLs stores "1" level at its capacitor CM coupled between a cell transistor Q M and a fixed potential V f , the bit line BL1 is raised slightly in potential while the bit line BL₁ remains at the precharge level (1/2 Vcc). When the signal SAP becomes high simultaneously with the signal line SAN being set low at a time point t₃, the sense amplifiers SA1 - SAn amplify the potential difference of the respective bit lines. When the column selection signal Y1 becomes high at a time point t₄, the bit lines BL1, BL1 and the data lines DB, DB are electrically connected through YSW1. Although the potential of the bit lines BL1 rises temporarily because of the injection of charge from the data line DB , the potential together with that of the data line DB is gradually set to the ground level (GND). Although the potential of the data line DB becomes lower in level than Vcc when electrically connected to the bit line BL1, the electrical connection of the bit line BL1 with the data line DB accelerates a rise in its potential. When the potential level of the bit line BL1 becomes lower than Vcc by the threshold voltage VT of the N-channel MOS transistor Q₈, the transistor Q₈ is turned off and the potential level of the data line DB is stopped from decreasing. The data (charge) stored in the memory cell CLs through a series of the aforementioned operations is amplified by the sense amplifier SA1 and supplied to the data lines DB, DB . Then, at a time point t₅, the active period is terminated. In the aforementioned conventional semiconductor memory device, the potential of the data lines is precharged at Vcc. The potential of the column selection signal Y1 is set high while the difference in potential between the bit lines BL1 and BL1 remains small. While storay resistors R1 and R2 are inevitably provided to the current paths of the transistors Q₈ and Q₉. If the resistance of the resistor R1 becomes abnormally higher by approximately 50% than the on-resistance of the transistor Q₈ due to deviations or deformities of the production system. While the resistance of R2 is normal (R1 > R2), the electrical connection of the bit line BL1 with the data line DB is apparently weakened as compared to that through R2, a rise in the potential of the bit line BL1 relies on only the amplification capability of the sense amplifier SA1. Regarding the bit line BL1 , its electrical connection with the data line DB results in a potential rise. If the potential of the column selection signal Y1 is set high while the difference in potential between the bit lines BL1 and BL1 is insufficiently great, the potential is inverted at the time point t₄ as shown in Fig. 3 and the bit line BL1 becomes high, whereas the bit line BL1 becomes low. The disadvantage is that the data stored in the memory cell may be destroyed. Description of the Embodiments: With reference to Fig. 4, the semiconductor memory device according to one preferred embodiment will be explained. In the following drawings, the elements or portions corresponding to those in Fig. 1 are denoted by the same or similar references, and detailed explanation thereon would be omitted. The memory device of this embodiment is basically obtained by employing a data line precharge circuit 10′ in place of the precharge circuit 10 of Fig. 1. The precharge circuit 10′ includes N-channel transistors Q₃₁ - Q₃₃ and operatively charges the pair of data lines DB and DB to the 1/2 Vcc level supplied to the line HVC in response to the high level of  P . A control circuit 14 includes P-channel MOS transistor Q₁₅ and N-channel MOS transistors Q₁₆ - Q₁₉. The control circuit 14 generates the 1/2 Vcc level of SAP and SAN in response to the high level of  P through the transistors Q₁₆ - Q₁₈ prior to a time point t₃ and, the high level Vcc of SAP and the low level(GND) of SAN in response to the high level of  S and the low level of  S in the active period after a time point t₃. Namely, the control circuit 14 generates the 1/2 Vcc level of SAP and SAN for precharging the respective nodes of the sense amplifiers SA1 - SAN in the precharge period and the Vcc level of SAN and the ground level of SAP for enabling the sense amplifiers in the active period. As will readily be understood from Figs. 4 and 5, the potential of the data lines is balance-precharged at 1/2 Vcc with the potential of  P kept high, whereas the bit line is precharged also at 1/2 Vcc with the potential of the signal line  P kept high. The potential of the signal  P is, set low before the potential of the word line WL1 becomes high at t₂. After t₃, the control circuit 14 generates the Vcc level of SAP and the GND level of SAN . As a result, the sense amplifiers SA1 - SAN are supplied with the Vcc level of SAN and the GND level of SAP as operating voltages so that one bit line having a high level and the other bit line having low level in each bit line pair are amplified to the Vcc level and the GND level gradually. The similar operation as that of the conventional example is performed until the potential of the column selection signal Y1 becomes high at t₄. When the potential of the column selection signal Y1 becomes high, the pair of data lines DB, DB are electrically connected to the respective bit lines BL1 and BL1 at t₄. The bit line BL1 temperarily falls to the potential of the data line DB, whereas the bit line BL1 temporarily rises to the potential of the data line DB , at t₄. There is also produced the difference in potential between the pair of data lines DB, DB because the potential difference between the bit lines BL1, BL1 tends to grow because of the amplification capability of the sense amplifier SA1. When the potential of the column selection signal Y1 becomes high while the difference in potential between the bit lines is not sufficiently great with the resistance of the resistor R1 being high, the potential of the bit line BL1 is kept from decreasing to the value shown in Fig. 5 because of the action of the resistor R1. Although the potential of the bit line BL1 is temporarily caused to rise up to that of I/O line likewise as shown in Fig. 5, it remains lower than 1/2 Vcc. As a result, the potential of the bit line BL1 becomes higher than that of the bit line BL1 , so that the data stored in the memory cell CLS is never destroyed. Although a description has been made of the bit line BL1, the same process is applicable to the other pairs of bit lines. With reference to Figs. 6 and 7, the semiconductor memory device according to another embodiment of the present invention will be explained. This embodiment is obtained by a precharge circuit 10″ composed of an N-channel transistor Q₃₃ in place of the circuit 10′ of Fig. 4 and further provided with a data amplifier BA having a CMOS type flip-flop made of P-channel transistors Q₄₁, Q₄₂ and N-channel transistors Q₄₃ and Q₄₄, and a P-channel enable transistor Q₄₅ and an N-channel enable transistor Q₄₆. The transistor Q₃₃ shortcircuits between the pair of data lines DB, DB in response to the high level of  P in the precharge period. Since the pair of data lines DB and DB have almost the same capacitance and are amplified into the Vcc level and the ground level by the amplifier BA enabled in response to the high level of  B and the low level of  B at a time point t₅ in Fig. 7 in the active period, the pair of data lines DB and DB are set approximately at the 1/2 Vcc level by simply shortcircuiting them by the circuit 10″. Also, in the respective bit line precharge circuits BP1 - BPn, the transistors Q₁₀ and Q₁₁ may be deleted by the same reason. As set forth above, the data stored in the memory cell can effectively be fed to the data lines by precharging the cell data lines to the same 1/2 Vcc level as that of the bit lines without being destroyed even though the effective resistance of the transfer switches for electrically connecting the data lines and bit lines become abnormally high because of variations in quality or deformities of the production system, or a case where the switch is turned on while the bit line differential potential stays insufficient.

Claims: A semiconductor memory device comprising a plurality of word lines (WL), a plurality of pairs of bit lines (BL) intersecting with said word lines, a plurality of memory cells (CL) coupled to said word lines and said bit lines, a plurality of sense amplifiers (SA) each having first and second input/output nodes and first and second power nodes, each of said sense amplifiers being coupled at said first and second input/output nodes thereof to each pair of bit lines and amplifying, when activated, one and the other of each pair of bit lines to first and second potentials, respectively, said first and second potentials being approximately equal to first and second power voltages (Vcc, GND), respectively, a plurality of bit line precharge circuits (BP) provided for said plurality of pairs of bit lines, each of said bit line precharge circuits operatively precharging each pair of bit lines to a third potential having an intermediate value between said first and second potentials, a pair of common data lines (DB), a column selection circuit (YSW) for selectively connecting one pair of bit lines to said pair of common data lines to thereby establish signal paths therebetween, and a data line precharge circuit (10', 10'') for operatively precharging said pair of data lines approximately at said third potential, characterized in that said memory device further comprises a control circuit (14) coupled to said first and second power nodes of each of said sense amplifiers and supplying said first and second power nodes with said third potential when each of said sense amplifier is deactivated and with said first and second power voltages, respectively, when each of said sense amplifiers is activated. The semiconductor memory device according to claim 1, in which each of said memory cells (22) includes a storage capacitor (C M ) and a transfer gate transistor (Q M ) coupled between said storage capacitor and one of said bit lines. The semiconductor memory device according to claim 1, in which said data line precharge circuit (10′, 10″) includes means (Q₃₃) for operatively shortcircuiting said pair of data lines. The semiconductor memory device according to claim 1, in which each of said bit line precharge circuits (BP) includes means (Q₁₂) for operatively shortcircuiting the associated pair of bit lines. The semiconductor memory device according to claim 1, in which each of said sense amplifiers (SA) includes a CMOS type flip-flop. The semiconductor memory device according to claim 1, further comprising a data amplifier (BA) for operatively amplifying potentials of said pair of data lines to said first and second potentials. The semiconductor memory device according to claim 1, in which said column selection circuit (YSW) includes a plurality of pairs of transfer gates (Q8, Q9) coupled between said plurality of pairs of bit lines and said pair of common data lines, and means (12) for selcetively enabling one pair of said transfer gates. The semiconductor memory device according to claim 1, characterized in that said control circuit (14) includes a first line (SAP) connected in common to said first power nodes of said sense amplifiers, a second line (SAN) connected in common to said second power nodes of said sense amplifiers, a first transistor (Q17) connected between said first line and a third line (HVC) supplied with said third potential, a second transistor (Q18) connected between said second line and said third line, a third transistor (Q16) connected between said first and second lines and having a gate connected in common to the gates of said first and second transistors, a fourth transistor (Q15) connected between said first line and a fourth line supplied with said first power voltage (Vcc), and a fifth transistor (Q19) connected between said second line and a fifth line supplied with said second power voltage, said first to third transistors being turned on when each of said sense amplifiers is deactivated and said fourth and fifth transistors being turned on when each of said sense amplifiers is activated.

Inventors: NAKADA KAZUHIRO C O NEC CORPOR, NAKADA, KAZUHIRO C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: G11C7
IPC codes: G11C11