Semiconductor memory having improved sense amplifiers

Abstract: A semiconductor memory device comprises a sense amplifier (SAa), a reference potential terminal (Vss), a switching element (Sa), and control means. The switching element (Sa) is connected between said sense amplifier (SAa) and said reference potential terminal (Vss). The control means generates and supplies a first column-selecting signal (CD1a) to the switching element (Sa) to turn on and off said switching element (Sa).

Description: The present invention relates to a semiconductor memory device comprising: i) a plurality of columns of memory cells, each column comprising a complementary pair of bit lines; ii) a plurality of first sense amplifiers, each associated with a corresponding pair of bit lines and all sharing a common activation line to a reference potential for discharging, in response to an activation signal (ACTIVATE SIGNAL), to the reference potential one bit line of each pair of bit lines through the common activation line. From EP-A-0 031 995 a semiconductor RAM device is known having a plurality of static type memory cells which are disposed in a matrix of rows and columns and each of which is selected by an output from a row decoder and an output from a column decoder, the row decoder being responsive to input address signals wherein the semiconductor RAM device comprises an amplifier circuit at each column which amplifies a data signal from the memory cell; and gate circuits which are operated by a control signal and which pass a data signal from a selected memory cell to the corresponding amplifer circuit. During read operation, only the amplifier circuit of a selected column is made active. Fig. 3 is a circuit diagram showing a part of a conventional DRAM (Dynamic Random Access Memory). As is shown in this figure, the DRAM has bit-line sense amplifiers SAa SAb, ..., each connected to a different pair of bit lines, (BLa, BLa ), (BLb, BLb ), or the like. These bit-line sense amplifiers are connected to the reference potential (Vss) terminal (i.e. the Vss potential pad) by means of a commond source line 31 and a MOS transistor 32. (The MOS transistor 32 is used to activate the sense amplifiers (SAa, SAb, ...). Each sense amplifer comprises the N-type MOS transistors, whose drains and gates are cross-coupled, and whose sources are connected to each other and also to the common source line 31. The current flowing in that MOS transistor of each sense amplifier, which is used to reduce the potential of the bit lines to a low level, is supplied through the source line 31 and discharged at the Vss terminal. Various parasitic resistances exist between the sense amplifier and the Vss terminal, such as the resistance of the source line 31, the resistance of the MOS transistor 32, and the resistance of the Vss power-supply line. The greater the storage capacity of the DRAM, and hence, the larger the chip of the DRAM, the higher these parasitic resistances. Further, the greater the storage capacity of the DRAM, the greater the number of the bit-line sense amplifiers, which are simultaneously activated. More specifically, when the storage capacity increases four times, twice as many bit-line sense amplifiers are activated at the same time in order to accomplish refresh operation. Consequently, the CR time constant of the sense amplifiers increases in proportion to the storage capacity of the DRAM. This is because the CR time constant is the product of capacitance C and resistance R, where C in turn is the product of the capacitance of one bit line and the number of the sense amplifiers, and R is the sum of the parasitic resistances existing between each sense amplifier and the Vss terminal. No data can be read from a bit line to an I/O bus until the sense amplifiers amplify the potentials of the bit lines to a sufficient degree. (Were the data be read out before the sense amplifiers sufficiently amplify the potentials of the bit lines, it would be destroyed) An increase of the CR time constant of the sense amplifiers directly results in an increase of the access time of the DRAM. In other words, the source potential of each sense amplifier cannot go fast to the Vss potential despite the amplification of the bit-line potential, and the bit lines cannot be latched quickly. Two methods of decreasing the CR time constant have been proposed. The first method is to reduce the capacitance of each bit line. To this end, the memory cells are divided into more blocks, so that less memory cells are connected to one bit line. When the memory cells are divided into many blocks, however, the DRAM need to have more decoders and more sense amplifiers which occupy a greater area on the semiconductor chip. The second method is to use a source line comprising two aluminum layers, thereby reducing the parasitic resistance existing between each sense amplifier and the Vss terminal. This method is, as it were, a forced, fast driving of the large capacitance of the source line, and results in capacitive coupling. This capacitive coupling is likely to greatly change the substrate capacitance, to influence the other circuits adversely which are used in combination within the DRAM. The present invention has been made to solve the problem inherent in the conventional DRAM, i.e. the long access time due to the greater CR time constant of the sense amplifiers incorporated in the DRAM, which cannot amplify the bit-line potential at sufficiently high speed. The ojbect of the present application is to improve the read speed in a memory device of the initially defined type. This object is solved according to claim 1 of the present application. Preferred embodiments are listed in the dependent claims. When the switching elements (Sa, Sb, ...) coupled to the sense amplifiers (SAa, SAb, ...) are turned on by column-selecting signals (CD1a, CD1b, ...) supplied from the control circuit (61), they connect the sense amplifiers (SAa, SAb, ...) with the reference potential terminal (Vss). Hence, it is only the capacitances of the selected bit lines that determine the CR time constant of the sense amplifiers (SAa, SAb, ...). As a result the CR time constant for the reference potential terminal (Vss) is small. The sense amplifiers (SAa, SAb, ...) can, thus, sense and amplify the bit-line potentials at high speed, whereby data can be read from the bit line to an I/O but at sufficiently high speed. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a part of a DRAM, which is an embodiment of the present invention; Fig. 2 is a circuit diagram showing a modification of the DRAM illustrated in Fig. 1; Fig. 3 is a circuit diagram representing a part of the conventional DRAM; Fig. 4 is a circuit diagram showing a DRAM according to the invention, wherein includes both N-channel sense amplifiers and P-channel sense amplifiers; Fig. 5 is a diagram explaining the relationship between a column-selecting signal and a decoder-gating signal; Fig. 6 is a timing chart illustrating the relationship between a column-selecting signal and other signals; and Fig. 7 is a diagram showing a circuit for delaying the column-selecting signal which control a column switch. An embodiment of the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a diagram showing a part of a DRAM, which is the embodiment of the invention. As is shown in Fig. 1, the DRAM has sense amplifiers SAa, SAb, ... connected to the bit-line pairs (Bla, BLa ), (BLb, BLb ), ... respectively. Each sense amplifier comprises two N-type MOS transistors whose drains and gates are cross-coupled, and whose sources are connected to each other. The bit lines of this DRAM are pre-charged to a half Vcc power-supply potential, and two P-type MOS transistors (not shown) are connected to each sense amplifier in order to restore the potentials of the bit lines. The connecting point 3 of the MOS transistors of the sense amplifier SAa, and the connecting point 4 of the MOS transistors of the sense amplifier SAb are connected to normally ON type MOS transistors Na and Nb, respectively. (These transistors Na and Nb are N-type MOS transistors whose gates are applied with the Vcc power-supply voltage.) The MOS transistors Na and Nb are connected to a common source line 1. The common source line 1 is connected to a MOS transistors 2 which is provided for activating the sense amplifiers SAa, SAb, .... The MOS transistor 2 is coupled to the reference potential terminal (i.e., the Vss-potential pad) of the memory chip. Thus, the connecting points 3 and 4 are connected to the reference potential terminal by means of the transistors Na and Nb, the common source line 1, and the MOS transistor 2. The MOS transistors Na and Nb can be replaced by resistors made of polycrystalline silicon. Fig. 2 is a circuit diagram showing a modification of the DRAM shown in Fig. 1. The modified DRAM is different from the DRAM shown in Fig. 1 in two respects. First, a timing signal T1 is supplied to the gates of the MOS transistors Na and Nb, so that they are turned on at the same time. Second, it comprises no element equivalent to the MOS transistor 2 used in the DRAM shown in Fig. 1, so that the DRAM can be made smaller. The DRAM shown in Fig. 1 will be further described. The connecting points 3 and 4 of the sense amplifiers SAa, SAb, ... are connected to the Vss-potential pad by means of switching elements Sa, Sb, ..., respectively. These switching elements Sa, Sb, ... are selectively turned on under the control of a control circuit 61 shown in Fig. 5. They are, for example, N-type MOS transistors, whose gates are coupled to receive column-selecting signal CD1a, CD1b, .... The DRAM further comprises column switches CSa, CSb, ..., and a pair of data lines I/O and I/O . The column switches CSa, CSb, ... connect the bit-line pairs BLa, BLa ), (BLb, BLb ), ... with the data lines I/O and I/O . The column switches CSa, CSb, ... are, for example, N-type MOS transistors, whose gates are connected to receive column-selecting signals CD2a, CD2b, ... output by a column decoder (not shown). The column-selecting signals CD1a, CD1b, ... are output of the control circuit 61. As is shown in Fig. 5, the control circuit 61 receives the column address signals and a decoder-gating signal CG. As has been described, the signals CD1a, CD1b, ... control the switching elements Sa, Sb, ... (Fig. 1). The control circuit 61 outputs any column-selecting signal designated by the column address signals Y supplied to the circuit 61, upon receipt of the decoder-gating signal CG which is input to the circuit 61. The column-selecting signals CD2a, CD2b, ..., which control the column switches CSa, CSb, ..., are generated some time later than the column-selecting signals CD1a, CD1b, ..., as is evident from Fig. 6. As is shown also in Fig. 6, the decoder-gating signal CG is generated a little later than a sense amplifier activate signal . The column-selecting signals CD1a, CD1b, ... are generated, as has been pointed out, simultaneously with the decoder-gating signal CG. The column-selecting signals CD2a, CD2b, ... are produced by delaying the column-generating signals CD1a, CD1b, ... by means of the delay circuit illustrated in Fig. 7. It will now be explained how the sense amplifiers of the DRAM detect the potentials of the bit lines and how they read data to the I/O buses. When the MOS transistor 2 is turned on, the sense amplifiers SAa, SAb, ... start detecting the potentials of the bit lines. Simultaneously, the currents flowing in those MOS transistor of the sense amplifiers SAa, SAb, ..., which are used to reduce the potential of the bit lines to a low level, are supplied via the normally ON type MOS transistors Na and Nb and discharged at the Vss terminal. Various parasitic resistances exist between each sense amplifier and the Vss terminal, such as the resistance of the source line 1, the resistance of the MOS transistor 2, and the resistance of the Vss power-supply line. However, each sense amplifier is by-passed to the Vss terminals by the switching elements Sa, Sb, .... This is because the switching elements Sa, Sb, ..., which are connected to the sense amplifiers of any selected column, have been selected and turned on in accordance with the column-selecting signals CD1a, CD1b, .... That is, when the column-selecting signals CD1a, CD1b, ... become active, some of the column of sense amplifiers, only a few, in most cases, are selected. Inevitably, parasitic resistances come into being between the sense amplifiers of the selected columns, on the one hand, and the Vss terminal, on the other. Nonetheless, the total capacitance of the few bit lines coupled to these sense amplifiers is very small. Therefore, the CR time constant of the sense amplifier is extremely small, however thin the line connecting each sense amplifier and the Vss terminals is. The source potential of the sense amplifier thus falls quickly to the Vss potential. The pair of bit lines, which are connected to the sense amplifiers, are quickly latched. In other words, a specific potential difference is fast set between these bit lines. That is, the sense amplifiers can quickly detect the potentials of the bit lines. Moreover, the potential difference between the bit lines of each pair is read to the corresponding I/O bus through the switching element which has been turned on when the column-selecting signal becomes active. Nevertheless, since a specific potential difference is fast set between these bit lines, the data stored in any memory cell coupled to the bit lines is not destroyed, and can be readily read out to the I/O bus at high speed. As has been noted, Fig. 2 is a diagram illustrating a modification of the DRAM shown in Fig. 1. This modification is different form the DRAM shown in Fig. 1, in two respects. First, it has no element equivalent to the MOS transistor 2. Secondly, sense amplifiers SAa, SAb, ... are connected to a common source line 1 by MOS transistors 2a, 2b, ... which are provided to activating the sense amplifiers SAa, SAb, .... The modification accomplishes the same advantages as the DRAM shown in Fig. 1. Fig. 4 is a circuit diagram representing a DRAM according to this invention. This DRAM is of CMOS structure. In other words, switching elements are provided not only for a sense amplifier comprising N-type transistors 43 and 44, but also for a sense amplifier comprising P-type transistors 41 and 42. More precisely, a switching element 47 is connected to the sense amplifier comprising N-type transistors 43 and 44. A column-selecting switch CSa is connected between I/O lines. The connecting point of the sources of the transistors 43 and 44 is connected to the reference potential terminal (i.e. a Vss potential pad) by a resistance component 48, a MOS transistor 50 for activating the sense amplifier, and a common source line 51. Similarly, a switching element 45 is connected to the sense amplifier comprising P-type transistors 41 and 42. The connecting point of the sources of the transistors 41 and 42 is connected to a power-supply terminal (Vss) by a resistance component 46, a MOS transistor 49 for activating the sense amplifier, and a common source line 52. The unit comprising the elements 41, 42, 45, 46, 49, and 52, which is connected to the Vcc terminal, is symmetrical in structure to the unit comprising the elements 43, 44, 47, 48, 50, and 51, which is connected to the Vss terminal. Obviously, since only two switching elements, i.e., the elements 45 and 47, suffice to detect the potential difference between the bit lines, it is possible to detect the potential difference at high speed. It should be noted that the resistance component 46 is a normally ON type MOS transistor, and is connected in the common source line 52. As has been described above, the present invention can provide a semiconductor memory having sense amplifiers whose CR time constant can be reduced, when necessary, and which can, therefore, amplify the bit-line potential so fast that data can be read from the memory to an I/O bus at high speed. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor memory device comprising: i) a plurality of columns of memory cells, each column comprising a complementary pair of bit lines (BLa, BLa ; BLb, BLb ; BL, BL ); ii) a plurality of first sense amplifiers (SAa, SAb, 43,44), each associated with a corresponding pair of bit lines and all sharing a common activation line (Na, Nb, 1, 2, 2a, 2b, 48, 50, 51) to a reference potential (Vss) for discharging, in response to an activation signal (ACTIVATE SIGNAL), to the reference potential one bit line of each pair of bit lines through the common activation line; characterized by iii) a plurality of first switching elements (Sa, Sb, 47) connected in parallel with the activation line between one end of an associated sense amplifier and the reference potential; and iv) a first control means (61) for generating and supplying a first column selection signal (CD1a, CD1b) to the plurality of switching elements to turn on only that switching element which is associated with a selected column of memory cells, after the plurality of sense amplifiers have been activated by the common activation line. The semiconductor memory device according to claim 1, characterized by further comprising: a plurality of column switch elements (CSa, CSb), each connected to the other end of an associated sense amplifier (SAa, SAb); and a second control means (62) for generating and supplying a second column selection signal (CD2a, CD2b) to the plurality of column switch elements (CSa, CSb), said second column selection signal (CD2a, CD2b) being activated after said first column selection signal (CD1a, CD1b) to turn on the column switch element of the sense amplifer whose switching element is turned on by said first column selection signal. The semiconductor memory device according to claim 1 or 2, characterized by further comprising: a resistor means (Na, Nb, 2a, 2b) for providing a resistance between said respective sense amplifiers (SAa, SAb) and said reference potential terminal (Vss) on said activation line. The semiconductor memory device according to claim 3, characterized in that said resistor means (Na, Nb, 2a, 2b) includes a plurality of normally-on type MOS transistors. The semiconductor memory device according to claim 3, characterized in that said resistor means (Na, Nb, 2a, 2b) includes a plurality of transistors (2a, 2b) whose gates are connected to receive a timing signal (T1). The semiconductor memory device according to claim 3, characterized in that said resistor means (Na, Nb 2a, 2b) includes a plurality of resistors. The semiconductor memory device according to claim 1, characterized by further comprising: a plurality of second sense amplifiers (41, 42) each connected to a corresponding first sense amplifier and having an opposite conductivity than said first sense amplifier; a plurality of second switching elements (45) connected between one end of an associated second sense amplifier and a power-supply terminal (Vcc), and having said opposite conductivity. The semiconductor memory device according to claim 7, characterized in that said pluralities of first and second sense amplifiers (43, 44; 41, 42) comprise transistors which are N-type and P-type ones, respectively, the respective first and second switching elements and resistor means associated with the respective sense amplifiers having the same conductivity type as the associated sense amplifiers.

Inventors: OKADA YOSHIO C O INTELLECTUAL, OKADA, YOSHIO C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G11C7
IPC codes: G11C11, G11C7