Test facilitating circuit of logic circuit

Abstract: A test facilitating circuit comprises an arithmetic block (LB) to be tested including an arithmetic unit for operating multiple bits as well as including various registers related to the arithmetic unit. The test facilitating circuit further comprises flip-flops (FF) for receiving data from a first pin (P₁) and forming a shift register, multiplexers (M) for selectively generating control signals for controlling the elements in the arithmetic block to be tested, a second pin (P₂) connected to the flip-flops and multiplexers to externally provide them with a test mode signal under a test mode, a bus switch (7) connected between a third pin (P₃) and an internal data bus (B) to control input of test data from the third pin (P₃) to the arithmetic block (LB) and input of an operation result to the third pin (P₃) via the internal data bus (B), gates (G₁,G₂) for controlling data input and output with respect to the bus switch (7) and timing signal generator for generating timing signals for controlling the gates. At the time of test, the second pin (P₂) provides the test mode signal. According to this signal, the flip-flops hold test control data, while the multiplexers generate control signals based on the timing signals to test the arithmetic block at high speed.

Description: Field of the Invention The present invention relates to a test facilitating circuit of a logic circuit to improve efficiency of testing the logic circuit. The test facilitating circuit is generally applicable to an arithmetic circuit having bus structure. Description of the Prior Art To test a logic circuit, particularly a combinational circuit of large scale integrated (LSI) circuit, a scan pass method and an ad hoc method are known to be effective. According to the scan pass method, flip-flops in a logic circuit are used as a shift register to form a scan pass. The flip-flops are directly controlled from the outside to test the logic circuit, and then a result of the test is observed. Namely, combinational circuits (flip-flops) are rearranged as a sequential circuit (shift register) according to the scan pass method to achieve the test. The scan pass method is reliable and effective if testing time and hardware are allowed to increase. Therefore, the scan pass method is frequently employed to test LSI logic circuits. The conventional scan pass method will be explained with reference to Fig. 1. In the figure, an arithmetic circuit comprises an adder AD, input registers A and B, a data register D, an output inverting device I, an internal data bus B, an output driver BL, and a decoding logic circuit L₁. The decoding logic circuit L₁ generates signals for controlling the circuit elements by decoding the bit pattern of a flip-flop group FF. The registers A and B, data register D and flip-flop group FF are employed to form a scan pass according to the scan pass method. The circuit shown in Fig. 1 is a typical arithmetic circuit of a microprocessor having bus structure. In the circuit of Fig. 1, signal passes are clearly separated. Namely, control signals C₁ to C₆ are separately transmitted from a 32-bit data pass. Therefore, it is necessary to utilize this characteristic in designing a testing circuit. According to the scan pass method, the flip-flops in the flip-flop group FF are simply connected in series to form a shift register that handles both data and control signals in the test. This is not efficient. Meanwhile, the ad hoc method (not particularly shown but Fig. 1 may be referred to as a reference) inserts gates at nodes 10 of the control lines between the decoding logic L₁ and the adder AD of Fig. 1. The nodes 10 are directly controlled via external pins to carry out a test. The scan pass method firstly explained greatly increases a testing time due to data transfer in testing a large scale logic circuit block including various arithmetic circuits. In addition, a bit structure of a system increases, the number of bits to be involved in a scan pass drastically increases deteriorate testing efficiency. The ad hoc method secondly explained requires gates to be inserted in the same number as the number of nodes of control lines (six in Fig. 1) to form test points. Therefore, external pins for the exclusive use of test shall be prepared in the same number as the number of the gates. As a result, costs are drastically increased if the number of arithmetic circuits to be tested is increased. From US 3 790 885 a techique of decreasing the number of test patterns required to test a MOSFET module is known according to which a serial test pattern is applied to a single input pin on the module and a serial test pattern is stored in a shift register which is on the module. Each of the stages of the shift register are used to control or monitor an element or point which may be otherwise inaccessible or untestable. The shift register is also utilized in an output mode to provide an indication serially on a single output pin as to the functioning of the points accessed on the module. SUMMARY OF THE INVENTION An object of the present invention is to provide a test facilitating circuit of an arithmetic circuit to remarkably improve efficiency of testing the arithmetic circuit. According to the present invention this object is solved by a test facilitating circuit comprising: (a) an arithmetic block to be tested including elements such as arithmetic means for operating multiple bits as well as including various registers related to the arithmetic means; (b) a plurality of flip-flops for holding test control data supplied from a first pin, said plurality of flip-flops being connected to form a shift register; (c) a plurality of multiplexers for selectively supplying a plurality of test control signals and normal operation control signals to said arithmetic block to be tested to control respectively elements in the arithmetic block; (d) a second pin connected to said plurality of flip-flops and multiplexers to provide a test mode signal at the time of test; (e) bus switching means connected between third pins and an internal data bus to control test data input from the third pins to said arithmetic block via the internal data bus as well as controlling operation result input from said arithmetic block to the third pins via the internal data bus; (f) gate means for controlling data input and output with respect to said bus switching means, and (g) timing signal generating means responsive to a test timing signal for generating timing signals for controlling said gate means under a test mode; wherein, under a normal operation mode in which said plurality of multiplexers selects the normal operation control signals and supplies the same to the arithmetic block, said plurality of flip-flops sequentially transfers and holds the test control data for achieving the predetermined test, and, under a test operation mode, said plurality of flip-flops holding the test control data supplies the same to said plurality of multiplexers generating the test control signals according to the test mode signal given by said second pin, while the test data being inputted according to the timing signals thus testing said arithmetic block with high efficiency. In order to accomplish the object, the present invention provides a test facilitating circuit of a logic circuit. The test facilitating circuit of the invention comprises an arithmetic block to be tested. The arithmetic block includes arithmetic means for operating multiple bits, and various registers related to the arithmetic means. The test facilitating circuit further comprises a plurality of flip-flops for receiving data from a first pin and forming a shift register, a plurality of multiplexers for selectively generating a plurality of control signals for controlling the elements in the arithmetic block to be tested, a second pin connected to the flip-flops and multiplexers to externally provide them with a test mode signal under a test mode, bus switch means connected between a third pin and an internal data bus to control input of test data from the third pin to the arithmetic block and input of an operation result to the third pin via the internal data bus, gate means for controlling data input and output with respect to the bus switch means, and timing signal generating means for generating timing signals for controlling the gate means under the test mode. At the time of testing, the second pin provides the test mode signal. According to the test mode signal, the flip-flops hold input data. According to the timing signals, the multiplexers generate control signals to test the arithmetic block at high speed. These and other objects, features and advantages of the invention will be more apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block circuit diagram showing a conventional test moethod of an arithmetic logic circuit; Fig. 2 is a block circuit diagram showing a test facilitating circuit of a logic circuit, according to a first embodiment of the invention; Fig. 3 is a detailed circuit diagram showing a timing signal generating circuit for generating various timing signals shown in Fig. 2; Fig. 4 is a timing chart explaining operation of the circuit shown in Fig. 2; Fig. 5 is a block circuit diagram showing a test facilitating circuit of a logic circuit, according to a second embodiment of the invention; and Fig. 6 is a block circuit diagram showing a test facilitating circuit of a logic circuit, according to a third embodiment of the invention. DETAILED DESCRIPTION OF THE EMBODIMENTS Figure 2 shows a test facilitating circuit of logic circuits, according to the first embodiment of the invention. The circuit of the embodiment employs a 32-bit adder 1 as an example. Around the 32-bit adder 1, there are arranged an input register A2, an input register B3, an input data inverting circuit 4, an output data inverting circuit 5, and an output driver 6 for outputting data to a 32-bit internal data bus B. The adder 1 has an operation mode controlled by two operation control signals C₆ and C₇. A block encircled with a dotted line and including the elements around the adder 1 will be referred to as an arithmetic block LB. Control signals C₃, C₄, C₅, C₈ and C₉ directly control the arithmetic block LB. Control signals C₁ and C₂ are used for another purpose that will be explained later. The test facilitating circuit comprises a plurality of flip-flops FFi (i=1 to 7). The flip-flops FFI hold control signals for carrying out a required test in the arithmetic block LB under the test mode. The test facilitating circuit further comprises multiplexers Mi (i=1 to 7). The multiplexers Mi follow a test mode signal to selectively supply control signals held in the flip-flops FFi or control signals for normal operation. The G₃, G₄ and G₅ disposed between the flip-flops FF₁, FF₂ and FF₇ and the multiplexers M₁, M₂ and M₇, respectively, to control the operation timing of the input register A2, input register B3 and output driver 6 of the arithmetic block LB. The test facilitating circuit further comprises a bus switch 7 for controlling input and output of test data with respect to the internal data bus B, AND gates G₁ and G₂ for controlling operation of the bus switch 7, and a timing signal generating circuit (Fig. 3) for supplying timing signals TA to TE to the AND gates G₁ to G₅ to carry out a required test. The flip-flops FFi (i=1 to 7) except the flip-flop FF₁ on the left end side are connected in series such that a D-input terminal and a Q-output terminal of adjacent flip-flops are connected to each other in series, thus forming a shift register. A D-input terminal of the flip-flop FF₁ is connected to a data input pin P₁. When no test mode signal S is inputted from a pin P₂, i.e., when the test mode signal S is 0, data from the pin P₁ are shifted in the flip-flops from FF₁ to FF i+1 . However, when the test mode signal S is 1, data set in the flip-flops FF i are held therein. The multiplexers Mi (i=1 to 7) receive normal operation control signals C₁₀ to C₁₆, respectively, and outputs of the flip-flops FF₁ to FF₇, respectively. When the test mode signal S is 1, the multiplexers Mi output the data held in the respective flip-flops FFi as the control signals C₃ to C₉. Under the normal operation with the test mode signal S being 0, the multiplexers Mi output the normal operation control signals C₁₀ to C₁₆ as the control signals C₃ to C₉. The internal data bus B is connected to the bus switch 7 that controls input and output of test data with respect to the internal data bus B. The bus switch 7 is connected to the data pin P₃ for inputting the test data. The bus switch 7 comprises two buffers controlled by the control signals C₁ and C₂. The AND gates G i (i=1 to 5) operate AND between the timing signals TA, TB, TC, TD and TE generated under the test mode (S=1) and the outputs of the flip-flops FFi to generate output signals according to the AND operation. Figure 3 shows an example of the timing signal generating circuit for generating the timing signals TA to TE shown in Fig. 2. The timing signal generating circuit comprises two flip-flops FF₁₀ and FF₁₁, two inverters I₁ and I₂ and two AND gates A₁ and A₂. According to test timing signals Tin and clock signals CLK, the timing signal generating circuit generates the timing signals TA to TE. Operation of the test facilitating circuit of the invention will be explained with reference to a timing chart of Fig. 4. Under normal operation, the test mode signal S from the pin P₂ is 0, and the normal operation control signals C₁₀ to C₁₆ are sequentially applied to the respective elements of the arithmetic block BL via the multiplexers M₁ to M₇. Under the normal operation with the test mode signal S being 0, the test control data from the pin P₁ are sequentially transferred to the flip-flops FFi. For example, to control bus access timing, a bit pattern of 1010001, i.e., a bit pattern with first, third and seventh bits being 1 is set in the flip-flops FFi. After the required data are transferred to the flip-flop FFi, the test mode signal S from the pin P₂ is set to 1. Then, the contents of the shift register comprising the flip-flops FFi are transmitted to the arithmetic block LB via the multiplexers Mi to prepare for testing the elements of the arithmetic block LB. After that, the test timing signal Tin is given to the timing signal generating circuit of Fig. 3. to generate the timing signals TA to TE. The AND gates G₁ to G₅ operate ANDs to provide outputs for controlling the bus switch 7 and multiplexers M₁, M₂ and M₇. Test execution sequences shown in Fig. 4 will be explained. With the timing signal TA=1 in cycle I of sequence I, test data given to the data pin P₃ are outputted to the internal data bus B via the bus switch 7 according to the control signal C₁ from the AND gate G₁. With the timing signal TC=1, the test data are received by the register A2 from the internal data bus B. Similarly, with the timing signals TA=1 and TD=1 in cycle II, test data from the data pin P₃ are received by the register B3 via the internal data bus B. In cycle III, the data in the registers A2 and B3 are added to each other in the adder 1. With the timing signal TE=1, an added result is outputted to the internal data bus B via the bus driver 6. With the timing signal TB=1, the bus switch 7 is switched over such that the added result outputted to the internal data bus B are given to the data pin P₃. In this way, according to the test facilitating circuit of the invention, the adder 1 can be tested once in three cycles, i.e., in the cycles I, II and III. Therefore, by repeating the test sequences in required times, optional tests may be achieved. As is apparent in the timing chart of Fig. 4, a single test of the adder 1 is completed at high speed within three clock cycles after the test mode is established, i.e., after the test mode signal is set to 1. If the data pin P₃ already exists, pins necessary for the test will be the pins P₁ and P₂ and a pin Pin for the test timing signal Tin. Namely, only three additional pins are needed for the test, thereby reducing hardware overhead. Figure 5 shows a test facilitating circuit according to the second embodiment of the invention. In Fig. 5, for the sake of simplicity, the second flip-flop FF₂, AND gate G₄ and multiplexer M₂ of Fig. 2 are presented with a reference mark F₁, while the sixth flip-flop FF₆ and multiplexer M₆ of Fig. 2 are represented with a reference mark F₂. The adder 1 and its related elements of Fig. 2 are represented with an arithmetic block LB in Fig. 5. Unlike the first embodiment of Fig. 2, the second embodiment of Fig. 5 has a decoding logic circuit DL on respective control lines (nodes) entering the arithmetic block LB. When timing signals TA to TE are generated, the decoding logic circuit DL decodes output signals of the respective elements Fi to provide decoded outputs to the elements in the arithmetic block BL to achieve a test. Figure 6 shows a test facilitating circuit according to the third embodiment of the invention. In this embodiment, a plurality of macroblocks, i.e., arithmetic blocks I, II and III are tested. Flip-flop chains (shift registers) MI, MII and MIII each comprising flip-flops are arranged. Any of the flip-flop chains can be selected to independently test corresponding one of the arithmetic blocks. For example, to selectively test the arithmetic block II, bits each of 0 will be transferred to portions for controlling bus-outputs of the flip-flop chains I and III. Then, the flip-flops I and III are blocked so that only the arithmetic block II may be tested independently of the others. In summary, the present invention can test a logic circuit at high speed with small number of pins. In testing a plurality of arithmetic blocks, the present invention can test particular one of the arithmetic blocks selectively and independently of the others. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

Claims: Test facilitating circuit comprising: (a) an arithmetic block (LB) to be tested including elements (1-6) such as arithmetic means for operating multiple bits as well as including various registers related to the arithmetic means; (b) a plurality of flip-flops (FF1-FF7) for holding test control data supplied from a first pin (P1), said plurality of flip-flops being connected to form a shift register; (c) a plurality of multiplexers (M1-M7) for selectively supplying a plurality of test control signals and normal operation control signals (C10-C16) to said arithmetic block to be tested to control respectively elements in the arithmetic block; (d) a second pin (P2) connected to said plurality of flip-flops and multiplexers to provide a test mode signal at the time of test; (e) bus switching means (7) connected between third pins (P3) and an internal data bus (B) to control test data input from the third pins to said arithmetic block via the internal data bus as well as controlling operation result input from said arithmetic block to the third pins via the internal data bus; (f) gate means (G1, G2) for controlling data input and output with respect to said bus switching means, and (g) timing signal generating means responsive to a test timing signal (Tin) for generating timing signals (TA-TE) for controlling said gate means under a test mode; wherein, under a normal operation mode in which said plurality of multiplexers selects the normal operation control signals and supplies the same to the arithmetic block, said plurality of flip-flops sequentially transfers and holds the test control data for achieving the predetermined test, and, under a test operation mode, said plurality of flip-flops holding the test control data supplies the same to said plurality of multiplexers generating the test control signals according to the test mode signal given by said second pin (P₂), while the test data being inputted according to the timing signals thus testing said arithmetic block with high efficiency. The test facilitating circuit as claimed in claim 1, further comprising other gate means (G3, G4, G5) connected to inputs of predetermined ones of said multiplexers, wherein said timing signal generating means generating other timing signals for controlling the other gate means.

Inventors: NISHIMURA AKIRA, NOZUYAMA YASUYUKI, NISHIMURA, AKIRA, NOZUYAMA, YASUYUKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G06F11
IPC codes: G06F11, G01R31