A stereo multiplex demodulator

Abstract: A composite stereo signal comprised of a modulated signal balanced-modulated by a sum signal which is the sum of left and right channel audio signals and a difference signal which is the difference between the left and right channel audio signals, and a pilot signal synchronised with the modulated signal, has the left and right channel audio signals demodulated therefrom by a stereo multiplex demodulator that includes a phase-locked loop (PLL) circuit (10) for forming a sine wave signal synchronised (So) with the pilot signal (Sp) and having a frequency equal to a subcarrier frequency of the modulated signal, and a multiplying circuit (8) for multiplying the composite stereo signal (Sc) and the sine wave signal (So) to generate the demodulated left and right channel audio signals.

Description: The present invention relates to a stereo multiplex demodulator which is suitable for application to an FM stereo receiver or the like. In present FM stereo broadcasting, a main carrier signal is frequency-modulated by a composite stereo signal Sc which is expressed as Therefore, in the FM receiver, a switching signal synchronised with the pilot signal Sp is generated with the frequency f, and this switching signal is used to switch the composite signal Sc into two channels, thereby demodulating the signals L and R into respective ones of those channels.. When the stereo signals are demodulated by switching as described above, the switching signal used is a rectangular wave signal, and contains higher order odd-numbered harmonics. Further, the composite signal Sc contains a higher harmonic components due to the non-linearity of the signal system, and it is frequently observed that the composite signal Sc contains a beat frequency component for the adjacent channel and an intermediate frequency signal component. Thus, when the stereo signals are demodulated, an undesired signal component contained in the composite signal Sc is switched by the higher harmonic component of the switching signal so that the stereo demodulated output contains a beat interference component caused by the undesired signal component in addition to the original signals L and R. In some FM receivers, the composite signal Sc is supplied to a low-pass filter thereby to remove the undesired signal component contained in the composite signal Sc. However, such low-pass filter needs to have a steep cut-off characteristic, which results in a complex circuit and therefore an increased cost. Further, when the composite signal Sc is processed by the low-pass filter, the phase and the frequency characteristic of the composite signal are affected by the low-pass filter, with the result that distortion is increased and the separation is made less effective. It has also been proposed that the composite signal Sc be switched only by the higher harmonic component of the switching signal, and that the beat interference component contained in the original stereo demodulated output be cancelled by the switched output. However, for this proposal to achieve its desired results, the level of the beat interference component used to cancel the beat interference component must accurately coincide with that of the beat interference component contained in the stereo demodulated output. Therefore, strict or very accurate adjustment is needed. Patent Abstracts of Japan Vol. 5, No. 109 (E-65)(781) discloses a stereo demodulator in which the composite stereo signal is multiplied by a signal phase locked to the pilot signal. Accordingly, it is an object of the present invention to provide an improved stereo multiplex demodulator which avoids the above noted problems of the prior art. More specifically, it is an object of the present invention to provide a stereo multiplex demodulator which can provide a stereo demodulated output which is devoid of any interference components. According to the present invention, there is provided an analog stereo multiplex demodulator for demodulating left and right channel audio signals from a stereo composite signal comprised of a modulated signal having a subcarrier frequency and being balanced-modulated by a signal which is the sum of said left and right channel audio signals and by a signal which is the difference between said left and right channel audio signals and a pilot signal synchronised with said modulated signal, said stereo multiplex demodulator comprising: phase-locked loop means for forming a signal synchronised with said pilot signal and having a frequency equal to said subcarrier frequency of said modulated signal, the synchronised signal being a sine wave; and analog multiplying means for multiplying said stereo composite signal and said sine wave signal so as to generate said left and right channel audio signals; characterised in that said phase-locked loop means includes a voltage controlled oscillator generating said sine wave signal; and by means for detecting the level of said sine wave signal and for correspondingly controlling said voltage controlled oscillator so as to maintain a predetermined constant level of said sine wave signal. As will become apparent from the following description, the invention can provide a stereo demodulated output free of any cross-talk component by use of a stereo multiplex demodulator which can be fabricated as an integrated circuit and therefore is well-adapted for mass-production. The above, and other features and advantages of the present invention, will be apparent in the following detailed description of a preferred embodiment of the invention when read in conjunction with the accompanying drawings, in which like reference numerals are used to identify the same or similar parts in the several views. In the drawings:- Figure 1 is a block diagram showing a receiver including a stereo multiplex demodulator according to an embodiment of the present invention; Figure 2 is a schematic block diagram more fully showing a multiplying circuit included in the demodulator of figure 1; Figure 3 (formed of figures 3A and 3B to permit illustration on a relatively large scale) is a schematic diagram showing a detecting circuit and a voltage controlled oscillator that are desirably included in the embodiment of the present invention shown in figure 1; and Figure 4 is a schematic diagram of voltage levels to which reference will be made in explaining the operation of the stereo multiplex demodulator according to the present invention. A stereo multiplex demodulator according to an embodiment of the present invention is shown in figure 1, incorporated in an FM receiver which generally comprises an antenna 1 having an antenna tuning circuit 2 connected thereto, a radio (high) frequency amplifier 3 connected to the tuning circuit 2, a mixer circuit 4 and a local oscillating circuit 5. An FM broadcast signal having a frequency selected by the tuning circuit 2 is frequency-converted by the mixer circuit 4 to an intermediate frequency signal having a frequency of, for example, 10.7 MHz, on the basis of a local oscillation signal from the local oscillating circuit 5. The intermediate frequency signal is supplied from the mixer circuit 4 through an intermediate frequency amplifier 6 to an FM-demodulator circuit 7, in which it is demodulated to a composite stereo signal Sc. The composite stereo signal Sc is supplied to a multiplying circuit 8. The composite stereo signal Sc is also supplied to a phase comparing circuit 11 which forms part of a phase locked loop (PLL) circuit 10. More specifically, a voltage-controlled oscillator (VCO) 13 generates an oscillation signal SO of sine waveform having a free running frequency f . This signal S o is supplied through a buffer amplifier 14 to a limiter 15, in which it is converted to a rectangular wave signal Sr. The signal Sr is supplied to a frequency dividing circuit or a divide-by-2 circuit 16, in which it is divided to provide a rectangular wave signal Sd which inverts its polarity in response to each leading edge of the signal Sr, or the signal Sd is synchronised with the leading edge of the signal Sr (a zero-cross point at which the signal S o changes from the negative level to the positive level) and the signal 5d has a frequency f/2. This signal Sd is supplied to the phase comparing circuit 11. The phase comparing circuit 11 phase-compares a pilot signal Sp contained in the signal Sc and the signal Sd, and supplied the phase-compared output through a low-pass filter 12 to the VCO 13 as the control signal for the latter. Accordingly, in the stable state of the PLL circuit 10, the signal S is a sine wave signal having the frequency f and which is synchronised with the pilot signal Sp. The signal S o is supplied to the multiplying circuit 8 and is there multiplied by the signal Sc. By this multiplication, the signal Sc is demodulated, as hereinafter described in detail, to provide left and right channel signals L and R. The signals L and R are supplied to terminals 100L and 100R via low-pass filters 9L and 9R, respectively, for de-emphasising and which are used to remove unnecessary high band components. Simultaneously, a portion of the signal S o supplied to the multiplying circuit 8 is supplied to a level detecting circuit 21 which detects the level of the signal S o . The resulting detected signal St is supplied from the detecting circuit 21 through a low-pass filter 22 to the VCO 13 as a control signal fr controlling the magnitude of its oscillation. Therefore, the signal S o is controlled to have a predetermined constant level. The signal Sr from the limiter 15 is also supplied to a frequency dividing circuit (or divide-by-2 circuit) 31, in which it is divided to provide a rectangular wave signal Sb which inverts its polarity in response to each trailing edge of the signal Sr. Therefore, the signal Sb has the same frequency f/2 as the signal Sd and is delayed in phase from the signal Sd by 90 degrees. The signal Sb is supplied to a comparing circuit 32, and the signal Sc from the demodulating circuit 7 is also supplied to the comparing circuit 32. In the example being described, between the pilot signal Sp in the signal Sc and the signal Sd there is a phase difference of 90 degrees maintained by the PLL circuit 10. The signal Sb also has a phase difference of 90 degrees relative to the signal Sd. Accordingly, when the received FM broadcast is in the stereo mode, the signal Sp in the signal Sc and the signal Sb are of the same phase so that the comparing circuit 32 generates a compared output having the level "1". When the FM broadcast is a monaural broadcast, the demodulating circuit 7 generates the output signal (L + R) and no pilot signal Sp is supplied to the comparing circuit 32 which accordingly provides a random noise as its output. The compared output of the comparing circuit 32 is supplied to a low-pass filter 33 which derives a signal which is "1" in the stereo broadcast mode and "0" in the monaural broadcast mode. This signal "1" or "0" is supplied to a suitable displaying device, such as, a light emitting diode (LED) 34 or the like, thereby provided a stereo/monaural indication. Referring now to figure 2, it will be seen that, in an example of the multiplying circuit 8 of figure 1, the collector-emitter path of a constant current source transistor Q5 is connected between ground and the connected together emitters of transistors Q1 and Q2 which constitute a differential amplifier A1. Further, the collector-emitter path of a constant current source transistor Q6 is connected between ground and the connected together emitters of transistors Q3 and Q4 which constitute a differential amplifier A2. The collectors of transistors Q1 and Q3 are connected together and the collectors of transistors Q2 and Q4 are connected together to form a pair of output terminals. The composite stereo signal Sc from the demodulating circuit 7 is supplied to a voltage-to-current converting circuit 41 in which the signal Sc is converted to a pair of balanced-type signal currents. The resultant signal currents are supplied to the bases of transistors Q5 and Q6 so that the transistors Q5 and Q6 are supplied, at their collectors, with currents I₁ and I₂, respectively, corresponding to the signal Sc. The currents I₁ and I₂ are expressed by the following equations: I₂ = I x = γ(Im + Is sinωt) where I x is the direct current component, Im is L + R, Is is L - R and γ is a predetermined constant. In the above equations (1) and (2), a current component corresponding to the pilot signal Sp is neglected for the sake of simplicity. Continuing with the description of the circuit shown on figure 2, it will be seen that an amplifier A3 and transistors Q11 and Q12 are connected to constitute a current-to-voltage converting circuit 43 having a logarithmic compression characteristic. More specifically, an output terminal of the amplifier A3 is connected to the base of the transistor Q11 whose collector is connected to a power source terminal T1. The emitter of the transistor Q11 is connected to an inverting input terminal of the amplifier A3 and a bias voltage source Vr is connected between the non-inverting input terminal of the amplifier A3 and the terminal T1. Furthermore, the collector-emitter path of the transistor Q12 is connected between the emitter of the transistor Q11 and the ground. An amplifier A4 and transistors Q13 and Q14 are shown to be similarly connected to constitute a current-to-voltage converting circuit 44 having a logarithmic compression characteristic. The oscillation signal S o from the VCO 13 is supplied through the buffer amplifier 14 to a voltage-to-current converting circuit 42, in which it is converted to a pair of balanced-type signal currents supplied to the bases of transistors Q12 and Q14, and the transistors Q12 and Q14 are supplied at their collectors with currents I₃ and I₄ corresponding to the signal S o . The currents I₃ and I₄ are expressed by the following equations: I₃ = (1 + Asinωt) Iy I₄ = (1 - Asinωt) Iy where A is the ratio of alternating current components to direct current components of the currents I₃ and I₄ and is determined so as to satisfy 0 < A ≦ 1. The output terminal of the amplifier A3 is also connected to the bases of the transistors Q1 and Q4 and the output terminal of the amplifier A4 is also connected to the bases of the transistors Q2 and Q3. In the circuit of figure 2, the corresponding transistors are arranged to have the same or similar characteristics. It will be appreciated that the currents I₃ and I₄ are also the emitter currents from the transistors Q11 and Q13, respectively, so that the transistors Q11 and Q13 generate, at their base-emitter paths, a pair of voltages V₃ and V₄ which are current-to-voltage-converted from the currents I₃ and I₄ and which are compressed from a logarithmic standpoint. The voltages V₃ and V₄ thus logarithmic-compressed are respectively supplied to the bases of the transistors Q1, Q4 and to the bases of the transistors Q2, Q3 so that the collector currents of the transistors Q1, Q4 and of the transistors Q2, Q3 are linearly changed in accordance with the currents I₃ and I₄, respectively. The collector currents of the transistors Q1, Q2 and of the transistors Q3, Q4 are also changed linearly in response to their emitter currents I₂ and I₂, respectively, so that the transistors Q1, Q2 and Q3, Q4 generate at their collectors a pair of linear multiplied output currents I₅ and I₆, respectively. Such currents I₅ and I₆ are stereo demodulated outputs, or signal currents corresponding to the signals L and R. More specifically, the currents I₁, I₂ are changed in accordance with the currents I₃, I₄ so that if the ratio (multiplication gain) in which the I₅ and I₆ are changed in accordance with the currents I₃ and I₄ is, for the sake of simplicity, selected to be one multiple, the following equations are established: Starting from I₃ = (1 + Asinωt) Iy I₄ = (1 - Asinωt) Iy the currents I₅ and I₆ become: I₅ = ½ (1 + Asinωt) I₁ + 171 (1 - Asinωt) I₂ I₆ = ½ (1 + Asinωt) I₁ + 171 (1 - Asinωt) I₂ The above equations (5) and (6) lead to This current I₅ is supplied to the low pass filter 9L (shown in figure 1) which removes its undesired high band component, so that the low-pass filter 9L provides an output current I L expressed as Similarly, the output current I R of the low-pass filter 9R is represented as I R = I x + 2(1 -γ) + A(1 +γ) 4 R + 2(1 -γ) - A(1 +γ) 4 L If the numerators of the third team in equations (8) and (9) for the currents I L and I R are zero, or if the following equation is established 2 (1 -γ) - A (1 +γ) = 0 A = 2 (1 -γ)/(1 +γ), this yields I L = I x + (1 -γ) L I R = I x + (1 -γ) R It is thus possible to obtain the stereo demodulated outputs I L and I R without any cross-talk component. Further, these stereo demodulated outputs I L and I R do not contain a beat interference component. It will be apparent from the foregoing that if the magnitude of the ratio "A" is changed, then the levels of cross-talk components in the demodulated outputs I L and I R are also changed. As earlier noted, the value "A" represents the ratio of the current of the signal S o relative to the direct current components in the currents I₃ and I₄. In other words, in the currents I₃ and I₄, the ratio "A" between the direct current components and the alternating current component sinωt has to be made constant. To this end, as described above, the level of the oscillation signal S o is detected by the detecting circuit 21 and the level or amplitude of the oscillation signal S o is controlled on the basis of the detected output from the detecting circuit 21. Figure 3 (formed of figures 3A and 3B together) illustrates specific examples of the detecting circuit 21 and the VCO 13 that may be used in the circuit of figure 1. More specifically, in the detecting circuit 21 of figure 3, the bases of transistors Q21 and Q22 are respectively connected to the bases of transistors Q12 and Q14 and the emitters thereof are grounded. Resistors R1 and R2 having equal resistance values are connected between the collectors of the transistors Q21 and Q22, respectively, and the terminal T1. Resistors R3 and R4 also having equal resistance values are serially connected between the collectors of the transistors Q21 and Q22, and a resistor R5 is connected between the junction point of the resistors R3 and R4 and the terminal T1. The emitters of transistors Q23 and Q25 are connected together to a constant source A5 which has the ground as its reference potential point. Resistors R6 and R7 which have equal resistance values are connected between the collectors of the transistors Q23 and Q25, respectively, and the terminal T1, thereby providing a differential amplifier A6. Also, the collector-emitter path of a transistor Q24 is connected in parallel to the collector-emitter path of the transistor Q23 so as to form a full-wave rectifying circuit 52 of a differential amplifier circuit arrangement. The bases of the transistors Q23 and Q24 are connected to the collectors of the transistors Q21 and Q22, and the base of the transistor Q25 is connected to the junction point of the resistors R3 to R5. A bias voltage V B is applied to the bases of transistors Q26 and Q27 with the voltage of the terminal T1 being taken as the reference potential point so that the transistors Q26 and Q27 are base-grounded. The emitters of the transistors Q26 and Q27 are connected to the collectors of the transistors Q23 and Q25, respectively, and the collectors of the transistors Q26 and Q27 are connected to the collectors of the transistors Q28 and Q29, respectively. The transistors Q28 and Q29 constitute a current mirror circuit A7 in which the transistor Q28 is made the input side and the reference potential point is the ground. A resistor R8 is connected between the collectors of the transistors Q26 and Q27 for adjusting the current gain of the current mirror circuit A7. The output currents of the detecting circuit 21 are derived from the connected together collectors of the transistors Q27 and Q29. In the VCO 13 shown on figure 3, the collector-emitter path of a constant current source transistor Q33 is connected between the connected-together emitters of transistors Q31 and Q32 and ground, thereby to provide a differential amplifier A8. The collector of transistor Q31 is connected to the terminal T1, and the base of transistor 31 is connected to the collector of the transistor Q32. A parallel resonant circuit 53 is connected between the collector of the transistor Q32 and the terminal T1, and the base of the transistor Q32 is connected to the terminal T1. The transistor Q32 generates, at its collector, the oscillation signal S o which is then fed through the buffer amplifier 14 to the converting circuit 42. To the resonant circuit 53, there is connected an equivalent variable capacitor C₃ which utilises, for example, the Miller effect. The output voltage of the low-pass filter 12 is supplied to the variable capacitor C₃ as the control voltage for the latter. The transistor Q33 forms a current mirror circuit A9 in which the transistor Q33 is the input side transistor and the reference potential point is grounded. Further, the collector of a transistor Q34 is connected with a constant current source A10 in which the terminal T1 is used as the reference potential point. The collectors of the transistors Q27 and Q29 are connected together to the base of a transistor Q41 which has its collector connected to the base of a transistor Q42 whose emitter is connected to the terminal T1. A capacitor C₄ is connected between the collector of the transistor Q42 and the ground. The collector of the transistor Q42 is further connected to the base of a transistor Q43 whose emitter is grounded. The collector of the transistor Q43 is connected to the collector of the transistor Q34. In the above described arrangement, the transistors Q21 and Q22 are respectively supplied at their collectors with currents I′₃ and I′₄ proportional to the currents I₃ and I₄ from the collectors of the transistors Q12 and Q14, for example, the current I′₃ and I′₄ may be of the same magnitude as currents I₃ and I₄, respectively, whereby voltages E₃ and E₄ linearly proportional to the currents I₃ and I₄ are obtained at the collectors of the transistors Q21 and Q22 by the resistors R1 and R2. At that time, there are established the equations I₃ = (1 + Asinωt) Iy I₄ = (1 - Asinωt) Iy Thus, as shown in figure 4, the voltages E₃ and E₄ have a direct current component E o and alternating current components e which are opposite to each other in phase. The direct current component E o is expressed as E o = Iy R1 (R3 + 2R5)/(R1 + R3 + 2R5) Further, since the alternating current components e of the voltages E₃ and E₄ are opposite to each other in phase, only the direct current components of the voltages E₃ and E₄, divided by the resistors R3 and R5, are developed at the junction point of the resistors R3 to R5, and the resultant direct current voltage E₅ is expressed as E₅ = 2Iy R1 R5/(R1 + R3 + 2R5) The above mentioned direct current voltage E₅ is supplied to the base of the transistor Q25 and the voltages E₃ and E₄ are supplied to the bases of the transistors Q23 and Q24 so that, as shown in figure 4, the voltages E₃ and E₄ are compared with the voltage E₅. Thus, the differential amplifier A6 generates the portions of the voltages E₃ and E₄ greater than the voltage E₅, that is, E₃ > E₅ and E₄ > E₅ Further, when the oscillation level of the VCO 13 is larger than a predetermined level, the alternating current components of the currents I₃ and I₄ are large. Accordingly, E₃ (E₄) > E₅ is satisfied near the positive peak points of the voltages E₃ and E₄ with the result that a collector current I₇, which is the sum of the collector currents of the transistors Q23 and Q24, becomes larger than the collector current I₈ of the transistor Q25. As a result, the emitter current of the transistor Q26 is decreased and the emitter current of the transistor Q27 is increased. In such case, the emitter current of the transistor Q26 is made equal to the collector current of the transistor q29 by the current mirror circuit A7, whereby the collector current of the transistor Q29 is decreased. Hence, a current which is the difference between the collector current (large) of the transistor Q27 and the collector current (small) of the transistor Q29 is supplied to the base of the transistor Q41. Consequently, the collector current of the transistor Q41 is increased and the collector current of the transistor Q42 is also increased whereby the collector current of the transistor Q43 is increased, thereby decreasing the collector current of the transistor Q34. Thus, the collector current of the transistor Q33 is decreased for decreasing the oscillation level of the VCO 13. Since the voltages E₃ and E₄ contain the alternating current component e having the frequency f , the currents of the respective portions, which are the results of comparing the voltages E₃ and E₄ with the voltage E₅, are intermittently generated at the period of frequency 2f. In this case, the collector current of the transistor Q42 is smoothed by a capacitor C₄ so that the collector currents flowing to the transistors Q43, Q34 and Q33, respectively, become direct currents with the levels thereof corresponding to the results of comparing the voltages E₃, E₄ with the voltage E₅. When the oscillation level of the VCO 13 is less than the predetermined level, that is, E₃ (E₄) < E₅ even at the positive peak points of the voltages E₃ and E₄, the relation I₇ < I₈ is established. Thus, the collector current of the transistor Q27 is decreased while the collector current of the transistor Q26 is increased, thereby increasing the collector current of the transistor Q29. As a result, the base current of the transistor Q41 is reduced to zero, thereby turning off the transistor Q41. Consequently, the transistor Q24 is turned off and the transistor Q43 is turned off, whereby the collector current of the transistor Q34 is increased to a value determined by the constant current source A10, and the collector current of the transistor Q33 is increased similarly. As a result of the foregoing, the oscillation level of the VCO 13 is increased. If the loop gain of the control loop for the oscillation level is sufficiently large, the oscillation level of the VCO 13 is controlled so that the levels of the voltage E₃ and E₄ at the positive peak points are equal to the level of the voltage E₅, as shown in figure 4. The oscillation is thereby stabilised at that oscillation level. At that time, and as is apparent from figure 4, e = E o - E₅ Substituting the expressions for E o and E₅ from equations (12) and (13), the above equation (14) yields: Consequently, the ratio A is expressed as A = alternating current components of I₃, I₄/direct current components of the currents I₃ and I₄ As described above, the ratio A is determined by the resistance R5 and the ratio of (R1 + R3). When the circuit is fabricated as an integrated circuit (IC), the ratio of these resistors can be determined with high accuracy. Thus, when the above mentioned circuit is fabricated as an integrated circuit, the ratio A becomes the pre-determined value, whereby cross-talk components of the demodulated signals L and R (currents I L and I R ) can be positively removed. As set forth above, in a stereo multiplex demodulator according to an embodiment of the present invention, since the sine wave signal S o synchronised with the pilot signal Sp and having the frequency f is provided and this sine wave signal S o and the composite stereo signal Sc are linearly multiplied to thereby demodulate the stereo signals, it is possible to avoid the appearance in the stereo demodulated outputs L and R of a beat interference component. Further, the circuits and the elements of the demodulator need not be adjusted for that purpose and, therefore, the stereo multiplex demodulator embodying this invention is excellently adapted for mass-production. Moreover, when the stereo multiplex demodulator embodying the present invention is fabricated as an integrated circuit (IC), it does not need any external terminal pins for adjusting the circuit or the elements thereof. Thus, the stereo multiplex demodulator embodying the present invention is ideally suited to be fabricated as an integrated circuit. Furthermore, since the oscillation level of the VCO 13 is stabilised by a feedback control operation, it is possible to avoid the presence of cross-talk components in the stereo demodulated outputs L and R. In addition, adjustment for avoidance of cross-talk is not necessary so that the stereo multiplex demodulator embodying the present invention is thereby yet further suited for mass-production and for fabrication as an integrated circuit. Although a preferred embodiment of the invention has been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to that precise embodiment, and that many modifications and variations thereof could be effected by one with ordinary skill in the art without departing from the scope of the appended claims.

Claims: An analog stereo multiplex demodulator for demodulating left and right channel audio signals from a stereo composite signal (Sc) comprised of a modulated signal having a subcarrier frequency and being balanced-modulated by a signal which is the sum of said left and right channel audio signals and by a signal which is the difference between said left and right channel audio signals and a pilot signal (Sp) synchronised with said modulated signal, said stereo multiplex demodulator comprising: phase-locked loop means (10) for forming a signal (So) synchronised with said pilot signal (Sp) and having a frequency equal to said subcarrier frequency of said modulated signal, the synchronised signal (So) being a sine wave; and analog multiplying means (8) for multiplying said stereo composite signal (Sc) and said sine wave signal (So) so as to generate said left and right channel audio signals; characterised in that: said phase-locked loop means (10) includes a voltage controlled oscillator (13) generating said sine wave signal (So); and by means (21) for detecting the level of said sine wave signal (So) and for correspondingly controlling said voltage controlled oscillator (13) so as to maintain a predetermined constant level of said sine wave signal (So). A stereo multiplex demodulator according to claim 1; in which said phase-locked loop means (10) includes a voltage controlled oscillator (13). A stereo multiplex demodulator according to claim 1 or 2, in which said multiplying means (8) includes current-to-voltage converting means (43) having a logarithmic compression characteristic.

Inventors: OKANOBU TAIWA C O SONY CORPORA, OKANOBU, TAIWA C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1989
Main classification: H03D1
IPC codes: H03L5, H04B1, H04H40, H04H1, H03D1