Integrated circuit comprising logic circuits and at least one push-pull stage

Abstract: Integrated circuit comprising logic circuits and at least one push-pull stage. In order to reduce the magnitude of induction voltages on power supply lines (V DD , V SS ) of the circuit, caused by the current variations in a push-pull stage comprising a push transistor (T₁) and a pull transistor (T₂), in accordance with the invention a first current through one transistor is kept substantially constant until after a most significant rise of a second current through the other transistor when the push-pull stage is switched. A push-pull stage having a less-disturbing switching behaviour can thus be realized without affecting the speed. Aspects of the invention concern the construction of the control means for the push and pull sections of the stage.

Description: The invention relates to an integrated logic circuit with a push-pull stage which comprises, connected in a first path between a first power supply line which carries a high supply voltage and a stage output, a current channel of a push transistor and, connected in a second path between the stage output and a second power supply line which carries a low supply voltage, a current channel of a pull transistor, there being provided control means which are connected to control electrodes of the push transistor and the pull transistor in order to generate, when a logic state of the stage changes, time-dependent control voltages in order to reduce voltage noise on the power supply lines which is caused by current variations on the stage output. Such an IC comprising a push-pull stage is known from Netherlands Patent Application 8601558. The known push-pull stage comprises control means for generating time-dependent control voltages on the control electrodes of the push transistor and the pull transistor in order to reduce voltage noise on the internal power supply lines of the circuit. Due to variations of the load current with which the push-pull stage supplies an output load, induction voltages are generated across inductances present in the power supply lines. The control means control the currents through the push transistor and the pull transistor so that the currents are varied by a constant amount per unit of time during switching. Consequently, the said load current, being the difference between these currents, is also varied by a constant amount per unit of time. When the load current is made to vary linearly in time, the maximum value of the interfering voltages induced thereby is limited. From DE-A-31 14 132 an electronic switch is known, wherein respective signal sources are connected alternately to an output through respective transistors. The switching of the transistors is such that both transistors are simultaneously conductive for a short time period. It is an object of the invention to improve the known push-pull stage by reducing the induction voltages occurring on the power supply lines even further. To achieve this, an integrated circuit in accordance with the invention is characterized in that during the switching of the push-pull stage the control means keep a first current through one transistor of the stage substantially constant until a greatest rise has occurred of a second current through the other transistor of the stage, for substantially instantly thereupon reducing the first current. This results in mutually time shifting of current peak and, accordingly, of maximum current-changes. As a result, the accummulation of inductive voltages is prevented. An embodiment of an integrated circuit in accordance with the invention in which the control means comprise controllable charging paths and discharging paths which are connected to the control electrodes of the push transistor and the pull transistor is characterized in that in its conductive state the discharging path between the control electrode of the pull transistor and the second power supply line conducts a substantially smaller maximum current than the charging path between the first power supply line and the control electrode of the push transistor in the conductive state of said charging path. The push transistor is then fully conductive before a current through the pull transistor can vary substantially; this is due on the one and to the rise of the driving voltage across the pull transistor and on the other hand to the decrease of the control voltage of the pull transistor. A further embodiment of an integrated circuit in accordance with the invention is characterized in that the discharging path for the control electrode of the push transistor comprises a current channel of a discharging transistor, which current channel connects a node between the current channels of the push transistor and the pull transistor to the control electrode of the push transistor. Just before the blocking of the push transistor, a current through this transistor is substantially independent of a voltage across its current channel which is referred to herein as the driving voltage. By thus connecting the control electrode of the push transistor, when this transistor is going to be blocked, to a node between the current channels of the push transistor and the pull transistor via the discharging transistor, during which operation the pull transistor is made conductive, the push transistor initially continues to supply a substantially constant current. This situation changes only when the voltage at said node has dropped so far below the voltage of the control electrode of the discharge transistor that the latter transistor starts to discharge the input of the push transistor. Another embodiment of a push-pull stage in accordance with the invention is characterized in that the control means comprise a control circuit which includes a switching transistor, a current channel of which is connected to the control electrode of the push transistor in series with the relevant charging path, which switching transistor forms an inverter circuit in conjunction with the discharging transistor, the control means comprising a second control circuit which includes a second inverter circuit which has an output connected to the control electrode of the pull transistor and which is formed by a second switching transistor, having a current channel connected between the control electrode of the pull transistor and the relevant charging path, and by a second discharging transistor having a current channel connected between the control electrode of the pull transistor and the second power supply line, the charging paths of the first and the second control circuit each comprising, connected to the second power supply line, a current channel of a respective cascode transistor, a control electrode of which is connected to the output of the respective inverter circuit, and also comprising, connected parallel to the current channel of the respective cascode transistor, a current channel of a respective further cascode transistor, an input of the first and the second inverter circuit being connected, via a first and a second delay element, respectively, to a control electrode of the respective further cascode transistors. The further cascode transistor is made conductive after a delay. Initially this cascode transistor does not influence the voltages in the inverter circuit which generates, as described in the state of the art, a suitable control voltage which ensures a linear variation in time of the currents switched by the transistors of the push-pull stage. The further cascode transistor raises the output voltage of the inverter circuit to the voltage level of the first power supply line only after expiration of a given period of time. In comparison with the state of the art, this is a better way of keeping the current variation in time to be substantially linear. According to the state of the art the further cascode transistor is rendered conductive without delay, so that the said variation of the current in time in the push transistor or the pull transistor is influenced from the very beginning. Another embodiment yet of a push-pull stage in accordance with the invention is characterized in that the discharging path between the control electrode of the pull transistor and the second power supply line comprises at least two parallel paths, a first path of which can be switched off in dependence on a control signal to be applied to the control means while a second path can be switched off in dependence on a voltage on a gate output of a logic gate, gate inputs of which are connected to the control electrode of the pull transistor and to the stage output. For example, in the case of an extremely large capacitive load on the stage output the pull transistor could be blocked prematurely, thus causing large current variations and hence high induction voltages. By switching off a part of the discharging path in these circumstances, a more gradual current variation through the pull transistor is achieved. The invention will be described in detail hereinafter with reference to a drawing; therein: Fig. 1 shows a circuit diagram of a push-pull stage, Figs. 2A and 2B illustrate a current variation in a push-pull stage according to the state of the art, Figs. 3A and 3B show a current variation in a push-pull stage in an integrated circuit in accordance with the invention, Fig. 4 shows a preferred embodiment of a push-pull stage in an integrated circuit in accordance with the invention, and Fig. 5 shows a detail of the push-pull stage in the integrated circuit shown in Fig. 4. Fig. 1 shows a circuit diagram of a push-pull stage. The stage comprises a cascode connection of a push transistor T₁ and a pull transistor T₂ between power supply lines carrying the supply voltages V DD and V SS . The output K of the stage is loaded by, for example, a TTL circuit which is represented in the Figure by resistances R₁ and R₂, connected in series between the power supply lines, and a capacitance C₀ which is connected parallel to the resistance R₂. The stage also comprises a control circuit CC, inputs of which receive logic signals D and D . The transistors T₁ and T₂ are controlled by means of mutually logically complementary control signals. The load current I₀ at all times equals the difference between the current I₁ conducted by the transistor T₁ and the current I₂ conducted by the transistor T₂. For example, when the push transistor T₁ is made conductive and the pull transistor T₂ is blocked substantially simultaneously, the variation of the current I₁ per unit of time amounts to: dI₁/dt, positive, and the variation of the current I₂ per unit of time is: dI₂/dt, negative. The variation of the load current I₀ per unit of time (dI₀/dt) equals the sum of the absolute values of the variations in I₁ and I₂: dI₀/dt = |dI₁/dt| + |dI₂/dt| . On the internal power supply lines, inevitably forming parasitic inductances L₁ and L₂ and being coupled via a parasitic capacitance C p , this current variation dI₀/dt causes a high induction voltage, giving rise to interference (for example, in the logic state of other parts of an integrated circuit in which the push-pull stage is included). Figs. 2A and 2B illustrate the variation in time of the currents I₁ and I₂ and the load current I₀, and their time derivatives, for a circuit according to the present state of the art. When the most significant variations in the currents I₁ and I₂ coincide substantially in time, the variation dI₀/dt generates a maximum induction voltage equal to the sum of the absolute extreme values of dI₁/dt and dI₂/dt. Figs. 3A and 3B illustrate the variation in time of the currents I₁ and I₂ and the load current I₀, and their time derivatives, for a circuit in accordance with the invention. Because the extreme values of dI₁/dt and dI₂/dt have been shifted in time with respect to one another, the maximum induction voltage dI₀/dt is substantially a factor 2 smaller than in the case illustrated with reference to the Figs. 2A and 2B. Fig. 4 shows a preferred embodiment of a push-pull stage in accordance with the invention. A TTL load, represented by resistances R₁, R₂ and a capacitance C₀, is connected to output terminal K of the stage which comprises a push transistor T₁ and a pull transistor T₂. The push transistor T₁ receives a control signal V₁ from a first control circuit INV 1 and the pull transistor T₂ receives a control signal V₂ from a second control circuit INV 2. Both control circuits INV 1 and INV 2 comprise a controllable discharging path which is formed by a transistor T₃ and a transistor T₈, respectively. The function of the transistor T₃, being connected between the control electrode of the pull transistor T₁ and the output terminal K, will be described with reference to Fig. 5. The charging paths of the control circuits INV 1 and INV 2 comprise transistors T₄ to T₇ and T₉ to T₁₂, respectively. Because the charging paths have the same construction, only that of the control circuit INV 1 will be described hereinafter. A similar reasoning applies to the charging path in the control circuit INV 2. Therefore, when reference is made to a component of the control circuit INV 1, a reference to a corresponding component of the control circuit INV 2 is stated between parentheses. The transistor T₄ (T₉) serves as a switch for the transistor T₅ (T₁₀) which is connected as a current source and which has a control electrode connected to the control electrode of the push transistor T₁ (pull transistor T₂). Using this set-up, such a time-dependent control signal V₁ (V₂) is formed that, when the push transistor T₁ (pull transistor T₂) is activated, the current therethrough increases approximately linearly in time. This linear time dependency limits the maximum value of the interference voltages induced by the current variations in the push-pull stage. Because T₅ (T₁₀) is cut off further as the control voltage V₁ (V₂) increases, there is provided a parallel transistor T₆ (T₁₁) which raises the control voltage V₁ (V₂) to the supply voltage V DD after a retardation via the delay DL1 (DL2). Due to the delayed switching-on of the parallel transistor, it initially has no effect on the control voltage variation realized by the transistor T₅ (T₁₀). In ordere to improve the control voltage variation of V₁ (V₂) for a current which varies linearly in time in the push transistor T₁ (pull transistor T₂) when the control voltage V₁ (V₂) approaches the supply voltage V DD , there is provided a non-linear capacitance which is realized by means of the transistor T₇ (T₁₂). Because this capacitance decreases strongly as the control voltage V₁ (V₂) increases beyond a voltage equal to V DD minus a threshold, an excessively low charging current via the transistors T₅ and T₆ (T₁₀ and T₁₁) to the control electrode of the push transistor T₁ (pull transistor T₂) is compensated for in said control voltage interval. In order to enable the current through the pull transistor T₂ to be kept substantially constant when the push transistor T₁ is turned on, the discharging path for the control electrode of the pull transistor T₂, comprising the transistors T₈, T₁₃ and T₁₄, is proportioned with respect to the charging path for the control electrode of the push transistor T₁, comprising the transistors T₄, T₅ and T₆, in such a way, that the maximum discharge current through the former discharging path is a factor from 1.5 to 10 smaller than the maximum charging current through the latter charging path. For a W/L ratio of 535/1.3 for the push transistor T₁ and of 531/1.3 for the pull transistor T₂, it has been found that the following W/L ratios suffice: - T₄ : 80/1.3 - T₅ : 30/1.3 - T₆ : 40/1.3 - T₈ : 2/1.3 - T₁₀ : 14/1.3 - T₁₄ : 14/1.3. It is thus achieved that the push transistor T₁ is already fully conductive before a current through the pull transistor T₂ changes substantially. The pull transistor T₂ then operates in the linear range. The decrease of the control voltage on the control electrode of T₂ and the increase of the driving voltage across the current channel of T₂ oppose one another in as far as the current variation is concerned. The discharging path in INV 2 comprises a first path with transistors T₈ and a second path with transistors T₁₃ and T₁₄. The transistors T₈ and T₁₄ receive the same control signal, the transistor T₁₃ receiving a signal from a logic NAND gate P₁. The gate P₁ fed on the one hand by the control signal for the pull transistor T₂ (V₂) and on the other hand by the output voltage V₀ on the terminal K. For example, if the load capacitance C₀ or the load resistance R₁ were very high, the switching off of the pull transistor T₂ would be too fast when the discharging path is fully conductive, thus causing an excessively large current variation and hence an excessively high induction voltage. This can be avoided by temporary switching off a part of the discharging path. When the control signal V₂ is high and the output voltage V₀ still has a level above a predetermined value, the transistor T₁₃ is blocked via the NAND-gate P₁. The instant of switching on or off of the transistor T₁₃ depends inter alia on a transition point of the gate P₁, the dimensions of the transistors forming the gate, and on a delay DL3, if any, between the gate output of the gate P₁ and the control electrode of the transistor T₁₃. The capacitance T₁₅ serves to achieve gradual switching of the transistor T₁₃. Fig. 5 shows a detail of the push-pull stage shown in Fig. 4. The push transistor T₁ and the pull transistor T₂ are shown, and also the TTL load which is represented by the resistances R₁, R₂ and the capacitance C₀, which load is connected to the output terminal K. Terminals A and B are connected to further parts of the control circuit (not shown). Between the control electrode of the push transistor T₁ and the output terminal K there is formed a discharging path which includes a discharging transistor T₃. Just before the instant of switching off, the push transistor T₁ operates in the saturated state. The current conducted is thus independent of a driving voltage across the current channel. The output voltage V₀ on the output terminal K is then high. The switching off of the push transistor T₁ is preceded by the switching on of the pull transistor T₂, the uncoupling of the terminal A from the remainder of the control circuit, and the activation of the further transistor T₃ by means of a high voltage. Via the terminal E the further transistor T₃ is driven to full output when the push transistor T₁ is switched off; because the output voltage V₀ is still high at that instant, the further transistor T₃ will operate beyond or near its treshold voltage, which implies that the control electrode of the push transistor T₁ is not discharged or only hardly so. During the decreasing of the output voltage V₀, the push transistor T₁ remains saturated and delivers a constant current. It is only when the output voltage V₀ has decreased sufficiently far that the further transistor T₃ starts to conduct so that the control electrode of the push transistor T₁ is discharged further.

Claims: An integrated logic circuit with a push-pull stage comprising: a push transistor (T1) having a current channel arranged between a first power supply line for carrying a high supply voltage (VDD) and a stage output (K); a pull transistor (T2) having a current channel arranged between the output (K) and a second power supply line for carrying a low supply voltage (VSS); control means (CC) for supplying to a control electrode of the push transistor (T1) and to a control electrode of the pull transistor (T2) time-dependent control voltages in order to switch logic states of the push pull stage and in order to reduce voltage noise on the supply lines due to current variations at the stage output (K); characterized in that, during the switching of the logic states, the control means (CC) keep a first current (I1 or I2, respectively) through one of said transistors (T1 or T2, respectively) substantially constant until a greatest rise has occurred in a second current (I2 or I1, respectively) through the other one of said transistors (T2 or T1, respectively), for substantially instantly thereupon reducing the first current (I1 or I2, respectively). An integrated logic circuit as in claim 1, wherein the control means (CC) comprises a discharging path (T8, T13, T14) being arranged between the control electrode of the pull transistor (T2) and the second power supply line, and a charging path (T4, T5, T6) being arranged between the control electrode of the push transistor (T1) and the first power supply line, characterized in that, the discharging path (T8, T13, T14) conducts a smaller maximum current when conductive than does the charging path (T4, T5, T6) when conductive. An integrated logic circuit as in claim 2, characterized in that a ratio between the maximum current conducted by the charging path (T4, T5, T6) and the maximum current conducted by the discharging path (T8, T13, T14) lies in a range of 1,5 to 10. An integrated logic circuit as in claim 2 or 3, characterized in that the control means (CC) comprises a further discharging path for discharging the control electrode of the push transistor (T1), said further discharging path comprising a current channel of a discharging transistor (T3) that connects the control electrode of the push transistor (T1) to a node (K) between the current channel of the push transistor (T1) and the current channel of the pull transistor (T2). An integrated logic circuit as in claim 4, characterized in that the control means (CC) comprises a control circuit (INV1) wherein, in the charging path (T4, T5, T6), a current channel of a switching transistor (T4) is connected to the control electrode of the push transistor (T1), the switching transistor (T4) forming an inverter circuit in conjunction with the discharging transistor (T3). An integrated logic circuit as in claim 5, wherein the control means (CC) comprises a second control circuit (INV2) which includes a second inverter circuit (T8, T9) that has an output connected to the control electrode of the pull transistor (T2) and that is formed by a second switching transistor (T9), with a current channel connected to the control electrode of the pull transistor (T2) and arranged in a charging path (T9, T10, T11) for the control electrode of the pull transistor (T2), and by a second discharging transistor (T8), with a current channel connected between the control electrode of the pull transistor (T2) and the second power supply line; and wherein the charging paths (T4, T5, T6; T9, T10, T11) in each of the first and second control circuits (INV1 and INV2) comprises a respective cascode transistor (T5; T10), having a current channel connected to the first power supply line and having a control electrode connected to an output of the respective inverter circuit (T3, T4; T8, T9), and comprises a respective further cascode transistor (T6; T11), having a current channel connected in parallel to the current channel of the respective cascode transistor (T5; T10); characterized, in that inputs of the first and second inverter circuits (T3, T4; T8, T9) are connected, respectively, to a control electrode of the respective further cascode transistor (T6; T11) via a first and a second delay element (DL1; DL2), respectively. An integrated logic circuit as in claim 2, 3, 4, 5 or 6, characterized in that the discharging path (T8, T13, T14) between the control electrode of the pull transistor (T2) and the second power supply line comprises a parallel arrangement of at least a first and a second path, the first path (T8) being turned off depending on a control signal supplied to the control means (CC) and the second path (T13, T14) being turned off under control of a voltage at a gate output of a logic gate (P1), the logic gate (P1) having a first gate input connected to the control electrode of the pull transistor (T2) and a second gate input connected to the stage output (K). An integrated logic circuit as in claim 7, characterized in that a further delay element (DL3) is connected between the gate output and a control electrode of a specific transistor (T13) that has a current channel arranged in the second path (T13, T14). An integrated logic circuit as in claim 8, characterized in that the control electrode of the specific transistor (T13) is coupled to the second power supply line via a further capacitance (T15).

Inventors: DIKKEN JAN, DIKKEN, JAN
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1989
Main classification: H03K17
IPC codes: H03K19, H03K17