Power supply switching circuit

Abstract: A circuit is disclosed which comprises first to third MOS transistors (Pl, P2 and P3) connected in series between a high-potential source (or a low-potential source) and a standard-potential source, performs a switching operation using a standard potential (V PP ) and at least one kind of potential which is different from the standard potential, and outputs plural power supply potentials. The third MOS transistor (P3) is inserted between the first and second MOS transistors (P1 and P2), the back gate of the third transistor (P3) is connected to an output terminal (OUT1) formed between the second transistor (P2) and the third transistor (P3) and prevents the formation of a current path via the turned-­ off transistor (P1) by the action of a parasitic diode (D1) in the first and second transistors due to potential fluctuations.

Description: The present invention relates to a power supply switching circuit, especially for use in LSI circuit. In a LSI circuit comprising an EPROM or the like, it is necessary to apply a potential (V pp ) which is higher than a power supply potential (V DD ) for writing while in a write mode, and to use a standard potential and a potential which is higher than the standard potential as power supplies. These potentials have to be switched on demand. Heretofore, a circuit for switching power supplies as described above is known which is shown in Figure 4. The conventional power supply switching circuit which is capable of switching the potential of an output terminal OUT1 between a first potential (V pp ) and a second potential (V DD ) in accordance with a control signal supplied to an input terminal IN1, comprises a level shifter 8 connected to the input terminal IN1; an inverter P4, N5 also connected to the input terminal IN1; a first P-channel MOS transistor P1 having its source connected to the first potential (V pp ), its gate connected to an output of the level shifter 8 and its backgate connected to its source; and a second P-channel MOS transistor P2 having its drain connected to the second potential (V DD ), its gate connected to an output of the inverter P4, N5 and its backgate connected to its source, to which also the drain of the first P-channel MOS transistor (P1) is connected. The output terminal OUT1 is connected to the node 6 formed by the drain of the first P-channel MOS transistor P1 and the source of the second P-channel MOS transistor P2. In other words, this conventional circuit includes the first p-channel MOS transistor P1 and the second p-channel MOS transistor P2 which are connected in series. A high potential V pp is supplied from IN2 to the source of the first p-channel MOS transistor P1, and a standard potential V DD is supplied from a terminal 10 to the drain of the second p-channel MOS transistor P2. The input terminal IN1, to which control signals are input, is connected to the input of a level shifter 8, to which the gate of the first p-channel MOS transistor P1 is connected. The input terminal IN1 is also connected to the gate of the inverter circuit 7 which comprises a p-channel MOS transistor P4 and an n-channel MOS transistor N5. The output terminal OUT1 is connected to the connection point of the drain of the first MOS transistor and the source of the second MOS transistor, and grounded at GND0 via the p-channel MOS transistor P4 and the n-channel MOS transistor N5. The gate of the second MOS transistor P2 is connected to a connection point of the p-channel MOS transistor P4 and the n-channel MOS transistor N5. In the following the operation of this power supply switching circuit of the prior art will be explained. An input signal is applied to the input terminal IN2 at the potential level V pp which is higher than the standard potential (V DD ). The level shifter 8 is inserted for completely 5 turning off the first p-channel MOS transistor P1 when the level "V DD " is input to the input terminal IN1, and is a circuit which outputs the level IN2 when the level "V DD " is input to the input terminal IN1, and outputs the level "GND" when the level "GND" is input. First, when the level "GND" is input to the input terminal IN1, the level "GND", which is an output of the level shifter 8, is applied to the gate of the first p-channel MOS transistor P1, and the first p-channel MOS transistor P1 is turned on. Accordingly, the connection point 6 (node) of the drain of the first MOS transistor P1 and the source of the second MOS transistor P2 assumes level "V pp ". Furthermore, since ground potential is applied to the gate of the n-channel MOS transistor N5 of the inverter 7 connected to the input terminal IN1, the n-channel MOS transistor N5 is turned off. Ground potential is also applied to the gate of the p-channel MOS transistor P4 connected to the input terminal IN1, and since the node 6 is at level "V pp ", the p-channel MOS transistor P4 is turned on. The gate of the second MOS transistor P2 assumes level "V pp " via the turned-on p-channel MOS transistor P4, and the second MOS transistor P2 is completely turned off. Consequently, the level "V pp " is output from the output terminal OUT1. When the level "V DD " is input to the input terminal IN1, the level "V pp ", which is an output of the level shifter 8, is applied to the gate of the first p-channel MOS transistor P1, and the first p-channel MOS transistor P1 is turned off. Furthermore, since the level "V DD " is applied to the gate of the n-channel MOS transistor N5 of the inverter 7 connected to the input terminal IN1, the n-channel MOS transistor N5 is turned on. The gate of the second p-channel MOS transistor P2 then assumes ground potential, and the second p-channel MOS transistor P2 is turned on. Hence, the node 6 assumes level "V DD ". Since the gate and the source of the p-channel MOS transistor P4 are both at level "V DD ", the p-channel MOS transistor P4 is turned off. Hence, the level "V DD " of the node 6 is output as it is from the output terminal OUT1. As described above, in the power supply switching circuit of the prior art shown in FIG. 4, the level "V pp " is output when the level "GND" is input to the input terminal IN1, and the level "V DD " is output from the output terminal OUT1 when the level "V DD " is input to the input terminal IN1. When a potential applied to the high-potential input terminal IN2 is at a level equivalent to or higher than the level "V DD ", no forward-direction bias is applied to a parasitic diode D1 which exists between a source diffusion region (p-type) and an n-well of the first p-channel MOS transistor P1 as shown in FIG. 5, and so no current flows. However, when a potential applied from the input terminal IN2 is lower than the level "V DD ", although the first p-channel MOS transistor P1 is turned off, a forward-direction bias is applied to the parasitic diode D1. Hence, a current path is formed between the V DD and the IN2 via the first and second p-channel MOS transistors P1 and P2, and the output level from the output terminal OUT1 decreases. Since there exists the above-described inconvenience when a potential applied from the input terminal IN2 is lower than the level "V DD ", a high-potential input signal and other input signals can not use the terminal IN2 in common, and it is necessary to provide exclusive terminals for respective inputs. The present invention has been made on the basis of the above-described background. It is an object of the present invention to provide a power supply switching circuit in which an input terminal can be used in common for other input signals, in a semiconductor device, such as a CMOS·LSI and the like, having inputs of many potential levels. After performing research and development for solving the above-described problems, the inventor has found that, by further providing a third MOS transistor between a first MOS transistor and an output terminal OUT, the third MOS transistor is turned off even when a potential applied from an input terminal is lower than the level "V DD ", a reverse bias is applied to a parasitic diode to suppress the above-described conduction and securely maintain an output level from the output terminal OUT without decreasing the level, and it is possible to use the input terminal in common for other input signals, and thus completed the present invention. A power supply switching circuit capable of switching the potential of an output terminal OUT1 between a first potential (V DD ) and a second potential (V pp ) in accordance with a control signal supplied to an input terminal IN1 comprises a level shifter 8 connected to said input terminal IN1; an inverter P4, N5; N4, P5 connected to said input terminal IN1; a first MOS transistor P1, N1 having its source connected to said first potential V pp its gate connected to an output of said level shifter 8 and its back gate connected to its source; a second MOS transistor P2, N2 having its drain connected to said second potential V DD , its gate connected to an output of said inverter P4, N5; N4, P5 and its back gate connected to its source; a third MOS transistor P3, N3 having its source connected to the drain of said first MOS transistor P1, N1, its drain connected to the source of said second MOS transistor P2, N2, its gate connected to said input terminal IN1, and its back gate connected to its drain; and an output terminal OUT1 connected to the junction point of the second and third MOS transistors wherein the first potential V pp and the second potential V DD are different from each other. In a preferred aspect of the present invention, the first, second and third MOS transistors may be p-channel transistors, and a high potential may be supplied to the source of the first MOS transistor. In the aspect of providing p-channel transistors and supplying a high potential to the source of the first MOS transistor, a gate signal of the second MOS transistor may be made an output signal of an inverter comprising MOS transistors in which an output is from a source. Furthermore, in the aspect of providing p-channel transistors and supplying a high potential to the source of the first MOS transistor, a gate signal of the first MOS transistor may be supplied from a level shifter which outputs a high potential or a ground potential. In another aspect of the present invention, the first, second and third MOS transistors may be n-channel transistors, and a low potential may be supplied to the source of the first MOS transistor. The function of the power supply switching circuit according to the present invention will be schematically explained. In the power supply switching circuit of the present invention, the third MOS transistor is newly provided between the first and second MOS transistors. That is, the third MOS transistor is provided between the first MOS transistor and the output terminal OUT. Hence, the third MOS transistor is turned off even when a potential applied from the input terminal is lower than the level "V DD " of the standard potential, and a reverse bias is applied to a parasitic diode which exists between a source diffusion region and an n-well of the third MOS transistor to suppress conduction between the standard potential and the input terminal. In the following the present invention will be explained in further detail with reference to the drawings. FIG. 1 is a circuit configuration diagram showing an embodiment of a power supply switching circuit according to the present invention; FIG. 2 is an explanatory diagram of the circuit shown in FIG. 1; FIG. 3 is a circuit configuration diagram showing a modified example of a power supply switching circuit according to the present invention; FIG. 4 is a circuit configuration diagram showing an example of a power supply switching circuit of the prior art; and FIG. 5 is an explanatory diagram for explaining disadvantages of the circuit example shown in FIG. 4. FIG. 1 is a circuit configuration diagram of an embodiment according to the present invention, and FIG. 2 is a circuit configuration diagram for explaining the function of the circuit of the embodiment. A power supply switching circuit of the embodiment comprises a first MOS transistor P1 and a second MOS transistor P2 which are connected in series, and a third MOS transistor P3 between the first and second MOS transistors P1 and P2. The drain of the first MOS transistor P1 is connected to the source of the third MOS transistor P3, the source of the second MOS transistor P2 is connected to the drain of the third MOS transistor P3, and the back gate of the third MOS transistor is connected to an output OUT1. A connection point 6 of the drain of the third MOS transistor P3 and the source of the second MOS transistor P2 is made the output OUT1, a high potential V pp is supplied to the source of the first MOS transistor P1, and a standard potential V DD is supplied to the drain of the second MOS transistor P2. Accordingly, the output OUT1 is connected to IN2 via the transistors P3 and P1, to a standard potential V DD 10 via the transistor P2, and also to GND0 via transistors P4 and N5 which constitute an inverter circuit 7. On the other hand, an input terminal IN1 for control signals is connected to the input of a level shifter 8, to the gate of the third p-channel MOS transistor P3, and also to the gate of the inverter circuit comprising the transistors P4 and N5. Furthermore, the gate of the first p-channel MOS transistor P1 is connected to the output of the level shifter 8, and the gate of the second p-channel MOS transistor P2 is connected to a connection point of the p-channel MOS transistor P4 and the n-channel MOS transistor N5. The level shifter 8 is inserted for completely turning off the first p-channel MOS transistor P1 when the level "V DD " is input to the input terminal IN1, and is a circuit which outputs the level IN2 when the level "V DD " is input to the input terminal IN1, and outputs the level "GND" when the level "GND" is input. Next, the operation of the circuit of the embodiment according to the present invention will be explained. When a potential "V pp " which is not lower than the level "V DD " is applied to the IN2, the operation is as follows. First, when a potential of the level "GND" is applied to the IN1, the gates of the first p-channel MOS transistor and the third p-channel MOS transistor P3 both assume ground potential, both transistors are turned on, and the node 6 assumes "V pp ". At this time, since a potential of the level "GND" is applied to the gate of the n-channel MOS transistor N5, the transistor N5 is turned off. Since a potential of the level "GND" is also applied to the gate of the p-channel MOS transistor P4, and the node 6 is at the level "V pp ", the transistor P4 is turned on. The gate of the second p-channel MOS transistor P2 assumes potential "V pp ", and the transistor P2 is completely turned off. Hence, the level "V pp " is output at the output terminal OUT1. Next, when the level "V DD " is applied to the IN1, the gate of the first p-channel MOS transistor P1 assumes level "V pp ", and the transistor P1 is turned off. Since the gate of the n-channel MOS transistor N5 assumes level "V DD ", the transistor N5 is turned on, and since the gate of the second p-channel MOS transistor P2 assumes level "GND", the second p-channel MOS transistor P2 is turned on. Hence, the node 6 assumes level "V DD ". At this time, since both the gate of the p-channel MOS transistor P4 and the node 6 assume level "V DD ", the transistor P3 is turned off. Furthermore, since both the gate of the third p-channel MOS transistor P3 and the node 6 assume level "V DD ", the third p-channel MOS transistor P3 is turned off. Hence, a potential of the level "V DD " is output at the OUT1. A case in which a potential which is lower than the level "V DD " is applied to the IN1 will be hereinafter explained with reference to FIG. 2. When a potential of the level "V DD " is applied to the IN1, the gate of the n-channel MOS transistor N5 assumes level "V DD ", the transistor N5 is turned on, and the gate of the second p-channel MOS transistor P2 assumes level "GND". Hence, the second p-channel MOS transistor P2 is turned on. Consequently, the node 6 assumes level "V DD ", and since the gate of the transistor P4 is at the level "V DD ", the transistor P4 is turned off. In this aspect, the gate of the third p-channel MOS transistor P3 is at the level "V DD ", the transistor P3 is turned off. Furthermore, since a potential which is lower than the level "V DD " is applied to the IN2, and the node 6 is at the level "V DD ", a parasitic diode D2 which exists between a source diffusion region (p-type) and n-well of the transistor P3 is reverse-biased, and the transistor P3 is not conducting. Hence, irrespective of the condition of the MOS transistor P1, it is possible to interrupt by the transistor P3 a current path between the 5 level "V DD " 10 of the standard potential and the high-potential input terminal IN2 via the transistors P1, P3 and P2. Accordingly, it becomes possible to suppress a decrease in the output level at the output terminal OUT1 which is a disadvantage of the conventional power supply switching circuit, and to securely output the level "V DD " at the OUT1. The present invention can also be applied when a low potential, such as a negative power supply or the like, is used instead of a high-potential power supply. As an example thereof, p-channel and n-channel transistors may be replaced by n-channel and p-channel transistors, respectively, as shown in FIG. 3. Furthermore, the level shifter 8 may be of any type provided that it can completely turn off the first MOS transistor P1. The third MOS transistor P3 may-also have an arbitrary structure, provided that it effectively interrupts a current path between the level "V DD " 10 of the standard potential and the high-potential or low-potential input terminal IN2. The power supply switching circuit of the present invention has the following effects. In a power supply switching circuit according to claim 1, a third MOS transistor is provided between a first MOS transistor and an output terminal OUT. Hence, the third MOS transistor is turned off even when a potential applied from an input terminal IN2 is lower than the level "V DD " of a standard potential. Furthermore, a reverse bias is applied to a parasitic diode which exists between a source diffusion region and an n-well of the third MOS transistor to suppress a current path between the standard potential and the input terminal. Accordingly, it makes it possible to securely output the level "V DD " at the OUT1, even when the potential applied from the input terminal is lower than the level "V DD " of the standard potential. Although an exclusive terminal for applying a high potential is necessary in a conventional circuit, an input terminal for the high-potential level "V pp " and other input terminals for different potentials can be used in common in a power supply switching circuit. Hence, the present invention is effective in reducing the number of pins. The present invention can also be applied when a low potential, such as a negative potential and the like, is used, and an input terminal for a low potential level and other input terminals for different potentials can be used in common. Hence, the present invention is similarly effective in reducing the number of pins.

Claims: A power supply switching circuit capable of switching the potential of an output terminal (OUT1) between a first potential (V pp ) and a second potential (V DD ) in accordance with a control signal supplied to a input terminal (IN1) comprising a level shifter (8) connected to said input terminal (IN1); an inverter (P4, N5; N4, P5) connected to said input terminal (IN1); a first MOS transistor (P1, N1) having its source connected to said first potential (V pp ), its gate connected to an output of said level shifter (8) and its back gate connected to its source; a second MOS transistor (P2, N2) having its drain connected to said second potential (V pp ), its gate connected to an output of said inverter (P4, N5; N4, P5) and its back gate connected to its source; a third MOS transistor (P3, N3) having its source connected to the drain of said first MOS transistor (P1, N1), its drain connected to the source of said second MOS transistor (P2, N2), its gate connected to said input terminal (IN1), and its back gate connected to its drain; and an output terminal (OUT1) connected to the junction point of the second and third MOS transistors wherein the first potential (V pp ) and the second potential (V DD ) are different from each other. A power supply switching circuit according to claim 1, wherein said first, second and third MOS transistors (P1, P2, P3) are p-channel transistors, both the first and the second potentials (V pp , V DD ) being positive and the latter being lower than the former. A power supply switching circuit according to claim 2, wherein said inverter comprises a p-channel MOS transistor (P4) having its source connected to said output terminal (OUT1) and its gate connected to said input terminal (IN1) and a n-channel MOS transistor (N5) having its drain connected to the drain of said p-channel MOS transistor (P4) and the gate of said second MOS transistor (P2), its source connected to a ground potential (GND0) and its gate connected to said input terminal (IN1). A power supply switching circuit according to claim 1, wherein said first, second and third MOS transistors (N1, N2, N3) are n-channel transistors, both the first and the second potentials (V pp , V DD ) being negative and the latter being higher than the former. A power supply switching circuit according to claim 4, wherein said inverter comprises a n-channel MOS transistor (N4) having its source connected to said output terminal (OUT1) and its gate connected to said input terminal (IN1) and a p-channel MOS transistor (P5) having its drain connected to the drain of said n-channel MOS transistor (N4) and the gate of said second MOS transistor (N2), its source connected to a ground potential (GND0) and its gate connected to said input terminal (IN1). A power supply switching circuit according to one of the preceding claims, wherein said level shifter (8) outputs said first potential (V pp ) when said second potential (V DD ) is supplied to said input terminal (IN1).

Inventors: ABE ISAO, MURATA HIROYOSHI TOSHIBA SHINK, SUZUKI YASOJI, TAKIBA AKIRA B- TOSHIBA HIYOSH, ABE, ISAO, MURATA, HIROYOSHI 503, TOSHIBA SHINKOYASU, SUZUKI, YASOJI, TAKIBA, AKIRA B-112, TOSHIBA HIYOSHI RYO
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1989
Main classification: H03K17
IPC codes: H03K17