Memory for programmable digital filter

Abstract: The filter comprises an arithmetical chain of parallel adders (30, 32...34) alternated with delay elements (40, 42) and a memory constituted by a plurality of lines (12...20) of a plurality of one-bit cells, each being addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory furthermore comprises a number of read amplifiers (22) which is equal to the number of cells of one line in order to read the bits of the addressed line, and the outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. According to the invention, each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic, and the output of each read amplifier corresponding to the most significant bit of each value is connected to the corresponding input bit line of the associated adder and to all the other most significant input bit lines.

Description: The present invention relates to a memory for programmable digital filter for wide-band electronic signals, particularly video signals, and more particularly the invention relates to an EPROM memory which can be used to implement a digital filter of the non-recursive type with finite impulse response (FlR) of the kind described in the antedated patent application No. 22890-A/88 in the name of the same Applicant, entitled "Programmable Digital Filter", filed on December 6, 1988. Said antedated patent relates to a digital filter of the kind with a transposed canonical structure, wherein an array of multipliers provides partial products of the digital signal to be filtered by successive coefficients of the filter's impulse response. The antedated patent replaces said multipliers with tables of pre-calculated partial products contained in one or more re-programmable memories, and each memory cell contains the partial product of an associated stage which corresponds to the value to be processed which coincides with the address of said cell. In particular, said antedated patent uses a single memory which contains, in each line, all the partial products between the address of that line and all the coefficients from h₀ to h T , T being the overall number of coefficients of the filter. The line is transmitted in parallel to the arithmetical block of the filter by means of a bank of read amplifiers which are equal in number to the length of the memory line. However, though the use of a table thus defined instead of multipliers offers advantages in terms of operating speed, simplicity of implementation etc., as the precision of the coefficients of the filter rises, the dimensions of the memory also grow in a linear manner together with the number of read amplifiers, with an increase in silicon area occupation and with a consequent limitation of the performance obtainable from a filter integrated according to a given technology. A FIR digital filter is known from US-A-4,771,395. The known digital filter also includes tables with previously stored data representative of the product between an input signal and the filter coefficients. However, in a similar manner to the previously described table, the table of US-A-4,771,395 also necessitates a large memory. Accordingly, the aim of the invention is to provide a programmable digital filter which has the tabular memory architecture described in said antedated patent application, which requires a smaller memory capacity than said prior filter for an equal equivalent output dynamics and with no complications in the circuits associated with the memory. In a typical application, a digital filter according to the present invention provides in output an equivalent dynamics of 20 word bits with a memory size which would allow a dynamics of only 16 bits in said antedated patent application. Together with the reduction in memory size and therefore in the occupied silicon area, the invention also provides an increase in the filter's processing speed (as required, for example, for video applications) for an equal dynamics, or an increase in dynamics with unchanged speed. The invention achieves the above mentioned aim and other objects and advantages such as will become apparent from the continuation of the description with a programmable digital filter as defined in claim 1. The invention is now described in greater detail with reference to a preferred embodiment thereof, illustrated in the accompanying drawings and given only by way of non-limitative example, wherein: figure 1 is a conceptual block circuit diagram of a programmable FIR digital filter according to said antedated patent application; figure 2 is a plot of the amplitudes of the successive multiplication coefficients from the lowest characteristic to the highest one by which the sampled signal must be multiplied in order to generate the partial products to be added in the arithmetical unit of an FIR filter with transposed canonical structure; and figure 3 is a detail diagram of the connection between the read amplifier and the adder in a filter according to the invention. Figure 1 is the block circuit diagram of a digital FlR filter with transposed structure according to the teachings of the above mentioned antedated patent application in the name of the same Applicant, No. 22890-A/88 entitled "Programmable digital filter". The samples x k of the input signal are fed, with the clock's timing, to a decoder 10 adapted to convert the input word into the selection of one of a plurality of lines 12, 14, 16, ..., 18, 20 of cells of a memory M. The memory has read amplifiers 22 with a number of channels equal to the number of cells which constitute one line; said amplifiers are adapted to allow, in a known manner, the reading of a required memory line. Each line of cells of the memory M comprises a plurality of one-bit cells which store in succession the products of progressive coefficients h₀, h₁, h₂, ..., h T for a value which corresponds to the address of said line. Thus, when a sample x i to be processed is applied to the decoder, the line with address x i will be excited and the output amplifiers will provide the products h₀x i , h₁x i , h₂x i , ... , h T x i . The outputs of the amplifiers are applied in a known manner to respective first parallel inputs of an array of adders 30, 32, ..., 34, and each adder (starting from the one with lowest characteristic) receives on its second input the output of the preceding adder via a respective delay element 40, 42, ..., 44; all of said delay elements have an identical delay T which is equal to a clock period. In this manner, the time required to generate each individual partial product is constant and independent from the characteristics of the operands, and is shorter than the time required by the multipliers used in the circuit of figure 1. The products can furthermore be obtained with arbitrary precision, while any rounding or truncation is performed only on the final result. For a number T of coefficients and an input dynamics of N bits, the filter of the above described kind requires a memory of the following size: 2 N x T x b, where b is the number of bits assigned to the product of the input datum and the coefficient h of the impulse response. Since the described structure requires the transfer of all said products to the arithmetical unit in parallel, T x b read amplifier lines, divided into T buses of b lines, are required. In order to reduce the number of memory cells and therefore the silicon area, as well as the number of read amplifiers, the invention started from the observation that in a typical video filter with a band 0.25-0.50 times the value of the sampling frequency a repetitive decay occurs in passing from one coefficient to the other. With reference to figure 2, which plots the amplitude of the successive coefficients h i of i-th impulse response, the following decay can be observed starting from the central coefficient h₀: a) h₁/h₀ < 0.5 b) h i + 1 /h i < 0.7 (for i > 0) This means that the binary representation of the coefficient loses one significant bit for every 2 increment coefficients in the sequence h₀, h₁, h₂, ..., h T for i > 0. According to the invention, a filter is thus provided which still has the same basic architecture as figure 1 but has successive partial products in each line contained in variable-length words, i.e.: a number b₀ of bits for the central coefficient; a number b₀-1 of bits for the coefficients h₁ and h₂; a number b₀-2 of bits for the coefficients h₃ and h₄; ... a number b₀-T/2 of bits for the last coefficient (where T/2 is rounded down to the nearest integer if T is odd). Since the circuits which are external to the memory (adders, delay elements, and the other registers) assume words of uniform length, it is then necessary to expand the shortened words upon their exit from the memory, inserting the bits which had been eliminated therefrom. Choosing a two's-complement representation of the partial products, it is sufficient to replicate the most significant bit of the word as many times as is required to return the word to the standard length, as illustrated in the partial diagram of figure 3. The number of total non-zero bits required is: N b = b₀ + 2(b₀-1) + 2(b₀-2) + ... + 2(b₀-T/2) where b₀ is the precision of the central coefficient. This relationship is reduced to N b = b₀T - T²/4. This means that if the words are stored with variable lengths, eliminating the redundant bits, a saving of T²/4 one-bit cells for each line is achieved, giving a total of 2 N x T²/4 on the entire memory of 2 N lines. A number T²/4 of read amplifiers is also saved. In a typical application with 16 coefficients, 20-bit dynamics and with N = 8, the total memory required is, according to the given equations: 2 N (b₀T - T²/4) = 65536 bits with a saving of 16384 bits with respect to a standard memorization which would require 81920 bits, therefore with a saving of approximately 25%. The saving of 64 amplifier units (320 to 256) must also be added to this. It can thus be seen that it is possible to achieve a performance which corresponds to 20-bit arithmetics using a memory with an average length of 16 bits with a consequent reduction in area and dissipation. Though the above described calculations are based on the assumption of an even number of coefficients, the saving would be of the same order even with an odd number of coefficients. The concepts of the invention may furthermore be also applied to all the other embodiments of the filter as described in said antedated patent application, such as symmetrical ones with or without central coefficient, asymmetrical ones, etc. The invention is applicable equally well to filters using EPROM, RAM or any other kind of memory. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included just for the sole purpose of increasing intelligibility of the claim and accordingly, such reference signs do not have any limiting effect on the scope of the claim.

Claims: Programmable digital filter comprising an arithmetical chain of parallel adders (30,32,34) alternated with delay elements (40,42,44), and a memory (M) constituted by a plurality of lines (12,14,16,18,20) of a plurality of one-bit cells, each being addressable by a decoder (10) controlled by a digital signal to be filtered, each line (12,14,16,18,20) of memory (M) containing side by side values corresponding to the results of respective partial products of successive impulse response coefficients (h i ) with the instantaneous value of a sampled input signal (x k ) corresponding to the line address, said memory (M) furthermore comprising a number of read amplifiers (22) equal to the number of cells of one line to read the bits of the addressed line, the outputs of said amplifiers (22) being connected to respective parallel inputs of said adders (30,32,34) of said arithmetical chain, characterized in that each memory line (12,14,16,18,20) contains said values in two's-complement binary form in words which decrease in length by one bit for every increment of 2 in the index of said coefficients (h i ) starting from the one with lowest index, and in that the output of each read amplifier (22) corresponding to the most significant bit of each value is connected to a corresponding input bit of the associated adder and also to all input bits of the same adder which are more significant that said corresponding input bit.

Inventors: CAVALLOTTI FRANCO, CREMONESI ALESSANDRO, POLUZZI RINALDO, CAVALLOTTI, FRANCO, CREMONESI, ALESSANDRO, POLUZZI, RINALDO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1989
Main classification: H03H17
IPC codes: H03H17, G11C17, G06F7, G06F17