Method for testing a hierarchically organised integrated circuit device, and integrated circuit device suitable for being so tested

Abstract: A method for testing a hierarchically organized integrated circuit means first attacks each assembly in sequence thereof, and in each assembly executing an assembly test cycle. Each assembly test cycle within the assembly in question attacks each macro thereof in sequence and conditionally executes therein a test run under selective control of a macro test mode (MTM) signal. The number of hierarchy levels may be three or more. The method may be applicable to separate integrated circuits or to a wired board with a plurality of circuits.

Description: FIELD OF THE INVENTION The invention relates to a method for testing one or more integrated circuits, such circuit being built up from various functional blocks hereinafter called macro's. The invention also provides a philosophy for designing integrated circuit means such as integrated circuits and integrated circuit boards that are readily testable. Testing of large integrated circuits has grown to become a particular tricky problem, especially when such circuit contains various blocks that have different functions. In particular, the generation of a set of test patterns that sufficiently covers generally occurring errors or error patterns, is time-consuming unless specific measures are taken. As regards internal integrated circuit testing, the scan-test or LSSD principle has become standard practice. BACKGROUND ART In such scan test, flipflops of the circuit are chained to a test register. After filling with a test pattern, the whole circuit is operated, synchronously or asynchronously. Then the contents of the test register are serially shifted out as a result pattern for further evaluation. Scan test of a static RAM memory along the above lines has been described in European Patent Application EP-A- 0 350 538 priority date July 13, 1988. The known system comprises as functional blocks the RAM-matrix, various control and other information registers, address decoder. In particular, the known system to a large degree obviates the need for extensive external communication, in that the test evolves internally and self-controlled. There is a test scan chain which needs a relatively long test/result pattern, and in a more complicated circuit, in particular one that has various function blocks of different character, the generation of the test and its execution would take unbearably long. In IEEE Design & Test, December 1986, F.P.M BEENKER ET AL: "Macro Testing: Unifying IC and Board Test", p.26-32, a method of partitioning an electronic assembly into macros is disclosed, where the macro tests can be put together to an assembly (chip) test. SUMMARY OF THE INVENTION Accordingly, it is one of the objects of the present invention to provide a method for testing such a complicated circuit wherein the respective functional blocks that may be of any of a wide range of particular functions, are tested thoroughly and independently of each other, while in a hierarchical organization of at least three successive levels allowing great ease of design and test management by on each level of the hierarchy presenting only a narrow interface for so realizing the testability at a small overhead. In a practical example, an overhead of some 7% in area was required only. Therefore, according to one of its aspects, the invention provides a method for testing a digital integrated circuit means that has a hierarchical organization of at least three levels, to wit, at least one assembly on a high level, at least one such assembly comprising on a next lower level a first sequence of subassemblies, at least one such subassembly comprising on a lowest level a second sequence of testable macro's, said method comprising the steps of: a. collectively resetting any said macro to its initial state, by an overall reset signal; b. entering an assembly test cycle while within its first sequence of subassemblies successively pointing each subassembly for controlling an associated subassembly test cycle until therefor receiving an associated subassembly ready signal; c. running the subassembly test cycle of the subassembly so pointed, and returning to the associated assembly test cycle after completion of the latter subassembly test cycle; wherein said subassembly test cycle comprises: d. entering said subassembly test cycle while within its second sequence of macro's successively pointing each macro and in each so pointing selectively and conditionally running a macro test under control of an overall, macro-test-mode (MTM) control signal but otherwise bypasssing the macro in question, and anyway returning to the subassembly test cycle after completion of the latter macro test; e. and after completely traversing said first sequence of subassemblies each in an appropriate subassembly test cycle producing an assembly good/faulty indication. Sequentially, all macro's are tested as far as required, the interaction between respective test cycles being on an elementary and clear level. The overall reset allows for a clear initial state. The integrated circuit means may be a single integrated circuit. The method described is very suitable for testing very complicated circuits, in which certain subfunctions would be combined to a function, and a particular set of functions to the functionality of the whole circuit. Thus, the testing organization goes hand-in-hand with the design organization. The same method may be used for testing an integrated circuit board that adds an additional hierarchical level. Likewise, a single circuit could have four or more hierarchical levels. Advantageously, after running through its sequence of next subaltern test cycles, each next higher level test cycle contains an idle state that is controlled by an overall macro-test mode control signal value. The invention also relates to an integrated circuit and integrated circuit arrangement so testable. Further advantageous aspects are recited in dependent claims. BRIEF DESCRIPTION OF THE FIGURES The invention will be further explained with respect to the following Figures that give a preferred embodiment not intended to give a limitation of the inventive scope. Figure 1 shows a hierarchical organization of an integrated circuit arrangement; Figure 2 symbolizes a test structure among parallel functional blocks at processor level; Figure 3 symbolizes a test structure among parallel subassemblies at multiprocessor level; Figure 4 shows hierarchical control of test control blocks. Figure 5 shows a series arrangement of scan-testable macro's according to the invention. ORGANIZATIONAL DESCRIPTION OF AN INTEGRATED CIRCUIT Figure 1 shows a hierarchical organization of an integrated circuit arrangement. Top right of the Figure has integrated circuit board 70, featuring integrated circuits, such as 20, 72, 74, of which circuit 20 will be detailed hereinafter, circuit 74 is a test control circuit or block, circuits 72 not further specified for brevity. All circuits have been shown as being surface-mounted DIL packages, but this is not to be conceived as a restriction. Block 20, top left, shows more in detail the same integrated circuit 20 mounted on board 70. Now, on the lowest level, block 34 symbolizes a testable functional block or macro. Such functional block may have various functions. In particular, the following feasible solutions have been designed: the macro is a fully combinatorial operation unit, which in consequence is completely synchronous; the macro is a fully scannable operation unit in that each internal flipflop thereof is accessible by a scan-chain. The macro may have one or a plurality of distinct scan-chains; a particular example could be the static random access memory referenced earlier; the macro in question is fully pipelined over its full word width, and in particular, does not contain a feedback. This means that the timing relation between input signals and output signals is always constant and uniform. A particular example would be a register file. If the intended function would require such feedback, the solution of course would be distribution over more than one macro. The above references macro's obey an elementary set of macro-leaf testability rules. It is envisaged that other functions by suitable adaptation would be made compatible to these rules in future. Now, after rendering the testable functional block operational, so that taken in isolation, it would operate correctly, no further changes should be made thereto when it is used as a building block or "black box" in a higher level structure. Block 24 symbolizes a subassembly that comprises testable functional block or macro 34 along with an assortment of other such macro's 30, 32, 36, 38 of the same or other function or structure, be it that they too, are testable and may not be changed when included in subassembly 24. For controlling the test within subassembly 24 there is provided test control block 25 that selectively assigns and controls test execution to the various macro's and also interfaces to external world, from the outlook of the subassembly, with interconnections 29. For simplicity, no interconnections within the subassembly have been shown. Apart from the test organizational requirements, the various macro's have their normal interconnections, both inside and outside the subassembly, but these neither have been shown for clarity. Block 20 symbolizes the complete functional circuit that comprises testable subassembly 24 along with its test control block 25, plus an assortment of other such subassemblies 22, 26 along with their respective test control blocks 23, 27, these assemblies thus being likewise testable and having the same or different functionality with respect to subassembly 24. Neither on this level, the subassemblies may be changed when included in overall circuit 20. For controlling the test in circuit 20, there is provided test control block 28 that selectively assigns test execution to the various subassemblies and also interfaces to external world, from the outlook of the assembly, with interconnections 21. For simplicity, no further interconnections within the circuit or for communicating with the external world and the subassemblies directly have been shown. Likewise, on the board level, test control circuit 71 controls and assigns the tests of various circuits 20, 72, no interconnections in this respect having been shown. Test control circuit 74 has external test pins 75 for connection to a test control machine, that under software or other controlling entity provides a test signal string to the circuit board, and thus, to the various circuits, subassemblies and macro's. The hierarchy shown has four levels: board, circuit, subassembly, macro. It is not necessary for each subassembly to be decomposable into a plurality of macro's. It is not necessary for each circuit to be decomposable into a plurality of subassemblies. On the other hand, the hierarchy could have more than four levels: for example, within a single circuit there could be more than three levels. Thus, on a lowest hierarchical level, the test control block directly controls the execution of the test. On each next higher level, the test control block only assigns the execution of the test to the test control block(s) on the next lower level. Note that, for example, block 26 could be the lowest level in its own branch of the tree. The particular nature of the test provisions will be discussed hereinafter. DESCRIPTION OF A TEST STRUCTURE Figure 2 symbolizes a test structure among parallel functional blocks at processor level in the form of a state diagram. The test hardware is discussed later. The processor level is the lowest level where a test control block (TCB) manages the test data flow. This test control block is activated by a test control block one level upwards in the hierarchy with either of two input control signals. In the first place, an overall reset signal MTR=1 (macro test reset) will drive the system to reset state 44. In the second place an enabling signal PRO_ENA=0 (processor enable) will drive the signal to idle strategy. The test control block operating according to Figure 2 may send back a "ready" signal to the next higher control level. In a particularly advantageous mode of execution, however, the functional blocks operate completely synchrously, and the local test control block would know the time length or number of clock cycles necessary for executing any particular test. The commands to the test control block are given in serial form via an overall primary input signal MTM (macro test mode). As shown in Figure 2, with respect to the processor in question the procedure starts with a reset signal of the finite state machine realized in the test control block in question: 40:MTR=1, whereupon the reset state RS(44) is attained. As long as signal MTM=0, loop 42 is traversed once every clock pulse received, inasmuch as the circuit is completely synchronous. Upon receiving the signal MTM=1, the test operation is begun (line 46). As far as MTM changes back to zero, each clock pulse brings the system in the next state of the chain 48, 50, 52, this chain having as many steps as there are macro's. It is feasible that two or more steps are assigned to a particular single macro. However each testable macro has at least one step in the chain. In coincidence with MTM=1, the machine branches off to running the test of either of types 1, 2 or 3 (blocks 58, 60, 62, respectively), each one corresponding to an associated macro. When the test in question is terminated under control of signal MTM=0, the systems reverts via line 64 to state 48. The changeover of signal MTM is controlled by the software that has been presented with the length of the test in question. If, during traversal of the chain 48, 50, 52, the system goes to idle state 54, it remains there, as long as either MTM=0, or the enable signal PRO_ENA remains zero (looping in loop 56). Only if both of these control signals go to 1, the system may revert to chain 48, 50, 52. As long as the system is in idle loop 56, the remainder of the test with respect to another subassembly than the one in question may be executed, for example by loading this other subassembly with a test control signal or test pattern. Thus, generally, all macro's are tested in sequence. In a particular refinement, it was found advantageous to do the loading of the test signals in the various macro's in sequence, and then have a plurality of macro's to execute their assigned tests in parallel. This parallellization of the tests at the lowest level in particularly advantageous in combination with the selftest strategy. There a sequence of test patterns is generated in sequence as based on one or more earlier result patterns, so that to a large degree the content of the eventual result is randomized for providing an excellent fault detection. The lesser capability for explicitly pointing at the fault within one particular macro, usually is not detracting from the strategies's advantageous properties. It has been found that the above loading in sequence and then executing the various tests proper in parallel alleviates the writing of the software for the test. In the above, the generation of the test patterns proper was not considered, but only the management of the test states. However, such test patterns would always be determined according to standard techniques, such as recited in the reference. The result thereof would be either straight result patterns, or such result patterns compacted to a signature pattern, or such patterns or signature evaluated for correctness to yield a good/fault indication. The evaluation may done on each feasible level, i.e., in the macro itself, on the subassembly, assembly, or superassembly level, or in an external tester machine. Besides the good/fault indication that in effect is a minimum prerequisite, various strategies not privy to the present invention would allow to identify any deviant behaviour. In principle also a repair procedure could be feasible, but none of these elaborated steps is being considered here. Figure 3 symbolizes a test structure among parallel subassemblies at multiprocessor level. In similar way, be it that the names of the various signals be different, an identical test structure (or parametrized in that the numbers of steps in any chain be larger or smaller) could be used for assigning and executing the test on the level of the various circuits on any higher level than corresponding to circuit 20 in Figure 1, be it within a single integrated circuit or on the level of a wired board with a plurality of integrated circuit modules mounted thereon. Anyway, the test control block realizing the state diagram of Figure 3, after being rendered operational by a higher level control block, may send back a "ready" signal when appropriate, to this next higher level. In a particular advantageous mode of execution, however, the functional blocks and subassemblies operate synchronously, and the test control block according to Figure 3 would know the time length or number of clock cycles necessary for any particular test. Notably, this would be the case when the state diagram of Figure 3 would represent the highest level of test cycle according to the present invention. Now, the commands to the test control block in question are again given in serial form as a primary input signal MTM (macro test mode), in addition with the signal MTR considered earlier, that controls the resetting. As shown in Figure 3, after the reset executed, changeover to MTM=1 will drive the system to connection 86. Upon reaching state 88 the system can execute a test on subassembly 1 under control of enabling signal PRO_ENA 1=1. This test period many proceed until the ready signal from the subassembly in question, RD1, changes from 0 to 1, whereupon the system goes to state 92. Likewise, a test on assembly 2 may now be executed. Upon attainment and leaving of state 96, via connection 100, the system goes to idle state 102, which is kept as long as either MTM=0 or MTE=0 (macro test enable); functionally, this latter signal corresponds to the enabling signal PRO_ENA ... In state 102 a "ready" signal is produced not shown explicitly. Upon MTM=1 and MTE=1 (not shown), the system again goes via connection 106 to state 88. From state 102 a delay may be effected in loop 104. In case of more than three successive hierarchical levels present, each higher level could be represented by a similar organizational structure as the one shown in Figure 3. Some further comments on Figure 3 are as follows: In order to stay compatible with the processor TCB state diagram, it has to be enabled and it has to generate a READY signal. Furthermore, a control signal is required to traverse the finite state machine. Since the multi-processor will normally be the highest level of hierarchy having a TCB, the nomenclature is somewhat different compared to the names used for the processor TCBs. The names for the multi-processor TCB control signals are according to the macro-test terminology: The multi-processor TCB is enabled by an external signal called MTE (Macro-Test Enable). It then starts appointing a lower level TCBs by the signal PRO_ENA. The state-diagram of the multi-processor is traversed under control of the signal MTM and the READY signals generated by the various processors. The appointed (enabled) processor TCB then starts running through a state diagram under control of the same external signal MTM (The MTM signal is passed to the enabled processor TCB). If the IDLE state in this diagram is entered, it generates the READY signal to indicate the multi-processor TCB that it has finished its test. Upon this signal the multi-processor TCB generates a PRO_ENA signal for the next processor. This process continuous until the last processor TCB has generated its READY signal. Due to this last signal the multi-processor TCB enters its own IDLE state and therefore generates its own READY signal. The IDLE state in the multi-processor state diagram is used for waiting during execution of self-tests in the various processors. A second reason is that during testing of the multiprocessor the whole circuit will stay in a defined known-good ("quiet") state. This process of appointing processors at a lower leel to operate is equivalent to tree-traversing. This is a hierarchical process and not limited by any level of hierarchy. HARDWARE REALIZATION Figure 4 shows the hierarchical control of test control blocks. Only data communication between the various processors (subassemblies) is shown. Control signals with associated test interface elements (TIE) have not been shown. Test control block 110 (TCB) receives signals MTR, MTM, MTE from the overall control level, and returns thereto ready signal READY. To various test control blocks TCB 112, 114 on the next lower level it transmits signals pro_ena (indices not specified) and therefrom receives signals Ready (indices not specified). The latter test control blocks also receive overall control signals MTR, MTM, that have no index. Test control blocks 112, 114 control processors 116, 118, respectively. As shown by way of example, the processors are interconnected by data buses 120, 122, of unspecified multibit width, each such bus having a control block 124, 126. The processors from their associated test control block receive the bus control block (BCB) control signal on lines 128, 130, respectively, an enabling one of the latter as shown controlling output buffers 132, 134 respectively, for transmitting the bus control block signals to the BCB control bus 136. The significance of the two control signals (the bus width is two control bits) is as according to the following table: In consequence, in the set-up shown, the control bus 136 is either driven by processor 116 or by processor 118 as selected by the signals on lines 128, 130. By way of example, the processors have been shown interconnected by two data buses 120, 122, but any other number would do. In this convention, while one processor would be able to drive control bus 136, and therefore, to be in command of data transfer on data buses 120, 122, any other processor connected thereto would be able to observe the data transferred on the data bus in question. The bus control blocks inside the respective processors would act as hold registers. Generally, the test inside of a macro is effected according to the well-known scan test principle referred supra. Inside a processor or assembly there are four scan chains controlled by the associated test control block. 1. data scan chains: Bus Control Block (BCB) scan chain. All BCBs in the processor are part of this scan chain. Data scan chain. The data scan chain consists of all other scannable flip flops in the processor. 2. Control scan chains: Instruction Register (IR) scan chain. 3. Self-test scan Chains . Self-test scan chain. All register cells and register files of self-testable macro's in the processor are part of this scan chain. Taken separately, the self-test principle has been described in US Patent 4,435,806. Self-test needs little external communication; the result is a go-no go information and relatively little fault-identification is produced. Merging or splitting of the various test scan chains may be feasible for shortening test time. For reference, the following set of signals is listed: MTM : Macro Test Mode (determines the mode of each TCB). MTE : Macro Test Enable (enables the highest level TCB and controls the BCB control bus). MTC : Macro Test Clock (present in case of multiple clocks). MTR : Macro Test Reset (reset the test control logic by forcing all TCBs to the RESET state). A number of serial data inputs and serial data outputs for the four types of scan-chans. These pins can be multiplexed with normal functional pins. In case of boundary scan, c.f. US Patent Application Serial No. 374,515: TDI, TDO, TCK, TMS as the four boundary-scan pins. MTM : Macro Test Mode (determines the mode of each TCB). The signals MTE and MTR can possibly be generated via the boundary-scan instruction register and boundary-scan TAP. The MTC can be the same as the TCK. Figure 5 shows the sitation where respective processors 142, 148 have each a separate scannable chain of flipflops 164, 166 that are connectable in series. The chains have only been indicated by a single line. In order to test the processors separately, they have been provided by a respective bypass, 156, 158, that each may contain a buffering flipflop for providing timing tolerance between input and output thereof. Furthermore, for allowing selective routing of the test patterns and result patterns through the scan chains, various multiplexers 140, 146, 152 have been shown with appropriate control signal inputs 154, 160, 162. The set-up shown is only an elementary example and could be developed along the same principle to a more sophisticated configuration. As explained, each processor may have four types of scan-chains. The question arises, what to do with these chains when designing a multi-processor. To shorten the time of serially testing all EXUs in the various processors so-called bypass-cells are used. A bypass cell is a scannable register cell placed along side a processor. This bypass cell provides a short-circuit route for test data in the scanning cycle of each scan-chain. IT can be used when an EXU in another processor has to be accessed. The multi-processor TCB controls this bypass cell via the PRO_ENA signal. This bypass cell is used for every type of scan-chain. The output of the multiplexer is connected to the serial data input of the scan-chain of the same type in another processor. In this manner the multi-processor has again four types of scan-chains. A second and even more important reason for using bypass cells is the generation of control signals for scan-chains in a multi-processor. A processor TCB generates control signals for its own local part of the scan-chains. If scan-chains of several processors are concatenated, conflicts can easily arise: Which TCB has control over the concatenated scan-chain? This problem could be solved by "tuning" the various TCBs. This is impossible in the hierarchical set-up as defined in this report. Hence, the only way to overcome this problem is either via test control buses as is the case with the BCB control bus or not concatenating scan-chains of various processors. We have chosen for the latter possibility. To minimize wiring to primary IC pins and to avoid large multiplexers (with corresponding control signals) the bypass cells are used. Hence, we have to state this as a rule: Scan-chains of various processors may not be concatenated and bypass cells have to be used.

Claims: A method for testing a digital integrated circuit means (70) that has a hierarchical organization of at least three levels, to wit, at least one assembly (20, 72) on a high level, at least one such assembly (20, 72) comprising on a next lower level a first sequence of subassemblies (22, 24, 26, 28), at least one such subassembly comprising on a lowest level a second sequence of testable macro's (25, 30, 32, 34, 36, 38), said method comprising the step of: a. collectively resetting all of said macros (25, 30, 32, 34, 36, 38) to its initial state, by an overall reset signal; characterized in that it further comprises the steps of: b. entering an assembly test cycle while within its first sequence of subassemblies (22, 24, 26, 28) successively pointing at each subassembly for controlling an associated subassembly test cycle until therefore receiving an associated subassembly ready signal; c. running the subassembly test cycle of the subassembly so pointed, and returning to the associated assembly test cycle after completion of the latter subassembly test cycle; wherein said subassembly test cycle comprises: d. entering said subassembly test cycle while within its second sequence of macro's successively pointing at each macro and in each so pointing selectively and conditionally running a macro test under control of an overall, macro-test-mode (MTM) control signal but otherwise bypasssing the macro in question, and anyway returning to the subassembly test cycle after completion of the latter macro test; e. and after completely traversing said first sequence of subassemblies (22, 24, 26, 28) each in an appropriate subassembly test cycle producing an assembly good/faulty indication. A method as claimed in Claim 1, wherein said integrated circuit means (70) is a single integrated circuit. A method as claimed in Claim 1, wherein said integrated circuit means (70) has a hierarchical organization of four levels, to wit, a superassembly on a highest level, at least one superassembly comprising third sequence of assemblies, wherein after said resetting said method further executes the following steps: a1. entering a superassembly cycle while within its third sequence of assemblies successively pointing at each assembly until receiving an associated assembly ready signal; a2. running in each assembly so pointed an assembly test cycle, and after completion of the assembly test cycle returning to the superassembly test cycle; f. and after completely traversing said third sequence of assemblies each in an appropriate test cycle producing a superassembly good/faulty indication. A method as claimed in Claim 3, wherein said integrated circuit means (70) is a wired board, each assembly (20, 72) representing an integrated circuit. A method as claimed in Claim 1 or 3, wherein each assembly test cycle after traversing pointing at all subassemblies (22, 24, 26, 28) therein comprises a first idle state (54, 102). A method as claimed in any of Claims 1, 3 or 5, wherein each subassembly test cycle after traversing pointing at all macro's (25, 30, 32, 34, 36, 38) therein comprises a second idle state (52, 54). A method as claimed in Claim 5 or 6, wherein any such idle state is accessible by an overall macrotest mode control signal value. A method as claimed in any of Claims 1 to 7, wherein said macro's (25, 30, 32, 34, 36, 38) are scan testable. A method as claimed in any of Claims 1 to 8, wherein any such integrated circuit (70) is boundary scan testable. An integrated circuit means (70) having an internal hierarchical organization of at least three levels, to wit, at least one assembly (20, 72) on a high level, at least one such assembly (20, 72) on a next lower organizational level comprising a first sequence of subassemblies (22, 24, 26, 28), atleast one such subassembly comprising on a lowest level a second sequence of testable macro's (25, 30, 32, 34, 36, 38), said circuit means (70) comprising: a. an overall reset signal input feeding any macro by a collective reset signal (MTR); characterized in that it further comprises: b. in any said assembly (20, 72) a respective first test control block (110, 112, 114) for within its associated first sequence of subassemblies (22, 24, 26, 28) circulating a first pointer for assigning a subassembly test cycle, until reception of a subassembly ready signal from the subassembly (22, 24, 26, 28) so pointed; c. in any said subassembly (22, 24, 26, 28) a respective second test control block (110, 112, 114) for within its associated second sequence of macro's (25, 30, 32, 34, 36, 38) circulating a second pointer for assigning a macro test under control of an overall macro-test-mode (MTM) control signal but otherwise bypassing the macro in question, and return means for returning from the macro test upon reception of a macro ready signal from the macro so pointed; d. and report means for after completely traversing said first sequence of subassemblies (22, 24, 26, 28) each in an appropriate subassembly test cycle producing an assembly good/faulty indication. An integrated circuit means (70) as claimed in Claim 10, which has a hierarchical organization of at least four levels, to wit, a superassembly on a highest level that comprises a third sequence of assemblies, said integrated circuit means (70) in said superassembly comprising a superassembly test control block (110, 112, 114) for within its associated third sequence of assemblies circulating a third pointer for assigning an assembly test cycle, until reception of an assembly ready signal from the assembly so pointed, and second report means for after completely traversing said third sequence of assemblies each in an appropriate assembly test cycle as based on any aggregated assembly good/faulty indication produced, generating a superassembly good/faulty indication. An integrated circuit means (70) as claimed in Claim 10 or 11, being realized as a single integrated circuit. An integrated circuit means (70) as claimed in Claim 10 or 11, wherein said macro's (25, 30, 32, 34, 36, 38) comprise at least a first macro having a first internal test-scan chain of flipflops, and a second macro having a second internal chain of further flipflops, and serializing means for serializing said first and second internal test-scan chains, said first and second macro having a respective first and second buffered bypass, said serializing means having at least a first state for therein serializing said first internal chain and said second bypass for deactivating said second internal chain, and a second state for therein serializing said first bypass and said second internal chain for deactivating said first internal chain. An integrated circuit means as claimed in Claim 10 or 11, wherein at least one subassembly comprises two macro's interconnected by a data bus provided with a bus control block (124, 126) external to both of said macro's, said integrated circuit means (70) having a bus control block control bus for feeding said bus control block with at least two different control signals in parallel, each of said two macro's comprising gate means for under control of their own control block gating bus control block control signals received from their own control block to said control bus.

Inventors: BEENKER FRANCISCUS PETRUS MARI, DEKKER ROBERTUS WILHELMUS CORN, STANS RUDI JOSEPHINE JULIAAN C, VAN DER STAR MAX C O INTERNATI, BEENKER, FRANCISCUS PETRUS MARIA C/O INTERNAT., DEKKER, ROBERTUS WILHELMUS CORNELIS C/O INTERNAT., STANS, RUDI JOSEPHINE JULIAAN C/O INTERNATIONAL, VAN DER STAR, MAX C/O INTERNATIONAL OCTROOI-
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1989
Main classification: G06F11
IPC codes: G01R31, G06F11