Clock driven data sampling circuit

Abstract: A circuit for recovering clock information from an incoming data signal preferably in NRZ1 form, the circuit including a VCO (18) providing a clock signal (CK) to four integrate/hold circuits (I1 to I4) which receive an incoming data signal, the integrate/hold circuits providing an error signal to the VCO (18) for adjusting the phase thereof to that of the incoming data signal, the integrate/hold circuits being seque∼ced by logic (10) to provide within each period of the clock signal three functions: (1) an integration of the incoming data signal in every bit period in which a voltage transition occurs, (2) a holding of the integrated value within a subsequent bit period or periods, and (3) a resetting of the integrated value following the next voltage transition in the incoming data signal, whereby the held integrated value, whose magnitude is dependent of the phase of the clock signal relative to the phase of the incoming data signal, provides said error signal.

Description: This invention relates to a circuit for recovering clock information from an incoming data signal. Such circuits are of particular use for aligning a local clock in a data receiver circuit to an incoming data signal to minimise bit error rates in the received data signal. Data signals are frequently nowadays transmitted along optical fibre links. Most of the noise in such signals is exhibited as phase jitter, being created by dispersion within the fibres, differential slew rates in the edges of the signals caused by LED switching, and because of noise in transimpedance amplifiers. An international standard, FDDI, has been set requiring that data be transmitted at a set rate, typically 125MBs⁻¹ in 4B/5B format a five bit code word represents four data bits) and in non return to zero inverse (NRZI) coding wherein a positive or negative transition in a bit period indicates a ′1′ and the absence of a transition in a bit period indicates a ′O′. Transitions may occur at a maximum rate of one every bit period, and at a minimum rate of one every 10 bit periods (known as the master line state). Thus a major problem in the design of receiver circuits for such data signals is the provision of a local clock which can accurately lock onto the incoming data signal despite phase jitter so that the data signal can accurately be decoded with minimal bit error rates. In our copending application GB-A-2187316 there is disclosed a receiver circuit including a modified Costas phase locked loop including a voltage controlled oscillator (herein referred to as a VCO) and dual integrate and hold circuits responsive to an incoming biphase Manchester coded signal to provide an error signal to the VCO dependent on the phase difference between the incoming signal and a local clock signal. The dual integrate and hold circuits operate in phase opposition so that one circuit integrates for half a cycle while the other circuit holds and then resets. This type of operation is suitable where there is a regular transition in each bit period providing phase information. However such circuits are not suitable where, as with NRZI coding, there is not a regular transition within the bit period of the incoming data signal, since transitions only occur when a ′1′ bit is indicated. In United States Patent No. 3,806,656 there is disclosed a clock recovery circuit in which two pairs of integrate and hold circuits are arranged cyclically to integrate and hold received signals and to provide error signals to control a voltage controlled oscillator from the difference between integrated values held by each pair in turn. The present invention provides a circuit for recovering clock information from incoming data signals exhibiting transitions between upper and lower voltage levels, the circuit including a controlled oscillator providing clock signals to integrate/hold means which receive said incoming data signals, the integrate/hold means providing an error signal to the controlled oscillator for adjusting the phase thereof to that of the incoming data signals, characterised in that said integrate/hold means comprises at least two integrate/hold circuits operable in turn to integrate the incoming data signals, and there are provided control means responsive to a transition in said incoming data signals between said voltage levels during a period of said clock signals to provide a hold signal to an operable integrate/hold circuit at the end of that period such as to hold the integrated value at least during the succeeding period to provide said error signal. As preferred, a plurality of similar integrate/hold circuits are employed, each performing an integrate/hold/reset function during each bit period. In order to sample every voltage transition in the incoming data signal, three circuits are provided so that one circuit is in a condition for integrating an incoming signal upon a voltage transition, a second circuit can hold an integrated value previously integrated, and a third circuit can be reset from a value held in the circuit upon a previous voltage transition. To achieve such functions with three integrate/hold circuits requires complicated sequencing circuits for regulating the operation of the three circuits so that for example one circuit is always ready to receive a signal for integration while the other circuits are performing their respective functions. In accordance with the invention, it is preferred to use four integrate/hold circuits, two such circuits being dedicated to positive-going transitions of the incoming data signal and two integrate/hold circuits being dedicated to negative-going transitions of the incoming data signal. In operation, one circuit of each pair integrates in each bit period, and the other circuit is reset. If no voltage transition occurs, the integrated value is discarded by resetting the circuit in the next bit period, but if a, say positive, voltage transition occurs, the integrated value is held over subsequent bit periods until such time as a negative going transition occurs following which the first circuit is reset. When the negative going transition occurs, one circuit of the negative pair integrates the signal and holds it over subsequent bit periods until a positive-going transition occurs following which it is reset. During the time when one circuit is being held, the other circuit of the appropriate pair is reset so as to be in condition for integration if necessary upon further voltage transitions. If desired more that four circuits may be employed for example six circuits which provides for increased accuracy in that two held versions of the incoming signal can be averaged to avoid problems of different slew rates causing modified duty cycles. Whilst in principle any type of integrate/hold circuit may be employed which is resettable within a well defined time period, it is preferred to employ a circuit of the type disclosed and claimed in our copending application GB-A-2 187 316. A preferred embodiment of the invention will now be described with reference to the accompanying drawings wherein:- Figure 1 is a block diagram of the preferred embodiment of the present invention; and, Figure 2 is a block diagram of sequencing logic for the integrate/hold circuits of Figure 1; Figure 3 is a circuit diagram of an integrated/hold circuit of Figure 1; and, Figure 4 is a waveform diagram of typical operating sequences of the circuit of Figure 1. Referring now to the block diagram of Figure 1 there is shown a receiver for receiving incoming data RCVD, being data transmitted across an optical fibre link at 125Mbs⁻¹ in an NRZI code wherein a ′1′ bit is indicated by a voltage level transition (positive or negative) in a bit period and a ′O′ bit is indicated by the absence of a transition, as shown in Figure 4A. The data signal is coupled to an integrate/hold detector comprising four similar circuits I₁, I₂, I₃, I₄ and sequencing logic 10. Data signal RCVD is applied to each of circuits I₁ to I₄ and logic 10. Data signal RCVD is coupled to an NRZ1 to NRZ converter 12 for converting the data into an NRZ format for further processing e.g. serial to parallel conversion. The output of converter 12 is coupled to a counter 14, the output of which is coupled together with ganged outputs from I₁ to I₄, via a charge pump and filter 16 to a voltage controlled oscillator 18, the output of VCO 18 providing a clock signal which is coupled to counter 14, integrate/hold detectors I₁ to I₄ sequencing logic 10, and converter 12. VCO 18 may be of any suitable type for example a narrow band VCO having a clearly defined centre frequency, since normally the frequency of the data RCVD will be similarly well defined. A configuration of an integrate/hold circuit is shown in Figure 3 and is more fully described in our copending application GB-A-2 187 316. A data signal is applied in differential form to two transistors connected in long tailed pair configuration Q1, Q2 and providing outputs to two transistors Q3, Q4 having a sampling capacitor C connected between their emitters, the outputs from the emitters of transistors Q3, Q4 being connected to a hold circuit Q5, Q6 comprising transistors in long-tailed pair configuration. Current sources I1 to I6 are selectively connected to the transistor stages Q1 to Q6 by switches indicated schematically as S1, S2, S3. These switches are controlled by suitable control logic inputs from control logic 10. Control logic 10 is shown in more detail in Figure 2 as comprising D-type flip-flop 20 for receiving a data signal RCVD and providing outputs to four further D-type flip-flops 22 to 28 via NOR gates 30 to 36. The clock signal CK is also clocked to flip-flops 20 to 28, and to further flip-flops 38 to 46. The Q and Q outputs of flip-flop 20 are coupled to NOR gates 30 to 36. The Q, Q outputs of flip-flop 38 are coupled to AND gates 48 to 54 and to X-OR gates 56, 58. The outputs of flip-flop 40 are coupled to gates 48, 50, 56. The outputs of flip-flop 44 are coupled to gates 34, 36 and the outputs of flip-flop 46 are coupled to gates 52, 54, 58. In operation, data RCVD is applied to the input of the integrate/hold circuits I1 to I4. The integrate/hold circuits are divided into two pairs I1, I2 and I3, I4, the circuits of each pair operating in phase opposition, one circuit operating in each bit period to integrate an incoming signal by closing of switch S1 while the other integrate/hold circuit operates to reset an integrated signal by closure of switch S2 in the absence of received data. Should a voltage transition be received and detected, the appropriate integrate/hold circuit is held in a hold condition by control circuit 10. Control circuit 10 is clocked by clock signal CK and operates in response to voltage transitions received at the input to flip-flop 20. A positive transition provides a high signal to gates 30, 32 and a negative transition provides a high signal to gates 34, 36. The gates 30, 32 are sequenced by flip-flops 40, 42 so that upon a positive voltage transition one flip-flop provides an integrate signal IN1 to gate S1 (Figure 3) of circuit I1 and the other flip-flop applies a reset signal to gate S2 of circuit I2. The appropriate gate 48, 50 then provides in the subsequent bit period a hold signal HS1 or HS2 to gate S3. A similar operation occurs when a negative transition occurs with gates and flip-flops 26 to 54, appropriate signals being applied to gates S1 to S3 of integrate/hold circuits I3, I4. In addition a negative transition resets the hold signal HS1 or HS2 of gates 48, 50 and resets the appropriate circuit I1 or I2 while putting the other circuit into condition for integration. The integrated values which are held by circuits I1 to I4 are provided as an error signal to filter 16 and hence to VCO18. The form of the error signal is shown in Figure 4D. When in the condition shown in solid lines in Figure 4A, the incoming data signal and the clock signal are perfectly in phase with voltage transitions in RCVD occuring at the centre of the bit period, then the integrated values in I1 to I4 all have the same magnitude as shown in Figure 4D. If the phase of RCVD advances so that voltage transitions occur in the first part of the bit period, then the phase error signal increases since the integrated values in I1 to I4 will all increase. If however the phase of RCVD lags, then the phase error signal decreases since the integrated values in I1 to I4 will all decrease. Naturally such changes in phase error signal will operate to shift the phase of CK in an appropriate direction to reduce the phase error. It is possible with an extended sequence of all 1's that the circuit be in a condition which does not detect the incoming data. This is shown in Figure 4E in which the phase has drifted and there is differential slew rates in the edge transitions so as to create a duty cycle not equal to 50/50 such that both positive and negative transitions occur within a single sampling period. In this situation the data will not be detected in converter 12 and on all 'O's state may be indicated. There is therefore provided a further circuit comprising counter 14 responsive to the clock signal CK which counts up to 16 and forces a transition error signal into charge pump and filter 16 in the absence of a data signal output from circuit 12 which acts to reset the counter. There is shown and disclosed a circuit for recovering clock in formation which is suitable for use with data in NRZI form. It is suitable for integration since the various integrate/hold circuits may be integrated on a single chip with similar resistance/capacitance values (although absolute values will only be approximate). Although the circuit disclosed is designed for receiving data in NRZ1 form, the invention is not limited to such a form of coding and may be employed with any form of NRZ coding.

Claims: A circuit for recovering clock information from incoming data signals exhibiting transitions between upper and lower voltage levels, the circuit including a controlled oscillator providing clock signals to integrate/hold means (I1 - I4) which receive said incoming data signals, the integrate/hold means (I1 - I4) providing an error signal to the controlled oscillator for adjusting the phase thereof to that of the incoming data signals, characterised in that said integrate/hold means (I1 - I4) comprises at least two integrate/hold circuits (I1, I2) operable in turn to integrate the incoming data signals, and there are provided control means (10) responsive to a transition in said incoming data signals between said voltage levels during a period of said clock signals to provide a hold signal to an operable integrate/hold circuit (I1, I2) at the end of that period such as to hold the integrated value at least during the succeeding period to provide said error signal. A circuit according to Claim 1 wherein said controlled oscillator comprises a voltage controlled oscillator. A circuit according to Claim 1 wherein four integrate/hold circuits (I1, I2, I3, I4) are provided, and said control means (10) is responsive to the incoming data signals such that one pair of circuits (I1, I2) is responsive to positive going transitions and the other pair of circuits (I3, I4) is responsive to negative going transitions. A circuit according to Claim 3, wherein, for each pair, said control means (10) is operative so that one circuit (I1, I2) is operative to integrate the incoming data signal while the other circuit (I2, I1) is reset so as to be ready for an integration operation in a subsequent period. A circuit according to Claim 4, wherein said control means (10) comprises a logic circuit including a plurality of bistable circuits and gates responsive to an incoming data signal and to said clock signals whereby to provide within each clock period appropriate integrate, hold and reset control signals to each integrate/hold circuit (I1 - I4). A circuit according to Claim 5 wherein said bistable circuits comprise D-type flip flops. A circuit according to any preceding claim including a counter for counting clock periods which is arranged to be reset in response to a recovered data transition, and being operative to provide a phase error signal to said controlled oscillator upon reaching a predetermined count. A circuit according to any preceding claim forming part of a data receiver circuit for data in NRZI form, wherein in any bit period a voltage transition represents a ′1′ bit and the absence of a transition represents an ′O′ bit.

Inventors: FLETCHER GRAHAM JOHN, LAWS PETER GRAHAM, FLETCHER, GRAHAM JOHN, LAWS, PETER GRAHAM
Applicants: PLESSEY SEMICONDUCTORS LTD, PLESSEY SEMICONDUCTORS LIMITED
Application year: 1989
Main classification: H04L7
IPC codes: H04L7