Semiconductor device

Abstract: A semiconductor device at a submicron miniaturization level comprises a high-current bipolar transistor having a wide emitter width and a high-speed bipolar transistor having a narrow emitter width, which transistors are formed in a common semiconductor substrate. According to a first embodiment, a base region of the former transistor is thicker than that of the latter transistor, and thus a suitable h FE balance is maintained, and according to another embodiment, a base region of the former transistor has a higher impurity concentration than that of another base region of the latter transistor and has the same depth as that of another base region, so that a suitable h FE balance is maintained.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IC, LSI, and VLSI, comprising a high-speed transistor and a high-current (or output) transistor formed in a common substrate. The semiconductor device generally comprises high-speed bipolar transistors for an arithmetic unit, a logic circuit, memory elements, and the like, and high-current bipolar transistors for an output circuit. Namely, the high-speed transistors operate at a small current and have a low breakdown voltage, but the high-current transistors operate at a large current and at a slower speed than that of the high-speed transistor, and have a high breakdown voltage. 2. Description of the Related Art In the semiconductor device comprising the high-speed bipolar transistor and the high-current bipolar transistor, a suitable balance of the static common-emitter current gains h FE of both transistors should be maintained, to ensure a stable operation and enable a simple circuit design for the device. A suitable h FE balance is that where the h FE of the high-current bipolar transistor is within ±30% of that of the high-speed bipolar transistor. In the prior art, both bipolar transistors have the same emitter width of several micrometers (i.e., more than 1 µm) in view of the h FE balance. Recently, to increase the switching (operating) speed of the high-speed bipolar transistor, shallow junction type bipolar transistors have been proposed (e.g., K. Kikuchi et al: "A High-Speed Bipolar LSI Process Using Self-Aligned Double Diffusion Polysilicon Technology", IEEE IEDM, 1986, pp. 420-423; M. Nakamae; "Recent Progress and Future Prospe for VLSI Si Bipolar Transistors", IEEE BCIM, 1987, pp. 5-6). The shallow junction structure is formed by a thermal diffusion of impurities into a silicon substrate (particularly, a silicon epitaxial layer corresponding to a collector region) from a polycrystalline silicon layer doped with the impurities by an ion-implantation process. Preferably, the emitter width is made narrower (less than 1 µm) for a higher operation speed, shallower shallow junction, lower power consumption, and in view of device miniaturization. The high-speed bipolar transistor can operate at 0.1 mA. Since the high-current bipolar transistor can operate at a large current (e.g., 24 to 30 mA), the emitter width should be wider than that of the high-speed bipolar transistor, but a simultaneous fabrication of the bipolar transistor with a narrow emitter width (Fig. 1B) and the bipolar transistor with a wide emitter width (Fig. 1A) leads to an h FE unbalance. As shown in Figs. 1A and 1B, base regions 51a and 51b having the same depth are simultaneously formed in collector regions 52a and 52b, which are portions of an epitaxial Si layer on an Si substrate (not shown). A wide emitter window 53a having an emitter width X of, e.g., 1.5 µm, and a narrow emitter window 54b having an emitter width Y of, e.g., 0.5 µm, are opened in an insulating (SiO 2 ) layer 54 covering the epitaxial layer, and when a polycrystalline silicon layer 55 having a thickness of, e.g., 100 nm, is deposited over the whole surface by a chemical vapor deposition (CVD) process, a portion 55b of the layer 55 filling the window 53b is thicker than a portion 55a filling the window 53a. The polycrystalline silicon layer 55 is then doped with impurities by an ion-implantation process at the projected range R p of, e.g., 50 nm. To diffuse the doped impurities into the base regions 51a and 51b, the device is subjected to a heat-treatment at 950°C for 30 minutes, so that emitter regions 56a and 56b are formed in the base region 51a and 52b, respectively. The emitter region 56a has a depth of, e.g., 150 nm, and the emitter region 56b has a depth of, e.g., 100 nm. The emitter region 56b is shallower (thinner) than the emitter region 56a, because the filling portion 55b includes an undoped portion thicker than that included in the filling portion 55a, and as a result, an active base region thickness Za of the wide emitter is smaller than the Zb of the narrow emitter. In general, the h FE is in inverse proportion to the amount of impurities in the active base region, and therefore, as the thickness of the active base becomes thinner, the h FE becomes larger and is not suitably balanced. To control the h FE of the high-current bipolar transistor, a multi-emitter structure increasing the number of the emitter regions, or an elongation of an emitter length, may be adopted, but this leads to an enlargement of the transistor size, which does not allow a miniaturization of the device and prevents an increase of the degree of integration. From EP-A-0 108 204 a semiconductor device is known, during the fabrication of which a plurality of n-type regions having different diffusion depths are formed within a single substrate by a single thermal diffusion step. The transistors of said semiconductor device in accordance with one embodiment stated in EP-A-0 108 204 have base regions with the same junction depth, and emitter regions with different junction depths. The transistors of said semiconductor device in accordance with another embodiment disclosed in EP-A-0 108 204 have base regions with different junction depths, and emitter regions with different junction depths wherein the transistor with the smaller base region also comprises the smaller emitter region. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device comprising shallow junction type bipolar transistors, the emitter regions of which have different submicron widths, while maintaining a suitable h FE balance, and the operation speeds of which can be made different. According to the present invention this object is solved by the features of claim 1. Improved embodiments of the inventive semiconductor device result from the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more apparent from the description of the preferred embodiments set forth below, with reference to the accompanying drawings, in which: Fig. 1A is a schematic sectional view of a bipolar transistor having a wide emitter width; Fig. 1B is a schematic sectional view of another bipolar transistor having a narrow emitter width; Fig. 2 is a schematic sectional view of a semiconductor device useful for understanding the present invention; Figs. 3A to 3C are schematic sectional views of the semiconductor device of Fig. 2 in various stages of production; Figs. 4A to 4C are schematic sectional views of a semiconductor device according the present invention, in various stages of production. DESCRIPTION OF EMBODIMENTS Referring to Fig. 2, a semiconductor device comprising a high-current (output) bipolar transistor A and a high-speed bipolar transistor B not covered by the present invention is now explained. For example, both of the npn-type transistors A and B are formed in a common semiconductor substrate consisting of a p-type semiconductor (Si) substrate (wafer) 1 and an n-type semiconductor (epitaxial Si) layer 3 having a resistivity of 0.5 Ωcm and a thickness of 1.6 µm, and n + -type buried layers 2a and 2b having a resistivity of 20 Ω/□ and a thickness of 3 µm are separately formed between the substrate 1 and the epitaxial layer 3. The epitaxial layer 3 is covered with a relatively thick insulating layer (field SiO 2 layer) 4 having a thickness of 600 nm and a thin insulating layer 5 having a thickness of 50 nm, and is divided into collector regions 3a and 3b by an isolation region 6 composed of a p + -type impurity doped region (or insulator). The collector contact (n + -type) regions 7a and 7b extend from the surface of the collector regions 3a and 3b to the buried layers 2a and 2b, respectively. Then p + -type base regions 9a and 9b are formed in the collector regions 3a and 3b, respectively, and N + -type emitter regions 8a and 8b are formed in the base regions 9a and 9b, and covered with impurity-containing layers 10a and 10b of, e.g., polycrystalline silicon, containing donor impurities and having a thickness of 100 nm. Electrodes (collector electrodes 11a, 11b, emitter electrodes 12a, 12b and base electrodes 13a, 13b) are formed on the collector contact regions 7a, 7b, the impurity-containing layers 10a, 10b and the base regions 9a, 9b, respectively, and accordingly, the high-current bipolar transistor A is composed of the collector region 3a, base region 9a, emitter region 8a, and electrodes 11a, 12a and 13a, and the high-speed bipolar transistor B is composed of the collector region 3b, base region 9b, emitter region 8b, and electrodes 11b, 12b and 13b. For example, the base region 9a has a depth of from 0.45 to 0.55 µm and the base region 9b has a depth of from 0.3 to 0.4 µm, and thus is shallower than the region 9a. The high-current transistor A has a wide emitter width of 2.0 µm, and accordingly, the emitter region 8a has a depth of 0.25 µm, and the high-speed transistor B has a narrow emitter width on the order of submicrons (0.6 µm), and thus the emitter region 8b has a depth of 0.15 µm, which is less than that of the region 8a. As a result of the depth control of the regions 9a, 9b, 8a and 8b, the static common-emitter current gains h FE of both transistors A and B can be made roughly equivalent (e.g., an h FE difference between the high-current transistor A and high-speed transistor B can be kept to within ±30% of the h FE of the high-speed transistor B). Therefore, while maintaining the h FE balance between the high-current transistor A and high-speed transistor B, the emitter width of the high-current transistor A can be suitably expanded, so that the transistor A operates at an operating current of, e.g., 30 mA. In this case, the high-current power transistor A occupies about half (50%) of the space required by a conventional power transistor having a multi-emitter structure, and this reduction of size of the high-current bipolar transistors contributes to a miniaturization of, and an increase of the integration degree of, an IC device. The semiconductor device shown in Fig. 2 is produced as follows and as as shown in Figs. 3A to 3C. As shown in Fig. 3A, using a conventional process for producing an npn-type bipolar transistor, donor impurities (e.g., Sb) are introduced into the Si substrate 1 by an ion-implantation process, and the n-type Si layer 3 having a thickness of 600 nm is epitaxially grown on the Si substrate 1 to form the n + -type buried layers 2a and 2b having a thickness of 3 µm and a resistivity of 20 Ω/□. The Si epitaxial layer 3 is thermally and selectively oxidized to the field SiO 2 layer 4 having a thickness of 600 nm, by the LOCOS process, donor impurities are selectively introduced into the Si epitaxial layer 3 and acceptor impurities are selectively introduced into the layer 3, and then the Si epitaxial layer 3 is thermally oxidized so that a thin SiO 2 layer 5 having a thickness of 50 nm is formed, and simultaneously, an annealing is carried out to form the collector regions 7a and 7b reaching the buried layers 2a and 2b and the p + -type isolation region 6 reaching the Si substrate 1, to divide the Si epitaxial layer into the collector regions 3a and 3b. As shown in Fig. 3B, for the power bipolar transistor, for example, acceptor impurities (e.g., boron ions) are introduced into the collector region 3a through the SiO 2 layer 5 by an ion-implantation process at an energy of 100 keV and a dose of 5 x 10 13 cm -2 . For the high-speed bipolar transistor, the same acceptor impurities (boron ions) are introduced into the collector region 3b through the SiO 2 layer 5 by an ion-implantation process at an energy of 35 keV and a dose of 5 x 10 13 cm -2 . Therefore, although the doses are the same, the implantation energies are different. Thereafter, an annealing (heat-treatment) after ion-implantation is carried out at 900°C for 30 minutes, so that the base region 9a having a depth of from 0.45 to 0.5 µm and the base region 9b having a depth of from 0.3 to 0.4 µm are formed in the collector regions 3a and 3b, respectively. Therefore, the base region 9a is thicker than the base region 9b. As shown in Fig. 3C, the insulating layer (SiO 2 layer) 5 is selectively etched by a conventional lithographic and etching process to form emitter windows 14a and 14b in which the base regions 9a and 9b are exposed, respectively. The emitter window 14a has a width of 2.0 µm and the emitter window 14b for the high-speed transistor has a width of 0.6 µm. Before the lithographic process, a SiO 2 layer (not shown) may be additionally deposited over the whole surface by a CVD process. Preferably a reactive ion etching process is used as the etching process. Then a polycrystalline silicon layer having a thickness of 100 nm is deposited over the whole surface by a CVD process, so that the windows 14a and 14b are completely filled therewith, and donor impurities (e.g., arsenic ions) are introduced into the polycrystalline Si layer only by an ion-implantation process at an energy of 60 keV and a dose of 5 x 10 15 cm -2 , to form the impurity-containing layer 10. To diffuse the impurities from the layer 10 into the base regions 9a and 9b, the device is subjected to a heat-treatment at 950°C for 30 minutes, and as a result, as shown in Fig. 2, the emitter regions 8a and 8b are formed to depths of 0.25 µm and 0.15 µm, respectively. Then the impurity-containing layer 10 is selectively etched by a conventional process to leave the portions 10a and 10b of the layer 10 on the emitter regions 8a and 8b, and the thin SiO 2 layer 5 is selectively etched to form contact windows for the collector contact regions 7a and 7b and the base regions 3a and 3b. A conductor layer is then deposited over the whole surface and is patterned (selectively etched) to form the electrodes 11a, 11b, 12a, 12b, 13a and 13b, whereby the semiconductor device shown in Fig. 2 is obtained. Referring to Figs. 4A to 4C, a semiconductor device comprising a high-current bipolar transistor A' and a high-speed bipolar transistor B' according to the embodiment of the present invention is now explained. Where the reference numerals used in Figs. 2 and 3A to 3C are used in Figs. 4A to 4C, these reference numerals indicate the same portions as, or portions corresponding to, those used in Figs. 2 and 3A to 3C. For example, both of the npn-type transistor A' and B' are formed in a common semiconductor substrate consisting of a p-type semiconductor Si wafer substrate 1 and n-type epitaxial Si layer 3. The n + -type buried layers 2a, 2b, the collector regions 3a and 3b, the n + -type collector contact regions 7a, 7b, the emitter regions 8a, 8b, the isolation region 6, the thick insulating (SiO 2 ) layer 4, the thin insulating (SiO 2 ) layer 5, the impurity-containing layer portions 10a, 10b, and the electrodes 11a, 11b, 12a, 12b, 13a, 13b are the same as those of the semiconductor device shown in Fig. 2. According to the present invention, for example, a p + -type base region 19a of the high-current transistor A' and a p + -type base region 19b of the high-speed transistor B' have the same depth of 0.15 µm, but the former region 19a has an impurity concentration (a dose of 8 x 10 13 cm -2 ) higher than that (a dose of 5 x 10 13 cm -2 ) of the latter region 19b. Since the emitter region 8a has a depth deeper than that of the emitter region 8b, the distance between the emitter-base junction face and the base collector junction face, i.e., the active base region thickness under the emitter region 8a, is smaller than the active base region thickness under the emitter region 8b. As mentioned above, the impurity concentration of the base region 19a is higher than that of the base region 19b. The impurity amount of the active base region of the high-current transistor A' can become, accordingly, almost equivalent to that of the active base region of the high-speed transistor B'. As a result of the impurity concentration control of the base regions 19a and 19b and the depth control of the emitter regions 8a and 8b, the static common-emitter current gains h FE of the transistors A' and B' can be made roughly equivalent, as obtained in the device shown in Fig. 2 of the first embodiment. Therefore, the device shown in Fig. 4C has the same advantages as those of the device of the previous embodiment. The semiconductor device (shown in Fig. 4C) of the embodiment of the present invention is produced as follows and as shown in Fig. 3A and Figs. 4A to 4C. In accordance with a conventional npn-type bipolar transistor, as shown in Fig. 3A, the n + -type buried layers 2a, 2b, the n-type epitaxial Si layer 3 including the collector regions 3a, 3b, the thick SiO 2 layer 4, the thin SiO 2 layer 5, the p + -type isolation region 6, and the n + -type collector contact region are formed as explained in the first embodiment. The buried layers 2a and 2b have a thickness of 3 µm and a resistivity of 20 Ω/□, and the epitaxial Si layer has a thickness of 600 nm. Then, as shown in Fig. 4A, for example, acceptor impurities (e.g., boron ions) are introduced into the collector regions 3a and 3b through the thin SiO 2 layer layer 5 by a first ion-implantation process at an energy of 35 keV and a dose of 5 x 10 13 cm -2 . Using a second ion-implantation process, the same acceptor impurities are then introduced into the collector region 3a only of the power transistor A' at the same energy (35 keV) and a dose of 3 x 10 13 cm -2 . Accordingly, the p + -type base regions 19a and 19b are formed and the former region 19a has an impurity concentration higher than that of the latter region 19b, but has the same depth as the latter region 19b. It is possible to form the base region 19a with boron ions at a dose of 8 x 10 13 cm -2 and to form the base region 19b with boron ions at a dose of 5 x 10 13 cm -2 , by respective ion-implantation processes at a constant energy of 35 keV. As shown in Fig. 4B, the thin SiO 2 layer 5 is selectively etched by a conventional lithographic and etching process to form emitter windows 14a and 14b, to expose portions of the base regions 19a and 19b, in a manner similar to that explained in the first embodiment. Then a polycrystalline silicon layer having a thickness of 100 nm is deposited over the whole surface by a CVD process, to fill the windows 14a and 14b, and donor impurities (e.g., arsenic ions) are introduced into the polycrystalline silicon layer 10 only by an ion-implantation process at an energy of 60 keV, and a dose of 5 x 10 15 cm -2 , to form the impurity-containing layer 10. Next, as shown in Fig. 4C, the device with the arsenic-containing layer 10 is subjected to a heat-treatment at 950°C for 30 minutes, to form the emitter regions 8a and 8b in the base regions 19a and 19b, respectively. The emitter region 8a has a depth of 0.25 µm and the emitter region 8b has a depth of 0.15 µm. The impurity-containing layer 10 is selectively etched to leave the portions 10a and 10b on the emitter regions 8a and 8b, and the thin SiO 2 layer 5 is selectively etched to form contact windows for the electrodes. A conductor layer is deposited over the whole surface and is patterned to form the emitter electrodes 11a, 11b, emitter electrodes 12a, 12b, and base electrodes 13a, 13b, and thus the semiconductor device is obtained. As mentioned above, although the emitter width of the high-current bipolar transistor is different from that of the high-speed bipolar transistor, the h FE valves of both transistors are kept at a similar or same level, and the high-current bipolar transistor size is reduced. It will be obvious that the present invention is not restricted to the above-mentioned embodiments and that many variations are possible for persons skilled in the art without departing from the scope of the invention.

Claims: A semiconductor device comprising a high-current transistor (A') having a wide emitter width and a high-speed transistor (B') having a narrow emitter width, the transistors being formed in a common semiconductor substrate and being vertical bipolar transistors, and the former emitter width being wider than the latter emitter width, wherein the depths of the base regions (19a,19b) of both transistors are the same and the depth of the emitter (8a) of the high-current transistor is greater than that of the high-speed transistor so that the thickness of the active base region of the high-current transistor is smaller than that of the high-speed transistor and wherein the impurity concentration of the active base region of the high-current transistor is higher than that of the active base region of the high-speed transistor, and the impurity amount of the active base region of the high-current transistor is similar to that of the active base region of the high-speed transistor. A semiconductor device according to claim 1, wherein said impurity concentration of the base region (19a) of the high-current transistor corresponds to a dose of from 3 x 10 13 cm -2 to 10 x 10 13 cm -2 , and said impurity concentration of the base region (19b) of the high-speed transistor corresponds to a dose of from 1 x 10 13 cm -2 to 8 x 10 13 cm -2 , the former concentration being higher than the latter concentration. A semiconductor device according to claim 2, wherein said impurity concentration of the base region (19a) of the high-current transistor corresponds to a dose of from 4 x 10 13 cm -2 to 7 x 10 13 cm -2 , and said impurity concentration of the base region (19b) of the high-speed transistor corresponds to a dose of from 3 x 10 13 cm -2 to 6 x 10 13 cm -2 , the former concentration being higher than the latter concentration. A semiconductor device according to any of claims 1-3, comprising a high-current bipolar transistor (A') and a high-speed bipolar transistor (B') formed in a common semiconductor substrate: said high-current bipolar transistor (A') being composed of: the common semiconductor substrate which consists of a semiconductor wafer substrate (1) and an epitaxial semiconductor layer (3) formed on the wafer substrate (1), the epitaxial layer (3) serving as a collector region (3a); a base region (19a) formed in said epitaxial layer (3); an emitter region (8a) formed in said base region (19a) and having a wide width; an impurity-containing layer portion (10a) covering the surface of said emitter region (8a), and having served as an impurity diffusion source for the emitter region (8a); and a collector electrode (7a), a base electrode (13a), and an emitter electrode (12a) lying on said collector region (3a), base region (19a) and impurity-containing layer portion (10a), respectively; said high-speed transistor (B') being composed of: said common semiconductor substrate consisting of the wafer substrate (1) and the epitaxial layer (3) serving as another collector region (3b); another base region (19b) formed in the another collector region (3b) and having a same depth as the depth of said base region (19a) of said high-current transistor (A') and having an impurity concentration lower than the impurity concentration of said base region (19a); another emitter region (8b) formed in said another base region (19b) and having a narrow width, relatively to said wide emitter width, and a depth shallower than the depth of said base region (19b), another impurity-containing layer portion (10b) covering the surface of said another emitter region (8b) and having served as an impurity diffusion source for the another emitter region (8b); and a collector electrode (7b), a base electrode (13b), and an emitter electrode (12b) lying on said another collector region (3b), another base region (19b) and another impurity-containing layer portion (10b), respectively.

Inventors: YAMAUCHI TUNENORI, YAMAUCHI, TUNENORI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H01L27
IPC codes: H01L29, H01L21, H01L27