Sum/differential signal processing circuit

Abstract: A sum/differential signal processing circuit for use in a sound reproduction system, such as a Dolby surround processing system, includes a pair of operational amplifiers (IC₁,IC₂), a resistor (R₅) connected between the inverting input terminals of the operational amplifiers (IC₁,IC₂), two resistors (R₈,R₉) connected between the output terminals of the operational amplifiers (IC₁,IC₂), a signal output terminal connected to a junction between the two resistors (R₈,R₉) for producing the sum of output signals from the output terminals of the operational amplifiers (IC₁,IC₂). A make switch (SW), connected across one of the two resistors (R₈) is selectively rendered ON and OFF. When the make switch (SW) is ON, the sum of output signals of the operational amplifiers (IC₁,IC₂) is derived from the signal output terminal while when the make switch (SW) is OFF, the difference between the output signals thereof is derived therefrom. Even when a monaural signal is applied to each of the two signal input terminals, the signal is not cancelled by the circuit thus arranged.

Description: The present invention relates to a sum/differential signal processing circuit for use in a surround processor such as a Dolby® surround processing system. Surround processors, such as Dolby® surround processing systems, are generally required to produce signals representing the sum of and the difference between left and right stereophonic signals. Therefore, sound reproduction systems, such as these surround processors, include a sum/differential signal processing circuit for producing left and right signals. When a monaural signal is reproduced from an AM broadcasting program or a monaural VTR, the monaural signal would be cancelled if it passed through a difference detector. Thus, it is necessary to switch between differential and sum signal processing modes dependent on an input signal applied. It would be conceivable to provide a sum/differential signal switching circuit as shown in FIG.2, in which operational amplifiers IC₁ and IC₂ generate signals V1 = A-B and V2 = A+B independently of each other. Either one of these signals is selected by a transfer switch SW′ so that an output voltage V0 may be either V0 = V1 or V0 = V2. The transfer switch SW′ is of the two-contact switching type. Where the transfer switch SW′ is constructed of bipolar transistors, as shown in FIG.3, a control voltage signal is applied directly to the base of one transistor TR₂ and via an inverter to the base of the other transistor TR₁ for allowing input signals applied to the emitters of the transistors TR₁ and TR₂ to be selectively picked up as an output signal from the collectors thereof. Therefore, the transfer switch requires two transistors, and the inverter is further required to invert the control voltage signal. The transfer switch of FIG.3 is thus complex in arrangement. French patent application FR-A-2 313 807 discloses a signal processing circuit for receiving first and second input signals and producing differential signals upon processing said first and second input signals, said circuit comprising: first and second operational amplifiers, each having an inverting input terminal, a noninverting input terminal and an output terminal; first and second signal input terminals, said first and second input signals being applied to said first and second signal input terminals, respectively; an attenuator having one end connected to said first and second signal input terminals and another end connected to one of said input terminals of said first and second operational amplifiers for attenuating said first and second input signals when applying to said one input terminals thereof, wherein said first and second operational amplifiers output first and second output signals in response to said attenuated first and second input signals and also having one resistor connected between said output terminal of said first operational amplifier and said inverting input terminal thereof and another resistor connected between said output terminal of said second operational amplifier and said inverting input terminal thereof, forming negative feedback loops. It is therefore an object of the present invention to provide a sum/differential signal processing circuit which can switch between a sum signal and a differential signal simply by employing single bipolar transistor as a make switch. According to the present invention, there is provided a sum/differential signal processing circuit for receiving first and second input signals and producing a sum signal and a differential signal upon processing the first and second input signals, the circuit comprising: first and second operational amplifiers, each having an inverting input terminal, a noninverting input terminal and an output terminal; first and second signal input terminals, the first and second input signals being applied to the first and second signal input terminals, respectively; an attenuator having one end connected to the first and second signal input terminals and another end connected to the noninverting input terminals of the first and second operational amplifiers for attenuating the first and second input signals when applying to the noninverting input terminals thereof, wherein the first and second operational amplifiers output first and second output signals in response to the attenuated first and second input signals, respectively; a first resistor connected between the inverting input terminals; second and third resistors connected in series to each other at a junction, the series-connected resistors being connected across the output terminals of the first and second operational amplifiers; fourth resistor connected between the output terminal of the first operational amplifier and the inverting input terminal thereof; fifth resistor connected between the output terminal of the second operational amplifier and the inverting input terminal thereof; a signal output terminal connected to the junction; a switch connected across the second resistor, the switch being selectively rendered ON and OFF, the second resistor being short-circuited when the switch is ON; and wherein the sum signal is indicative of a sum of the first and second outputs and the differential signal is indicative of a difference between the first and second outputs, the sum signal appears on the signal output terminal when the switch is OFF and the differentiai signal appears thereon when the switch is ON, and wherein resistances of the first, second, third, fourth and fifth resistors are selected so that the sum signal and the differentiai signal are provided on the signal output terminal. The sum/differential signal processing circuit thus arranged is preferably employed in a sound reproduction system, such as a Dolby® surround processing system. Even when a monaural signal is applied to each of the first and second signal input terminals, the signal is not cancelled. The above and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of illustrative example. In the drawings: FIG.1 is a circuit diagram of a sum/differential signal processing circuit according to an embodiment of the present invention; FIG.2 is a circuit diagram of a sum/differential signal processing circuit on which the present invention is based; and FIG.3 is a circuit diagram of a switch for selecting one of a sum signal and a differential signal produced in the sum/differential signal processing circuit shown in FIG. 2. FIG.1 shows a sum/differential signal processing circuit according to the present invention. The sum/differential signal processing circuit includes a pair of operational amplifiers IC₁ and IC₂ having respective noninverting input terminals for receiving signals A and B, respectively, through respective resistors R₁ and R₃. The noninverting input terminals are connected to ground through respective resistors R₂ and R₄ which serve as an attenuator. The operational amplifiers IC₁ and IC₂ have respective output terminals connected to an output terminal OUT of the sum/differential signal processing circuit via respective resistors R₈ and R₉. Output signals from the operational amplifiers IC₁ and IC₂ are fed back to the respective inverting input terminals via associated resistors R₆ and R₇ for forming negative feedback loops. A resistor R₅ is connected between the inverting input terminals of the operational amplifiers IC₁ and IC₂. A make switch SW which may be made up of a bipolar transistor is connected between the output terminal of the operational amplifier IC₁ and the output terminal OUT. Setting that α = R₂/(R₁ + R₂) β = R₄/(R₃ + R₄), signal voltages V₁ and V₂ at the output terminals of the operational amplifiers IC₁ and IC₂ are expressed as follows: V₁ = α · A · (1 + R₆/R₅) - β · B · (R₆/R₅) V₂ = β · B · (1 + R₇/R₅) - α · A · (R₇/R₅) The voltage signal V₀ at the output terminal OUT is given as follows: V₀ = {R₉/(R₈ + R₉)} · V₁ + {R₈/(R₈ + R₉)} · V₂ For the sake of brevity, it is assumed here that β = 1 and R₆ = R₇. By substituting equations (1) and (2) for equation (3), equation (3) is expressed as follows: V₀ = [{R₉/(R₈ + R₉)} · {α/(1 - α)} - {R₈/(R₈ + R₀)} · {α²/(1 - α)}] · A + [{R₈/(R₈ + R₉)} · {1/(1 - α)} - {R₉/(R₈ + R₉)} · {α/(1 - α)}] · B Equation (4) can be rearranged as follows: V₀ = A · α 1 - α · R₉ - R₈ · α R₈ + R₉ + B 1 1 - α · R₈ - R₉ · α R₈ + R₉ By determining R₁ through R₆ so that α(1 + R₆/R₅) = β · R₆/R₅ in equation (1) and using a constant K, the voltage V₁ can be rewritten as: V₁ = K (A - B). Assuming that R₃ = 0, i.e., β = 1, then R₆/R₅ = α/(1 - α) Hence, K = α/(1 - α). By determining R₈ and R₉ so that α 1 - α · R₉ - R₈ · α R₈ + R₉ = 1 1 - α · R₈ - R₉ · α R₈ + R₉ in equation (4)′, and using a constant K′, the voltage V0 is given by: V₀ = K′ (A + B) Equation (4)″ is simplified as follows: α · R₉ - α² · R₈ = R₈ -α · R₉ Therefore, α² · R₈ - 2α · R₉ + R₈ = 0. If R₈ is a real number, the following equation can be obtained by dividing both sides of the above equation by R8. α² - 2α · R₉/R₈ + 1 = 0 α = R₉ ± R₉² - R₈² R₈ Assuming that α = 1/2, for example, R₉ = (5/4) · R₈ Thus, by determining so that R₁ = R₂, R₃ = 0, R₅ = R₆ = R₇, R₉ = (5/4) · R₈, the signal voltages of (A-B) and (A+B) are selectively available from the output terminal OUT dependent on whether the make switch SW is turned on or off. Where the values of the resistors are determined as described above, since K′ = α 1 - α · R₈ - R₉ · α R₈ + R₉ K′ = 1/3 Because R₅ = R₆ and from equation (5), K = α/(1 - α) = 1 With the present invention, simply by selecting the values of the resistors in the sum/differential signal processing circuit, and employing a simple make switch which may be composed of a bipolar transistor, sum and differential signals can selectively be produced from the output terminal of the circuit. Although a certain preferred embodiment has been shown and described, it should be understood that many changes and modifications may be made therein without departing from the scope of the appended claims.

Claims: A sum/differential signal processing circuit for receiving first and second input signals and producing a sum signal and a differential signal upon processing said first and second input signals, said circuit comprising: first and second operational amplifiers (IC₁, IC₂) each having an inverting input terminal (-), a noninverting input terminal (+) and an output terminal; first and second signal input terminals (A, B), said first and second input signals being applied to said first and second signal input terminals, respectively; an attenuator (R₂, R₄) having one end connected to said first and second signal input terminals (A, B via R₁, R₃) and another end connected to said noninverting input terminals (+) of said first and second operational amplifiers (IC₁, IC₂) for attenuating said first and second input signals when applying to said noninverting input terminals thereof, wherein said first and second operational amplifiers output first and second output signals in response to said attenuated first and second input signals, respectively; a first resistor (R₅) connected between said inverting input terminals (-); second and third resistors (R₈, R₉) connected in series to each other at a junction, said series-connected resistors being connected across said output terminals of said first and second operational amplifiers (IC₁, IC₂); fourth resistor (R₆) connected between said output terminal of said first operational amplifier (IC₁) and said inverting input terminal (-) thereof; fifth resistor (R₇) connected between said output terminal of said second operational amplifier (IC₂) and said inverting input terminal (-) thereof; a signal output terminal (V₀) connected to said junction; a switch (SW) connected across said second resistor (R₈), said switch being selectively rendered ON and OFF, said second resistor being short-circuited when said switch is ON; and wherein said sum signal is indicative of a sum of said first and second outputs (V₁, V₂) and said differential signal is indicative of a difference between said first and second outputs (V₁, V₂), said sum signal appears on said signal output terminal when said switch is OFF and said differential signal appears thereon when said switch is ON, and wherein resistances of said. first, second, third, fourth and fifth resistors are selected so that said sum signal and said differential signal are provided on said signal output terminal. A sum/differential signal processing circuit according to claim 1, wherein said attenuator comprises a first attenuator (R₁) connected between said first signal input terminal (A) and said noninverting input terminal (+) of said first operational amplifier (IC₁) for attenuating said first input signal, and a second attenuator (R₃) connected between said second signal input terminal (18) and said non-inverting input terminal (+) of said second operational amplifier (IC₂) for attenuating said second input signal. A sum/differential signal processing circuit according to claim 2, wherein said first attenuator comprises a sixth resistor (R₁) and a seventh resistor (R₂), said sixth resistor (R₁) having a first terminal connected to said first input terminal (A) and a second terminal connected to said noninverting input terminal (+) of said first operational amplifier (IC₁), said seventh resistor (R₂) having a third terminal connected to said second terminal and a fourth terminal connected to ground, said second attenuator comprises an eighth resistor (R₃) and ninth resistor (R₄), said eighth resistor (R₃) having fifth terminal connected to said second input terminal (B) and a sixth terminal connected to said noninverting input terminal (+) of said second operational amplifier (IC₂), said ninth resistor (R₄) having seventh terminal connected to said sixth terminal and eighth terminal connected to ground.

Inventors: NAKAYAMA KAZUAKI C O PIONEER E, NAKAYAMA, KAZUAKI C/O PIONEER ELECTRONIC CORP.
Applicants: PIONEER ELECTRONIC CORP, PIONEER ELECTRONIC CORPORATION
Application year: 1989
Main classification: H04S3
IPC codes: H03F3, H04S7, H04S3