ANALOG OPERATION CIRCUIT

Abstract: An analog operation circuit adapted to operating multiplication, division, compression, elongation, and combinations thereof. In order to realize the circuit in the form of MOS LSI overcoming the problems inherent in the existing analog operation circuits, the invention comprises a DELTA SIGMA modulation circuit with A/D conversion circuits (11 to 18) and a first D/A conversion circuit (19), a second D/A conversion circuit (20) that receives the output of the DELTA SIGMA modulation circuit, and a low-pass filter (30) which receives the output of the second D/A conversion circuit (20) and produces the result of operation.

Description: ANALOG ARITHMETIC CIRCUIT TECHNICAL FIELD The present invention relates to an analog arithmetic circuit, and more particularly to an analog arithmetic circuit adapted to execute arithmetic operations such as multiplications, additions, divisions, compressions and expansions, as well as combinations thereof. BACKGROUND ART In some conventional analog multipliers, a multiplication is executed, for instance, by adding logarithmic functions represented by the equation I ≃ Is·e KV that expresses the relationship between the current I and the voltage V at a PN junction (where I = the current flowing through the PN junction; Is = a saturation current; V = a voltage across the PN junction; and K = a constant). However, the voltage V across the PN junction in the conduction state is on the order of about 0.6 V, and hence, the magnitude of an analog input signal is limited. As a result, it has been impossible to execute a multiplication of analog signals each having a large amplitude. Furthermore, in this type of multiplication, the arithmetic operations are frequently adversely affected by noise so that it cannot be expected to obtain a product with a high degree of accuracy. In addition, it has been difficult to construct this type of analog circuit in the form of a MOS-LSI. There has been proposed and demonstrated a time-division type multiplier (for instance, as disclosed in the Japanese Patent Application Laying Open No.55-82375), in which a first input voltage Ex and its inverted voltage -Ex are alternately switched on, and the duty ratio of the switching is subjected to the pulse-width modulation by a second input voltage Ey. After that, the pulse-width modulated outputs are averaged, thereby obtaining the output Ex × Ey. In this circuit, however, the pulse-width modulated output is obtained as a level ratio between an analog input signal Ey and a triangle waveform signal. Consequently, the pulse duration of the output takes an arbitrary value as long as the analog input signal takes an arbitrary value, even if the frequency of the triangle waveform signal is maintained constant. In other words, the pulse duration takes a continuous value. In view of the fact that the duty ratio of the pulse-width modulation circuit varies continuously, a high-speed and high-accuracy analog circuit is required in order to make the duty ratio correctly follow the original signal. In addition, a triangle generator in a pulse-width modulation circuit must have a high degree of accuracy because the amplitude and frequency of the triangle waveform signal considerably affect the modulation characteristics. This not only makes it difficult to fabricate the generator in the form of a MOS-LSI, but also makes the generator susceptible to noise. Two types of conventional analog dividers are well known in the art: one is a system utilizing a logarithmic amplifier; and the other is a multiplication-feedback system in which analog multiplier is inserted into the feedback loop of an operational amplifier. However, the former system has the problems that the arithmetic operation speed is slow, and that only the arithmetic operation can be achieved between an operated signal (a signal that represents the entity such as dividend) and an operating signal (a signal that represents the entity such as divisor) of either positive or negative signs. In the case of the latter, since the system has the feedback loop including the multiplier, it tends to oscillate so that a satisfactory degree of stability cannot be achieved. Two types of conventional analog expansion and compression circuits are well known in the art: a system using a gain control circuit utilizing a nonlinear characteristic of bipolar transistors; and a system using a diode-clamp piecewise linear approximation circuit including a resistor-diode network. In these systems, when they are used as an expansion circuit, the nonlinear element is connected to the input of an amplifier, whereas when they are used as a compression circuit, the nonlinear element is inserted into the feedback loop. As a result, the system using the non-linear characteristic of the bipolar transistors presents the problems that each transistor has a different non-linear characteristic, and that it is difficult o make the system compact in the form of an LSI. On the other hand, the system using the diode-clamp piecewise linear approximation circuit must use a large number of resistors, and hence, it is substantially difficult to construct the system in the form of an LDI. The above-described various conventional analog arithmetic circuits have their own defects. In addition, their circuit configurations are greatly different from one another according to the arithmetic operations demanded so that they cannot be used in common and cannot be universalized. As a result even if it is possible to construct them in the form of an LSI, various types of LSIs must be fabricated. This will greatly reduce the merits resulting from the mass production system. An article entitled "A high-performance CMOS stereo ADC and DAC chip-set for Digital Audio" by W. Bradinal et al, IEEE International conference on Consumer Electronics - June 1987 (published at pages 49-49 of the transactions) describes an I.C. with analog to digital and digital to analog convertor for sampling and processing of audio signals. The analog to digital converts employ switched capacitors and an operational amplifier. DISCLOSURE OF THE INVENTION One of the objects of the present invention is to provide an analog arithmetic circuit which can substantially solve the above and other problems encountered in the conventional analog arithmetic circuits. Another object of the present invention is to provide an analog arithmetic circuit which has a simple construction and a stable operation. A further object of the present invention is to provide an analog arithmetic circuit which can be fabricated in the form of a MOS-LSI so that the analog arithmetic circuit can be made compact in size. A still further object of the present invention is to provide a universal type analog arithmetic circuit which can use a fundamental common circuit for executing various arithmetic operations. An analog arithmetic circuit according to the invention receives an operated signal and an operating signal, and outputs the results of an arithmetic operation, and comprises: ΔΣ modulation means having AID conversion means and first D/A conversion means. said AID conversion means sampling said operated signal at a sampling rate determined by a clock signal with a predetermined sampling frequency significantly higher than the maximum frequency of the operated signal thereby outputting a digital signal and said first D/A conversion means receiving said digital signal outputted from the AID conversion means and a first reference signal said first D/A conversion means serving to convert the first reference signal into a first analog signal which takes a positive or negative amplitude in response to said digital signal, (Vd) in the first analog signal being fed back to said A/D conversion means; a second D/A conversion means for receiving said digital signal and outputting a second analog signal in response to a second reference signal said second analog signal alternating between positive and negative values in response to said second reference signal, and low-pass filtering means for receiving said second analog signal and outputting an analog signal representing the result of an arithmetic operation, wherein at least one of said first reference signal or said second reference signal is selected as said operating signal. Other preferred features of the invention can be found in the dependent claims. The digital signal outputted from ΔΣ modulation means can be a 1-bit digital signal. Furthermore, each of the first and second conversion means can be constructed with an operational amplifier and switched-capacitors. The low pass filtering means can also be constructed with an operational amplifier and switched-capacitors. More preferably, the second reference signal is inputted as an operating signal so that the output signal representative of the product of the operated signal and the operating signal can be produced. When the first reference signal is inputted as an operating signal, the signal representative of the quotient obtained by dividing the operated signal by the operating signal can be produced. When the signal obtained by rectifying-and-averaging operation of the operated signal is used as the second reference signal, i.e., as an operating signal, it becomes possible to output an expanded signal. Furthermore, when the signal obtained by rectifying-and-averaging the quotient signal is used as the first reference signal, i.e., as the operating single, it becomes possible to output a compressed signal. It is preferable that the rectifying-and-averaging operation be carried out by using switched-capacitors, a comparator, and an operational amplifier. More preferably, the analog arithmetic circuit can be provided with a selection means for selecting a predetermined output as the operating signal instead of the rectified-and-averaged output when the rectified-and-averaged output is decreased below a predetermined value. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a block diagram showing a basic construction of an analog arithmetic circuit in accordance with the present invention; Figs. 2A - 2K are diagrams illustrating waveforms at various points of the analog arithmetic circuit of the present invention; Fig. 3 is a block diagram illustrating a first or a second D/A converter of the analog arithmetic circuit of the present invention; Fig. 4A is a block diagram illustrating ΔΣ modulator of the analog arithmetic circuit of the present invention; Fig. 4B is a block diagram illustrating a circuit consisting of the second D/A converter and a low-pass filter of the analog arithmetic circuit of the present invention; Fig. 5 is a block diagram of the analog arithmetic circuit in accordance with the present invention when it is used as a multiplier; Fig. 6 is a block diagram of the analog arithmetic circuit in accordance with the present invention when it is used as a divider; Fig. 7 is a block diagram of the analog arithmetic circuit in accordance with the present invention when it is used as an expansion circuit; Fig. 8 is a block diagram of the analog arithmetic circuit in accordance with the present invention when it is used as a compression circuit; Fig. 9 is a schematic block diagram illustrating one example of an rectifying-and-averaging circuit used in the analog arithmetic circuit in accordance with the present invention; Fig. 10 is a block diagram illustrating a more practical construction of the rectifying-and-averaging circuit shown in Fig. 9; Figs. 11A - 11D are diagrams illustrating the signal waveforms at various points in Fig. 7; and Fig. 12 is a block diagram illustrating one example of a compression circuit wherein a minimum-output-setting unit is added to the compression circuit shown in Fig. 8. BEST MODE FOR CARRYING OUT THE INVENTION Fig. 1 is a block diagram illustrating the basic construction of an analog arithmetic circuit in accordance with the present invention. The analog arithmetic circuit comprises ΔΣ modulator 10, a second D/A converter 20 and a low-pass filter 30. The basic construction of the ΔΣ modulator 10 is well known, and in general, converts an analog signal into a pulse-density modulated signal. Various types of the ΔΣ modulator are well known in the art. In the analog arithmetic circuit shown in Fig. 1, a dual-modulation-type ΔΣ modulator 10 is used, which comprises operational amplifiers 11 and 12, adders 13 and 14, and feedback capacitors 15 and 16 connected to the operational amplifiers 11 and 12, respectively. Because of the capacitors 15 and 16, each operational amplifier 11 or 12 functions as an integrator. The ΔΣ modulator 10 further comprises a comparator 17, a flip-flop 18 for receiving the output of the comparator 17 in synchronism with clock pulses having a sampling frequency (fs), a first D/A converter 19 (1-bit D/A converter), an input line 10a for inputting an operated signal Va (an analog signal), a line 10b for supplying a reference signal Vb to the first D/A converter 19, a line 10s for delivering clock pulses fs to the flip-flop 18, a line 20c for delivering a reference electrical signal Vc to the second D/A converter 20, and an output line 30a of the analog arithmetic circuit. The frequency of the clock pulses-delivered through the line 10s must be at least ten times higher than the maximum frequency of the operated signal, and preferably should be as high as 50 - 1000 times. The frequency less than 10 times is not preferable because S/N ratio declines accordingly. Quantizing noise in the ΔΣ modulator 10 increases at the high frequency band. In order to improve the frequency characteristics with regard to the quantizing noise, the following techniques can be used: a plurality of integrators, each using an operational amplifier, are connected in a serial fashion as shown, for instance, in Fig. 1; and/or the D/A converter 19 is constructed so as to convert not a single bit but multi-bits. Referring to Fig. 1, the operated signal Va (analog signal) having, for example, a sinusoidal waveform with a peak A as shown in Fig. 2A is transmitted through the line 10a. The operated signal Va (Fig. 2A) and the output from the first D/A converter 19 are fed to the adder 13 which in turn delivers its output to the inverting input terminal of the operational amplifier 11. The adder 14, receiving the output of the operational amplifier 11 and the output of the D/A converter 19, produces the sum of these signals, and feeds it to the inverting input terminal of the operational amplifier 12. The noninverting input terminals of the operational amplifiers 11 and 12 are connected to an analog ground voltage. The comparator 17 compares the output of the operational amplifier 12 with the analog ground voltage, and outputs "1" when the output of the operational amplifier 12 is higher than the analog ground voltage. Otherwise, it outputs "0". The 2-value output of the comparator 17, i.e., a "1" or a "0", is delivered to a data input terminal of the flip-flop 18. The clock pulses, the frequency fs of which is more than several tens of times higher than that of the operated signal Va, are supplied through the line 10s. In synchronism with each clock pulse, the data "0" or "1" from the comparator 17 is read into the flip-flop 18. Thus, the operated signal Va (Fig. 2A) is sampled at a high speed in synchronism with the clock pulse fs, and is converted, for instance, into 1-bit digital output Vd, as shown in Fig. 2B. The comparator 17 and the flip-flop 18 are not restricted to a 1-bit circuit. It can be multi-bit circuit. However, in the later description, the 1-bit A/D conversion will be explained for easier understanding of the present invention. The digital signal Vd (Fig. 2B) forms a pulse train having pulse density proportional to the instantaneous value of each sampling of the operated signal (Fig. 2A). The pulse of the digital output Vd takes only discrete duration of 1/fs (second) multiplied by an integer, because the flip-flop 18 operates in response to the clock pulse fs. More particularly, as best shown in Fig. 2B, the pulse density varies in response to the amplitude and polarity of the operated signal Va (Fig. 2A) : the density of "1" increases as the input signal increases toward positive; the density of "1" and "0" are equal when the amplitude is zero, i.e., when no signal exists. The first D/A converter 19 converts the first reference signal into the positive or negative analog signal ±Δ in response to the digital signal supplied from the flip-flop 18, and the analog output ±Δ thus obtained is fedback as a difference signal to the operational amplifiers 11 and 12 through the adders 13 and 14, respectively. As a result, the difference between the current operated signal Va and the analog signal ±Δ corresponding to the digital signal at the previous sampling time is always integrated. When the reference signal to the first D/A converter 19 is Vb, the respective difference outputs fed from the adders 13 and 14 to the operational amplifiers 11 and 12 take the following values: when the output of the flip-flop 18 is "1", the difference outputs take a value of Va - Vb; whereas, when the output of the flip-flop 18 is "0", the difference outputs take a value of Va + Vb. For instance, as shown in Fig. 2C, when the reference signal Vb (= V₁ or V₂) is applied to the first D/A converter 19 through the line 10b shown in Fig. 1, the output Vd from ΔΣ modulator 10 becomes a 1-bit digital signal as shown in Fig. 2D. When the reference signal Vb = V₁, the digital signal (in the left half of Fig. 2D) forms a pulse train with the pulse density proportional to Va/V₁ in response to the values of the operated signal Va (Fig. 2A) and the reference signal Vb = V₁. Likely, when the reference signal Vb = V₂, the digital signal becomes a pulse train with the pulse density proportional to Va/V₂. So far the reference signal Vb has been described as the positive signal (voltage or current). With regard to the negative reference signal, the pulse train can be obtained in a manner substantially similar to that described above. When the reference signal Vb of a constant value is supplied to the first D/A converter 19, the output signal Vd of the ΔΣ modulator 10 forms a pulse train having a pulse density proportional to the operated signal. The output Vd from ΔΣ modulator 10 is delivered to the second D/A converter 20. For the simplicity of the explanation, the operated signal Va inputted to the line 10a is supposed to take values V₁, 0, and -V₂ as shown in Fig. 2E, and the reference signal Vb fed through the line 10b is supposed to be maintained at a constant value. Then, the ΔΣ modulator 10 will produce a pulse train shown in Fig. 2F. Next, consider the case when the sinusoidal signal with a peak value A as shown in Fig. 2G is delivered to the second D/A converter 20 through the line 20c as a reference signal Vc. In response to the "1" or "0" of the digital signal Vd shown in Fig. 2F, the second D/A converter 20 produces the signal Ve shown in Fig. 2H, which is obtained by converting the signal Vc in Fig. 2G into the signal alternately swinging in positive and negative direction. The operation of the second D/A converter 20 is similar to that of the first D/A converter 19, and hence, when the reference signal Vc thereto is maintained constant, the digital output Vd of the ΔΣ modulator 10 is converted into an analog signal directly corresponding to the digital output Vd by the second D/A converter 20. The output Ve of the second D/A converter 20 is delivered to the low-pass filter 30 so that the higher frequency components above the cutoff frequency is suppressed. As the low-pass filter 30, for instance, a conventional passive filter consisting of capacitors and resistors, or an active filter consisting of capacitors, resistors and an operational amplifier can be used. Furthermore, the low-pass filter 30 can be constructed with switched-capacitors. In this case, the aliasing noise problem arises, but the analog arithmetic circuit in accordance with the present invention has an advantage that such problem will never arise. More specifically, the switched-capacitor filter samples the input signal by the sampling clock so that the signal in the frequency band between (the frequency of the sampling clock multiplied by an integer) ± (the frequency of the passband of the filter) are folded back to the passband. In the conventional analog multiplier using a conventional pulse-width modulation circuit, the duration of the output pulses is indefinite as described above, and hence, the frequency spectrum of the output pulses will be spread over the entire band, and the frequency spectrum of the entire band can be folded back. Therefore, in order to prevent such folding back (aliasing noise), an antialiasing filter must be placed at the preceding stage of the switched-capacitor filter, thus suppressing the higher frequency components above the cutoff frequency of the filter. In contrast, according to the embodiment of the present invention, both the sampling clock frequency fs of the ΔΣ modulator 10 and the sampling clock frequency of the switched-capacitors in the low-pass filter 30 are set sufficiently high, i.e., are selected N (an integer more than ten) times higher than the frequencies of the passband. As a result, it is not necessary to place the antialiasing filter at the preceding stage of the switched-capacitor filter. Furthermore, both the first D/A converter 19 and the second D/A converter 20 can be constructed by using the switched-capacitors. Fig. 3 illustrates the first D/A converter 19 arranged by using the switched-capacitor system (the second D/A converter 20 can be arranged in a similar manner). The first D/A converter 19 comprises a first switched-capacitor circuit 21, a second switched-capacitor circuit 22, and a first gate 23 and a second gate 24 connected to the outputs of the circuits 21 and 22, respectively. A reference signal Vb is fed through the line 10b, and the analog output ±Δ (= ± Vb) is produced through an output line 25. The first switched-capacitor circuit 21 comprises a capacitor C2, a pair of switches 1 for discharging the capacitor C2, and another pair of switches 2. The first and second switch pairs 1 and 2 are turned on and off by clocks that do not overlap each other. The second switched-capacitor circuit 22 comprises a capacitor C3, and a first and a second switch pairs 1 and 2 for charging and discharging the capacitor C3, which are arranged in a manner different from the switch pairs 1 and 2 described above. Next, the operation of the first D/A converter 19 will be described in more detail. When the switches 1 are turned on and the switches 2 are turned off, the capacitor C2 is discharged, while the capacitor C3 is charged. In contrast, when the switches 1 are turned off and the switches 2 are turned on, the capacitor C2 is ready to be charged, while the capacitor C3 is ready to be discharged. Assuming that the flip-flop 18 in Fig. 1 in the ΔΣ modulator 10 outputs a 1-bit digital signal, either the first gate 23 or the second gate 24 is selected in response to the output Q or Q . When the output Q is fed, the first gate 23 is turned on so that the reference voltage Vb, charging the capacitor C2, is supplied to the next stage via the output line 25. On the other hand, when the output Q is fed, the second gate 24 is turned on, and the stored charge in the capacitor C3 opposite in voltage to the reference signal Vb is outputted through the output line 25. Thus, the reference signal Vb supplied through the line 10b is converted into a positive or a negative analog signal of a constant magnitude ±Vb, and is outputted through the output line 25 in response to the digital signal Q or Q . Fig. 4A illustrates the ΔΣ modulator 100 using the D/A converter 19 described above with reference to Fig. 3. The ΔΣ modulator 100 comprises a first sampling unit 106 for sampling the operated signal Va, operational amplifiers 102 and 103, feedback capacitors C4 and C6 connected to the operational amplifiers 102 and 103, respectively, a comparator 104, a D flip-flop 105, a first D/A converter 19, a second sampling unit 107, and an adder 108. The operation of the switches 1 and 2, and the output signals Q and Q are substantially similar to those described above with reference to Fig. 3. An operated signal Va supplied through the line 10a charges the capacitor C1 so as to be sampled while the switches 1 in the first sampling unit 106 are turned on. In contrast, when the switches 2 are turned on, the charged (sampled) signal is supplied through an adding point 109 to the operational amplifier 102 in which the operated signal Va is integrated. The output of the operational amplifier 102 charges the capacitor C5 so as to be sampled in the second sampling unit 107 when the switches 1 are turned on. Then, the charged (sampled) signal is supplied to the operational amplifier 103 so as to be integrated when the switches 2 are turned on. When the switches 2 is turned on, the capacitor C7 is charged by the output from the operational amplifier 103, and the capacitor C8 is charged by the output from the operational amplifier 102. Both the outputs of these capacitors are added by the adder 108, and are delivered to the comparator 104 so as to be compared with the ground voltage. In response to the result of comparison, the comparator 104 delivers the output "1" or "0" to the flip-flop 105. This output, which is latched into the flip-flop 105 by the leading edge of the clock pulse having the sampling frequency fs, is produced as a 1-bit digital signal Q and Q . Fig. 4B illustrates a circuit constructed into one body by integrating the second D/A converter 20 and the low-pass filter 30 in Fig. 1 using switched capacitors. A second D/A converter 110 including switched-capacitors 111 and 112 is substantially similar in construction to the first D/A converter 19 described above with reference to Fig. 3. The output from the second D/A converter 110 is delivered to the inverting input terminal of an operational amplifier 113. To the noninverting input terminal thereof, on the other hand, the analog ground voltage is applied. A capacitor C₁₁ and a switched-capacitor 114 are interconnected between the inverting input terminal and the output line 113a of the operational amplifier 113. In response to the output Q or Q from the ΔΣ modulator 10, the second D/A converter 110 supplies the reference signal Vc entering the line 20c to the noninverting input terminal of the operational amplifier 113, either in a noninverting form +Vc or in an inverting form -Vc. Owing to the charging and discharging of the capacitor C₁₀ in response to the ON/OFF of the switches 1 and 2, the switched-capacitor 114 functions as a kind of feedback resistor, and operates as a low-pass filter in conjunction with the switched-capacitor 111 or 112. In short, the reference signal Vc is not reversed or reversed in response to the outputs Q and Q of the ΔΣ modulator 10, and the high frequency component of the reference signal Vc is cut off by the low-pass filter, and then the output signal of the filter is produced from the output line 113a. The analog arithmetic circuit in accordance with the present invention can execute various arithmetic operations such as multiplication, division, expansion, compression and the combinations thereof by supplying an operated or operating signal (analog signal) as a reference signal to at least one of the first and second D/A converters 19 and 20 as will be described hereinafter. 1) Multiplication (Fig. 5): An operated signal Va is fed to the line 10a, an operating signal Vc is fed to the line 20c, and a constant reference signal Vb is applied to the line 10b so that the product Vo = Va × Vc can be obtained from the line 30a. 2) Division (Fig. 6): An operated signal Va is fed to the line 10a, an operating signal Vb is applied to the line 10b, and a constant reference voltage Vc is fed to the line 20c. Then the output Vo = Va/Vb is derived from the output line 30a. 3) Expansion (Fig. 7): An operated signal Va is fed to the line 10a; the signal obtained by processing the operated signal Va by the rectifying-and-averaging circuit 40 (to be described in detail hereinafter) is applied to the line 20c as an operating signal Vc; and a predetermined constant reference voltage Vb is applied to the line 10b. Then the expanded signal Vo of the operated signal Va is obtained from the output line 30a. 4) Compression (Fig. 8): An operated signal Va is delivered to the line 10a; the signal Vb obtained by processing the output signal Vo from the line 30a by the rectifying-and-averaging circuit 50 (to be described in more detail hereinafter) is applied to the line 10b; and a predetermined constant reference voltage Vc is supplied to the line 20c. Then the compression signal Vo of the operated signal Va can be derived from the output line 30a. 5) Multiplication and division: an operated signal Va is applied to the line 10a; an operating signal Vb is supplied to the line 10b; and another operating signal Vc is delivered to the line 20c. Then the result (Va × Vc)/Vb is derived from the output line 30a. 6) AGC (Automatic Gain Control) : an operated signal Va is delivered to the line 10a; the signal obtained by processing the operated signal Va by the rectifying-and-averaging circuit (to be described in detail hereinafter) is supplied to the line 10b as the operating signal Vb; and a predetermined constant reference voltage Vc is applied to the line 20c. Then, the analog signal Vo having a constant amplitude regardless of the average level of the operated signal Va can be obtained from the output line 30a. 7) Combinations of the arithmetic operations: an operated signal Va is delivered to the line 10a; the signal Vb obtained as in 4) above is supplied to the line 10b; and an operating signal Vc is applied to the line 20c. Then, the compression signal Vo of the product (Va × Vc) can be derived from the output line 30a. Furthermore, when an operated signal Va is applied to the line 10a, the signal Vc obtained as in 3) above is supplied to the line 20c, and an operating signal Vb is applied to the line 10b, the output Vo which is the expansion signal of the quotient Va/Vb is derived from the output line 30a. As described above, the analog arithmetic circuit in accordance with the present invention can execute various arithmetic operations. If it is required to supply two or more operating signals to the first or second D/A converter 19 or 20 as a reference signal, it is sufficient to provide another adder so as to obtain the sum total of a plurality of the operating signals. In like manner, when it is necessary to deliver a plurality of operated signals, it is sufficient to provide an adder so as to obtain the sum total of the operated signals. Each of the signals delivered to the lines 10a, 10b and 20c can be a voltage or current signal depending on the construction of the circuit. Practical examples of various arithmetic operations carried out by the analog arithmetic circuit shown in Fig. 1 will be described. MULTIPLIER Fig. 5 is a block diagram illustrating the fundamental construction of the multiplier. A predetermined constant reference signal Vb to be applied to the first D/A converter 19 is generated within the circuit. For example, a sinusoidal operating signal Vc shown in Fig. 2G is supplied as the reference signal to the second D/A converter 20 through the line 20c. When the analog signal shown in Fig. 2E is delivered to the line 10a as an operated signal Va, a pulse train Ve shown in Fig. 2H with the pulse density corresponding to the product Va × Vc is produced in response to the clock pulses fs transmitted through the line 10s, and is delivered to the low-pass filter 30 which suppresses the high frequency component. Thus, the product output Vo (= Va × Vc) shown in Fig. 2I is derived from the output line 30a. DIVIDER Fig. 6 is a block diagram illustrating a basic construction of a divider. A predetermined constant reference signal Vc generated in the circuit is applied to the second D/A converter 20, and the operating signal Vb in the form of an electric current shown in Fig. 2C are delivered to the line 10b as a reference signal for the first D/A converter 19. When a sinusoidal waveform having an amplitude A as shown in Fig. 2A is delivered to the line 10a as an operated signal Va, the pulse train Vd with the pulse density proportional to Va/Vb (= A/V₁ or A/V₂) as shown in Fig. 2D is delivered to the second D/A converter 20 in synchronism with the clock pulse fs transmitted through the line 10s. The high frequency component is then cut off by the low-pass filter 30, and the quotient Vo (= Va/Vb) shown in Fig. 2J is obtained from the output line 30a. EXPANSION CIRCUIT Fig. 7 is a block diagram illustrating a fundamental construction of an expansion circuit. The operated signal Va transmitted through the line 10a is processed by the rectifying-and-averaging circuit 40 and is delivered through the line 20c to the second D/A converter 20 as the reference signal Vc. On the other hand, a predetermined constant signal Vb is generated in the first D/A converter 19, and is applied thereto. The second D/A converter 20, in response to the digital signal Vd from the flip-flop 18, converts the reference signal Vc into a pulse train with positive and negative pulses representing the polarity and the density of the reference signal Vc. After that, the output signal Ve of the second D/A converter 20 is filtered by the low-pass filter 30, and the expanded signal of the operated signal Va is produced from the output line 30a. Fig. 9 is a block diagram illustrating a basic construction of a rectifying-and-averaging circuit 40 which comprises a rectifier 201, and an averaging circuit 202 connected to the output terminal of the rectifier 201. As the rectifier 201, a full-wave or half-wave rectifier utilizing diodes can be used. The averaging circuit 202 is a kind of low-pass filter, and for instance, as shown in Fig. 9, is constructed by an operational amplifier 205 with a feedback loop consisting of a capacitor C₁₃ and a resistor connected in parallel each other. Fig. 10 illustrates the rectifying-and-averaging circuit 40 which is constructed with switched-capacitors. The construction shown in Fig. 10 uses the outputs from a comparator 203 and an inverter 204 as gate signals instead of using the output Q and Q from ΔΣ modulator 10 which are used as gate signals of the switched-capacitors in Fig. 4B: the rectifying-and-averaging circuit 40 compares the input signal supplied to the input line 40d with the ground voltage by the comparator 203, and produces the gate signals. When the input signal supplied to the input line 40d is positive, the input signal is delivered through a switched-capacitor 207 and a gate 211 to an operational amplifier 205 which transmits and outputs only the low frequency component using a switched-capacitor 208 and a capacitor C₁₇. On the other hand, when the input signal is negative, the output from the comparator 203 is inverted through an inverter 204, and the output gate 210 of the switched-capacitor 206 is turned on. The input signal transmitted through the input line 40d is inverted by using switched-capacitors 206 and 208, the capacitor C₁₇, and the operational amplifier 205, and only the low frequency component is outputted. As described above, the rectifying-and-averaging circuit 40 functions as a rectifying circuit: when the signal entering the input line 40d is positive, it is maintained positive, whereas when the signal is negative, it is reversed to positive. In such a way, the rectifying-and-averaging circuit 40 accomplishes the rectification, and in addition, delivers the low frequency component, thereby accomplishing the averaging operation. Incidentally, the cutoff frequency of the low-pass filter is preferably lower than that of the low-pass filter shown in Fig. 4B. Referring back to Fig. 7, when an analog signal with the maximum amplitude X shown in Fig. 11 A is delivered to the line 10a as an operated signal Va, the output Vd from the ΔΣ modulator 10 takes a form of a pulse train with the pulse density proportional to the operated signal Va of Fig. 11A as shown in Fig. 11B. The operated signal Va with the maximum amplitude X shown in Fig. 11A is also delivered to the rectifying-and-averaging circuit 40 so that the analog signal output Vc with the amplitude α (not shown) can be derived. The output Ve of the second D/A converter 20 takes a pulse-shaped waveform shown in Fig. 11C, the pulse density of which is proportional to the amplitude of the operated signal Va with the maximum amplitude X, and the amplitude of which is equal to the amplitude α of the output Vc from the rectifying-and-averaging circuit 40. The output Ve thus obtained is transmitted through the low-pass filter 30. As a result, the output signal shown in Fig. 11D, the wave shape of which is substantially similar to that of the operated signal Va in Fig. 11A, and the amplitude of which is x, is obtained from the low-pass filter 30. Next, when the operated signal Va with the maximum amplitude Y (see Fig. 11A) is delivered to the input line 10a, the amplitude of the output Vo from the rectifying-and-averaging circuit 40 takes a value β, and the above-mentioned values X, Y, α and β have the following relation: Y/X = β / α In addition, the pulse density of the output Vd of ΔΣ modulator 10 varies to (Y/X) times the previous density. Incidentally, the pulse train shown in Fig. 11B is drawn as if the pulse density thereof were not varied, but in practice, the pulse density varies. Hence, the amplitude of the operated signal Va with the maximum amplitude Y, when it has passed through the low-pass filter 30, is increased by the ratio expressed by the following equations: y/x = (β / α)·(Y/X) = (Y/X)·(Y/X) = (Y/X) 2 . This is because, in the case of the analog signal Va with the amplitude Y, the input signal Vc fed from the rectifying-and-averaging circuit 40 to the second D/A converter 20 is increased by the factor β / α, and at the same time the pulse density of the pulse train Vd fed from the flip-flop 18 to the second D/A converter 20 is increased by the factor Y/X, compared with the analog signal Va with the maximum amplitude X. As a result, the ratio between these two output signals from the low-pass filter 30 becomes a square of the ratio of the maximum amplitudes of the original input signals. So far it has been described that X and Y have their respective constant amplitudes, so that α and β are maintained constant. However, if each X and Y represents an arbitrary amplitude of the operated signal Va, α and β have the amplitudes and pulse density in accordance with the amplitudes X and Y. Thus, the above-mentioned relation can be maintained, and hence, the dynamic range of the input signal is expanded, whereby the function of the expansion circuit is accomplished. COMPRESSOR Fig. 8 is a block diagram illustrating a basic construction of a compressor. The operated signal Va is transmitted through the input line 10a. The analog output signal Vo produced from the output line 30a is further processed by a rectifying-and-averaging circuit 50, and is delivered through the line 10b to the first D/A converter 19 as the reference signal Vb. The predetermined constant reference signal Vc is generated within the second D/A converter 20, and is supplied thereto. As the rectifying-and-averaging circuit 50, a circuit similar to that used in the expansion circuit described above can be used. In Fig. 8, the operated signal Va with the maximum amplitude A shown in Fig. 2A is applied to the input line 10a, and the signal with the amplitude B (to be described in detail hereinafter) is delivered to the first A/D converter 19 as the reference signal Vb. Then the ΔΣ modulator 10 outputs a pulse train Vd with the pulse density proportional to A/B as shown in Fig. 2D. When the signal thus obtained is transmitted through the second A/D converter 20 and the low-pass filter 30, the signal with the maximum amplitude C shown in Fig. 2K is obtained. In this case, when the signal Vo shown in Fig. 2K is transmitted through the rectifying-and-averaging circuit 50, the reference signal Vb with the amplitude B is obtained. The above-mentioned amplitude C is proportional to A/B, and in addition B is proportional to C so that the following equation is obtained: C = K 1 ·(A/B) = K 1 ·A·(1/K 2 ·C) and the above equation can be transformed into C = K 1 /K 2 · √A Therefore, the analog output signal Vo derived from the output line 30a is proportional to the root of the operated signal Va entering the input line 10a. Thus, the dynamic range (represented by logarithm) of the operated signal Va can be compressed by one half. When the operated signal Va entering the input line 10a approaches zero, the output signal Vo derived from the output line 30a also approaches zero. As a result, the reference signal Vb applied to the first D/A converter 19 also approaches zero so that the stable operation cannot be ensured. To prevent this, a minimum-output-setting circuit 300 shown in Fig. 12 is provided in addition to the rectifying-and-averaging circuit 50. When the output of the rectifying-and-averaging circuit 50 declines below the output of the minimum-output-setting circuit 300, the input Vb to the first D/A converter 19 is switched from the output of the rectifying-and-averaging circuit 50 to the output of the minimum-output-setting circuit 300 by means of a comparator 301 and a switch 302. Thus, the above-described unstable operation can be avoided. The minimum-output-setting circuit 300 shown in Fig. 12 will be described in more detail hereinafter. The ΔΣ modulator 10, the second D/A converter 20, the low-pass filter 30 and the rectifying-and-averaging circuit 50 are arranged in a manner substantially similar to those described hereinbefore. The output voltage of the minimum-output-setting circuit 300 is determined to a voltage at which the operation of the arithmetic operation circuit becomes unstable because of the decline of the output of the rectifying-and-averaging circuit 50. In this case, the voltage set by the circuit 300 is assumed to be, for instance, 10 mV. The comparator 301 compares the output of the rectifying-and-averaging circuit 50 with the output voltage derived from the minimum-output-setting circuit 300. When the output voltage from the rectifying-and-averaging circuit 50 declines below 10 mV, in response to the signal from the comparator, the input signal Vb applied to the input line 10b of the first D/A converter 19 (Fig. 8) is switched from the output of the rectifying-and-averaging circuit 50 to the output of the minimum-output-setting circuit 300. When the output signal of the minimum-output-setting circuit 300 is delivered to the input line 10b, the output of the analog arithmetic circuit is proportional to the operated signal Va, and its operation is stabilized. The lower the output voltage produced from the minimum-output-setting circuit 300, the wider the compression region, and the narrower the proportional region. This will make the operation more unstable. In contrast, the higher output voltage of the minimum-output-setting circuit 300 makes the operation more stable, although the compression region is made narrower. As described above, according to the present invention, ΔΣ modulator, the D/A converters and the low-pass filter are utilized. As a reference signal for the first and/or second D/A converters, an operating signal is applied to one or both of the converters so that various arithmetic operations such as multiplication, division, expansion, compression and the combinations thereof can be executed. Furthermore, the present invention can provide an analog arithmetic circuit which is simple in construction ahd can be made compact in size in the form of an LSI. Moreover, a common circuit can provide various arithmetic circuits so that the data associated with the circuit can be collected as a library. This makes it possible to shorten the time for designing the analog arithmetic circuit, and in addition, to systematize the design in conjunction with other circuits.

Claims: An analog arithmetic circuit which receives an operated signal (Va) and an operating signal and outputs the results of an arithmetic operation, said analog arithmetic circuit comprising: ΔΣ modulation means (10) having A/D conversion means (11-18) and first D/A conversion means (19), said A/D conversion means (11-18) sampling said operated signal (Va) at a sampling rate determined by a clock signal (CLK) with a predetermined sampling frequency (fs) significantly higher than the maximum frequency of the operated signal (Va) thereby outputting a digital signal (Vd), and said first D/A conversion means (19) receiving said digital signal (Vd) outputted from the A/D conversion means 11-18) and a first reference signal (Vb), said first D/A conversion means (19) serving to convert the first reference signal (Vb) into a first analog signal (±Δ) which takes a positive or negative amplitude in response to said digital signal (Vd), the first analog signal being fed back to said A/D conversion means (11-18) a second D/A conversion means (20) for receiving said digital signal (Vd) and outputting a second analog signal (Ve) in response to a second reference signal (Vc), said second analog signal (Ve) alternating between positive and negative values in response to said second reference signal (Vc) and low-pass filtering means (30) for receiving said second analog signal (Ve) and outputting an analog signal (Vo) representing the result of an arithmetic operation, wherein at least one of said first reference signal (Vb) or said second reference signal (Vc) is selected as said operating signal. An analog arithmetic circuit as claimed in claim 1, wherein the digital signal (Vd) outputted from said ΔΣ modulation means is a 1-bit digital signal. An analog arithmetic circuit as claimed in claim 1 or 2, wherein each of said first and second D/A conversion means (19,20) comprises switched capacitor circuits (21,22,111,112). An analog amplifier circuit as claimed in any one of claims 1 to 4, wherein said low-pass filtering means (30) comprises an operational amplifier (113) and a switched capacitor circuit (114). An analog arithmetic circuit as claimed in any one of claims 1 to 4, wherein said second reference signal (Vc) is inputted as said operating signal, and said analog arithmetic circuit produces a signal representative of a product of said operated signal (Va) and said operating signal (Vc). An analog arithmetic circuit as claimed in any one of claims 1 to 4, wherein said first reference signal (Vb) is inputted as said operating signal, and said analog arithmetic circuit produces a signal representative of a quotient obtained by dividing said operated signal (Va) by said operating signal (Vb). An analog arithmetic unit as claimed in claim 5, wherein said operating signal (Vc) is a signal obtained by rectifying and averaging said operated signal (Va). An analog arithmetic circuit as claimed in claim 6, wherein said operating signal (Vc) is a signal obtained by rectifying and averaging said quotient signal. An analog arithmetic circuit as claimed in claim 8, further comprising selecting means (301,302) for selecting a predetermined value as said operating signal instead of selecting said rectified and averaged output when said rectified and averaged output declines less than a predetermined output value. An analog arithmetic circuit as claimed in claim 7, 8 or 9, wherein the rectifying and averaging operation is carried out by using switched capacitors (206,207,208) a comparator (203) and an operational amplifier (205).

Inventors: TAKAHASHI KEN ICHI, TAKASUKA KAORU, TAKAHASHI, KEN'ICHI, TAKASUKA, KAORU
Applicants: ASAHI CHEMICAL MICRO SYST, ASAHI KASEI MICROSYSTEMS CO., LTD.
Application year: 1989
Main classification: G06G7
IPC codes: H03M3, H03G7, G06F1, G06G7