Wrist watch

Abstract: A wrist watch comprises an AC generator (1,17,18, 19), a rectifier circuit (2) for rectifying the output of the AC generator, and a re-chargeable secondary power supply (3) for storing the rectified output. Auxiliary re-chargeable means (10) for operating a clock circuit (12) are chargeable from the output of the re-chargeable secondary power supply by way of charging control means (6,7,11,15,16) which are arranged such that the output of the auxiliary re-chargeable means is enlarged relative to the output of the re-chargeable secondary power supply over a range of values for the output of the re-chargeable secondary power supply.

Description: The present invention relates to a wrist watch. In wrist watches employing batteries, considerable attention has been given to extending the life time of the batteries. However, the size of a battery which can be incorporated in a wrist watch is naturally limited. As one means for solving the problem, an electronic wrist watch has been proposed in which a solar battery is provided on a display face, for example a dial, and in which either a secondary battery or a charging capacitor is charged by means of the solar battery for driving a clock circuit. Such a wrist watch is disclosed in U. S. Patent No. 4,653,931. With this arrangement, however, since a black or blue solar battery is disposed on the dial, the design is limited and is therefore not suitable for electronic watches which attract purchasers by their design. Another prior proposal for a wrist watch features an AC generator, and a clock circuit driven by the power generated therefrom. In the case of AC electromotive force, however, a rectifier circuit is needed. It has been considered that the most efficient rectifier circuit is one which performs full wave rectification by means of a diode bridge that employs four diodes, but it has heretofore been difficult to incorporate four diodes in the small space inside a wrist watch. Further, in order for the clock circuit to operate continuously without any error even when the generator is in an inoperative state, it is necessary to store the generated power in either a secondary battery or a capacitor and to drive the clock circuit continuously by the output thereof. However, the range of operating voltages of the clock circuit is limited, so that the watch is not activated until the secondary power supply (hereinafter used as a general term for both a secondary battery and a capacitor) is charged such that the voltage thereof exceeds the lower limit of the operating range of the clock circuit. If the capacity of the secondary power supply is decreased in order to shorten the time required to charge the secondary power supply, the above described problem is solved to a certain extent. However, another problem arises instead, namely that the time available before the voltage drops below the lower limit of the operating range of the clock circuit when the generator is in an inoperative state is reduced. The present invention at least in its preferred form aims to solve the above described problems in regard to re-chargeable wrist watches employing AC generators. According to the present invention there is provided a wrist watch having: an AC generator; a rectifier circuit for rectifying an output from the AC generator; a re-chargeable secondary power supply for storing the rectified output for operating a clock circuit; auxiliary re-chargeable means chargeable from the output of the re-chargeable secondary power supply for operating the clock circuit; and charging control means for controlling the charging of the auxiliary re-chargeable means such that the output of the auxiliary re-chargeable means is enlarged relative to the output of the re-chargeable secondary power supply for a given range of values for the output of the re-chargeable secondary power supply when the output of the rechargeable secondary power supply has a value above a first predetermined reference value; characterised in that said charging control means comprises means selectively connected to said re-chargeable secondary power supply for enlarging the output thereof when the output of the re-chargeable secondary power supply has a value below a predetermined lower limit whereby the enlarged output exceeds the threshold at which the wristwatch will operate. The charging control means may comprise a resistor connected in series with the re-chargeable secondary power supply and further comprising means, responsive to the output of the re-chargeable secondary power supply, for providing a by pass to the resistor when the value of the output of the re-chargeable secondary power supply exceeds the predetermined lower limit. Preferably, the charging control means may also comprise a booster circuit for boosting the output of the re-chargeable secondary power supply for generating an enlarged charging signal for charging the auxiliary re-chargeable means. The invention is described further, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a general circuit diagram of an electronic wrist watch according to the present invention; Figure 2 is a diagrammatic view of an AC generator of the wrist watch; Figure 3 (A) is a diagram showing a half wave rectifier circuit according to the present invention, included in the wrist watch; Figure 3(B) is a comparative diagram showing a full wave rectifier circuit according to the prior art; Figure 4 is a current waveform diagram; Figure 5 (A) is a circuit diagram showing a limiter circuit according to the present invention included in the wrist watch; Figure 5 (B) is a circuit diagram showing a limiter circuit according to the prior art; Figure 6 (A) shows a conventional limiter circuit that employs a PNP type transistor; Figure 6 (B) shows a conventional limiter circuit that employs an NPN type transistor; Figure 7 (A) show a modified limiter circuit according to the present invention that employs a PNP type transistor; Figure 7 (B) shows a further modified limiter circuit according to the present invention that employs an NPN type transistor; Figure 8 shows a limiter circuit according to the present invention in a full wave rectifier circuit; Figure 9 is a voltage diagram illustrating the operation of a multi-stage booster circuit of the wrist watch; Figure 10 is a detailed circuit diagram of the multi-stage booster circuit; Figure 11 is a chart showing a method of storing boosting factors in the circuit; Figure 12 is a timing chart of the signals generated in the multi-stage booster circuit; Figure 13 is a diagram showing equivalent capacitor connection circuits of the multi-stage booster circuit, corresponding to the timing situations of Figure 12; Figure 14 is a detailed circuit diagram of an auxiliary capacitor voltage detecting circuit of the wrist watch; Figure 15 is a timing chart of the signals generated in the circuit shown in Figure 14; Figure 16 is a detailed circuit diagram of an immediate start circuit of the wrist watch; Figure 17 is a diagram of a sampling signal generating circuit of the wrist watch; Figure 18 is a timing chart of the signals generated in the sampling signal generating circuit; and Figure 19 is a schematic view showing changes in the voltage of an auxiliary capacitor of the wrist watch at the time when an immediate start state is cancelled. Referring initially to Figure 1, the reference numeral 1 denotes a coil of an AC generator, arranged such that an AC induced voltage is generated there-across in use. The reference numeral 2 denotes a rectifier diode, which subjects the AC induced voltage to half wave rectification and charges a high capacitance capacitor 3. The reference numeral 4 denotes a limiter transistor for preventing over charge of the capacitor 3, the limiter transistor 4 being arranged to turn on when the voltage V sc of the capacitor 3 (the voltage value of the capacitor 3 being hereinafter defined as V sc ) reaches a predetermined voltage V lim so as to bypass the power generated in the generator coil 1. The voltage V lim is set so that it is above the maximum value of the "voltage required in a clock circuit 12 and within the range of the rated voltage of the capacitor 3. The reference numeral 5 denotes a reverse current preventing diode for preventing a reduction in the generation efficiency which would otherwise be caused by an increase in electro-magnetic brake force in the generator due to a reverse current, which will be described later. The reference numeral 7 denotes a multi-stage booster circuit arranged to transfer the charge in the capacitor 3 to an auxiliary capacitor 10 by switching the connections between booster capacitors 8, 9, the capacitor 3 and the auxiliary capacitor 10, boosting the voltage at the same time. The multi-stage booster circuit 7 selectively provides four different boosting factors, that is 3-times, 2-times, 1.5-times and 1-time. The boosted voltage is applied to the auxiliary capacitor to charge it. The clock circuit 12 is operable at the voltage V ss of the auxiliary capacitor 10 (the voltage value of the auxiliary capacitor 10 being hereinafter defined as V ss ). Employment of such a multi-stage booster circuit 7 enables optimisation of the operation of the clock circuit 12. The reference numeral 11 denotes a V ss detecting circuit for detecting the voltage of the auxiliary capacitor 10. The reference voltage that is employed in the V ss detecting circuit 11 has two values V up and V down which are related to each other as follows: V up < V down The V ss detecting circuit 11 outputs the result of detection to the multi-stage booster circuit 7 in such a manner that, when V ss exceeds V down the boosting factor is lowered whereas when V down is below V up , the boosting factor is raised. The clock circuit 12 includes an oscillation circuit for driving a crystal oscillator 13 having an original frequency of 32,768 Hz, a frequency divider, and a drive circuit for driving a motor coil 14. The dock circuit 12 is operable at the voltage V ss . The motor coil 14 is provided to drive a stepping motor for rotating a watch hand. A shorting transistor 15 and a series resistor 16 constitute in combination an immediate start circuit which is arranged such that, when V sc is lower than a predetermined voltage V ON , an immediate start operation is performed, which will be described later in detail. A V sc detecting circuit 6 detects that V sc has reached the above described V lim or V on The relationship between these voltage and the above described V up and V down is as follows: V on < V up < V down < V lim . In the foregoing, the circuit has been briefly explained. The following is a detailed description of the operation of each of the sections and effects thereof. The principle of the AC generator that is used in this embodiment will first be explained with reference to Figure 2. The reference numeral 115 denotes a means for generating rotational torque comprising an oscillating weight in which the centre of rotation and the centre of gravity are eccentric with respect to each other. The rotation of the oscillating means 115 is arranged, by way of a speed increasing wheel train 116, to cause rotation of a rotor 17 forming part of the AC generator. The rotor 17 includes a permanent magnet 17a. A stator 18 is disposed in such a manner as to surround the rotor 17. The coil 1 is wound on a core 19a. The core 19a and the stator 18 are rigidly secured to each other by means of screws 20. Rotation of the rotor 17 induces in the coil 1 an electro-motive force which is expressed as follows: e = N dø dt and a current is produced which is expressed as follows: where N is the number of turns of the coil ø is the magnetic flux passing through the core 19a t is time R is the resistance of the coil W is the speed of rotation of the rotor 17 L is the inductance of the coil. This electro-motive force is an alternating voltage represented by a substantially sine shaped curve. The rotor 17 and the stator 18 that surrounds it define concentric circles, the stator 18 surrounding the rotor magnet over substantially the entire circumference. Thus, it is possible to minimise any force (attractive torque) which acts so as to stop the rotor at a certain position. The AC voltage which is obtained from such an AC generator is rectified, to charge the capacitor 3, by means of a half wave rectification circuit, shown in Figure 3 (A), which employs a simpler diode arrangement than is conventionally used in a wrist watch. A combination of the generator shown in Figure 2 and the half wave rectification circuit of Figure 3 (A) enables the same level of generation efficiency to be obtained as in the case of a conventional full wave rectification arrangement illustrated in Figure 3 (B). The reasons for this will be explained below. In Figures 3 (A) and 3 (B), as in Figure 1, the reference numeral 1 denotes the generator coil, the numeral 3 denotes the capacitor, and the numerals 2, 2a to 2d denote rectifier diodes. In the half wave rectifier circuit shown in Figure 3 (A), only one diode is interposed in the charging loop whereas, in the full wave rectifier circuit shown in Figure 3 (B), two diodes are interposed in the charging loop. Accordingly, the potential difference across the diodes in the full wave rectifier circuit is twice that in the half wave rectifier circuit Figure 4 shows comparatively the current waveforms obtained by the two rectifier circuits. The reference numeral 24 denotes a reference line, the numeral 25 denotes a curve representing the current generated in a conventional rectifier circuit, the numeral 26 denotes a curve representing the current generated in the present invention, numeral 27 denotes a line representing the loss due to the voltage drop in the conventional rectifier circuit, and the numeral 28 denotes a line representing the loss due to the voltage drop in the rectifier circuit according to the present invention. In the prior art, the amount of charge stored in the capacitor 3 corresponds to the area bounded by the lines 25 and 27 whereas, in the present invention, the amount of charge stored in the capacitor 3 corresponds to the area bounded by the lines 26 and 28. Comparing these areas, there is substantially no difference, and the accumulation performances in both cases are equivalent to each other. The reason why there is no difference in terms of the accumulation performance between the conventional full wave rectifier circuit and the half wave rectifier circuit will be explained below. During the period (denoted by the reference numeral 29 in Figure 4) when the current is cut off in the half wave rectifier circuit, no current flows through the coil 1. Accordingly, the brake torque applied to the rotor 17 is small, so that the movement of the oscillating weight is accelerated. More specifically, during the period 29, energy is stored, in the form of the kinetic energy of the oscillating weight, and it is released when power is generated. For this reason, the peak value of the curve 26 is greater than that of the curve 25. Also, the fact that two diodes are reduced to one, that is, the number of diodes required is halved, has an advantageous effect on reduction in the rectification loss. As a result, despite the half wave rectification, the generation and accumulation performances of the invention are not inferior to those in the case of the full wave rectification. As has been described above, it is possible according to the present invention to obtain satisfactory generation performance even by means of half wave rectification and to reduce by a large margin the number of diodes required, that is, from four diodes in the case of the diode bridge system to a single one. This has considerable advantages in terms of both space efficiency and cost. Next, the arrangement of the limiter transistor 4 will be described. Figure 5 (A) shows the limiter arrangement according to the present invention, while Figure 5 (B) shows a general limiter arrangement which has heretofore been employed. The limiter transistor 4 for bypassing the current when in an operative state is constituted by a P channel MOSFET. This is because ICs for watches necessitate a low power consumption as a necessary condition and are therefore produced using the CMOS process. More specifically, the limiter transistor 4 is fabricated in the form of a MOSFET within an IC, which is more advantageous, in terms of both space efficiency and cost, than the case where an external element is provided outside the IC. In the conventional arrangement, the limiter transistor 4 is connected in parallel with the capacitor 3 such that, when the limiter transistor 4 turns on, the charge stored in the capacitor 3 is undesirably discharged through the path shown in Figure 5 (B) by the chain line 30. The limiter transistor 4 is provided for the purpose of preventing over charging of the capacitor 3 and in the prior art the limiter transistor 4 is indeed arranged to discharge excess charge from the capacitor 3. Therefore, it would seem that there is no problem in the prior art arrangement However, if the limiter transistor 4 is left turned on, the capacitor 3 discharges more than it need. In order to avoid this problem, it is necessary to monitor constantly the voltage value of the capacitor 3 and to turn off the limiter transistor 4 immediately when V sc is below V lim . However, if the voltage detecting circuit is constantly activated, the amount of current consumed in a reference voltage generator and a comparator within this circuit increases by a large margin. The prior art has another disadvantage that, when the limiter transistor 4 is turned on, a high voltage of the capacitor 3 is applied directly to the limiter transistor 4 and a large current flows through the same. In order to prevent breakdown of the transistor 4, it must have an extremely large size, and this leads to an increase in the IC size, which is disadvantageous in terms of the cost. To solve the above described problems, the limiter circuit according to the present invention is additionally provided with a reverse current preventing diode 5, as shown in Figure 5 (A). With this arrangement, even when the limiter transistor 4 turns on, there is no possibility of the capacitor 3 being discharged, due to the presence of the rectifier diode 2. Accordingly, even after V sc has reached V lim , V sc varies only at a rate corresponding to the rate of consumption of charge in the clock circuit 12, i.e. at a rate following a gently decreasing curve, so that it is unnecessary to activate the V sc detecting circuit 6 at all times. In other words, it is only necessary to drive the V sc detecting circuit 6 intermittently in a sampling manner and hence it is possible to minimise the increase in the consumption of current resulting from operation of this circuit Further, there is no fear of a large current flowing through the transistor 4 so that the transistor size does not have to be increased more than is necessary. The chain line 31 shows the direction of the current bypassed by the limiter transistor 4. It is only necessary to cut off the supply of current after V sc has reached V lim . The reference numeral 52 denotes a parasitic diode formed between the substrate and the drain of the limiter transistor 4. If there were no reverse current diode 5, a current would flow in the direction reverse to the chain line 31 during the generation of power even when the limiter transistor 4 were off. In such a case, the brake torque of the generator would increase, as described in the paragraph explaining the rectifier circuit, resulting in a lowering of the generation efficiency. In order to prevent this, the reverse current preventing diode 5 is added. Thus, various effects, such as a lowering in power consumption obtained by the intermittent activation of the voltage detecting circuit 6, a reduction in the size of the limiter transistor 4 and an improvement in the generation performance, are produced simply by adding the reverse current preventing diode 5 and changing the connection arrangement of the limiter transistor 4. The arrangement of the limiter circuit according to the present invention is also effective in the case where a bi-polar transistor is employed to constitute a switching element. Figure 6 shows a conventional limiter circuit in which a bi-polar transistor is employed to constitute a switching element and no reverse current preventing circuit is provided. Figure 6 (A) shows an arrangement in which a PNP type bi-polar transistor is employed, while Figure 6 (B) shows an arrangement in which a NPN type bi-polar transistor is employed. Referring first to Figure 6 (A), in this arrangement even when the PNP type transistor 44 is off, a reverse current 46 (shown by the chain line) undesirably flows through a diode 44b, formed between the collector and the base of the transistor 44, and through a switching control circuit 45. The switching control circuit 45 ensures that the base of the PNP type transistor 44 is placed at a high potential (the same potential as the emitter of the PNP type transistor 44) in order to turn off the PNP type transistor 44. Accordingly, there exists a current path through the switching control circuit 45 which enables the reverse current shown by the chain line 46 to flow undesirably. Similarly, in the case of the arrangement shown in Figure 6 (B), a reverse current 49 (shown by the chain line) undesirably flows through a current path which includes a diode 47a, formed between the base and the collector of an NPN type transistor 47, and a switching control circuit 48. Therefore, according to another embodiment of the present invention shown in Figure 7, a reverse current preventing diode 5 is arranged in series with either the bi-polar transistor 44 or 47, whereby it is possible to form a limiter circuit, without lowering the generation performance, by cutting off the reverse current. This arrangement of the limiter circuit according to the present invention is also effective in a full wave rectifier circuit that employs a diode bridge. One embodiment thereof is shown in Figure 8. When the voltage induced in the generator coil 1 has a higher potential at the lower end thereof, as shown in Figure 8, the current normally flows through the path shown by the chain line 50. Assuming that the reverse current preventing diode 5 is not provided, the current undesirably flows through the path shown by the chain line 51 through a parasitic diode 52 even when the limiter transistor 4 is off, so that the current from only one side of the full wave rectifier circuit is stored in the capacitor 3. As a result, the charging performance is halved. Accordingly, the addition of the reverse current preventing diode 5 according to the present invention is also effective in the case of full wave rectification. A specific example of the multi-stage boosting will now be described with reference to Figure 9. The abscissa represents time, while the ordinate represents the voltage. The voltage V sc of the capacitor 3 is shown by a chain line and the voltage V ss of the capacitor 10 is shown by a solid line. The above described V ON , V up , V down and V lim are set as follows: V ON = 0.4 V V up = 1.2 V V down = 2.0 V V lim = 2.3 V. During the time interval from t 0 to t 6 , the generator is mainly in an operative state, i.e. this time interval is defined as a charging period, whereas, during the time interval after t 6 , the generator is assumed to be in an inoperative state, i.e. this time interval is defined as a discharging period. It should be noted that, although in Figure 9 both the charging and discharging periods are drawn on the basis of the same time scale, in actual practice the charging period is of the order of several minutes while the discharging period is of the order of several days. In the time interval from t 0 to t 1 and after the time t 10 , the circuit is in an immediate start state, which will be described later. From the time t 1 at which V sc (which is increasing) exceeds 0 .4 V, a 3-times boosting state is commenced so that a voltage of V sc x 3 is stored as V ss . As the charging continues further, V ss reaches 2.0 V at the time t 2 . Then, the boosting factor is stepped down by one level to 2-times. Thereafter, as the charging progresses further, V ss reaches 2.0 V at each of the times t 3 and t 4 . Thus, every time V ss reaches 2.0 V, the boosting factor is stepped down by one level: i.e. 3-times boosting occurs during the time interval from t 1 to t 2 ; 2-times boosting occurs from t 2 to t 3 ; 1.5-time boosting occurs from t 3 to t 4 ; and 1-times boosting occurs from t 4 to t 7 . It should be noted that, during the 1 -times boosting period, the voltage rises in such a manner that V sc = V ss and during this period, even when V ss reaches 2.0 V, the boosting factor is not changed. During the time interval from t 5 to t 6 when the voltage has risen to 2.3 V (i.e. V sc = V ss = 2.3 V), the limiter transistor 4 is turned on to prevent the voltage from rising above 2.3 V. During the discharging period after t 6 , the boosting factors are changed over from one to another at 1.2 V. More specifically, as the voltage lowers so that V ss = 1.2 V, the boosting factor is stepped up by one level to 1.5-times. Thereafter, every time V ss reaches 1.2 V, the boosting factor is stepped up by one level: i.e. 1.5-times boosting occurs during the time interval from t 7 to t 8 ; 2-times boosting occurs from from t 8 to t 9 ; and 3-times boosting occurs from t 9 to t 10 . Employment of such a boosting system enables V ss , which is the voltage of the power supply for driving the watch to be constantly maintained at 1.2 V or more under the condition of V sc ≧ 0.4 V, thus extending the operating time of the watch. It should be noted that V up (1.2 V) is set at the lowest operating voltage for the stepping motor for advancing the wrist watch hand. If the arrangement was such that no boosting was effected and V sc was employed as a driving voltage, the watch would operate only during the period when V sc = 1.2 V or more, i.e. from t 11 to t 7 , and during the charging period, the time required for the watch to start would be long, whereas, during the discharging period, the time elapsed until the watch stopped would be short, resulting in a watch which is unfavourable to the user. It should be noted that, since V ON (0.4 V) is a voltage at which 3-times boosting is started, it is obvious that V ON is set so as to satisfy the condition of V ON x 3 ≧ V up . V lim (2.3 V) is set at 2.3 V with some allowance being made because the breakdown voltage of the capacitor 3 used in this embodiment is 2.4 V. The change over of the boosting factors is effected by the comparison of V s with V up and V down with a view to obtaining the following effects. There are three detection voltages which contribute to the change over of the boosting factors in the present invention, i.e. V ON , for the change over between the immediate start and the 3-times boosting, and the above described V up and V down whereas an arrangement in which the change over of the boosting factors is effected by voltage detection of V sc needs four detection voltages. More specifically, in such an arrangement it is necessary to set detection voltages for four change over points, respectively, i.e. between immediate start and 3-time boosting, between 3-times boosting and 2-times boosting, between 2-times boosting and 1.5-times boosting, and between 1.5-times boosting and 1-times boosting. Thus, in order to ensure that V ss obtained by boosting V sc will be equal to or higher than V up (1.2 V), it is necessary to provide detection voltages as follows: Immediate start <-> 3-times boosting ... 0.4 V 3-times boosting <-> 2-times boosting ... 0.6 V 2- times boosting <-> 1.5-times boosting .. 0.8 V 1.5-times boosting <-> 1-times boosting .. 1.2 V According to the present invention, however, it is possible to decrease by one the number of detection voltages required and to reduce the chip area of the IC correspondingly. Further, even when the lowest level of the operating voltage of the watch is changed for reasons of design or operation, it is only necessary in the present invention to change the values of two detection voltages, that is V ON (0.4 V) and V up (1.2 V), whereas in an arrangement in which the boosting change over is effected by detection of V sc , the four detection voltages require changing. More specifically, when adjustment of detection voltages is effected by using detection voltage adjusting terminals led out from the IC, a relatively large number of adjusting terminals are generally required; however, it is possible according to the present invention to reduce the number of such adjusting terminals and hence prevent increase in the chip area of the IC. Further, although in the described embodiment of the present invention, the multi-stage booster circuit has four values for the boosting factor, it is possible by increasing the number of boosting capacitors 8 and 9, which is two in the present invention, to three to set eight values for the boosting factor i.e. 1-times, 1 1/3-times, 1.5-times, 1 2/3-times, 2-times, 2.5-times, 3-times and 4-times. Although the system wherein the boosting factors are changed over from one to another by the detection of V sc needs the provision of detection voltages for all the above described values, it is unnecessary in the present invention to provide any additional detection voltage. Thus, the present invention enables the booster circuit to be readily graded up. Next, a specific arrangement of the multi-stage booster circuit 7 will be described with reference to Figure 10. Tr1 to Tr7 denote FETs for switching the connection between the capacitors. The FETs are switched ON/OFF under the control of a boosting clock having a 1 kHz cycle. The chain line block 32 represents a known up/down counter. The four boosting factors are held in the form of combinations of the 2 bit outputs S A and S B of the up/down counter 32. Figure 11 shows the relationship between S A , S B and the boosting factors. M up , which is input to the up/down counter 32, is a signal output from the V ss detecting circuit 11 in the form of a dock pulse when V ss is below V up (1.2 V), with "0" being defined as being active. Similarly, M down is a clock pulse which is output when V ss exceeds V down (2.0 V). In this way, the boosting factors are changed over from one to another in accordance with the output of the V ss detecting circuit 11. The expressions "0" and "1" will be hereinafter used to explain logic signals. "0" refers to the -side (the V ss side) of the auxiliary capacitor 10, while "1" refers to the +side (the V DD side) of the auxiliary capacitor 10. The reference numeral 33 denotes a boosting reference signal generating circuit which outputs boosting reference signals CL1 and CL2 on the basis of standard signals ⊘1 K and ⊘2KM which are output from the frequency divider of the dock circuit 12. The reference numeral 34 denotes a switching control circuit which outputs a signal, derived from the above described CL1, CL2, S A and S B , to control switching of Tr1 to Tr7. Figure 12 shows the above described circuit operation for each boosting factor in the form of a timing chart, while Figure 13 shows the circuit operation for each boosting factor in the form of a capacitor connection equivalent diagram. In Figure 12, it signifies, when Trn is 1, that Trn turns on. Figure 12 (A) shows the switching control signals at the time of 1-times boosting, in which Tr1, Tr3, Tr4, Tr5 and Tr7 are constantly turned on. The capacitor equivalent circuit at this time is shown in Figure 13 (A). More specifically, all the capacitors 3, 8, 9 and 10 are connected in parallel, so that the voltage V sc of the capacitor 3 and the voltage V ss of the auxiliary capacitor 10 become equal to each other. Figure 12 (B) shows the switching control signals at the time of 1.5-times boosting. During the interval (a), Tr1, Tr3 and Tr6 are turned on, while during the interval (b), Tr2, Tr4, Tr5 and Tr7 are turned on. Figure 13 (B) shows the capacitor equivalent circuit at the time of 1-times boosting. During the interval (a), the boosting capacitors 8 and 9 are charged with 0.5 x V sc , while during the interval (b), the auxiliary capacitor 10 is charged with the sum of V sc and 0.5 x V sc , i.e. 1.5 x V sc . Similarly, Figures 12 (C) and 13 (C) show the operation during 2-times boosting, in which, during the interval (a), Tr1, Tr3, Tr5 and Tr7 are turned on while, during the interval (b), Tr2, Tr4, Tr5 and Tr7 are turned on. As a result, the auxiliary capacitor 10 is charged with 2 x V sc . Figures 12 (D) and 13 (D) show the operation during 3-times boosting, in which, during the interval (a), Tr1, Tr3, Tr5 and Tr7 are turned on while, during the interval (b), Tr2, Tr4 and Tr6 are turned on. As a result, the auxiliary capacitor 10 is charged with 3 x V sc . The signal "OFF" shown in Figure 10 is 1 when the condition of V sc ≦ 5 V ON (0.4 V) is satisfied, that is, when the system is in an immediate start state. At that time, the output of the boosting reference signal generating circuit 33 is suspended to turn off all of Tr1 to Tr7 so as to effect no boosting. Both the outputs S A and S B of the up/down counter 32 are initially set at 1 so that boosting is started from 3-times boosting when the immediate start is cancelled. Figure 14 shows a specific example of the V ss detecting circuit. SP 1.2 and SP 2.0 are sampling signals. When the signals are "1", the circuit is activated, whereas, when the signals are "0", the circuit is brought into a fixed state so that no current is consumed. The block surrounded by the chain line 35 represents a known constant voltage circuit, the output voltage of which is denoted by V REG . The reference numeral 36 denotes a resistor for detecting V ss , while the numeral 37 denotes a resistor for producing a reference voltage. Each intermediate tap of the resistor 37 is set so that, when V ss = 1.2 V, VM = V REG r 1 r 1 + r 2 + r 3 whereas, when V ss = 2.0 V, VM = V REG r 1 + r 2 r 1 + r 2 + r 3 The reference numeral 38 denotes transmission gates which are arranged to change over detection voltages from one to the other when the circuit is to detect that V ss has reached 1.2 V and when the circuit is to detect that V ss has reached 2.0 V. The reference numeral 39 denotes a comparator by which V ss and the relevant detection voltage are compared with each other. The reference numeral 40 denotes a master latch which latches the output of the comparator 39 in response to the rise of R 1.2 (described below). The reference numeral 41 denotes another master latch which latches the output of the comparator 39 in response to the rise of R 2.0 (also described below) in the same way as in the case of the master latch 40. The reference numeral 42 denotes a known differentiating circuit which outputs either a clock pulse M up or M down when the contents of the master latches 40, 41 change, thereby changing the contents of the up/down counter 32 shown in Figure 10. ⊘8, ⊘64 and ⊘128 are reference signals which are output from the frequency divider. ⊘8 is used to initialise the master latches 40, 41 and the differentiating circuit 42 for subsequent sampling. The above described operation will be explained with reference to the timing chart shown in Figure 15. The first half ofthe Figure is a chart showing the operation conducted in the case of V ss > 2.0 V, while the second half of the Figure is a chart showing the operation in the case of V ss < 1.2 V. R 2.0 , SP 2.0 R 1.2 and SP 1.2 are output once every two seconds from a sampling signal generating circuit (described later). When V ss > 2.0 V, M down is output to step down the boosting factor by one level, whereas, when V ss < 1.2 V, M up is output to step up the boosting factor by one level. The immediate start circuit will be explained next The immediate start circuit is provided for the purpose of enabling the boosting operation to start smoothly and reliably at the transition point where V sc changes from a voltage below 0.4 V to a voltage above 0.4 V. Boosting needs to start from the above described transition point and, for boosting to start, it is necessary that the oscillation circuit within the clock circuit 12 should already be in an oscillating state and the clock circuit 12 itself should already be in an operative state. However, the voltage at the transition point is low, i.e. 0.4 V, and the voltage has, as a matter of course, not yet been boosted before reaching the transition point. Therefore, the circuit cannot operate. If the transition point is set at a voltage at which the dock circuit 12 is operable, introduction of the boosting system makes no sense. To solve the above described problems, the immediate start circuit enables the voltage V ss to be raised to a high voltage by a method which is different from that of the booster circuit. A specific circuit configuration of the immediate start circuit is shown in Figure 16. When the fact that V sc < V ON (0.4 V) is detected by the V sc detecting circuit 6, the "off" signal becomes 1, so that the shorting transistor 15 turns off. Further, in response to the "off" signal, the booster circuit shown in Figure 10 is initially set and all the transistors Tr1 to Tr7 are turned off. When the generator is activated in this state, a charging current i flows through the capacitor 3. At this time, the series resistor 16 causes a voltage drop v = the resistance value thereof x i . More specifically, a voltage of v + V sc is applied across the auxiliary capacitor 10 only when the current i is flowing. Although Tr3 and Tr4 are off at the time of the immediate start operation, the auxiliary capacitor 10 can be charged with the voltage v + V sc through parasitic diodes 43 of these transistors. The auxiliary capacitor 10 also serves as a smoothing capacitor, and after the auxiliary capacitor 10 has been charged with v + V sc , the circuit operation is available. It suffices to set the resistance value of the series resistor 16 such that the resistance value x i = v is equal to or higher than V ON (1.2 V). The "off signal is set in the circuit 6 so that it is "1" even when oscillation is suspended and hence the clock circuit 12 is in an inoperative state. Therefore, there is no problem in regard to the starting of the immediate start circuit When V sc exceeds V ON to start a boosting operation, the shorting transistor 15 is turned on so that no excess impedance is applied during the following charging of the capacitor 3. Since the fact that V sc , which is rising, exceeds the transition point means, as a matter of course, that the generator is in an operative state and the charging current is flowing, it is possible to commence any immediate start operation, that is to raise V ss to a high voltage at the transition point. Accordingly, the present invention enables the dock circuit 12 to be already in an operative state at the transition point and hence permits the circuit operation to shift to a boosting operation smoothly and reliably. Further, according to the immediate start circuit of the present invention, the watch is operable without fail as long as the generator is in an operative state. Therefore, the dock operation can be readily monitored even when the capacitor voltage is below 0.4 V. More specifically, this is very effective in the performance check carried out when watches are shipped from the factory or in over the counter selling and PR work. Figure 17 shows a sampling signal generating circuit for detecting four different kinds of voltage in the present invention. The detection of four different kinds of voltage means the detection of V up and V down in the V ss detecting circuit 11 and the detection of V ON and V lim in the V sc detecting circuit 6. ⊘256M, ⊘1/2, ⊘64, ⊘128M, ⊘16 and ⊘32 are reference signals which are output from the frequency divider. Each sampling pulse is generated by de-coding these signals. R 2.0 , R 1.2 , R LIM and R 0.4 are latch signals for comparators, respectively, while SP 2.1 , SP 1.2 , SP LIM and SP 0.4 are signals for activating detecting circuits, respectively. Figure 18 is a timing chart showing these signals. Great effectiveness is obtained by ordering the sampling pulses such as in this embodiment, particularly the detection sampling signal SP 2.0 for stepping down the boosting factor by one level when V ss has reached V down (2.0 V) and the sampling signal SP 0.4 for starting a boosting operation when V sc has reached V ON (0.4 V). Figure 19 (A) shows the operation carried out with the sampling pulses ordered as shown in Figure 18, while Figure 19 (B) shows the operation carried out in the case where the sampling pulse order is reversed. Referring first to Figure 19 (B), it is assumed that V sc is lower than V ON (0.4 V) and hence the system is in an immediate start state before SP 0.4a is output. It is further assumed that, when SP 0.4a is output, V sc ≧ V ON , so that the immediate start state is cancelled and 3-times boosting is commenced. At this time, V ss drops towards 1.2 V (0.4 V x 3) from the voltage in the immediate start state. However, V ss does not drop instantaneously but with a certain time constant At this time, if the voltage V ss is at a sufficiently high level (i.e. V ss > 2.0 V) in the immediate start state, the following problem arises: at P1, V ss starts to drop towards 1.2 V and, when SP 2.0a is output at P2, if V ss is still higher than 2.0 V, 2-times boosting is commenced although 3-times boosting has been commenced when an immediate start state is cancelled. In consequence, V ss lowers to 0.4 V x 2 = 0.8 V, which is below the lower limit of the clock circuit operating voltage range, so that this circuit comes to rest. Accordingly, a normal boosting operation cannot be started until V sc is raised to 0.6 V and this extends the time required for the watch to start from a resting state, which is inconvenient. The reason why V sc is set so as to be equal to 0.6 V in the foregoing is that, even if 2-times boosting is commenced when an immediate start state is cancelled, V ss is 2 x 0.6 V = 1.2 V and therefore it is possible to ensure the circuit operation. Accordingly, in this embodiment, shown in Figure 19 (A), the above described problem is solved as follows. The order in which SP 2.0 and SP 0.4 are generated is reversed by comparison with the case of Figure 19 (B) and therefore the period from the instant that SP 0.4 , is output until the instant that SP 2.0 is output is relatively long. According to the present invention, the period is 2 - 0.047 = 1.953 secs, whereas, in the case of Figure 19 (B), the period is 0.047 secs. When SP 2.0a is output, the circuit is still in the immediate start state and immune to the change over of boosting factors, and, when SP 0.4a , is output subsequently, the immediate start state is cancelled and 3-times boosting is commenced, so that at P1 V ss begins to lower towards to 1.2 V. Since the period from SP 0.4a to SP 2.0a is sufficiently long, i.e. 1.953 secs, V ss is already below 2.0 V at the point P2 at which SP 2.0b is output. In other words, when SP 2.0b is output, no detection is carried out and the boosting factor can be maintained for 3-times boosting. More specifically, the period from SP 0.4 to SP 2.0 may be set as follows: it suffices to set a period which is longer than T (sec) that is obtained from the following expression: {(i x r + V ON ) - V ON x N}e x P( - T CR ) + V ON x N < V down where i is the maximum current value obtained from the AC generator r is the sum of the resistance of the series resistor 16 and the internal resistance of the capacitor 3 V ON is 0.4 V N is the boosting factor (N = 3 in this embodiment) C is the capacitance of the auxiliary capacitor 10 R is the equivalent resistance value of the switching transistor within the multi-stage booster circuit 7 V down is 2.0 V. The above "expression means that, when the immediate start state is cancelled, V ss has been raised to i x r + V ON and V ss drops from this voltage to V ON x N (1.2 V) with a time constant CR. According to this expression, therefore, by the time T (sec) has elapsed from the time when the immediate start state is cancelled, the voltage V ss has dropped below V down (2.0 V). Thus, it is possible according to the present invention to reliably shift the circuit operation state from an immediate start state to a boosting state simply by adjusting the timing at which each of the sampling pulses SP 2.0 and SP 0.4 is output In terms of the logic, it is only necessary to adjust the de-coding condition for the sampling signal generating circuit and no additional arrangement is needed. Thus, it is possible to guarantee that, when the capacitor voltage V sc is equal to or higher than 0.4 V, the clock operation is available even if the generator is not in an operative state, which is the aim in introducing the booster circuit.

Claims: A wrist watch having: an AC generator (1,17,18,19); a rectifier circuit (2) for rectifying an output from the AC generator; a re-chargeable secondary power supply (3) for storing the rectified output for operating a clock circuit (12); auxiliary re-chargeable means (10) chargeable from the output (Vsc) of the re-chargeable secondary power supply (3) for operating the clock circuit (12); and charging control means (6,7,8,9,11,15,16) for controlling the charging of the auxiliary re-chargeable means (10) such that the output (Vss) of the auxiliary re-chargeable means (10) is enlarged relative to the output (Vsc) of the re-chargeable secondary power supply (3) for a given range of values for the output (Vsc) of the re-chargeable secondary power supply (3) when the output (Vsc) of the rechargeable secondary power supply (3) has a value above a first predetermined reference value (Vup); characterised in that said charging control means comprises means (16) selectively connected to said re-chargeable secondary power supply (3) for enlarging the output (Vsc) thereof when the output (Vsc) of the re-chargeable secondary power supply (3) has a value below a predetermined lower limit (Von) whereby the enlarged output exceeds the threshold at which the wristwatch will operate. A wrist watch as claimed in claim 1, in which said means (16) comprises a resistor connected in series with the re-chargeable secondary power supply (3) and further comprising means (6,15), responsive to the output (Vsc) of the re-chargeable secondary power supply (3), for providing a by pass to the resistor (16) when the value of the output (Vsc) of the re-chargeable secondary power supply (3) exceeds the predetermined lower limit (Von). A wrist watch as claimed in claim 2, in which said by pass providing means includes a first output detecting means (6) for detecting whether the output (Vsc) of the re-chargeable secondary power supply (3) has a value below or above the predetermined lower limit (Von). A wrist watch as claimed in claim 3, further comprising a second output detecting means (11) for comparing the output (Vss) of the auxiliary re-chargeable means (10) with the first and second predetermined reference values (Vup,Vdown). A wrist watch as claimed in any one of the preceding claims, in which said charging control means further comprises a booster circuit (7) for boosting the output (Vsc) of the re-chargeable secondary power supply (3) for generating an enlarged charging signal for charging the auxiliary re-chargeable means (10). A wrist watch as claimed in claim 5 when dependent on claim 4, in which said booster circuit (7) is arranged to select one of a plurality of boosting factors depending upon the comparison of the output (Vss) of the auxiliary re-chargeable means (10) with the predetermined reference values (Vup,Vdown). A wrist watch as claimed in claim 6, further comprising activating means for activating periodically each of the first and second output detecting means, the activating means being arranged to activate the second output detecting means (11) immediately after the first output detecting means (6). A wrist watch as claimed in claim 7 characterised in that the booster circuit (7) includes switching means (Tr1 - Tr7) and in that the time interval between the activation of the first output detecting means (6) and the previous activation of the second output detecting means (11) is greater than a time (T) defined as follows: ((i x r +V on ) - V on x N) exp (-T/CR)) + V on x N < V down where i is the maximum current value obtained from the AC generator r is the sum of the resistance of the resistor of claim 2 and the internal resistance of the secondary power supply V on is the predetermined lower limit N is the factor by which the boosting means changes the voltage of the secondary power supply C is the capacitance value of the auxiliary rechargeable means R is the equivalent resistance of the switching means of the booster circuit V down is the maximum reference value of the second output detecting means. A wrist watch according to any preceding claim, further characterised by means (4) for limiting charging of the re-chargeable secondary power supply (3), and means (5) for inhibiting a reverse flow of current through a coil (1) of the AC generator (1) through the limiting means (4). A wrist watch according to claim 9, characterised in that the limiting means (4) and the inhibiting means (5) comprise respectively a switching element and a diode connected in series with one another and in parallel with the coil (1). A wrist watch as claimed in claim 10, in which said switching element comprises a low power consumption transistor. A wrist watch according to any preceding claim, characterised in that the rectifier circuit (2) is arranged to provide half wave rectification of the output of the AC generator (1).

Inventors: HAYAKAWA MOTOMU, HAYAKAWA, MOTOMU
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1989
Main classification: G04C10
IPC codes: G04G19