METHOD FOR PROCESSING TRANSMITTED AND REFLECTED SIGNALS FOR REMOVING UNWANTED SIGNALS AND NOISE FROM WANTED SIGNALS

Abstract: In an identification system based on reflections of radar signals from a bit-coded transponder, the received signals are processed to remove unwanted signals and noise from the required, reflected and received signals that have a recurrent, equal cycle. The reflected signals are extremely weak in relation to the unwanted signals and noise. A transmitter unit (11) and a time slot device (15) form through a random bit sequence (14) phase modulated pulse trains which are transmitted. These are reflected from a coded passive transponder (12) back to a receiver (13) which leads the demodulated signal into an integrator array (16) that is controlled by said bit sequence (14) together with the time slot signal from a device (15). The inverted signal is also utilized. The synchronization is being performed through shift registers (19) which together with the bit sequence control the integrator array (16).

Description: Method for processing transmitted and reflected signals for removing unwanted signals and noise from wanted, signals, The invention concerns a method for processing signals in an ident fication system, as described in the introduction to Claim of Patent 1. The invention is designed for application in an iden ification system that consists of a transmitter, a mobile bit-coded passive transponder that produces identification, and a receiver unit that in combination make up a processing system. The transponder can be realized by means of SAW _ technology (Surface Acoustic Wave) . This is a technol¬ ogy with many advantages for such an application, it is inexpensive, straightforward to produce, requires no maintenance, and is independent o f external power sources etc. However a transponder realized in accordance with this technology lias a characteristic which initially has one drawback: the high insertion loss. This means that the reflected return signal is weak in relation to the incoming interrogator pulse. The disadvantage is intensified as the transmitter unit utilizes a low output radar to meet the beam output requirements in the frequency used. The combined result is that the output of the required return signal to the system's receiver unit is * very low in relation to the unwanted bignaJs, noise and Λ ►• ■ the inherent noise in t_he receiver itself. Other known solutions. The traditional method for processing signals to improve the signal/noise ratio for the applications mentioned is to digitalize the reflected signal directly with an A/D converter and follow this by digital processing. The processing is done by averaging the digital values of the analog signals for several repeated return signal cycles. This will improve the signal/noise ratio because the required signal is identical for each cycle whilst the noise is different. On the other hand, this method necessitates a powerful digital processing unit. The unit has to be fast and have substantial calculating power to average an adequate number of cycles. At the same time, the A/D converter must be one of the fastest and most advanced types available. This solution means that the technol¬ ogy used clearly limits how efficient the processing is. This will also necessitate the use of expensive digital processors and A/D converters. Another traditional method which is used in radar technology is using delay lines so that a signal is delayed one cycle and averaged by adding these signals analogously. This method has one limitation that the number of averages that can be made is very restricted and there is no synchronization with the cycle. US Patent Specification 3.706.094 describes a receiver for a low output radar surveillance system, where the receiver consists of equipment for analog processing of received, recurrent pulse signals whereby each pulse signal is divided up into a certain number of time slots in gate control circuits. Further, the signal from each gate circuit is led to an integrator for the recurrent integration of the pulse signals as the repetition frequency of the pulse signals is considerably higher than the integrator's low-pass filter frequency. The pulse signal can be reconstructed from the responder by reading the output from the integrator . The main objective of the present invention is to create a safe means of recognizing a radar signal which is reflected from a passive, coded transponder by the phase modulation of the transmitted signal. This can be done by implementing the method stated in Claim of Patent 1. Other aspects of the invention are stated in the remaining claims of patent. The present invention can be dis inguished from the technique adopted in the patent specification referred to by the fact that the present invention utilizes interaction between the transmitted and reflected signals. This s done by a random binary digital sequence which modulates the transmitted signal, and employing the same bit sequence when the demodulated reflected signal is to be recognized. This generates a large number of phase-modulated pulse trains, which are preferably different. This iβ achieved by dividing the above-mentioned random bit sequence up and using these divisions of the random bit sequence to lead the demodulated reflected signal into a storage medium such as an integrator link that is designed so that the medium will contain values from the means of the required signals, whilst the unwanted signals and noise are greatly reduced. Advantages of the ' application of the invention. The technique used in the invention consists of an analog averaging of the signal before it is digital ized . This has several advantages over traditional techniques. A huge processing capacity can be achieved using only completely conven ional, commercially accessible, inexpensive components. This results in a speed and averaging capability for recurrent cycles that is far in excess of any of the above-men¬ tioned traditional approaches. At the same time, the lower reading rate will mean that a standard conven¬ tional type of A/D converter and later the digital processing unit can be used so that this will be commercially attractive. As a bit sequence i s used both for the transmis¬ sion to modulate the transmitted signal and for the receiver to control the storage and average the demodulated, reflected signal, all types of noise and unwanted signals are reduced significantly compared to the required signal. Since the above bit sequence is part of a random bit sequence, noise and unwanted signals will be greatly reduced even if they are part of an unfavourable recurrent cycle. It is also possible to achieve better transmis¬ sion by using phase-modulated and preferable different pulse trains instead of a single pulse, where the increased length of a pulse train is limited ahead by the time of the first reflected pulse train. Design of the invention. An example of the design of the invention will be given with reference to the illustrations. Fig. 1 is a block diagram of one means of designing the invention which includes the main component . Fig. 2 shows a more detailed presentation of the transmitter unit in this particular design Fig. 3 shows a more detailed presentation of the receiver- a d decoder unit in this particular design. Fig. 4 shows a chronological presentation of the transmitted and reflected signals in this design of the inven ion . The design in Fig. 1 consists of a transmitter unit ll r an identification chip 12 which could for example be a passive SAW transponder, and a receiver unit 13 which is connected to an array 16 of integrator sections. A device 14 creates a random bit sequence which is fed to the transmitter unit 11 and a shift register 17 connected to the integrator array 16. A device 15 forms a signal with time boundaries which is fed to the transmitter unit 11 and the shift register 17. The design functions as follows: The transmitter unit 11 transmits a phase-modulated pulse train which is received and reflected by the coded transponder 12, so that the reflected signal consists of a series of pulse trains and spaces where there are no pulse train, which together form an identity that equates the transponder code, which also consists of phase-modulated pulse trains. The required signal is picked up by the receiver 13 which then demodulates it and sends it to an integrator array 16, this is controlled by the above-ment oned bit sequence from device 14 together with the time slot from device 15. Fig. 2 gives a more detailed presentation of the transmitter unit. This consists of an oscillator 21 which forms a fixed frequency signal. This signal is phase-modulated by a random bit sequence from device 14. Once modulated, the signal is divided up into pulse trains by means of a gate device 23, controlled by the time slots from device 15. The pulse trains are then amplified by an amplifier 24 prior to transmission. Fig. 3 shows a more detailed presentation of the receiver- and decoder unit. The signal is demodulated in a receiver 13 into a time- and phase-coded signal 31a, superimposed upon unwanted noise. In this example of the invention the signal 31a enters- a switch 36a which leads the signal 31a into an integrator section 37. This integrator section 37 can, for exampl , be an RC filter with a high time constant compared to the individual signal cycles (e.g. , 10 000 times greater). The bit sequence from device 14 and the time slot signal from device 15 form the input to an AND-gate 32a, where the output goes to a shift register 33a, which then receives exactly the same bit sequence as that used in the transmitter to form the phase- modulated pulse train. This bit sequence is then clocked along the shift register 33a by means of an external clock signal (not illustrated on the figure). It is possible to obtain a signal from different positions " on the shift register 33a, i.e. , after certain intervals of time after the signal has been fed into the shift register 33a. When the time interval which equates the time delay for- the first bit on the transponder 12 has elapsed, the signal is removed from the shift register and used to control the switch 36a that opens or closes for the demodulated signal 31a from the receiver 13 and in to the integrator section 37. The signal 31a can be inverted by means of an inverter 34 to a signal 31b, which is also fed into the integrator section 37. This is done by feeding the random bit sequence 14 through an inverter 35 to another shift register 33b and removing it at an equivalent position to the first shift register 33a and controlling the switch 36b so that it opens or closes for the inverted signal 31b into the integrator section 37. Both switches 36a and 36b can be controlled for instance so that a logical "1" in bit sequence 14 opens the switch for the non-inverted signal 31a from the receiver and the switch for the inverted signal 31b closes; if a logical "0" occurs in the bit sequence 14, the opposite will occur. In the time interval where pulse trains are not formed from the transmitter 13 because the signal from device 15 has a logical value of "0", the AND-gates 32a and 32b will always have a logical "0" m their output, this ensures that both switches 36a and 36b will be open to hinder unwanted noise from entering the integrator section. The integrator array 16 is formed from a number of integrator sections 37, which typically equate the number of bits or the multiple of the number of bits in the reflector device 12. The individual integrator sections 37 can be read whenever the required number of pulse trains have been processed. This reading can be done asynchronical ly without any attention having to be paid to anything that has happened previously. Fig. 4 shows a chronological presentation of how two pulse trains are transmitted from the transmitter 11 and are reflected from the transponder 12, in an example where the transponder 12 has a resolution of four bits. Here the transponder 12 is coded with the bit sequence 1101. The first pulse train 41a is a phase modulated signal which is modulated by the first part of a random bit sequence from device 14, with a length determined by the time slot formed by device 15. The first pulse train 41a is received by the transponder 12 and reflected where it is coded to logical "1". As the transponder in this example has the code 1101, the reflected signal will form a pattern as shown in 41b where bit 1, bit 2 and bit 4 reflect a pulse train, whilst bit 3, which has the logical value of "0", will not reflect any signal. The reflecting pulse trains 41b can and will overlap each other in the various bit positions without this having any negative consequences on the result . Once the last reflected pulse t-rain i received, the second pulse train will be transmi ed. This pulse train is phasemodulated by another part of a random bit series, different from that in the first pulse train, from device 14 activated for a certain length of time decided by the time slot in device 15. This second pulse train 42a is then reflected from the transponder 12 as in the first case, thus forming a row of reflected pulse trains 42b. A large number of pulse trains, equivalent to pulse trains 41a and 42a, all phase modulated in different ways, can be transmitted, reflected, and led into the integrator array 16 so that the required signal is averaged and unwanted signals that are random and asychronoύs will be greatly reduced.

Claims: CL IM OF PATENT: 1. A method in an identification system, where a radar signal is transmitted from a transmitter and is designed to be received by a mobile, bit-coded, preferably passive identification transponder which returns a coded signal that is received by a receiver unit linked to the transmitter, where the signal is processed to remove unwanted signals and noise from the reflected, coded and wanted signals, c h a r a c t e r i z e d by the use of a random bit sequence to phase modulate the signal that is trans¬ mitted and reflected from a binary coded device, back to a receiver where the signal is demodulated and the said random bit sequence delayed so that it can be used with the demodulated signal to store, average and thereby process identification from the bit-coded device for recognition. 2. A method in accordance with Claim 1, . c h a r a c t e r i z e d by the transmitted signal consisting of a large number of pulse trains, formed by " a device which opens and closes for the modulated signal . 3. A method in accordance with Claims 1 and 2, c h a r a c t e r i z e d by the said random bit sequence that is formed, being preferably different for each recurrent cycle, a d which for example is a part of a larger bit sequence. 4. A method in accordance with Claim 1, c h a r a c t e r i z e d by the said binary-coded device reflecting the said pulse trains to different times by means of the various bit positions in the devfce . 5. A method in accordance with Claim 1, c h a r a c t e r i z e d by the demodulated signal being led into a storage medium where the discrete values in the random bit sequence are able to control a device that opens for signals with a given bit value, and closes for signals that have the inverse value. 6. A method in accordance with Claims 1-5, c h a r a c t e r i z e d by the random bit sequence being led through a device that delays the values in time so that they are synchronized with the reflected signal . 7. A method in accordance with Claims 2, 5 and 6, c h a r a c t e r i z e d by the signal that opens and closes for the modulated signal, and the random bit sequence passing through a logical AND-operation prior to the delay device, so that the storage device is blocked for signals outside the periods that equate the reflected pulse trains. 8. A method in accordance with Claims 2, 5-7, c h a r a c t e r i z e d by the inverse demodulated signal being led into the said storage medium, controlled by the inverse values of the said part of a random bit sequence. 9. A method in accordance with Claims 1-8, c h a r a c t e r i z e d by the said storage medium including the possibility to store a number of values which typically correspond to the number of bits or the multiple of the number of bits in the reflecting device. 10. A method in accordance with Claims 7-9, c h a r a c t e r i z e d by the said control signal being able to be extracted and used at different points in time, corresponding to the positions of the different bits in the reflecting device or the multiple of these time delays. 11. A method in accordance with Claims 2, 5-8, h a r a c t e r i z e d by the said storage medium being designed so that a recurrent cycle of the received, demodulated and stored signal cycles are averaged here over time. 12. A device to implement the method in Claims 6- 8, that consists of . a) a transmitter unit (13) for the transmission of a phase modulated signal , b) a device (12) that receives the transmitted signals and reflects them in accordance with a binary code, which identifies the said device (12), c) a receiver unit (13) where the reflected signal is received and demodulated, d) a controllable storage medium (18), e) one or more shift registers (17), c h a r a c t e r i z e d by the said transmitter unit (13) containing a device (14) to generate a random bit sequence which can be used to phase modulate a signal which is divided up into pulse trains by means of a device (15) prior to transmission, and that the random bit sequence from device (14) and the signal from device (15) are connected through an AND-gate on one or more shift registers (17), and clocked through them so that they can be removed at different times and used to control the said storage medium (16). '

Inventors: KIRKNES STEFFEN, KIRKNES, STEFFEN
Applicants: MICRO DESIGN AS, MICRO DESIGN A.S.
Application year: 1989
Main classification: G01S13
IPC codes: G01S13