Reference generator

Abstract: A reference generator is used in a digital-to-analog converter to provide for a replication of colors in accordance with binary information introduced to the converter. The generator is responsive to binary signals each having first and second logic levels respectively representing binary "1" and binary "0" and each representing a different one of the binary colors red, green and blue. Each of the binary signals is introduced to an individual one of transistors in a first plurality. An energizing voltage is also introduced to the transistors to obtain a flow of current through such transistors in accordance with the logic levels of such input signals and the magnitude of the energizing voltage. A substantially constant current is provided at first particular times and a reference voltage is provided at other times. An impedance may be common to the circuit for the substantially constant current and the reference voltage. A first control is responsive to the constant current to maintain the energizing voltage at a substantially constant value. A second control is responsive to the reference voltage to maintain the energizing voltage at the substantially constant value. When the reference voltage is produced, the production of the substantially constant voltage from the constant current is overridden. The first and second controls for each of the different colors are disposed in an electrical circuit to provide an output from the circuit only in accordance with the logic levels of the binary signals. The first and second controls may respectively include transistors in second and third pluralities.

Description: The invention relates to an integrated circuit chip for providing a substantially constant voltage. The invention has particular utility in converting binary information relating to the primary colors such as red, green and blue into corresponding analog information. Data processing systems are now in use for processing a wide variety of information. For example, data processing systems are now in use for aiding scientists and engineers in designing complex three-dimensional articles. Such data processing systems have been instrumental in materially shortening the time required to design such three-dimensional articles. The systems have also been instrumental in showing weaknesses and deficiencies in the design of such articles before prototypes of such articles have been constructed and tested. As a result, such data processing systems have proved to be a boon to suppliers of many different types of products. Visual displays are included in many different data processing systems. For example, visual displays are included in the systems discussed in the previous paragraph for aiding scientists and engineers to design new products. Such visual displays are often in color. To provide such displays, data processing information in binary form is converted to an analog form for each of three (3) different primary colors such as red, green and blue. The colors are mixed at each different position to obtain a resultant color at that position. The resultant color for each position is then displayed on a visual screen. Since the three different primary colors are mixed for each position, the conversion of the binary information to the analog information at each position for each color has to be quite precise. Different systems have been provided in the prior art to provide such precise conversion. In each of these prior art systems, a transistor receiving the binary information for each individual color has been energized with a substantially constant voltage to assure that the transistor will operate only in accordance with the binary input signal. Two systems have been provided in the prior art for energizing each transistor receiving a binary input signal for each primary color. One of these systems receives a substantially constant current and produces the substantially constant voltage from this current. The other system receives a reference voltage and produces the substantially constant voltage from this reference voltage. One system has been used by certain suppliers and the other system has been used by other suppliers. As will be appreciated, it is desirable for a supplier to provide a system which can be easily adapted to provide the substantially constant voltage from either the substantially constant current or the reference voltage. This is particularly true since the converters discussed in the previous paragraph are disposed on an integrated circuit chip and the production of the substantially constant voltage for energizing the transistors providing the conversion are also disposed on this chip. By providing the chip with the capabilities of producing the substantially constant voltage either from a substantially constant current or a reference voltage, the chip is able to be used on a universal basis. Since the desirability of producing a universal chip such as discussed in the previous paragraph has been known for some time, a considerable effort has been made, and significant amounts of money have been expended, to provide such a universal chip. Such effort and money expenditure have not been successful. No system has been provided which is adaptable to provide a substantially constant voltage, either from a substantially constant current or from a reference voltage, for energizing transistors in a converter. This invention provides a universal integrated circuit chip for producing a substantially constant voltage, either from a substantially constant current or from a reference voltage, to energize transistors in a converter. These transistors provide a conversion of binary values to an analog value in accordance with the logic levels of binary signals introduced to the transistors. By energizing the transistors with the substantially constant voltage, the transistors are operative only in accordance with the logic levels of the binary signals introduced to the transistors. In one embodiment of the invention, the circuit chip is used in a digital-to-analog converter to provide for a replication of colors in accordance with binary information introduced to the converter. The chip is responsive to binary signals each having first and second logic levels respectively representing binary "1" and binary "0" and each representing a different one of the binary colors red, green and blue. Each of the binary signals is introduced to an individual one of transistors in a first plurality. An energizing voltage is also introduced to the transistors to obtain a flow of current through such transistors in accordance with the logic levels of such input signals and the magnitude of the energizing voltage. A substantially constant current is provided at first particular times and a reference voltage is provided at other times. An impedance may be common to the circuits for the substantially constant current and the reference voltage. A first control is responsive to the constant current to maintain the energizing voltage at a substantially constant value. A second control is responsive to the reference voltage to maintain the energizing voltage at the substantially constant value. When the reference voltage is produced, the production of the substantially constant voltage from the constant current is overridden. The first and second controls for each of the different colors are disposed in an electrical circuit to provide an output from the circuit only in accordance with the logic levels of the binary signals. The first and second controls may respectively include transistors in second and third pluralities. The single Figure is a circuit diagram of an integrated circuit chip constituting one embodiment of the invention. In one embodiment of the invention, a chip generally indicated at 10 is shown in the single Figure for controlling the currents produced by a digital-to-analog converter in accordance with the logic levels of binary signals introduced to the converter. The chip 10 is particularly adapted to be used to convert binary signals relating to primary colors such as red, green and blue for different positions in a visual image into analog signals indicating the color information represented by such binary signals. In the embodiment of the invention shown in the single Figure, a source 12 of a reference voltage such as approximately one and two tenths volt (1.2V.) is connected to a first input terminal of an operational amplifier 14. The operational amplifier 14 may be constructed in a conventional manner. A second input terminal of the operational amplifier 14 is connected to the drain of a transistor 16, which may be a p-type. The drain of the transistor 16 is also in series with a grounded resistance 17 which is connected to provide a substantially constant current designated in the single Figure as "I REF". The source of the transistor 16 receives a positive potential from a voltage source 18. The operational amplifier 14 includes a ground 20 at one of the terminals internal to the amplifier. The output terminal of the amplifier 14 has a common connection to one stationary terminal of a switch 22, the other stationary terminal of which is common to the gate of the transistor 16. A capacitance 24 is disposed electrically between the voltage source 18 and the gate of the transistor 16. The voltage introduced to the gate of the transistor 16 is also introduced to the gates of transistors 26, 28, 30 and 32, each of which may be a p-type. The sources of the transistors 26, 28, 30 and 32 receive an energizing voltage from the voltage source 18. The drains of the transistors 26, 28, 30 and 32 are respectively common with the sources of transistors 34, 36, 38 and 40, all of which may be a p-type. The gate and drain of the transistor 34 are connected to the ground 20. The drains of the transistors 36, 38 and 40 are respectively connected to lines 37, 39 and 41 providing red, green and blue signals. The sources of transistors 42, 44 and 46 are respectively connected to the drains of the transistors 28, 30 and 32. The drains of the transistors 42, 44 and 46 are grounded as at 20. The gates of the transistors 42, 44 and 46 respectively receive binary signals on lines 48, 50 and 52. The signals on the lines 48, 50 and 52 individually represent a binary value for the primary colors red, green and blue. In a mode of operation the switch 22 is open in the position shown. This isolates the operational amplifier 14 from the circuit and prevents the reference voltage from the source 12 from affecting the operation of the integrated circuit chip 10. This is true even though a reference voltage may be provided by the source 12 at this time. When the reference current transistor 16 receives a substantially constant flow of current indicated as "I REF", this current flows through a circuit including the voltage source 18, the transistor 16 and the resistance 17. This current produces a substantially constant voltage across the resistance 17. This voltage, applied to the gate of the transistor 16 when the switch 22 is in the up-position, is exactly the voltage required to cause the current "I REF" to flow between the gate and the drain of transistor 16. The voltage on the gate of the transistor 16 is introduced to the gates of the transistors 26, 28, 30 and 32. This causes a current substantially equal to "I REF" to flow through several transistors including the circuit consisting of the voltage source 18, the transistor 26 and the transistor 34. The flow of current through the transistor 34 causes a substantially constant voltage such as approximately one and two tenths volt (1.2 V.) to be produced on the source of the transistor. The voltage on the source of the transistor 34 provides a substantially constant voltage bias on the gates of the transistors 36, 38 and 40. Since a substantially constant voltage is also introduced to the gates of the transistors 28, 30 and 32, a substantially constant current flows through the transistors 28, 30 and 32 and a substantially constant voltage is produced on the sources of the transistors 36, 38 and 40, provided that the transistors 42, 44 and 46 are turned off by their respective input logic levels. Since the transistors 42, 44 and 46 are turned off, current will flow through these transistors only when the logic levels of the signals on the gates of the transistors drop to a low voltage or logic low state. Logic low states at the gates of the transistors 42, 44 and 46 divert the current from transistors 36, 38 and 40 since the substantially constant current through the transistors 28, 30 and 32 is divided between the current through the transistors 42, 44 and 46 and the current through the transistors 36, 38 and 40. As a result, the current flowing through the lines 37, 39 and 41 respectively represent the logic levels introduced to the gates of the transistors 48, 50 and 52. The switch 22 is in the down position when the chip 10 is to respond to the reference voltage ("V REF" in the single Figure) from the reference voltage source 12. This reference voltage may be approximately one and two tenths volts (1.2 V.). This reference voltage is introduced to the operational amplifier 14 which produces on its output terminal a voltage which is introduced through the closed switch 22 to the gate of the transistor 16. Current accordingly flows through a circuit including the voltage source 18, the transistor 16 and the resistance 17. The voltage produced across the resistance 17 by the flow of current through the resistance is substantially one and two tenths volts (1.2V.) This voltage is introduced to the second input terminal of the operational amplifier 14 and results in an output voltage appropriate to maintain the voltage input to the operational amplifier substantially equal to the reference (1.2V) voltage. In this way, the resistance 17 is included in a feedback circuit to maintain the current through the transistor 16 at a substantially constant and predictable value. Unlike the previous mode of operation, V REF rather than the transistor 34 establishes the substantially constant voltage on the sources of the transistors 36, 38 and 40 when their current flow is substantially equal to the constant current ("I REF" in the single Figure) through the resistance 17. The transistor 34 plays no significant role in this mode of operation since the voltage at the V REF terminal (12) establishes the voltage at the source of the transistor 34. The substantially constant voltage produced on the gate of the transistor 16 by the operational amplifier 14 is introduced to the gates of the transistors 28, 30 and 32 to produce a substantially constant current through the transistors and a substantially constant voltage on the sources of the transistors 36, 38 and 40. This is true except when the logic signals at the inputs of the transistors 42, 44 and 46 cause the constant currents generated by transistors 28, 30 and 32 to be diverted. As a result, the flow of current through the lines 37, 39 and 41 is affected only by the logic levels of the binary input signals introduced to the gates of the transistors 42, 44 and 46. Distributed capacitances respectively exist on the integrated circuit chip between the sources of the transistors 42, 44 and 46 and the gates of the transistors 26, 28 and 30. These distributed capacitances may affect the production of the substantially constant current through the transistors 36, 38 and 40 even though the distributed capacitances may be in the picofarad range. To offset any effect of these distributed capacitances on the production of the substantially constant current at the drains of the transistors 36, 38 and 40, the capacitance 24 is provided between the voltage source 18 and the gate of the transistor 16. The value of this capacitance may be about a hundredth of a microfarad (0.01 fd). This capacitance causes the voltage at the gates of transistors 16, 26, 28, 30 and 32 to remain substantially constant in the presence of changing logic levels at the inputs of the transistors 42, 44 and 46. It will be appreciated that the currents in the output lines 37, 39 and 41 represent only one binary stage. For example, the currents through the lines 37, 39 and 41 may be for only the stage of least binary significance. Circuits similar to those shown in Figure 1 may be provided for each of the stages of progressive binary significance. These circuits provide currents on output lines corresponding to the lines 37, 39 and 41. The currents on the different output lines for each position in the visual display are then processed to produce the color for that particular position. The integrated circuit chip described above has certain important advantages. It receives a substantially constant current at first times and produces a substantially constant voltage for introduction to control stages. These control stages then operate to produce on output lines (such as the lines 37, 39 and 41) a current only in accordance with the logic levels of binary signals providing color information for a particular position in a visual display. The chip also receives a reference voltage at other times and produces the substantially constant voltage for introduction to the control stages. When the reference voltage is introduced to the chip 10, it operates to override the stages producing the substantially constant voltage during the introduction of the substantially constant current.

Claims: Integrated circuit chip for providing a substantially constant voltage from either an internally generated constant current or an external reference voltage terminal (12), an operational amplifier (14) receiving the reference voltage, at a first input terminal switch means (22) for selecting either the output of said operational amplifier (14) or an internally generated voltage, said selected voltage serving to control generation of said internally generated constant current, an impedance (17) for generating said internally generated voltage from said internally generated current, said operational amplifier (14) receiving said internally generated voltage at a second input terminal, a plurality of output means (36, 38, 40) responsive at a first input terminal, to the selected voltage and connected at a second input terminal to said reference voltage terminal (12), said second input terminal providing the substantially constant voltage, said plurality of output means (36, 38, 40) providing for variations at its output terminals in accordance with the logic level of further input signals applied to said first input terminals of the output means. Integrated circuit chip as set forth in claim 1, further comprising means (42, 44, 46) for providing the said further input signals with a first and second logical level, respectively representing a binary "1" and a binary "0". Integrated circuit chip as set forth in claim 1 or 2, further comprising a first additional transistor (34) having a drain, a gate and a source, the drain and the gate being connected to each other and the source being connected to the second input terminal of the output means (36, 38, 40). Integrated circuit chip as set forth in one of claims 1 to 3, further comprising: a first plurality of transistors (28, 30, 32) each operatively coupled to the selected voltage for producing a substantially constant voltage for introduction to an individual one of the first input terminals of the output means (36, 38, 40), and wherein the output means include a second plurality of transistors (36, 38, 40), an individual one of the transistors in the first plurality being connected with an individual one of the transistors in the second plurality. Integrated circuit chip as set forth in claim 4, wherein the means for providing the input signals comprise a third plurality of transistors (42, 44, 46), each having a first, second and third electrode. Integrated circuit chip as set forth in claim 4 or 5, wherein the first plurality of transistors (28, 30, 32) each have a first, second and third electrode and the integrated circuit chip further comprises: means for applying the selected voltage to the second electrodes of the transistors (28, 30, 32) in the first plurality, a source of voltage (18) connected to the first electrodes of the transistors (28, 30, 32) in the first plurality, and whereby the third electrodes of the transistors (28, 30, 32) in the first plurality are connected to respective first electrodes of the transistors in the second plurality (36, 38, 40). Integrated circuit chip as set forth in claim 6, wherein the third electrode in each of the transistors (28, 30, 32) in the first plurality is also connected to the first electrodes of associated ones of the transistors in the third plurality. Integrated circuit chip as set forth in one of claims 1 to 7, further comprising: means (24) connected to the output of the operational amplifier (14) for compensating for distributed capacitances between each of the transistors (42, 44, 46) in the third plurality and the associated ones of the transistors (28, 30, 32) in the first plurality to maintain the introduction of the selected voltage from the operational amplifier to the transistors in the first plurality. Integrated circuit chip as set forth in one of claims 1 to 8, further comprising a second additional transistor (16) having a first, second and third electrode, wherein the said selected voltage is introduced to the second electrode of the second additional transistor to regulate its flow of current. Integrated circuit chip as set forth in claim 9, wherein the first electrode of the second additional transistor (16) and the first electrodes of the transistors (28, 30, 32) in the first plurality receive the voltage from a voltage source (18) and the second electrodes of the transistors in the first plurality receive the said selected voltage. Integrated circuit chip as set forth in claims 4 and 9, further comprising a third additional transistor (26), wherein the said selected voltage is coupled to the third additional transistor and the second input of the operational amplifier is coupled to the second additional transistor (16). Integrated circuit chip as set forth in claim 11, wherein the transistors in the first, second and third pluralities are p-transistors and wherein the first, second and third additional transistors (34, 16, 26) are p-transistors.

Inventors: COLLES JOSEPH H, COLLES, JOSEPH H.
Applicants: BROOKTREE CORP, BROOKTREE CORPORATION
Application year: 1989
Main classification: H03M1
IPC codes: G09G1, H03M1, G05F1