Amplifier arrangement, in particular for amplifying a digital signal

Abstract: The invention relates to an amplifier arrangement comprising a first (T1) and a second (T2) field-effect transistor of the same conductivity type and a driver circuit (Q1, Q2, Q3, T3, T4, T5, I) which is responsive to drive the respective drain electrodes of the two field-effect transistors (T1, T2) to a signal to be amplified and applied to the input terminals (3, 4) drive the respective drain electrodes of the two field-effect transistors (T1, T2). An element (R) having a resistive action is formed between the drain and the gate electrode of the first field-effect transistor (T1) and an element (C) having a capacitive action is formed between the gate and the source electrode. Together with said elements (R, C) the first field-effect transistor (T1) constitutes a reactance circuit having an inductive character, which is arranged in parallel with the parasitic gate-source capacitance of the second field-effect transistor (T2). This results in the step-function response and edge steepness of step-function signals on the output terminal (5) at the drain electrode of the second field-­ effect transistor (T2) being improved in comparison with an amplifier arrangement without said reactance circuit. The circuit is very suitable for integration in BICMOS technology.

Description: The invention relates to an amplifier arrangement for amplifying an input signal, comprising: a first and a second field-effect transistor of a first conductivity type, a driver circuit for driving the first and the second transistor in response to the input signal. As is known, step-function signals, for example digital squarewave signals, may be thought to consist of an infinite sequence of harmonic signals. For amplifying such signals it is, in principle required to use amplifiers having a maximal bandwidth, because otherwise the waveform of the amplified output signal will differ excessively from that of the input signal to be amplified. This specifically results in the signal edges being affected. The step-function response of an amplifier arrangement can be corrected inductively, for example by arranging an inductance parallel to the load of the amplifier arrangement, inter alia to cancel the effect of stray and wiring capacitances. Such an inductance speeds up the charging (or discharging) process of a capacitive load or the capacitive component thereof, which improves the steepness of the edges of the step-function signal. The edge steepness of a step-function signal is represented inter alia by its rise time, which is to be understood to mean the time required for a signal to rise from 10% to 90% of its final steady value. In integrated circuits no inductances can be formed on the substrate of the circuit, so that these elements have to be added externally to the integrated circuit. Such external elements are generally less desirable. Therefore, it is an object of the present invention to provide an amplifier arrangement, in particular for amplifying digital signals, which does not require the use of external inductances or other correction networks to improve the steepness of the edges of the output signal. In accordance with the invention this is achieved in an amplifier arrangement of the type defined in the opening sentence in that the driver circuit is coupled to a first power-supply terminal and has a first and a second output, the drain-source path of the first transistor is coupled between the first output of the driver circuit and a second power-supply terminal, the drain-source path of the second transistor is coupled between the second output of the driver circuit and the second power-supply terminal, and the drain of the first transistor is coupled to the gate of the second transistor and through a resistive element to the gate of the first transistor, which gate of the first transistor is coupled to the second power-supply terminal through a capacitive element. In the arrangement in accordance with the invention the two field-effect transistors are not driven by applying a drive signal to their gate electrodes, as is customary, but the drive signal is applied to their drain electrodes. The resistive and capacitive then constitute such a phase shifting circuit that the drive signal applied to the drain electrode of the first field-effect transistor will appear on the gate electrode of said transistor with a phase lag. Consequently, the drain current thus produced will lag the applied drain-source voltage, so that a reactance circuit having an inductive character is obtained. In the arrangement in accordance with the invention this inductive reactance circuit is arranged in parallel with the parasitic gate-source capacitance of the second field-effect transistor, as a result of which this second field-effect transistor is turned on and turned off more rapidly. This results in the output signal, which appears on the drain electrode of this field-effect transistor, having steeper edges than without the reactance circuit. The arrangement in accordance with the invention is very suitable for use in integrated amplifier arrangements. Another embodiment of the invention, in which the amplifier arrangement is fabricated in "Bipolar Complementary Metal Oxide Silicon" (BICMOS) technology, in which both bipolar and unipolar components are formed in the same substrate, is characterized in that the arrangement is constructed as an integrated circuit in which the resistive element is an integrated resistor. A further embodiment of the invention is characterized in that the capacitive element is constituted by the gate-source capacitance of the first field-effect transistor. The arrangement can be dimensioned in such a way that when the first field-effect transistor is turned off the voltage on its gate electrode does not decrease below the threshold voltage of the field-effect transistor, which precludes a loss of time when the field-effect transistor is turned on again. To this end an embodiment of the invention is characterized in that the resistive element has a resistance between approximately 10 and 100 kohms and the capacitive element has a capacitive action as a capacitance between 100 and 1000 pF. A driver circuit which is very suitable for fabrication in BICMOS technology is characterized in that the driver circuit comprises a first and a second bipolar transistor, whose base electrodes respectively constitute a first and a second input terminal for the input signal to be amplified, which transistors have their collector-emitter paths coupled between the first power-supply terminal and to the source electrodes of a third and a fourth field-effect transistor of a second conductivity type respectively, the drain electrodes of the third and the fourth field-effect transistors constituting the first and the second output of the driver circuit, and the gate electrodes of the third and the fourth field-effect transistor being interconnected and being connected to an output of a current reference circuit. The input signal to be amplified can be applied in phase opposition to the base electrodes of the first and the second bipolar transistor. However, the amplifier arrangement can also be driven asymmetrically by maintaining one of the base electrodes at a fixed potential and applying the input signal to the other base electrode. Yet another embodiment of the amplifier arrangement in accordance with the invention is characterized in that the current-reference circuit comprises between the first and the second supply terminal the series arrangement of a third bipolar transistor connected as a diode, the source-drain path of a fifth field-effect transistor of the second conductivity type and a current-reference element, the drain and gate electrodes of said fifth field-effect transistor being interconnected and constituting the output of the current-reference circuit. A preferred embodiment of an integrated amplifier arrangement in accordance with the invention will now be described in more detail, by way of example, with reference to the drawing, which shows the circuit diagram of the arrangement. The arrangement shown in the Figure comprises a first N-channel insulated-gate field-effect transistor T1 (generally referred to as MOST "Metal Oxide Silicon Transistor" in the English literature) and a second N-channel insulated-gate field-effect transistor T2 of the enhancement mode type. The source electrodes of the two MOS transistors T1, T2 are connected to a power-supply terminal 2, which constitutes the signal earth. The drain electrode of T1 is connected to the gate electrode of T2. In accordance with the invention a resistor R, which is integrated in the substrate, is arranged between the gate electrodes of the MOS transistors T1 and T2 and the element C having a capacitive action and forming part of the MOS transistor T1 is represented diagrammatically as a capacitor C arranged between the gate electrode T1 and the power-supply terminal 2. The drain electrodes of T1 and T2 are connected to the respective drain electrodes of a third and a fourth P-channel insulated-gate field-effect transistor T3 and T4. The source electrodes of T3 and T4 are connected to the emitters of a first and a second bipolar emitter-follower transistor Q1, Q2, both of the NPN type. The transistors Q1 and Q2 have their collectors connected to a power-supply terminal 1. The bases of the transistors Q1 and Q2 constitute a first input terminal 3 and a second input terminal 4 respectively. The gate electrodes of the MOS transistors T3 and T4 are interconnected and connected to the gate electrode of a fifth P-channel insulated-gate field-effect transistor T5. This MOS transistor T5 is also of the enhancement type. The drain and gate electrodes of T5 are interconnected, so that the MOS transistors T3, T4 and T5 constitute a current-mirror circuit. The source electrode of T5 is connected to the emitter of a third bipolar NPN transistor Q3, which has its collector and its base connected to the power-supply terminal 1. Consequently this transistor Q3 functions as a diode. The drain electrode of the MOS transistor T5 is connected to a current reference element I, whose other end is connected to the power-supply terminal 2. The current reference element I supplies the bias current for the arrangement and may be of any suitable integrable configuration known per se . The output signal of the arrangement is taken from an output terminal 5, which is connected to the drain electrode of the MOS transistor T2. The operation of the arrangement is as follows. By applying a step-function signal to the amplified, for example a digital squarewave signal, in phase opposition to the first input terminal 3 and the second input terminal 4 the transistors Q1 and Q2 are alternately turned on and turned off. This means that the circuits comprising the MOS transistors T1, T3 and the transistors T2, T4 are alternately turned on or turned-off. Consequently, the voltage on the drain electrode of the second MOS transistor T2 will vary between the power-supply voltage minus the voltage across the collector emitter path of the transistor Q2, and signal earth. Since the resistor R and the element C constitute a phase shifting network the gate voltage of the MOS transistor T1 will lag its drain voltage when this transistor is turned on or turned off at its drain electrode, depending on the values of R and C. As a result of this, the drain current will also lag the drain voltage. Therefore, an inductive circuit comprising the MOS transistor T1, the resistor R and the element C is arranged in parallel with the gate electrode of the second MOS transistor T2. This results in the stray capacitance at the gate electrode of T2 being charged and discharged more rapidly than without the parallel connected inductive circuit. This means that the transistor T2 is turned on and turned off comparatively rapidly, so that the output signal on its drain electrode will have comparatively steep edges. When the bandwidth of the arrangement is thus in fact, increased the occurrence of a delay of the output signal relative to the applied signal to be amplified can be avoided by suitably dimensioning the arrangement. The delay time is dictated by the choice of the values of R and C. In practice a value for R between 10 and 100 kOhms and for C between 100 and 1000 pF is found to be satisfactory. With these values it can also be achieved that when the MOS transistor T1 is turned off its gate voltage remains at a value above the threshold voltage, obviously related to the frequency of the signal to be amplified. When T1 is turned on again there will be no or only a very small delay, because the gate voltage need not first be brought above its threshold value before the transistor T1 can conduct. It is obvious that the arrangement can be modified in various ways, for example by replacing the current-mirror comprising P-channel MOS transistors by a current-mirror circuit comprising bipolar PNP transistors.

Claims: An amplifier arrangement for amplifying an input signal, comprising: a first and a second field-effect transistor (T1, T2) of a first conductivity type, a driver circuit (Q1, Q2, Q3, T3, T4, T5, I) for driving the first and the second transistor (T1, T2) in response to the input signal, characterized in that the driver circuit (Q1, Q2, Q3, T3, T4, T5, I) is coupled to a first power-supply terminal (1) and has a first and a second output, the drain-source path of the first transistor (T1) is coupled between the first output of the driver circuit (Q1, Q2, Q3, T3, T4, T5, I) and a second power-supply terminal (2), the drain-source path of the second transistor (T2) is coupled between the second output of the driver circuit (Q1, Q2, Q3, T3, T4, T5, I) and the second power-supply terminal (2), and the drain of the first transistor (T1) is coupled to the gate of the second transistor (T2) and through a resistive element (R) to the gate of the first transistor (T1), which gate of the first transistor is coupled to the second power-supply terminal (2) through a capacitive element (C). An amplifier arrangement as claimed in Claim 1, characterized in that the arrangement is constructed as an integrated circuit in which the resistive element (R) is an integrated resistor. An amplifier arrangement as claimed in Claim 2, characterized in that the capacitive element (C) is constituted by the gate-source capacitance of the first field-effect transistor (T1). An amplifier arrangement as claimed in Claim 3, characterized in that the resistive element (R) has a resistance between approximately 10 and 100 kohms and the capacitive element (C) has a capacitance between 100 and 1000 pF. An amplifier arrangement as claimed in any one or several of the Claims 1 to 4, characterized in that the driver circuit (Q1, Q2, Q3, T3, T4, T5, I) comprises a first and a second bipolar transistor (Q1, Q2), whose base electrodes respectively constitute a first and a second input terminal (3, 4) for the input signal to be amplified, which transistors (Q1, Q2) have their collector-emitter paths coupled between the first power-supply terminal (1) and the source electrodes of a third and a fourth field-effect transistor (T3, T4) of a second conductivity type respectively, the drain electrodes of the third and the fourth field-effect transistors (T3, T4) constituting the first and the second output of the driver circuit (Q1, Q2, Q3, T3, T4, T5, I) and the gate electrodes of the third and the fourth field-effect transistor (T3, T4) being interconnected and being connected to an output of a current-reference circuit (Q3, T5, I). An amplifier arrangement as claimed in Claim 5, characterized in that the current-reference circuit (Q3, T5, I) comprises between the first and the second supply terminal (1, 2) a series arrangement of a third bipolar transistor (Q3) connected as a diode, the source-drain path of a fifth field-effect transistor (T5) of the second conductivity type and a current-reference element (I), the drain and gate electrodes of said fifth field-effect transistor (T5) being interconnected and constituting the output of the current-reference circuit (Q3, T5, I).

Inventors: CORNELISSEN BERNARDUS HENRICUS, CORNELISSEN, BERNARDUS HENRICUS JOZEF
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1989
Main classification: H03K19
IPC codes: H03F1, H03K5, H03K19, H03F3