Master slice semiconductor integrated circuit device

Abstract: A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.

Description: The present invention relates to a technique of utilizing a master slice approach and, more particularly, to a master slice semiconductor integrated circuit device. A semiconductor integrated circuit or large scale integrated circuit device produced through the master slice approach is hereinafter referred to as a master slice type LSI device. The master slice approach generally comprises a first process of forming a master chip and a second process of forming a desired wiring pattern on the master chip. In the first process, a basic cell region including a plurality of basic cells, each consisting of a predetermined number of transistors, is formed together with an input/output (I/O) cell region on a chip using a common and fixed pattern mask. The second process is carried out in accordance with a specification or conditions demanded by a user and includes a plurality of steps. In this case, the second process normally includes four steps of: forming contact holes in a first insulation layer formed on the master chip; forming thereon a first wiring layer; forming through holes in a second insulation layer formed thereon; and forming thereon a second wiring layer so as to contact the first wiring layer via through holes. Therefore, four pattern masks corresponding to the contact hole, first wiring layer, through hole and second wiring layer are required to constitute a given circuit in the basic cell region. To cope with the above drawbacks, a so-called one custom mask approach has been recently proposed in the wiring patterning process. This one custom mask approach is a method of forming a wiring pattern on the master chip using a one layer custom mask (wiring pattern mask according to user's specification). According to the one custom mask approach, since the wiring pattern mask can be made common to a plurality of master slice type LSI devices, it becomes possible to easily realize the reduction of the turnaround time and the simplification of the process. GB-A-2 137 413 discloses a variable geometry automated universal array in which rows of basic cells are spaced apart by wiring corridors. Only a single, uppermost wiring layer is customized in the wiring corridors. No details are disclosed of the structure of the basic cells. JP-A-59 204 254 discloses a master slice integrated circuit in which basic cells are made up of source and drain regions separated from each other by wirings of a first wiring layer having a fixed pattern. Two of the fixed wirings take the form of electrodes extending along the length of the basic cell and constituting gate electrodes of basic cell transistors. Subsequent wiring layers, and the positions of through holes for making connections to the first wiring layer, are customized. JP-A-60 242 639 by the present applicant discloses a semiconductor integrated circuit device in which the basic cells are provided with electrodes extending along the length of each basic cell and constituting gate electrodes of basic cell transistors. These electrodes have enlarged or extended portions at their ends and their middles for facilitating electrical connection to wiring. According to the present invention, there is provided a master slice semiconductor integrated circuit device for realizing a given circuit desired by a user, the device comprising: a master chip including a plurality of basic cells and a plurality of wiring channels arrayed on the master chip, the wiring channels defining predetermined positions where wiring, contact holes or through holes can be formed; each basic cell being formed on a region of the master chip defined by at least fourteen first wiring channels extending in parallel along a first direction at a constant spacing, and at least three second wiring channels extending in parallel along a second direction perpendicular to the first direction at a constant spacing, and each basic cell comprising: a pair of p-channel transistors and a pair of n-channel transistors, each of the transistors having a gate, source, and drain; a pair of electrodes having an elongate shape and extending in parallel along the second direction to constitute gate electrodes of the transistors, each electrode being aligned along a respective one of said second wiring channels and having portions at both ends and at its middle extended in the first direction so as to overlie said first wiring channels thereby forming four end lead portions and two middle lead portions, for connecting the gate electrodes to wiring of the given circuit, the pair of electrodes being separated along the first direction by another one of said second wiring channels; said p-channel and n-channel transistors being respectively formed by p-type and n-type impurity regions arranged along the second direction, the p-type region being separated from said n-type region by a separation region of the master chip, the p-type region extending between one end and said middle lead portions of the electrodes, and the n-type region extending between said middle lead portions and the other end of the electrodes, said p-type region being divided in the first direction into physically separate first to third regions such that the third region lies in an area between the electrodes and the first and second regions respectively lie in areas on either side of the electrodes, said n-type region being likewise divided in the first direction into physically separate fourth to sixth regions such that the sixth region lies in an area between the electrodes and the fourth and fifth regions respectively lie in areas on either side of the electrodes; wherein a pair of said basic cells disposed in parallel along said first direction constitute a basic block for realizing said given circuit; and wherein the device further comprises: a first insulation layer formed on said master chip, having contact holes positioned on said wiring channels for permitting electrical contact to said p-type and n-type impurity regions and to said four end lead portions; a first wiring layer formed on said first insulation layer, constituted by fixed wirings which are predetermined irrespective of said given circuit, formed along said first and second wiring channels, and comprising wirings electrically connected to said contact holes; a second insulation layer formed on said first wiring layer, having through holes positioned on said wiring channels, said fixed wirings further comprising wirings electrically connected to and interconnecting said through holes; and a second wiring layer formed on said second insulation layer, including wirings formed along said first and second wiring channels in accordance with demanded conditions of said given circuit and electrically connected to said fixed wirings at said through holes. An embodiment of the present invention may provide a master slice type LSI device which can greatly reduce a turnaround time. Reference is made, by way of example, to the accompanying drawings in which:- Fig. 1 is a plan view schematically illustrating the whole constitution of a master chip in the master slice type LSI device of the present invention; Fig. 2 is a view for explaining a basic cell; Fig. 3 is a view illustrating a common pattern employed in a first embodiment of the present invention; Fig.s 4A to 4C are views illustrating examples of a second wiring layer pattern applied to the common pattern shown in Fig. 3; Fig. 5 is a view illustrating a common pattern employed in a second embodiment ; Figs. 6A to 6D are views illustrating examples of a second wiring layer pattern applied to the common pattern shown in Fig. 5; Fig. 7 is a view illustrating a common pattern employed in a third embodiment ; Figs. 8A to 8D are views illustrating examples of a second wiring layer pattern applied to the common pattern shown in Fig. 7; Fig. 9 is a view illustrating a common pattern employed in a fourth embodiment ; Figs. 10A to 10D are views illustrating examples of a second wiring layer pattern applied to the common pattern shown in Fig. 9; Figs. 11 is a view illustrating a common pattern employed in a fifth embodiment ; Figs. 12A to 12D are views illustrating examples of a second wiring layer pattern applied to the common pattern shown in Fig. 11; Fig. 13 is a block diagram for explaining the concept of designing the master slice type LSI device; and Figs. 14A to 14C are sectional views for explaining a process of producing the master slice type LSI device. Figure 1 schematically illustrates a whole constitution of a master chip in the master slice type LSI device of the present invention. In Fig.1, reference 201 denotes a basic cell region, which is formed on the central region of a master chip 203 and includes a plurality of basic cell arrays 206 extending along Y direction at a predetermined space therebetween. Each of the basic cell arrays 206 includes a plurality of pairs of basic cells 204,205, and each pair of basic cells are parallelly disposed along X direction perpendicular to Y direction. Namely, a plurality of basic cells 204,205 are arranged in the form of a so-called double column structure on the master chip. Reference 202 denotes an I/O cell region, which is formed along the periphery of the master chip 203 and includes a plurality of I/O cells 207. A concrete constitution of each I/O cell will be described later. Reference 208 denotes a wiring channel region formed between adjacent basic cell arrays 206. Figure.2 illustrates a portion of the basic cell array shown in Fig.1. As shown in Fig.2, each basic cell 1 (corresponding to the basic cell 204 or 205 in Fig.1) is constituted by a pair of p-channel transistors Qp connected in series and a pair of n-channel transistors Qn connected in series. One of the p-channel transistors is constituted by a gate electrode 2 and p-type impurity regions 4,5 serving as a source/drain, and another is constituted by a gate electrode 3 and p-type impurity regions 5,6 serving as a source/drain. Also, one of the n-channel transistors is constituted by a gate electrode 2 and n-type impurity regions 7,8 serving as a source/drain, and another is constituted by a gate electrode 3 and p-type impurity regions 8,9 serving as a source/drain. Reference 10 denotes a separation region for separating a region on which p-channel transistors are formed from a region on which n-channel transistors are formed. References 11 to 16 denote lead portions used for connecting gate electrodes 2,3 to each portion of a given logic circuit or gate, which are constituted by a portion of the gate electrodes and formed in each end portion and each central portion, respectively. The lead portions 11 to 16 are hereinafter referred to as gate electrode lead portions. The gate electrode lead portions 11 to 16 and the gate electrodes 2,3 are composed of, for example, polysilicon. Also, reference B1 indicates a basic block in which the logic circuit or gate is formed, and which is constituted by a pair of basic cells 1 parallelly disposed along a longitudinal (Y) direction. Reference B2 indicates a basic block as well, which is constituted by a single basic cell 1. Next, preferred embodiments according to the present invention will be explained with reference to Figs.3 to 14D. (1) First Embodiment (see Figs.3 to 4C) Figure 3 illustrates a common pattern employed in the first embodiment. In Fig.3, solid round marks indicate contact holes formed in the first insulation layer; (thin) solid lines indicate fixed wirings formed in the first wiring layer; and empty round marks indicate through holes formed in the second insulation layer. In the present embodiment, a given logic circuit or gate is constituted with a unit of the basic block B1 consisting of a pair of basic cells. Note, the manner of each indication of the contact holes, first wiring layer(wirings) and through holes is common to other embodiments and applications described later. In a wafer process, the common pattern of Fig.3 is formed by: forming the basic cell array as shown in Fig.2; forming thereon the first insulation layer consisting of, for example, silicon oxide, by chemical vapor deposition; forming contact holes at predetermined positions of the first insulation layer; forming thereon the first wiring layer including predetermined fixed wirings; forming thereon the second insulation layer consisting of, for example, phospho-silicate glass, by chemical vapor deposition; and forming through holes at predetermined positions of the second insulation layer. Next, the arrangement of each pattern of the contact holes, first wiring layer(wirings) and through holes will be explained. Referring to Fig.3, each basic cell is formed on a region defined by three wiring channels CX1 ~ CX3 parallelly extending in parallel along a horizontal (X) direction at a constant space therebetween, hereinafter referred to as horizontal wiring channels, and fourteen wiring channels CY1 ~ CY14 parallelly extending along a vertical (Y) direction at a constant space therebetween, hereinafter referred to as vertical wiring channels. The contact holes, first wiring layer(wirings) and through holes are formed at predetermined positions defined by horizontal wiring channels and vertical wiring channels. As shown in Fig.3, each pattern of the contact holes, first wiring layer(wirings) and through holes is formed in the symmetrical arrangement with respect to the center of the basic block B1. Namely, the first insulation layer includes one contact hole 17~26 in each region corresponding to the gate electrode lead portions 11~14 and the impurity regions 4 ~ 9, and the second insulation layer includes, one through hole 27~30 in each region corresponding to the gate electrode lead portions 11~14, three through holes 31~33 in each region corresponding to the impurity regions 4,6,7,9, and four through holes 34~37 in a region corresponding to the separation region 10. Also, the first wiring layer includes: wirings 38, each connecting a contact hole to a through hole in each region corresponding to the gate electrode lead portions 11~14; wirings 39, each connecting a pair of through holes between each region corresponding to the impurity regions 4 and 6, between each region corresponding to the impurity regions 7 and 9, respectively; wirings 40, each connecting another pair of through holes between each region corresponding to the impurity regions 4,6, between each region corresponding to the impurity regions 7,9, respectively, and extending along one of the vertical wiring channels CY1 ~CY14, and mainly serving as a power supply line; wirings 41, each connecting a contact hole to a through hole in each region corresponding to the impurity regions 4,6,7,9; wirings 42, each connecting a contact hole in each region corresponding to the impurity regions 5,8, respectively, to a corresponding through hole in a region corresponding to the separation region 10; and wirings 43, each connecting another through hole in a region corresponding to the separation region to a corresponding through hole provided in a region corresponding to a separation region included in the adjacent basic cell. Figures. 4A to 4C illustrate various examples of the second wiring layer pattern constituting a logic circuit or gate based on the common pattern shown in Fig. 3, together with an equivalent circuit diagram symbolically shown. In each drawing, (thick) solid lines indicate wirings formed in the second wiring layer. Note, the manner of the indication of the second wiring layer(wirings) is common to other embodiments and applications described later. As explained above, according to the first embodiment, it is possible to easily realize a desired logic circuit or gate by suitably changing only the second wiring layer pattern in accordance with demanded conditions of a given circuit. Accordingly, the turnaround time of the master slice type LSI device can be greatly reduced. (2) Second Embodiment (see Figs.5 to 6D) Figure 5 illustrates a common pattern employed in the second embodiment. In the present embodiment, a given logic circuit or gate is constituted with a unit of the basic block B1 as in the first embodiment, and each basic cell is formed on a region defined by three horizontal wiring channels CX1 ~ CX3 and fourteen vertical wiring channels CY1 ~CY14. The process of forming the illustrated common pattern is the same as that of the first embodiment and, accordingly, the explanation thereof is omitted. As shown in Fig.5, each pattern of the contact holes, first wiring layer(wirings) and through holes is formed in a symmetrical arrangement with respect to the center of the basic block B1. Namely, the first insulation layer includes one contact hole 44 ~49 in each region corresponding to the gate electrode lead portions 11~14 and the impurity regions 4,6,7,9, and two contact holes 50,51 in each region corresponding to the impurity regions 5,8. The second insulation layer includes: one through hole 52,53 in each region corresponding to the gate electrode lead portions 11 ~14; three through holes 54~56 in each region corresponding to one of the impurity regions 4,6 and one of the impurity regions 7,9; two through holes 57,58 in each region corresponding to another of the impurity regions 4,6 and another of the impurity regions 7,9; two through holes 59,60 in a region corresponding to the separation region 10; and two through holes 61,62 in a region corresponding to each cell-to-cell wiring channel BCX1,BCX2. Also, the first wiring layer includes: wirings 63, each connecting a contact hole to a through hole in each region corresponding to the gate electrode lead portions 11~14; wirings 64, each connecting a contact hole in each region corresponding to the impurity regions 5,8, respectively, to a corresponding through hole in each region corresponding to one of the impurity regions 4,6 and one of the impurity regions 7,9; wirings 65, each connecting a pair of through holes between each region corresponding to the impurity regions 4,6, between each region corresponding to the impurity regions 7,9, respectively, and extending along one of the vertical wiring channels CY1 ~CY14, and mainly serving as a power supply line; wirings 66,67, each connecting a contact hole to a through hole in each region corresponding to the impurity regions 4,6,7,9; wirings 68, each connecting a contact hole in each region corresponding to the impurity regions 5,8, respectively, to a corresponding through hole in a region corresponding to the separation region 10; and wirings 69, each connecting two through holes provided in a region corresponding to each cell-to-cell wiring channel. Figures. 6A to 6D illustrate various examples of the second wiring layer pattern constituting a logic circuit or gate based on the common pattern shown in Fig. 5, together with an equivalent circuit diagram symbolically shown. The second embodiment has the same advantage as in the first embodiment, i.e., reduction of the turnaround time, plus the following advantages: Since the cell-to-cell wiring channels BCX1,BCX2 extending parallelly to the horizontal wiring channels CX1~ CX3 are provided between adjacent basic cells, and two through holes 61,62 and the wiring 69 are provided along each cell-to-cell wiring channel, the wiring 69 can be utilized as a signal line extending in the horizontal direction. As a result, it is possible to easily effect a connection between basic cells disposed in the horizontal direction. This enables formation of a large scale circuit. (3) Third Embodiment (see Figs.7 to 8D) Figure 7 illustrates a common pattern employed in the third embodiment. In the present embodiment, a given logic circuit or gate is constituted with a unit of the basic block B1 as in the first embodiment, and each basic cell is formed on a region defined by three horizontal wiring channels CX1~CX3 and fourteen vertical wiring channels CY1 ~CY14. The process of forming the illustrated common pattern is the same as that of the first embodiment and, accordingly, the explanation thereof is omitted. As shown in Fig.7, each pattern of the contact holes, first wiring layer(wirings) and through holes is formed in the symmetrical arrangement with respect to the center of the basic block B1. Namely, the first insulation layer includes one contact hole 70 ~72 in each region corresponding to the gate electrode lead portions 11~14 and the impurity regions 4,6,7,9, and two contact holes 73,74 in each region corresponding to the impurity regions 5,8, and the second insulation layer includes: one through hole 75 in each region corresponding to the gate electrode lead portions 11~14; three through holes 76~78 in each region corresponding to one of the impurity regions 4,6 and one of the impurity regions 7,9; two through holes 79,80 in each region corresponding to another of the impurity regions 4,6 and another of the impurity regions 7,9; two through holes 81,82 in a region corresponding to the separation region 10; and four through holes 83 ~86 in a region corresponding to each cell-to-cell wiring channel BCX1,BCX2. Also, the first wiring layer includes: wirings 87, each connecting a contact hole to a through hole in each region corresponding to the gate electrode lead portions 11~14; wirings 88, each connecting a contact hole in each region corresponding to said the impurity regions 5,8, respectively, to a corresponding through hole in each region corresponding to one of the impurity regions 4,6 and one of the impurity regions 7,9; wirings 89, each connecting a pair through holes between each region corresponding to the impurity regions 4,6, between each region corresponding to the impurity regions 7,9, respectively, and extending along one of the vertical wiring channels CY1 ~CY14, and mainly serving as a power supply line; wirings 90, each connecting a contact hole to a through hole in each region corresponding to the impurity regions 4,6,7,9; wirings 91, each connecting a contact hole in each region corresponding to the impurity regions 5,8, respectively, to a corresponding through hole in a region corresponding to the separation region 10; and wirings 92, each intermittently connecting each through hole provided in a region corresponding to each cell-to-cell wiring channel so that it is out of contact with the power supply line, i.e., the wiring 89. Figures. 8A to 8D illustrate various examples of the second wiring layer pattern constituting a logic circuit or gate based on the common pattern shown in Fig. 7, together with an equivalent circuit diagram symbolically shown. The third embodiment has the same advantage as in the first embodiment, i.e., reduction of the turnaround time, plus the following advantages: Since each wiring 92 provided along each cell-to-cell wiring channel intermittently connects each through hole 83 ~86 provided thereon so that it is not short-circuited to the wiring 89 serving as the power supply line, the wiring 89 can be continuously formed along the vertical direction without using contact holes. Accordingly, it is possible to decrease the voltage drop caused when currents flow through the the power supply line 89. This contributes to an increase in the speed of the circuit operation. (4) Fourth Embodiment (see Figs.9 to 10D) Figure 9 illustrates a common pattern employed in the fourth embodiment. In the present embodiment, a given logic circuit or gate is constituted with a unit of the basic block B1 as in the first embodiment, and each basic cell is formed on a region defined by three horizontal wiring channels CX1 ~ CX3 and sixteen vertical wiring channels CY1~CY16. The process of forming the illustrated common pattern is the same as that of the first embodiment and, accordingly, the explanation thereof is omitted. As shown in Fig.9, each pattern of the contact holes, first wiring layer(wirings) and through holes is formed in the symmetrical arrangement with respect to the center of the basic block B1. Namely, the first insulation layer includes one contact hole 93 ~95 in each region corresponding to the gate electrode lead portions 11~14 and the impurity regions 4,6,7,9, and two contact holes 96,97 in each region corresponding to the impurity regions 5,8, and the second insulation layer includes: one through hole 98 in each region corresponding to the gate electrode lead portions 11~14; three through holes 99~101 in each region corresponding to one of the impurity regions 4,6 and one of the impurity regions 7,9; two through holes 102,103 in each region corresponding to another of the impurity regions 4,6 and another of the impurity regions 7,9; two through holes 104,105 in a region corresponding to the separation region 10; and four through holes 106 ~109 in a region corresponding to each cell-to-cell wiring channel BCX1~BCX3. Also, the first wiring layer includes: wirings 110, each connecting a contact hole to a through hole in each region corresponding to the gate electrode lead portions 11 ~14; wirings 111, each connecting a contact hole in each region corresponding to said the impurity regions 5,8, respectively, to a corresponding through hole in each region corresponding to one of the impurity regions 4,6 and one of the impurity regions 7,9; wirings 112, each connecting a pair through holes between each region corresponding to the impurity regions 4,6, between each region corresponding to the impurity regions 7,9, respectively, and extending along one of the vertical wiring channels CY1 ~CY16, and mainly serving as a power supply line; wirings 113,114, each connecting a contact hole to a through hole in each region corresponding to the impurity regions 4,6,7,9; wirings 115, each connecting a contact hole in each region corresponding to the impurity regions 5,8, respectively, to a corresponding through hole in a region corresponding to the separation region 10; and wirings 116, each intermittently connecting each through hole provided in a region corresponding to each cell-to-cell wiring channel so that it is out of contact with the power supply line, i.e., the wiring 112. Figures. 10A to 10D illustrate various examples of the second wiring layer pattern constituting a logic circuit or gate based on the common pattern shown in Fig. 9, together with an equivalent circuit diagram symbolically shown. The fourth embodiment has the same advantage as in the first embodiment, i.e., reduction of the turnaround time, plus the following advantages: Since the number of the vertical wiring channels is increased to sixteen(CY1 ~CY16) compared with the third embodiment, the position of the through hole 107 provided on the cell-to-cell wiring channel can be shifted by a distance corresponding to a space between wiring channels from that of the through hole 101 provided on the basic cell. Accordingly, it is possible to form a pair of series-connected transmission gates on one basic cell, i.e., on half of the region of the basic block, as shown in Fig.10D. This contributes to reduction in the formation area of the pattern. Especially, where a circuit including two series-connected transmission gates as a constituent element, e.g., a flipflop circuit, counter circuit or the like, is formed, the present embodiment is advantageous in that it is possible to realize a high degree of integration of the circuit. (5) Fifth Embodiment (see Figs.11 to 12D) Figure 11 illustrates a common pattern employed in the fifth embodiment. In the present embodiment, a given logic circuit or gate is constituted with a unit of the basic block B1 as in the first embodiment, and each basic cell is formed on a region defined by three horizontal wiring channels CX1 ~ CX3 and fourteen vertical wiring channels CY1 ~CY14. The process of forming the illustrated common pattern is the same as that of the first embodiment and, accordingly, the explanation thereof is omitted. As shown in Fig.11, each pattern of the contact holes, first wiring layer(wirings) and through holes is formed in the symmetrical arrangement with respect to the center of the basic block B1. Namely, the first insulation layer includes one contact hole 117 ~120 in each region corresponding to the gate electrode lead portions 11 ~14 and the impurity regions 4 ~9, and the second insulation layer includes: one through hole 121 in each region corresponding to the gate electrode lead portions 11 ~14 and the impurity regions 5,8; two through holes 122~125 in each region corresponding to the impurity regions 4,6,7,9; two through holes 126,127 in a region corresponding to the separation region 10; and four through holes 128 ~131 in a region corresponding to each cell-to-cell wiring channel BXC1~BCX3. Also, the first wiring layer includes: wirings 132, each connecting a contact hole to a through hole in each region corresponding to the gate electrode lead portions 11 ~14; wirings 133, each connecting a pair of through holes between each region corresponding to the impurity regions 4, 6, between each region corresponding to the impurity regions 7,9, respectively, and extending along one of the vertical wiring channels CY1 ~CY14, and mainly serving as a power supply line; wirings 134,135, each connecting a contact hole to a through hole in each region corresponding to the impurity regions 4,6,7,9; wirings 136, each connecting a contact hole in each region corresponding to the impurity regions 5,8, respectively, to a corresponding through hole in a region corresponding to the separation region 10; and wirings 137, each intermittently connecting each through hole provided in a region corresponding to each cell-to-cell wiring channel so that it is out of contact with the power supply line, i.e., the wiring 133. Figures. 12A to 12D illustrate various examples of the second wiring layer Dattern constituting a logic circuit or gate based on the common pattern shown in Fig. 11, together with an equivalent circuit diagram symbolically shown. The fifth embodiment has the same advantage as in the first embodiment, i.e., reduction of the turnaround time, plus the following advantages: According to the present embodiment, it is possible to form two series-connected transmission gates on one basic cell as shown in Fig.12D, as in the fourth embodiment (see Fig.10D). In this case, since the number of the vertical wiring channels is decreased to fourteen(CY1~CY14) compared with the fourth embodiment, it is possible to realize a further high degree of integration of the circuit. Although only the logic circuits or gates having a fundamental function are illustrated in Figs. 3 to 12D, it is apparent to those skilled in the art that other embodiments and modifications are possible by suitably changing only the second wiring layer pattern. Next, a constitution of an apparatus for designing the master slice type LSI device will be described with reference to Fig. 13. The illustrated designing apparatus 400 comprises a fundamental mask pattern memory means 401, a wiring mask pattern memory means 402 and a pattern synthesizing means 403. The fundamental mask pattern memory means 401 stores two kinds of fundamental mask pattern information. One is a first fundamental mask pattern information consisting of four kinds of mask patterns, i.e., contact holes NA, first wiring layer(wirings) LA, through holes NB and second wiring layer(wirings) LB, necessary for forming a demanded connection between constituent elements in the basic cell region. Another is a second fundamental mask pattern information consisting of four kinds of mask patterns, i.e., contact holes NA, first wiring layer(wirings) LA, through holes NB and second wiring layer(wirings) LB, necessary for forming a demanded connection between constituent elements in the I/O circuits provided on the master chip. Also, the wiring mask pattern memory means 402 stores two kinds of wiring mask pattern information. One is a first plurality of wiring mask patterns with respect to one wiring layer to be combined on the fundamental mask patterns, and another is a second plurality of wiring mask patterns necessary for forming one wiring layer in the program points in accordance with the kind of the I/O circuit to constitute the connection portions. The mask pattern of the internal circuit (basic cells) in the LSI is generated based on the first fundamental mask pattern information stored in the fundamental mask pattern memory means 401 and the first wiring mask pattern information stored in the wiring mask pattern memory means 402. On the other hand, the mask pattern of the I/O circuit in the LSI is generated based on the second fundamental mask pattern information and the second wiring mask pattern information. The second fundamental mask pattern information and the second wiring mask pattern information corresponding to the kind of the I/O circuit are read out by the pattern synthesizing means 403, where both groups of pattern information are synthesized to generate the mask pattern 404 of the I/O circuit. Thus, the designing of the mask pattern of the I/O circuit can be facilitated and, accordingly, it is possible to greatly reduce time needed for the designing, compared with the prior art designing apparatus. Next, a method of producing the master slice type LSI device will be explained with reference to Figs. 14A to 14C. The method of producing the master slice type LSI device roughly classifying, includes the steps of forming the basic cell regions 201 together with the I/O cell regions 202 (see Fig.1) and forming the wiring pattern using a custom mask on the cell reqions. As shown in Fig. 14A, the basic cell regions and I/O cell regions are produced by: forming an insulation layer 301 consisting of silicon oxide and including contact holes NA (not shown) on a semiconductor substrate 300; forming thereon the first wiring layer LA by aluminium(Al) evaporation; forming thereon an insulation layer 302 consisting of silicon oxide; forming through holes NB in the insulation layer 302 so that they contact the first wiring layer LA; and forming thereon a conduction layer 303. Next, the mask pattern (including the mask pattern 404 of the I/O circuit) is designed by the designing apparatus 400 (see Fig.13) in accordance with the user's specification and then a desired wiring patterning is effected on the conduction layer 303 by etching process using the designed mask pattern (see Fig.14B). As a result of the above steps, a desired second wiring layer LB is formed as shown in Fig.14C, and the master slice type LSI device according to the user's specification can be produced. As explained above, it is possible to produce a desired master slice type LSI device easily and in a short period by suitably designing only the mask pattern of the second wiring layer. Especially, since one custom mask approach is applied to the I/O cell region, it is possible to greatly reduce the turnaround time of the device. Also, since the conduction layer is formed on the entire insulation layer in forming the master chip, the subsequent process of wiring patterning can be omitted. This simplifies a process of producing the LSI device and, accordingly, contributes to the reduction in the turnaround time. Although the present invention has been disclosed and described by way of various embodiments, it is apparent to those skilled in the art that the other embodiments and modifications of the present invention are possible within the scope of the accompanying claims.

Claims: A master slice semiconductor integrated circuit device for realizing a given circuit desired by a user, the device comprising: a master chip (203) including a plurality of basic cells (1) and a plurality of wiring channels arrayed on the master chip, the wiring channels defining predetermined positions where wiring, contact holes or through holes can be formed; each basic cell being formed on a region of the master chip defined by at least fourteen first wiring channels (CY1-CY14; CY1-CY16) extending in parallel along a first direction (Y) at a constant spacing, and at least three second wiring channels (CX1-CX3) extending in parallel along a second direction (X) perpendicular to the first direction (Y) at a constant spacing, and each basic cell comprising: a pair of p-channel transistors (Q p ) and a pair of n-channel transistors (Q n ), each of the transistors having a gate, source, and drain; a pair of electrodes (2,3) having an elongate shape and extending in parallel along the second direction (X) to constitute gate electrodes of the transistors, each electrode (2,3) being aligned along a respective one of said second wiring channels (CX1-CX3), and having portions at both ends and at its middle extended in the first direction (Y) so as to overlie said first wiring channels (CY1-CY14;CY1-CY16), thereby forming four end lead portions (11,12,13,14), and two middle lead portions (15,16) , for connecting the gate electrodes to wiring of the given circuit, the pair of electrodes (2,3) being separated along the first direction (Y) by another one of said second wiring channels (CX1-CX3); said p-channel and n-channel transistors being respectively formed by p-type and n-type impurity regions arranged along the second direction (X), the p-type region being separated from said n-type region by a separation region (10) of the master chip, the p-type region extending between one end and said middle lead portions (15,16) of the electrodes (2,3), and the n-type region extending between said middle lead portions (15,16) and the other end of the electrodes (2,3), said p-type region being divided in the first direction (Y) into physically separate first to third regions (4,6,5) such that the third region (5) lies in an area between the electrodes (2,3) and the first and second regions (4,6) respectively lie in areas on either side of the electrodes (2,3), said n-type region being likewise divided in the first direction (Y) into physically separate fourth to sixth regions (7,9,8) such that the sixth region (8) lies in an area between the electrodes (2,3) and the fourth and fifth regions (7,9) respectively lie in areas on either side of the electrodes (2,3); wherein a pair of said basic cells (1) disposed in parallel along said first direction constitute a basic block (B1) for realizing said given circuit; and wherein the device further comprises: a first insulation layer (301) formed on said master chip, having contact holes (NA) positioned on said wiring channels for permitting electrical contact to said p-type and n-type impurity regions and to said four end lead portions (11-14); a first wiring layer (LA) formed on said first insulation layer (301), constituted by fixed wirings which are predetermined irrespective of said given circuit, formed along said first and second wiring channels, and comprising wirings electrically connected to said contact holes (NA); a second insulation layer (302) formed on said first wiring layer, having through holes (NB) positioned on said wiring channels, said fixed wirings further comprising wirings electrically connected to and interconnecting said through holes (NB); and a second wiring layer (LB) formed on said second insulation layer, including wirings formed along said first and second wiring channels in accordance with demanded conditions of said given circuit and electrically connected to said fixed wirings at said through holes. A device as set forth in claim 1, further comprising at least one cell-to-cell wiring channel (BCX1-BCX3) extending along said second direction (X) in a region between adjacent basic cells (1) of a basic block (B1), and disposed along said first direction. A device as set forth in claim 1, wherein there are fourteen of said first wiring channels (CY1-CY14), and wherein: said first insulation layer includes one contact hole (17-26) at each of said four end lead portions (11-14) and said first to sixth impurity regions (4-9); said second insulation layer includes: one through hole (27-30) at each of said four end lead portions (11-14); three through holes (31-33) at each of said first, second, fourth and fifth impurity regions (4,6,7,9); and four through holes (34-37) at said separation region (10); and said first wiring layer includes: wirings (38) within the areas of each of the four end lead portions (11-14), connecting a contact hole to a through hole; wirings (39) extending from a through hole at said first impurity region (4) to a through hole at said second impurity region (6), and extending from a through hole at said fourth impurity region (7) to a through hole at said fifth impurity region (9); wirings (40) extending from another through hole at said first impurity region (4) to another through hole at said second impurity region (6), and extending from another through hole at said fourth impurity region (7) to another through hole at said fifth impurity region (9), these wirings (40) further extending along respective ones of said first wiring channels (CY1-CY14) and mainly serving as power supply lines; wirings (41) within the areas of each of the first, second, fourth and fifth impurity regions (4,6,7,9), each connecting a contact hole to a through hole; wirings (42) extending from a contact hole (22,25) at each of said third and sixth impurity regions (5,8) to a corresponding through hole (34,35) at said separation region (10); and wirings (43) extending from a through hole (35,37) at said middle lead portion (16) to a corresponding through hole at a middle lead portion of an adjacent basic cell (1). A device as set forth in claim 2, wherein there are fourteen of said first wiring channels (CY1-CY14), and wherein: said first insulation layer includes one contact hole (44-49) at each of said four end lead portions (11-14) and said first, second, fourth and fifth impurity regions (4,6,7,9), and two contact holes (50,51) at each of said third and sixth impurity regions (5,8); said second insulation layer includes: one through hole (52,53) at each of said four end lead portions (11-14); three through holes (54-56) at one of said first and second impurity regions and one of said fourth and fifth impurity regions; two through holes (57,58) at another of said first and second impurity regions and another of said fourth and fifth impurity regions; two through holes (59,60) at said separation region; and two through holes (61,62) at said cell-to-cell wiring channel (BCX1,BCX2); and said first wiring layer includes: wirings (63) within the areas of each of the four end lead portions (11-14), connecting a contact hole to a through hole; wirings (64) extending from a contact hole (50) at said third impurity region (5) to a corresponding through hole (54) at said first or second impurity region (4 or 6), and extending from a contact hole at said sixth impurity region (8) to a corresponding through hole at said fourth of fifth impurity region (7 or 9); wirings (65) extending from a through hole (55) at said first impurity region (4) to a through hole (57) at said second impurity region (6), and extending from a through hole at said fourth impurity region (7) to a through hole at said fifth impurity region (9), these wirings (65) further extending along respective ones of said first wiring channels (CY1-CY14) and mainly serving as power supply lines; wirings (66,67) within the areas of each of the first, second, fourth and fifth impurity regions (4,6,7,9) respectively, each connecting a through hole to a contact hole; wirings (68) extending from a contact hole at each of said third and sixth impurity regions (5,8) to corresponding through holes at said separation region (10); and a wiring (69) connecting said through holes (61,62) at said cell-to-cell wiring channel (BCX1-BCX2). A device as set forth in claim 2, wherein there are fourteen of said first wiring channels (CY1-CY14), and wherein: said first insulation layer includes one contact hole (70-72) at each of said four end lead portions (11-14) and said first, second, fourth and fifth impurity regions (4,6,7,9), and two contact holes (73,74) at each of said third and sixth impurity regions (5,8); said second insulation layer includes: one through hole (75) at each of said four end lead portions (11-14); three through holes (76-78) at one of said first and second impurity regions and at one of said fourth and fifth impurity regions; two through holes (79,80) at the other of said first and second impurity regions and at the other of said fourth and fifth impurity regions; two through holes (81,82) at said separation region; and four through holes (83-86) at said cell-to-cell wiring channel (BCX1,BCX2); and said first wiring layer includes: wirings (87) within the areas of each of the four end lead portions (11-14), connecting a contact hole to a through hole; wirings (88) extending from a contact hole (73) at said third impurity region to a corresponding through hole (76) at said first or second impurity region, and extending from a contact hole at said sixth impurity region to a corresponding through hole at said fourth or fifth impurity region; wirings (89) extending from a through hole at said first impurity region to a through hole at said second impurity region, and extending from a through hole at said fourth impurity region to a through hole at said fifth impurity region, these wirings (89) further extending along respective ones of said first wiring channels (CY1-CY14) and mainly serving as power supply lines; wirings (90) within the areas of each of the first, second, fourth and fifth impurity regions, each connecting a contact hole to a through hole; wirings (91) extending from a contact hole at each of the third and sixth impurity regions to corresponding through holes at the separation region (10); and wirings (92) each connecting a pair of said through holes (83-86) at said cell-to-cell wiring channel (BCX1,BCX2) without contacting said power supply lines (89). A device as set forth in claim 2, wherein there are sixteen of said first wiring channels (CY1-CY16), and wherein: said first insulation layer includes one contact hole (93-95) at each of said four end lead portions (11-14) and said first, second, fourth and fifth impurity regions, and two contact holes (96,97) at each of said third and sixth impurity regions; said second insulation layer includes: one through hole (98) at each of said four end lead portions; three through holes (99-101) at one of said first and second impurity regions and at one of said fourth and fifth impurity regions; two through holes (102,103) at the other of said first and second impurity regions and at the other of said fourth and fifth impurity regions; two through holes (104,105) at said separation region (10); and four through holes (106-109) at said cell-to-cell wiring channel (BCX1,BCX3); and said first wiring layer includes: wirings (110) within the areas of each of the four end lead portions (11-14), connecting a contact hole to a through hole; wirings (111) extending from a contact hole at said third impurity region to a corresponding through hole at said first or second impurity region, and extending from a contact hole at said sixth impurity region to a corresponding through hole at said fourth or fifth impurity region; wirings (112) extending from a through hole at said first impurity region to a through hole at said second impurity region, and extending from a through hole at said fourth impurity region to a through hole at said fifth impurity region, these wirings (112) further extending along respective ones of said first wiring channels (CY1-CY16) and mainly serving as power supply lines; wirings (113,114) within the areas of each of the first, second, fourth and fifth impurity regions, each connecting a contact hole to a through hole; wirings (115) extending from a contact hole at each of the third and sixth impurity regions to corresponding through holes at the separation region (10); and wirings (116) each connecting a pair of said through holes (106-109) at said cell-to-cell wiring channel (BCX1-BCX3) without contacting said power supply lines (112). A device as set forth in claim 2, wherein there are fourteen of said first wiring channels (CY1-CY14), and wherein: said first insulation layer includes one contact hole (117-120) at each of said four end lead portions and said first to sixth impurity regions; said second insulation layer includes: one through hole (121) at each of said four end lead portions and said third and sixth impurity regions; two through holes (122-125) at each of said first, second, fourth and fifth impurity regions; two through holes (126,127) at one (16) of said middle lead portions; and four through holes (128-131) at said cell-to-cell wiring channel (BCX1-BCX3); and said first wiring layer includes: wirings (132) within the areas of each of the four end lead portions (11-14), connecting a contact hole to a through hole; wirings (133) extending from a through hole at said first impurity region to a through hole at said second impurity region, and extending from a through hole at said fourth impurity region to a through hole at said fifth impurity region, these wirings (133) further extending along respective ones of said first0 wiring channels (CY1-CY14) and mainly serving as power supply lines; wirings (134,135) within the areas of each of the first, second, fourth and fifth impurity regions, each connecting a contact hole to a through hole; wirings (136) extending from a contact hole at each of the third and sixth impurity regions to corresponding through holes (126,127) at the middle lead portion (16); and wirings (137), each connecting a pair of said through holes (128-131) at said cell-to-cell wiring channel (BCX1-BCX3) without contacting said power supply line (133).

Inventors: HIROSE YOSHIO, KAWAHARA SHIGEKI, KUMAGAI ATARU, SASAKI TAKESHI, SATO SHINJI, YAMASHITA KOICHI, HIROSE, YOSHIO, KAWAHARA, SHIGEKI, KUMAGAI, ATARU, SASAKI, TAKESHI, SATO, SHINJI, YAMASHITA, KOICHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H01L27
IPC codes: H01L27, H01L23, H01L21