TTL TOTEM POLE ANTI-SIMULTANEOUS CONDUCTION CIRCUIT

Abstract: An anti-simultaneous conduction transistor is incorporated into the standard TTL circuit totem pole to reduce simultaneous conduction of the pullup and pulldown transistor elements of the totem pole. The collector of the active discharge anti-simultaneous conduction transistor element (Q5) is operatively coupled to a base of the pullup transistor element (Q2,Q3) through a diode (D5), the emitter is coupled to low potential, and the base is coupled to the base of the pulldown transistor element (Q4) through ballast resistance (R6,R7). The anti-simultaneous conduction transistor element (Q5) mirrors the conducting state of the pulldown transistor element (Q4) without current hogging substantially diverting or discharging base current from the base of the pullup transistor element (Q2,Q3) whenever the pulldown transistor element (Q4) is conducting. Undesirable current spikes in the sourcing current are avoided by preventing simultaneous conduction in the totem pole.

Description: The present invention relates to an improvement in electronic circuits, and particularly TTL circuits incorporating a totem pole. The invention provides an anti-simultaneous conduction circuit which reduces simultaneous conduction of the pullup transistor element and pulldown transistor element. By reducing simultaneous conduction at the totem pole, the anti-simultaneous conduction circuit of the present invention reduces current spikes from the TTL power supply. Typical TTL circuits incorporating a totem pole include TTL buffers, TTL output gates or devices, TTL to ECL, and ECL to TTL converters, etc. A prior art TTL output device is illustrated in Figure 1. A pullup transistor element, Darlington transistor pair Q2 and Q3, sources current from the positive TTL power supply V cc through collector resistor R4 to an output node V o . A pulldown transistor element Q4 sinks current from the output node V o to ground or low potential. The phase splitter transistor Q1 controls the conducting states of the pullup transistor element Darlington pair Q2, Q3 and the pulldown transistor element Q4 in response to high and low level logic signals at the input node V IN so that the pullup and pulldown transistor elements are generally in opposite conducting states. The base of phase splitter transistor Q1 is coupled to the input node V IN through the diode network D1,D2,D3 which delivers base drive current to phase splitter transistor Q1 from the TTL power supply V cc through resistor R1 when the input signal at input node V IN is at the logic high level. When a logic low level signal appears at the input node V IN the phase splitter transistor Q1 is deprived of base drive current. The TTL output gate of Figure 1 is therefore inverting as a logic high level potential signal at input node V IN produces a logic low level potential signal at output node V o and vice versa. With a high level potential signal at V IN , phase splitter Q1 conducts current from TTL power supply V cc through resistor R2. Current is diverted from the base of the Darlington transistor Q2. Phase splitter transistor Q1 drives the base of the pulldown transistor element Q4. Diode D4 helps discharge the base of Darlington transistor Q3 during the transition from high to low at the output. With a low level potential signal at V IN , phase splitter transistor Q1 is not conducting, the pulldown transistor element Q4 is deprived of base drive, and current from TTL power supply V cc through resistor R2 drives the base of the pullup transistor element Q2. Resistor R3 is the discharge path for the pulldown transistor Q4. The combination of the pullup transistor element Q2,Q3 and the pulldown transistor element Q4, generally in opposite conducting states for controlling the signal potential level at an output node V o , is known as a totem pole. A disadvantage of the totem pole presently incorporated in TTL circuits is that a temporary simultaneous conduction of the totem pole pullup and pulldown transistor elements occurs during transition from low to high level potential at the output V o . When the input signal V IN switches from high to low level potential as illustrated in Figure 2A, pulldown transistor Q4 starts to turn off. However the Darlington pullup transistor element Q2,Q3 starts conducting while pulldown transistor Q4 is still conducting in the active region. The simultaneous conduction in the totem pole temporarily creates a low impedance path to ground from the power supply before transistor Q4 turns off and before the output signal V o rises from low to high level potential as illustrated in Figure 2B. The result is an undesired sudden increase in the supply current or sourcing current I s from TTL power supply V cc as illustrated in Figure 2C. The supply current spiking in conventional TTL circuit totem pole configurations increases power dissipation and heat at the output and causes electromagnetic interference particularly when multiple TTL output devices are switching simultaneously. Another disadvantage of the conventional TTL totem pole circuit configuration, in the case of TTL output gates of the non-inverting type, is that the rising ground potential or "ground bounce" caused by supply current spikes for multiple outputs reduces the noise margin for the input signal. Uncontrolled switching of the output circuit may result. A circuit having the features set forth in the preamble of patent claim 1 is known from JP-A-61-118020. In this circuit, the anti-simultaneous transistor is connected with its collector node to the first stage transistor of the Darlington pair, and the ballast resistor network comprises a single resistor which connects the base nodes of the pulldown transistor and of the anti-simultaneous transistor. The anti-simultaneous transistor is an active discharge element which follows the conducting state of the pulldown transistor and thus helps to divert base drive current from the pullup transistor Darlington pair whenever the pulldown transistor element is conducting. According to the invention, and as set forth in the characterizing clause of patent claim 1, the collector node of the anti-simultaneous transistor is connected to the second stage transistor base node. A further buffer circuit is disclosed in JP-A-59-15330 and includes some of the features set forth in subclaims of the present invention, in particular, a phase splitter transistor. A feature of the present invention is that it is applicable in any TTL circuit that incorporates a totem pole configuration. Such a circuit is disclosed, e.g., by US-A-4,677,320 Thus the invention is applicable in TTL buffer circuits, TTL output gates and devices, TTL to ECL and ECL to TTL convertors, TTL circuits incorporating a totem pole with or without a phase splitter transistor, etc. The improved totem pole circuit configuration permits controlled switching from low to high potential at the output node at the maximum permissable slew-rate. By avoiding the sudden increases and spikes in supply current the invention reduces power dissipation, heat, electromagnetic interference, and ground bounce. The invention also improves the speed of the low to high transition at the TTL output. Other objects, features and advantages of the invention are apparent in the following specification and accompanying drawings. Figure 1 is a schematic circuit diagram of a prior art TTL inverting output gate. Figures 2A, 2B and 2C are diagrammatic graphs of the input signal V IN , the output signal V o and supply current I s versus time. Figure 3 is a schematic circuit diagram of a generalized TTL output gate incorporating the anti-simultaneous totem pole conduction circuit of the present invention. Figure 4 is a schematic circuit diagram of an ECL to TTL converter or translator incorporating the anti-simultaneous conduction circuit at the TTL totem pole. An inverting TTL output gate incorporating the anti-simultaneous totem pole conduction circuit of the present invention is illustrated in Figure 3. Components performing the same function as those illustrated in the TTL output gate of Figure 1 are identified by the same reference designation. In addition there is added the active discharge transistor or anti-simultaneous transistor Q5 with a collector coupled through diode D5 to the base of the Darlington pulldown transistor pair Q2,Q3. Diode D5 is oriented to block current flow back to the base of the Darlington transistor pair and sets the voltage at the emitter of Darlington transistor Q2 high enough to avoid continuous current drainage through transistor Q5. The emitter of active discharge transistor Q5 is coupled to ground or low potential for diverting and discharging current from the base of the pullup transistor element when the active discharge transistor Q5 is conducting. The base of the active discharge transistor Q5 is coupled through the buffer resistors R6 and R7 to the base of pulldown transistor Q4. As a result the active discharge transistor and anti-simultaneous transistor Q5 mirrors the conducting state of the pulldown transistor Q4. At the same time the values of the resistors R6 and R7 are selected to prevent or reduce current hogging between the transistors Q4 and Q5. Current hogging is the pre-emption of base drive current by one of a pair of transistors coupled in such a mirror configuration as the transistors seek to equalize emitter currents. When the input changes from high to low phase splitter transistor Q1 turns off. While active discharge transistor Q5 is still in the active conducting region it continues to maintain the base of the pullup transistor Q2 sufficiently low to avoid turn on of the pullup transistors. The anti-simultaneous transistor Q5 does not turn off until pulldown transistor Q4 turns off, only then releasing the base of the pullup transistors. The Darlington transistor pair Q2,Q3 then sources current to the output to pullup the output V o to the logic high level potential. Whenever the pulldown transistor Q4 tries to turn on for example because of Miller feedback current through its base-collector capacitance, the mirroring active discharge transistor Q5 also turns on, discharging the base of Q2 and turning off the Darlington transistor Q2. Simultaneous conduction of the totem pole is prevented and current spikes in the supply current are therefore avoided. The circuit also provides some improvement during low to high transition in the output also. The anti-simultaneous conduction circuit consisting of the active discharge transistor Q5, one-way diode D5, and ballast resistors R6 and R7 can be used in any type of TTL circuit incorporating a totem pole with or without a phase splitter for example as shown in the ECL to TTL translator 15 of Figure 4. The ECL to TTL translator consists of an ECL input gate 20 for receiving ECL voltage level logic input signals ECL V IN at the input transistor Q13 compatible with ECL circuits and a TTL output gate 22 for delivering corresponding TTL voltage level logic output signals at the output V o compatible with TTL circuits. The ECL input gate 20 includes a differential ECL pair of transistors, input transistor Q13 and reference transistor Q19 with a common emitter coupling connected to the ECL current source I ECL . The input and reference transistors Q13 and Q19 provide alternative transistor collector paths through load resistors R11 and R15 according to the ECL logic level voltage signal at the ECL input ECL V IN . Transistor Q19 controls the base of transistor Q11 which provides base drive to TTL output pulldown transistor Q4. Diode connected transistor Q15, diode D6, and diode connected transistor Q16 provide a voltage clamp, clamping the base of transistor Q11 when reference transistor Q19 is non-conducting and resistor R11 is pulling up the base of Q11. The voltage at the base of Q11 is clamped to a level so that the current through Q11 is limited. The ECL high and low level logic potential levels ECL V IN are established on either side of the reference potential V REF applied at the base of reference transistor Q19 so that either one or the other of the reference transistor Q19 or input transistor Q13 is conducting. The current source I ECL is connected to a low level voltage source V EE for example -5 volts +/- 0.5 volts so that the ECL logic voltage levels are in the negative voltage potential range. The TTL output 22 translates the negative potential logic level signals at the ECL input gate to corresponding high and low level voltage signals in the positive TTL voltage range compatible with TTL circuits. The elements of the TTL output gate 22 performing functions comparable to the totem pole components of the TTL output gate illustrated in Figure 3 are identified by the same reference designations. In particular the TTL output gate includes the totem pole consisting of the Darlington transistor pair pullup element Q2,Q3 and the pulldown transistor element Q4. Resistor R15 provides the base drive to the Darlington pullup element Q2,Q3. Diode D4 helps discharge the base of Darlington transistor Q3 during the low to high transition of the TTL output TTL V o . Diode D5 serves dual purposes in the ECL to TTL translator and in the anti-simultaneous conduction circuit. To the TTL output gate 22 is added the anti-simultaneous conduction circuit of the present invention comprising the anti-simultaneous active discharge transistor element Q5, one-way diode D5 already present in the ECL to TTL translator, and buffer resistors R6 and R7 performing the functions heretofore described with the same features and advantages. The anti-simultaneous conduction circuit reduces simultaneous conduction in the totem pole thereby substantially avoiding undesirable current spikes in the TTL supply current. While the invention has been described with reference to particular TTL circuits it is applicable to any TTL circuit incorporating a totem pole. For example the invention is applicable in other ECL to TTL translators such as described in U.S. Patent No. US-A-4,677,320 and TTL to ECL translators such as described in U.S. Patent No. US-A-4,654,549. Similarly the invention is applicable in all types of TTL buffer circuits and output circuits such as multiple phase splitter TTL output circuits and TTL tristate output circuits such as described in U.S. Patent No. US-A-4,661,727, U.S. Patent No. US-A-4,287,433 and U.S. Patent No. US-A-4,255,670; to TTL output circuits with so called "AC miller killers" such as described in U.S. Patent No. US-A-4,321,490 and U.S. Patent No. US-A-4,330,723; to TTL output devices and TTL tristate devices incorporating so called "DC miller killers" such as described in U.S. Patent No. US-A-4,311,927 and U.S. Patent No. US-A-4,581,550; to TTL circuits incorporating a totem pole with or without a phase splitter; and to any of a variety of other TTL circuits. The anti-simultaneous conduction circuit of the present invention is also applicable to the complementary metal oxide semiconductor (CMOS) family of logic circuits incorporating a CMOS totem pole with active pullup and pulldown transistor elements. The anti-simultaneous transistor element and related components of the present invention in CMOS are incorporated in the logic circuit as described.

Claims: A buffer circuit having an output node (V o ), a Darlington transistor pair (Q2, Q3) comprising first and second stage pullup transistors with an emitter node of the first stage pullup transistor (Q2) coupled to the base node of the second stage pullup transistor (Q3) for sourcing current from a high potential power rail (V cc ) to the output node, a pulldown transistor (Q4) coupled for sinking current from the output node to a low potential power rail (GND), an anti-simultaneous transistor (Q5) having a collector node coupled to a base node of said Darlington transistor pair, and an emitter node directly connected to said low potential power rail (GND), and a ballast resistor network (R6, R7) coupled between the base node of the anti-simultaneous transistor and the base node of the pulldown transistor, characterized in that said collector node of said anti-simultaneous transistor (Q5) is coupled to the base node of said second stage pullup transistor (Q3) and to the emitter node of said first stage pullup transistor (Q2) for sinking current from the base node of said second stage pullup transistor (Q3). The buffer circuit of claim 1 comprising a phase splitter transistor (Q1, Q11) having an emitter node coupled to drive a common node to which each of the base nodes of said pulldown transistor (Q4) and of said anti-simultaneous transistor (Q5) are coupled via a first ballast resistor (R7) and a second ballast resistor (R6), respectively, said first and second ballast resistors combining to form said ballast resistor network. The buffer circuit of claim 2 wherein the phase splitter transistor (Q1) comprises a collector node coupled to respective base nodes of the first stage pullup transistor (Q2) and second stage pullup transistor (Q3) of the Darlington transistor pair, said phase splitter transistor (Q1) controlling the conducting states of the pullup and pulldown transistors substantially in opposite phase. The buffer circuit of claim 2 wherein the phase splitter transistor (Q11) comprises a collector node coupled to the high potential power rail (V TTL ) without connection to the base nodes of the first and second stage pullup transistors of the Darlington transistor pair (Q2,Q3). The buffer circuit of claim 4 wherein the collector node of the anti-simultaneous transistor (Q5) is also coupled to the base node of the first stage pullup transistor (Q2). The buffer circuit of claim 5 wherein the collector node of the anti-simultaneous transistor (Q5) in coupled to the base node of the first stage pullup transistor (Q2) through a first diode (D5), and is coupled to the base node of the second stage pullup transistor (Q3) through a second diode (D4). The buffer circuit of claim 2 wherein the collector node of the anti-simultaneous transistor (Q5) is coupled to the emitter node of the first stage pullup transistor (Q2) and the base node of the second stage pullup transistor (Q3) through a diode (D5).

Inventors: ESTRADA, JULIO
Applicants: NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1989
Main classification: H03K19
IPC codes: H03K19, H03K17