Address modification circuit

Abstract: An n-bit address modifying instruction read from a program ROM (11) comprises a control bit part and an m-bit (m < n) operand part. Data used for address modi­ fication is stored in k (k ≦ m) extra bit positions of the control bit part. The data stored in the control bit part (12-1) is supplied to a control bit data detecting circuit (16). The detecting circuit is responsive to the control bit data in the control bit part (12-1) to produce first and second control signals (SA and SB). Detecting an address modifying instruction, the detect­ ing circuit (16) produces the first control signal (SA) so that a first data entry gate (13) is enabled. When the first data entry gate (13) is enabled, address modifying data stored in the operand part (12-2) included in the address modifying instruction is written into an m-bit address counter (14). When the detecting circuit (16) detects the address modifying instruction and that the number of bits of an address to be modified is "m + 1" bits or more, the second control signal (SB) enables a second data entry gate (17). As a result, part of data in the control bit part (12-1) is written into a k-bit address counter (18) as address modifying data. "m + k"-bit address modifying data is output from the m-bit address counter (14) and the k-bit address counter (18). The bits of the address output are sup­ plied to the program ROM (11) simultaneously.

Description: The present invention relates to an address modification circuit for modifying addresses of a program ROM (read-only memory) contained in an LSI (large-scale integrated circuit) of a computer system, such as a microcomputer system. In microcomputer systems, address modification circuits are used to modify addresses of a program ROM contained in an LSI and storing a control program and data for readout only. A prior art address modification circuit is arranged as shown in Fig. 1. Included in an n-bit instruction word read from a program ROM 11 is an address modifying instruction 12 to modify addresses of the ROM consists of a control bit part 12-1 and an m-bit (m < n) operand part 12-2. Control bit part 12-1 contains control bit data, while operand part 12-2 contains address modification data. In operand part 12-2, address modifying data for ROM 11 is described in a length of m bits. Data entry gate 13 is controlled by the control bit data in control bit part 12-1. When data entry gate 13 is enabled, the address modifying data in operand part 12-2 is loaded into counter 14 through gate 13. The parallel output bits (address output) of m-bit address counter 14 are applied to program ROM 11 as its address data. Such an address modification circuit as shown in Fig. 1, however, cannot modify addresses with more than m bits. That is, the number of bits of address data which can be modified is governed by the limited number of bits in operand part 12-2, making it impossible to prepare a program for address data whose number of bits is larger than that of the operand part. If operand part 12-2 were expanded up to the desired number m' of bits, the number of bits in an output instruction of program ROM 11 would have to be increased by "m' - m" bits. The number of signal lines of a data bus and the number of bits in an instruction register would thus have to be increased correspondingly, and the occupied area of the program ROM in the LSI would be increased. A Japanese laid-open patent publication No. 61-48174 discloses a data storage device in which stored contents of a program ROM are modified within a semiconductor memory so as to produce address modified data. The data storage device has a memory for address modifying data as well as a main memory. The data read out from the main memory is subjected to modification by the data read out from the modifying data memory. According to the data storage device disclosed in the patent publication, however, an extra modifying data memory is required, and the modifying data in the modifying data memory must be increased in number for intricate data modifications. This will disadvantageously increase the area of a semiconductor chip. It is accordingly an object of the present invention to provide an address modification circuit which is capable of modifying addresses which are larger in bit number than the operand part of an address modifying instruction without increasing the area of a semiconductor chip. To solve this object the present invention provides an address field modification circuit as specified in claim 1. The address field modification circuit of the present invention comprises especially a control bit data detecting circuit connected to receive data in a control bit part of an n-bit address modifying instruction having the control bit part and an m-bit (n > m) operand part for producing a first control signal when detecting that the control bit data in the control bit part is an instruction for address modification and a second control signal when detecting that the number of bits of an address to be modified is "m + 1" bits or more; a first m-bit address counter circuit responsive to the first control signal to be loaded with address modifying data stored in the operand part; and a second k-bit (k ≦ m) address counter circuit responsive to the second control signal to be loaded with part of data in the control bit part as address modifying data when the address modifying instruction is detected and that the number of bits of an address to be modified is "m + 1" bits or more is detected by the detecting circuit. With such an arrangement, since k extra bits in the control bit part are used as address modifying data, the modification of addresses of "k + m" bits in excess of m bits is made possible without expansion of the number of bits in the operand part. In this case, since the address modification is performed in one step of a program, the operating speed will not be lowered. It is also possible to keep the bit length of the operand part as it was. Address modified data can be supplied to the program ROM storing instructions without particular provision of a modifying data memory. Accordingly, there is provided an address modification circuit which can modify addresses which are larger in bit number than the operand parts of address modifying instructions without leading to an increase in the area of a semiconductor chip. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a prior art address modification circuit; Fig. 2 is a block diagram of an address modification circuit embodying the present invention; Fig. 3 is a block diagram of a portion of a microcomputer in which the address modification circuit of Fig. 2 is contained; Figs. 4A through 4C show practical arrangements of the control bit data detecting circuit of Figs. 2 and 3; and Fig. 5 shows a practical arrangement of the data entry gate of Figs. 2 and 3. Referring now to Fig. 2, an address modification circuit embodying the invention comprises a control bit data detecting circuit 16, a first data entry gate 13, an m-bit address counter 14, a second data entry gate 17 and a k-bit (k ≦ m) address counter 18. In an n-bit instruction word read from program ROM 11, an address modifying instruction 12 intended to modify the addresses of program ROM 11 is comprised of a control bit part 12-1 and an m-bit (m < n) operand part 12-2. Control bit part 12-1 contains control bit data, and data used for address modification, while operand part 12-2 contains address modifying data. In control bit part 12-1, control bit data is described in j-bit length. In extra bit positions, for example, k low-order bit positions (into which 0s are usually written) of control bit part 12-1, data used for modifying ROM addresses is described in k-bit length. In operand part 12-2, data for modifying the ROM addresses is described in m bit length. Since control bit part 12-1 is "n - m" bits in length, n - m = j + k. Control bit data detecting circuit 16 is supplied with the control bit data of n-m bits contained in the n-bit address modifying instruction read from program ROM 11 so as to produce first and second control signals SA and SB and output the k-bit data used for address modification. Detecting circuit 16 has a function to decide whether the control bit data in control bit part 12-1 is an address modifying instruction or not and whether the range for address modification is "m + 1" bits or more or not. The m-bit address modifying data contained in the address modifying instruction is written into address counter 14. Data entry gate 13 is controlled by first control signal SA from detecting circuit 16. When detecting circuit 16 detects an address modifying instruction, gate 13 is enabled to transmit the address modifying data contained in operand part 12-2 of the address modifying instruction to m-bit address counter 14. On the other hand, data entry gate 17 is controlled by second control signal SB from detecting circuit 16. When detecting circuit 16 detects that an instruction read from ROM 11 is an address modifying instruction, and address modifying data is "m + 1" bits or more in length, data entry gate 17 is enabled to transmit the k-bit data contained in control bit part 12-1 and used for address modification to k-bit address counter 18. In operation, an n-bit instruction is read from program ROM 11 first. The control bit data in the n-bit instruction is applied to control bit data detecting circuit 16. Detecting circuit 16 decodes which type of instruction is specified by the n-bit instruction. That is, by detecting circuit 16 decisions are made as to whether the n-bit instruction is an instruction for address modification or not and whether the bit range for address modification is "m + 1" bits or more or not. If detecting circuit 16 decides that the n-bit instruction is for address modification and the address modification range is below "m + 1" bits, then data entry gate 13 is enabled so that the address modifying data in operand part 12-2 is written into address counter 14 through data entry gate 13. The address which has been written into address counter 14 is transmitted to program ROM 11 as address modifying data. On the other hand, when it is decided that the n-bit instruction is an instruction for address modification and the address modification range is "m + 1" bits or more, data entry gates 13 and 17 are enabled by control signals SA and SB, respectively. As a result, the address modifying data in operand part 12-2 is written into address counter 14 through data entry gate 13. At the same time, the k low-order bits in control bit part 12-1 are written into address counter 18 through data entry gate 17 as address modifying data. The "k + m"-bit data written into address counters 14 and 18 is transmitted to program ROM 11 as address modified data. According to the address modification circuit described above, since the k extra bits in control bit part 12-1 can be used as address modifying data, address modification exceeding "k + m" bits is made possible without expanding the bit length of operand part 12-2. In the present case, since an address modification can be performed in one step of a program, the operation speed can be prevented from lowering and the bit length of the operand part of an instruction may be kept unchanged. Furthermore, address modified data can be supplied to program ROM 11 storing instructions without particular provision of a memory for modifying data. Therefore, addresses which are greater in bit length than the operand part of address modifying instructions can be modified without leading to an increase in the area of a semiconductor chip used. If address modification circuit 15 and program ROM 11 are integrated together into a semiconductor chip on a large scale, an LSI having a high performance program control function will be realized without expansion of the occupied area of the ROM and lowering the limit of LSI operating speed. Fig. 3 schematically shows an arrangement of a portion of an LSI, such as a microcomputer, which contains a program ROM and has a program control function. An ALU (arithmetic logic unit) 19 has first and second inputs connected to an internal bus 20. An accumulator 21 has an input connected to the output of ALU 19 and an output connected to internal bus 20. A data buffer 22 has an input connected to internal bus 20 and an output connected to an external output pin. A RAM (random access memory) 23 is connected to internal bus 20. Addresses and data are written into and read from RAM 23. Registers 24-1 and 24-2 have inputs connected to internal bus 20 and outputs connected to inputs of an address buffer 25. The output of address buffer 25 is connected to an external output pin. Of n-bit output lines of program ROM 11, m-bit lines (corresponding to the operand part) are connected to internal bus 20 and "n - m"-bit lines (corresponding to the control bit part) are connected to input lines of control bit detecting circuit 16. Data entry gate 13 is connected between internal bus 20 and m-bit address counter 14. Connected between the control input of data entry gate 13 and one of the control signal outputs of detecting circuit 16 is a signal line 26-1 for transferring control signal SA from detecting circuit 16 to data entry gate 13. Data entry gate 17 is connected between k-bit output lines of detecting circuit 16 and input lines of k-bit address counter 18. Connected between the control input of data entry gate 17 and the other control signal output of detecting circuit 16 is a signal line 26-2 for transferring control signal SB from detecting circuit 16 to data entry gate 17. Address input lines of program ROM 11 are connected to output lines of address counters 14 and 18. With such an arrangement as described above, various devices connected inside and outside the microcomputer are subjected to control on the basis of data stored in program ROM 11. The modification of addresses of ROM 11 is performed in substantially the same manner as in the circuit of Fig. 2. The arrangement of Fig. 3 only differs from that of Fig. 2 in that data in the operand part of an instruction read from program ROM 11 is applied to data entry gate 13 via internal bus 20. It will thus be understood that the arrangement of Fig. 3 is the same as that of Fig. 2 in operation and advantage. Figs. 4A through 4c show practical arrangements of control bit detecting circuit shown in Figs. 2 and 3. In the arrangement of Fig. 4A, control bit detecting circuit 16 is formed of a decoder (mask ROM). The decoder is arranged to decide whether the control bits (j high-order bits) of the control bit part specify an instruction for address modification or not and whether the range for address modification is "m + 1" bits or more or not in order to produce control signals SA and SB. The decoder has parallel input lines 28 to which control bits and complemented control bits obtained through inverters 27 are applied. Output signal lines 29 are formed to intersect input signal lines 28. The end of each of signal lines 29 is connected to a power supply V. Transistors Tr are formed at selected intersections of input signal lines 28 and output signal lines 29. Each of transistors Tr is connected to receive at its gate a control bit or a complemented control bit. When all the transistors in the same row (connected to the same output signal line) are turned on, a "H" level voltage of power supply V is transmitted over the conducting transistors so that control signal SA or SB goes to a "H" level. As a result, data entry gate 13 or 17 is enabled. The k low-order bits used for address modification is supplied to data entry gate 17 via the decoder. Detecting circuit 16 shown in Fig. 4B is adapted to produce control signals SC and SD for controlling peripheral circuits not shown in addition to control signals SA and SB. Detecting circuit 16 is comprised of a first decoder (mask ROM) 16A adapted to produce control signals SA and SB and a second decoder (mask ROM) 16B adapted to produce control signals SC and SD. First decoder 16A is the same as the circuit shown in Fig. 4A. Control signals SC and SD are produced by decoding the j-bit control data and the k-bit data. The k-bit data used for address modification is supplied to data entry gate 17 via second decoder 16B. In the circuits shown in Figs. 4A and 4B, the k low-order bits of control bit part 12-1 are directly used for address modification. However, the circuit shown in Fig. 4C is adapted to decode the "j + K"-bit data to produce the k-bit address modifying data. More specifically, detecting circuit 16 is comprised of first decoder (mask ROM) 16A for producing control signals SA and SB, second decoder (mask ROM) 16B for producing control signals SC and SD and third decoder (mask ROM) 16C for producing address modifying data. Control signals SA, SB, SC and SD are produced in the same manner as in the circuit shown in Fig. 4B. The k-bit address modifying data is produced by decoding the j control bits and the k bits in third decoder 16C. The resulting address modifying data is supplied to address counter 18 via data entry gate 17. In the circuit of Fig. 4C, decoder 16B adapted to produce control signals SC and SD for controlling peripheral circuits may be omitted. Each of the output signal lines has its one end connected to power supply V to obtain a decode output. Alternatively, each output signal line may have the end connected to ground and the other end connected to the power supply via a load, in which case control signal SA or SB goes to a "L" level when all transistors having their current paths serially connected in the same out signal line are turned on. When at least one transistor is in the off state, the control signal remains at a "H" level. Moreover, in the circuit of Fig. 4C, third decoder 16C decodes the j-bit control data and the k-bit data used for address modification. Alternatively, only data used for address modification may be decoded. The data need not be k bits in length so long as k output bits are obtained. Fig. 5 shows a practical arrangement of data entry gate 13 or 17 in the circuits of Figs. 2 and 3. Data entry gate 13 comprises m NAND gates 30. Each of first inputs of NAND gates 30 is connected to receive a corresponding bit of address modifying data in m-bit operand part 12-2 read from ROM 11. Second inputs of NAND gates 30 are connected to receive control signal SA in common. Hence, the data entry gate performs an inverting operation when control signal SA is at a "H" level. When control signal SA is at a "L" level, each of NAND gates 30 provides a "H" level output, irrespective of the level of a corresponding input bit. Similarly, data entry gate 17 comprises k NAND gates 30. In this case, each of first inputs of NAND gates 30 is connected to receive a corresponding bit of k-bit address modifying data output from control bit data detecting circuit 16. Second inputs of NAND gates 30 are connected to receive control signal SB in common. As described above, according to the present invention, there is provided an address modification circuit which can modify addresses which are larger in bit number than the operand parts of address modifying instructions without leading to an increase in the area of a semiconductor chip.

Claims: An address field modification circuit for modifying the length of the address section of fixed length instructions read out of a semiconductor memory device characterised by detecting means (16) connected to receive data in a control bit part (12-1) of an n-bit address modifying instruction (12) having the control bit part (12-1) and an m-bit (n > m) operand part (12-2) for producing a first control signal (SA) when detecting that the control bit data in the control bit part is an instruction for address modification and a second control signal (SB) when detecting that the number of bits of an address to be modified is "m + 1" bits or more; first m-bit address counter means (13, 14) responsive to the first control signal (SA) to be loaded with address modifying data stored in the operand part (12-2); and second k-bit (k ≦ m) address counter means (17, 18) responsive to the second control signal (SB) to be loaded with part of data in the control bit part (12-1) as address modifying data when the address modifying instruction is detected and when the bit length of the address modifying instruction is "m + 1" bits or more is detected by said detecting means, whereby an "m + k"-bit address output is obtained from said first and second address counter means (13, 14). The address modification circuit according to claim 1, characterized in that the address modifying instruction (12) is read from a program ROM (11). The address modification circuit according to claim 1, characterized in that said detecting means (16) includes decoder means for decoding the control bit data in said control bit part (12-1). The address modification circuit according to claim 3, characterized in that said decoder means includes a mask ROM. The address modification circuit according to claim 1, characterized in that said detecting means (16) includes decoder means for decoding the control bit data in said control bit part (12-1) and transfer means for transferring data contained in said control bit part and used for address modification to said second address counter means (17, 18). The address modification circuit according to claim 5, characterized in that said decoder means includes a mask ROM. The address modification circuit according to claim 1, characterized in that said detecting means (16) includes first decoder means (16A) for decoding the control bit data in said control bit part and second decoder means (16C) for decoding data used for address modification and contained in said control bit part (12-1) and supplying decoded outputs to said second address counter means (17, 18). The address modification circuit according to claim 7, characterized in that each of said first and second decoder means (16A, 16C) includes a mask ROM. The address modification circuit according to claim 1 or 2, characterized in that said first address counter means (13, 14) comprises an m-bit address counter (14) and a data entry gate (13) responsive to the first control signal (SA) from said detecting means (16) for supplying address modifying data in said operand part (12-2) to said m-bit address counter (14). The address modification circuit according to any one of claims 1, 2 and 9 characterized in that said second address counter means (17, 18) comprises an k-bit address counter (18) and a data entry gate (17) responsive to the second control signal (SB) from said detecting means (16) for supplying part of data in said control bit part (12-1) to said k-bit address counter (18) as address modifying data.

Inventors: KASHIMA MASAHIKO, KASHIMA, MASAHIKO, KASHIMA, MASAHIKO C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G06F9
IPC codes: G06F9, G06F12