Method and apparatus for synchronising clock signals

Abstract: Apparatus for synchronising a clock signal to a pulse comprises a clock signal generator (1) for generating a first clock signal having a frequency equal to that of a desired clock signal. A delay circuit (2) to which the first clock signal is fed generates a number of time delayed versions of the first clock signal, each time delay being less than the period of the first clock signals. Logic (9) compares the time delayed versions of the first clock signal and the original clock signal at the time of occurrence of the pulse and selects as the desired clock signal, a version of the first clock signal which has changed state close to the time of occurrence of the pulse.

Description: The invention relates to an apparatus for synchronising a clock signal to a pulse. There is a common requirement to generate a clock signal which is synchronised to a pulse, particularly a regular pulse stream. In the past, this has been achieved by feeding a high frequency clock signal to a counter, such as a divide-by-four counter which outputs a final clock signal at a lower frequency. The pulse is sent as a reset pulse to the counter so that on each occurrence of the reset pulse, the counter is reset and the output clock signal is then synchronised to the reset pulse. This approach has two disadvantages. Firstly, it only allows the output clock signal to be synchronised within the accuracy of the ratio of the input and output clock signals (1/4 in the case of the divide-by-four counter mentioned above), and secondly it requires the initial clock frequency to be a multiple of the actual output clock frequency required. This latter requirement is a problem because it is generally necessary to provide a circuit to multiply an original clock frequency to generate the high frequency version and this circuit is liable to introduce phase jitter as the multiplication factor is increased. This is a particular problem at high clock speeds where the ratio of the input and output clock speeds is high to produce greater accuracy. Patent document DE A 2 360 450 discloses a method of synchronising three clocks by means of a 2 out of 3 majority logic circuit. Patent document US A 4 316 148 discloses a method of synchronising a clock to the microinstruction cycle of a CPU. Patent document US A 3 577 128 discloses a method of synchronising a slave clock to a master clock. US A 4 600 895 describes a circuit for synchronising a clock to a reference signal. In accordance with the present invention, apparatus for synchronising a clock signal to a pulse comprises a clock signal generator for generating a first clock signal having a frequency equal to that of a desired clock signal; delay means to which the first clock signal is fed for generating a number of time delayed versions of the first clock signal, each time delay being less than the period of the first clock signal; and comparison and selection means for comparing the logical states of the time delayed versions and the original version of the first clock signal at the time of occurrence of the pulse, in order to identify the two versions of the first clock signal which change state adjacent to the time of occurrence of the pulse and for selecting, as the desired clock signal, one of the two identified versions. Such an apparatus is disclosed in US 4600895. The present invention is characterised by the delay means further comprising a shift register having a serial input port connected to the clock signal generator and having a number of parallel output ports for providing the time delayed versions; and by frequency multiplier means, receiving the first clock signal, for generating a second clock signal having a frequency higher than the first clock signal, the second clock signal controlling the shift rate of the shift register, wherein each of the parallel output ports of the shift register is connected to the comparison means to provide the time delayed versions of the first clock signal. In contrast to the previous methods of clock signal synchronisation, this invention enables a lower frequency clock generator to be used thus reducing the problems of phase jitter mentioned above. In addition, a higher degree of accuracy can be achieved by selecting a delay element with a shorter time delay provided there are sufficient delay elements so that the total delay through all of the elements is at least one clock period. Each time delay typically has the same duration (although this is not essential) and is less than a fraction of the period of the first clock signal where the fraction is equal to or less than the accuracy with which it is desired to synchronise the clock signal to the pulse. Typically, the comparison and selection means comprises a latch to which each time delayed version of the first clock signal is fed; a multiplexer to which each time delayed version of the first clock signal is fed; and logic means, the latch being responsive to the pulse to enable the logic means to compare the contents of the latch at the time of the pulse and to select the time delayed version of the first clock signal which changes state closest to the pulse, the logic means controlling the multiplexer to output the selected version of the first clock signal. One important application of the invention is in the field of raster image output scanning in which the position of the recording beam on a record medium needs to be accurately controlled. In this case, each clock pulse will typically correspond to a single image pixel. An example of apparatus according to the invention will now be described and contrasted with a known synchronisation system with reference to the accompanying drawings, in which:- Figure 1 is a block diagram of an example of a known synchronisation system; Figure 2 is a pulse diagram illustrating operation of the system shown in Figure 1; and, Figure 3 is a block diagram of an example of the apparatus according to the invention. The apparatus shown in Figure 1 comprises a clock generator 1 for generating a first clock signal having a fixed frequency as shown in Figure 2A. This clock signal is fed to a tapped delay line 2 which may be provided by a Newport Microtex 50450. Alternatively, a series of integrated circuit logic elements could be used as delay components. In this simple example, nine different time delays are imparted to the original clock signal, each time delay being greater than 1/10 of the clock period. The original clock signal together with each time delayed version is fed along a respective output line to a latch 3. The first two delayed versions of the clock signal are illustrated in Figures 2B and 2C respectively and the signals shown in Figures 2A - 2C are fed to the latch 3 via lines 4 - 6 respectively. In addition, the original clock signal and the time delayed versions are fed in parallel to multiplexer 7. In practice, the clock frequency could be in the order of 20MHz, and a large number of time delayed versions will be generated with each time delay being 5 nanoseconds. The latch 3 is actuated by a synchronisation pulse fed to the latch along a line 8. This synchronisation pulse may be generated in a variety of ways but in the case of image scanning apparatus which makes use of a rotating drum, may be generated by sensing each complete rotation of the drum in a conventional manner. The synchronisation pulse is illustrated in Figure 2D. Upon the receipt of the synchronisation pulse, the latch 3 latches the current states of each of the signals fed to it from the tapped delay line 2 as a series of 1 or 0 values. For example, if the pulse occurs at the point shown in Figure 2D, the first two locations in the latch 3 will contain binary 1 while the remainder will contain binary 0. The contents of the latch 3 are fed to a logic circuit 9 which determines where there is a transition in the binary values being latched from binary 1 to binary 0. The logic circuit 9 selects one of the versions of the clock signal on each side of the transition. The logic circuit 9 cannot determine which version of the clock signal adjacent to the transition is closest to the pulse in time but the circuit 9 will be pre-programmed to select either the version corresponding to the location of the latch with binary 1 or that corresponding to the location in the latch with binary 0. The decision made by the logic circuit 9 is conveyed to the multiplexer 7 by one of the set of 10 output lines, with the output line corresponding to the selected version of the delayed clock signal carrying a binary 1 signal while the remainder carry binary 0 signals. The multiplexer 7 responds to the single line carrying a binary 1 to switch the appropriate version of the clock signal from one of the input lines to the output line 10 so as to constitute the final output clock signal. At each occurrence of the synchronisation pulse, new information will be latched into the latch 3 and the process will be repeated. Figure 3 illustrates apparatus according to the invention. This takes the form of a modification of the apparatus shown in Figure 1. The tapped delay line 2 is replaced by a shift register 11 having a serial data input which is coupled with the clock generator 1. The shift register 11 is clocked by a clock signal derived from a xN frequency multiplier 12 to which the clock signal from the clock generator 1 is also fed. In one example, N = 10. The shift register 11 is of a conventional form so that if it is clocked at a frequency of 10 times the original clock frequency, it will contain within it a set of five binary "0" and five binary "1" corresponding to a single clock period. Thus, on the parallel output ports of the shift register 11 which are connected in parallel to the latch 3 different time delayed versions of the original clock signal will appear. The operation of the remainder of the apparatus shown in Figure 3 is exactly as in the Figure 1 example. We will now consider briefly the advantage of the Figure 3 example over a conventional arrangement. Consider a typical clock rate of 20Mhz with a requirement to synchronise the clock to the pulse within 1/10th of the clock period. In order to do this conventionally it would require a frequency multiplier which would multiply the 20 Mhz clock to 200Mhz and subsequently use a divide by 10 counter in order to synchronise the pulse within 1/10th. If the frequency were to jitter at the output of the frequency multiplier by say 1% (this is much more than might be expected in practice) then at times the clock may be 1% fast ie. a frequency of 201 Mhz and at other times a frequency of 1% slow ie. 199 Mhz. Having divided the clock by a factor of 10 in the synchronising divider there would still be an error of 1% on the rate at which the pixels were laid down onto the film medium (assuming that the device was being used in a scanning application) and this would lead to severe dislocation of the raster pattern making the resultant image unusable. However, consider now the case of the pulse synchroniser, where the delay is provided by the shift register 11 with the input signal being the original clock signal ie. 20Mhz and the shift signal being the original clock multiplied by 10 with a 1% jitter on it as before. We now see that the clock read out speed remains correct, however, the phasing of the start of each clock pulse may vary by 1% of its correct position. As the aim is to synchronise the clock to the pulse to within 10% of the clock period the result of the 1% jitter on the 200Mhz would be that the time delay equivalent given by the shift register could vary by 1% from their nominal positions of 10% of the 20Mhz period, that is the precise positions of each time delayed version of the 20Mhz clock pulse could vary by .1% of the period of the 20Mhz clock and thus even though the frequency multiplier still introduces 1% jitter the dislocation of pixel position is now substantially reduced. In the case where the clock frequency of 20Mhz after leaving the synchronising divider has a 1% jitter on it then the position of the trailing pixel of a 600 mm long line could be displaced by up to 6mm from its neighbouring line (the pulse synchronisation only ensures that adjacent lines start next to one another. The finishing position is dependent on the clock and the linear position of the spot over the recording material). However in the case where the new method of pulse synchronisation is used each stage of the shift register by virtue of having a 200Mhz nominal clock would introduce a delay of approximately 5 nano seconds with a tolerance of 50 pico seconds. Therefore assuming that the 20Mhz clock signal is absolutely stable and the writing speed constant the last pixel of each line using the new synchronisation circuit would be laid down in the correct position but with a position error of 10% ± 0.1% (due to the jitter) of its correct position. The last pixel in each line would then differ in position from its neighbour not by 6mm but typically by 15 microns or so which is truly negligible and very probably unmeasurable. Thus in this instance phase jitter in the 200Mhz oscillator has been reduced from an intolerable to an insignificant problem. Finally, it should be noted that provided the total delay through the delay element (shift register 11) is greater than the period of the clock signal, this circuit can be used to phase synchronise clocks of varying periods.

Claims: Apparatus for synchronising a clock signal to a pulse, the apparatus comprising a clock signal generator (1) for generating a first clock signal having a frequency equal to that of a desired clock signal; delay means to which the first clock signal is fed for generating a number of time delayed versions of the first clock signal, each time delay being less than the period of the first clock signal; and comparison and selection means (3,9,10) for comparing (3,9) the logical states of the time delayed versions and the original version of the first clock signal at the time of occurrence of the pulse, in order to identify the two versions of the first clock signal which change state adjacent to the time of occurrence of the pulse and for selecting (9,10), as the desired clock signal, one of the two identified versions; and characterised by said delay means further comprising a shift register (11) having a serial input port connected to the clock signal generator and having a number of parallel output ports for providing said time delayed versions; and by frequency multiplier means (12), receiving the first clock signal, for generating a second clock signal having a frequency higher than the first clock signal, the second clock signal controlling the shift rate of the shift register (11), wherein each of the parallel output ports of the shift register is connected to the comparison means (3,9) to provide the time delayed versions of the first clock signal. Apparatus according to claim 1, wherein the comparison and selection means comprises a latch (3) to which each time delayed version of the first clock signal is fed; a multiplexer (7) to which each time delayed version of the first clock signal is fed; and logic means (9), the latch (3) being responsive to the pulse to enable the logic means (9) to compare the contents of the latch at the time of the pulse and to select the time delayed version of the first clock signal which changes state closest to the pulse, the logic means controlling the multiplexer (7) to output the selected version of the first clock signal.

Inventors: DUDLEY NEIL FRANK, DUDLEY, NEIL FRANK
Applicants: CROSFIELD ELECTRONICS LTD, CROSFIELD ELECTRONICS LIMITED
Application year: 1989
Main classification: G06F1
IPC codes: H04L7, H03K5, H03L7, G06F1