Liquid crystal display device

Abstract: A liquid crystal display device for image display realizing clear and optimum image display by comprising a brightness detector for detecting brightness of image signal after digital conversion and a voltage dividing circuit for outputting the reference voltage in the level depending on the detected value in view of adjusting contrast of display screen by judging brightness of image signal and controlling the reference voltage.

Description: Field of the Invention The present invention relates to an improvement of a liquid crystal display device for displaying images of improved contrast ratio. Description of the Prior Art DE-A-35 18 433 is concerned with adapative scaling of contrast and discloses a LCD color display device having a color demodulator, parallel A/D converters for each color signal, processing means, brightness detectors, voltage dividing circuits within the brightness detectors for inputting reference voltages of a level depending on the detected values of the brightness detectors to the A/D converters, and capacitors for obtaining voltages corresponding to reference voltages. From EP-A-0 261 901, a display device is known which also comprises a brightness detector which uses a first A/D converter. From the outputs of this first A/D converter a level control signal is derived which is provided as reference voltage to a second A/D converter in order to obtain an adaptive scaling effect for the grey scales of a LCD display. Fig. 1 is a block connection diagram indicating a further conventional liquid crystal display device disclosed in JP-A-62-188477. In this figure, a reference numeral 1 designates an analog switch; 2, an autolevel control circuit; 3, an analog/digital converter (hereinafter referred to as A/D converter); 4, a multiplexer working as a signal processing circuit for supplying separated signals of red, green and blue to a drive circuit for image display. Operations will be explained. In Fig. 1, a video signal input from an input system not illustrated is separated to three primary-color signals of red, green and blue (hereinafter referred respectively as R, G, B) by a color demodulation circuit (not illustrated), these separated analog primary-color signals are time-multiplexed by an analog switch 1 and these are supplied to an autolevel control circuit 2 as an S-RGB signal. The autolevel control circuit 2 clamps the S-RGB signal to the lower limit reference voltage Vr-- of the A/D converter 3 and generates an upper limit reference voltage Vr++. Next, a multiplexer as a signal processing circuit separates again the output of the A/D converter into the three primary-color signals of R, G, B. Though depending on resolution of the A/D converter 3, a dynamic drive type liquid crystal display device cannot obtain sufficient contrast ratio generally, and therefore it has been in such a tendency to generate a saturated white or black display. Considering such tendency, it is naturally possible to detect the maximum value of the image signal and use such value as the upper limit reference voltage of the A/D converter 3 in order to improve such tendency. However, the three primary-color signals must be time-multiplexed to the one signal by the analog switch 1. As a result, the prior art has been accompanied by a problem that the analog switch cannot follow the high speed operation in case the resolution of liquid crystal display screen, namely the number of pixels, particularly the number of pixels in the horizontal direction, increases. Summary of the Invention An object of the invention is to provide a circuit for an improved adapative scaling of grey scales in a color LCD display by using a color demodulator and parallel A/D conversion without multiplexing of the digitized color signals. In view of attaining the above object, according to the present invention, there is provided a liquid crystal display device comprising a color demodulator for demodulating an input color image signal to three primary-color signals, three analog/digital converters working in parallel, one for each color, for quantizing the primary-color signals demodulated by said color demodulator to digital signals, wherein each converter has a separate output with a set of digital output lines including one line for a most significant bit, a brightness detector for detecting brightness of the image signal, and a voltage dividing circuit for inputting a reference voltage of a level depending on the detected values of said brightness detector to said converters, characterized by a triple input OR gate, each input of which is associated with a different one of the converters and is connected to the most significant bit output of the associated converter and the output of which gate is connected to the brightness information input of said brightness detector, a means for holding the output voltage level of said brightness detector for a specified period; and a triple output voltage dividing circuit being said voltage dividing circuit which is controlled by the output voltage level of said voltage holding means and supplies an individual reference voltage to the reference voltage input of each converter, wherein the control of the reference voltages of the converters is such that if an image is dark, the contrast of the image is adjusted automatically to prevent a saturated black image on the display screen. Accordingly, the brightness detector detects the most significant bit of the output of the A/D converter, judges brightness or darkness of the image signal based on such detected signal and thereby automatically adjusts contrast of the display screen. Further advantages and embodiments are defined in the subclaims. The aforementioned and other objects and a novel feature of the present invention will become apparent by thorough understanding of following detailed explanation with reference to the accompanying drawings. However, the drawings are accompanied only for the convenience of explanation and do not specify the scope of the present invention. Brief Description of the Drawings Fig. 1 is a block connection diagram indicating a liquid crystal display device in the prior art. Fig. 2 is a block connection diagram indicating the liquid crystal display device as an embodiment of the present invention. Detailed Description of the Preferred Embodiments An embodiment of the present invention will be explained with reference to the accompanying drawings. In Fig. 2, 3a, 3b, 3c designate A/D converters; 5, a color demodulator; 6, a signal processing circuit; 11, a brightness detector consisting of a resistor R1 and a transistor Q1 to detect brightness of image signal; 12, an integrator consisting of resistors R2, R3, a capacitor C1, a diode D1 and a variable resistor VR1; 13, a discharge circuit by a blanking pulse PB consisting of resistors R6, R7 and a transistor Q3; 14, a voltage dividing circuit consisting of resistors R4, R5 and a transistor Q2; R8, R9, R10, voltage dividing resistors; VR2, VR3, VR4, voltage dividing variable resistors; A1, A2, A3, reference voltage output amplifiers; 15, OR gate for logical OR of the most significant bits of the A/D converters 3a, 3b, 3c; D2, D3, D4, reverse current shut-off diodes. Operations will be explained below. An image signal input to the input terminal P is first separated to three primary-color signals of R, G, B in the color demodulator and the primary-color signals are then supplied to the A/D converters 3a, 3b, 3c. These A/D converters 3a, 3b, 3c convert the R, G, B signals to quantized digital signals. The most significant bits of these digital signals, R, G, B are calculated on logical OR in the OR gate 15 and then the output signal of the OR gate 15 is input to the brightness detector 11 for detection of brightness of image signal. For example, in the case of a dark image signal, the most significant bits of digital outputs of the A/D converters 3a, 3b, 3c are all set to low level. Therefore, the transistor Q1 turns OFF. In this case, a capacitor C1 of integrator 12 is charged with the voltage set by the variable resistor VR1 and then a base voltage of transistor Q2 is held to this voltage during the one field period of the vertical blanking pulse PB. As a result, the transistor Q2 turns ON and a voltage determined by the variable resistor VR2, and resistors R4, R5, R8 is supplied to the A/D converter 3a as the reference voltage for example. The similar operations are carried out for the A/D converters 3b, 3c. In this case, the resolutions of the A/D converters 3a, 3b, 3c virtually increase because the reference voltages become lower. On the other hand, in the case of a bright image signal, the output of OR gate 15 becomes high level, the transistor Q1 turns ON and the capacitor C1 is not charged. Accordingly, the transistor Q2 turns OFF and a voltage determined by the variable resistor VR2 and voltage dividing resistor R8 is applied to the A/D converter 3a as the reference voltage input, for example. The reference voltages of the A/D converters 3a - 3c can take two kinds of values depending on the quality of image signal input, namely the brightness of the image signal. If the image is dark, the virtual contrast can be raised by setting such two kinds of voltage values to the optimum value and a high quality image can be obtained by preventing the saturated black image of display screen. In this embodiment, the A/D converters 3a - 3c of 4 bits are used but the converters are not limited only to them. As explained previously, the present invention has the constitution that the reference voltage of the A/D converter is controlled with the most significant bit output signal of the A/D converter and therefore provides the effect that if an image is dark, the contrast can be adjusted automatically depending on the level of image signal, and thereby saturated black image on the display screen can be prevented and clear and optimum display image can be obtained.

Claims: A liquid crystal display device comprising a color demodulator (5) for demodulating an input color image signal (P) to three primary-color signals (R, G, B); three analog/digital converters (3a - c) working in parallel, one for each color, for quantizing the primary-color signals (R, G, B) demodulated by said color demodulator (5) to digital signals (R, G, B), wherein each converter (3a, 3b, 3c) has a separate output with a set of digital output lines (D0 - D4) including one line (D4) for a most significant bit; a brightness detector (11) for detecting brightness of the image signal; and a voltage dividing circuit for inputting a reference voltage of a level depending on the detected values of said brightness detector (11) to said converters (3a - c); characterized by a triple input OR gate (15), each input of which is associated with a different one of the converters (3a - c) and is connected to the most significant bit output (D4) of the associated converter (3a-c) and the output of which gate is connected to the brightness information input of said brightness detector (11), a means (12) for holding the output voltage level of said brightness detector (11) for a specified period; and a triple output voltage dividing circuit (14, D2-D4, R8-R10, VR2-VR4, A1-A3) being said voltage dividing circuit which is controlled by the output voltage level of said voltage holding means (12) and supplies an individual reference voltage to the reference voltage input (REF) of each converter (3a-c), wherein the control of the reference voltages of the converters (3a-c) is such that if an image is dark, the contrast of the image is adjusted automatically to prevent a saturated black image on the display screen. A device according to claim 1, characterized in that the control of the reference voltages is such that, if all most significant bits (D4) of said converters (3a - c) are indicating a dark signal level, the reference voltages to said converters (3a - c) are automatically scaled such that an optimum contrast is obtained on a display screen, otherwise the reference voltages remain at fixed, predetermined levels. A device according to claim 1 or 2, characterized in that said voltage holding means (12) is an integrator including a capacitor (C1) which holds the output voltage level of said brightness detector (11), and that a discharging circuit (13) is provided for discharging said capacitor (C1) after said specified period. A device according to claim 3, characterized in that said discharging circuit (13) is operated by a periodic blanking pulse (PB).

Inventors: FUKUMARA KENICHIRO C O MITSUBI, YOSHIOKA KAZUO C O MITSUBISHI, FUKUMARA, KENICHIRO C/O MITSUBISHI DENKI K.K., YOSHIOKA,KAZUO C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1989
Main classification: G09G3
IPC codes: G02F1, H04N3, G09G3, H04N9