Error location system

Abstract: The invention is an error correcting system which calculates the error locations, that is, finds the roots of the error locator equation: 1 + δ₁*x + δ₂*x² + δ₃x³ + ... + δ v-1 *x v-1 + δ v *x v = 0 (1) where "+" and "*" represent Galois Field addition and Galois Field multiplication, respectively, and "v" is the number of errors in the data by substituting the error location equation coefficients into a succession of v error location formulas along with successive values of x to determine if the various x's are roots of equation (1). When the first root is found, extraction of the root corresponds to reducing the degree of equation (1) by one, to (v-1), and also to reducing the number of error location formulas by one to (v-1). Thus substitution in the error location formulas of further values of x to find the next root requires one fewer addition operation and one fewer multiplication operation. When another root is found, the error location formulas are further reduced by one. This procedure is repeated until, depending on the system utilized, all v roots are found or v is reduced to a value of 2, 3 or 4, and a fast-decoding method is utilized to find the remaining roots.

Description: FIELD OF INVENTION This invention relates to error correction code decoding mechanisms in general and more particularly to the decoding of Bose-Chaudhuri-Hocquenghem (BCH) error correction codes, including Reed-Solomon error correction codes. DESCRIPTION OF PRIOR ART The importance of error correction coding of data in digital computer systems has increased greatly as the density of the data recorded on mass storage media, more particularly magnetic disks, has increased. With higher recording densities, a tiny imperfection in the recording surface of a disk can corrupt a large amount of data. In order to avoid losing that data, error correction codes ("ECC's") are employed to, as the name implies, correct the erroneous data. Before a string of data symbols is recorded on a disk, it is mathematically encoded to form ECC symbols. The ECC symbols are then appended to the data string to form code words - data symbols plus ECC symbols - and the code words are then stored on the disk. When the stored data is to be retrieved from the disk, the code words are mathematically decoded. During decoding any errors in the data are detected and, if possible, corrected through manipulation of the ECC symbols [For a detailed description of decoding see Peterson and Weldon, Error Correction Codes , 2d Edition, MIT Press, 1972]. Stored digital data can contain multiple errors. One of the most effective types of ECC used for the correction of multiple errors is a Reed-Solomon code [For a detailed description of Reed-Solomon codes, see Peterson and Weldon, Error Correction Codes ]. Error detection and correction techniques for Reed-Solomon ECC's are well known. Id. One such technique begins with again encoding the data string in the retrieved code word to generate ECC symbols and then comparing these ECC symbols with the ECC symbols in the retrieved code word, i.e. the ECC symbols generated by the pre-storage encoding of the data, to detect any errors in the retrieved code word data. [For a detailed discussion of this error detection technique, see United States Patent 4,413,339 issued to Riggle and Weng]. The comparison of the two sets of ECC symbols is made by exclusive OR'ing ("XOR'ing") them. If there are no errors in the retrieved code word data, the XOR'ing will produce a string of symbols containing only zeros. If there are errors in the retrieved data, the result of the XOR'ing will be non-zero and error correction will be then performed, if possible. If the number of non-zero symbols which result from the XOR'ing is less than the number of errors the code is designed to correct, all the errors are in the ECC symbols, i.e. there are no errors in the data string, and no error correction is required. If the number of non-zero resulting symbols is equal to or greater than the number of errors the code is designed to correct, the retrieved data string contains one or more errors and error correction is then performed. In order to correct the data errors, the locations and the magnitudes or "values" of the errors must be determined. The first step in determining the error locations and the error values is to form error syndrome equations from the results of the XOR'ing of the ECC symbols. [For a detailed discussion of the generation of the error syndromes refer to United States Patent 4,413,339 issued to Riggle and Weng]. The error syndromes are then used to generate polynomials which, when evaluated, will identify the location and the value of each of the errors. Alternatively the error syndromes may be formed by using the entire retrieved code word. This will avoid the steps of re-encoding the retrieved data and comparing the ECC symbols with the retrieved ECC symbols. However, error syndromes must then be generated for every code word, even those without errors, although in the latter case the syndromes will be identically zero. Where there are errors, i.e. the error syndromes are not zero, the syndromes are then used to locate and correct any errors in exactly the same manner as the syndromes formed from the results of the XOR'ing of the ECC symbols. The choice between these two arrangements may, for example, depend on whether the syndromes are generated in software or hardware. The calculation of the values of the errors is necessarily dependent on their locations. The error locations are calculated by using the error syndromes to generate an error locator polynomial δ(x) of degree v, where v is the number of errors. The solutions or roots of the equation δ(x) = 0 designate the locations of the errors. These roots are of the form x i = α i , where α is the primitive element of the Galois Field GF(p q ) used to encode the data. The roots of the error locator equation are typically found using a Chien search. The Chien search systematically tries each element x of GF(p q ) as a possible solution to δ(x) = 0. Each time a new value of x is tried, v Galois Field multiplication operations and v Galois Field addition operations are performed to determine if x is a solution. Once all v roots have been found, they are substituted into an error evaluator polynomial Φ(x) and the corresponding error magnitudes, or values are calculated. The data can then be corrected by multiplying the erroneous data symbol by a correction symbol to produce an error-free data symbol. The time it takes to perform error correction significantly affects the rate at which data can be retrieved from a storage device. As the potential for errors in stored data increases with the use of higher recording densities, slow error correction has a material effect on the average speed with which the data can be retrieved. The increased data retrieval time in turn limits the speed of all computer applications that require the retrieval of stored data. This speed limitation occurs at a time when computer system technology advances have otherwise made possible faster data transfer operations. Thus there is a need for an error correction technique that can be performed more quickly than the methods currently in use. Such a technique will enable computer systems to operate at the faster rates permitted by the advances in the state of the art computer technology. SUMMARY OF THE INVENTION The invention is an error correcting system which calculates the error locations with a reduced number of operations. The error correcting system can thus more quickly correct the errors. Basically, each time a root of the error locator equation is found, the equation is modified to reduce the number of Galois Field multiplication and addition operations that are required to evaluate as possible solutions the remaining values of x. The modification, in effect, reduces the degree of the equation. All of the roots of the equation may be found using this technique, or the technique may be used to find several of the roots and a fast-decode method designed specifically for solving equations having two, three or four roots may be used to find the remaining roots. In brief summary the error locator equation is: 1 + δ 1 *x + δ 2 *x 2 + δ 3 x 3 + ... + δ v-1 *x v-1 + δ v *x v = 0 where "+" and "*" represent Galois Field addition and Galois Field multiplication, respectively, and "v" is the number of errors in the data. As described below, the coefficients of equation (1) are substituted into a succession of v error location formulas along with successive values of x, to determine if the various x's are roots of equation (1). Since equation (1) is of degree v, each such determination requires v multiplication and v addition operations. When the first root is found, extraction of the root corresponds to reducing the degree of equation (1) by one, to (v-1), and also to reducing the number of error location formulas by one to (v-1). Thus substitution in the error location formulas of further values of x to find the next root requires one fewer addition operation and one fewer multiplication operation. Thereafter, when another root is found, the error location formulas are further reduced by one. This procedure is repeated until, depending on the system utilized, all v roots are found or v is reduced to a value of 2, 3 or 4, and a fast-decoding method is utilized to find the remaining roots. Reducing the number of multiplication and addition operations required to find the remaining roots of the error locator equation each time a root is found speeds-up the error correction process. The faster errors in the data can be corrected, the faster the data can be transmitted to the remainder of the data processing system. This is particularly important as data is recorded at increased densities, leading to more errors, and thus requiring more error correction. DESCRIPTION OF THE DRAWINGS This invention is pointed out with particularity in the appended claims. The above and further advantages of this invention may be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which: Figure 1 is a functional block diagram of a decoding system built in accordance with a first embodiment of the invention; Figures 2A-B are flow charts of the steps involved in the operation of the first embodiment of the invention; Figure 3 is a functional block diagram of a decoding system built in accordance with a second embodiment of the invention; and Figures 4A-B are flow charts of the steps involved in the operation of a second embodiment of the invention. DETAILED DESCRIPTION It should be understood that all addition and multiplication operations performed by the inventive system are Galois Field operations and that the Galois Fields are of the form GF(p q ). Conventional techniques are used to generate the error syndromes from the data and then to generate the error locator equation, δ(x) = 0. With reference to Figures 1 and 2, an error correcting system 8 evaluates δ(x) at various values of x using the following set of error location formulas: δ 1 ' = δ 1 + α i (2 1 ) δ 2 ' = δ 1 '*α i + δ 2 (2 2 ) δ v '= δ v-1 '*α i + δ v (2 v ) where α i = x and the terms δ j ' are modifications of the δ j terms, not derivatives of these terms (step 50). Successive values of δ j ' are calculated from the previous values until the value of δ V ' is determined. If δ v ' is equal to ZERO for a particular x, x is a root of equation (1) (steps 51, 56). Formulas 2₁-2 V are evaluated using registers 10₁-10 v (generally referred to by the numeral 10), Galois Field multipliers 12₁-12 v (generally referred to by the numeral 12) and Galois Field adders 14₁-14 v (generally referred to by the numeral 14). To begin, the coefficients of equation (1) are stored in registers 10, a counter 18 and a comparator 30 are initialized to v, and an α register 38 is initialized to a first value of x, x = α i where i is typically zero. Register 38 applies the first x value to each of the multipliers 10 and to the adder 14₁. The adder 14 ₁ calculates the sum: δ 1 '= δ 1 + α i . This sum is applied to both to a register 16 where it is stored and to a multiplier 12₁ which, when clocked by a clock 34 through gates 26 as discussed in more detail below, calculates the product: δ 1 '*α i This product is applied to adder 14₂, which calculates the sum, δ₂'. The value of δ₂' is stored in a register 16, and it is also used to calculate the product δ₂'*α i . This product is then used to calculate δ₃' and the value of δ₃' is stored in register 16. The sums δ j ' and the products δ j '*α i are similarly calculated for each coefficient using the multipliers 12 and the adders 14, and the each of the values of δ j ' are in turn stored in the register 16. Register 16 is addressed by counter 18, which is set to the value v. Thus the register 16 applies the contents of the storage location addressed by the counter to its output. Accordingly, when the term δ v ' is applied to the register 16, it appears also at its output. This output is then applied to a zero compare 20 where it is compared to ZERO. If δ v ' equals ZERO, indicating that α i is a root of the error location equation, the output of the zero compare 20 is asserted. If δ v ' does not equal ZERO, indicating α i is not a root of the error locator equation, the output of the zero compare 20 is not asserted. Clock 34 controls the timing of the various multipliers and gates using three timers, namely t₁, t₂, and t₃, to avoid race conditions. Timer t₁ clocks counter 28 which, in effect, counts the number of multiplication operations performed in calculating δ v '. Timer t₂, which is slightly slower than t₁, clocks gates 26 which in turn clock multipliers 12. Timer t₃, which is slightly slower than timer t₂, acts as an input to an AND gate 32. To begin calculating the formulas 2₁-2 v , the sum δ i ' is calculated by adder 14₁ as described above and the sum is applied to multiplier 12₁. Timer t₁ clocks counter 28, and the counter applies a count of one, signalling the first of v multiplication operations, to the gates 26. Thereafter the gates 26, when clocked by timer t₂, apply a clock pulse to the first multiplier 12₁ and the first product, δ₁'* α i , is calculated. The output of counter 28 is also applied to the comparator 30, where it is compared to v. The comparator 30 asserts its output when the count equals v, indicating the occurrence of the "vth" multiplication operation. If the count of counter 28 is not equal to v, the output of the comparator 30 remains de-asserted. Assuming that the count does not equal v, the first product calculated by multiplier 12₁ is applied to adder 14₂ which adds it to δ₂ to produce the sum δ₂'. This sum is stored in the register 16 and is also applied to multiplier 12₂. Timer t₁ clocks the counter 28, which increases the count to two, indicating that the second multiplication is to occur. The output of counter 28 is applied to gates 26 which, when subsequently clocked by timer t₂, clock multiplier 12₂ which then calculates the product: δ 2 '*α i . This product is applied to adder 14₃ which calculates the sum δ₃', and the sum is again stored in register 16. The same series of addition and multiplication operations continue and the sums δ j ' are stored in the register 16 until the count of counter 28 equals v, indicating the start of the calculation of formula (2 v ). When the count of counter 28 equals v, the output of the comparator 30, which is comparing the count to v, is asserted. The output is applied to one input of an AND gate 32, which has a second input connected to timer t₃. Thus when timer t₃ is pulsed, the output of the AND gate 32 is asserted. The output is applied to one input of AND gate 22, which has a second input connected to the output of zero compare 20. If the sum δ v ' is equal to ZERO, that is, x is a root, the output of AND gate 22 will then be asserted. Otherwise, if δ v ' is not equal to ZERO, the output of the zero compare 20 remains de-asserted and thus the output of AND gate 22 is not asserted. If x is not a root of equation (1), a new value of x is substituted into formulas 2₁-2 v and the sum δ v ' is calculated and compared to ZERO to determine if it is a root (steps 52-54). Thus the asserted output of AND gate 32 is applied, through delay 33, to i) reset the clock 34, ii) load a new value of x=α i+1 from calculator 36 into register 38, and iii) enable calculator 36 to calculate a new value of x. The value of x loaded into register 38 is then evaluated as a possible root, in the manner described above. This evaluation involves v multiplication operations and v addition operations. If x is a root, the coefficients of equation (1), and accordingly the formulas 2₁-2 v , are modified and the degree of equation (1), that is, the value of v, is reduced by one (steps 58-60). Thereafter, a new value of x is substituted into the modified formulas 2₁-2 v and a new sum δ v ' is calculated (steps 62-64). With further reference to Figure 1, if x is a root the sum δ v ' is equal to ZERO and the output of the zero compare 20 is asserted. This output is applied to one input of AND gate 22. The second input of AND gate 22 is connected to the output of AND gate 32 which is asserted at the next t₃ clock pulse. Thus, two gate delays after t₃ is pulsed, the output of AND gate 22 is asserted. The asserted output of AND gate 22 is applied simultaneously to i) a memory 40, which stores the value α i as a root; ii) the counter 18, which decrements its count to v-1; and iii) the registers 10, which load the sums δ j '. The output of gate 22 is also applied a short time later, through delay 24, to the comparator 30, which decrements the value of v stored therein by one. Thereafter, clock 34 is reset through delay 33 and a new value of x=α i+1 is loaded into the α register 38. The calculator 36 is also enabled to begin calculating a new value of x=α i+1 . When timer t₁ is pulsed, the evaluation operations begin, using the modified coefficients, δ j ', and the new value of x. The evaluation involves one less multiplication operation and one less addition operation. Thus the time required for the evaluation is reduced from the time taken to evaluate the previous value of x as a root. Each value of x=α i+1 calculated by calculator 36 is checked against the code block length, not exceeding P q -1, to determine if the value is a "new" value of x (steps 54,64). If i+1 is less than or equal to the code block length, the value of x=α i+1 is a new value. If, however, i+1 is greater than the code length, the calculated value of x=α i+1 corresponds to an error location outside of the code length. If the value of x calculated by calculator 36 is not a "new" x value, it indicates that all the roots of equation (1) can not be found and thus the error locations can not all be determined to be within the code length. Thus calculator 38 notifies a system controller (not shown) that the data is uncorrectable (steps 55, 65). All the roots of equation 1 which are of the form x = α i can be found using the technique described above. However, known methods of finding the roots of degree 2, 3 or 4 equations in GF(p q ) may be used to find the remaining roots (steps 70-71, Figure 2B). The particular method used will depend on system design. A second embodiment uses a direct modification of the Chien search to find the roots of the error locator equation. With respect to Figures 3 and 4, an error correcting system 99 iteratively evaluates δ(x) by first adding the coefficients of equation (1) to produce the sum S v and comparing the sum to ONE (step 150-152). Thereafter δ(x) is evaluated using the following set of iterative error location formulas: δ 1 = δ 1 * α (3 1 ) δ 2 = δ 2 * α 2 (3 2 ) ... δ v = δ v * α v (3 v ) (step 166). Thus new values of S j are calculated each iteration and after i iterations the formulas have calculated δ k = δ k(original) * (α k ) i . After each iteration the δ j terms are added to produce the sum S v (step 168). If S v is equal to ONE for a particular iteration, for example the i th iteration, x=α i is a root (step 171). Formulas 3₁-3 v are evaluated using registers 100₁-100 v (generally referred to by the numeral 100), Galois Field multipliers 102₁-102 v (generally referred to by the numeral 102) and Galois Field adders 104₁-104 v (generally referred to by the numeral 104). To begin, the coefficients of equation (1) are stored in registers 100, a counter 108 and a comparator 120 are each initialized to v, and a register 126 is initialized to a first value of i = 0. The multipliers, counters and timers are clocked by a clock 124, which operates in the same manner as the clock 34 described above with reference to Figure 1. Each intermediate sum, S j , calculated in adders 104 is applied to a register 106 which is addressed by counter 108. When the sum S v is applied to the register 106, it appears at the output, also. The sum S v is then compared to ONE in a one compare 110. If the sum S v equals ONE, x=α i is a root of equation (1). If the sum S v does not equal ONE, x=α i is not a root. If x is not a root of equation (1), formulas 3₁-3 v are iteratively updated and the sum S v is calculated (steps 166-168). The sum is then compared to ONE to determine if the x corresponding to the particular iteration is a root (step 170). Accordingly, system 99 operates in a manner similar to the system described with reference to Figure 1. Thus the clock 124 is reset and the formulas are iteratively updated, corresponding to the earlier-described system trying a new value of x. The new sum Sv is then evaluated to detemine if x is a root. This evaluation involves v multiplication operations and v addition operations. If x is a root, the coefficients of formulas 3₁-3 v are modified and the degree of the equation, that is, the value of v, is reduced by one (steps 156-158). This reduces the number of multiplication and addition operations required to evaluate the formula for the next iteration. The coefficients δ j are modified as follows: δ 1 ' = 1 + δ 1 δ 2 '= δ 1 '+ δ 2 ... δ v ' = δ v-1 ' + δ v where the terms δ j ' are modifications of the δ j terms, not derivatives of these terms (step 156). The modified coefficients are then substituted into formulas 3₁-3 v and the formulas are evaluated for an associated next value of x. With further reference to Figure 3, if the sum S v is equal to ONE if x=α i is a root and the output of the one compare 110 is asserted. Thus the output of AND gate 112 is asserted two gate delays after the output of AND gate 122 is asserted at the next t₃ clock pulse. The asserted output of AND gate 112, which signifies that x=α i is a root of equation (1), is applied simultaneously to i) a memory 130, which stores the value α i as a root; ii) the counter 108, which decrements its count to v-1; and iii) a counter 126, which, through gates 128, enables successive registers 100 to load the associated sums δ j . The output of gate 112 is also applied a short time later, through delay 123, to the comparator 120, which decrements the value of v stored therein by one. Thereafter, clock 124 is reset through delay 123, and the evaluation operations begin, using the modified coefficients, when timer t₁ is pulsed. The evaluation involves one less multiplication operation and one less addition operation. Thus the time required for the evaluation is reduced from the time taken to evaluate the iteratation corresponding to the previous value of x. The value of i in registers 126, which is updated for each iteration is continuously checked against the code block length, P q -1, to determine if the value is a "new" value of x (step 164) in the same manner as calculator 36 described with reference to Figure 1. If x is a new value, an i th iteration will be performed. If x is not a "new" value, it indicates that all the roots of equation (1) can not be found in GF(p q ) and thus the error locations can not all be determined. The system controller is thus notified that the data is uncorrectable (step 165). All the roots of equation 1 of the form x = α i can be found using the technique described above. However, known methods of finding the roots of degree 2, 3 or 4 equations in GF(p q ) may be used to find the remaining roots (step 176). The particular method used will depend on system design. The foregoing description has been limited to two specific embodiments of this invention. It will be apparent, however, that variations and modifications may be made to the invention, with the attainment of some or all of the advantages of the invention. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the scope of the invention as defined by the appended claims.

Claims: A method of determining the locations of erroneous symbols in a received data code word which is formulated by encoding data symbols in accordance with a BCH code, said method comprising the steps of: A. receiving a data code word; B. determining if the code word contains errors; C. if the code word contains errors, generating an error locator equation relating to the code word, the error locator equation being of the form: 1 + δ 1 *x + δ 2 *x 2 + δ 3 *x 3 + ... + δ v-1 *x v-1 + δ v *x v = 0, where * represents multiplication over a Galois Field used to encode the data symbols and + represents addition over the Galois Field and the roots of the error locator equation correspond to the locations of erroneous code word symbols; the method being characterised by the steps of: D. determining if α i , where α i corresponds to the location of a data symbol in the code word, is a root of the error locator equation, and thereby determining that the corresponding data symbol is erroneous, by: i. calculating (50), using the coefficients of the error locator equation, the value of δ v ' by iteratively calculating δ j ' j=1 to v according to the formulas: δ 1 ' = δ 1 + α i δ 2 '= δ 1 '*α i + δ 2 ... δ v ' = δ v-1 '*α i + δ v ii. comparing (51) δ v ' to ZERO, and iii. storing α i as corresponding to the location of an erroneous data code word symbol if δ v ' equals ZERO, which indicates that α i is a root of the error locator equation; E1. if α i is not a root, trying as a root of the error locator equation a next value of α i = α i+1 (53,50), which corresponds to the next data symbol location, by repeating step D; E2. if α i is a root; i. updating (58) the error locator equation and the error locator formulas by replacing the coefficients with the δ j ' values calculated in step D and thereby reducing (60) the degree of the equation and the number of formulas, ii. selecting a next value of α i = α i+1 (62), which corresponds to the next data symbol location; F. repeating steps D and E until a predetermined number of error locations have been found. The method of claim 1 further including the steps of: G. determining (72) the remaining error locations by finding the roots of the reduced error locator equation by using a fast-decode method that finds the roots of an equation of the predetermined degree; and H. transmitting the received code word and the stored α i values corresponding to the error locations to an error correction circuit for correction of the erroneous data symbols. The method of claim 1, wherein the step of repeating steps D and E further includes: a. repeating the steps (50,51) until either all the roots of the error locator equation are found or the α i values corresponding to all possible code word symbol locations have been tried as possible roots; and b. if all the roots have been found, transmitting the received code word and the stored α i values corresponding to the error locations to an error correction circuit for correction of the erroneous data symbols; or c. if the α i values corresponding to all possible code word symbol locations have been tried as possible roots and all the roots have not been found, labeling (55) the data code word uncorrectable. A method of determining the locations of erroneous symbols in a received data code word which is formulated by encoding data symbols in accordance with a BCH code, said method comprising the steps of: A. receiving a data code word; B. determining if the code word contains errors; C. if the code word contains errors, generating an error locator equation relating to the code word, the error locator equation being of the form: 1 + δ 1 *x + δ 2 *x 2 + δ 3 *x 3 + ... + δ v-1 *x v-1 + δ v *x v = 0, where * represents multiplication over a Galois Field used to encode the data symbols and + represents addition over the Galois Field and the roots of the error locator equation corresponds to the locations of erroneous code word symbols; the method being characterised by the steps of D. determining if α i , where α i corresponds to the location of a data symbol in the code word, is a root of the error locator equation, and thereby determining that the corresponding data symbol is erroneous, by: i. setting (150) an iteration counter to 0; ii. adding (150) the coefficients of the error locator equation, and iii. if the sum equals ONE (152,154) indicating α i is a root of the error locator equation, storing the value α i , where i equals the count of the iteration counter; E1. if α i is a root (154), updating the error locator equation by replacing (156) the coefficients and reducing (158) the degree of the equation, said coefficients of the error locator equation being updated by replacing (156) them with δ j ' values calculated using, as appropriate, the formulas: δ 1 ' = 1 + δ 1 δ 2 ' = δ 1 '+ δ 2 ... δ v ' = δ v-1 ' + δ v ; the resulting error location equation having v-1 terms; E2. if α i is not a root (160), updating (166) the coefficients of the error locator equation using the fomulas: δ 1 = δ 1 * α δ 2 = δ 2 * α 2 δ v = δ v * α v ; F. incrementing (162) said counter by one; G. repeating steps D through F for successive values of α i . The method of claim 4 wherein the steps D and F are repeated until either all the roots of the error locator equation are found or the α i values corresponding to all possible code word symbol locations have been tried as possible roots, and the method further includes the step of a. if all the error locations have been found, transmitting the received code word and the stored α i values corresponding to the error locations to an error correction circuit for correction of the erroneous data symbols; or b. if the α i values corresponding to all possible code word symbol locations have been tried as possible roots and all the roots have not been found, labeling the data code word uncorrectable. The method of claim 4 further including repeating steps D-F for successive values of α i until either a predetermined number of roots are found and the reduced error locator equation has a predetermined degree (174) or the α i values corresponding to all possible code word locations have been tried as possible roots; and a. if the α i values corresponding to all possible code word locations have not been tried: i. determining (176) the remaining error locations by using a fast-decode method designed to find the roots of an equation of the predetermined degree, and ii. transmitting the received code word and the α i values corresponding to the error locations to an error correction circuit for correction of the erroneous data symbols, or b. if the α i values corresponding to all possible code word locations have been tried labeling the data code word uncorrectable. An apparatus for determining the locations of erroneous symbols in a received data code word which is formulated by encoding data symbols in accordance with a BCH code, said apparatus including: A. means for receiving a data code word; B. means for determining if the code word contains errors; C. means for generating, for a code word that contains errors, an error locator equation relating to the code word, the error locator equation being of the form: 1 + δ 1 *x + δ 2 *x 2 + δ 3 *x 3 + ... + δ v-1 *x v-1 + δ v *x v = 0, where * represents multiplication over a Galois Field used to encode the data symbols and + represents addition over the Galois Field and the roots of the error locator equation correspond to the locations of erroneous code word symbols; the apparatus being characterised by D. calculating means (10,12,14) for calculating for α i , where α i corresponds to the location of a data code word symbol, using the coefficients of the error locator equation, the value of δ v ' by iteratively calculating δ j ' j = 1 to v, according to the formulas: δ 1 '= δ 1 + α i δ 2 '= δ 1 '*α i + δ 2 δ v ' = δ v-1 '*α i + δ v E. means (40) for storing α i as an indicator of the location of an erroneous symbol if δ v ' equals ZERO, which indicates that α i is a root of the error location equation; F. updating means (20,22,EN,10), responsive to finding an α i value which is a root, for updating the error location equation and the error location formulas by replacing the coefficients with the δ j values calculated by said calculating means and thereby reducing the degree of the error locator equation and the number of formulas; and supplying the updated error locator equation to said calculating means (10,12,14); G. means (36,38) for supplying to said calculating means a next value of α i = α i+1 ; H. said calculating means (10,12,14) calculating the value of δ v ' for the α i value supplied to it until a predetermined number of roots are found. The apparatus of claim 7 wherein the calculating means (10,12,14) finds the remaining error locations by using a fast-decode method designed to solve an equation of the predetermined degree. The apparatus of claim 8 further including a means for correcting the errors in the received code word using the α i values corresponding to the error locations if all the roots of the error location equation are determined. The apparatus of claim 7 wherein the means (36,38) for supplying the α i values to the calculating means either supplies all values up to the block length of the code used to encode the data or supplies values only until all error locations are determined. An apparatus for determining the locations of erroneous symbols in a received data code word which is formulated by encoding data symbols in accordance with a BCH code, said apparatus including: A. means for receiving a data code word; B. means for determining if the code word contains errors; C. means for generating, for a code word that contains errors, an error locator equation relating to the code word, the error locator equation being of the form: 1 + δ 1 *x + δ 2 *x 2 + δ 3 *x 3 + ... + δ v-1 *x v-1 + δ v *x v = 0, where * represents multiplication over a Galois Field used to encode the data symbols and + represents addition over the Galois Field and the roots of the error locator equation correspond to the locations of erroneous code word symbols; D. an iteration counter (126), set to an initial value; E. an adder (100,104) for adding the coefficients of the error locator equation; F. storage means (130) for storing the value α i , where i equals the count of the iteration counter, as an indicator of the location of an erroneous symbol if the coefficient sum equals ONE, which indicates that α i is a root of the error locator equation; G. updating means including: i. cascaded adding means for updating the coefficients of the error locator equation when α i is a root, that is, when an error location is found, by replacing the coefficients and reducing the degree of the error locator equation, said coefficients of the error locator equation being updated by replacing them with δ j values calculated using, as appropriate, the formulas: δ 1 ' = 1 + δ 1 δ 2 ' = δ 1 ' + δ 2 ... δ v ' = δ v-1 ' + δ v the resulting error location equation having v-1 terms; said updating means supplying the updated coefficients to the adder, or ii. multiplication means (102) for updating the coefficients of the error locator equation, if an α i value is not a root, using the formulas: δ 1 = δ 1 * α δ 2 = δ 2 * α 2 ... δ v = δ v * α v said updating means supplying the updated coefficients to the adder; H. means (124) for incrementing said iteration counter (126) each time said updating means supplies updated coefficients to said adder, provided that all the roots have not been found or i does not exceed the code block length of the code used to encode the data; I. means for correcting the errors in the code word using the stored α i values if all the roots are found; and J. means for labeling the code word uncorrectable if all the α i values corresponding to all possible code word symbol locations have been tried and all the roots have not been found. The apparatus of claim 11 wherein the means for incrementing said counter does so until either a predetermined number of roots are found or i equals the block length of the code used to encode the data, and the apparatus further includes K. means for labeling the code word uncorrectable if all the α i values corresponding to all possible code word symbol locations have been tried and the predetermined number of roots have not been found; L. means for finding the remaining error locations by using a fast-decode method designed to solve an equation of the predetermined degree. The apparatus of claim 11 further including a means for correcting the errors in the code word using the α i values corresponding to the error locations.

Inventors: WENG LIH-JYH, WENG, LIH-JYH
Applicants: QUANTUM CORP, QUANTUM CORPORATION
Application year: 1989
Main classification: H03M13
IPC codes: H03M13, G06F11