Logic circuit

Abstract: The present invention provides a logic circuit com­ prises a first power terminal (V SS ), a second power ter­ minal (V DD ) set at a higher potential than the first power terminal (V SS ), a first FET (Q₁) of a first con­ ductivity having a current path coupled to the first power terminal (V SS ), a second FET (Q₂) of a second con­ ductivity having a current path coupled to the second power terminal (V DD ), and an input terminal commonly coupled to gate terminals of the first and second FETs (Q₁, Q₂), the first FET (Q₁) and the second FET (Q₂) having a relationship expressed approximately by the following equation: where R S is a resistance of a resistor element parasitically produced between the first power terminal (V SS ) and the current path of the first FET (Q₁), R D is a resistance of a resistor element parasitically pro­ duced between the second power terminal (V DD ) and the current path of the second FET (Q₂), W P is a channel width of the first FET (Q₁), W P is a channel width of the second FET (Q₂), L N is a channel length of the first FET (Q₁), L P is a channel length of the second FET (Q₂), µN is a first carrier mobility of the first FET (Q₁), and µ P is a second carrier mobility of the second FET (Q₂).

Description: The present invention relates to a logic circuit and, more particularly, to a technique of making the layout of a power source of an analog circuit in a semiconductor integrated circuit and setting a circuit constant. A description will be given below of a chopper type comparator for typical use in conventional A/D comparators. Fig. 3 exemplifies the use of a chopper type comparator. In this diagram, reference numeral 1 denotes the main part of a chopper type comparator, reference numeral 2 a sample and hold circuit of the comparator, Q1 and Q2 N and P channel field effect transistors (IG-FET) which constitute an inverter 3, Q₃ and Q₄ feedback switching transistors, V DD and V SS power sources, C a capacitor, SW1 and SW2 switches whose switching operations are controlled by signals  and  , V ref a reference voltage, and A in a comparator input. Referring to Fig. 3, the switch SW1 on the A in side and the feedback switches Q₃, Q₄ of the inverter 3 are turned ON to accumulate charges in the capacitor C. Since the inverter 3 has its input and output short-circuited at this time, the potential at the point A equals a threshold value V C of the inverter 3. The charges Q accumulated in the capacitor C can therefore bve given by: Q = (V C - A in ) C Then, the switches SW1, Q₃ and Q₄ are turned OFF and the switch SW2 on the V ref side is turned ON. As the amount of charges accumulated in the capacitor C does not vary, with V A being the potential of the point A, the following can be derived: Q = (V A - V ref ) C From equations (1) and (2), we can attain: V A = V C + (V ref - A in ) Fig. 4 illustrates the input-output characteristic of a typical inverter. The point where the linear line V in =V out intersects the characteristic curve is the threshold value V C of the inverter. From this diagram, it is understood that when an input voltage is off V C , even slightly, this deviation will appear in amplified manner in the output. That is, V₁′ - V C = α₁ (V C - V₁) V C - V₂′ = α₂ (V₂ - V C ) where α₁ and α₂ are amplification factors of the inverter 3. From the equation (3), therefore, if A in is smaller than V ref , the output V A1 (= V out ) of the comparator would be: V A1 = V C + α₁ (V ref - A in ) α₁ > 1, and if A in is greater than V ref , the output V A2 (= V out ) of the comparator would be: V A2 = V C + α₂ (V ref - A in ) α₂ > 1. The conventional comparators should be concerned with an offset initiated by the resistors in the power sources because of the following reason. As the input of the inverter 3 is as the middle level at the sampling time (at which charges are being accumulated in the capacitor C with SW1, Q₃ and Q₄ all being ON), the P and N type transistors Q₂ and Q₁ of the inverter are both turned ON to thereby permit a through current to flow between the power sources V DD and V SS . Given that I P is the through current at that time and R S and R D are a source resistor of the inverter on the side of the reference power source (V SS ) and a source resistor on the side of the supplying power source (V SS ), respectively, the potential on the V SS side increases by I P R S while the potential on the V DD side falls by I P R D . The threshold value V C at this time can be given by: VC = β N V TN + β P {(V DD - I P R D ) - I P R S - |V TP |} β N + β P + I P R S β N V TN + β P (V DD - |V TP |) + I P (β N R S - β P R D ) β N + β P β N ≡ W N 2L N · E 0X t 0X µ N , β P ≡ W P 2L P · E 0X t 0X µ N where V TN and V TP are the threshold voltages of N and P type transistors, respectively, L N and W N are the channel length and width of the N type transistor, L P and W P are the channel length and width of the P type transistor, µ N and µ P are the mobilities of electrons and holes, and E 0X and t 0X are the dielectric constant and thickness of a gate oxide film. When the operation enters a comparing period (unlike in the sampling time, only SW2 being turned ON), the input potential of the inverter varies from V C , thus causing the through current to become to I P ′. The threshold value V C ′ at this time is VC′ = β N β TN + β P (V DD - |V TP |) + IP′(β N R S - β P R D ) β N + β P From the equations (5) and (6) it should be understood that V C and V C ′ have the following relationship: V C ′ = V C + ΔV ΔV = (I P - I P ′)(β N R S - β P R D ) β N + β P Therefore, the actual charges Q′ accumulated in the capacitor C at the sampling time is Q′ = (V C + ΔV - A in ) C. From this equation, the potential V A at the point A at the time a comparison is made will be V A = V C + (V ref ) - A in ) + ΔV Comparing the equation (3) with the equation (7) shows that the an offset of ΔV occurs according to the prior art. To reduce the offset originated from the resistors of power sources, efforts have been made to make the resistances of these resistors as small as possible. This has resulted in thick power wires, which is a cause of a larger chip size. Minimizing the resistances also restricts the location of the comparator. From A. H. Seidman, Integrated Circuits applications handbook, 1983, John Wiley & Sons, New York, US, pages 107 - 111 "CMOS Inverters" a balanced CMOS inverter design is known. wherein the dimensioning of an inverter circuit is described to achieve a voltage V m which is 2,5 volt, i. e. in the middle between V DD = + 5 volt and V SS = 0 volt. From Patent Abstract of Japan, Vol. 9, No. 277 (E-355), November 6, 1985 referring to JP-A-60-119 120, a chopper type comparator is known, including an (n) channel MOS transistor and and a (p) channel MOS transistor. The threshold voltage of the (n) channel MOS transistor and the (p) channel MOS transistor is set to 1/2 of a power supply voltage of the inverter. Accordingly, it is an object of this invention to reduce or eliminate a variation in threshold value of an inverter originated from the resistors of power sources of a circuit. The present invention provides a logic circuit comprising: a first power terminal; a second power terminal set at a higher potential than said first power terminal; a first FET of a first conductivity having a current path coupled to said first power terminal via a first current path; a second FET of a second conductivity having a current path coupled to said second power terminal via a second current path; said first and second FET's being connected in series between said first and second power terminals; an input terminal commonly coupled to gate terminals of said first and second FET's, and an output terminal connected to the common point between said first and second FET's characterized by the current path of said first FET and the current path of said second FET having a relationship expressed approximately by the following equation: where R S is the resistance of said first current path from said first power terminal to said current path of said first FET, R D is the resistance of said second current path from said second power terminal to said current path of said second FET, W N is a channel width of said first FET, W P is a channel width of said second FET, L N is a channel length of said first FET, L P is a channel length of said second FET, µ N is a mobility of a first carrier of said first FET, and µ p is a mobility of a second carrier of said second FET. The variation in threshold value in an inverter which does not embody this invention is caused by the offset ΔV, and is originated from the term IP(β N R S - β P R D ) in the aforementioned equation (5) which is a variation in threshold value of the inverter. If the following is satisfied in this term, therefore, β N R S = β P R D the offset ΔV would become zero, and the variation in threshold would be also zero as a consequence. In other words, this invention is characterized in that, paying attention to the source resistors on the V DD and V SS sides to which no consideration has conventionally been given, the resistances of these resistors and the circuit constant of the inverter are made to have the relationship given by the equation (8). In the case of a chopper type comparator, for instance, since the threshold value does not vary, ΔV in the equation (7) is 0 V, thus eliminating a ΔV-originated offset. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram illustrating one embodiment of this invention; Fig. 2 is a circuit diagram illustrating another embodiment of this invention; Fig. 3 is circuit diagram for explaining an example to which this invention is not applied; Fig. 4 is diagram illustrating the input-output signal characteristic of an inverter; Fig. 5 is diagram illustrating transistors embodying the invention with the same channel width and the same channel length; Fig. 6 is a diagram illustrating transistors embodying this invention with different channel widths and the same channel length; Fig. 7 is a diagram illustrating transistors embodying this invention with the same channel width and different channel lengths; and Fig. 8 is a diagram illustrating transistors embodying this invention with different channel widths and different channel lengths. On embodiment of this invention will now be described referring to the accompanying drawings. Fig. 1 illustrates a circuit according to this embodiment in comparison with the one shown in Fig. 3, with only the main part of a chopper type comparator being illustrated. For the purpose of comparison and ease of understanding, the same reference numerals as shown in Fig. 3 are used in Fig. 1 to specify the identical or corresponding elements. R D and R S specify, as mentioned earlier, the wiring resistances of power sources V DD and V SS , and these resistances are set from the circuit constant of the inverter 3 to satisfy the equation (8). If R D and R S are known in advance, the circuit constant of the inverter 3 should be altered to satisfy the equation (8). In other words, if there is the relationship of the equation (9) satisfield in I P (β N R S - β P R D ) in the equation (5), a variation in threshold value, the threshold values R S and R D and the circuit constant of the inverter 3 need only to have the relation of the equation (8), i.e., The following is an example of parameters satisfying these equations (5) and (8). The first channel length L N of the first FET Q₁ is 2.4 µm, the first channel width W N thereof 6.2 µm, and the first carrier mobility µ N 200 cm²/V·sec. With regard to the second FET Q₂, the second channel length L P is 2.4 µm, the second channel width W P 14.1 µm, and the second carrier mobility up 85 cm²/V·sec. Of these parameters, the first channel length L N and the first channel width WN of the first FET Q₁ should preferably be 1.2 µm to 100 µm, and so should the second channel length L P and second channel width W P of the second FET Q₂. Such simple means can eliminate a variation in threshold value of the inverter 3 to thereby eliminate an offset originated from the source resistors. This can be achieved irrespective of the resistances of the source resistors, which does not therefore restrict the location of the comparator so much. Further, the wires of the power sources need not be made thick, thus preventing the chip size to be undesirably increased. Fig. 2 illustrates another embodiment of this invention in which an addition to wiring resistors R AlD and R AlS (equivalent to R S and R D , respectively) of Al, higher resistors R D ′ and R S ′ are inserted in the circuit. If the values of R D ′ and R S ′ are set to make R AlS and R AlD negligible, the circuit constant can be determined only from R D ′ and R S ′. In other words, given that R AlD , R AlS << R D ′, R S ′, R S ′ + R AlS R D′ + R AlD = R S R D . In this case, the aforementioned parameters need only be set to satisfy as per the first embodiment. Different influences will be exerted on fabrication of a semiconductor device depending on which of the parameters, the channel lengths (L N , L P ) of the two FETs, their channel widths (W N ,W P ) or the resistances (R S , R D ) of the source electrodes, should be adjusted in realizing the above equation. Fig. 5 illustrates transistors embodying this invention which have the same channel width and the same channel length; reference numeral 50 denotes a P-type diffusion, 52 an N-type diffusion, and 54 contact holes. If the equality is realized by the resistances R S , R D of the source electrodes while making the channel lengths L N , L P and the channel widths W N , W P fixed as shown in Fig. 5, regular channel lengths and channel widths can be maintained, thus ensuring a uniform shape of the device. This produces such a merit that there would be no variation in fabricated semiconductor devices which is inevitably caused by altering the channel lengths L N , L P and channel width W N , W P , and an error in characteristic of the devices it not therefore likely to occur. In addition, the circuit area of the semiconductor device will not be increased, making it possible to realize a higher integration of the device. The resistances R S , R D of the source electrodes may be adjusted by using a resistor made of polysilicon, etc. Fig. 6 illustrates transistors embodying this invention which have different channel widths but the same channel length; reference numeral 50 denotes a P-type diffusion, 52 an N-type diffusion, and 54 contact holes. The equality of this invention may be realized by altering the channel width W N , W P while setting the channel lengths L N , L P equal to each other, as shown in Fig. 6. Employing the same channel length for L N , L P throughout the device ensures alignment of this invention without causing a variation in electric characteristic of the overall device. In addition, designing the pattern of a semiconductor device in this case is easier than the one involved in a case where the channel width W N , W P are altered. Fig. 7 illustrates transistors embodying this invention which have the same channel width but different channel lengths; reference numeral 50 denotes a P-type diffusion, 52 an N-type diffusion, and 54 contact holes. The equality of this invention may be realized by altering the channel lengths L N , L P while setting the channel widths W N , W P equal to each other, as shown in Fig. 7. Fig. 8 illustrates transistors embodying this invention which have different channel widths and different channel lengths; reference numeral 50 denotes a P-type diffusion, 52 an N-type diffusion, and 54 contact holes. The equality of this invention may be realized by altering both the channel widths W N , W P and the channel lengths L N , L P , as shown in Fig. 8. Although the foregoing description has been given mainly with reference to a chopper type comparator, this invention can also be applied to an inverter being used as an amplifier. As described above, according to this invention, a variation in threshold value of an inverter can be eliminated by simple means, so that an offset originated from the resistors of power sources can easily be eliminated. In addition, since the elimination of the offset can be realized irrespective of the values of the source resistors, no restriction will be made on the location of the comparator. Further, the wires of the power sources need not be made particularly thick, thus preventing the chip size from being undesirably increased.

Claims: A logic circuit comprising: a first power terminal (V SS ); a second power terminal (V DD ) set at a higher potential than said first power terminal (V SS ); a first FET (Q₁) of a first conductivity having a current path coupled to said first power terminal (V SS ) via a first current path; a second FET (Q₂) of a second conductivity having a current path coupled to said second power terminal (V DD ) via a second current path; said first and second FET's (Q₁, Q₂) being connected in series between said first and second power terminals (V SS ; V DD ); an input terminal (A) commonly coupled to gate terminals of said first and second FET's (Q₁, Q₂), and an output terminal connected to the common point between said first and second FET's (Q₁, Q₂) characterized by the current path of said first FET (Q₁) and the current path of said second FET (Q₂) having a relationship expressed approximately by the following equation: where R S is the resistance of said first current path from said first power terminal (V SS ) to said current path of said first FET (Q₁), R D is the resistance of said second current path from said second power terminal (V DD ) to said current path of said second FET (Q₂), W N is a channel width of said first FET (Q₁), W P is a channel width of said second FET (Q₂), L N is a channel length of said first FET (Q₁), L P is a channel length of said second FET (Q₂), µ N is a mobility of a first carrier of said first FET (Q₁), and µ p is a mobility of a second carrier of said second FET (Q₂). A logic circuit according to claim 1, characterized by : a capacitor (C) having one end commonly coupled to said gate terminals of said first and second FETs (Q₁,Q₂); a first switch (SW1) having one end coupled to said capacitor (C) and another end supplied with a signal (A in ) to be detected; and a second switch (SW2) having one end coupled to said capacitor (C) and another end applied with a reference voltage (V ref ). A logic circuit according to claim 1 or 2, characterized in that said first channel length (L N ) equals said second channel length (L p ), and said first channel width (W N ) equals said second channel width (W p ). A logic circuit according to claim 1 or 2, characterized in that said first channel length (L N ) equals said second channel length (L p ). A logic circuit according to claim 1 or 2, characterized in that said first channel width (W N ) equals said second channel width (W p ). A logic circuit according to claim 1 or 2, characterized in that said first channel length (L N ) differs from said second channel length (L p ) and said first channel width (W N ) differs from said second channel width (W p ). A logic circuit according to claim 1 or 2, characterized in that said first channel length (L N ) of said first FET (Q₁) is in a range from 1.2 um to 100.0 µm. A logic circuit according to claim 1 or 2, characterized in that said first channel width (W N ) of said first FET (Q₁) is in a range from 1.2 µm to 100.0 µm. A logic circuit according to claim 1 or 2, characterized in that said second channel length (L p ) of said second FET (Q₂) is in a range from 1.2 µm to 100.0 µm. A logic circuit according to claim 1 or 2, characterized in that said second channel width (W p ) of said second FET (Q₂) is in a range from 1.2 µm to 100.0 µm.

Inventors: SAITO TOMOTAKA C O INTELLECTUA, SAKAI HIDEO C O INTELLECTUAL P, SAITO, TOMOTAKA C/O INTELLECTUAL PROPERTY DIV., SAKAI, HIDEO C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H03K5
IPC codes: H03F3, H03K5, H03K19