Improved floating point computation unit

Abstract: The floating point computation unit for providing a sign/­ magnitude subtraction operation, uses propagate/generate logic (10, 11, 12) responsive to the subtraction operands (A and B) to produce intermediate and final propagate and generate outputs (P and G). First carry computation logic (13) is responsive to the final propagate and generate outputs (P and G) and to a carry-in bit (C₆₃) to produce final carry outputs (C₁₅, C₃₁, C₄₇) and a carry-out bit (C o ). The latter outputs are used (14, 15, 17) to produce a first subtraction result (R). Second carry computation logic (18) responds to the intermediate propagate and generate outputs (P and G) to produce second final carry outputs (C′₁₅, C′₃₁, C′₄₇). The latter outputs and selected intermediate propagate outputs (P) are used (19, 20, 21) to produce a second subtraction result ( -R ). The carry-out bit (C o ) then selects (22) one of the two subtraction results as the final subtraction result (R or -R ). The floating point unit can further normalize an exponent result in conjunction with a mantissa result which is formed as a plurality of data slices. The number of leading zeros in each data slice is determined and each number of leading zeros is subtracted from the exponent result to produce a plurality of subtracted results. One of the subtracted results is then selected as the normalized exponent result.

Description: This invention relates to a system for use in a floating-point computation unit for providing a sign/magnitude subtraction operation for a first operand A and a second operand B. In performing a sign/magnitude mantissa subtraction operation, conventional techniques utilize multi-stage propagate/generate carry techniques for producing a subtraction result, e.g. a subtraction of operands A and B, algebraically represented by (A-B), and then utilise a completely redundant set of propagate/generate carry stages for producing the negative result, i.e. (B-A). The highest order carry-out bit of the (A-B) process is then used to determine which result to select in accordance with well-known binary arithmetic techniques. Japanese Laid-open patent application JP-A-56 147 237 is believed to constitute an example of this general type of operation. Also, United States Patent US-A-3 814 925 describes a system which generates A-B and B-A using two totally separate sets of circuits. Other techniques which have been proposed to reduce costs by using fewer components have undesirably increased the overall time needed to perform the operation. It is desirable to perform the operations at as low a cost as possible without increasing the time required for the performance thereof. We have appreciated that the need for a completely redundant set of propagate/generate carry stages undesirably increases the cost of the overall system in performing such operation. The present invention is defined in claim 1 below, to which reference should now be made. Advantageous features of the invention are set forth in the appendant claims. An example of the invention is described below with reference to the drawing in which, in order to reduce the component costs for performing a sign/magnitude mantissa subtraction operation without increasing the time required therefor in comparison with conventional techniques, the need for using a completely redundant propagate/generate carry system is avoided. It makes use of a portion of the same propagate/generate carry stages for both the (A-B) and (B-A) subtraction operations. The remaining carry generator stages are used to complete the (A-B) operation to achieve a first result R, while a number of more simplified carry generator stages are used to complete the (B-A) operation to achieve the negative result -R. The carry-out bit from the (A-B) operation then determines which result, i.e. R or -R, is to be used as the desired subtraction result. The use of common propagate/generate carry stages in determining both results, and the use of simplified stages to complete the inverse subtraction result, reduces the overall cost of the subtraction operation as compared with previously-used techniques. The invention can be described in more detail, by way of example, with the help of the drawing, in which the sole figure depicts a block diagram of a portion of a floating point computation unit for use in performing an improved subtraction operation in accordance with the invention. The figure shows a block diagram which illustrates a particular embodiment of the technique of the invention in improving the performance of a subtraction operation of a mantissa in a floating point unit. As can be seen therein, the subtraction of two operands, e.g. (A-B), is carried out in a conventional floating point unit by an addition process in which the binary digital addition can be represented by the quantity (A+ B +1), where B is the logical inverse of B, which quantity is in effect the algebraic equivalent of (A-B). Such a technique is well known and is performed by utilizing a number of propagate/generate carry stages as depicted in the figure. Thus, in a system which utilizes 64-bit operands A and B, such operands are supplied to the first stage of a plurality of successive stages 10-12 of propagate/generate carry logic which produce, respectively, 64-bit, 16-bit and 4-bit propagate (P) and generate (G) outputs in accordance with conventional propagate/generate carry stage operations. The P and G outputs of generator stage 12 are supplied to a carry generator stage 13 which has a carry-in bit (CY IN) inserted at bit 63 thereof, identified as (C₆₃), so as to produce 3 output carry bits at bit positions 15, 31 and 47 (C₁₅, C₃₁ and C₄₇) and a carry-out bit (C O ). Further carry bits are supplied, as shown, at stages 14 and 15, to which the CY IN bit is also supplied, the carry outputs of stage 15 thereupon being combined at exclusive-or gates 17 with the corresponding propagation bits P of the P outputs of stage 10, as would be well-known, to provide an output result R which in effect represents algebraically the subtraction of operand B from operand A, i.e. (A-B). The operation of such stages 10-17 is well known in the art and has been used for many years to provide a subtraction result R, or (A-B), for a pair of input operands A and B. In order to obtain the negative result (B-A), which can be referred to as -R, it has been conventional to utilize essentially a completely redundant set of all the same stages of operation for performing a (B-A) operation (in this case B+ A +1), and then to select the appropriate result, R or -R, in accordance with the carry-out bit, as is well-known for conventional handling of such a subtraction process. In accordance with the invention, however, the process for obtaining -R is greatly simplified by utilizing the P and G outputs from propagate/generate stage 12 for supply to a plurality of simplified carry generator stages 18, 19 and 20, as depicted in the figure. In such operation, in order to obtain the (B-A) result, no carry in (CY IN) bit is required at such stages and, accordingly, the logic required at each of such stages to produce the required output carry bits from the last stage 20 can be simplified. The carry bits from stage 20 are suitably combined with the propagation bits P at exclusive-or gates 21 to produce the - R output as shown. In the figure, for convenience, the carry bits from each of such stages each use the notification C′ to distinguish them from the carry bits generated at stages 13, 14 and 15. The R and -R outputs are supplied to a multiplexer circuit 22 (- R being inverted to produce -R as shown) which selects one or the other result depending on the presence or absence of a carry-out (C O ) bit from stage 13 to produce the desired subtraction result, i.e., either (A-B) or (B-A). The use of common propagate/generate stages 10-12 together with simplified carry stages 18-20, as opposed to an entirely redundant set of all of the stages 10-15, for determining the -R result, reduces the number of components required and the corresponding costs thereof over conventional approaches, without sacrificing the speed of the subtraction operation process, since the results R and -R are computed substantially simultaneously for supply to multiplexer 22.

Claims: A system for use in a floating-point computation unit for providing a sign/magnitude subtraction operation for a first operand A and a second operand B to produce two subtraction results A-B and B-A substantially simultaneously and selecting one or the other as output, the system comprising: propagate-generate means (10,11,12) responsive to the first and second operands for producing intermediate propagate and generate outputs and final propagate and generate outputs; a first carry computation means (13) responsive to the final propagate and generate outputs and to a carry-in bit for producing first final carry outputs and a carry-out bit; and means (14,15,17) responsive to the first final carry outputs and to selected intermediate propagate outputs for producing a first subtraction result (A-B); characterised by: second carry computation means (18) responsive to the final propagate and generate outputs for producing second final carry outputs; means (19,20,21) responsive to the second final carry outputs and to selected intermediate propagate outputs for producing a second subtraction result (B-A); and means (22) responsive to the carry-out bit for selecting one of the first or second subtraction results as the subtraction result of the sign/magnitude subtraction operation. A system in accordance with claim 1, wherein the propagate-generate means comprises a plurality of propagate-generate computation stages (10,11,12) for producing the propagate and generate outputs, a first one of the said stages producing the intermediate propagate outputs. A system in accordance with claim 2, wherein the first carry generate means (13) comprises a plurality of first carry generate computation stages. A system in accordance with claim 2 or 3, wherein the second carry generate means (18) comprises a plurality of second carry generate computation stages. A system in accordance with claim 2, 3 or 4, wherein the intermediate propagate output is from the first computation stage (10) of the plurality of propagate-generate stages. A system in accordance with any preceding claim, wherein the means for producing the first and second subtraction results each include a plurality of exclusive-OR gates (17,21).

Inventors: GELINAS ROBERT G, RADOGNA THOMAS V, GELINAS, ROBERT G., RADOGNA, THOMAS V.
Applicants: DATA GENERAL CORP, DATA GENERAL CORPORATION
Application year: 1989
Main classification: G06F7
IPC codes: G06F7, G06F5