Standard cells with flip-flops

Abstract: The invention relates to standard cells in which the accurate estimation of the clock routing length and the minimization of the clock routing are possible so that an optimal protection against the malfunctions due to the racing can be schemed. The standard cells includes flip-flop circuits (F/F) collectively arranged in a region (12) of the substrate (10); and clock routing (11) for the flip-flop circuits (F/F) with connections (L) connecting the clock routing (11) and each of the flip-flop circuits (F/F) at shortest distance.

Description: The present invention relates to standard cell layouts and semi-custom LSIs which include flip-flop circuits. A known standard cell layout comprises: a substrate on which circuits are to be arranged; standard cells comprising flip-flop circuits arranged on the substrate to constitute a group of at least three flip-flop circuits for common clocking; other standard cells arranged on the substrate; and clock wiring for the flip-flop circuits with connections connecting the clock wiring and each of the flip-flop circuits. In designing the placement and routing of certain types of logic circuits in standard cells, care must be taken to avoid possible malfunctions. In particular, when the standard cells involves flip-flops, consideration must be given to avoiding malfunctions due to so-called clock-skew and racing. First, clock-skew will be explained with references to Figs. 1 and 2. In a shift register shown in Fig. 1, a clock signal CLK1 for a first flip-flop FF1 and a clock signal CLK2 for a second flip-flop FF2 have, as shown in Fig. 2, a phase difference called skew due to the presence of routing resistance R and routing capacitance C in a clock routing CLK between the first and second flip-flops FF1 and FF2. The appearance of such a skew in clock signal is called clock-skew. Since the longer routing makes more delay of a transmission of a clock signal between two flip flops, it is desirable for the flip-flops to have routing for clock signal as short as possible. Next. racing will be explained with further reference to Figs. 3. 4. and 5. Again, in the shift register of Fig. 1. when there is a large clock-skew while there is only a short routing between an output terminal Q of the first flip-flop FF1 and an input terminal D of the second flip-flop FF2. a switching of data at the input terminal D of the second flip-flop FF2 will occur before a switching of the clock at a point h, because a delay of data in going from the first flip-flop FF1 to the second flip-flop FF2 will be smaller than a delay of clock signal due to the clock-skew. As a result. as shown in Fig. 3, while a clock at a point g switches when data in a routing d is a₁ so that the first flip-flop FF1 receives data a₁, a corresponding clock at a point h switches so much later that data in a routing e has already switched from a₀ to a₁ by the time a clock at a point h switches, so that the second flip-flop FF2 also receives the same data a₁ at the same timing, causing an erroneously premature output of data a₁ in a routing f. This phenomenon is called racing. Conventionally, racing is avoided by providing an extra delay X between the output terminal Q of the first flip-flop FF1 and the input terminal D of the second flip-flop FF2, as shown in Fig. 4, such that the data delay is suitably elongated to be compatible with the clock delay due to the clock-skew, so as to achieve correct timing as shown in Fig. 5 in which the output in the routing f is correctly a₀. Although this method of preventing racing by means of an extra delay between two flip-flops is very common, there is a tendency to use an unnecessarily long delay time for such an extra delay, as a safety measure for the general situation where the length of the clock routing which determines an amount of clock-skew is not known precisely before the cell placing and routing. Furthermore, when another logic circuit such as a combinational circuit is to be connected between two flip-flops in addition to the delay, an actual operation time will be limited not only by the time for clock-skew and the delay time but also by an access time of the combinational circuit, so that a severe limitation is posed on how much can be done in a single clock cycle. In such a case, the unnecessary delay time taken by the delay can be a serious obstacle to improvement. Thus, it is desirable on one hand to be able to estimate the length of the clock routing accurately so that just the appropriate delay time can be selected. and on the other hand to make the clock routing as short as possible so that the clock-skew can be minimized. However, as shown in Fig. 6, a conventional standard cell layout has numbers of flip-flops F/F scattered in numbers of lines R so that the clock routings l₁, l₂, l₃, l₄, and l₅ become long and complicated, and neither an accurate estimation of the clock routing length nor minimization of the clock routing has been possible. It is therefore an object of the present invention to provide standard cells in which an accurate estimation of the clock routing length and minimization of the clock routing are possible so that improved protection against malfunctions due to the racing can be achieved. According to the present invention there is provided a layout of standard cells as initially defined, characterized in that: all said standard cells comprising flip-flop circuits of said group are collectively arranged in a first region of the substrate; the other standard cells are arranged in a second region of the substrate; and said connections each take the shortest path from said clock wiring to the associated flip-flop circuit. The features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a conventional shift register for explaining the phenomena of clock-skew and racing ; Fig. 2 is a timing chart for clock signals in the conventional shift register of Fig. 1 for explaining the phenomenon of clock-skew; Fig. 3 is a timing chart for clock signals and data signals for the flip-flops of the conventional shift register of Fig. 1 for explaining the phenomenon of racing; Fig. 4 is a circuit diagram of a conventional shift register with protection against the racing; Fig. 5 is a timing chart for clock signals and data signals for the flip-flops of the conventional shift register with protection against the racing of Fig. 4 for explaining the effect of its protection; Fig. 6 is an example of a schematic circuit diagram of a conventional standard cells for explaining its problems; Fig. 7 is a schematic circuit diagram of one embodiment of standard cells according to the present invention; and Fig. 8 is a schematic circuit diagram of another embodiment of standard cells according to the present invention. Referring now to Fig. 7, there is shown one embodiment of standard cell layout according to the present invention. In this embodiment, standard cells formed on an LSI substrate 10 are arranged such that all cells comprising flip-flops F/F are positioned collectively, one adjacent to another, all on a single cell line to form a flip-flop area 12 which has an associated clock routing area 11 located nearby, along the flip-flop area 12, while other logic circuits are arranged in the remaining logic circuit areas 13 with other routing areas 14. As shown in Fig. 7, numbers of connections l₁, l₂, -- , l n are provided to connect each of the flip-flops cells F/F with the clock routing area 11 in shortest distances. Thus, the clock routing in this embodiment is minimized so that the amount of clock-skew is minimized. Moreover, in this embodiment, the clock routings are arranged in very ordered and simple geometrical manner and, in particular, all the connections l₁, l₂, -- , l n have the same length. All of these features significantly contribute to the fact that in this embodiment the clock routing length can accurately be estimated. Thus, from the resistance and capacitance of the clock routing and the estimated clock routing length, it is possible to select an appropriate delay to be incorporated for an optimal protection against the racing. Referring now to Fig. 8 there is shown another embodiment of standard cells according to the present invention. In this embodiment, the previous embodiment is modified such that the flip-flops F/F are arranged not on a single cell line but on two cell lines. However, the same care to arrange the flip-flops F/F collectively in one specific region of the LSI substrate 10 has also been taken. The connections l₁, l₂, -- ,l i for an upper cell line for the flip-flops F/F and the connections l i+1 , -- , l n for a lower cell line for the flip-flops separately have the same advantageous features of the connections l₁, l₂, -- ,l n of the previous embodiment. Clearly, the similar effects and advantages of the previous embodiment can be achieved by this embodiment. It is obvious that further modification of the last embodiment in similar manner in which more number of cell lines for the flip-flops are used with the care to arrange the flip-flops F/F collectively in one specific region of the LSI substrate 10 is equally possible. It is further to be noted that in the above embodiments, the clock routing may be incorporated within the flip-flop area 12, without providing a separate clock routing area 11. Besides these, many modifications and variations of the above embodiments may be made without departing from the novel and advantageous features of the present invention. Accordingly, all such modifications and variations are intended to be included within the scope of the appended claims.

Claims: Layout of standard cells, comprising: a substrate (10) on which circuits are to be arranged; standard cells comprising flip-flop circuits (FF) arranged on the substrate to constitute a group of at least three flip-flop circuits for common clocking; other standard cells arranged on the substrate; and clock wiring (11) for the flip-flop circuits (FF) with connections (l₁, l₂, l₃ ...) connecting the clock wiring and each of the flip-flop circuits (FF), characterized in that: all said standard cells comprising flip-flop circuits (FF) of said group are collectively arranged in a first region (12) of the substrate (10); the other standard cells are arranged in a second region (13) of the substrate (10); and said connections (l₁, l₂, l₃ ...) each take the shortest path from said clock wiring (11) to the associated flip-flop circuit (FF). A standard cell layout according to claim 1, wherein the first region (12) comprises a single cell line. A standard cell layout according to claim 2, wherein the standard cells comprising flip-flop circuits are arranged to be adjacent to each other on the cell line. A standard cell layout according to claim 2 or 3 wherein the clock wiring (11) is routed along the cell line. A standard cell layout according to claim 4, wherein all the connections between the clock wiring (11) and the flip-flop circuits have the same length. A standard cell layout according to any preceding claim wherein the clock wiring (11) is included within the first region (12). A standard cell layout according to any preceding claim, comprising a further group of at least three flip-flop circuits for common clocking, all said flip-flop circuits of said further group being collectively arranged in a second region of the substrate.

Inventors: KUDO TSUNEAKI, SASAKI TOHRU, TOKUMARU TAKEJI, KUDO, TSUNEAKI, SASAKI, TOHRU, TOKUMARU, TAKEJI
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1989
Main classification: G11C5
IPC codes: H01L21, H01L23, G11C5, H03K19, H01L27, G11C11