Semiconductor memory device

Abstract: In a semiconductor memory device, an output of a sense amplifier circuit and a reference voltage of a reference voltage producing circuit are compared to decide whether a content of a selected memory cell is "1"or "0". A load characteristic of a load circuit of the reference voltage producing circuit is different from that of the sense amplifier circuit, so that current flowing through a reference field effect transistor can be increased to a level of current flowing through a memory cell in which"0" is stored. Therefore, a time in which an output voltage of the reference voltage producing circuit is lowered from a voltage set at the stand-by mode to the reference voltage set at the reading mode is shortened at the reading mode subsequent to the stand-by mode.

Description: FIELD OF THE INVENTION The invention relates to a semiconductor memory device according to the preamble part of claim 1 and as e.g. known from EP-A-0 238 812. BACKGROUND OF THE INVENTION One type of a conventional EE-PROM mainly comprises memory cells arranged in a matrix pattern, a sense amplifier circuit for producing a signal dependent on the content of a memory cell selected from the matrix memory cells, a reference voltage producing circuit for producing a reference signal, and a differential amplifier for comparing the signal dependent on the content of the selected memory cell and the reference signal and amplifying a compared difference between the signals. In operation of the reading mode, a reading voltage is applied to a gate electrode of a transistor for the selected memory cell. Then, the transistor is turned on where the memory cell has been programmed, while the transistor is turned off where the memory cell has been erased. As a result, a voltage V ON which is lower than the reference signal is supplied from the sense amplifier circuit in the former state, while a voltage V OFF which is higher than the reference signal is supplied from the sense amplifier circuit in the latter state. Consequently, a signal "L" is supplied from the differential amplifier in the former state, while a signal "H" is supplied therefrom in the latter state. Accordingly, stored information can be read from the selected memory cell. The construction and operation of the conventional EE-PROM will be described in detail latter. According to the conventional EE-PROM, however, there is a disadvantage that a speed of reading a content of a selected memory cell is not so fast as expected for the reason why the time in which a reference signal level is set to be a reference value is difficult to be shortened. The reasons thereof will be explained in more detail later. SUMMARY OF THE INVENTION Accordingly, it is an object of the invention to provide a semiconductor memory device in which a speed of reading a content of a memory cell selected from the matrix memory cells can be fast without inviting a complicated circuit structure. This object of the invention is solved by means of the features of the characterizing part of claim 1. Further features are shown by the subclaims. In the semiconductor memory device, a load characteristic of a load circuit of the reference voltage producing circuit is different from that of the sense amplifier circuit, so that a level of current flowing through a reference IGFET in the reference voltage producing circuit is set to the same extent as current flowing through a memory cell storing "0" therein. For this circuit structure, the time in which an output voltage of the reference voltage producing circuit is lowered from a voltage (V CC -V TP ) set at the stand-by mode to a reference voltage V REF set at the reading mode is shortened at the reading mode subsequent to the stand-by mode as compared to that of the conventional semiconductor memory device. Therefore, an operation speed of the semiconductor memory device is determined by the intrinsic operation speed of the sense amplifier circuit independently of an operation speed of the reference voltage producing circuit. BRIEF DESCRIPTION OF DRAWING S The invention will be explained in more detail in conjunction with appended drawings wherein, Fig. 1 is a circuit diagram showing a conventional semiconductor memory device, Fig. 2 is an explanatory diagram showing a load characteristic of a sense amplifier circuit and a reference voltage producing circuit in the conventional semiconductor memory device. Fig. 3 is an explanatory diagram showing waveforms of signals in the conventional semiconductor memory device, Fig. 4 is a circuit diagram showing a semiconductor memory device in a first embodiment according to the invention, Fig. 5 is an explanatory diagram showing load characteristies of a sense amplifier circuit and a reference voltage producing circuit in the semiconductor memory device in the first embodiment Fig. 6 is an explanatory diagram showing waveforms of signals in the semiconductor memory device in the first embodiment, and Fig. 7 is a circuit diagram showing a semiconductor memory device in a second embodiment according to the invention. DESCRIPTION OF PREFERRED EMIBODIMENTS Before explaining a semiconductor memory device in an embodiment according to the invention, the aforementioned conventional semiconductor memory which is an electrically erasable PROM (EE-PROM) will be explained in conjunction with Figs. 1 to 3. In Fig. 1, a part of the EE-PROM which operates in the reading mode is shown, while circuits for controlling the writing mode and the erasing mode are not shown. In the EE-PROM, Y₁ denotes an output signal line of a Y decoder circuit provided in a chip (not shown), X₁...X n output signal lines of an X decoder circuit provided in the chip, CG a signal line for applying a reading voltage to read information from one of memory cells in the chip, and RD a control signal line which is controlled, such that the control signal line RD is "L" in the reading mode, and the control signal line RD is "H" in the stand-by mode. Although memory cells are disposed in the column and row directions so as to form a matrix in an actual EE-PROM, only two memory cells M M11 and M Mn1 belonging to a row Y₁ are shown in Fig. 1. For simplification of the explanation, it is assumed that Y₁ is selected as being a Y address line for selecting a column direction, while X₁ is selected as being an X address line for selecting a row direction. When a memory cell has been programmed, the threshold value of this memory cell is negative and, when a reading voltage is applied to the gate, the memory cell turns conductive, which is defined as "0". On the other hand, when a memory cell has been erased, the threshold value of this memory cell is positive and, when a reading voltage is applied to the gate, the memory cell turns non-conductive, which is defined as "1". M S11 ...M Sn1 denote N-channel enhancement type IGFETs (hereinafter referred to as "NE-IGFETs") for selecting the X addresses of memory cells, and the NE-IGFETs are connected in series to the respective memory levels. Q YS1 is an NE-IGFET for selecting the Y address of a memory cell, while Q YT1 is an NE-IGFET for selecting the Y address of a byte, and M T1 ...M Tn are NE-IGFETs for selecting the X addresses of bytes which are provided in one-to-one correspondence with the bytes. SS is connected to the source of the memory cells and is set at "0" in the reading mode. I M denotes current flowing through a memory cell stored with "0". In a sense amplifier circuit 100, Q S1 , Q S3 and Q S4 are P-channel enhancement type IGFETs (hereinafter referred to as "PE-IGFETs"). Q S2 , Q S5 , Q S6 and Q S7 are NE-IGFETs. Q S1 to Q S6 , Q YS1 and M S11 constitute in combination a load with respect to the memory cell M M11 . The voltage V SA of the output SA of the sense amplifier circuit 100, when a memory cell stored with "0" is selected, is based on a load characteristic determined by these IGFETs and the value of the current IM flowing through the memory cell. Further, Q S2 is defined as a first FET, and Q S1 a second FET, while a first inverted amplifier is provided as indicated therein. In a reference voltage producing circuit 200 Q R111 , Q R3 and Q R4 are PE-IGFETs, while Q R2 , Q R5 , Q R6 , Q R7 , Q D1 and Q D2 are NE-IGFETs, and Q D13 an N-channel depletion type IGFET. Q R111 , Q R2 to Q R6 , Q D1 and Q D2 constitute in combination a load with respect to the reference IGFET Q D13 . The voltage V RA1 of the output RA₁ of the reference voltage producing circuit 200 is based on a load characteristic determined by these IGFETs and the value of the current I R1 flowing through Q D13 . Further, Q D13 is defined as a third FET, and Q R2 a fourth FET, while a second inverted amplifier is provided as indicated therein. In the reference voltage producing circuit 200 Q R111 , Q R2 , Q R3 , Q R4 , Q R5 , Q D1 and Q D2 are designed, such that the gate length and gate width of these transistors are the same as those of the IGFETs Q S1 , Q S2 , Q S3 , Q S4 , Q S5 , Q S6 , Q YS1 and M S11 which determine in combination a load characteristic of the sense amplifier circuit 100. Therefore, the load characteristic of the reference voltage producing circuit 200 are the same as that of the sense amplifier circuit 100. Further, C R collectively denotes a capacitance (including an aluminum wiring capacitance, input capacitances of comparators other than a differential amplifier to be explained, etc.) which is loaded on the output RA₁ of the reference voltage producing circuit 200. 300 denotes a differential amplifier which makes a comparison between an output voltage V SA of the sense amplifier circuit 100 which changes in accordance with whether a selected memory cell is stored with "0" or "1" and a reference voltage V RA1 of the reference voltage producing circuit 200 and amplifies the difference therebetween. When it is detected that "0" is stored in the selected memory cell, "H" is produced as the output D O , while when it is detected that "1" is stored therein, "L" is produced as the output D O . Finally, 400 denotes an output buffer circuit which serves to transmit the output D O of the differential amplifier 300 to an external terminal 500. Fig. 2 shows the change in the voltage V SA of the output SA of the sense amplifier circuit 100 in accordance with the change of the current flowing through M M11 in a case where M M11 is stored with "0", and the change in the voltage V RA1 of the output RA₁ of the reference voltage producing circuit 200 in accordance with the change of current flowing through the reference IGFET Q D13 . As described above, since the reference voltage producing circuit 200 is designed, such that the load characteristic of the load circuit are same as that of the load circuit in the sense amplifier circuit 100, the characteristics of the voltages V SA and V RA1 are represented by the same curve L1 shown in Fig. 2. In operation, a power supply voltage V CC is applied to Q S1 , Q S3 , Q R111 and Q R3 , RD is set to be "0", and a reading voltage CG is applied to Q YT1 . Here, it is assumed that all the NE-IGFETs have the same threshold value V TN and all the PE-IGFETs have the same threshold value V TP . When a memory cell stored with "0" is selected, current of the current value I M flows through this memory cell. In consequence, the voltages at the digit line SD and the node SC lower, while the voltage at the node SI rises, thereby causing Q S2 called the first FET to turn conductive. Thus, the voltage at the node SA moves from [V CC -V TP ] along the load curve L₁ and reaches equilibrium at the point P₁ as shown in Fig. 2. At this time, the same current as I M flows through Q S2 . The voltage V SA at the node SA is an output voltage of the sense amplifier circuit 100 when a memory cell stored with "0" is selected, and the value of this output voltage is hereinafter referred to as V ON . On the other hand, when a memory cell stored with "1" is selected, this memory cell turns non-conductive. In consequence, the voltages at the digit line SD and the node SC rise, while the voltage at the node SI lowers, thereby causing Q S2 to turn non-conductive. Thus, the voltage V SA at the node SA reaches equilibrium at the point S₁ . At this time, the voltage V SA at the node SA is [V CC -V TP ], and the value of this output voltage is hereinafter referred to as V OFF . Thus, the reference voltage V REF1 is set approximately a median between V ON and V OFF , so that the differential amplifier 300 can accurately detect whether a selected memory cell is stored with "1" or "0". The load circuit of the sense amplifier circuit 100 and the load circuit of the reference voltage producing circuit 200 are designed, such that the value of [V OFF -V REF1 ] and the value of [V REF1 -V ON ] are not lower than a minimum voltage V MIN which can be detected by the differential amplifier 300. In this point, the current I R1 flowing through the reference IGFET Q D13 is set to be 3/8I M , so that the reference voltage V REF1 is set at a median between V ON and V OFF (the point R1) as shown in Fig. 2. The operation will be further explained with reference to Fig. 3. When the device is in the stand-by mode, RD is "H", and Q S7 , Q R7 , Q S6 and Q R6 are conductive, while Q S3 and Q R3 are non-conductive. In consequence, the nodes SC, RC, SI and RI are all "L", and both Q S2 and Q R2 are non-conductive, so that the output SA of the sense amplifier circuit 100 and the output RA₁ of the reference voltage producing circuit 200 are raised in accordance with the charge thereof to a voltage [V CC -V TP ]. In addition, the output D O of the difference amplifier 300 is raised in accordance with the charge thereof to the voltage V CC (although not shown). When RD changes from "H" and "L" and the operation mode is changed from the stand-by mode to the reading mode, Q S3 and Q S4 turn conductive, so that the node SI changes from "L" to "H". Simultaneously, address signals X₁ and Y₁ become high. In consequence, Q S2 turns conductive and the charge accumulated at the node SA is rapidly discharged. As a result, the voltage V SA at the node SA lowers linearly as shown in Fig. 3. If it is assumed that a memory cell which is selected at this time has "1" stored therein, the nodes SC and SD are charged again. As a result, the voltage at the node SC rises, while the voltage at the node SI lowers. In consequence, Q S2 turns non-conductive and the voltage V SA at the node SA rises again and reaches equilibrium at [V CC -V TP ] (the curve SA OFF ). If the selected memory cell has "0" stored therein, the nodes SA and SC which have been overdischarged are charged to the equilibrium voltage. As a result, the voltage V SA at the node SA reaches equilibrium at V ON (the curve SA ON ). In the reference voltage producing circuit 200, when RD changes from "H" to "L", Q R3 and Q R4 turn conductive and the node RI changes from "L" to "H", thereby causing Q R2 to turn conductive. In consequence, the charge accumulated in the capacitor C R formed between the node RA₁ and the ground is gradually discharged in accordance with the current I R1 flowing through Q D13 . As a result, the voltage V RA1 at the node RA₁ changes from [V CC -V TP ] to a set value V REF1 with a time constant, as shown in Fig. 3. The reason why the voltage waveform V RA1 at the node RA₁ does not rapidly lower to "L" as compared to the voltage waveform V SA at the node SA, when the operation mode is changed from the stand-by mode to the reading mode, is that the capacitance which is produced on the digit line SD is much larger than the capacitance which is produced on the nodes RC and RD in the reference voltage producing circuit 200. Therefore, when Q S2 turns conductive, the charge accumulated at the node SA rapidly moves to the digit line SD. On the other hand, in the reference voltage producing circuit 200, since the capacitance produced on the node RA₁ is larger than the capacitance produced on the nodes RC and RD, when the operation mode is changed from the stand-by mode to the reading mode, the time td₁ in which the voltage V RA1 at the node RA₁ changes from [V CC -V TP ] to the set value V REF1 is simply determined in accordance with capacitor C R formed between the node RA₁ and the ground, and the current I R1 flowing through the reference IGFET Q D13 . The time td₁ is expressed in the equation (1). td₁=C R ·ΔV/I R1 where ΔV=(V CC -V TP )-V REF1 For example, if the device is designed, such that the current I R1 of 10µA flows through the reference IGFET Q D13 , the time td₁ of 200 ns is obtained, under the conditions that the current I M is 25µA, the capacitance C R is 2PF, and the voltage difference ΔV is 1 V when the output voltage V RA1 lowers from [V CC -V TP ] to [V CC -V TP - V MIN ], the output D O of the differential amplifier 300 changes from "H" to "L". Thus, the content of a selected memory cell can be read out. Therefore, the minimum time after which the content of a selected memory cell can be read out practically depends on the lowering speed of the voltage V RA1 , and is expressed by t DO1 in Fig. 3. The time t D O 1 is considerably longer than the time t S O needed for the output V SA of the sense amplifier circuit 100 to equilibrate with the set values of V OFF and V ON . Consequently, the content of a selected memory cell is read out in accordance with the comparison in the differential amplifier 300 between the output voltage V SA of the sense amplifier circuit 100 and the output voltage V RA1 , which will be V REF1 in the lapse of the time t d1 , of the reference voltage producing circuit 200. Then, an output of the differential amplifier 300 is supplied through the output buffer 400 to the output terminal 500. Next, a semiconductor memory device in the first embodiment according to the invention will be explained in Fig. 4. The semiconductor memory device comprises memory cells M M11 .... M Mn1 (only two bits of one column shown) arranged in a matrix pattern, NE-IGFETs M S11 ... M Sn1 for selecting X addresses of the memory cells M M11 ...M Mn1 , NE-IGFETs M T1 ...M Tn for selecting X addresses of a byte, a sense amplifier circuit 100 for producing a signal of a level dependent on the content of a selected memory cell, a reference voltage producing circuit 200 for producing a reference signal, a differential amplifier 300 for comparing the memory cell signal and the reference voltage signal and amplifying a compared difference between the both signals, and a output buffer 400 for supplying an output of the differential amplifier 300 to an output terminal 500. As understood from the comparison between the circuit diagrams of Figs. 1 and 4, wherein like parts are indicated by like reference numerals and symbols, arrangement and operation of the semiconductor memory device in the invention are common to those of the conventional semiconductor memory device except for those of the reference voltage producing circuit 200. In the reference signal producing circuit 200, Q R11 , Q R12 and Q R13 are PE-IGFETs having the same device dimension as that of Q S1 . Q D3 is an N-channel depletion type IGFET through which a current I R of a low value flows in the reading mode. The voltage V RA of the output RA is determined by a load characteristic of a load circuit for Q D3 and the value of the current I R flowing through Q D3 . The load circuit for Q D3 comprises Q R11 , Q R12 and Q R13 which have the same device dimension as that of Q S1 are connected in parallel to provide a characteristic modifying circuit 210. Therefore, the load characteristic of the reference voltage producing circuit 200 is different from that of the sense amplifier circuit 100. Fig. 5 shows the load characteristics L₁ and L₂ of the sense amplifier circuit 100 and the reference voltage producing circuit 200, wherein the current I R is approximately equal to the current I M . More specifically, the current driving capacity of the characteristic modifying circuit 210 comprising Q R11 , Q R12 and Q R13 can be large than that of the corresponding IGFET Q S1 in the sense amplifier circuit 100. Therefore, the value of the output voltage V RA can be set at the reference voltage V REF of a median between V OFF and V ON , despite that the current I R is approximately equal to the current I M . That is, the voltage V RA of the node RA reaches equilibrium at Q1 shown in Fig. 5, and therefore becomes equal to the reference voltage V REF . Fig. 6 shows waveforms of the output voltage V SA of the sense amplifier circuit 100, the output voltage V RA of the reference voltage producing circuit 200, the output signal D O of the differential amplifier 300, the control signal RD of the reading mode, and address signals X₁ and Y₁. In operation, the voltage V RA of the output RA of the reference voltage producing circuit 200 is raised in accordance with the charge thereof to [V CC -V TP ] in the stand-by mode. When RD changes from "H" to "L" at the time of t CE , Q R3 and Q R4 turn conductive and the node RI changes from "L" to "H", thereby causing Q R2 to turn conductive. In consequence, the charge accumulated in the capacitor C R formed between the node RA and the ground is gradually discharged in accordance with the current I R flowing through Q D3 . As a result, the voltage V RA at the node RA changes from [V CC -V TP ] to the set value V REF with a time constant, as shown in Fig. 6. The time td in which the voltage V RA lowers down to the set value V REF is expressed in the equation (2). t d =C R ·ΔV/I R where ΔV=(V CC -V TP )-V REF From the equation (2), the time t d of 80ns is obtained, where Q D3 is designed to have a device dimension, such that the current I R is 25µA which is equal to the current I M under the condition that the capacitance C R is 2PF, and the voltage difference Δ V is 1 V. Accordingly, the reading speed is much higher than that of the conventional semiconductor memory device. That is, the time t D O in which the voltage difference between the voltage V OFF and the voltage V RA becomes the mimmum voltage V MIN , thereby enabling the differential amplifier 300 to operate, is shortened. In the lapse of the time t D O , the output D O of the differential amplifier 300 changes from "H" to "L", so that the content of a selected memory cell can be read therefrom. Fig. 7 shows a semiconductor memory device in the second embodiment according to the invention, wherein like parts are indicated by like reference numerals and symbols as explained in Fig. 4. In the sense amplifier circuit 100 of the semiconductor memory device, Q S21 is an NE-IGFET which is connected at the drain and gate thereof to a power supply CC. In the reference voltage producing circuit 200, Q R21 , Q R22 and Q R23 are NE-IGFETs having the same device dimension as that of Q S21 . The voltage V RA2 of the output RA₂ is determined by the load characteristic of a load circuit for Q D3 and the value of the current I R flowing through Q D3 . The load circuit comprises Q R21 , Q R22 , Q R23 , Q R2 to Q R7 , Q D1 and Q D2 . IGFETs Q R21 , Q R22 and Q R23 having the same device dimension as that of Q S21 are connected in parallel. Therefore, the load characteristic of the reference voltage producing circuit 200 is different from that of the sense amplifier circuit 100. Far this purpose, the device dimension of Q S21 , Q R21 , Q R22 and Q R23 is appropriately determined, such that a load characteristic of the sense amplifier circuit 100 and a load characteristic of the reference voltage producing circuit 200 are set as represented by the curves L₁ and L₂, respectively, of Fig. 5. Accordingly, the value of the output voltage V RA2 can be set at the reference voltage V REF which is a median between the voltages V OFF and V ON in a state that the current I R is approxinately equal to the current I M in the same way as in the first embodiment. Therefore, the semiconductor memory device of the second embodiment provides the same advantage as described in the first embodiment. As a matter of course, the sense amplifier circuit 100 and the reference voltage producing circuit 200 operate in the same manner as in the first embodiment, provided that [V CC -V TP ] is replaced by [V CC -V TN ], wherein V TP is a threshold value of PE- IGFET, and V TN is that of NE-IGFET. As described above, a semiconductor memory device according to the present invention is arranged, such that the reference voltage is set at a median between the output voltage V ON of the sense amplifier circuit 100, where a memory cell is stored with "0", and the output voltage V OFF of the sense amplifier circuit 100, where a memory cell is stored with "1", in the circuit structure that a load characteristic of a load circuit in the reference voltage producing circuit 200 is different from that of a load circuit in the sense amplifier circuit 100. Therefore, a current value of a constant current source of the reference voltage producing circuit 200 can be set to be greater as compared to that of a conventional semiconductor memory device and to be substantially equal to a value of a current flowing through a selected memory cell which is stored with "0". Accordingly, the following advantages are resulted therefrom. (1) When the operation mode is changed from the stand-by mode to the reading mode, the time in which the reference voltage equilibrates with a set value is shorter than in the conventional semiconductor memory device. Therefore, the invention is applied to a semiconductor memory device of a large capacity and a high speed. (2) Even if noise is carried on a power supply or the ground due to current flowing through IGFETs during the switching thereof thereby deviating a reference voltage from a set value, charge and discharge for the reference voltage is carried out in the reference voltage producing circuit 200 faster than in that of the conventional semiconductor memory device, so that the reference voltage can be restored to the set value at a higher speed than in the conventional semiconductor memory device. Accordingly, a semiconductor memory device having a large noise margin can be provided. Although a characteristic modifying circuit provided in a reference voltage producing circuit in the embodiments of the invention is a parallel circuit comprising three transistors of the same type as a second field effect transistor provided in a sense amplifier circuit, the number of field effect transistors used therein is not necessarily limited to three. The circuit may have a plurality of field effect transistors of a type a described above and connected in parallel.

Claims: A semiconductor memory device comprising, a sense amplifier circuit (100) for detecting a content of a memory cell (Mm11) selected from a plural of memory cells and producing a memory cell signal (VSA) of high or low level, whereby said sense amplifier circuit includes means for setting said memory cell signal (VSA) at a first predetermined voltage (V OFF ; V CC -V TP ) at the stand-by mode, and means for lowering said first predetermined voltage to a second predetermined voltage and then increasing said second predetermined voltage to said memory cell signal of said high or low level in accordance with a first load characteristic thereof at the reading mode subsequent to said stand-by mode, a reference voltage circuit (200) for producing a reference voltage (V RA1 ; V RA ) having a reference voltage level (V REF1 ; V REF ) lying between said memory cell signals of said high or low level comprising a load circuit (210) with a second load characteristic and a series circuit of serial connected IGFETS (Q R2 , Q D1 , Q D2 , Q D3 ) and producing said reference voltage (V RA1 ; V RA ) at the connection node (RA) between the load circuit and the series circuit, and means (300) for comparing said memory cell signal and said reference voltage to decide whether that content is "1" or "0", characterized in that said reference voltage circuit (200) includes means for setting said reference voltage (V RA ) at a third predetermined voltage equal to said first predetermined voltage (V CC -V TP ) at the stand-by mode, means for lowering said third predetermined voltage to said reference voltage level (VREF) at the reading mode subsequent to said stand-by mode, and an N-channel depletion type IGFET transistor (Q D3 ) being part of said series circuit for supplying a reference current (I R ). A semiconductor memory device according to claim 1, wherein said means for lowering of said reference voltage producing circuit (200) provides a voltage drop equal to a median of the voltage difference between said high and low levels of said memory cell signal in accordance with said first and second load characteristics, and currents of the same level flowing through said means for lowering of said sense amplifier circuit and said reference voltage producing circuit (200). A semiconductor memory device according to claims 1 or 2 wherein, said sense amplifier circuit (100) includes a first inverted amplifier (Q S3 -Q S7 ) having an input connected to a digit line of said memory cell, a first field effect transistor (Q S2 ) having a gate electrode connected to an output of said first inverted amplifier, a source electrode connected to said digit line and a drain delivering said memory cell signal (V SA ), and a second field effect transistor (Q S1 ) positioned between a power supply and a drain electrode of said first field effect transistor (Q S2 ) and controlled to be constantly turned on in accordance with a gate potential, said reference voltage producing circuit (200) including a third field effect transistor (Q D3 ) having a drain electrode connected to a predetermined node (RD) therein and a source electrode connected to the ground, a second inverted amplifier (Q R3 - Q R7 ) having an input connected to said predetermined node and the same input and output characteristics as those of said first inverted amplifier, a fourth field effect transistor (Q R2 ) having a gate electrode connected to an output of said second inverted amplifier, a source electrode connected to said predetermined node (RD), a drain delivering said reference voltage (V RA ) and the same device dimension as that of said first field effect transistor (Q S2 ), said load circuit (210) being composed of plural field effect transistors (Q R11 -Q R13 ) connected in parallel and positioned between a power supply and the drain electrode of said fourth field effect transistor (Q R2 ), each of said plural field effect transistors (Q R11 - Q R13 ) having the same dimension as that of said second field effect transistor (Q S1 ).

Inventors: HASHIMOTO KIYOKAZU, HASHIMOTO, KIYOKAZU
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: G11C7
IPC codes: G11C16, G11C17, H01L27, G11C7, H01L29, H01L21