Method of driving ferroelectric liquid crystal display panel

Abstract: In a method of driving a ferroelectric liquid crystal display panel, a non-selection voltage B is continuously applied to a scanning electrode L i from the time at which the selection voltage A is applied to the scanning voltage L i to the time at which the selection voltage A is again applied to the scanning electrode L₁, and a succeeding erasing voltage H is applied to the scanning electrode L i at the time N x t₀ before the application of the selection voltage A, whereby approximately the same effect as realized by the application of voltage -V g for P x t₀ can be provided on a pixel A ij , no matter whether a bright voltage D or a dark voltage E is applied to a signal electrode S j , so that the pixel A ij can be set to the dark memory state. At the time Q x t₀ before the application of the succeeding erasing voltage H to the scanning electrode L i , a compensation voltage G is applied, so that driving with no DC component left on the pixel A ij can be realized.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method of driving a ferroelectric liquid crystal displaying panel. More specifically, the present invention relates to a method of driving a ferroelectric liquid crystal displaying panel having a plurality of scanning electrodes arranged parallel to each other, signal electrodes arranged parallel to each other intersecting the plurality of scanning electrodes and ferroelectric liquid crystal sealed between each of the scanning electrodes and each of the signal electrodes. Description of the Background Art Fig. 6 is a cross sectional view of a conventional simple matrix panel sealing ferroelectric liquid crystal. Referring to Fig. 6, two deflecting plates 1 are provided at the top and bottom, arranged in the relation of crossed nicols with each other. A glass 2 is provided on the deflecting plate 1, and on which glass 2 the scanning electrode 3 or the signal electrode 4 is formed. An insulating film 5 is formed over the scanning electrodes 3 and the signal electrodes 4 to protect the ferroelectric liquid crystal 8. An aligning film 6 is provided on the insulating film 5 which is subjected to a process such as rubbing so as to align the molecules of the ferroelectric liquid crystal 8. Sealing member 7 is provided for preventing the ferroelectric crystal liquid in the cell from leaking outward. Fig. 7 shows the structure of the electrodes in the simple matrix panel sealing ferroelectric crystal liquid shown in Fig. 6. The example shown in Fig. 7 is a simple matrix panel comprising 4 scanning electrodes 3 and 4 signal electrodes 4, which will be referred to as a 4 x 4 simple matrix panel (the former numeral indicating the number of the scanning electrodes 3 and the latter numeral indicating the number of the signal electrodes 4). The scanning electrodes 3 are labeled as L₁, L₂, L₃ and L₄ respectively, from the uppermost one, and the signal electrodes are labeled, from the left side, as S₁, S₂, S₃ and S₄, respectively. The intersection of the scanning electrode L i and the signal electrode S j is represented as a pixel A ij (i and j are positive integer). Fig. 8 shows a 16 x 16 simple matrix panel displaying a letter " ". Fig. 9 is a diagram of voltage waveforms applied to the scanning electrodes when the panel of Fig. 8 is driven. Fig. 10 is a diagram of voltage waveforms applied to the signal electrodes 4 for driving the panel shown in Fig. 8. Figs. 11A and 11B are diagrams of voltage waveforms applied to the pixels when the panel shown in Fig. 8 is driven. The operation for driving the panel shown in Fig. 8 in accordance with the conventional method of driving will be described in the following. The voltage shown in Fig. 9 is applied to the scanning electrode L i by the scanning driver 10, and the voltage shown in Fig. 10 is applied to the signal electrode S j by the signal driver 9. Then, the voltages such as shown in Figs. 11A and 11B are applied to the pixel A ij , so that the pixel A ij is set in a bright or dark memory state, thereby displaying the character " ". The ferroelectric liquid crystal has two memory states, one of which is referred to as the dark memory state while the other is referred to as the bright memory state. In the following, the bright memory state and the dark memory state maybe changed with each other. More specifically, as to the scanning electrodes L i , during the time period -t₀ to 0, the voltage C (the voltage V₀, and then the voltage -V₀) is applied to the scanning electrodes L₁ to L₄ as shown in Fig. 9 (a) to (d), while the voltage G (voltage -2V₀/3, and then the voltage 2V₀/3) is applied to the scanning electrodes L₅ to L₉ as shown in Fig. 9 (e) to (h). During the time period 0 to t₀, the voltage A (voltage -V₀ and then voltage V₀) is applied to the scanning electrode L₁ and the voltage B (voltage 2V₀/3 and then the voltage -2V₀/3) is applied to the remaining scanning electrodes. During the time t₀ to 2t₀, the voltage A is applied to the scanning electrode L₂ and the voltage B is applied to the remaining scanning electrodes. During the time period 2t₀ to 3t₀, the voltage A is applied to the scanning electrode L₃ and the voltage B is applied to the remaining scanning electrodes. During the time period 3t₀ to 4t₀, the voltage A is applied to the scanning electrode L₄ and the voltage B is applied to the remaining scanning electrodes. Then, during the time 4t₀ to 5t₀, the voltage C is applied to the scanning electrodes L₅ to L₈ and the voltage G is applied to the scanning electrode L₉ and L₁ to L₄. Thereafter, the similar operation is repeated. As to the signal electrodes S j , during the time period -t₀ to 0, the voltage F (voltage -V₀ and then voltage V₀) is applied to all the signal electrodes S j as shown in Fig. 10. During the time period 0 to 4t₀, the voltage D (voltage V₀ and then the voltage -V₀) or the voltage E (voltage V₀/3 and then voltage -V₀/3) is applied to each of the signal electrodes S j . During the time period 4t₀ to 5t₀, the voltage F is applied to all the signal electrodes S j . Thereafter, the same operation is repeated. By applying the voltages to the scanning electrodes L₁ to L₄ and L₅ to L₉ and to the signal electrodes S j in the above described manner, the voltages such as shown in Figs. 11A and 11B are applied to the pixels A ij . More specifically, the voltage applied to the pixel is equal to the voltage applied to the scanning electrode L i minus the voltage applied to the signal electrode S j . For example, the voltage shown in Fig. 11A (a) is applied to the pixel A₂₂. Namely, the voltage CF is applied to the pixels A 1j to A 4j including the pixel A₂₂ during the time period -t₀ to 0. By this voltage CF, the voltage 2V₀ and then -2V₀ are applied to the pixels including the pixel A₂₂, which are set in the dark memory state. The ferroelectric liquid crystal sealed in this panel has a nature to be set in the dark memory state when the voltage -2V₀ is applied for t₀/2. When the voltage A is supplied to the scanning electrode L₂ and the voltage E is applied to the signal electrode S₂ during the time period t₀ to 2t₀, then the voltage AE is applied to the pixel A₂₂, keeping the dark memory state. The ferroelectric liquid crystal sealed in this panel has a nature that it is not set to the bright memory state even if the voltage 4V₀/3 is applied for t₀/2. The voltage shown in Fig. 11A (d) is applied to the pixel A 2c . Namely, the voltage CF is applied to the pixels A 1j to A 4j including the pixel A 2c during the time -t₀ to 0. By the voltage CF, the voltage 2V₀ and then -2V₀ are applied to the pixels including the pixel A 2c , so that these pixels are set to the dark memory state. If the voltage A is applied to the scanning electrode L₂ and the voltage D is applied to the signal electrode S c during t₀ to 2t₀, then the voltage AD is applied, so that the bright memory state is realized. The ferroelectric liquid crystal introduced in this panel has a nature that it is set to the bright memory state when the voltage 2V₀ is applied for t₀/2. The pixels A₂₂ and A 2c rewritten in this manner are kept in the bright or dark memory state until the voltage CF is applied the next time as shown in Fig. 11A (a) and (d). Since the example shown in Fig. 8 is a 16 x 16 simple matrix panel, the erasing voltage C and the non-selection voltage G are applied to a set of scanning electrodes 3, each set including 4 scanning electrodes 3. Generally, the erasing voltage C and the non-selection voltage G are applied to a set of scanning electrodes 3, each set including 2 to 16 electrodes. When we represent the minimum panel time width necessary for rewriting the memory state of a ferroelectric liquid crystal with a certain applied voltage as t m (sec), then the time T a necessary for rewriting all pixels in the M x N simple matrix panel will be as follows, when the erasing voltage C and the non-selection voltage G are applied to a set of scanning electrodes 3 including 16 electrodes. With a minimum integer K satisfying the condition of K ≧ M ÷ 16 the time Ta will be T a = (M + K) x 2 t m (sec) Assuming that M is a multiple of 16, then, T a = (17M ÷ 16) x 2t m (sec) Consequently, the scanning time per 1 scanning electrode provided by dividing the above value by the number of scanning electrodes m is about 2.1 x t m (sec). Fig. 12 is a block diagram for the display of output signal of a conventional personal computer. Fig. 13 is a diagram of waveforms showing the output signal of the personal computer and the input signal of the signal driver showing in Fig. 12. By using the above described method of driving, the scanning time per scanning electrode can be made considerably close to 2t m (sec). However, a timing converting circuit 12 must be provided between the personal computer 11 and the control circuit 13 shown in Fig. 12. The reason for this is that although the output signal from the personal computer 11 is continues to the signal for the scanning electrodes L₁, L₂, L₃, L₄, L₅, L₆ and so on as shown in Fig. 13 (a), the actual signal to be applied to the signal driver 9 must include a signal corresponding to the timing of applying the voltage F to the signal electrode S j as shown in Fig. 13 (b). Therefore, the timing of the output signals of the personal computer 11 must be converted, so that they can be applied to the signal driver 9. See also GB-A-2 175 725. SUMMARY OF THE INVENTION Therefore, one object of the present invention is to provide a method of driving a ferroelectric liquid crystal displaying panel in a relatively simple manner without providing a timing converting circuit. Briefly stated, in the present invention, the liquid crystal displaying panel comprises a plurality of scanning electrodes arranged parallel to each other, signal electrodes arranged parallel to each other intersecting the plurality of scanning electrodes, and ferroelectric liquid crystal sealed between the plurality of scanning electrodes and the plurality of signal electrodes. A compensation voltage G is applied followed by a succeeding erasing voltage H to the scanning electrode L i (i is a positive integer) corresponding to a pixel to be displayed out of the plurality of scanning electrodes, and thereafter a selecting voltage A is applied thereto, a bright voltage D is applied to a signal electrode corresponding to the pixel to be displayed, so that the corresponding pixel is turned on. Therefore, in accordance with the present invention, the scanning time t₀ per scanning electrode can be set twice the pulse width t m necessary for rewriting the memory state of the ferroelectric liquid crystal without providing the timing converting circuit as in the prior art. In accordance with a preferred embodiment of the present invention, the compensation voltage G is a voltage which becomes negative for a prescribed time period, the succeeding erasing voltage H is a voltage which becomes positive for a prescribed time period, the selection voltage A is, in a former half of the predetermined time period, a negative voltage which is approximately equal to the succeeding erasing voltage H and, in the latter half of the period, a positive voltage which is approximately equal to the compensation voltage G, the bright voltage D is, in the former half of the predetermined period, a positive voltage which is approximately the same as the selection voltage A in the latter half of the period, and in the latter half of the period, it is selected to be a negative voltage which is approximately equal to the selection voltage A in the former half of the period. In a more preferred embodiment, a dark voltage E is applied to the signal electrode corresponding to the pixel to be displayed, so that the corresponding pixel is set in the off state. The dark voltage E is selected to be, in the former half of the prescribed period, a positive voltage lower than the bright voltage D in the former half of the period, and in the latter half, it is selected to be a negative voltage higher than the bright voltage D. In a more preferred embodiment, the non-selection voltage B is applied to the scanning electrodes corresponding to the pixels which are not to be displayed, so that these pixels are set to the non-selected state. The non-selection voltage B is selected to be, in the former half in the predetermined time period, a positive voltage lower than the selection voltage A in the latter half and higher than the dark voltage E in the former half, and in the latter half of the period, a negative voltage higher than the selection voltage A in the former half and lower than the dark voltage E in the latter half. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram of voltage waveforms illustrating the principle of the present invention; Fig. 2 is a schematic block diagram of one embodiment of the present invention; Fig. 3 is a diagram of voltage waveforms applied to scanning electrodes in driving the liquid crystal display panel shown in Fig. 8; Fig. 4 is a diagram of voltage waveforms applied to signal electrodes in driving the panel shown in Fig. 8; Figs. 5A and 5B are diagrams of voltage waveforms applied to pixels in driving the liquid crystal display panel shown in Fig. 8; Fig. 6 is a cross sectional view of a conventional simple matrix panel sealing ferroelectric liquid crystal; Fig. 7 shows an electrode structure of the simple matrix panel sealing the ferroelectric liquid crystal shown in Fig. 6; Fig. 8 shows an example of a display of a letter "A" on a 16 x 16 matrix panel; Fig. 9 is a diagram of voltage waveforms applied to the scanning electrodes when the liquid crystal display panel shown in Fig. 8 is driven in a conventional manner; Fig. 10 is a diagram of voltage waveforms applied to the signal electrodes when the liquid crystal display panel of Fig. 8 is driven in the conventional manner; Figs. 11A and 11B are diagrams of voltage waveforms applied to the pixels when the panel shown in Fig. 8 is driven in the conventional manner; Fig. 12 is a schematic block diagram of a conventional apparatus for displaying output signals from a personal computer; and Fig. 13 shows output signals from the personal computer and the input signals of the signal driver shown in Fig. 12. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 is a diagram of waveforms illustrating the principle of the present invention. Referring to Fig. 1, the principle of the present invention will be described. Before the selection voltage A is applied to the scanning electrode L i (i is a positive integer), the compensation voltage G is applied followed by the succeeding erasing voltage H. More specifically, from the time 0 to t₀, a selection voltage A having the waveform as shown in Fig. 1 (1), that is, -V a in the former half of a predetermined time period and Va in the latter half of the period, is applied to the scanning electrode L i . A non-selection voltage B having such a waveform as shown in Fig. 1 (2), that is, the voltage V b in the former half of the period and -V b in the latter half of the period, or a compensation voltage G having such waveform as shown in Fig. 1 (3), that is, V g in the predetermined period, or a succeeding erasing voltage H having such a waveform as shown in Fig. 1 (4), that is, -V g in the prescribed time period, is applied to other scanning electrodes L k (k ≠ i). When a bright voltage D having the waveform as shown in Fig. 1 (5), that is, V d in the former half of the period and -V d in latter half of the period,is applied to the signal electrode S j , then the pixel A ij corresponding to the scanning electrode L i is set to the bright memory state. When the dark voltage E having the waveform of Fig. 1 (6), that is, V e in the former half of the period and -V e and in the latter half of the period is applied, then the memory state of the pixel A ij corresponding to the scanning electrode L i is kept as it is. At the time P x t₀ (P= 1, 2...) before the application of the selection voltage A, the succeeding erasing voltage H is applied to the scanning electrode L i . When the bright voltage D is applied to the signal electrode S j at this time, then the voltage -V g - V d is applied in the former half of the period and the voltage -V g + V d is applied in the latter half of the period to the pixel A ij , as shown in Fig. 1 (g). If the dark voltage E shown in Fig. 1 (6) is applied to the signal electrode S j at this time, then the voltage -V g - V e is applied in the former half of the period and the voltage -V g + V e is applied in the latter half of the period to the pixel A ij as shown in Fig. 1 (h). Therefore, by determining the value of the voltage V g such that -V g + V d ≦ 0 and -V g + V e ≦ 0, then the pixel A ij can be kept in the dark memory state, since it is approximately the same as the application of the voltage -V g for the time P x t₀ to the pixel A ij no matter whether the bright voltage D is applied or the dark voltage E is applied to the signal electrode S j . In addition, at the time Q x t₀ (Q= 1, 2...) before the application of the succeeding erasing voltage H to the scanning electrode L i , the compensation voltage G is applied. If the bright voltage D is applied to the signal electrode S j at this time, then, the voltage V g - V d is applied followed by the voltage V g + V d to the pixel A ij as shown in Fig. 1 (e). When the dark voltage E is applied to the signal electrode S j at this time, then the voltage V g - V e is applied followed by the voltage V g + V e to the pixel A ij as shown in Fig. 1 (f). Namely, no matter whether the bright voltage D is applied or the dark voltage E is applied to the electrode S j , an average voltage of V g is applied for the time Q x t₀ to the pixel A ij . Therefore, by applying the succeeding erasing voltage H to the scanning electrode L i and by applying the compensation voltage G to the signal electrode S j , the voltage time product V g x P x t₀ applied to the pixel A ij is cancelled, realizing driving with no DC component left therein. The voltage -V a is applied in the former half and the voltage V a is applied in the latter half as the selection voltage A, the voltage V b is applied in the former half and the voltage -V b is applied in the latter half as the non-selection voltage B, the voltage V g is applied as the compensation voltage G and the voltage -V g is applied as the succeeding erasing voltage H, the voltage V d is applied in the former half and the voltage -V d is applied in the latter half as the bright voltage D and the voltage V e is applied in the former half and the voltage -V e is applied in the latter half as the dark voltage E. However, the same effect can be obtained provided that the same voltage waveform is applied to the pixel A ij , even if the voltage V z or the like is commonly added to the respective voltages. Fig. 2 is a block diagram showing one embodiment of the present invention. In this embodiment, provided are a personal computer 11, a control circuit 13, a signal driver 9 and a scanning driver 10. The timing converting circuit 12 shown in Fig. 11 is omitted. In this embodiment also, the simple matrix panel shown in Fig. 8 is driven. Fig. 3 is a diagram of voltage waveforms applied to the scanning electrodes when the panel shown in Fig. 8 is driven. Fig. 4 is a diagram of voltage waveforms applied to the signal electrodes. Figs. 5A and 5B are diagrams of voltage waveforms applied to the pixels. A driving method of one embodiment of the present invention will be described in the following. As shown in Fig. 3 (a) to (d), from the time 0 to t₀, the selection voltage A (voltage -V₀ and then voltage V₀) is applied to the scanning electrode L₁; the succeeding erasing voltage H (voltage -V₀) is applied to the scanning electrode L₂; the compensation voltage G (voltage V₀) is applied to the scanning electrode L₃; and the non-selection voltage B (voltage 2V₀/3 and then voltage -2V₀/3) is applied to the scanning electrodes L₄ to L₉. Then, from the time t₀ to 2t₀, the selection voltage A is applied to the scanning electrode L₂, the succeeding erasing voltage H is applied to the scanning electrode L₃, the compensation voltage G is applied to the scanning electrode L₄, and the non-selection voltage B is applied to the scanning electrodes L₅ to L₉ and to L₁. While the scanning electrodes L₁ to L₉ are scanned in this manner, the dark voltage E (voltage V₀/3 and then voltage -V₀/3) or the bright voltage D (voltage V₀ and then voltage -V₀) is applied to the signal electrode S j . In order to display the letter "A" as shown in Fig. 8, the voltages shown in Fig. 4 (a) to (e) are applied to the signal electrodes S₂, S₆, S b , S c and S d . Consequently, the voltages applied to the pixels A₂₂, A₂₆, A 2b , A 2c , A 2d , A 3b , A₃₂ and A₃₆ are as shown in Fig. 5A (a) to (d) and Fig. 5B (e) to (h). The pixel A₂₂, for example, is once set to the dark memory state by the difference voltage between the succeeding erasing voltage H and the dark voltage E or the bright voltage D, that is, HD or HE. The sealed ferroelectric liquid crystal is set to the dark memory state by the difference voltage HD as described with reference to the prior art. Approximately the same effect is provided by the difference voltage HE. In view of the variations of the characteristics of the cells, the succeeding erasing voltage H may be applied twice. The selection voltage A is applied from the time t₀ to 2t₀ to the scanning electrode L₂. When the pixel A 2j is to be set to the dark memory state on this occasion, then the dark voltage E must be applied to the signal electrode S j as shown in Fig. 4 (a) to (c). At this time, the difference voltage AE is applied to the pixel A 2j as shown in Fig. 5A (a) to (c). However, the memory state of the pixel A 2j is not changed, as shown in the prior art. If the pixel A 2j is to be set to the bright memory state, then the bright voltage D must be applied to the signal electrode S j as shown in Fig. 4 (d) and (e). On this occasion, the difference voltage AD is applied to the pixel A 2j as shown in Fig. 5A (d) and Fig. 5B (e) so that the pixel A 2j is changed to the bright memory state. In practice, CS - 1014 produced by CHISSO Corp. is sealed in the simple matrix panel as the ferroelectric liquid crystal and it is driven with V₀ = 16 (V) t₀ = 240 (µsec) As described above, in this embodiment of the present invention, a compensation voltage G and then the succeeding erasing voltage H are applied to the scanning electrode L₁ before the application of the selection voltage A, so that the scanning time t₀ (sec) per each scanning electrode can be set twice the time width t m (sec) of the pulse necessary for rewriting the memory state of the ferroelectric liquid crystal, without providing the timing conversion circuit as in the prior art. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A method of driving a liquid crystal display panel having a plurality of scanning electrodes (L i , i is a positive integer) arranged parallel to each other, a plurality of signal electrodes (S j , j is a positive integer) arranged parallel to each other and intersecting said plurality of said scanning electrodes, and ferroelectric liquid crystal (8) sealed between said plurality of scanning electrodes and the plurality of signal electrodes, comprising the steps of: applying a compensation voltage (G) followed by a succeeding erasing voltage (H) and thereafter applying a selection voltage (A) to a selected scanning electrode (L i ) corresponding to a pixel to be displayed out of said plurality of scanning electrodes; and applying a bright voltage (D) to a signal electrode corresponding to said pixel to be displayed; whereby the corresponding pixel is turned on. A method of driving a ferroelectric liquid crystal display panel according to claim 1, wherein said succeeding erasing voltage (H) has a pulse width of at least twice the duration of a pulse width of said selection voltage (A), such that by applying said succeeding erasing voltage (H) having the same magnitude as said selection voltage (A) to said scanning electrode (L i ) said corresponding pixel can be erased prior to applying said selection voltage (A) to said scanning electrode (L i ). A method of driving a ferroelectric liquid crystal display panel according to claim 1 or claim 2, wherein: said compensation voltage (G) comprises a voltage which becomes negative for a prescribed time period, said succeeding erasing voltage (H) comprises a voltage which becomes positive for said predetermined time period; said selection voltage (A) comprises, in the former half of said predetermined time period, a negative voltage approximately equal to the succeeding erasing voltage (H) and, in the latter half of said predetermined time period, a positive voltage approximately equal to said compensation voltage (G); and said bright voltage (D) comprises, in the former half of said predetermined time period, a positive voltage approximately equal to said selection voltage (A) in the latter half of the period, and in the latter half of the period, a negative voltage approximately equal to said selection voltage (A) in the former half of the period. A method of driving a ferroelectric liquid crystal display panel according to claim 3, further comprising the step of: applying a dark voltage (E) to the signal electrode corresponding to said pixel to be displayed, whereby the corresponding pixel is turned off. A method of driving a ferroelectric liquid crystal display panel according to claim 4, wherein: said dark voltage (E) comprises, the former half of said predetermined period, a positive voltage lower than said bright voltage (D) in the former half of the period, and, in the latter half of the period, a negative voltage higher than said bright voltage (D) in the latter half of the period. A method of driving a ferroelectric liquid crystal display panel according to claim 5, further comprising the step of: applying a non-selection voltage (B) to the scanning electrodes other than the selected scanning electrode. A method of driving a ferroelectric liquid crystal display panel according to claim 6, wherein: said non-selection voltage (B) comprises, in the former half of said predetermined period, a positive voltage lower than said selection voltage (A) in the latter half of the period and higher than said dark voltage (E) in the former half of the period, and in the latter half of the period, a negative voltage higher than said selection voltage (A) in the former half of the period and lower than said dark voltage (E) in the latter half of the period. Liquid crystal matrix display drive circuit in which an erasing voltage (H) applied to a scanning electrode prior to the selection thereof by a selection voltage (A) is preceded by a compensation voltage (G) applied to that scanning electrode. A drive circuit for driving a liquid crystal display panel by a method according to any one of claims 1 to 7.

Inventors: NUMAO TAKAJI, NUMAO, TAKAJI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1989
Main classification: G09G3
IPC codes: G09G3, G06F3, G02F1