Memory system and method of using same

Abstract: The number (S) of erase cycles in addressed blocks are counted and compared with a preset number. The addressed block is replaced if the preset number is reached. Furthermore, an intelligent erase algorithm is provided to get an increased life of the memory.

Description: This invention relates to a method of using a memory system and to a memory system having safety features. An electrically programmable read only memory (Eprom) utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over but insulated from a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but also insulated therefrom. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. The memory cell transistor's state is read by placing an operating voltage across its source and drain and on its control gate, and then detecting the level of current flowing between the source and drain as to whether the device is programmed to be "on" or "off" at the control gate voltage selected. A specific, single cell in a two-dimensional array of Eprom cells is addressed for reading by application of a source-drain voltage to source and drain lines in a column containing the cell being addressed, and application of a control gate voltage to the control gates in a row containing the cell being addressed. In addition to the floating and control gates, an erase gate is included. The erase gate passes through each memory cell transistor closely adjacent to a surface of the floating gate but insulated therefrom by a thin tunnel dielectric. Charge is then removed from the floating gate of a cell to the erase gate, when appropriate voltages are applied to all the transistor elements. An array of EEprom cells are generally referred to as a Flash EEprom array if an entire array of cells, or a significant group of cells, is erased simultaneously (i.e. in a flash). EEproms have been found to have a limited effective life. The number of cycles of programming and erasing that such a device can endure before becoming degraded is finite. After a number of such cycles in excess of 10,000, depending upon its specific structure, its programmability can be reduced. Often, by the time the device has been put through such a cycle for over 100,000 times, it can no longer be programmed or erased properly. This is believed to be the result of electrons being trapped in the dielectric each time charge is transferred to or away from the floating gate by programming or erasing, respectively. It is already known to use several EEproms in a momory system and have a separate EEprom for storing erasing and writing frequencies carried out by the center control unit ("Patent Abstracts of Japan", vol. 9. No. 217 (P-385), 4 September 1985 & JP-A-60 076097 (Ichida Denki)). It is also known to count programming and erasing cycles and to compare same with a predetermined number, and if so reached, to switch from one EEprom region (block) to another EEprom region (block) for further operation of the device (DE 35 17 087 A1). In a method or memory system according to the preamble of claims 1 and 7 ("Patent Abstracts of Japan", vol. 9, o. 16 (P-329), 23 January 1985 & JP-A-59 162695 (Toshio Ninomiya)) the erasing/writing cycles of the memory are stored in an area of the memory so that the user can know when the memory (EEprom) should be replaced. The number of cycles that an EEprom has undergone it rough standard for evaluating the remaining quality of an EEprom. From an article in "Alta Frequenza", vol. 52, no. 6, November 1983 - December 1983, Milano IT, pages 487,494, Torrelli, Lupi "An Improved Method for Programming a Word-Erasable EEprom", it is known to apply a series of modifying pulses instead of a continuous modifying voltage to the cell electrodes of an EEprom. The cell is read after each pulse. The time required for performing such method is a problem. The invention solves the problem of fully exploit the limited useful effective life of an EEprom. Furthermore, the number of program/erase cycles that an EEprom can indure is to be increased. The invention is defined in claims 1 and 7. An intelligent erase algorithm is provided which results in a significant reduction in the electrical stress experienced by the erase tunnel dielectric and results in much higher endurance to program/erase cycling and a resulting increased life of the memory. The objects, features and advantages of the present invention will be understood from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings. Fig. 1 is a cross section of an example split channel Eprom or EEprom, Fig. 2a is a schematic representation of the composite transistor forming a split channel Eprom device, Fig. 2b shows the programming and erase characteristics of a split channel Flash EEprom device, Fig. 2c shows the four condition states of a split channel flash EEprom device in accordance with this invention, Fig. 2d shows the program/erase cycling endurance characteristics of prior art Flash EEprom devices, Fig. 2e shows a circuit schematic and programming/read voltage pulses required to implement multistate storage, Fig. 3 outlines the key steps in the new algorithm used to erase with a minimum stress, Fig. 4 shows the program/erase cycling endurance characteristics of the split channel Flash EEprom device using intelligent algorithms for multistate programming and for reduced stress during erasing. Referring initially to Figure 1, the structure of a split-channel Eprom or EEprom cell is described that is suitable for use in the improved memory array and operation of the present invention. A semiconductor substrate 11 includes source region 13 and drain region 15, usually formed by ion implantation. Between the source and drain is a channel region 17. Over a portion of the channel region designated as L1 is a floating gate 19, separated from the substrate by a thin layer of gate oxide 21. Over a portion of the channel region designated as L2 is formed a control gate 23, separated from the substrate 11 by a thin gate oxide layer 25. The control gate 23 is also electrically isolated from the floating gate 19 by an oxide layer 27. It is the amount of electrical charge on the floating gate 19 that is programmed in accordance with the state desired to be stored in the cell. If the charge level is above some set threshold, the cell is considered to be in one state. If below that threshold, it is designated to be in its other state. The desired charge level is programmed by applying an appropriate combination of voltages to the source, drain, substrate and control gate, for a designated period of time, in order to cause electrons to move from the substrate 11 to the floating gate 19. The floating gate is confined to its one memory cell and is electrically isolated from all other parts of the structure. The control gate 23, on the other hand, extends across a large number of cells sharing a common word line. As described hereinafter, the split-channel has the effect of providing two field-effect-transistors in series, one with the floating gate 19 as its control gate and the other with the control gate 23 as its control gate. The generic split-channel Eprom or EEprom structure of Figure 1 becomes a Flash EEprom device when an erase gate (not shown) is added. The erase gate is a separate electrode positioned near a portion of the floating gate 27 and separated from it by a tunnel dielectric. When the proper voltages are applied to the source, drain, substrate, control gate and erase gate, the amount of charge on the floating gate is reduced. A single erase gate extends to a large number of memory cells, if not the entire array, so that they may be erased all at once. In some prior art Flash EEprom cells the source or drain diffusions underneath the floating gate are used also as the erase electrode, while in other cells the erase electrode is implemented either in the same conductive layer as the control gate or in a separate conductive layer. The split channel Flash EEprom device can be viewed as a composite transistor consisting of two transistors T1 and T2 in series - figure 2a. Transistor T1 is a floating gate transistor of effective channel length L1 and having a variable threshold voltage V T1 . Transistor T2 has a fixed (enhancement) threshold voltage V T2 and an effective channel length L2. The Eprom programming characteristics of the composite transistor are shown in curve (a) of figure 2b. The programmed threshold voltage V tx is plotted as a function of the time t during which the programming conditions are applied. These programming conditions typically are V CG = 12V, V D = 9V, V S = V BB = OV. No programming can occur if either one of V CG or V D is at OV. A virgin (unprogrammed, unerased) device has V T1 = +1.5V and V T2 = +1.0V. After programming for approximately 100 microseconds the device reaches a threshold voltage V tx ≥ +6.0 volts. This represents the off ("0") state because the composite device does not conduct at V CG = +5.0V. Prior art devices employ a so called "intelligent programming" algorithm whereby programming pulses are applied, each of typically 100 microseconds to 1 millisecond duration, followed by a sensing (read) operation. Pulses are applied until the device is sensed to be fully in the off state, and then one to three more programming pulses are applied to ensure solid programmability. Prior art split channel Flash EEprom devices erase with a single pulse of sufficient voltage V ERASE and sufficient duration to ensure that V T1 is erased to a voltage below V T2 (curve (b) in figure 2b). Although the floating gate transistor may continue to erase into depletion mode operation (line (c) in figure 2b), the presence of the series T2 transistor obscures this depletion threshold voltage. Therefore the erased on ("1") state is represented by the threshold voltage V tx = V T2 = +1.0V. The memory storage "window" is given by Δ V = V tx ("0") - V tx ("1") = 6.0-1.0=5.0V. However, the true memory storage window should be represented by the full swing of V tx for transistor T1. For example, if T1 is erased into depletion threshold voltage V T1 = -3.0V, then the-true window should be given by Δ V = 6.0 - (-3.0) = 9.0V. None of the prior art Flash EEprom devices take advantage of the true memory window. In fact they ignore altogether the region of device operation (hatched region D in figure 2b) where V T1 is more negative than V T2 . The memory system of this invention considers a scheme to take advantage of the full memory window. This is done by using the wider memory window to store more than two binary states and therefore more than a single bit per cell. For example, it is possible to store 4, rather than 2 states per cell, with these states having the following threshold voltage: State "3": - V T1 = -3.0V, V T2 = +1.0V (highest conduction) = 1, 1. State "2": - V T1 = -0.5V, V T2 = +1.0V (intermediate conduction) = 1, 0. State "1": - V T1 = +2.0V, V T2 = +1.0V (lower conduction) = 0, 1. State "0": - V T1 = +4.5V, V T2 = +1.0V (no conduction) = 0, 0. To sense any one of these four states, the control gate is raised to V CG = +5.0V and the source-drain current I DS is sensed through the composite device. Since V T2 = +1.OV for all four threshold states transistor T2 behaves simply as a series resistor. The conduction current I DS of the composite transistor for all 4 states is shown as a function of V CG in figure 2c. A current sensing amplifier is capable of easily distinguishing between these four conduction states. The maximum number of states which is realistically feasible is influenced by the noise sensitivity of the sense amplifier as well as by any charge loss which can be expected over time at elevated temperatures. Eight distinct conduction states are necessary for 3 bit storage per cell, and 16 distinct conduction states are required for 4 bit storage per cell. Multistate memory cells have previously been proposed in conjunction with ROM (Read Only Memory) devices and DRAM (Dynamic Random Access Memory). In ROM, each storage transistor can have one of several fixed conduction states by having different channel ion implant doses to establish more than two permanent threshold voltage states. Prior art multistate DRAM cells have also been proposed where each cell in the array is physically identical to all other cells. However, the charge stored at the capacitor of each cell may be quantized, resulting in several distinct read signal levels. To take full advantage of multistate storage in Eproms it is necessary that the programming algorithm allow programming of the device into any one of several conduction states. First it is required that the device be erased to a voltage V T1 more negative than the "3" state (-3.0V in this example). Then the device is programmed in a short programming pulse, typically one to ten microseconds in duration. Programming conditions are selected such that no single pulse can shift the device threshold by more than one half of the threshold voltage difference between two successive states. The device is then sensed by comparing its conduction current I DS with that of a reference current source I REF , i (i=0,1,2,3) corresponding to the desired conduction state (four distinct reference levels must be provided corresponding to the four states). Programming pulses are continued until the sensed current (solid lines in figure 2c) drops slightly below the reference current corresponding to the desired one of four states (dashed lines in figure 2c). To better illustrate this point, assume that each programming pulse raises V tx linearly by 200 millivolts, and assume further that the device was first erased to V T1 = -3.2V. Then the number of programming/sensing pulses required is: For state "3" (V T1 = -3.0V) No. of pulses = (3.2-3.0)/.2 = 1 For state "2" (V T1 = -0.5V) No. of pulses = (3.2-0.5)/.2 = 14 For state "1" (V T1 = +2.0V) No. of pulses = (3.2-(-2.0))/.2 = 26 and for state "0" (V T1 = +4.5V) No. of pulses = (3.2-(-4.5))/.2 = 39. In actual fact shifts in V tx are not linear in time, as shown in figure 2b (curve (a)), therefore requiring more pulses than indicated for states "1" and "0". If 2 microseconds is the programming pulse width and 0.1 microseconds is the time required for sensing, then the maximum time required to program the device into any of the 4 states is approximately 39x2 + 39x.1 = 81.9 microseconds. This is less than the time required by "intelligent programming algorithms" of prior art devices. In fact, with the new programming algorithm only carefully metered packets of electrons are injected during programming. A further benefit of this approach is that the sensing during reading is the same sensing as that during programming/sensing, and the same reference current sources are used in both programming and reading operations. That means that each and every memory cell in the array is read relative to the same reference level as used during program/sense. This provides excellent tracking even in very large memory arrays. Large memory systems typically incorporate error detection and correction schemes which can tolerate a small number of hard failures i.e. bad Flash EEprom cells. For this reason the programming/sensing cycling algorithm can be automatically halted after a certain maximum number of programming cycles has been applied even if the cell being programmed has not reached the desired threshold voltage state, indicating a faulty memory cell. There are several ways to implement the multistate storage concept in conjunction with an array of Flash EEprom transistors. An example of one such circuit is shown in figure 2e. In this circuit an array of memory cells has decoded word lines and decoded bit lines connected to the control gates and drains respectively of rows and columns of cells. Each bit line is normally precharged to a voltage of between 1.0 V and 2.0 V during the time between read, program or erase. For a four state storage, four sense amplifiers, each with its own distinct current reference levels IREF,0, IREF,1, IREF,2, and IREF,3 are attached to each decoded output of the bit line. During read, the current through the Flash EEprom transistor is compared simultaneously (i.e., in parallel) with these four reference levels (this operation can also be performed in four consecutive read cycles using a single sense amplifier with a different reference applied at each cycle, if the attendant additional time required for reading is not a concern). The data output is provided from the four sense amplifiers through four Di buffers (D0, D1, D2 and D3). During programming, the four data inputs Ii (I0, I1, I2 and I3) are presented to a comparator circuit which also has presented to it the four sense amp outputs for the accessed cell. If Di match Ii, then the cell is in the correct state and no programming is required. If however all four Di do not match all four Ii, then the comparator output activates a programming control circuit. This circuit in turn controls the bit line (VPBL) and word line (VPWL) programming pulse generators. A single short programming pulse is applied to both the selected word line and the selected bit line. This is followed by a second read cycle to determine if a match between Di and Ii has been established. This sequence is repeated through multiple programming/reading pulses and is stopped only when a match is established (or earlier if no match has been established but after a preset maximum number of pulses has been reached). The result of such multistate programming algorithim is that each cell is programmed into any one of the four conduction states in direct correlation with the reference conduction states I REF , i. In fact, the same sense amplifiers used during programming/reading pulsing are also used during sensing (i.e., during normal reading). This allows excellent tracking between the reference levels (dashed lines in figure 2c) and the programmed conduction levels (solid lines in figure 2c), across large memory arrays and also for a very wide range of operating temperatures. Furthermore, because only a carefully metered number of electrons is introduced onto the floating gate during programming or removed during erasing, the device experiences the minimum amount of endurance-related stress possible. In actual fact, although four reference levels and four sense amplifiers are used to program the cell into one of four distinct conduction states, only three sense amplifiers and three reference levels are required to sense the correct one of four stored states. For example, in figure 2c, I REF ("2") can differentiate correctly between conduction states "3" and "2", I REF ("1") can differentiate correctly between conduction states "2" and "1", and I REF ("0") can differentiate correctly between conduction states "1" and "0". In a practical implementation of the circuit of figure 2e the reference levels I REF , i (i=0,1,2) may be somewhat shifted by a fixed amount during sensing to place them closer to the midpoint between the corresponding lower and higher conduction states of the cell being sensed. Note that the same principle employed in the circuit of figure 2e can be used also with binary storage, or with storage of more than four states per cell. Of course, circuits other than the one shown in figure 2e are also possible. For example, voltage level sensing rather than conduction level sensing can be employed. In the example above,states "3" and "2" are the result of net positive charge (holes) on the floating gate while states "1" and "0" are the result of net negative charge (electrons) on the floating gate. To properly sense the correct conduction state during the lifetime of the device (which may be specified as 10 years at 125'C) it is necessary for this charge not to leak off the floating gate by more than the equivalent of approximately 200 millivolts shift in V T1 . This condition is readily met for stored electrons in this as well as all prior art Eprom and Flash EEprom devices. From device physics considerations, retention of holes trapped on the floating gate should be significantly superior to the retention of trapped electrons. This is so because trapped holes can only be neutralized by the injection of electrons onto the floating gate. So long as the conditions for such injection do not exist it is almost impossible for the holes to overcome the potential barrier of approximately 5.0 electronvolts at the silicon-silicon dioxide interface (compared to a 3.1 electron volts potential barrier for trapped electrons). Therefore it is possible to improve the retention of this device by assigning more of the conduction states to states which involve trapped holes. For example, in the example above state "1" had V T1 = +2.0V, which involved trapped electrons since V T1 for the virgin device was made to be V T1 = +1.5V. If however V T1 of the virgin device is raised to a higher threshold voltage, say to V T1 = +3.0V (e.g. by increasing the p-type doping concentration in the channel region 560a in figure 5a), then the same state "1" with V T1 = +2.0V will involve trapped holes, and will therefore better retain this value of V T1 . Of course it is also possible to set the reference levels so that most or all states will have values of V T1 which are lower than the V T1 of the virgin device. Intelligent Erase for Improved Endurance The endurance of Flash EEprom devices is their ability to withstand a given number of program/erase cycles. The physical phenomenon limiting the endurance of prior art Flash EEprom devices is trapping of electrons in the active dielectric films of the device. During programming the dielectric used during hot electron channel injection traps part of the injected electrons. During erasing the tunnel erase dielectric likewise traps some of the tunneled electrons. The trapped electrons oppose the applied electric field in subsequent write/erase cycles thereby causing a reduction in the threshold voltage shift of V tx . This can be seen in a gradual closure (figure 2d) in the voltage "window" between the "0" and "1" states. Beyond approximately 1x10 4 program/erase cycles the window closure can become sufficiently severe to cause the sensing circuitry to malfunction. If cycling is continued the device eventually experiences catastrophic failure due to a ruptured dielectric. This typically occurs at between 1x10 6 and 1x10 7 cycles, and is known as the intrinsic breakdown of the device. In memory arrays of prior art devices the window closure is what limits the practical endurance to approximately 1x10 4 cycles. At a given erase voltage, V ERASE , the time required to adequately erase the device can stretch out from 100 milliseconds initially (i.e. in a virgin device) to 10 seconds in a device which has been cycled through 1x10 4 cycles. In anticipation of such degradation prior art Flash EEprom devices specified to withstand 1x10 4 cycles must specify a sufficiently long erase pulse duration to allow proper erase after 1x10 4 cycles. However this also results in virgin devices being overerased and therefore being unnecessarily overstressed. A second problem with prior art devices is that during the erase pulse the tunnel dielectric may be exposed to an excessively high peak stress. This occurs in a device which has previously been programmed to state "0" (V T1 = +4.5V or higher). This device has a large negative charge Q. When V ERASE is applied the tunnel dielectric is momentarily exposed to a peak electric field with contributions from V ERASE as well as from Q. This peak field is eventually reduced when Q is reduced to zero as a consequence of the tunnel erase. Nevertheless, permanent and cumulative damage is inflicted through this erase procedure, which brings about premature device failure. To overcome the two problems of overstress and window closure a new erase algorithm is disclosed, which can also be applied equally well to any prior art Flash EEprom device. Without such new erase algorithm it would be difficult to have a multistate device since, from curve (b) in figure 2d, conduction states having V T1 more negative than V T2 may be eliminated after 1x10 4 to 1x10 5 write/erase cycles. Figure 3 outlines the main steps in the sequence of the new erase algorithm. Assume that a block array of mxn memory cells is to be fully erased (Flash erase) to state "3" (highest conductivity and lowest V T1 state). Certain parameters are established in conjunction with the erase algorithm. They are listed in figure 3: V 1 is the erase voltage of the first erase pulse. V 1 is lower by perhaps 5 volts from the erase voltage required to erase a virgin device to state "3" in a one second erase pulse. t is chosen to be approximately 1/10th of the time required to fully erase a virgin device to state "3". Typically, V 1 may be between 10 and 20 volts while t may be between 10 and 100 milliseconds. The algorithm assumes that a certain small number, X, of bad bits can be tolerated by the system (through for example error detection and correction schemes implemented at the system level. If no error detection and correction is implemented then X = 0). These would be bits which may have a shorted or leaky tunnel dielectric which prevents them from being erased even after a very long erase pulse. To avoid excessive erasing the total number of erase pulses in a complete block erase cycling can be limited to a preset number, n max . Δ V is the voltage by which each successive erase pulse is incremented. Typically, Δ V is in the range between 0.25V and 1.0V. For example, if V 1 =15.0V and Δ V=1.0V, then the seventh erase pulse will be of magnitude V ERASE =21.0V and duration t. A cell is considered to be fully erased when its read conductance is greater than I "3" . The number S of complete erase cyclings experienced by each block is an important information at the system level. If S is known for each block then a block can be replaced automatically with a new redundant block once S reaches 1x10 6 (or any other set number) of program/erase cycles. S is set at zero initially, and is incremented by one for each complete block erase multiple pulse cycle. The value of S at any one time can be stored by using for example twenty bits (2 20 equals approximately 1x10 6 ) in each block. That way each block carries its own endurance history. Alternatively the S value can be stored off chip as part of the system. The sequence for a complete erase cycle of the new algorithm is as follows (see figure 3): 1. Read S. This value can be stored in a register file. (This step can be omitted if S is not expected to approach the endurance limit during the operating lifetime of the device). 1a. Apply a first erase pulse with V ERASE =V 1 + n ΔV, n=0, pulse duration = t. This pulse (and the next few successive pulses) is. insufficient to fully erase all memory cells, but it serves to reduce the charge Q on programmed cells at a relatively low erase field stress, i.e., it is equivalent to a "conditioning" pulse. 1b. Read a sparse pattern of cells in the array. A diagonal read pattern for example will read m+n cells (rather than mxn cells for a complete read) and will have at least one cell from each row and one cell from each column in the array. The number N of cells not fully erased to state "3" is counted and compared with X. 1c. If N is greater than x (array not adequately erased) a second erase pulse is applied of magnitude greater by Δ V than the magnitude of the first pulse, with the same pulse duration, t. Read diagonal cells, count N. This cycling of erase pulse/read/increment erase pulse is continued until either N ≤ X or the number n of erase pulses exceed n max . The first one of these two conditions to occur leads to a final erase pulse. 2a. The final erase pulse is applied to assure that the array is solidly and fully erased. The magnitude of V ERASE can be the same as in the previous pulse or higher by another increment Δ V. The duration can be between 1t and 5t. 2b. 100% of the array is read. The number N of cells not fully erased is counted. If N is less than or equal to X, then the erase pulsing is completed at this point. 2c. If N is greater than X, then address locations of the N unerased bits are generated, possibly for substitution with redundant good bits at the system level. If N is significantly larger than X (for example, if N represents perhaps 5% of the total number of cells), then a flag may be raised, to indicate to the user that the array may have reached its endurance end of life. 2d. Erase pulsing is ended. 3a. S is incremented by one and the new S is stored for future reference. This step is optional. The new S can be stored either by writing it into the newly erased block or off chip in a separate register file. 3b. The erase cycle is ended. The complete cycle is expected to be completed with between 10 to 20 erase pulses and to last a total of approximately one second. The new algorithm has the following advantages: (a) No cell in the array experiences the peak electric field stress. By the time V ERASE is incremented to a relatively high voltage any charge Q on the floating gates has already been removed in previous lower voltage erase pulses. (b) The total erase time is significantly shorter than the fixed V ERASE pulse of the prior art. Virgin devices see the minimum pulse duration necessary to erase. Devices which have undergone more than 1x10 4 cycles require only several more Δ V voltage increments to overcome dielectric trapped charge, which only adds several hundred milliseconds to their total erase time. (c) The window closure on the erase side (curve (b) in figure 2d) is avoided indefinitely (until the device experiences failure by a catastrophic breakdown) because V ERASE is simply incremented until the device is erased properly to state "3". Thus, the new erase algorithm preserves the full memory window. Figure 4 shows the four conduction states of the Flash EEprom devices of this invention as a function of the number of program/erase cycles. Since all four states are always accomplished by programming or erasing to fixed reference conduction states, there is no window closure for any of these states at least until 1x10 6 cycles. In a Flash EEprom memory chip it is possible to implement efficiently the new erase algorithm by providing on chip (or alternatively on a separate controller chip) a voltage multiplier to provide the necessary voltage V1 and voltage increments Δ V to n Δ V, timing circuitry to time the erase and sense pulse duration, counting circuitry to count N and compare it with the stored value for X, registers to store address locations of bad bits, and control and sequencing circuitry, including the instruction set to execute the erase sequence outlined above. While the embodiments of this invention that have been described are the preferred implementations, those skilled in the art will understand that variations thereof may also be possible. Therefore, the invention is entitled to protection within the full scope of the appended claims.

Claims: A method of using a memory system comprising an array of electrically erasable and programmable read only memory cells arranged in a plurality of addressable blocks whose cells are individually erasable together, wherein at lease one of the blocks is a redundant block, comprising the steps of maintaining a count of the number of times that the individual blocks have been subjected to an erase cycle, and substituting for another of the blocks whose erase cycles count has reached a predetermined number, characterized by the steps of storing the erase cycle count (S) within memory cells of the individual blocks to which they pertain, prior to erasing a block, reading the cycle count (S) that is stored in the block and temporarily storing that count in a register, updating the cycle count read from the block to reflect the occurrence of another erase cycle, erasing the block and then writing the updated cycle count back into the block. The method of claim 1 wherein said set number of counts (S) is an endurance limit of said addressed block. The method of claim 1 or 2 wherein when said number of counts (S) has been reached for an addressed block, said block is replaced with a new redundant block. The method of any of claims 1 to 3 wherein each cell has a field effect transistor with a natural threshold voltage that is alterable by controlling the level of charge on the floating gate, comprising the steps of: pulsing the cells of the addressed block for a predetermined time (t) and voltage (V 1 ) sufficient to alter the threshold voltage, but insufficient to completely erase said cells, thereafter reading the current through the addressed cells in order to ascertain the altered threshold levels, and repeating the pulsing and reading steps a plurality of times, each repeat of pulsing step increasing the voltage an increment (ΔV) above that of the last pulsing step. The method of claim 4 wherein the repeating, pulsing and reading steps are terminated upon the first occurrence of anyone of the following conditions: the threshold level of each of the addressed cells has reached an erased state, or a predetermined number (n max ) of erased pulses has been applied, or a predetermined maximum voltage of the erase pulses has been reached, or the number (N) of the addressed cells which remain not fully erased has declined below a predetermined acceptable number (X) of not fully erased cells. The method of claim 5 wherein, when the number (N) of addressed cells not fully erased is significantly larger than the predetermined acceptable number (X), the endurance limit of the addressed block of cells is indicated by a flag. A memory comprising: an electrically erasable and programmable read only memory which includes an array of electrically erasable and programmable read only memory cells, arranged in a plurality of addressable blocks whose cells are individually erasable together, wherein at least one of the blocks is a redundant block, means for programming the memory state of said cells, means for reading the memory state of said memory cells, means for maintaining a count of the number of times that the individual blocks have been subjected to an erase cycle (S), means for substituting the redundant block for another of the blocks whose erase cycle count has reached a predetermined number, characterised in that cycle count reading means is connected to a register for temporarily storing the cycle count, means for updating the cycle count in the register is provided, and in that said maintaining means is a part of said memory cells in said addressed block, and means is provided for writing back the updated cycle count into said maintaining means. The memory system of claim 7 wherein said counting and storing means is an endurance limit indicating means for the addressed block. The memory system of claim 7 or 8 further including redundant blocks for being handled by said replacing means. The memory system of any of claims 7 to 9 wherein each said cell includes a transistor with source and drain connections, an erase electrode and a floating gate and defines at least two threshold levels, wherein means for pulsing an addressed block for predetermined erase time (t) and/or voltage levels (V erase ) is provided, said reading means being adapted to read the current through the addressed block so as to ascertain any altered threshold level after each occurring pulse, said pulsing means being adapted to increase the erase time (t) and/or voltage level (V erase ) by an increment (ΔV), and wherein control means to terminate the operation of the pulsing means is provided. The memory system of claim 10 wherein said erasing means operates to repeat erase cycles only until the first occurrence of anyone of the following conditions: (1) the threshold level of each of the addressed cells has reached the base level of the respective cell for a fully erased state; or (2) a predetermined number (S) of erase pulses has been applied; or (3) a predetermined maximum voltage of the erase pulse has been reached; or (4) the number (N) of the addressed cells which remain not fully erased has declined below a predetermined acceptable number (X) of cells which are not fully erased.

Inventors: SANDISK CORP, HARARI, ELIYAHOU, SANDISK CORPORATION
Applicants: SANDISK CORP, SANDISK CORPORATION
Application year: 1989
Main classification: G11C11
IPC codes: G11C16, G11C11, H01L27, G11C29