Error correction circuit

Abstract: Reed-Solomon outer code for error correction concatenated with a CRC inner code for detection of miscorrections. The error correction circuit has a parallel circuit of an RS coding sequence circuit 23 and a CRC coding sequence circuit 22 to form a sequence circuit and a control circuit 24 for selecting either one of them depending on the desired operation mode. High speed decoding is obtained since the CRC computation is carried out in parallel with the Reed-Solomon decoding operation.

Description: Background of the Invention The present invention relates generally to error correction circuits for recording media by error correction in Reed Solomon (RS) codes and error detection in cyclic redundancy codes (CRCs) and, more particularly, to an error correction circuit with high speed CRC computation capability. In digital audio disks (DADs), digital audio tapes (DATs), and optical disks, m bits of information are handled as a single symbol, and RS codes, in which t symbols are correctable for 2t redundancy symbols and m = 8, are used. In optical disks, RS codes for correcting 8 symbols are used in contrast to other recording media where RS codes for correcting 2 or 3 symbols are used. One way to correct 8 symbols at high speeds is to perform a repeated operation, such as Euclid or Berlekamp algorithm, with a Galois field operation circuit such as shown in Yoshida et al. "A Study of Decoding RS Codes with Galois Operation Unit" The 9th Information Theory and its Application Symposium, pp, 167-170 (1986) and in EP-A- 0 034 142. A conventional error correction circuit, such as shown by Yoshida et al. "Error Correction Unit for Optical Disks" Sho 61 Shin So Zen Tai, 6-53 (1987) , is shown in FIG. 3. In order to handle long codes, sequence circuits for performing syndrome computation of RS codes from the received data are paralleled to find an error location. This error correction circuit includes a buffer memory 1 for storing a plurality of interleaved data streams which includes RS codes (external codes) and CRS (internal codes); an interface 2 for untying the interleaving in the buffer memory 1; a Galois field operation circuit 3 for performing the four rules of arithmetic in the Galois field based on a syndrome of each RS code; and a sequence circuit 4 for performing not only computation of the syndrome of a RS code from each data block but also parallel operations of the Chien search from the results of the four rules of arithmetic operation. These components are connected via data buses. A control circuit 5 controls the interface 2, the Galois operation circuit 3, and the sequence circuit 4. A CRC coding sequence circuit, which is fabricated on a separate chip from the sequence circuit 4 and described hereinafter, is connected to the control circuit 5. The data streams having CRCs as internal codes and RS codes are external codes are highly error detectable and has low probabilities of wrong correction in the loss correction in RS codes. The interleaved structure of these codes is highly resistant to burst errors. CRCs are a sort of cyclic codes aiming at error detection, and RS codes also are as useful for error detection as CRCs. RS codes are also used for 5 1/4″ write-once-read-may (WORM) optical disks and about to be standardized. See ISO/TC 97/SC23, Proposal for ISO, first ISO DP9171/4, July 1987. FIG. 4 shows an example of the standard format of 512 bytes per sector. For the RS codes used herein, the primitive polynomial p(X) is p(X) = X⁸ + X⁵ + X³ + X² + 1 and the generator polynomial G(X) is wherein α i = (β i )⁸⁸ and β is an element of the primitive polynomial p(X). For the CRCs, the primitive polynomial is the same as p(X) and the generator polynomial g(X) is In the format of FIG. 4, an RS check symbol is provided at the end of each of code words #0-#4. The generation of a CRC check symbol in the CRC coding sequence circuit is described below. First of all, I(X) is determined from data using the following Eq. (4) wherein L is the number of interleaves, n the code length, d is the minimum distance in RS codes, and i j,k the information symbol. If i ≧ L - 4, then i j,0 = 0. For 512 bytes per sector, L = 5, n = 122, d = 17. Hence, the CRC check symbol C(X) with respect to I(X) is C(X)=I(X)X⁴+Re[I(X)X⁴/g(X)] =I(X)⁴+a₃X³+a₂X²+a₁X+a₀ wherein Re[A/B] is the excess polynomial of A/B and a k (k = 0-3) the CRC check symbol. The check symbol a k of Eq. (5) can be determined with a simple circuit if I(X) is given. FIG. 5 shows such a CRC coding sequence circuit which includes an input terminal 6, an output terminal 7 for CRC check symbols a₀-a₄, a control signal input terminal 8 connected to the control circuit 5, four 8-bit registers 9-12, four OR circuits 13-16 each connected to the output of each register, four α M multiplication circuits 17-20, wherein M is 40, 117, 228, and 97 in Eq. (3), each connected to the input of each register, and an AND gate 21 for feeding each multiplication circuit 17-20 with a logical product of an output of the OR circuit 16 and a control signal from the control signal input terminal 8. In operation, when a reset signal is applied to the registers 9-12 via the control signal input terminal 8 to clear the contents of each register and I(X) is fed to the input terminal 6 in the order of degree, the symbol of I(X) is logically added to the output of the register 12 in the OR circuit 16 and fed to the multiplication circuits 17-20 via the AND gate 21. The data multiplied by α⁴⁰ in the multiplication circuit 17 is latched in the register 9 with the timing signal inputted via the control signal input terminal 8. The data multiplied by α¹¹⁷ in the multiplication circuit 18 is logically added to the output of the register 9 in the OR circuit 13 and the result is latched in the register 10 with the timing signal inputted via the control signal input terminal 8. The data outputted from the multiplication circuits 19 and 20 are processed in the same way as above. When the entire data I(X) is inputted, the data of a₀, a₁, a₂, and a₃ of Eq. (5) are latched in the registers 9, 10, 11, and 12, respectively. Then, after the gate 21 is turned off, these data are shifted sequentially through the registers 9-12 and the CRC check symbols a₀-a₃ are outputted at the output terminal 7. For coding, these CRC check symbols a₀-a₃ are written in the check symbol write area in the format of FIG. 4 as follows: a₃ → i 1,0 a₂ → i 2,0 a₁ → i 3,0 a₀ → i 4,0 For decoding, they are compared to detect errors. The RS codes are corrected for the received words #0-#4 (data including errors) by the following steps. (1) Find an RS code syndrome from the received word. (2) Find an error location polynomial and the error value polynomial from the syndrome. (3) Determine an error location from the error location polynomial by the Chien search. (4) Determine an error value from the error location, the error location polynomial, and the error value polynomial and make correction. The steps (2) and (4) are carried out by the Galois field operation circuit 3 while the steps (1) and (3) are carried out by the sequence circuit 4. The corrected data is stored in the buffer memory 1. After all the code words (coded data) are corrected with RS codes, CRC check symbols are found in the CRC coding sequence circuit of FIG. 5, and the CRCs are computed in the OR circuit. As described above, if I(X) is given, it is easy to determined the CRC check symbol a k , but it is necessary to not only logically add interleaved information symbols but also make the CRC check symbol portion zero at the zero order of I(X) for computation. In addition, it is impossible to start computation of CRCs in decoding until all the interleaved code words are corrected with the RS codes. Summary of the Invention Accordingly, it is an object of the invention to provide an error correction circuit which is able to compute CRC check symbols at high speeds without determining complex special I(X). According to the invention, as defined by Claim 1, there is provided an error correction circuit which includes a parallel circuit of RS code sequence and CRC coding sequence circuits, and a control circuit for selecting one of the above sequence circuits. The above object and others not specifically mentioned will become clear to those skilled in the art from the following description. Brief Description of the Drawings FIG. 1 is a block diagram of an error correction circuit according to an embodiment of the invention; FIG. 2 is a flowchart showing the operation of the error correction circuit; FIG. 3 is a block diagram of a conventional error correction circuit; FIG. 4 is a diagram showing the standard data format of a 512 bytes/sector optical disk; and FIG. 5 is a schematic diagram of a conventional CRC coding sequence circuit. Description of the Preferred Embodiment In FIG. 1, like reference numerals denote like or corresponding parts of FIG. 3. A sequence circuit 4A is composed of a parallel circuit of a CRC coding sequence circuit 22 of the same configuration as that of FIG. 5 and and RS code sequence circuit 23 for carrying out the syndrome computation and the Chien search in RS codes. Bus output control gates 26 and 27 are connected to the respective outputs of the CRC coding sequence circuit 22 and the RS code sequence circuit 23. A control signal 24 is inputted to the sequence circuit 4A from the control circuit 5. A data bus 25 connects the sequence circuit 4A to the interface 2 and the Galois field operation circuit 3. In FIG. 2, the operation of an optical disk with the standard format of FIG. 4 is described. Steps S01, S11, S21, S31, and S41 correspond to the above step (1); S02, S12, S22, S32, and S42 to the above step (2); S03, S13, S23, S33, and S43 to the above step (3); and S04, S14, S24, S34, and S44 to the above step (4). Also, S05, S15, S25, S35, and S45 are CRC computation steps; S06, S16, S26, S36, and S46 CRC check symbol storing steps; S50 is a logical add step; and S60 a comparison step. The intermediate repeated steps S32-S43 are not shown. In response to the control signal 24, the sequence circuit 4A selects the operations mode in which the RS code sequence circuit 23 operates. After correcting the received word #0 in the steps S01-S04, the RS code sequence circuit 23 finds the syndrome in RS codes of the received word #1 (S11) and transfers it to the Galois field operation circuit 3 via the bus output control gate 27. The Galois field operation circuit 3 finds an error location polynomial and an error value polynomial from the syndrome data (S12) and continues the correction operation in RS codes. While the RS codes of the next received word are decoded, the RS code sequence circuit 23 is not used. In response to the control signal 24, the sequence circuit 4A selects the CRC coding sequence circuit 22. The data of the corrected word #0 is inputted to the CRC coding sequence circuit 22 via the buffer memory 1, the interface 2, and the data bus 25 in the order of information symbols i₀ ,n-d i₀ ,n-d-1 , ..., i₀ ,0 . The CRC coding sequence circuit 22 determines the CRC check symbol a k (S05). At this point, a received word is inputted to the input terminal 6 in place of I(X). When the steps S05 and S12 are completed, the CRC check symbol data of the received word #0 is transferred to the Galois field operation circuit 3 from the CRC coding sequence circuit 22 via the bus output control gate 26 and the data bus 25 and stored until the CRC check symbol data of the received word #1 is determined in the step S15 (S06). In response to the control signal 24, the sequence circuit 4A selects the RS code sequence circuit 23 to find the error location of the received word #1 by the Chien search based on the respective polynomial data from the Galois field operation circuit 3. When all the error locations of the received word #1 are found, the Galois field operation circuit 3 determines the error values and correct the received word #1 (S14). All the received words #0-#4 are similarly processed in the format sector of FIG. 4 in the steps S01-S46. The CRC check symbols (a₃-a₀) on the format (i₁ ,0 -i₄ ,0 ) are mixed in the information data but left for the time being. The CRC check symbol data of the received word #1 and subsequent words obtained in the steps S15, S25, S35, and S45 are logically added to the CRC check symbol data of the received word #0 in the steps S6, S26, S36, and S46 and stored in the Galois field operation circuit 3. The CRC check symbol written in the information symbol data portion is logically added in the Galois field operation circuit 3 to find the CRC check symbol, which is logically added to the data obtained from logical addition of the CRC check symbol data of the received words #0-#4 (S50). The resulting CRC check code data is compared with the CRC check code written on the format of the buffer memory 1 (S60) for detecing an error after the correction in RS codes. In the above decoding operation, an error is detected at the time of computation of CRC check symbols of each respective code stream by computing the CRC check symbol in the CRC coding sequence circuit 22 including the CRC check code portion in the buffer memory 1; computing the CRC check symbol in the Galois operation circuit 3 on the CRC check code portion within the buffer memory 1; logically adding it to the above CRC check symbol in the Galois field operation circuit; and comparing it with the CRC check code in the buffer memory 1 for detecing the error. In the coding operation, the CRC check code portion in the buffer memory 1 is cleared before computation of the CRC check symbol and, then, the CRC check symbol is computed in the CRC coding sequence circuit 22 including the CRC check code portion in the buffer memory and written in the CRC check code portion of the buffer memory 1. As described above, with the parallel circuit of RS code and CRC coding sequence circuits, either of which is selected depending on the operation mode, according to the invention, it is possible to detect an error in CRC by adding a minimum circuit necessary for CRC computation without finding a complex special I(X). Since the CRC computation is carried out in parallel with the RS decoding operation, high speed correction in units of sector is obtained.

Claims: An error correction circuit comprising: a buffer memory (1) for storing a plurality of interleaved data streams, each having as an external code an RS code for correcting an error in data and as an internal code a CRC for detecting an error in data; an interface (2) for untying said interleaved data streams; a Galois field operation circuit (3) for carrying out the four rules of arithmetic in a Galois field on a syndrome of said RS code and determining an error value based on an error location for effecting correction; an RS code sequence circuit (23) for computing said syndrome to find an error location from results of said four rules of arithmetic operation by a Chien search; a CRC coding sequence circuit (22) for coding and computing said CRC, said RS code sequence circuit and said CRC coding sequence circuit being paralleled to form a sequence circuit; and a control circuit (5) for controlling said interface, said Galois field operation circuit, said RS code sequence circuit, and said CRC coding sequence circuit and outputting a control signal for selecting either said RS code sequence circuit or said CRC coding sequence circuit for operation. The error correction circuit of claim 1, wherein said CRC coding sequence circuit determines a first CRC check symbol of a first code stream in said interleaved code streams, which is stored in said Galois field operation circuit; said CRC coding sequence circuit determines a second CRC check symbol of a second code stream, which is logically added to said first CRC check symbol and stored; and means for carrying out repeated operations similar to that of said second code stream for the number of times equal to that of interleaving stages and, in coding, writing a resulting CRC check symbol in said Galois operation circuit in a CRC check symbol portion of said buffer memory while, in decoding, comparing said CRC check symbol with a CRC check code in said buffer memory for detecting an error. The error correction circuit of claim 1 or 2, wherein, in coding, said CRC coding sequence circuit computes said CRC check symbol including said CRC check code portion in said buffer memory after said CRC check code portion in said buffer memory is cleared. The error correction circuit of claim 1 or 2, wherein, in decoding, said CRC coding sequence circuit is selected to compute said CRC check symbol of said first code stream while said RS sequence circuit is not used during decoding RS codes in said second code stream but data of said first code stream in said buffer memory is corrected by RS decoding and similarly compute CRC check symbols of a code stream corrected by previous RS decoding during RS decoding of each code stream; a resulting CRC check symbol of each said code stream being logically added and compared with said CRC check code in said buffer memory to detect an error after RS decoding. The error correction circuit of claim 1 or 2, wherein, in decoding, said CRC coding sequence circuit computes said CRC check symbol including said CRC check code portion of said buffer memory; said Galois operation circuit computes a CRC check symbol on said CRC check code portion of said buffer memory and logically adds a result to said CRC check symbol to eliminate any influence of said CRC check code on said CRC check symbol; said CRC check symbol being compared with said CRC check code in the buffer memory to detect an error. An error correction circuit comprising: a buffer memory for storing a plurality of interleaved data streams, each having as an external code an RS code for correcting an error in data and as an internal code a CRC for detecting an error in data; an interface for untying said interleaved data streams; a Galois field operation circuit for carrying out the four rules of arithmetic in a Galois field on a syndrome of said RS code and determining an error value based on an error location for effecting correction; an RS code sequence circuit for computing said syndrome to find an error location from results of said four rules of arithmetic operation by a Chien search; a CRC coding sequence circuit for determining a first CRC check symbol of a first code stream in said interleaved code streams, which is stored in said Galois field operation circuit, and then for determining a second CRC check symbol of a second code stream in said interleaved code streams, which is logically added to said first CRC check symbol and stored in said Galois operation circuit; a control circuit for controlling said interface, said Galois field operation circuit, said RS code sequence circuit, and said CRC coding sequence circuit and for outputting a control signal for selecting either said RS code sequence circuit or said CRC coding sequence circuit for operation; in coding said CRC coding sequence circuit for computing said CRC check symbol including said CRC check code portion in said buffer memory after said CRC check code portion in said buffer memory is cleared, and in decoding, said CRC coding sequence circuit for being selected to compute said CRC check symbol of said first code stream while said RS sequence circuit is not used during decoding RS codes in said second code stream but data of said first code stream in said buffer memory is corrected by RS decoding and similarly to compute CRC check symbols of a code stream corrected by previous RS decoding during RS decoding of each code stream; said CRC check symbol of each said code stream being logically added and compared with said CRC check code in said buffer memory to detect an error after RS decoding, said Galois field operation circuit computes a CRC check symbol on said CRC check symbol on said CRC check portion in said buffer memory and logically adds to said CRC check symbol to eliminate any influence of said CRC check code on said CRC check symbol; said CRC check symbol being compared with said CRC check code in said buffer memory to detect an error, said RS code sequence circuit and said CRC coding sequence circuit being paralleled to form a sequence circuit.

Inventors: YOSHIDA HIDEO C O MITSUBISHI D, YOSHIDA, HIDEO C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1989
Main classification: H03M13
IPC codes: G06F11, H03M13