Data reproducing circuit for memory system and having equalizer generating two different equalizing signals used for data reproduction

Abstract: A data recording and reproducing circuit for a memory system, such as a magnetic disk memory system, and including a reflection type cosine equalizer (2) and a data reproducing circuit (4). The equalizer includes a first equalizing circuit (21a), having a first equalizing gain (k₁), and outputting a first equalized signal, and a second equalizing circuit (21b) having a second equalizing gain (k₂) smaller than the first equalizing gain, and outputting a second equalizing circuit. The data reproducing circuit includes a differentiator (40) for differentiating the first equalized signal, a window generating circuit (42) for generating a window signal (WS) from the second equalized signal, and a data separator (43) for discriminating the differentiated signal in response to the window signal to produce de pulsed reproductions signal (DT).

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention-relates to an improved data reproducing circuit used for a memory system having a reading head, such as a magnetic disk memory system, a magnetic tape memory system, an optical disk memory system, etc., and reproducing analog signals read from the head as digital reproduction signals, with a high accuracy. 2. Description of the Related Art In memory systems, for example, a magnetic disk memory system, a magnetic tape memory system, etc., data is read from a magnetic recording medium, such as a magnetic disk, as analog signals, and accordingly, a magnetic reproducing circuit for reproducing the analog signals as digital signals is required. In such memory systems, since the memory density has been improved, to improve the resolution of a signal, an equalizer for equalizing an analog output is used. If however, the equalizing ability is improved, the signal reproduction accuracy is reduced. This relationship will be described later with reference to the accompanying drawings. Also, a differentiator in a data reproduction circuit provided as a circuit following the equalizer circuit, can not provide a stable differentiated result, due to the affects of noise, which result in a low signal reproduction accuracy. There is also known from patent document US-A-4 319 288 a current injection tapped delay line spectral shaping equalizer and differentiator whose characteristics correspond to the preamble of claim 1. Finally, a cosine equalizer comprising a delay line and an amplitude divider in series between the inputs to a differential amplifier is discussed in a paper authored by T. Kameyama et al, published in IEEE Transactions of Magnetics, Vol. . Mag-12, No. 6, November 1976. SUMMARY OF THE INVENTION An object of the present invention is to provide a data reproducing circuit used for a memory system and including an equalizer, in which an accuracy of a reproduction signal is improved without an improvement of an equalization ability of the equalizer. Another object of the present invention is to provide an equalizer used for a data reproducing circuit, and providing two different equalized signals. Still another object of the present invention is to provide a differentiator used for a data reproducing circuit and providing a reliable differentiated value free from noise. According to the present invention, there is provided a data reproducing circuit for a memory system having a data sensing head, comprising an equalizer having a delay circuit, first and second gain adjustment circuits and two differential amplifier circuits each having a first input connected to the output of a respective one of said gain adjustment circuits, said equalizer being operatively connected to receive an analog signal from the data sensing head and varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals from said analog signal; and a digital data reproducing circuit, operatively connected to said equalizer, for receiving said first and second equalized signals, said reproducing circuit differentiating said first equalized signal and generating a window signal when and during a time said second equalized signal is greater than a predetermined threshold value, and for outputting a pulsed reproduction signal when said differentiated signal exceeds a predetermined level and said window signal exists, characterized in that said equalizer is of the reflection type comprising a single delay element having an input receiving said input signal and one signal reflecting output connected to the second inputs of said differential amplifier circuits, the input of said delay element also being coupled to the input of each of the respective gain adjustment circuits, so that said delay element outputs a first delayed signal f(t + τ) to said second input terminals of said differential amplifier circuits and a second delayed signal f(t + 2τ) based upon said reflection signal from said second input terminal of said differential amplifer circuits to the respective input terminals of said first and second gain adjustment circuits, whereby said first gain adjustment circuit outputs a signal k₁.f(t) and k₁.f(t + 2τ) to said first input terminal of said first differential amplifier circuit, said first differential amplifier circuit subtracting the signal supplied by said first adjustment gain circuit from the signal supplied by said delay element, to output said first equalized signal expressed by : f1 = f(t + τ) - k₁ {f(t) + f(t + 2τ)} where, f(t) is a signal sensed by said head, τ is said delay time, and k₁ is said first equalizing gain, said second gain circuit outputs a signal k₂.f(t) and k₂.f(t + 2τ) to said first input terminal of said second differential amplifier circuit, said second differential amplifier circuit subtracting the signal supplied by said second gain circuit from the signal supplied by said delay element, to output said second equalized signal expressed by f2 = f(t + τ) - k₂ {f(t) + f(t + 2τ)}; where k₂ is said second equalizing gain. According to another aspect of the present invention, there is also provided an equalizer for a data reproducing circuit in a memory system having a data sensing head, the equalizer being substantially as defined in claim 4. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and features of the present invention will be described in more detail with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a prior art magnetic reproducing circuit; Figs. 2 and 3 are views showing equalizing signals generated in the magnetic reproducing circuit shown in Fig. 1; Figs. 4 and 5 are views showing waveforms in the magnetic reproducing circuit shown in Fig. 1; Fig. 6 is a principle diagram of a data reproducing circuit for a memory system in accordance with the present invention; Fig. 7 is a diagram of an embodiment of the data reproducing circuit shown in Fig. 6, as a magnetic recording/reproducing circuit; Figs. 8 and 9 are circuit diagrams of the magnetic reproducing circuit shown in Fig. 7; Fig. 10 is a circuit diagram of a pulse generation circuit, shown in Fig. 9; Figs. 11 and 12 are views showing waveforms in the circuits shown in Figs. 7 to 10; Fig. 13 is a simplified circuit diagram of a differentiator shown in Fig. 9; Figs. 14 and 15 are views showing waveforms in the differentiator shown in Fig. 13; Fig. 16 is a principle diagram of a differentiator in accordance with the present invention; Fig. 17 is a diagram of another data reproducing circuit using the differentiator shown in Fig. 16, in accordance with the present invention; Fig. 18 is a view showing waveforms in the differentiator shown in Fig. 16; Fig. 19 is a circuit diagram of the differentiator shown in Figs. 16 and 17; Fig. 20 is a view showing waveforms in the differentiator shown in Fig. 19; Fig. 21 is a diagram of another embodiment of a magnetic reproducing circuit of the present invention; and Fig. 22 is a view showing waveforms in the magnetic reproducing circuit shown in Fig. 21. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the preferred embodiments of the present invention, a prior art data reproducing circuit for a magnetic disk memory system, i.e., a magnetic reproducing circuit, will be described. Figure 1 is a circuit diagram of the prior art magnetic reproducing circuit. The magnetic reproducing circuit includes a reflection type cosine equalizer 2′ for equalizing an analog output f(t) from a magnetic head 1, a low-pass filter 3 for rejecting noise of an equalized signal, and a digital data reproducing circuit 4 for obtaining a digital reproduction output DT from the equalized and filtered signal f′ . The reflection type cosine equalizer 2′ has a delay element 20 having an open output end, a gain adjustment circuit 21, and a differential amplifier 22 for subtracting an output from the gain adjustment circuit 21 from the output from the delay element 20. The input signal f(t) is delayed at the delay element 20 by a delay time τ, and a delayed signal is supplied to a first input terminal of the amplifier 22. The input impedance of the amplifier 22 is very high, and the delayed signal supplied to the first input terminal is reflected to the delay element 20. The reflected signal is further delayed at the delay element 20 by the delay time τ, and the further delayed signal is added to the gain adjustment circuit 21. The gain adjustment circuit 21 has a gain k, where k ≦ 1. Namely, the first input terminal of the amplifier 22 receives a signal f(t+τ), and the gain adjustment circuit 21 receives signals kf(t) and kf(t+2τ). As a result, as shown in Figs. 2 and 3, the differential amplifier 22 calculates a difference between an analog output f(t+τ) obtained by delaying the analog output by the delay time τ at the delay element 20 and an output k·f(t)+k·f(t+2τ) from the gain adjustment circuit 21, to equalize the analog output Sf into an analog output f′ (t+τ) having a sharp waveform. This waveform has a cosine shape. The digital data reproducing circuit 4 has a differentiator 40 for differentiating the equalized and filtered signal f′, a zero-cross comparator 41 for detecting a zero-cross point of the differentiated signal df, a window generating circuit 42 for slicing the equalized signal Sf′ with a fixed slice level V SL to generate a window signal WS, and a data separation circuit 43 for separating a zero-cross signal ZCS by the window signal WS to obtain the digital reproduction signal DT. As shown in Fig. 4, the input signal f(t) from the magnetic head 1 is added to the reflection type cosine equalizer 2′, and is delayed at the delay element 20 by the delay time τ. Accordingly, the output f(t+τ) is supplied to the differential amplifier 22. At the same time, the gain adjustment circuit 21 outputs a gain adjusted signal of k·f(t)+k·f(t+2τ), since the delay element 20 is an open output terminal type, and the equalized signal Sf′ shown in Figs. 2 and 3 and Fig. 4 can be obtained by a differential operation of the differential amplifier 22. The equalized signal Sf′ is supplied to the reproducing circuit 4 through the filter 3, is differentiated by the differentiator 40, and is zero-cross detected by the zero-cross comparator 41, to thereby output the zero-cross signal ZCS. The equalized signal Sf′ is also sliced (discriminated) at fixed slice (threshold) levels V SL and -V SL in the window generating circuit 42, to generate two window signals WS1 and WS2 having reverse phases. The zero-cross signal ZCS is separated by the window signals WS1 and WS2, by the data separator circuit 43, to thereby output the digital reproduction signal DT. To improve the S/N ratio of the differentiator 40, a gain k of the equalizer 2 is increased to sharpen the waveform, as shown in Fig. 3. When the gain k is increased to increase an equalizing value, shoulder portions appear at two sides of an original waveform, and as a result, a voltage V₁ is decreased and a voltage V₂ is increased as the equalizing value is increased, as shown in Fig. 3 and as indicated by arrows in Fig. 5. If a signal due to defects on a disk medium is superposed on the shoulder portion, the level of that signal may exceed the fixed slice level V SL , as indicated by dotted curves in Fig. 4 and as shown in Fig. 5. In this case, as indicated by dotted curves in Fig. 4 and as shown in Fig. 5, erroneous data D1′ due to the shoulder portions is reproduced in addition to normal data D1, and correct data D2 may be omitted. For this reason, in the prior art, an improvement of the S/N ratio of the differentiator and the removal of an erroneous reproduction signal due to medium defects are conflicting requirements. The above defects may occur in other magnetic systems, such as the magnetic tape memory system and optical disk memory system, etc. The present invention is intended to overcome the above problems and provides a data reproducing circuit which can simultaneously achieve an improvement of the S/N ratio of the differentiator and a removal of an erroneous reproduction signal due to medium defects. Figure 6 is a principle view of the present invention. In the drawings, a data reproducing circuit of the present invention has a reflection type cosine equalizer 2 including a delay circuit 20, a pair of gain adjustment circuits 21a and 21b, a pair of differential amplifiers 22a and 22b, a digital data reproducing circuit 4 including a differentiator 40, a zero-cross comparator 41, a window generating circuit 42, and a data separation circuit 43. The circuit construction of the digital reproducing circuit 4 is the same as the circuit construction shown in Fig. 1, except that the equalizer 2 is different from the equalizer 2′ shown in Fig. 1. The reflection type cosine equalizer 2 receives data Sf from a data reading head 1, for example, a magnetic head in a magnetic disk memory system, and generates two equalized signals f₁ and f₂ having different gains k₁ and k₂ , to enable the digital data reproducing circuit 4 to use the equalized signals expressed by the following formulas: f₁ = k₁·f(t) + k₁·f(t+2τ) f₂ = k₂·f(t) + k₂·f(t+2τ) The mode of generation of the equalized signals f₁ and f₂ is the same as that described above with reference to Fig. 1. The first equalized signal f₁ is supplied to the differentiator 40 and differentiated thereat, and zero-cross points of the differentiated signal are detected by the zero-cross comparator 41. The second equalized signal f₂ is used to generate windows WS1 and WS2 at the window generating circuit 42. A differentiation with a high S/N ratio can be made by using the equalized signal f₁ having the large equalizing gain k₁ , and windows can be generated using the equalized signal f₂ having a small equalizing gain k₂. Namely, the window generation is made regardless of the S/N ratio. Therefore, the defects accompanying the generation of the windows WS1 and WS2 can be prevented, and an erroneous reproduction signal due to medium defects can be stably removed. Conversely, the requirement that the gain k₂ should be set greater than the gain k, exists. The present invention can be applied to systems in which such requirement exists. An embodiment of a data recording and reproducing circuit of the present invention will now be described. Figure 7 is a diagram of the data recording and reproducing circuit used in a magnetic disk memory system, such as a magnetic recording and reproducing circuit. In Fig. 7, the same reference numerals denote the same parts as in Fig. 6. Reference numerals 3a and 3b denote low-pass filters for cutting high frequency noise components (harmonic components) in outputs from differential amplifiers 22a and 22b; 5a denotes an amplifier for amplifying a read output from a magnetic head 1a; and 5b denotes an automatic gain control (AGC) circuit for carrying out an automatic gain control of the amplified signal. Figure 8 is a circuit diagram of the reflection type cosine equalizer shown in Fig. 7, and Fig. 9 is a circuit diagram of the data reproducing circuit shown in Fig. 7. In Fig. 8, reference numeral 20a denotes an input terminal circuit, which receives the analog input Sf, constitutes an open termination of a delay circuit 20, and comprises coupling capacitors C₁ and C₂ for receiving the analog signal Sf, a pair of emitter-follower transistors Q₁ and Q₂ constituting a differential amplifier, a coupling resistor R₃ , collector resistors R₄ and R₅ , and current sources Is. The collector resistors R₄ and R₅ serve as terminal resistors. Reference symbol DL denotes a delay line consisting of an inductor and delaying the collector output from the transistor Q₁ by a delaying time τ. The output of the delay line DL is connected to a pair of emitter-follower transistors Q₃ and Q₄ , to increase an input impedance of the amplifier 22a to cause a reflection. An output f(t+τ) from the delay line DL is applied to the differential amplifier 22a through a transistor Q₃ , a coupling capacitor C₃ , a pull-down resistor R₆ , a transistor Q₅ , a coupling capacitor C₅ , and a pull-down resistor R₉. An input to the delay line DL is also input to the first gain adjustment circuit 21a consisting of voltage-dividing resistors R₇ and R₈ which define the gain k₁ through the transistor Q₄ and the coupling capacitor C₄ , and is then applied to the differential amplifier 22a through a transistor Q₆ , a coupling capacitor C₆ , and a pull-down resistor R₁₀. The differential amplifier 22a has a pair of differential transistors Q₇ and Q₈ , a coupling resistor R₁₁ , collector resistors R₁₂ and R₁₃ , a pair of transistors Q₉ and Q₁₀ for outputting the collector output as the emitter output, and coupling capacitors C₇ and C₈ connected to the filter 3a. Similarly, the output f(t+τ) of the delay line DL is input to a transistor Q₁₁ to increase an input impedance of the amplifier 22b to cause a reflection, and is added to the differential amplifier 22b through a coupling capacitor C₉ , a pull-down resistor R₁₄ , a transistor Q₁₃ , a coupling capacitor C₁₁ , and a pull-down resistor R₁₇. The input to the delay line DL is also added to the second gain adjustment circuit 21b consisting of voltage-dividing resistors R₁₅ and R₁₆ which define the gain k₂ through a transistor Q₁₂ and a coupling capacitor C₁₀ , and is then added to the differential amplifier 22b through a transistor Q₁₄ , a coupling capacitor C₁₂ , and a pull-down resistor R₁₈. The differential amplifier 22b includes a pair of differential transistors Q₁₅ and Q₁₆ , a coupling resistor R₁₉ , collector resistors R₂₀ and R₂₁ , a pair of transistors Q₁₇ and Q₁₈ for outputting the collector output as the emitter output, and coupling capacitors C₁₃ and C₁₄. The emitters of the emitter-follower transistors Q₁ to Q₁₈ are coupled to current sources Is, respectively. In Fig. 9, the differentiator 40 includes coupling capacitors C₁₀₁ and C₁₀₂ connected to the filter 3a, a differential amplifier consisting of transistors Q₁₁₁, Q₁₁₂ and Q₁₁₃, a differential circuit consisting of a capacitor C₁₀₅ and a resistor R₁₀₅, and output transistors Q₁₁₆ and Q₁₁₇. Transistors Q₁₀₁, Q₁₀₂, Q₁₀₄, Q₁₀₅, Q₁₀₇, Q₁₀₈, Q₁₁₈, Q₁₁₉, Q₁₂₀, an emitter of each which is connected to a base, function as diodes and function as level shifters. A plurality of series-connected circuits of transistors and resistors, for example, a transistor Q₁₂₄ and a resistor R₁₄₄, are current sources. The zero-cross comparator 41 includes coupling capacitors C₁₀₃ and C₁₀₄, a pair of voltage divider circuits, which consist of series-connected resistors R₁₁₆ and R₁₁₈, and R₁₁₇ and R₁₁₉, respectively, and three differential amplifiers; a first of which consists of a pair of differential operation transistors Q₁₃₃ and Q₁₃₄ and a pair of output transistors Q₁₃₅ and Q₁₃₆, a second of which consists of a pair of differential operation transistors Q₁₃₇ and Q₁₃₈ and a pair of output transistors Q₁₃₉ and Q₁₄₀, and a third of which consists of a pair of differential operation transistors Q₁₄₁ and Q₁₄₂ and a pair of output transistors Q₁₄₃ and Q₁₄₄. The window generating circuit 42 includes coupling capacitors C₁₀₆ and C₁₀₇, voltage dividing circuits which consists of series connected resistors R₁₃₉ and R₁₄₁, and R₁₄₀ and R₁₄₂, comparators CMP1 and CMP2 which operate in reverse to each other and generate the window signals WS1 and WS2, and a set-reset type flip-flop FF1 outputting a third window signal WS3. The data separation circuit 43 includes a delay type flip-flop FF2, and a pulse generation circuit 431. Figure 10 shows a circuit diagram of the pulse generation circuit 431. The pulse generation circuit 431 receives a pair of outputs DTA and DTA and generates the pulsed reproduction signal DT. Figures 11 and 12 show waveforms in the circuits shown in Figs. 7, 8, 9, and 10. The output signal from the magnetic head 19 is amplified by the amplifier 5a, subjected to AGC control by the AGC circuit 5b, and applied to the reflection type cosine equalizer 2. The analog input f(t) is delayed by the delay time at the delay circuit 20 to be the delayed signal f(t+τ) . The first gain adjustment circuit 21a outputs the first gain adjusted signal k₁·f with a large gain k₁ , and the second gain adjustment circuit 21b outputs the second gain adjusted signal k₂·f with a small gain k₂. The amplitude of the first gain adjusted signal k₁·f is higher than that of the second gain adjusted signal k₂·f. The differential amplifiers 22a and 22b output differences between the delay signal f(t+τ) and the gain adjusted signals k₁·f and k₂·f as the equalized signals f₁ and f₂. Since the first equalized signal f₁ has a larger equalizing value than that of the second equalized signal f₂ , it has a sharp waveform and shoulder portions, whereby the equalized signal f₁ is differentiated by the differentiator 40 to be the differentiated signal df. The differentiated signal is zero-cross detected by the zero-cross comparator 41, thus obtaining a zero-cross signal ZCS. In this case, since the equalized signal f₁ has a sharp waveform, the S/N ratio of the differentiated output is improved, and a good zero-cross output can be obtained. The equalized signal f₂ is sliced at fixed slice levels V SL and -V SL by the window generating circuit 42, thus outputting two window signals WS1 and WS2. In this case, since the equalizing value of the equalized signal f₂ is small, almost no shoulder portions appear, and if a signal due to a medium defect is superposed on this portion, the resultant level does not exceed the slice level, and thus a good window signal can be generated. The zero-cross signal ZCS and the window signals WS1 and WS2 are supplied to the data separator circuit 43 and defects of the in-phase components are removed, and thus a reproduction signal DT is obtained. In this manner, since equalized signals f₁ and f₂ having optimal equalizing values suitable for differentiation and window generation are generated, the S/N ratio of differentiation can be improved, and an effective reproduction can be performed even if a medium defect occurs. In the above embodiment, the two window signals WS1 and WS2 are generated, but the equalized signal f₂ is full-wave rectified and is sliced at one slice level V SL , to form one window signal for data separation. In Fig. 12, signals SA to SC show waveforms at nodes A, B and C in the pulse generation circuit shown in Fig. 10. Also, the gain k₂ can be set greater than the gain k₁. The digital data reproducing circuit 4 may be arranged such that the differentiator is operated by the window signal, and the equalized signal f₁ is differentiated and input to the zero-cross comparator 41 only during a window period, to reproduce data. As described above, according to the present invention, since two equalized signals having different equalizing values are generated and used for differentiation and window generation, respectively, a differentiation with a high S/N ratio can be obtained and a window signal free from an influence of medium defects can be generated, and thus a reproduction free from an erroneous operation caused by medium defects can be realized. In addition, an improved differentiator for differentiating an analog data exceeding a predetermined slice level will be described. Figure 13 is a simplified circuit diagram of the differentiator 40 shown in Fig. 9. Note, this differentiator 40 is a rectification active type differentiator. Figure 14 shows waveforms in the differentiator 40 shown in Fig. 13. When the differential analog signal f′₁ or f′₂ exceeds the slice voltage V SL , a current corresponding to a difference between the transistors Q₁₁₂ and Q₁₁₄, or Q₁₁₁ and Q₁₁₄ flows in the capacitor C₁₀₅ and through the resistor R₁₀₅ of the differentiating circuit, to thus achieve a differentiation. Therefore, the differentiation cannot be made for a noise component below the slice voltage V SL , and thus a noise component can be removed, and a differentiation can be made for only a regular signal. When such a differentiator 40 is used for the magnetic reproducing circuit, some problems may arise as shown in Fig. 15. The input signal f(t) from the magnetic head 1a is input to the reflection type cosine equalizer 2 and is delayed by the delay time τ at the delay element 20, and the delayed output f (t+τ) is supplied to the differential amplifier 22a. The gain adjustment circuit 21a connected in parallel to the delay element 20 outputs the gain adjusted signal k₁·f(t)+k₁ ·f(t+2τ). The equalized signal fl can be obtained by the differential operation of the differential amplifier 22a. The equalized signal fl is supplied to the differentiator 40 through the filter 3a, and is differentiated thereby as described above. The differentiated signal is then zero-cross detected by the zero-cross comparator 41, and thus a reproduction signal DT is obtained. Nevertheless, since the differentiator 40 directly slices the input analog signal fl with the slice voltage V SL , only a difference between the analog signal f1 and the slice voltage V SL is differentiated and the differentiated signal has a small level, resulting in a small differentiation gain, and thus the S/N ratio is lowered. In the magnetic reproducing circuit, to increase the S/N ratio of the differentiator 40, shoulder portions appear in both side portions of an original waveform, as indicated by arrows in Fig. 15. As the equalizing value is increased, the voltage V₁ is decreased, and the voltage V₂ is increased. If a signal caused by defects on a disk medium is superposed on this shoulder portion, the level thereof may exceed the fixed slice level V SL , as indicated by dotted curves in Fig. 15. In this case, erroneous data D11′ caused by the shoulder portion is reproduced in addition to data D11, as indicated by dotted curves in Fig. 15. For this reason, an increase in the S/N ratio of the differentiator 40 and removal of an erroneous reproduction signal due to medium defects are conflicting requirements. Figure 16 is a principle view of a differentiator 7 in accordance with the present invention. In Fig. 16, the differentiator of the present invention has a window generating circuit 42 for slicing the analog signal f(t) at a predetermined slice level V SL to generate a window signal WS, and a selective differentiating circuit 7b for receiving the analog signal f(t) and differentiating the analog signal exceeding a level signal input to the gate terminal thereof. The window signal WS is supplied to the gate terminal of the selective differentiating circuit 7b. As shown in Fig. 17, a data reproducing circuit of the present invention has the reflection type cosine equalizer 2 having the same circuit construction as that shown in Fig. 6, for outputting the pair of equalized signals f₁ and f₂ , the window generating circuit 42 for slicing one f₂ of the pair of equalized signals at the predetermined slice level V SL to generate a window signal WS, the selective differentiating circuit 7b for receiving the other f₁ of the pair of equalized signals and differentiating the equalized signal f₁ exceeding the window signal WS input to the gate terminal, and the zero-cross comparator 43 for obtaining a digital reproduction signal DT from the output from the selective differentiating circuit 7b. A digital data reproducing circuit 4a consists of the selective differentiating circuit 5b, the window generating circuit 42, and the zero-cross comparator 43. As shown in Fig. 18, in the differentiator 7 of the present invention, the input analog signal f(t) and the slice level V SL are compared to generate the window signal WS, and the window signal WS is added to the selective differentiating circuit 7b as a level signal. The window signal WS is low level when the analog signal f(t) exceeds the slice level V SL , and is high level when the signal f(t) does not exceed the slice level. The level itself of the analog signal f(t) can be differentiated, and a differentiation gain can be increased. In the data reproducing circuit of the present invention, the reflection type cosine equalizer 2 generates the two equalized signals f₁ and f₂ having different gains k₁ and k₂ and the digital data reproducing circuit 4 can use the equalized signals f₁ and f₂ having the different equalizing gains k₁ and k₂ for differentiation and window generation, respectively. For this reason, a differentiation with a high S/N ratio can be made by the differentiator 57 supplied with the equalized signal f₁ having the large equalizing value, and a window can be generated using the equalized signal f₂ having the small equalizing value. Therefore, a window with defects is not generated, and an erroneous reproduction signal due to medium defects is stably removed. Figure 19 is a view showing a circuit of the differentiator 7 according to an embodiment of the present invention. The window generating circuit 7a has input resistors R₂₀₅ and R₂₀₆ and input transistors Q₂₁₀ and Q₂₁₁ for receiving the analog signals f₁ and f₂ , an input transistor Q₁₁₂ for receiving the slice voltage V SL , and a rectification differential amplifier consisting of transistors Q₂₁₃, Q₂₁₄, Q₂₁₅. Reference symbols R₂₀₇ and R₂₀₈ denote collector resistors; and Is, current sources. A selective differentiating circuit 7b is similar to the differentiating circuit shown in Fig. 11 except that different reference numerals are used, and is a rectification active type differentiating circuit in which the window signal WS is input to the gate terminal thereof, instead of the slice voltage V SL . Figure 20 is a view for explaining an operation of the differentiator 7 shown in Fig. 19. In the window generating circuit 42, one analog input signal f′₁ is supplied to the base of the transistor Q₂₁₄ through the transistor Q₂₁₀, and the other analog input signal f′₂ is supplied to a base of the transistor Q₂₁₅ through the transistor Q₂₁₁. Since a base of the transistor Q₂₁₃ receives the slice voltage V SL through the transistor Q₂₁₂, a rectification difference is obtained, and thus, when f′₁ ≧ V SL , or f′₂ ≧ V SL , the window signal WS is set at a low level; in another case, the window signal WS is set at a high level. In the selective differentiating circuit 7b, the analog signal f′₁ is supplied to a base of the transistor Q₂₀₆ through the transistor Q₂₀₁, and the analog signal f′₂ is supplied to a base of the transistor Q₂₀₇ through the transistor Q₂₀₂. Since bases of the transistors Q₂₀₄ and Q₂₀₅ receive the window signal WS, a current corresponding to a difference between the analog signals f′₁ and f′₂ and the low-level window signal WS flows through the differentiation resistor R and the capacitor C due to the rectification difference. In Fig. 20, references V N1 and V N2 denote voltages at nodes N1 and N2. Therefore, a differentiation is made at hatched portions in Fig. 20, and the differentiated signal is output through the output transistors Q₂₀₈ and Q₂₀₉. Accordingly, the differentiation gain can be increased, and the S/N ratio of a signal can be raised. Figure 21 is a diagram showing an arrangement of a magnetic reproducing circuit according to the embodiment of the present invention, and Figure 22 is a waveform chart of the embodiment of the present invention. The operation of the arrangement shown in Fig. 21 will be described below with reference to Fig. 22. The output from the magnetic head 1a is amplified by the amplifier 5a, is AGC-controlled by the AGC circuit 5b, and is then supplied to the reflection type cosine equalizer 2. The analog input is delayed by the delay time τ at the delay circuit 20 to be converted to a delay signal f(t+τ). The first gain adjustment circuit 21a outputs the first gain adjusted signal k₁·f having the large gain k₁ and the second gain adjustment circuit 21b outputs the second gain adjusted signal k₂·f with the small gain k₂. The amplitude of the first gain adjusted signal k₁·f is higher than that of the second gain adjusted signal k₂·f. The differential amplifiers 22a and 22b output differences between the delay signal f (t+τ) and the gain adjusted signals k₁·f and k₂·f as equalized signals f₁ and f₂. Since the equalized signal f₁ has a larger equalizing value than that of the equalized signal f₂ , the waveform thereof is sharp and has shoulder portions. The equalized signal f₂ is rectified and compared with the slice voltage V SL by the window signal generating circuit 42, thus generating the window signal WS. In this case, since the equalizing value of the equalized signal f₂ is small, almost no shoulder portions appear, and if a signal caused by medium defects is superposed on this portion, the level thereof does not exceed the slice level, and thus a good window signal can be generated. The equalized signal f₁ is supplied to the selective differentiating circuit 7b, and is differentiated while gating the window signal WS. The differentiated signal df is zero-cross detected by the zero-cross comparator 43, to thus obtain the reproduction signal DT. In this case, since the equalized signal f₁ has a sharp waveform, the S/N ratio of the differentiated output is raised, and a good zero-cross output can be obtained. Also, since the differentiation gain is large, a good differentiated output can be obtained. In this manner, since equalized signals having optimized equalizing values are generated for differentiation and window generation, respectively, the S/N ratio of differentiation can be raised, and an effective reproduction free from medium defects can be obtained. In the above embodiment, the rectification differentiating circuit 7b is used, but if a full-wave rectifier circuit is arranged at an input side, the differentiating circuit does not need a rectification function. Similarly, if a full-wave rectifier circuit is arranged at an input side of the window generating circuit, a rectification function is not needed. The application of the differentiator is not limited to the magnetic reproducing circuit. For example, the differentiator can be applied to other circuits if a noise component below a predetermined level is to be removed. As described above, according to the differentiator of the present invention, the differentiation gain of the selective differentiating circuit can be increased, and a good differentiated output can be obtained. According to the magnetic reproducing circuit of the present invention using the differentiator therein, since two equalized signals having different equalizing values are generated and used for differentiation and window generation, respectively, differentiation with a large gain and a high S/N ratio can be achieved, and a window signal free from the influence of signal defects can be generated, and thus reproduction free from erroneous operations caused by medium defects can be realized.

Claims: A data reproducing circuit for a memory system having a data sensing head (1), comprising: an equalizer (2) having a delay circuit (20), first and second gain adjustment circuits (21a, 21b) and two differential amplifier circuits (22a, 22b) each having a first input (-) connected to the output of a respective one of said gain adjustment circuits, said equalizer (2) being operatively connected to receive an analog signal f(t) from the data sensing head (1) and varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals (f1, f2) from said analog signal; and a digital data reproducing circuit (4), operatively connected to said equalizer (2), for receiving said first and second equalized signals (f1, f2), said reproducing circuit differentiating (at 40) said first equalized signal (f1) and generating (at 42) a window signal (WS1, WS2) when and during a time said second equalized signal (f2) is greater than a predetermined threshold value (VSL), and for outputting a pulsed reproduction signal (DT) when said differentiated signal exceeds a predetermined level and said window signal exists, characterized in that said equalizer is of the reflection type comprising a single delay element (20) having an input receiving said input signal f(t) and one signal reflecting output connected to the second inputs (+) of said differential amplifier circuits (22a, 22b), the input of said delay element also being coupled to the input of each of the respective gain adjustment circuits (21a, 21b), so that said delay element outputs a first delayed signal f(t + τ) to said second input terminals (+) of said differential amplifier circuits and a second delayed signal f(t + 2τ) based upon said reflection signal from said second input terminals of said differential amplifer circuits to the respective input terminals (-) of said first and second gain adjustment circuits (21a, 21b), whereby said first gain adjustment circuit (21a) outputs a signal k₁.f(t) and k₁.f(t + 2τ) to said first input terminal (-) of said first differential amplifier circuit (22a), said first differential amplifier circuit (22a) subtracting the signal supplied by said first gain adjustment circuit (21a) from the signal supplied by said delay element (20), to output said first equalized signal f1 expressed by f1 = f(t+τ) - k₁ {f(t) + f(t + 2τ)} where f(t) is a signal sensed by said head, τ is said delay time, and k₁ is said first equalizing gain, said second gain adjustment circuit (21b) outputs a signal k₂.f(t) and k₂.f(t + 2τ) to said first input terminal (-) of said second differential amplifier circuit (22b), said second differential amplifier circuit (22b) subtracting the signal supplied by said second gain adjustment circuit (21b) from the signal supplied by said delay element, to output said second equalized signal f2 expressed by f2 = f(t+τ) - k₂ {f(t) + f(t+2τ)}; where k₂ is said second equalizing gain. A data reproducing circuit according to claim 1, wherein said second inputs (+) of said differential amplifier circuits (22a, 22b) which are connected to an output terminal of said delay element (20) have a high.input impedance such that the signal from said delay element is reflected back thereto. A data reproducing circuit according to any one of claims 1 to 2, wherein said digital data reproducing circuit (4) comprises : a window generation circuit (42) for receiving said first equalized signal f1 and having an amplitude of a predetermined threshold value to generate a window signal (WS) when said signal is greater than said predetermined threshold value (VSL), a selective differentiating circuit (7b), operatively connected to said window generation circuit to receive said window signal, and differentiating another signal corresponding to said signal to be discriminated and having an amplitude higher than said amplitude of said discriminating signal by a predetermined differentiating constant, and gating said differentiated signal by said window signal from said window generation circuit, and a pulse generation circuit (43), operatively connected to said selective differentiating circuit, for generating said pulsed reproduction signal when said gated differential signal exceeds a predetermined pulsing threshold level. An equalizer for a data reproducing circuit used in a memory system, said equalizer comprising : a delay circuit (20), first and second gain adjustment circuits (21a, 21b) and two differential amplifier circuits (22a, 22b) each having a first input (-) connected to the output of a respective one of said gain adjustment circuits, said equalizer (2) being operatively connected to receive an analog signal f(t) from a data sensing head (1) and varying an amplitude of said analog signal in accordance with a predetermined time, and generating first and second equalized signals (f1, f2) from said analog signal; characterized in that said equalizer is of the reflection type comprising a single delay element (20) having an input receiving said input signal f(t) and one signal reflecting output connected to the second inputs (+) of said differential amplifier circuits (22a, 22b), the input of said delay element also being coupled to the input of each of the respective gain adjustment circuits (21a, 21b), so that said delay element outputs a first delayed signal f(t + τ) to said second input terminals (+) of said differential amplifier circuits and a second delay signal f(t + 2τ) based upon said reflection signal from said second input terminals of said differential circuits to the respective input terminals (-) of said first and second gain adjustment circuits (21a, 21b), whereby said first gain circuit (21a) outputs a signal k₁.f(t) and k₁.f(t + 2τ) to said first input terminal (-) of said first differential amplifier circuit (22a), said first differential amplifier circuit (22a) subtracting the signal supplied by said first adjustment gain circuit (21a) from the signal supplied by said delay element (20), to output said first equalized signal f1 expressed by f1 = f(t + τ) - k₁ {f(t) + f(t + 2τ)} where f(t) is a signal sensed by said head, τ is said delay time, and k₁ is said first equalizing gain, said second gain circuit (21b) outputs a signal k₂.f(t) and k₂.f(t + 2τ) to said first input terminal (-) of said second differential amplifier circuit (22b), said second differential amplifier circuit (22b) subtracting the signal supplied by said second gain adjustment circuit (21b) from the signal supplied by said delay element, to output said second equalized signal f2 expressed by f2 = f(t + τ) - k₂ {f(t) + f(t + 2τ)}; where k₂ is said second equalizing gain. An equalizer according to claim 1 or 4, wherein said delay element (20) comprises an inductor (DL), defining said delay time.

Inventors: KANEGAE MASAHIDE, KANEGAE, MASAHIDE
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: G11B5
IPC codes: G11B20, G11B5