MAGNETIC CHARACTER READING APPARATUS

Abstract: An apparatus for use in reading magnetic characters which are printed on a carrier (12) such as a financial document or a cheque, the character waveforms include positive and negative peak values and substantially zero values occuring at predetermined times for a predetermined character. A shaft encoder (25) is used to develop a nominal count in alternately operative counters (A-1, A-2), which count is correlated to the velocity of the carrier (12). The nominal count is used to generate a timing clock (CL-1 to CL-7) which is used to clock the positive and negative peak values and substantially zero values into registers for subsequent character recognition. The occurrence of the timing clock (CL-1 to CL-7) is adjusted by utilizing the occurrence of a positive or negative peak itself.

Description: MAGNETIC CHARACTER READING APPARATUS Technical Field This invention relates to apparatus for use in reading magnetically encoded characters on a carrier, with each said character having a waveform which starts with a positive peak value, and with the waveforms of said characters being composed of predetermined patterns of positive peak values, negative peak values, and substantially zero values occurring at predetermined clocking periods to identify a particular waveform as representing a particular character. The invention has a particular application to MICR (Magnetic Ink Character Recognition) readers. Background Art U.S. Patent No. 3,528,058 discloses a character recognition system which utilizes retiming means which corrects the separation of character segments to . compensate for variations in the speed of the document transport. Each sensed character provides a corresponding waveform, with such waveform being arranged in eight time zones. Each time zone is divided into eight subperiods and on oscillator supplies drive pulses to a timing ring which produces eight output signals defining the eight subperiods. The sensing of a waveform peak at an incorrect subperiod time, due to fast or slow document velocity, causes the timing ring to be reset, thereby shortening or lengthening one of the subperiods. Disclosure of the Invention It is an object of the present invention to provide apparatus of the kind specified which is able to read magnetically encoded characters on a document even though there is a variation in the speed of the document being read as it is moved past the reader. Therefore, according to the present invention, there is provided apparatus of the kind specified, characterized by: data register means adapted to store said positive peak values, negative peak values and substantially zero values when clocked therein; a clocking circuit adapted to clock said positive peak, negative peak, and substantially zero values into said data register means at times corresponding substantially to the times of the occurrences of said positive peak, negative peak and said substantiall -zero values; said clocking circuit having generating means including a shaft encoder and adapted to generate a nominal clock signal defining a nominal count period for each of said positive peak, negative peak, and substantially zero values, and adjusting means adapted to utilize a positive peak value or a negative peak value itself for adjusting the occurrence of an associated said nominal clock signal to generate an adjusted " clock signal which is used to clock the associated said positive or negative peak value into said data register means. An advantage of apparatus according to the invention is that it is economical to manufacture. Another advantage is that an inexpensive motor can be used in the drive for the character carrier, yet the characters can be accurately read, without the need for an expensive constant velocity motor. Brief Description of the Drawings One embodiment of the invention will now be described by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a general schematic plan view of the apparatus of this invention; Fig. 2 is a waveform of a MICR character which is read by the apparatus of this invention; Fig. 3 shows a general overall schematic view of the read circuit shown in Fig. 1; Figs. 4A and 4B, taken together, show a portion of the read circuit shown in Fig. 1; Figs. 4A-1, 4A-2, 4A-3, and 4A-4, included on the sheet containing Fig. 4A, show additional details of the read circuit; Figs. 5A and 5B, taken together, show additional details of the read circuit shown in Fig. 1; Fig. 6 shows certain waveforms associated with the circuit shown in Fig. 1; Fig. 7 shows certain waveforms associated with the portion of the circuit shown in Figs. 5A and 5B; Fig. 8 is a schematic diagram showing additional details of the early peak circuit shown in Fig. 5B; Fig. 9 shows " certain waveforms associated with the portion of the circuit shown in Fig. 4A; and Figs. 10A and 10B, taken together, show a portion of the circuit shown in Fig. 4B. Best Mode for Carrying Out the Invention As stated earlier herein, one of the purposes of this invention is to read MICR data on a document even though there is some variation in the speed of the document as it is moved past the associated read head. In this regard, Fig. 1 shows a typical environment or apparatus 10 in which this invention may be used. In the banking or financial systems, certain data is printed on documents in magnetic ink; this data is referred to as MICR data, and it generally appears near the bottom of the documents, like checks, for example. When the MICR data is to be read, the carrier or document 12, carrying the data, is moved in a document track 14 by a document transport 16 which includes rollers 16-1 and 16-2, with the document transport 16 being under the control of a controller 18. As shown in Fig. 1, the top edge of the document is visible, with the bottom edge of the document 12 gliding over the bottom of the document track 14. A read head 20 is positioned in the track 14 so as to be in reading relationship with the MICR data on the document 12 as it is moved past the read head 20. Prior to the document 12 reaching the read head 20, its leading edge encounters a document present sensor 22. The output of the sensor 22 is coupled to a MICR character read circuit which is designated generally as circuit 24; this circuit 24 is part of the apparatus 10. The apparatus 10 also includes a conventional shaft encoder 25 whose output is also coupled to the circuit 24. The encoder 25 is coupled to the shaft which rotates the drive wheel 25- 1, which, in turn, moves the document 12 past the read head 20. The encoder 25 is designed to produce a pulse for every 0.0125 inch (0.31 mm)of document travel; the significance of this relationship will be described hereinafter. Before describing the apparatus 10 in more detail, it appears appropriate to discuss the characteristics of the waveforms generated when the MICR data is moved in operative relationship with the read head 20. In the embodiment described, the waveforms to be discussed are associated with E13B characters, although the principles of this invention may be extended to the reading of magnetic waveforms other than the E13B mentioned. Some of the characteristics of E13B characters are as follows. The character pitch according to ABA standards is 0.125 inch (3.1 mm); that is, it is 0.125 inch (3.1 mm) from the start of one character to the start of the next character. The shaft encoder 25 produces one pulse for every 0.0125 inch (0.31 mm) of document travel, or, another way of stating the relationship is that the shaft encoder 25 produces 10 clocks for each character pitch. Within this 0.125 inch (3.1 mm), there are eight cells or equally-spaced windows which are used to examine the magnetic waveform for an associated character. In this regard, a magnetic waveform may have positive peaks, negative peaks, and no peaks or substantially zero values which are located in the cells in predetermined patterns so as to be indicative of a particular character within the system. Another point is that each character always starts with a positive going peak in the first cell or window. Fig. 2 shows a magnetic waveform 26 for the number zero. Notice that the character starts with a positive going peak 28. Whenever there is relative motion between the magnetized MICR characters on the document 12 and the read head 20, a voltage which is proportional to the rate of change of magnetic flux is generated. For the correct MICR recognition of a character, it is necessary that peaks within the waveform be identified and located properly. Whenever the speed of the document varies, the peaks in the associated waveform which is developed may not fall within the proper windows or cells of the waveform; consequently, an error in reading may result. The present invention provides a unique way of recognizing MICR characters by which instantaneous changes in the speed of the document moving past the read head 20 will have no effect on reading characters accurately. Fig. 2 also illustrates certain factors associated with this invention. As stated earlier herein, this figure shows the magnetic waveform of the number 0. There are ten clock pulses generated for a character pitch which is 0.125 inch (3.1 mm); these ten pulses are marked as CL-0 through CL-9. The first clock pulse starts with the generation of the first positive peak 28; this first clock is marked CL-0. After detecting the first positive peak 28 (Fig.2), a clock pulse is developed every 0.0125 (0.31 mm) inch of document travel to represent the next peak position (if any); however, if an actual peak is detected, the position of the next clock is adjusted to the speed derived from the detected peak. Thus, the system follows the motion or speed of the MICR characters rather than the speed of the document. This aspect will become clearer after a discussion of the read circuit 24. The read circuit 24 is shown in more detail in Fig. 3. The output of the read head 20 is amplified and filtered in circuit 30, and the output of circuit 30 is fed into an A/D converter 32 which produces a binary output which is clocked into one of the data storage registers DR-1 through DR-8 as will be described hereinafter. The output of the A/D converter 32 passes through a peak detector 34 associated with it. The output of the peak detector 34 is fed into a peak store clock circuit 36 which also receives the system clock (M clock) , the document present signal from sensor 22, and the pulses from the shaft encoder 25. In general, the peak store clock circuit 36 is used to clock data coming from the A/D converter 32 and the peak detector 34 into the data storage registers DR1 through DR-8. The data coming from the A/D converter 32 is made available to each of the data storage registers DR-1 through DR-8 over conductors or lines shown as line 38. Notice that the data storage registers DR-1 through DR-8 store both positive and negative data for the positive and negative-going peaks which are anticipated in the system. The signal sampling circuit 138 is used to determine whether the data from the A/D converter 32 is a positive value, negative value, or essentially a substantially zero value. These aspects and the remaining portion of the circuit shown in Fig. 3 will be discussed hereinafter. A portion of the peak store clock circuit 36 shown in Fig. 3 is designated as circuit portion 40 and is shown in Figs. 4A and 4B. In order to describe this circuit portion 40, it is convenient to describe it generally in relation to processing a document 12, and thereafter, the specific details of clocking and control signals for the various major components will be given. One of the problems of prior art systems of reading MICR data on documents was that it was difficult and expensive to maintain the speed of the document at a constant velocity while reading the MICR data. Even in those prior art systems which used a shaft encoder to sense changes in the speed of the document, it was possible for errors in reading to result. For example, suppose that there was some slip developed between the document being moved and the drive roller which drove it. The shaft encoder which was coupled to the drive roller would indicate that there was movement of the document; however, in fact, the document would not have moved. Because the shaft encoder indicated movement, the output of the shaft encoder would be used to produce a clocking signal for clocking the "expected peak" into appropriate storage registers for a subsequent character recognition operation. However, the "expected peak" would not be located at the associated read head, and consequently, this peak would be missed, and a misread would result. In contrast with the reading problem mentioned in the previous paragraph, this invention utilizes the magnetic peaks themselves from reading a waveform for the updating or adjusting of the clocks which are used to clock or strobe the oeak data on the associated data lines into storage registers. The present invention uses a shaft encoder to obtain a nominal velocity of the carrier or document; however, to repeat, the actual magnetic peaks are used to adjust the clocks, when necessary. The adjusted clocks are then used to strobe the positive peak values, negative peak values, and substantially zero values on the data lines into the storage registers. In the embodiment described, E13B font MICR characters are read; however, the principles of this invention may be extended to other magnetic waveforms. As seen from Fig. 2, the first peak in E13B font is always a positive going peak, and clock CL-0 is used to strobe this peak data into storage or data register DR-1 shown in Fig. 4B. Clocks CL-1 through CL-7 are used to strobe the remaining positive peak values, negative peak values, and substantially zero peak values into the data registers DR-2 through DR-8, respectively. Clock CL-8 relates to the end of a character and clock CL-9 simply provides inter- character spacing; these two clocks are not important from a character recognition standpoint. Each data register DR-2 through DR-8 is capable of storing positive or negative values as shown in Fig. 3; however to simplify the drawing, only the data registers for storing positive values are shown in Fig. 4B. Fig. 10 will be used to describe how the positive and negative peak values and substantially zero peak values are handled. This aspect will be discussed later herein. With the data values in the data registers DR-1 through DR-8, these data values can be examined, conventionally, by recognition logic 39 to determine the character represented by the associated magnetic waveform. The reading of MICR data on a document 12 is started when the leading edge of the document reaches the sensor 22 located just ahead of the read head 20 as shown in Fig. 1. In this situation, the sensor 22 issues a document present (DP) signal (Fig. 5A) which passes through the NAND gate 42 and OR gates 44 and 46 to reset the counters A-l, A-2, 48, and 50. Counters A-l and A-2 are used, alternately, to obtain a count which reflects the nominal velocity of the carrier or document 12 as it moves in reading relationship with the read head 20. Counter 48 is used to start and stop the counting by counter A-l, as will be described hereinafter, and counter 50 is used, similarly, with counter A-2. While the counters A-l and A-2 are enabled, their outputs are not utilized until after a first positive going peak from a character being read is obtained. As the document 12 is moved in the document track 14, the read head 20 encounters the first positive going peak (PD) for the first character to be read. The peak detect signal comes from the peak detector 34 (Fig. 3), and it is inverted, as shown by inverter 52 in Fig. 4A-4, to produce the PD/ signal shown in Fig. 4A. The PD/ signal is opposite to the PD signal and is read as PD "Bar". The PD/ signal is inverted by the inverter 54 and is fed into the flip flop 56. The output from the inverter 54 is also fed through the AND gate 58 to clock (CL-O) or strobe the data on the data lines 60 into the data register DR-1. Notice that the data lines 60 coming from the peak detector 34, shown in Fig. 3, are fed into all the registers DR-1 through DR-8; however, at this time, it is only the first register DR-1 which stores the data due to the PD signal being used to clock the value of the positive peak into this register. The first PD signal is also used to obtain a control signal PDO which remains at a high level during the reading of a single character. The PDO signal is derived from the Q output of the flip flop 56, and the Q output remains at this high level until the flip flop is reset by the master reset signal RM. The RM signal occurs at the end of reading each character. The function of the resistor Rl, the capacitor Cl, and the AND gate 62 will be discussed hereinafter; for the moment, it is sufficient to show how the first PD signal is used and how the PDO signal is derived. The PDO signal is used to condition the AND gate 64 (FIG. 5A) to enable the Q counter to start upcounting master clock or M CLK pulses. These same M CLK pulses are fed into the A-l and A-2 counters (Fig. 5A) under conditions to be later described herein. The shaft encoder 25 (Fig. 1), counters A-l and A-2, the selectors 66 and 68, and the comparator 70 (Fig. 5B) are the principal components of a means for generating a first count which reflects the speed of the document 12 as it is moved in reading relationship with the read head 20. As a general explanation, the first count which is placed alternately on counters A- 1 and A-2 is fed into the P0-P7 inputs of the comparator 70. The remaining Q0-Q7 inputs of the comparator 70 are coupled to the Q1-Q7 outputs of the Q counter. When the rising output of the Q counter equals the the first count which was placed on the P0- P7 inputs of the comparator 70, a P=Q or clock signal is generated at the output of the comparator 70. This P=Q signal will ultimately be used to clock a value on the data lines 60 (Fig. 4B) into the appropriate data storage register DR-2 through DR-8. In other words, the Q counter is part of a means for developing a nominal time period which is equivalent to the first count and also for generating a clock signal (P=Q) which is used (after some manipulation) for clocking data into the data registers DR2 through DR8. As P=Q signals are generated, they are routed through an early peak circuit 72 (Fig. 5B), and then, they are fed into a counter 74. The A-D outputs of - li ¬ the counter 74 are fed into a decoder 76. If the P=Q signal discussed in the previous paragraph were the first one generated, the A output of the counter 74 would rise to a high level, indicating a count of one. Subsequently, the Yl output of the decoder 76 would fall to a low level and be inverted by the inverter 78 to generate clock CL-1. The clock CL-1 is fed into a one shot delay 80 shown in Fig. 4B. After a predetermined delay, the clock CL-1 passes through the AND gate 82 and the logic circuitry 83-1 (to be later described herein) and is used to clock the data value on the data lines 60 into data register DR-2 in the example being described. In essence, the one shot 80 (Fig. 4B) provides a slight delay to "catch" a positive or negative peak value which comes a little later than anticipated. Conversely, the early peak circuit 72 (Fig. 5B) is used to handle the processing of a positive or negative peak value which comes earlier than the anticipated or nominal value. These aspects will be discussed in more detail hereinafter. Having described, generally, the operation of the read circuit 24, it seems appropriate to discuss the details of the circuit. In this regard. Fig. 6 shows the waveform output of the shaft encoder 25, which waveform consists of a plurality of SE pulses as shown. In the embodiment described, one such SE pulse occurs for each 0.0125 inch (0.31 mm) of document travel, and the document 12 moves past the read head 20 at a nominal speed of 100 inches (2.54 metres) per second. In describing the operation, assume that the first positive going pulse has occurred as previously described. This means that the PDO signal (Fig. 5A) , which is derived from the first PD signal, will remain at the high or active level for the duration of reading a character. The PDO signal conditions the Q counter to count only after the first positive peak has occurred; this means that the Q counter will begin to function to produce the P=Q pulses mentioned only after the reading of a character has begun. Continuing with the reading of a character, the rise of the first SE pulse (Fig. 6) conditions the AND gate 84 (Fig. 5A) to permit the next M CLK pulse to reach the counter 48. Counter 48 is a binary 2 counter. After the first count is registered on the counter 48, its A output rises to a high level, indicating a count of "one." The high level at the A output of counter 48 conditions the AND gate 86, permitting the M CLK pulses to be counted by the A-l counter. The A-l counter continues to count pulses until the next pulse or SE pulse 2 from the shaft encoder 25 occurs. As an illustration, there may be 40 pulses counted by the A-l counter between the occurrences of the first and second SE pulses as shown by the line marked counter A-l in Fig. 6. The first count of 40 reflects the speed of the carrier or document 12 as it is moved past the read head 20. When the second SE pulse occurs, as discussed in the example described in the previous paragraph, a count of two is registered on the counter 48. This means that the A output of the counter 48 falls to a low level, and the B output thereof rises to a high level. A low level on the A output just mentioned stops the flow of M CLK pulses to the A-l counter via the AND gate 86, leaving the first count of 40 thereon as discussed in the previous paragraph. The high level RT-1 output from the counter 48 is inverted by the inverter 88 (Fig. 4A-3) to produce a low level active Select signal which is fed into the Gl inputs of the selectors 66 and 68 (Fig. 5A) . The selectors 66 and 68 are wired together to produce a composite selector which shall be referred to hereinafter as selector 66-68. With the Select signal to selector 66-68 (Fig 5B) at a low level, that data which is on its inputs Al through Dl will be forwarded to the P0-P7 inputs of the comparator 70 (Fig. 5B) . In this example being discussed, the data on the comparator 70 is the first count of 40 which was obtained from the A-l counter. The data clock D CLK is used to clock the data into the selector 66-68. Notice from Figs. 4A and 4B that the first positive going peak produces the PDO signal already discussed. Notice also that the PDO signal and the SE signal are fed through the AND gate 90 (Fig. 4B) to generate the D CLK signal. This means that data from the A-l counter, for example, can be clocked into the selector 66-68 only after the first positive peak is detected, indicating the start of a new character. Each time a peak is detected by the peak detector circuit 34, that signal is fed through the OR gate 92 (Fig. 5B) to the AND gate 94. When the next M CLK falls to a low level, this signal is inverted by the inverter 96 and sent to the conditioned AND gate 94, causing the Q counter (Fig. 5A) to be reset. The Q counter then counts the M CLK pulses on its input, and this count is forwarded to the Q0-Q6 inputs of the comparator 70. When the count on the Q counter reaches the first count of 40 which appears on the P0-P7 inputs of the comparator 70 in the example described, the comparator issues a P=Q signal. For the moment, it is sufficient to state that the P=Q signal passes through the OR gate 98 in the early peak circuit 72 (Fig. 8) and is fed into the counter 74. Because this is the first P=Q signal in the example described, the A output or "1" output of the counter 74 will rise to a high level. The outputs of the counter 74 are coupled to the A, B, and C inputs of the decoder 76 as shown in Fig. 5B. A count of one on counter 74 corresponds to clock CL-1 coming from the Yl output of decoder 76. Correspondingly, a count of 7 on the counter 74 corresponds to clock CL-7 coming from the Y7 output of the decoder 76. A count of eight coming from the D output of the counter 74 corresponds to clock CL-8 which is associated with the portion of a character waveform which is near zero and the end of a character as shown in Fig. 2. The D or 8th count from the counter 74 is inverted by the inverter 100 and fed into the NAND gate 102 to condition the counter 74 to start counting when the next character to be read is encountered. The 8th count from the counter 74 is also used to obtain a master reset RM from the output of NAND gate 102. The RM/ signal is obtained by passing the RM signal through the inverter 104. Continuing with the example being discussed in the previous paragraph, assume that no peak data appeared on the data lines 60 at the exact time that the clock CL-1 was developed at the output of the decoder 76. In other words, suppose that the peak 106, shown in Fig. 2, came after the clock CL-1 was generated instead of having it occur at the time that clock CL-1 was generated as shown literally in Fig. 2. This would mean that no peak data would be on the data lines 60 when the clock CL-1 arrived, and a misread would result. In order to avoid a loss of data, a slight delay is introduced to the clock CL-1 by the one shot 80 (Fig. 4B) as previously discussed. A capacitor C2 and a variable resistor R2 are used to conventionally delay the clock CL-1 by about 50% of the nominal time between clocks. When the active high level clock CL-1 arrives at the one shot 80 (Fig. 4B), the Q/ output thereof switches to a low level, and at the end of the delayed period, the Q/ output switches to a high level. The high level from the Q/ output passes through AND gate 82 to clock the peak value data on data lines 60 into the DR-2 register in the example being described. As previously stated, there is a data register, like register DR-2, for each of the remaining data values and their associated clocks CL-3 through CL-7, with only registers DR-1, DR-2, and DR-8 being shown in Fig. 4B to simplify the drawing. Similarly, there is a one shot and related components for the remaining clocks CL-2 through CL-7; however, only the one shot 108, AND gate 109, capacitor C7, and resistor R7 for clock CL-7 are shown. While only data registers are shown for storing the positive peaks in Fig. 4B, it should be recalled that there are data registers for storing the negative peaks as shown in Fig. 3. The positive and negative peaks are clocked into the appropriate portion of the data register as will be described hereinafter in conjunction with Figs. 10A and 10B. To review some of the clocking and control pulses associated with the generation of the first clocking pulse CL-1 in the example being described, attention is directed to Figs. 5A, 5B, 6, and 7. Figs. 6 and 7 show various waveforms associated with the portion of the circuit shown in Figs. 5A and 5B. It should be recalled that the first count associated with clock CL-1 accrues on the A-l counter and the A-2 counter, with a count of 40 being shown on the A-l counter in Fig. 6. Notice from Fig. 6 that a count occurs on the A-l counter during the time that the A output of the associated counter 48 is at a high level, indicating a count of one. When the SE pulse 2 occurs, the B outputs of both counters 48 and 50 will rise to a high level. A high B output level at counter 48, passing through the inverter 88 in Fig. 4A-3, produces a low level select signal for selector 66-68 as previously described. The low level select signal on selector 66-68 selects the data or count on the A-l counter, and contrastingly, a high level select signal selects the data or count on the A-2 counter. Continuing with a discussion of the example described in the previous paragraph, the Yl signal (active-low) from decoder 76 (Fig. 5 B) would be developed as previously described to produce clock Cl-1. The Yl signal and the remaining Y2-Y7 signals are used in controlling the selection of data from the A-l and A-2 counters. At the time of the generation of Yl, the Y3, Y5, and Y7 outputs from decoder 76 are at an inactive or high level. These Yl, Y3, Y5, and Y7 outputs are fed into the NAND gate 110 shown in Fig. 4A-1, and because Yl is at a low level, a high level output is generated by the NAND gate 110. This high level is fed into AND gate 112, which is already conditioned by the high level RT-1 output from the counter 48, to produce the Rl output from AND gate 112. This newly developed Rl signal is fed into the OR gate 46 (Fig. 5A) to reset the A-l counter and the associated counter 48. The B output of the counter 48 now falls to a low level, and this low level signal is fed through the inverter 114 to condition the AND gate 84. This permits the A-l counter to start developing a new count which reflects the velocity of the document moving past the read head 20. At this time, the signal R2, which is fed into the OR gate 44 (Fig. 5A) , is at a low level, and consequently, the A-2 counter and the counter 50 are not reset. This means that the count which is on the A-2 counter will be used as the nominal speed value or count for the development of clock CL-2. Continuing with the example discussed in the previous paragraph, the R2 signal is at a low level because the Y2, Y4, and Y6 signals coming from the decoder 76 (Fig. 5B) are at a low level. These Y2, Y4, and Y6 signals are fed into the NAND gate 116 (Fig. 4A-2) , resulting in the output from the NAND gate 116 and the output from the AND gate 118 (R2) being at a low level. The R2 signal remains at a low level until the generation of the Y2 signal which is developed from the second P=Q signal. As a summary of the timing of the operation of the read circuit 24 as discussed in relation to Fig. 7, the following activities occur: 1. Shaft encoder signal SE rises to a high level. 2. The A-l and A-2 counters start to accumulate the first count after being reset by the document present signal DP. 3. The counting on the A-l and the A-2 counters terminates upon the occurrence of the next occurring SE. 4. The output B of counter 48 rises to a high level upon the occurrence of the SE signal discussed in the previous activity, selecting the count on the A-l counter. 5. There may be several SE signals before the first positive going pulse PD is encountered. 6. The first positive going peak PD is detected, indicating the start of the first character to be read. 7. The PD signal is used to generate the PDO signal and to reset the Q counter. 8. The PDO signal and the next SE signal (SE 2 in Fig 7) are used to generate the D CLK to clock the data or first count from the A-l counter into the comparator 70. 9. The PDO signal also conditions the Q counter to start upcounting to the first count on the comparator 70. 10. The P=Q signal is issued from the comparator 70 when the count on the Q counter equals the first count. 11. The P=Q signal passes through the early peak circuit 72, the counter 74, and the decoder 76 to produce Yl and clock CL-1. 12. The Yl signal is used to develop the Rl signal which is used to reset the A-l counter and counter 48. 13. The RT-1 signal from counter 48 falls to a low level to select the count from the A-2 counter. 14. The P=Q signal is also used to reset the Q counter which starts upcounting. 15. The next SE pulse (3 in Fig. 7) is used to clock (D CLK) the count from the A-2 counter into the comparator 70. 16. The rising count on the Q counter now approaches the count on the comparator 70. 17. The second P=Q signal from the comparator is issued when the count on the Q counter equals the count on the comparator 70. IS. The second P=Q signal is used to generate the Y2 signal and the clock CL-2 signal and to reset the Q counter. 19. The Y2 signal is used to develop the R2 signal which resets the A-2 counter and counter 50. 20. The next SE pulse (4 in Fig. ) shuts off the count to the A-l counter and generates the D Clk signal which clocks the count on the A-l counter into comparator 70. 21. The third P=Q in the example being described is generated. Notice from what has been described in the timing summary that the nominal clocks are developed from the counts which are recorded alternately on the A-l and A-2 counters. The A-2 counter has an inverter 120, an AND gate 122, and AND gate 124 associated with it to enable the A-2 counter to function in a manner similar to that already described in relation to counter A-l. The RT-2 output from the counter 50 is not used because the high and low outputs of the B output (RT-1) of counter 48 are used by the selector 66-68 to provide the selection of the counts from the A-l and A-2 counters, respectively. Notice also from Figs. 5A and 5B that the Q counter is reset upon the generation of a P=Q signal or the PD signal. The P=Q signal is used to develop the clocks CL-1 through CL-7. When the associated PD signal comes late, or after the generation of a nominal clock pulse, the PD signal is used to reset the Q counter. This means that if the document were travelling slower than the nominal speed, the count on the A-l or A-2 counters might be 44 instead of the usual 40 which represents the nominal count in the example being described. In a situation like this, the Q counter would be reset by the P=Q signal, and it would immediately start to register a count via the M CLK and AND gate 64. After the peak associated with a P=Q signal is generated, this peak itself is used to generate a PD signal which is used to reset the Q counter. The count which was on the Q counter is "lost", and consequently, a little more time than normal will be taken by the Q counter to match the count of 44 from one of the A-l and A-2 counters in the embodiment described. In a sense, the count which is "lost" on the Q counter represents the delay or lag in time between when the peak was nominally expected and when it actually occurred. If a peak occurs at the expected nominal time, then both the P=Q signal and the associated PD signal occur at substantially the same time. With both the P=Q and PD signals entering the OR gate 92 (Fig. 5B) at the same time, there would be only one resetting of the Q counter. Notice that the clocking signals are updated by the magnetic peaks themselves; this is a feature of this invention. Another feature is that the nominal clock or P=Q signal is updated by using the varying counts which are registered upon the A-l and A-2 counters as the speed of the motor driving the document changes. Another situation which needs to be discussed relates to those times in which a positive or negative peak value comes before the associated P=Q signal. When the peak value comes early, it means that the Q counter will be reset prior to upcounting to the nominal count from the A-l or A-2 counters. This means that a normal P=Q signal would not be generated, and accordingly, the associated clock and Y signals, like CL-3 and Y3, for example, would not be generated. To provide for this situation, the early peak circuit 72, alluded to earlier herein, is utilized. The early peak circuit 72 is shown in detail in Fig. 8, and it includes the AND gates 126, 128, and 130 and the OR gate 98 which are coupled as shown. The Ql/ through Q7/ signals shown are derived from the Q/ outputs of the one shots (like 80 shown in Fig 4B) associated with the generation of clocks CL-1 through CL-7. The Ql/ through Q7/ outputs remain at a high level until the associated clock, like CL-1, is received. After the occurrence of the first positive going peak, the PDO signal remains at a high level for a character, and this high level conditions AND gate 130. When a peak comes early, it is fed through AND gates 128 and 130 and the OR gate 98 to produce a count on the counter 74 in the same manner as does a typical P=Q signal passing through the OR gate 98. The P=Q signal coming out of the OR gate 98 is also used to reset the Q counter as previously described. The early peak circuit 72, shown in Fig. 8, also provides another function in addition to the one discussed in the previous paragraph. This function is to prevent a second P=Q signal from being developed when an actual peak comes later than its associated P=Q signal. For example, if the third peak (actual) comes after the associated third P=Q signal is generated, clock CL-3, which is fed into the associated one shot, causes the Q/ output of the associated one shot to fall to a low level. This low level Q3/ stops AND gate 126 from conducting, which in turn stops AND gate 130 from conducting to thereby prevent the late PD signal which is associated with the third clock CL-3 from producing a signal which is equivalent to another P=Q signal. Another point to be clarified relates to the delay introduced by the capacitor Cl and the resistor Rl associated with the input to the flip flop 56 (Fig. 4A) as alluded to earlier herein. This point relates to the first peak detect signal PD and the use- of this signal in the early peak circuit 72 shown in Fig. 8. Basically, it is necessary to prevent the generation of an output from the early peak circuit 72 for the first positive going peak which occurs at the start of reading a character. It should be recalled that the first positive going peak occurs for all characters to be read, and it is really the second and subsequent peaks which provide for the identification of a character. Fig. 9 shows the relationship of certain signals which prevent the generation of an output from the early peak circuit 72 as discussed in the previous paragraph. The PD and PD/ signals are shown along with their relationship to the PD-1/ signal which is present at the D input of the flip flop 56 (Fig. 4A) . The PD-1/ signal is delayed slightly with respect to the PD/ signal. Notice that the PD signal (Fig. 9) falls at line 134 prior to the rise of the PD-1/ signal as shown by line 136. This means that the output of the AND gate 128 (Fig. 8) falls to a low level (before the PDO signal rises to a high level) to thereby shut off the AND gates 128 and 130, thereby precluding an output from the early peak circuit 72 for the first PD signal. Notice that the PDO signal shown in Fig. 8 is generated by the PD-1/ signal which is fed into the flip flop 56 shown in Fig. 4A. Figs. 10A and 10B show the logic circuit 83-1 alluded to in the discussion of the portion of the circuit 24 shown in Fig. 4B. There is one such logic circuit like 83-1 provided for each of the clocks CL-1 through CL-7 shown in Fig. 4B r with logic circuit 83-1 being shown for clock CL-1 and logic circuit 83-7 being shown for clock CL-7. The function of the logic circuit 83-1, for example, is to provide the actual clocking signal which is used to clock the positive peak value, negative peak value or substantially zero peak value into the appropriate positive or negative register as generally described. Only the positive peak values are stored in the positive peak registers DR-2 through DR-8 (+VE PK) while the negative peak values and the substantially zero values are stored in the negative or no peak registers DR-2 through DR-8 (- VE PK) . Continuing with a description of Figs. 10A, and 10B, a conventional signal sampling circuit 138 is connected to the output of the A/D converter 32 (Fig. 3) and is used to determine whether a peak is positive or negative. For example, an output PP from circuit 138 which is a binary 1 is considered a positive peak value, and an output which is a binary 0 is considered a negative peak value or a substantially zero value. Each of the AND gates, like 82 and 109 shown in Fig. 4B has its own logic circuit, like 83-1, associated with it. For example, the logic circuit 83-1 includes the AND gates 140 and 142 and the inverter 144 which are coupled as shown in Fig. 10A. The operation of the logic circuit 83-1 shown in Fig. 10A is as follows. Because the first peak in waveform of a character being described is always a positive peak value, that value is always stored in the data registe DR-1 as previously described. If the second peak value is a positive value, the output (PP) from the signal sampling circuit 138 (Fig. 3) will be a binary one. Notice from Figs. 10A and 10B that the PP signal is fed to all the logic circuits 83-1 through 83-7. With a binary one value on the AND gate 140 in the example being described, and with a binary one coming from the output of the AND gate 82, a high level output from the AND gate 140 will clock the peak value data on the data lines 60 into the register DR-2. If, in the example being described, the first peak value after the first positive peak is a negative value or a zero value, then the PP signal will be at a low level. In this case, a low level PP signal is inverted by the inverter 144 causing a high level signal to be emitted from the AND gate 142 which was already conditioned by the high level output from the AND gate 82. A high level from the AND gate 142 clocks the negative peak value or substantially zero peak value appearing on the data lines 60. Each of the logic circuits 83-1 through 83-7 is the same. The logic circuit 83-7 also shown in Fig. 10B has an inverter 146 and AND gates 148 and 150 which operate in the same manner as that already explained in relation to logic circuit 83-1.

Claims: Claims : 1. Apparatus for use in reading magnetically encoded characters on a carrier (12) , with each said character having a waveform which starts with a positive peak value, and with the waveforms of said characters being composed of predetermined patterns of positive peak values, negative peak values, and substantially zero values occurring at predetermined clocking periods to identify a particular waveform as representing a particular character, characterized by: data register means (DR-1 to DR-8) adapted to store said positive peak values, negative peak values and substantially zero values when clocked therein; a clocking circuit adapted to clock said positive peak, negative peak, and substantially zero values into said data register means (DR-1 to DR-8) at times corresponding substantially to the times of the occurrences of said positive peak, negative peak and said substantially zero values; said clocking circuit having generating means including a shaft encoder (25) and adapted to generate a nominal clock signal defining a nominal count period for each of said positive peak, negative peak, and substantially zero values, and adjusting means adapted to utilize a positive peak value or a negative peak value itself for adjusting the occurrence of an associated said nominal clock signal to generate an adjusted clock signal (CL-1 to CL-7) which is used to clock the associated said positive or negative peak value into said data register means (DR- 1 to DR-8) . 2. Apparatus according to claim 1, characterized by reading means (20) adapted to generate said waveforms when a carrier (12) with said characters thereon is moved in reading relationship with said reading means (20), and converting means (32, 34) adapted to convert a waveform from said reading means (20) into said positive peak, negative peak, and substantially zero values and to place these values on data lines (60) associated with said converting means (32, 34). 3. Apparatus according to claim 2, characterized in that said generating means includes: first counting means (A-l, A-2), adapted to generate a first count which reflects the speed of said carrier (12) as it is moved in reading relationship with said reading means (20), with said first count varying in accordance with the speed of said carrier (12) as determined by said shaft encoder (25); and in that said adjusting means includes second counting means (Q) adapted to control the shortening of said nominal time period when a said positive or negative peak value comes before the end of said nominal time period to generate a said adjusted clock signal (CL-1 to CL- 7) to clock the value on said data lines (60) into said data register means (DR-1 to DR-8), and also to control the lengthening of said nominal time period when a said positive or negative peak value comes after the end of said nominal time period to generate a said adjusted clock signal (CL-1 to CL-7) to clock the value on said data lines (60) into said data register means (DR-1 to DR-8). 4. Apparatus according to claim 3, characterized in that said shaft encoder (25) produces successive outputs which are related to the speed of said carrier (12), and in that said first counting means includes first and second counters (A-l, A-2) adapted to generate said first count and also includes third and fourth counters (48, 50) coupled to said first and second counters (A-l, A-2), respectively, and adapted to limit the count on said first and second counters (A-l, A-2) to that which occurs between successive outputs from said shaft encoder (25). 5. Apparatus according to claim 4, characterized in that said first counting means also includes a selector (66, 68) adapted to alternately select the first counts from said first and second counters (A-l, A-2). 6. Apparatus according to claim 5, characterized in that said adjusting means includes a comparator (70) adapted to receive the first count alternately from said first and second counters (A-l, A-2) and a count from said up counter (Q) and to cause the generation of said nominal clock signal when the count on said up counter (Q) equals the count applied to said comparator (70) from said first or second counter (A-l, A-2). 7. Apparatus according to claim 6, characterized in that said adjusting means includes an early peak circuit (72) adapted to generate a said adjusted clock signal (CL-1 to CL-7) when a positive or negative peak value comes before the end of a nominal time period. 8. Apparatus according to claim 5, characterized in that said adjusting means includes reset means (92, 94, 96) to reset said up counter (Q) upon the occurrence of a positive or negative peak value which follows the generation of a said nominal clock signal.

Inventors: MAZUMDER ALI TAZAMMUL, MAZUMDER, ALI, TAZAMMUL
Applicants: NCR CO, NCR CORPORATION
Application year: 1989
Main classification: G06K9
IPC codes: G06K9, G06K17