Clock signal switching device of an IC card

Abstract: When an IC card (1) is attached to a terminal unit (30), a counter (17) counts pulses of an external clock signal and a switching circuit (20) outputs the external clock signal to an internal circuit (5) in place of an internal clock signal if a NAND gate (18) determines that the count of pulses of the external clock signal by the counter (17) is a predetermined value. When the IC card is ejected from the terminal unit, pulses of the internal clock signal are counted by a counter (7) and when the count attains a predetermined value, the counter (17) is cleared and the switching circuit outputs the internal clock signal to the internal circuit in place of the external clock signal in response to the output of the NAND gate (18). Thus, it can be correctly determined whether the IC card is operated in the form of a single body or in the form attached to any terminal unit.

Description: The present invention relates to a clock signal switching device for an IC card. More particularly, the present invention relates to a clock signal switching device for an IC card for switching from an internal clock signal to an external clock signal supplied from a terminal unit, whereby an IC card operable in response to the internal clock signal can operate in response to the external clock signal in place of the internal clock signal when the IC card is attached to the terminal unit. IC cards provided with displays are utilized in various fields these days. Such an IC card is operable not only as a single card but also when attached to a terminal unit. For these purposes, an IC card contains a battery, an internal clock signal generating circuit for generating an internal clock signal, and a processing circuit and, when operated as a single card, the processing circuit operates in response to the internal clock signal. When such a card is attached to a terminal unit, external power is supplied from the terminal unit to the IC card and an external clock signal is also supplied thereto. The processing circuit in the IC card operates in response to the external clock signal. Thus, switching between the clock signals is required to apply the internal clock signal when the IC card is to operate in the form of a single card and to apply the external clock signal when the IC card is attached to the terminal unit. For those purposes, it is necessary to determine whether the IC card is operated as a single card or it is connected to a terminal unit. Methods for such determination include a method of detecting a mechanical contact of an external terminal provided in the IC card, and a method of detecting a difference between the voltage of the battery contained in the IC card and that of the external power supplied when the card is attached to the terminal unit. However, in view of the structure of an IC card in general, it is difficult to attach a detector to its external terminal for the purpose of detecting the above mentioned mechanical contact. The method of detecting the difference between the respective voltages cannot always be utilized, for example, in cases in which there is only a small difference between the voltage of the battery contained in the IC card and the voltage of the external power supply. This is because when noise is present when using the IC card as a single card, it is often erroneously determined that the card is attached to a terminal unit, thus causing errors in operation. If an IC card is forcibly ejected from the terminal unit during communication of data between the card and the terminal unit, switching from the external clock signal to the internal clock signal occurs abruptly, causing a disorder in the program contained in the IC card. FR-A-2 596 897 discloses an IC card comprising the features of the preamble of claim 1 which can be connected to a card terminal and can also be operated independently using a battery built in the IC card. The IC card includes a switching circuit arranged to select one of a clock signal supplied by the terminal and another clock signal of much lower frequency generated by an oscillator built in the IC card. The switching circuit detects power supplied from the terminal. When the power is detected, the switching circuit selects the clock signal supplied by the terminal. Such an arrangement is disadvantageous, since the switching operation presupposes that the clock signal is supplied to the IC card when the terminal power is detected, whereas, for example, a faulty or poor connection of the IC card to the terminal may prevent supply of the terminal clock signal to the IC card. In these circumstances, the circuitry of the IC card would receive no clock signal from either the terminal or the in-built oscillator, and would therefore not operate. GB-A-2 080 585 discloses a semiconductor integrated circuit having a single clock signal scource consisting of an oscillator and a timing generator. When a battery voltage becomes unacceptably low, the operations of the oscillator and the timing generator are stopped to reduce power consumption. When the battery voltage recovers, the oscillator is re-started. However, in order to ensure stable operation, the timing generator is not restarted (and does not therefore output the clock signal) until a predetermined number of oscillation cycles has been counted by a counter. The invention addresses at least some of the problems encountered in the prior art. According to the present invention there is provided a portable electronic device having an internal clock source, means for receiving clock pulses from an external clock source, and switch means for switching a circuit of the device between a first mode in which the circuit is responsive to the internal clock source and a second mode in which the circuit is responsive to the external clock source, characterised in that the switch means is arranged to operate in response to reception of a predetermined number of the external clock pulses by the receiving means for switching the circuit from the first mode to the second mode and to operate in response to combined non-reception of the external clock pulses by the receiving means and reception of pulses from the internal clock source for a predetermined time period for switching the circuit from the second mode to the first mode. This arrangement advantageously ensures that a clock signal is supplied to said circuit of the IC card irrespective of whether the IC card is utilized as a single card or is attached to a terminal unit. Additionally, it can be correctly determined whether the IC card is operated as a single card or it is attached to a terminal unit. Furthermore, by arranging that the switch means switches from the first mode to the second mode in response to the reception of a predetermined number of the external clock pulses, it can be ensured that the external clock signal input to the device will have stabilised by the time said predetermined number of external clock pulses have been received by said receiving means. Also, by arranging that the switch means switches the circuit to the first mode in response to combined non-reception of external clock pulses by said receiving means and reception of pulses from the internal clock source for a predetermined period, an abrupt change from the external clock signal to the internal clock signal is avoided and disorder in the operation of the device is inhibited. An embodiment of the present invention will now be described, by way of example only, with reference to the accompanying drawings. Figs. 1A and 1B are block diagrams showing schematically the general construction of an IC card according to an embodiment of the present invention and a terminal unit. Figs. 2A and 2B are specific circuit diagrams of the embodiment of the present invention. Figs. 3, 4 and 5 are timing charts for explaining operation of the embodiment of the present invention. Figs. 1A and 1B are block diagrams showing an entire construction of an embodiment of the present invention. Referring first to Figs. 1A and 1B, the construction of the embodiment of the invention will be described. An IC card 1 has an external terminal set 2. This external terminal set is used to electrically connect the IC card 1 to a terminal unit 30 when the card 1 is attached thereto. An external power, an external clock signal and an external reset signal are applied from the terminal unit 30 through respective terminals 2a, 2b and 2c of the external terminal set 2. Those external power, the external clock signal and the external reset signal are applied to a clock switching circuit 3. An internal oscillation circuit 4 is provided to generate an internal clock signal. The clock switching circuit 3 switches between an internal clock signal generated from the internal oscillation circuit 4 and the external clock signal inputted through the external terminal set 2 and applies the signal selected by the switching circuit to an internal circuit 5. When the IC card 1 is not attached to the terminal unit 30, electric power is supplied from a battery 28 to the clock switching circuit 3, the internal oscillation circuit 4 and the internal circuit 5. Figs. 2A and 2B are specific circuit diagrams of the embodiment of the invention. Referring first to Fig. 2A, a counter 17 is provided to output signals Q4 and Q5 for outputting a signal p of a low (L) level from a NAND gate 18 and a signal p of a high (H) level from an inverter 19 in response to the count of a predetermined number of pulses of an external clock signal f out . A switching circuit 20 is used to switch between an internal clock signal f in and the external clock signal f out in response to the signal p, so that either clock signal is outputted as a system clock  to the internal circuit 5 shown in Fig. 1 and to a counter 21. The counter 21 is provided to output signals F1 to F4 for forming timing signals ACLR and ACL′ by means of gates 22 and 23 and a latch circuit 24. Referring to Fig. 2B, a counter circuit 7 is reset by an external clock signal f out , counts pulses of the internal clock signal f in and generates timing signals ARQ0 to ARQ2 for forming a signal AR. A latch circuit 12 is latched by an external reset signal and it is reset by a signal ACLR which attains H level after several cycles from the switching from the internal clock signal f in to the external clock signal f out . A synchronizing circuit 13 is provided to generate a signal ACL1 which synchronizes the output of the latch circuit 12 with clock signals 3 and 4 generated from the system clock . Figs. 3, 4 and 5 are timing charts for explaining a definite operation of this embodiment. Referring to Figs. 2A to 5, the definite operation of the embodiment will be described. First, in the case of operating the IC card 1 singly without being attached to the terminal unit 30, a power supply switch (not shown) provided in the IC card 1 is operated and then a power-on reset signal POR is applied to a reset input terminal of the counter 17 through an OR gate 16 shown in Fig. 2A, whereby the counter 17 is reset. The power-on reset signal POR is also applied to the counter 21 through an OR gate 25, whereby the counter 21 is reset. In consequence, the outputs Q4 and Q5 of the counter 17 are lowered to L level and the respective outputs are supplied to the NAND gate 18. The signal p outputted from the NAND gate 18 rises to H level and it is applied to one input terminal of the NAND gate 15. In consequence, this NAND gate 15 is opened. Further, the signal p is inverted by the inverter 19 to the signal p of L level, which is applied to the switching circuit 20. In response to this signal p, the switching circuit 20 selects the internal clock signal f in and outputs this signal as the system clock pulse  to the internal circuit 5 shown in Fig. 1. Then, in response to the system clock pulse , the internal circuit 5 carries out predetermined operation. Next, operation in the case of attaching the IC card 1 to the terminal unit 30 will be described. When the IC card 1 is attached to the terminal unit 30, the external power, the external clock signal f out and the external reset signal are applied from the terminal unit 30 to the external terminal set 2 of the card 1. The external reset signal of L level is inverted by the inverter 10 as shown in Fig. 2B and it is supplied as the signal ACL of H level to the OR circuit 11 as shown in (c) of Fig. 3. The OR circuit 11 outputs a signal ACLx of H level and in response to this signal, the latch circuit 12 is latched. The output of the latch circuit 12 is supplied to the synchronizing circuit 13 and the synchronizing circuit 13 synchronizes the clock pulses 3 and 4 with the output of the latch circuit 12 and outputs the signal ACL1 as shown in (j) of Fig. 3. This signal ACL1 is applied to one input terminal of the NAND gate 14. As a result, the NAND gate 14 is opened. The external clock signal f out as shown in (b) of Fig. 3 is applied to the other input terminal of the NAND gate 14. The external clock signal f out is applied to the NAND gate 15 through the NAND gate 14. At this time, the counter 17 is reset by the application of the signal ACLx outputted from the OR circuit 11 shown in Fig. 2B through the OR circuit 16 and, as shown in (f) and (g) of Fig. 3, the outputs Q4 and Q5 are respectively at L level. In consequence, the signal p outputted from the NAND gate 18 rises to H level as shown in (h) of Fig. 3, so that the NAND gate 15 is opened. As a result, the external clock signal f out is applied to the counter 17 through the NAND gate 15. The counter 17 starts counting pulses of the external clock signal f out . When a predetermined number of pulses of the external clock signal f out are counted, that is, when the outputs Q4 and Q5 of the counter 17 rise to H level, the signal p outputted from the NAND gate 18 falls to L level, whereby the NAND gate 15 is closed. As a result, the external clock signal f out is not applied to the counter 17. Thus, the counter 17 stops counting pulses of the external clock signal f out . On the other hand, the signal p of L level is inverted by the inverter 19 to H level and the signal of H level is applied to the switching circuit 20. In response to the signal p , the switching circuit 20 outputs the external clock signal f out as the system clock  to the internal circuit 5. At the same time, the system clock  is applied to the counter 21, so that the counter 21 outputs the timing signals F1 to F3 as shown in (c), (d) and (e) of Fig. 5. When all of the timing signals F1 to F3 attain H level, the AND gate 22 outputs the signal ACLR of H level as shown in (k) of Fig. 3 and (f) of Fig. 5 and the latch circuit 12 shown in Fig. 2B is reset by the signal ACLR. When the latch circuit 12 is reset, the synchronizing circuit 13 outputs the signal ACL1 falling to L level as shown in (j) of Fig. 3. The NAND gate 14 is closed by the signal ACL1 and the external clock signal f out is not applied to the NAND 15. The signal ACL1 is used to enable the internal circuit 5. More specifically, the internal circuit 5 is initialized in a period of H level of the signal ACL1 and after the signal ACL1 falls to L level, the internal circuit 5 operates. Thus, as shown in (j) of Fig. 3, since the signal ACL1 falls to L level after several cycles from the switching from the internal clock signal f in to the external clock signal f out , the internal circuit 5 operates stably and erroneous operation can be prevented. Referring now to the timing chart of Fig. 4, description will be made of the case in which the IC card 1 is forcedly removed from the terminal unit 30. When the IC card 1 is removed from the terminal unit 30, the external clock signal f out is no longer applied. On this occasion, the input terminal for the external clock signal f out is pulled up by a resistor 26 as shown in Fig. 2B and accordingly it is raised to H level. The signal of H level at this terminal is inverted by the inverter 27 and it is applied to the reset input terminal of the counter 7, whereby the counter starts counting pulses of the internal clock signal f in shown in (a) of Fig. 4. When the signals ARQ0 and ARQ2 of the counter 7 both rise to H level and the signal p rises to H level as shown in (b) and (d) of Fig. 4, the latch circuit 9 is latched and the signal AR outputted from the latch circuit 9 rises to H level as shown in (e) of Fig. 4. This signal AR is inputted to the OR circuit 11 and the signal ACLx outputted from the OR circuit 11 rises to H level as shown in (g) of Fig. 4, whereby the latch circuit 12 is latched. When the signal ACLx rises to H level, the counters 17 and 21 shown in Fig. 2A are reset and the NAND gate 18 outputs the signal p of H level, while the inverter 19 outputs the signal p of L level as shown in (h) of Fig. 4. In consequence, the switching circuit 20 selects the internal clock signal f in and outputs it to the internal circuit 5. Thus, when the IC card 1 is forcedly ejected from the terminal unit 30, switching occurs from the external clock signal f out to the internal clock signal f in and thereafter the signal ACL1 falls to L level, whereby the internal circuit 5 starts operation. As described in the foregoing, according to the embodiment of the present invention, when the IC card is attached to a terminal unit, pulses of the external clock signal supplied from the terminal unit are counted and, in response to counting of a predetermined number of pulses of the external clock signal, the external clock signal is selected and outputted in place of the internal clock signal. Accordingly, it can be correctly determined whether the IC card is operated in the form of a single body or in the form attached to any terminal unit. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being defined by the terms of the appended claims.

Claims: A portable electronic device having an internal clock source (4), means (2) for receiving clock pulses from an external clock source, and switch means (20) for switching a circuit (5) of the device between a first mode in which the circuit is responsive to the internal clock source and a second mode in which the circuit is responsive to the external clock source, characterised in that the switch means (20) is arranged to operate in response to reception of a predetermined number of the external clock pulses by the receiving means (2) for switching the circuit (5) from the first mode to the second mode and to operate in response to combined non-reception of the external clock pulses by the receiving means (2) and reception of pulses from the internal clock source for a predetermined time period for switching the circuit (5) from the second mode to the first mode. A device as claimed in claim 1, including a battery (28) and to which device electric power and an external clock signal are applied from a terminal unit (30) when said device is attached to said terminal unit (30), and wherein said switch means (20) comprises clock signal counting means (17) for counting pulses of said external clock signal supplied when said device is attached to said terminal unit (30), and for selecting and outputting said external clock signal in place of said internal clock signal when said clock signal counting means (17) counts said predetermined number of pulses of said external clock signal. A device as claimed in claim 2, further comprising input clock signal detecting means for detecting no input of said external clock signal and input of said internal clock signal, said switch means (20) further comprising means for outputting said internal clock signal in place of said external clock signal after said predetermined time period has elapsed from the first detection of no input of said external clock signal and input of said internal clock signal by said input clock signal detecting means. A device as claimed in claim 2 or claim 3, wherein said circuit comprises a processing circuit (5), and said switch means (20) comprises determining means (18) for determining that said clock signal counting means (17) counts said predetermined number of pulses of said external clock signal, and enable signal generating means (21,22) for outputting an enable signal for enabling said processing circuit (5) to operate after a predetermined time period has elapsed from the determination of said predetermined number of pulses of the external clock signal by said determining means. A device as claimed in claim 4, wherein said device includes a terminal (2c) for receiving an external reset signal for resetting said processing circuit (5), and said enable signal generating means includes means (13) for outputting said external reset signal as said enable signal in synchronization with said internal clock signal in response to the application of said external reset signal.

Inventors: KATSUTANI MASAFUMI, YAEGAWA KAZUHIRO, KATSUTANI, MASAFUMI, YAEGAWA, KAZUHIRO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1989
Main classification: G06K19
IPC codes: G06F1, G06K17, G06K19