Semiconductor memory device

Abstract: In a semiconductor memory device, a first load circuit (14A) is coupled with the column lines (BL1,..., BLn). first dummy cells (DC1,..., DCm) are connected to a dummy column line (DBL), a second load circuit (14B) is connected to the dummy column line, a second dummy cell (DCm+1) is connected to the dummy column line, and a sense amplifier (15) senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

Description: The present invention relates to a semiconductor memory device improved in a reference potential generating circuit for a sense amplifier and load circuits for memory cells. A conventional semiconductor memory device shown in Fig. 1 is an erasable and programmable ROM (EPROM) using floating gate MOSFETs as memory cells. In the figure, MC11, MC12, ..., MC1n designate floating gate MOSFETs; DC a floating gate MOSFET as a dummy cell; WL1, WL2, ..., WLm row lines; BL1, BL2, ..., BLn column lines; DBL a dummy column line; 11 a row decoder; 12 a column decoder; BT1, BT2, .., BTn column gate MOSFETs for column selection; DBT a MOSFET that is equivalent to the column gate MOSFET and is normally in a conductive state with application of a power voltage Vcc to the gate of the MOSFET; 13A a first bias setting circuit made up of n-channel MOSFETs QM1 to QM6; 14A a first load circuit made up of a p-channel MOSFET QM7; 13B a second bias setting circuit made up of n-channel MOSFETs QD1 to QD6; 14B a second load circuit made up of a p-channel MOSFET QD7; 15 a sense amplifier; and 16 an output buffer. In the description to follow, MOSFETs whose channels are not specified will be treated as n-channel MOSFETs. The dummy cell DC consists of a MOSFET equivalent to that of a memory cell MC that is any of the memory cells MC11 to MCmn. The dummy column line DBL is equivalent to the column line BL that is any of those column lines BL1 to BLn. A potential V1 at the output node of a low potential generating circuit formed of MOSFETs QM2 and QM3, which is lower than the power voltage Vcc, is applied to the gate of a MOSFET QM1 in the first bias setting circuit 13A. A potential V2 at the output node of a low potential generating circuit formed of MOSFETs QM5 and QM6, which is lower than the node potential V1, is applied to the gate of a MOSFET QM4. The node potential V2 is set at a voltage which is the sum of a potential on the column line BL when a predetermined current flows into the memory cell MC, and a threshold voltage of the n-channel MOSFET containing an increased threshold voltage due to the substrate bias effect. The MOSFET QM4 is an initial charging MOSFET for quickening an initial charging to the column line BL in which the column line BL is charged from an initial voltage 0 V. The initial charging MOSFET is rendered nonconductive when the column line potential exceeds a potential on the column line when a predetermined current flows into the memory cell MC. In the EPROM thus arranged, a reference potential Vref is generated by the second load circuit 14B on the basis of the data in the dummy cell DC, and appears at a node B. An input potential Vin is generated by the first load circuit 14A on the basis of the data read out of a memory cell MC as selected by the output signals of the row decoder 11 and the column decoder 12, and appears at a node A. The sense amplifier 15 compares the reference potential Vref and the input potential Vin to sense a type of the data stored in the memory cell MC. The sensed data is amplified by the sense amplifier 15, and outputted through the output buffer 16. In each memory cell of the EPROM, data is programmed by selectively injecting electrons into the floating gate of the cell. For injecting electrons into the floating gate, a high voltage, e.g., 12.5 to 21 V, which is much higher than the normal power voltage, e.g., 5 V, is applied to the column line and row lines as are selected by the row decoder 11 and the column decoder 12. Under such a high voltage, an impact ionization occurs in the vicinity of the drain of the memory cell located at a cross point of the selected row and column lines, to generate electron-hole pairs. Of the generated electron-hole pairs, the electrons are injected into the floating gate of the memory cell. A threshold voltage of the memory cell injected with electrons is much higher than that of the memory cell not injected. The memory cell whose floating gate is injected with electrons maintains an off-state even if a signal of "1" level (power voltage Vcc) is supplied to the control gate of the cell, or the row line. Under the same condition, the memory cell not injected with electrons is turned on. Since the dummy cell DC is not injected with electrons, no potential difference is caused between the potentials Vref and Vin. To avoid this, a channel width WD7 of the MOSFET QD7 in the second load circuit 14B is set to be larger than that WM7 of the MOSFET QM7 in the first load circuit 14A. With such a channel width selection, a conduction resistance of the MOSFET QD7 is smaller than that of the MOSFET QM7. To be more specific, the conduction resistance of the MOSFET QD7 is so selected that the reference potential Vref is between the Vin potential when the electron injected memory cell is selected and the Vin potential when the no electron injected memory cell is selected. With such an arrangement, even when the no electron injected memory cell is selected, a preset potential difference is caused between the potentials Vref and Vin. When the selected memory cell is an electron injected one, the potential Vin represents a potential which is the result of a subtraction of the threshold voltage of the load MOSFET QM7 from the power source voltage Vcc. In the subsequent description, the electron injected memory cell or the memory cell with a high threshold level will be assumed to be a memory cell storing "0" data. The no electron injected memory cell or the memory cell with a low threshold voltage will be assumed to be a memory cell storing "1" data. In the above EPROM, the data read out by the sense amplifier is received by the buffer 16, and the buffer 16 outputs the data. In the output buffer 16, it is necessary to charge and discharge an external large load capacitor. Therefore, when the output buffer 16 produces the data, noise is generated in the power source. The noise causes a variation in the power source voltage Vcc. As recalled, the conduction resistance of the MOSFET QD7 in the second load circuit 14B is different from that of the MOSFET QM7 in the first load circuit 14A. Therefore, these transistors respond to the power voltage variation in a different way. In an extreme case, a proper amplitude relationship between the potentials Vin and Vref is reversed, so that the sense amplifier may produce erroneous data. Such a malfunction of the sense amplifier should be avoided. The EPROM of Fig. 1 will encounter a situation that a row line connected to the memory cells of "1" data that is currently selected is switched to another row line connected to the memory cell having the same data, and subsequently the data are successively read out from the memory cells on the new row. In such a situation, the memory cells selected anew are insufficiently turned on in the initial stage, until the potential of the row line selected anew reaches power source voltage Vcc. Consequently, the potential of the selected bit line is temporarily increased. The threshold voltage of the memory cell of the floating gate structure is approximately 2 V. During the transient period of time that the row lines are switched one from the other, the memory cells connected to the selected column line are instantaneously in an off-state. Because of this, at the time of switching the row lines, there occurs a charging operation for the column line, and the potential Vin of the node A temporarily rises, as shown in Fig. 2. Meanwhile, since the dummy cell DC is placed always in an on state by the power voltage Vcc, the reference potential Vref is always constant as shown in Fig. 2 showing waveforms of potentials Vref and Vin. When the potential Vin rises and crosses a line of the reference potential Vref as shown, the sense amplifier 15 temporarily produces the data of an improper logic level. As a result, the output data of the buffer 16 varies its logic level, "1" → "0" → "1", during a short period. Therefore, an inductance component existing in the lead creates a great variation of the earth voltage, possibly causing a malfunction of a circuit in the EPROM. To prevent the malfunction of the circuit due to a variation of the earth voltage, there has been proposed an EPROM as shown in Fig. 3. In this EPROM, the dummy cells DC1 to DCm are provided corresponding to row lines WL1 to WLm, respectively. The control gates of the dummy cells DC1 to DCm are connected to the row lines WL1 to WLm, respectively. And, the drains of the dummy cells DC1 to DCm are connected to a dummy column line DBL. In the arrangement of the EPROM, the dummy cells are controlled by the signals on the row lines. Even in the situation that the row lines are switched from one to the other, and succeeding to the memory cell storing data "1" on the previous or old row line, the memory cell storing the data "1" on the present or new row line are subjected to the read operation, the dummy column line DBL is charged by the load circuit 14B at the time of switching the row lines. Accordingly, as seen from Fig. 4 showing waveforms, the reference potential Vref rises as the potential Vin ("1" level) rises. In the EPROM, the potential Vin does not cross the curve of the reference potential Vref. The output data of the output buffer 16 is invariable, and no variation of the earth voltage is caused. The rise of the potentials Vin and Vref is caused by the charging operation at the time of switching of the row lines, and hence the degree of the potential rise is different dependent on the conduction resistances of the MOSFETs QM7 and QD7 in the load circuits 14A and 14B. As described above, the conduction resistance of the MOSFET QD7 is set much smaller than that of MOSFET QM7. Because of this, the reference potential Vref rises to a level (denoted by Vref in Fig. 5) much higher than a level (denoted by a broken line in Fig. 5) in which the reference potential Vref in the Fig. 1 circuit is. Therefore, the reading speed for "0" data of the circuit shown in Fig. 3 is lower by time T (Fig. 5) than that of the circuit shown in Fig. 1. As described above, in a conventional semiconductor memory device, when the row lines are switched under the condition that a memory cell storing "1" data is selected to select a memory cell storing "1" data, error data is outputted, and a noise occurs in the power source to consequently cause a malfunction of the semi-conductor memory device. In another conventional semiconductor memory device solving the above problem, a variation of the reference potential is greater than that of the input potential. Therefore, the data reading speed when the selected row line is switched becomes slow. A characteristic curve depicted by a solid line in Fig. 6 shows a voltage vs. current characteristic curve of the first load circuit 14A in the conventional semiconductor memory device. In the figure, the abscissa represents a potential Vin at the node A and the ordinates a load, current flowing into the load circuit. It is assumed that Vin ("1" level) is a potential at the node A caused when the memory cell of a low threshold voltage is selected and a memory cell current Icell flows, and Vin ("0" level) is a potential at the node A and Vref is a potential at the node B. It has been known that the time required for the row line selection and the time required for the charging or discharging of the junction capacitance connected to the column line greatly determine a data read speed of a nonvolatile semiconductor memory device of the structure shown in Fig. 1. A signal delay time in the row line depends largely on a resistance of the material of the row line. For this reason, tungsten silicide has recently superseded polysilicon used conventionally. The resistance of tungsten silicide is smaller than that of polysilicon. As a result, the data read speed depends largely on the charging and discharging speed of the junction capacitance connected to the column line. Particularly, when the column line is switched one from the other, and the memory cell of a high threshold voltage is selected, the charging to the new selected column line starts at the voltage of 0 V. Capacitance connected to the column lines has become large, with the increase of the semiconductor memory capacity. Accordingly, to realize a high speed read operation, it is necessary to quicken both the charging speed of the column line and the read operation for reading out the "0" data. In conventional measures taken for this, the column line is charged at a high speed through the initial charging transistor QM4 when the potential is less than Vin ("1" level). When the potential of the column line BL exceeds Vin ("1" level), the transistor QM4 becomes nonconductive. At this time, only the p-channel transistor QM7 in the load circuit 14A charges the column line BL. Since the gate of the p-channel transistor QM7 is connected to the drain thereof, when the potential Vin at the node A rises, a conduction resistance of this transistor QM7 rapidly increases, and a charge current rapidly decreases. Therefore, it takes much time for the potential at the node A to rise from Vin ("1" level) to Vin ("0" level), lowering the data read speed. In other words, the time taken for the node A potential to rise from Vin ("1" level) to Vin ("0" level) can be reduced by increasing the channel width of the transistor QM7 and reducing its conduction resistance. However, the decrease of the conduction resistance of the transistor QM7 creates another problem that a margin for the power source noise is narrowed. In Fig. 6, a characteristic curve as indicated by a dotted line is obtained for the transistor QM7 whose conduction resistance is 1/2 that of the same transistor when the cell current vs. input voltage Vin characteristic thereof is indicated by a solid line. When the 1/2 conduction resistance of the transistor QM7 is set, the potential Vin at the node A when the memory cell storing the "1" data, viz., the memory cell of a low threshold voltage, is selected, is Vin ("1" level)'. The potential Vref′ at the node B is set at exactly the middle point between the potential Vin ("1" level)' at the node A when the memory cell of "1" data is selected and that Vin ("0" level) when the memory cell storing "0" data, i.e., the memory cell of a low threshold voltage. Accordingly, the conduction resistance of the p-channel MOS transistor QD7 in the second load circuit 14B is so selected that the potential at node B when the 1/2 conduction resistance of transistor QM7 is set is equal to Vref′ as {Vin ("0" level) - Vin ("1" level)'}/2. As a result, when the data of "1" or "0" is selected, a difference between the potential at the node B and that at the node A is reduced by ("Vin("1"level)'-Vin("1" level))/2. Generally, the ground potential greatly varies when the data is outputted from the output buffer. At this time, the potentials at the nodes A and B also vary due to the ground potential variation. In the first and second load circuits 14A and 14B, the conduction resistances of the transistors QM7 and QD7 are different from each other. The variation in the potentials at the nodes A and B are different. Accordingly, a small difference of the potential between the nodes A and B causes a malfunction of the circuit. As described above, in the conventional semiconductor memory device improved in the read speed by using a small conduction resistance in the load circuit, the semiconductor memory device is apt to malfunction due to the power noise. Accordingly, an object of the present invention is to provide a semiconductor memory device which is free from the power noise even during a transient period that row lines are switched from one to the other, and is operable at an increased data read speed. According to the present invention, there is provided a semiconductor memory device comprising: row lines; memory cells selected by the row lines; column lines receiving data from the memory cells; a first load circuit coupled with the column lines; first dummy cells selected by the row lines; a dummy column line to which the first dummy cells are connected; a pulse signal generating circuit for generating a pulse signal by detecting a change in an address input signal; a second load circuit connected to the dummy column line, a conduction resistance of the second load circuit to the dummy column line being increased by the pulse signal generated by the pulse signal generating circuit; and a sense amplifier for sensing the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. A conduction resistance of the second load circuit is changed during a transient period of the row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a conventional semiconductor memory device, Fig. 2 shows a graphical representation of transient voltage waveforms at the nodes A and B in the memory device shown in Fig. 1; Fig. 3 is a circuit diagram of another conventional semiconductor memory device; Figs. 4 and 5 show graphical representations of transient voltage waveforms at the nodes A and B in the memory device shown in Fig. 3; Fig. 6 shows a graphical representation of a load current vs. sensing node voltage characteristic of a first load circuit in the conventional memory device; Fig. 7 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention; Fig. 8 shows a set of waveforms of signals in an address transition detector used in the embodiment of Fig. 7. Some specific embodiments of a semiconductor device according to the present invention will be described with reference the accompanying drawings. Referring now to Fig. 7, there is shown a circuit diagram of a circuit arrangement for data-sensing of an EPROM using floating gate MOSFETs as already mentioned in the prior art description, to which a semiconductor memory device accordint to the present invention is applied. In Fig. 7, MC11, MC12, ..., MC1n, ..., MCmn designate floating gate MOSFETs; DC1, DC2, ...,DCm dummy cells as floating gate MOSFETs; WL1, WL2, ..., WLm row lines; BL1, BL2, ..., BLn column lines; DBL a dummy column line; 11 a row decoder; 12 a column decoder; BT1, BT2, ..., BTn column gate MOSFETs for column selection; DBT a MOSFET that is equivalent to the column gate MOSFET and is normally in a conductive state with application of a power voltage Vcc to the gate Of the MOSFET; 13A a first bias setting circuit made up of n-channel MOSFETs QM1 to QM6; 14A a first load circuit made up of a p-channel MOSFET QM7; 13B a second bias setting circuit made up of n-channel MOSFETs QD1 to QD6; 14B a second load circuit made up of p-channel MOSFETs QD7a and QD7b; 15 a sense amplifier; and 16 an output buffer. In the description to follow, MOSFETs whose channels are not specified will be treated as n-channel MOSFETs. The dummy cell DC that is any one of the dummy cells DC1 to DCm comprises a MOSFET quivalent to that of a memory cell MC that is any one of the memory cells MC11 to MCmn. In the dummy cells DC1, DC2, ..., DCm, the drains of them are connected together to the dummy column line DBL. The control gates of them are connected to the row lines WL1 to WLm, respectively. The sources of those transistors are grounded. The first and second bias potential setting circuit 13A and 13B are constructed like those in the conventional semiconductor memory device. For example, in the first bias potential setting circuit 13A, the source-drain current path of the MOSFET QM1 is inserted between a connection point of the column gate MOSFETs BT1 to BTn and the node A. The gate of the MOSFET QM1 is applied with a DC bias potential V1 which is lower than the power voltage Vcc and formed by the two MOSFETs QM2 and QM3. The source-drain current path of the MOSFET QM4 is inserted between a connection point of the column gate MOSFETs BT1 to BTn and the power voltage Vcc. The gate of the MOSFET QM4 is applied with a DC bias potential V2 which is lower than the DC bias potential V1 and formed by the two MOSFETs QM5 and QM6. The DC bias potential V2 is set at a value which is the sum of a column line potential when a memory cell whose threshold voltage is set at a low voltage is selected and a predetermined current flows through the source-drain current path of the memory cell, and a threshold voltage of the n-channel MOSFET contained an increased threshold voltage due to a substrate bias effect. The circuit arrangement of the second bias potential setting circuit 13B is substantially the same as that of the first bias potential setting circuit when the MOSFETs QD1 to QD6 are replaced by the MOSFETs QM1 to QM6. The first load circuit 14A is also substantially the same as in the conventional memory device. Specifically, in the first load circuit 14A, the source-drain curent path of MOSFET QM7 is inserted between the node A and the power source Vcc. The gate of the MOSFET QM7 is connected to its drain and the node A. The MOSFET QM4 in the first bias potential setting circuit 13A is for the initial charging of the column line. When a column line BL is selected and a charging for the column line BL starts form an initial value 0 V, the transistor QM4 quickens the initial charging. The DC bias voltage V2 is set such that the MOSFET QM4 is turned off when the column line potential exceeds a column potential when a predetermined current flows into the memory cell. The present embodiment is different from the semiconductor memory device shown in Fig. 3 in the following points. An address transition detector (ATD) 18 is additionally used. An output signal of the ADT 18 is applied to the second load circuit. A row address is applied to the row address buffer 17. When a row address changes and the word lines are switched, the ATD 18 generates a pulse signal of a predetermined pulse width. The holding back of the rise of the reference potential Vref is realized by directly controlling the conduction resistance of the second load circuit 14B. Incidentally, reference numeral 19 designates a column address buffer receiving a column address. The output signals of the address buffers 17 and 19 are applied to the row and column decoders 11 and 12, respectively. In this embodiment, during a transient period that a row address changes and the present row line is switched to another row line, the ATD 18 produces a pulse signal to directly control the conduction resistance of the second load circuit 14B. As shown in Fig. 7 a couple of p-channel MOSFETs QD7a and QD7b are connected in parallel between the power voltage Vcc and the node B. The gate of the transistor QD7a is connected to its drain. The transistor QD7b receives at the gate a pulse signal from the ATD 18. In the semiconductor memory device thus arranged, at the time of the row line switching, the ATD is produces an output pulse signal and turns off the MOSFET QD7b by the pulse signal. Accordingly, a current fed to the node B at which the reference potential Vref appears decreases, thereby to hold back the rise of the reference potential Vref. In this embodiment, after the row line switching is completed, the load transistors QD7a and QD7b in the second load circuit 14B are both turned on. Accordingly, the sum of the conduction resistance of these transistors QD7a and QD7b are selected to be substantially equal to that of the transistor QD7 in the memory device of Fig. 3. If necessary, two different bias voltages setting circuits may be provided for the MOSFETs QD7a and QD7b. Fig. 8 shows a timing chart for explaining the operation of the ATD 18 that is used in the embodiment of Fig. 7. As seen from the timing chart, a row address signal externally applied changes, and with the change of the address signal, the row line currently used is switched to a new row line. During this period of the row line switching, the ATD 18 produces a pulse signal which retains a "1" logical state during this period. A circuit having such a function may readily be realized by combining signal delay and logic circuits. It is evident that the present invention is applicable not only for the EPROM but also for a mask ROM using MOSFETs of a single gate structure as memory cells, whose threshold voltages are adjusted, low and high, by selectively doping impurity into the channel regions of the transistors during the manufacturing process. The p-channel MOSFET for load may be substituted by an n-channel MOSFET if its conduction resistance is comparable to the former. If the n-channel MOSFET is used in the Fig. 7 embodiment, the phase of the pulse signal generated by the ATD 18 must be inverted with respect to that of the pulse signal generated by the ATD in the Fig. 7 embodiment. As seen from the foregoing description, in the memory device according to the above-mentioned embodiment, a rise of the reference potential Vref is held back even during the time of the row line switching. Accordingly, no noise is entered into the power source. A data read speed of the memory device is improved.

Claims: A semiconductor memory device comprising: row lines (WL1, ..., WLm); memory cells (MC11, ..., MCmn) selected by said row lines; column lines (BL1, ..., BLn) receiving data from said memory cells; a first load circuit (14A) coupled with said column lines; first dummy cells (DC1, ..., DCm) selected by said row lines; a dummy column line (DBL) to which said first dummy cells are connected; a pulse signal generating circuit (18) for generating a pulse signal by detecting a change in an address input signal; a second load circuit (14B) connected to said dummy column line, a conduction resistance of said second load circuit being increased by the pulse signal generated by said pulse signal generating circuit; and a sense amplifier (15) for sensing the data stored in said memory cell in accordance with a potential difference between said column line and said dummy column line. A semiconductor memory device according to claim 1, characterized in that said second load circuit (14B) includes first and second MOSFETs (QD7a, QD7b) connected in parallel between a power source and said dummy column line, the gate of said first MOSFET (QD7a) is connected to said dummy column line, and the gate of said second MOSFET (QD7b) is coupled for reception with said pulse signal outputted from said pulse signal generating circuit.

Inventors: IWAHASHI HIROSHI C O INTELLECT, KANAZAWA KAZUHISA C O INTELLEC, KUMAGAI SHIGERU C O INTELLECTU, NAKAI HIROTO C O INTELLECTUAL, SATO ISAO C O INTELLECTUAL PRO, IWAHASHI, HIROSHI, C/O INTELLECTUAL PROPERTY DIV., KANAZAWA, KAZUHISA, C/O INTELLECTUAL PROPERTY DIV., KUMAGAI, SHIGERU, C/O INTELLECTUAL PROPERTY DIV., NAKAI, HIROTO, C/O INTELLECTUAL PROPERTY DIV., SATO, ISAO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1989
Main classification: G11C16
IPC codes: G11C16, G11C7