METHOD OF PRODUCING A SEMICONDUCTOR DEVICE

Abstract: A method of producing a semiconductor device comprises the steps of : preparing a semiconductor substrate (1), forming a gate insulating layer on the semiconductor substrate, forming a gate electrode (4) on the gate insulating layer, forming a source/drain region (2,3) in the semiconductor substrate, forming a cover layer (10,11) on the entire exposed surface, forming a mask (12) on the cover layer having an opening over the gate electrode (4), implanting one conductivity type impurity ions into the semiconductor substrate (1) through the cover layer, the gate electrode and the gate insulating layer as the first ion implanting process, implanting opposite conductivity type impurity ions into the semiconductor substrate therethrough as the second implanting process, at an implanting angle larger than that used in the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as the first ion implanting process, and at a dosage smaller than that in the first ion implanting process, whereby the one conductivity type impurity ions are compensated at laterally spread portions.

Description: The present invention relates to a method of producing a semiconductor device, and more particularly, to an ion implantation method of writing information in a Read Only Memory (ROM), etc. The method of writing information in a ROM by controlling the threshold voltage (Vth) of a MOS transistor is well known. In this ROM, each cell is composed of the MOS transistor or a resistance. Conventionally, the control of the threshold voltage (Vth) is usually carried out before the gate electrode formation during the MOS transistor production process, due to the limitations (usually 200 KeV or less) of the accelerating energy of the ion implanting apparatus used to introduce impurities into a semiconductor. Recently, however, an ion implanting apparatus having a high accelerating energy of, e.g., 0.4 to 3 MeV, has been actually used and control of the Vth realized thereby, through a gate electrode and/or an insulating film positioned thereon. This manner of writing information in a ROM shortens the period (turnaround time) from receipt of an order to shipment of the device. Conventional examples thereof are now explained. Figures 1A to 1C are cross-sectional process views of a conventional method of implanting ions in a ROM. As shown in Fig. 1A, a p type silicon substrate 1 is provided with n⁺ source/drain regions 2 and 3 on which is formed a gate electrode 4 having a 20 nm (200 Å) thick gate silicon oxide film 5. Then, as shown in Fig. 1B, after forming a patterning mask 7 by which the gate electrode 4 is exposed, ROM information is written by implanting n type impurity ions, for example Phosphorus (P⁺), in the silicon substrate 1 through the gate electrode 4 and the gate silicon oxide film 5 with an energy of about 100 to 200 KeV, so that an n-type region having a depth of about 0.2 µm or less is formed. Thereafter, the usual processes, for example, a wiring or interconnection forming process and a passivation process, are carried out as shown in Fig. 1C, and a final ROM product, is produced. In Fig. 1C, 8 denotes a passivation film, etc. In this process, however, the turnaround time from information writing to final product is a lengthy period of one week or more. Figure 2 shows a cross-sectional view of another conventional example, wherein impurity ions having a high energy are implanted, from above insulating films (passivation film 5, etc.) 8 formed on a gate electrode 4, in a p-type silicon substrate 1. Namely, as shown in Fig. 2, n-type impurities, e.g., P⁺, having a high energy of 0.4 to 3 MeV are implanted from above the passivation films etc. 8 formed on a gate electrode 4, in a p type silicon substrate 1. This high energy implanting method shortens the turnaround time from the ion implanting process to the final product to, for example, two or three days. However, since the implanting distance of ions is lengthened by using the high energy implanting apparatus the ion spread in the lateral direction is made wider (0.7 µm in Fig. 2) and the widened region has an adverse influence on an adjacent cell when information writing in a cell. This problem has become more serious with the need for a shrinkage of the cells in a ROM. Note, when the ion implanting energy is increased, the ion-spread in the lateral direction is greater, and thus, it is difficult to shrink ROM cells beyond a certain limit. For example, when implanting ions through a SiO₂ film or a Si film having a thickness of 1.5 µm, a width of about 0.2 - 0.4 µm occurs to a region having a concentration one-tenth that of the implanting region. To solve the above-mentioned problem of the widening of ion implanted region in the lateral direction, the present inventor proposed an ion implanting method disclosed in a Japanese Unexamined Patent Publication (Kokai) No. 63-299119 wherein, during a high energy ion implantation, opposite conductive type impurity ions (compensating ions) having a wider region in the lateral direction than that of the writing ions are implanted at a low dose from the opening of the same mask as used for the writing, so that the conductive type is compensated at a tail portion. Although, this ion implanting process allows a greater shrinkage of cells, the opposite conductive type ions were restricted such that they satisfy only the above-mentioned conditions with respect to the writing ions. An object of the present invention is to solve the above-mentioned problems. A further object of the present invention is to provide a method of producing a semiconductor device such as a ROM, wherein information can be written in a ROM by an ion implanting process using optional ions, in accordance with a design of a cell structure. A still further object of the present invention is to provide a method of producing a semiconductor device such as ROM, wherein a greater shrinkage of cells can be realized. An additional object of the present invention is to provide a method of producing a semiconductor device such as a ROM wherein a turnaround time from a ion implantation to produce completion is shortened. Accordingly, there is provided a method of producing a semiconductor device comprising the steps of: forming a gate insulating layer on a semiconductor substrate, forming a gate electrode on the gate insulating layer, forming a source/drain region in the semiconductor substrate, forming a cover layer on the entire exposed surface, forming a mask on the cover layer having an opening over the gate electrode, implanting a first conductivity type impurity ions into the semiconductor substrate through the cover layer, the gate electrode and the gate insulating layer as the first ion implanting process, implanting in a second implanting process a second conductivity type impurity ions, opposite to the first conductivity type, into the semiconductor substrate at an implanting angle larger than that used in the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as the first ion implanting process and at a dosage smaller than in the first ion implanting process, whereby said one conductivity type impurity ions are compensated at laterally spread portions In these steps, the order of the first ion implanting process and the second ion implanting process can be swapped, of course. According to the present invention, spread of the implanted writing ions in the lateral direction is prevented by the opposite conductivity type additional and compensating optionally selected ions implanted with a tilted angle. Although the compensating ion distribution in the substrate can sometimes reach the adjacent cell, the direction of shift of the threshold voltage is opposite to that for the writing ions, and thus the device functions without problem. Furthermore, even where a writing is effected into the adjacent cell, since ions extended from the target cell have smaller dosage than that of the ions implanted in the cell no problem arises. According to the present invention, the first conductivity type impurity ions are preferably implanted at an implanting angle of 0 to 7°, particularly 0° with respect to the normal plane of the semiconductor device, at a projective range of 0.5 to 3 µm, particularly about 1,7 µm, and a dosage of 1 to 5 x 10¹³/cm², particularly about 1.2 x 10¹³/cm². Further, according to the present invention the second conductivity type impurity ions are preferably implanted at an implanting angle of larger than 7°; particularly about 10°, at a projective range of 0.5 to 3 µm particularly about 1,7 µm, and a dosage of 1 to 5 x 10¹²/cm², particularly, about 2.5 x 10¹²/cm². Figures 1A to 1C are cross-sectional process views illustrating a conventional method of implanting ions in a ROM; Fig. 2 is a cross-sectional view of another example of a conventional method; Figs. 3A and 3B are cross-sectional process views of a ROM cell for explaining an example according to the present invention; Fig. 4 is a graph illustrating an impurity distribution or profile in the conventional examples shown in Fig. 2; Figs. 5A to 5C are cross-sectional views taken along the line AA of Fig. 7, for explaining another example of the present invention; Figs. 6A to 6C are cross-sectional views taken along the line BB of Fig. 7 for explaining another example of the present invention; and, Fig. 7 is a plane view of explaining another example of the present invention. The preferred embodiments of the present invention will now be explained with reference to drawings. Figures 3A and 3B are cross-sectional process views of a ROM cell for explaining an example according to the present invention. As shown in Figs. 3A and 3B, a gate electrode 4 provided with a 20 nm (200 Å) thick gate SiO₂ film 5 is formed by a usual process on a p type silicon substrate 1 having n⁺ source/drain regions 2 and 3 of a cell transistor. The gate electrode 4 is made of polycrystalline silicon (poly Si) having a thickness of 400 nm (4000 Å), and a phospho-silicate glass (PSG) interlayer insulating film 10 having a thickness of 500 nm (5000 Å) and a PSG cover film 11 having a thickness of 600 nm (6000 Å) are formed on the gate electrode 4. The gate length L of the cell transistor is 0.8 µm and the cell gap D is 0.8 µm. Then a mask 12 comprising tungsten 300 nm (3000 Å) and resist 500 nm (5000 Å), for ion implantation for writing information, is formed on the PSG cover film 11. In this mask formation, a slight deviation (ΔL) between the mask opening and the cell pattern can be for seen (not shown). The information is written by controlling a threshold voltage of the cell transistor, as mentioned before. The threshold voltage control is effected by implanting writing ions into a channel forming region of the Si substrate 1 through covered insulating films and the poly Si gate having a total thickness of 1.5 µm. Phosphorus ions (P⁺) having a n conductivity type are used as the writing ions. The P⁺ ion implanting conditions are as follows: implanting energy, 1.5 MeV, dosage: 1.2 x 10¹³/cm², and implanting angle ϑ: 0°. Then, as compensating ions, boron ions (B⁺) having an p conductivity type are used. The B⁺ ion implanting conditions are as follows; implanting energy: 0.75 MeV, dosage: 2.5 x 10¹²/cm⁻², and implanting angle ϑ: 10°. Figure 4 is a graph illustrating an impurity distribution or profile of the above conventional examples. In Fig. 4 the ordinate axis is a carrier concentration which is equal to the absolute value of the difference between the n type impurity concentration and the p type impurity concentration at an ordinary temperature, and the transverse axis is a distance in a lateral direction. After the ion implantation the ions are annealed at a usual temperature of 600°C or less (in this case, 600°C), for 30 minutes. As apparent from Fig. 2, in the conventional example having the implantation conditions: P⁺ writing ion, energy of 1.5 MeV, dosage of 1 x 10¹³/cm², and implanting angle ϑ of 0°, the spread in the lateral direction of the implanted ion is about 0.7 µm, as also shown in Fig. 3A and 4. The distance 0.7 µm possibly covers a part of the adjacent cell and shifts the threshold voltage to a depression side. This occurs when the mask is deviated and the gap between the cell and the adjacent cell is narrowed. On the contrary, in the example of the present invention, the carrier concentration in a writing cell is little varied and the distance of the n type region is reduced to 0.2 µm by the distribution (broken line X) of Boron (B⁺) having the opposite conductivity type to that of P⁺, so that the n type region does not reach the adjacent cell. These ion distributions of the n type impurity (P⁺), which is implanted in a conventional way, and the P type impurity (B⁺) which is additionally implanted with a tilted angle are also shown in Fig. 3A. In Fig. 3, the laterally spread low concentration n type region is reversed to a p type region by implanting p type ions with a tilted angle, and thus as shown in Fig. 3B, an n type region having a lesser spread is formed as information written in a ROM cell. Figures 5A to 5C are cross-sectional views taken along the line AA of Figure 7, for explaining another example of the present invention. Particularly Figure 5A shows a P⁺ ion (writing ion) implanted state. Figure 5B shows a B⁺ ion (compensating ion) implanted state, and Figure 5C shows a (P⁺) - (B⁺), i.e., compensated, state. As shown in Figs. 5A to 5C, except that the resist mask 12 and the tungsten mask 13 are slightly deviated (e.g., 0.3 µm) to the right side, the various conditions (e.g., ion implantation and thickness) are substantially the same as shown in the example of Figs. 3A and 3B. The P⁺ (n type) ion implanted width in the lateral direction from P to Q is about 0.85 µm, and the B⁺ (p type) ion implanted spread in the lateral direction from R to S is about 0.95 µm. The compensated ion implanted spread in the lateral direction T to U is about 0.55 µm, and thus is reduced by 0.3 µm. Figures 6A to 6C are cross-sectional views taken along the line BB of Figure 7 for explaining another example of the present invention. Particularly Figure 6A shows a P⁺ ion (writing ion) implanted state, Figure 6B shows a B⁺ ion (compensating ion) implanted state, and Figure 6C shows a (P⁺) - (B⁺), i.e., compensated, state. In Figs. 6A to 6C, except that the resist mask 12 and the tungsten mask 13 are slightly deviated (e.g., 0.3 µm) to the right side, the various conditions (e.g., ion implantation, and thickness) are substantially the same as in the example shown in Figs. 3A and 3B. In Figs. 6A to 6C, a field oxide film (SiO₂) 15 having a thickness of 600 nm (6000 Å) is provided, and as can be seen in Figs. 6A to 6C the compensated ion spread in the lateral direction is reduced by about 0.45 µm, and thus the spread thereof does not cover the adjacent cell.

Claims: A method of producing a semiconductor device comprising the steps of: forming a gate insulating (5) layer on a semiconductor substrate (1), forming a gate electrode (4) on the gate insulating layer, forming a source/drain region (2,3) in the semiconductor substrate, forming a cover layer (10,11) on the entire exposed surface, forming a mask (12) on the cover layer having an opening over the gate electrode, implanting a first conductivity type impurity ions into the semiconductor substrate through the cover layer, the gate electrode and the gate insulating layer as the first ion implanting process, implanting in a second implanting process a second conductivity type impurity ions, opposite to the first conductivity type, into the semiconductor substrate at an implanting angle larger than that of the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as in the first ion implanting process and at a dosage smaller than in the first ion implanting process, whereby said one conductivity type impurity ions are compensated at laterally spread portions. A method according to claim 1, wherein said semiconductor substrate (1) is a p type silicon substrate. A method according to claim 1, wherein said gate electrode (4) is a polycristalline silicon electrode having a thickness of about 400 nm (4000 Å). A method according to claim 1, wherein said cover layer (10,11) positioned on the entire exposed surface is composed of two phospho-silicate glass layers having a total thickness of 1.1 µm. A method according to claim 1, wherein said first conductivity type impurity ions are n type impurity ions. A method according to claim 5, wherein said n type impurity ions are phosphorus ions (P⁺). A method according to claim 1, wherein said first conductivity type impurity ions are implanted at an implanting angle of 0 to 7° with respect to the normal plane of the semiconductor device. A method according to claim 1, wherein said first conductivity type impurity ions are implanted at a projective range of 0.5 to 3 µm and a dosage of 1 to 5 x 10¹³/cm². A method according to claim 1, wherein said second conductivity type impurity ions are p type impurity ions. A method according to claim 9, wherein said p type impurity ions are boron ions (B⁺). A method according to claim 1, wherein said second conductivity type impurity ions are implanted at an implanting angle of larger than 7° with respect to the normal plane of the semiconductor device. A method according to claim 1, wherein said second conductivity type impurity ions are implanted at a projective range of 0.5 to 3 µm and a dosage of 1 to 5 x 10¹²/cm².

Inventors: MORI, HARUHISA
Applicants: FUJITSU LIMITED
Application year: 1989
Main classification: H01L21
IPC codes: H01L21, H01L29, H01L27