Memory diagnostic apparatus and method

Abstract: A system console (30) is enabled to read registers from memory boards 12 and 14 and to set registers within the memory boards which control the disabling of one or more memory arrays (16-22). The information read from the memory boards is indicative at least of which of the memory arrays has malfunctioned. The registers are within a memory logic array (40), one of which is disposed upon each of the memory boards (12) and (14) and also upon a memory controlling unit (26), the memory logic arrays being coupled together by a bit serial scan bus 41. In a preferred embodiment of the invention the memory logic arrays 40 are comprised of a highly integrated gate array semiconductor device, each of which is identical. Each memory logic array is provided with a base address input (46) from a preceding memory logic array and computes a base address for a subsequent memory logic array. A memory logic array which has a portion of an associated memory disabled automatically determines a revised base address for the subsequent memory logic array, thereby initiating the automatic reallocation of memory board base addresses of all subsequent memory boards.

Description: Field of the Invention: This invention relates generally to digital data processor memories and, in particular, to a distributed memory diagnostic system comprised of substantially identical memory logic arrays each of which is disposed upon a corresponding memory board and to a memory logic array disposed upon a memory control unit, the memory logic arrays being coupled together by a serial data bus. Background of the Invention Modern computer systems are typically comprised of one or more memory boards and other system units, such as a central processing unit (CPU), which are coupled together by a system bus. The CPU is operable for storing data within and retrieving data from memory devices located on the memory boards. Each memory board is typically comprised of a number of dynamic read/write memory devices and may have a total memory storage capacity of many megabytes of digital data. For example, each memory board may have a total storage capacity of 16, 32, 64 of 128 megabytes of data. The range of storage location addresses which each board corresponds to are typically contiguously arranged within the address space of the system such that, for example, a first memory board may have a range of storage addresses of between zero and 16 megabytes while a second board may have a range of addresses between 16 and 32 megabytes. As can be appreciated, a memory fault which results in a data storage error within a portion of the memory address space must be accurately identified as to the location within the address space. Related to this issue as to identifying the portion of the address space having a fault memory device is a problem related to the disabling of that portion of the memory to prevent the further occurrence of data storage errors. A still further problem is introduced inasmuch as the disabling of a portion of the memory, which is preferably "mapped out" of the memory space, typically requires that a reallocation of memory addresses among the memory boards be accomplished to reflect the amount of memory which has been effectively removed from the address space of the system. Obviously, it is desirable that a minimum amount of operator or system intervention be required to reallocate the memory addresses in order to minimize or prevent system downtime and to avoid the possibility of erroneously reallocating the memory addresses. EP-A-0 259 859 discloses an information processing system that includes a plurality of memory units, a memory access controller, and a request source processor and a diagnostic processor. A memory restructuring circuit is used to disconnect failing memory units. Relatedly, US-A-3 803 560 discloses a memory system comprised of memory modules. Memory modules are automatically removed upon a detection of a fault condition, and the remaining modules are reconfigured to form a contiguous address space. The foregoing problems are overcome and other advantages are realized in a digital data processing system according to claim 1. In accordance with the present invention, an apparatus or allocating memory address base addresses among a plurality of memory unit is provided, each of the memory units defining a predefined range of memory addresses, each of the range of memory addresses also being contiguous one with the other. For each of the memory units there is disclosed means for defining a total number of data storage memory addresses represented by a memory unit, the total number defining means having a first output; means for defining a portion or portions of the total number of memory unit memory addresses which are disabled from the storage of data therein, the portion defining means having a second output; means for defining a memory address base address for the memory unit, the base address defining means having a third output; means for combining the first, the second and the third outputs to produce a fourth output, the fourth output being substantially equal to the sum of the first and the third outputs minus the second output; and means for outputting the fourth output to another memory unit for defining a memory address base address for the other memory unit. In accordance with the invention there is disclosed a way of allocating memory address base addresses among a plurality of memory units, each of the memory units defining a predefined range of memory addresses, each of the range of memory addresses also being contiguous one with the other. The invention defines, for each of the memory units, a first value expressive of a total number of data storage memory addresses represented by a memory unit; a second value expressive of a portion or portions of the total number of memory unit memory addresses which are disabled from the storage of data therein; a third value expressive of a memory address base address for the memory unit; combines the first, the second and the third values to generate a fourth value, the fourth value being substantially equal to the sum of the first and the third values minus the second value; and outputs the fourth value to another memory unit for defining a memory address base address for the other memory unit. These and other aspects of the invention will be made more apparent hereinafter in a description of a preferred embodiment of the invention read in conjunction with the accompanying drawing wherein: Fig. 1 is a block diagram of a portion of a computer system having a preferred embodiment of a memory logic array of the invention; Fig. 2 is a block diagram of a memory logic array showing the input and output signals of the array; Fig. 3 is a block diagram of circuitry which comprises a portion of the memory logic array of Fig. 2, the circuitry functioning in a memory array board application; and Fig. 4 is a block diagram of circuitry which comprises a portion of the memory logic array of Fig. 2, the circuitry functioning in a memory controller application. Referring now to Fig. 1 there is shown in block diagram form a portion of a digital data processing system 10 having a preferred embodiment of the invention. System 10 can be seen to be comprised of a plurality of discrete memory units, such as memory boards 12 and 14, each of which comprises first and second memory banks, or arrays, (MA) 16, 18 and 20,22, respectively. Each of the memory arrays 16-22 is comprised of some desired number of memory storage locations. For example each memory array may comprise sixteen megabytes of read/write memory, such as well known dynamic random access memory (DRAM). Each memory array 16-20 may be organized as double memory words each of which comprise eight bytes of data. For example, each memory word within a memory array may comprise eight bytes of data for a total word width of 64 bits of data. Of course, the system 10 may comprise more than two memory boards. Address and data information are provided to the memory boards via a memory bus (MEMBUS) 24 which is sourced from a memory control unit (MCU) 26. Memory control unit 26 is coupled to a system address, control and data bus (SYSBUS) 28 and in general operates to interpret address and control information appearing on SYSBUS 28 which relates to data read/write operations to be performed upon one of the memory boards 12 or 14. Also coupled to the SYSBUS 28 are other system components such as a central processing unit CPU (not shown) and also typically one or more input/output (I/O) circuit boards (not shown). The system 10 also comprises a system console 30 which may be a data processing system such as a personal computer or some other data processing system which is operable for monitoring the operation and status of the system 10. System console 30 typically comprises an operator output device such as a well known display monitor 32 and an operator input device such as a keyboard 34. By means of the display monitor 32 and keyboard 34 an operator is enabled to determine the status of the system 10 and to control various aspects of the operation thereof. In the preferred embodiment of the invention the system console 30 is coupled to the system 10 via a serial diagnostic bus (SDB) 36 which comprises a two-bit wide serial bus. The SDB 36 is preferably coupled to each of the major system units, such as the memory control unit 26, such that the system console is effectively coupled to substantially all of the major system units. The interface between the SDB and each of the system units is accomplished by a system control interface unit (SCIU) 38. A description of the SCIU 38 will be provided hereinafter. In accordance with the invention the system console 30 is enabled to read status information from the memory boards 12 and 14 and to set registers within the memory boards which control the disabling of one or more of the MAs 16-22. The status information read from the memory boards is indicative at least of which of the MAs has malfunctioned. This valuable function is performed by a memory logic array (MLA) 40, one of which is disposed upon each of the memory boards 12 and 14 and also upon the MCU 26. In the preferred embodiment of the invention the MLAs 40 are comprised of a highly integrated gate array semiconductor device, each of which is identical. The specific function of each of the MLAs 40, that is whether the MLAs 40 function upon one of the memory boards or upon the MCU 26, is determined by the logical state of an MCU input. For example, if the MCU input is at a logic high the MLA 40 is configured to function upon the MCU 26. Conversely, if the MCU input is a logic low the MLA 40 is configured to function upon one of the memory boards 12 or 14. Fig. 2 illustrates one of the MLAs 40 and shows the input and output terminals thereof. It should be pointed out that certain of the input/output terminals are coupled to MEMBUS 24 and that internal circuitry performs memory timing, memory array selection, memory access, refresh and other functions related to the general operation of the memory devices upon the associated memory board. For the MLA 40 upon MCU 26 these memory device control related pins are generally unused. Communication between the MLAs 40 is accomplished by a scan bus (SCANBUS) 42 which comprises a SCANMODE signal line and bit serial SCANIN and SCANOUT signal lines. Synchronization of the internal operation of the MLAs 40 and the communication over the bit serial SCANBUS 42 is accomplished by a memory clock (MEMCLK) signal line which is coupled to each of the MLAs. In the preferred embodiment of the invention the MEMCLK signal has a period of approximately 38 nanoseconds. The MEMCLK signal is divided by four within each of the MLAs to provide the basic MLA operating clock frequency. The direction of data flow upon the SCANBUS 41 is controlled by the logic state of the SCANMODE signal line. The logic state of SCANMODE specifies whether data is being sourced from the MLA 40 upon the MCU 26 or whether the data is being sourced by an MLA 40 upon one of the memory boards 12 or 14. The SCANOUT signal line from the MLA 40 upon the MCU 26 is connected in common to a SCANIN input pin of the MLAs 40 upon the memory boards. Conversely, the SCANOUT signal of each of the MLAs 40 upon the memory boards are coupled together in common and are further coupled to the SCANIN pin of the MLA 40 of MCU 26. Communication between MLAs is initiated by the MLA 40 upon the MCU 26 which in turn is controlled, via SCIU 38, by the system console 30. The MLA on each memory board has five registers which contain information relating to the memory board. Board ID (BDID) is a register which is serially loaded from the SCANIN pin with a memory board ID and which is compared with data which is provided, typically, but input signals lines which are hardwired to predetermined signal levels. In the preferred embodiment of the invention BDID is three bits in width such that up to eight unique board IDs may be utilized. The three bits are hardwired to logic levels on a backplane to which the memory boards are coupled. Board status (BDSTAT) is a register which is also serially loaded fromthe SCANIN pin and is used to indicate how much of the memory upon the memory board is to be disabled. BDSTAT is a two bit register which conveys information for enabling both MAs, disabling one or the other of the MAs, or provides for disabling both of the MAs. The contents of BDSTAT are transferred to a pair of status flip/flops only within an MLA which detects a match between BDID and its externally provided ID. This aspect of the invention will be discussed in detail below. Board base address (BDBA) is a register which holds the base address which a MLA provides to another MLA via base address output signal lines 46. In the preferred embodiment of the invention, each MLA outputs six signal lines which correspond to the MSBs of the memory address bus and in general have a value which is one greater than the maximum address which the MLA responds to. This base address thereby provides to the subsequent memory board the memory address at the beginning of the memory address range to which the subsequent board will respond. It can be appreciated that since memory boards preferably represent logically contiguous, partioned sections of the physical address space of the system that if a portion of the memory upon one of the memory boards is disabled that the base address output signal lines must change state to indicate the reduction in memory capacity of the memory board. As will be described, this change of state causes other "downstream" memory boards to automatically remap their corresponding range of memory addresses such that the contiguous partioning of the memory space is preserved. The base address input signal lines of the first memory board in the system, for example memory board 12, may be hardwired to desired logic signal levels. In the preferred embodiment of the invention these input signal lines are coupled to signal ground and thus the first memory board 12 responds to addresses within an address range of zero to the value determined by the setting of a plurality of board size jumpers 48, which will be discussed below. Another register is board match (BDMATCH) which is a one bit register which indicates whether a memory address on MEMBUS 24 is a memory address which is within the range of addresses which a particular memory board responds to. That is, any particular memory access which occurs upon MEMBUS 24 will result in only one of the MLAs setting the BDMATCH register, that MLA being installed upon the memory board which responds to the particular memory address. BDMATCH is set by logic which compares the six MSBs of the address bus, which are input to each MLA on pins A[2:7], to logic signals which are related to the six base address inputs and the six base address outputs, in conjunction with logic signals related to the amount of memory which is enabled upon the memory board and also to the board size. Another register is designated board size (BDSIZE) and is typically set by the externally provided switches 48 which indicate the amount of memory installed upon the memory board. In the preferred embodiment of the invention the board size register is two bits in width and assumes values which correspond to a board size, or memory capacity, of 16, 32, 64 or 128 megabytes. The value of the BDSIZE register is used in conjunction with circuitry, which will be described below, in order to determine the value of the base address output signal 46. A scan register (SCANREG) holds data received by the MLA 40 upon the MCU 26 from the MLAs 40 on the memory boards 12 and 14, the data being received over SCANBUS 42. The MCU data ready register (MCUDR) is located within the MLA 40 of MCU 26 and is used to indicate that SCANREG has been fully loaded from a previously specified MLA 40 upon a memory board. The value of MCUDR is determined by the SCIU 38, in a manner which ill be described hereinafter, in order to facilitate the transfer of data from the MLAs to the system console 30. The aforementioned MCU input pin of each of the MLAs is utilized to determine the function of certain of the input lines of the MLA. When the logic state of the MCU input pin is high, the SCIU 38 provides control and data inputs to the MLA 40 upon the MCU 26 via the same input pins which are used for the base address and the board size in an MLA 40 upon one of the memory boards. One of these inputs is SCIU Command (SCIU CMD) which is connected to one of the base address lines of the MLA 40 of MCU 26 and indicates, when high, that the MLA 40 is to scan the memory board specified by SCIU ID. SCIU ID is a three bit signal connected to three of the base address input lines and specifies the board ID of one of the memory boards whose MLA 40 is to be scanned. Alternatively, when SCIU CMD is low SCIU ID specifies pairs of bits previously stored in SCANREG which are to be read out to the SCIU 38. The selected pairs of bits are read out to the SCIU 38 upon two SCIU READ signal lines. When the logic state of the SCIU CMD specifies that a scan operation is to be performed a two bit signal SCIU STAT is provided to the MLA upon the BDSIZE input lines for inputting the two bit status code of the memory board to be scanned. The codes have the following meaning: 00, both MAs enabled; 01, the lower MA is disabled; 10, the upper MA is disabled; and 11, both MAs are disabled. In general, the operation of the system is as follows. System console 30 maintains a record of the current status of each of the memory boards 12 and 14. This status information includes, for each memory board, whether both, one or neither of the memory arrays is enabled. When the system console 30 determines that a hardware memory error in a specific range of addresses has occurred, such as by the occurrence of a noncorrectable double bit memory error, system console 30 scans the MLA 40 upon the memory boards to locate a memory board which includes the failing address or range of failing addresses. To accomplish this function, the system console 30 provides a memory board ID and a two bit code indicating the present status of that memory board via SDB 36 to SCIU 38. SCIU 38 thereafter sets SCIU CMD to indicate that a scan operation is to occur and subsequently places the desired board ID and that boards present status code onto the signal lines SCIU ID and SCIU STAT, respectively. In response to these signals the MLA 40 upon the MCU 26 performs a scan operation. First, MLA 40 sets the SCANMODE signal to indicate that data is to flow to the MLAs 40 on the memory boards and thereafter serially outputs the contents of BDID and BDSTAT via the SCANOUT signal lines to all the MLAs 40 on the memory boards. As the contents of BDID and BDSTAT arrive at each of the MLAs 40 the MLAs serially input the ID data into their BDID registers and the status information into their BDSTAT registers. When these five bits of data have been inputted SCANMODE makes a transition from low to high, causing each MLA 40 on memory boards 12 and 14 to compare the received board ID value with the ID value indicated by signal lines. If a match occurs the MLA 40 on the specified memory board sets the two board status flip/flops from the value of BDSTAT and also sets a flip/flop which enables the MLA 40 to drive the SCANOUT signal line. Those MLAs not detecting a match between BDID and their ID inputs reset their SCANOUT enabling flip/flop, thereby ensuring that only one MLA is enabled to drive SCANOUT during any given scan. Of course, these nonselected MLAs do not change the state of their status flip/flops. During the initial scan of each of the MLAs the system console 30 preferably provides the current value of BDSTAT so that no change of state occurs in the selected MLA's status flip/flops. Subsequent to the transmission of BDID and BDSTAT, the aforementioned change of state from low to high of SCANMODE indicates that data is to flow from the selected MLA 40 on the memory board to the MLA 40 on the MCU 26. The selected MLA 40 upon the memory board responds to the change of state of SCANMODE by serially outputting on SCANOUT the contents of BDBA (ADRREG[0:5]), BDMATCH, BDSIZE and BDID via the SCANIN signal line to the MLA 40 on MCU 26. In addition, the selected MLA first outputs an active low signal BRDINSLOT which is indicative, when asserted, that a memory board is physically installed within the addressed slot. If BRDINSLOT is later determined to be high the other data fields can be ignored. When the registers within the MLA 40 of MCU 26 have been loaded with this data, the MLA 40 on MCU 26 sets the MCUDR signal line to reflect the completion of the loading. The following table summarizes the aforedescribed data transfers on a cycle by cycle basis. An "X" indicates that the data appearing on the associated pin is not relevant during the corresponding cycle. SCIU 38 typically polls the value of MCUDR to determine when these values have been loaded and thereafter serially scans out of the MLA 40 on MCU 26, two bits at a time, the values of these registers. The data is subsequently transferred via SDB 36 to the system console 30. In general, if a memory error occurred because a memory board did not respond to a memory access, as opposed to an access which resulted in, for example, a double bit error, this occurrence will be indicated by the value of BDMATCH. That is, if an address was provided on MEMBUS 24 which a memory board should have responded to but did not, BDMATCH being low will indicate that this response did not occur. The following table illustrates the logical states of the SCIU ID signal lines and the corresponding data appearing on the SCIU READ data lines. SCIU CMD is assumed to be low. By sequentially scanning the memory boards coupled to MEMBUS 24 in the above described manner, the system console 30 identifies, at least from BDBA and BDSIZE, which memory board and which memory array thereon includes the address or range of addresses at which the failure occurred. Having determined which of the memory boards and which portion thereof has malfunctioned, system console 30 thereafter again initiates a scan of the MLA 40s as previously described. However, during this subsequent scan the BDSTAT of the MLA 40 on the defective memory board is changed to disable the malfunctioning memory array(s). When the MLA 40 on the defective memory board scans in the revised status information the MLA 40 determines a new value for BDBA, thereby decreasing the value of BDBA by an amount equal to the amount of the memory which has been disabled. That is, the system console 30 scans the MLA 40 and sets BDSTAT as required by that memory board. The MLAs 40 on subsequent memory boards automatically determine the address ranges for their associated memory boards in the newly reconfigured memory address space. This is accomplished by each MLA 40 changing the state of the base address output signal lines such that an adjacent MLA in the sequential chain of MLAs determines a new value for its base address output signal. After scanning the last memory board a system address having a value greater than the highest address corresponding to installed memory will be indicated by the base address output signal lines of MLA 40 on MCU 26. This value is preferrably utilized as an illegal address threshold value against which incoming addresses associated with a memory request are compared. Referring now to Fig. 3 there is shown a block diagram of a portion of the circuitry within one of the MLAs; specifically that circuitry which is utilized on an MLA 40 upon one of the memory boards 12. In Fig. 3 it can be seen that the MEMCLK input is divided by four to provide a MEMCLK/4 signal which is utilized for internal timing within the MLA. The SCANIN pin is coupled to the input of a serial data reception means, such as a shift register 50, the register being clocked with MEMCLK/4. Data sourced fromthe MLA 40 upon MCU 26 is clocked into shift register 50 until four bits of data have been so clocked in. After transmitting the fifth bit of data the state of the SCANMODE pin is changed by the MLA 40 from a logic zero to a logic one which enables a comparison of the board ID inputs with the board ID clocked in. This comparison is accomplished by a comparison means, such as a comparator 52, which has an output a signal SCANOUT ENABLE. In addition, the two BDSTAT signals are clocked into storage means, such as status flip/flops 54a and 54b. The status outputs of flip/flops 54a and 54b are combined with the BDSIZE inputs in an ADDER logic block 56 which has outputs which are provided to an adding means, such as an ADDER circuit 58. ADDER circuit 58 also has as inputs the base address input signal lines. As previously described, these input signal lines for the MLA 40 on memory board 12 may be a logic zero and for other MLAs are a function of the base address output signals of a previous MLA. ADDER 58 effectively adds output signals from the ADDER logic block 56 to the base address input signal lines to provide the six base address output signal lines. The base address output signal lines are thus greater than the base address input signal lines by an amount equal to board size less the amount of memory which is disabled, as indicated by the status flip/flops. The MLA 40 also comprises an address comparison means, such as a comparator 60, which compares the address inputs A2-A7 from MEMBUS 24 to determine if the A2-A7 address signal lines correspond to a range of addresses upon the memory board. A2-A7 are typically the MSBs of the memory address bus. Address comparator 60 has a MATCH output which is true if the A2-A7 address inputs indicate that the addressed memory location is upon the corresponding memory board. BDMATCH is the registered version of the MATCH output and is stored within a flip/flop 62. The MATCH output is utilized, in conjunction with memory enable logic 63, to initiate an access to memory devices within a given memory array as defined by the address and control signal lines which comprise MEMBUS 24. If one or both of the outputs of status flip/flops 54a or 54b are set access to the corresponding memory array is disabled. The SCANOUT ENABLE signal being true indicates that the MLA has been addressed by the MLA upon the MCU 26. The addressed MLA thereafter drives onto its SCANOUT signal line the values of the various internal signals as previously described. This is accomplished in part by a parallel to serial conversion means 64, which may comprise a sequential chain if flip/flops and multiplexers. The SCANOUT signal line is connected, as previously described, to the SCANIN pin of the MLA 40 upon the MCU 26. Referring now to Fig. 4 there is shown circuitry operable for implementing the transmission of data from the MLA 40 on MCU 26 to the SCIU 38. A pair of multiplexers 70 and 72 each have selection inputs coupled in common to the SCIU ID signal inputs and a plurality of data inputs coupled to register outputs of MLA 40; the register outputs reflecting the data previously scanned in from a selected MLA 40 on one of the memory boards. Multiplexers 70 and 72 each have an output which is gated with SCIU CMD to provide signals a counter. Flip/flop 74 is reset by the aforedescribed SCIU ID code 111 asserted in conjunction with SCIU CMD being low. It should be realized that a presently preferred embodiment of the invention has been presented and that modifications to this embodiment may occur to those having skill in this art. For example, although the MLA 40 of the presently preferred embodiment is comprised of a highly integrated gate array semiconductor device the invention may be equally well realized by a number of circuit means, including discrete integrated circuit devices such as multiplexers, flip/flops and gates. Furthermore, although the invention has been described in the context of a system console coupled by a serial diagnostic bus to a SCIU device for interfacing to the MLA 40 on MCU 26 it can be appreciated that any suitable means may be employed for interfacing to the MLA 40. For example, the MLA 40 upon MCU 26 may be directly coupled to I/O pins of a microprocessor device or to logic devices configured for inputting and receiving data from the MLA 40 in accordance with the protocol described above.

Claims: A digital data processing system comprising a plurality of memory units (18, 22) each of which is coupled by a first bus (24) to a memory control unit (26), said first bus (24) coupling said memory units to the memory control unit for transferring at least memory addresses from the memory control unit to the memory array, the memory control unit being coupled to a system bus (28) for decoding address and control signals of said system bus for controlling memory accesses to said memory units, each of said memory units having a plurality of data storage addresses organized into one or more arrays of data storage locations (16, 18, 20, 22), the data storage addresses of each of said memory units being contiguous to another logically adjacent memory unit, characterized in that: a base address of a given memory unit, except for a first memory unit, is generated by generating means (56,58) contained within a logically contiguous memory unit and received therefrom through base address output signal lines (46) ; and wherein said system further comprises an interface means (40) for coupling to a second bus (42) that couples the plurality of memory units to the memory control unit, the second bus comprising: a first bit serial signal line (SCAN IN) for transferring, when active, information from the memory control unit to the memory units ; a second bit serial signal line (SCAN OUT) for transferring, when active, information from the memory units to the memory control unit ; and a third signal line (SCAN MODE) for conveying either a first logical state for indicating that the first bit serial signal line is active or a second logical state for indicating that the second bit serial signal line is active. A digital data processing system as defined in Claim 1 and further characterized in that said interface means comprises a first memory logic array, coupled to said second bus (42), that is responsive to the state of the third signal line for receiving information from and for transmitting information to the memory control unit, and wherein the memory control unit comprising a second memory logic array coupled to said second bus for receiving information from and for transmitting information to the first memory logic array. A digital data processing system as defined in Claim 2 wherein said first memory logic array is further characterized by first determining means for determining a total storage capacity of the memory unit; second determining means for determining a base memory address of the memory unit; and third determining means, coupled to the first and the second means, for determining a base memory address of another memory unit. A digital data processing system as defined in Claim 3 and further characterized in that each memory unit has an associated predefined and unique memory unit identification code (BDID) and further includes disabling means (54a, 54b) for selectively disabling said at least one memory array, wherein the information received by the first memory logic array from the second memory logic array is information related to the disabling of a portion or portions of the data storage means on an identified memory unit, the information being provided to said means for selectively disabling said at least one memory array. A digital data processing system as defined in Claim 4 and further characterized in that the information related to the disabling of said at least one memory array is determined by a system console means (30), the information being provided by the system console means over a third bus (36) to a system console interface means (38) within the memory control unit, the system console interface means being coupled to the second memory logic array for providing the information thereto. A digital data processing system as defined in Claim 5 and further characterized in that the third determining means is further coupled to the memory disabling means, and wherein the determined base memory address of another memory unit is decreased by an amount substantially equal to an amount corresponding to a number of addressable storage locations that comprise the disabled memory array. A digital data processing system as defined in Claim 6 and further characterized in that said third bus comprises a pair of bit serial signal lines. A digital data processing system as defined in claim 1 and further characterized as: said digital data processing system further comprises a system console (30) that is coupled over a third bus (36) to a system console interface means (38) within the memory control unit (26), said system console including means, responsive to an occurrence of a memory error at an address location within a range of address locations defined by the memory units, for outputting to the memory control unit (26) a memory unit identification code (BDID) that uniquely identifies one of the memory units and for outputting status data expressive of one or more arrays, if any, of data storage locations that are disabled upon the identified memory unit, said system console storing a record of the memory unit identification codes and the corresponding status data; said memory control unit (26) comprises interface means (40) for outputting in a simultaneous manner to each of the memory units over said second bus (42) the memory unit identification code and the status data that is received from said system console (30) over said third bus (36); each of said memory units comprises comparing means (52) for comparing the received memory unit identification code to a predefined memory unit identification code to determine a match therebetween; and outputting means (64), responsive to a detection of a match, for outputting data to the memory control unit, the outputted data being comprised of a plurality of data fields expressive at least of: a base memory address of a logically contiguous memory unit; a number of data storage locations which comprise the memory unit; and the predefined memory unit identification code of the memory unit. A digital data processing system as defined in claim 8 and further characterized as: said memory control unit (26) receives the data transmitted from the presently identified memory unit through said interface means (40); and said digital data processing system further comprises : further interface means (38) for transmitting the received data to said system console (30) over said third bus (36); wherein said system console (30) is responsive to the received data transmitted from the memory control unit over said third bus (36) for determining if the address location of the memory error is within a range of addresses upon the presently identified memory unit, as determined from the base memory address data field and from the number of storage locations data field, and if the memory error is determined to be within the presently identified memory unit, for identifying, in cooperation with the base memory address data field and the number of data storage locations data field, a memory array within the presently identified memory unit having the memory error, said system console unit further comprising means for outputting to third bus (36) the identified memory unit identification code and revised status data expressive of one or more banks of data storage locations which are to be disabled upon the identified memory unit. A digital data processing system as defined in claim 9 and further characterized as: said interface means (40) is responsive to the identified memory unit identification code and revised status data for outputting to each of the memory units over said second bus (42) the identified memory unit identification code and the revised status data; and said memory units include means (54a, 54b), responsive to an operation of said comparing means (52) detecting a match with the memory unit identification code received from the memory control unit (26), for disabling the one or more arrays that are specified by the revised status data; said memory units include generating means (56, 58), responsive to an operation of said comparing means (52) detecting a match with the memory unit identification code received from the memory control unit (26), for generating a revised base memory address for a logically contiguous memory unit, the revised base memory address being decreased by an amount substantially equal to a number of data storage locations within the one or more disabled memory banks; and outputting means for outputting the revised base memory address to the logically contiguous memory unit such that the logically contiguous memory unit is enabled to generate a revised base memory address for another memory unit.

Inventors: BECKER ROBERT D, COYLE RICHARD W, CURCURU KEVIN H, GIUNTA RICHARD F, SCHWARTZ MARTIN J, BECKER, ROBERT D., COYLE, RICHARD W., CURCURU, KEVIN H., GIUNTA, RICHARD F., SCHWARTZ, MARTIN J.
Applicants: WANG LABORATORIES, WANG LABORATORIES INC.
Application year: 1989
Main classification: G06F11
IPC codes: G06F11, G06F12, G11C29