Electronic memory

Abstract: A four device cell is disclosed for an electrically erasable programmable logic device. The four devices include a floating gate tunnel capacitor (130), a floating gate read transistor (140) having its floating gate (148) and control gate (146) connected respectively to the floating gate (138) and control gate (136) of the tunnel capacitor (130), a read select transistor (150) for selectively coupling the drain of the floating gate read transistor (140) to a product term output (PT) in response to an input term (IT), and a write select transistor (160) for selectively coupling the drain of the floating gate tunnel capacitor (130) to a write data line (WDL) in response to the signal on a write select line (WSL). During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V cg . The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V WDL = V cg . V WDL is applied to the drain of the floating gate tunnel capacitor by applying V WDL to all the write data lines (WDL) and applying at least V WDL + V T to all the write select (WSL) lines of the array.

Description: This Application is related to our European Patent Application 86304038.2 (EP-A-0 204 498). The present invention relates to electrically erasable programmable memory cells, and more particularly to such cells as optimized for use in programmable logic devices. A typical programmable logic array (PLA), which is a type of programmable logic device, incorporates a plurality of input terms feeding a programmable AND array, the output of which feeds either a fixed or programmable OR array. The output of the OR array may or may not pass through output circuitry before being made available to external package pins. The outputs of the AND array constitute product terms, and the array is programmable to select which of the inputs are ANDed together to form each of the product terms. A typical device which incorporates the above elements is the AmPAL22V10, described in the data sheet therefor published in October 1986. It should be noted that due to the laws of Boolean algebra, any AND array may be viewed equally as an OR array, and vice versa, and either or both in combination may be implemented in other forms in a combinatorial logic array. Programmable cells for use in programmable logic devices are typically arranged into words, each word representing an input term and each row of cells in corresponding positions in different words representing a product term. Each cell has two states: one in which the input associated with the cell acts on the product term and one in which it does not. All inputs whose cells are programmed to act on a product term are wire-ANDed together to generate the resulting product term signal. Cells are typically programmable by the user either by burning selected fuses, or by electrically programming a floating gate on a MOS transistor. It has been found particularly advantageous to use floating gate MOS transistors, made programmable and erasable through the use of Fowler-Nordheim tunnelling. The resulting programmable logic device is often called an EEPLD (Electrically Erasable and Programmable Logic Device). A typical cell for use in an EEPLD is shown in Fig. 1. It includes a floating gate tunnel capacitor 10, and floating gate read transistor 12, and a select transistor 14. The floating gate tunnel capacitor 10 and the floating gate read transistor 12 have a common control gate 16, and a common floating gate 18 located physically beneath the control gate 16. The drain region of the floating gate tunnel capacitor 10 is connected to a node 20, which is also connected to the drain of the floating gate read transistor 12 and to the source of select transistor 14. The source of floating gate read transistor 12 is connected to V ss , and the source of floating gate tunnel capacitor 10 is left unconnected. Floating gate tunnel capacitor 10 includes a tunnel dielectric between the floating gate 18 and the substrate. This tunnel dielectric is made extremely thin in order to permit tunnelling of electrons between the substrate and the floating gate under the influence of the net electric field across the tunnel oxide. It should be noted that though the connected region of floating gate tunnel capacitor 10 is referred to herein as the drain, the interchangeability between drain and source in FET's renders it equally valid to refer to this region as the source of the floating gate tunnel capacitor 10. When the cell shown in Fig. 1 is placed in an AND array, the drains of all the select transistors 14 in a row are connected together to form a product term (PT). The gates of all the select transistors 14 in a word are connected together to form an input term (IT). In memory technology, product terms become bit lines (BL) and input terms become word lines (WL). Similarly the control gates 16 for all the cells in the AND array are connected to form a word control gate line (CG). The operation of the cell of Fig. 1 for writing and sensing operations is summarized in the table of Fig. 2. The write mode typically encompasses both a global charging ("programming") step followed by a selective discharge ("selective erasure"). To charge the entire array, the input terms 24 for all words in the array are raised to a voltage greater than the V T of select transistor 14. This enables conduction between the product term 22 and the nodes 20 in each cell. The control gates 16 for all cells are then raised to a high voltage V pp , and the product terms 22 are held at ground. V ss may be left floating or held at ground potential. In this way a net electric field is created across the tunnel dielectric in the floating gate tunnel capacitors and charge is drawn from the drains of the tunnel capacitors to the floating gates. Selective discharge is typically accomplished one word at a time. First the IT 24 for the selected word is brought to V pp + V T and the control gate lines 16 are held at ground. Then only the selected ones of the PT's 22 are brought to V pp . The high voltage on the input term 24 causes the drain voltage V d of the tunnel capacitors 10 in the word to track the corresponding PT voltage, so only those cells in the selected word which have V pp on their PT 22 will have a net electric field tending to discharge electrons from the floating gate to the drain of tunnel capacitor 10. V ss typically floats during selective discharge. For words which are unselected during the selective discharge operation, the input term 24 is held at ground to isolate the floating gate tunnel capacitors from product terms 22, which may be at V pp for discharging other cells connected to the product term. When operating in the read or sense mode, each word is either selected or unselected. If a word is selected (i.e., the input term for that word is high), V cc is provided to the gate of the select transistor 14. This connects the node 20 to the bit line 22. The control gate 16 of the cell is held at a read potential V cg , for example at 1 volt, so that if the floating gate 18 of the floating gate tunnel capacitor 10 and floating gate read transistor 12 are charged, the read potential is insufficient to overcome the floating gate charge to generate a channel between the source and drain of floating gate read transistor 12. Floating gate read transistor 12 therefore remains off, and the cell has no effect on the voltage of the bit line 22. If the floating gate 18 is discharged, then the read potential is sufficient to generate a channel between the source and drain of floating gate read transistor 12. Assuming V ss is held at ground potential during the read operation, the bit line 22 will be pulled from its bias potential of V PT (2 volts, for example) toward ground. If the cell is unselected (i.e., the input term is at a logic zero level), then the gate of select transistor 14 will be held at 0 volts and the charge stored on the floating gate 18 for the cell will have no effect on the voltage of the product term 22. Thus, in the read mode, only those cells which are connected to the product term 22 and which have discharged floating gates 18 can pull the product term low. Those cells will do so if and only if the input term associated with any one of those cells is high. The product term therefore carries the product of all the input values associated with cells on the product term which have discharged floating gates. All electrically erasable devices which store charge on a floating gate suffer from potential charge loss over a long period of time due to undesired tunnelling through the tunnel dielectric. Manufacturers usually specify data retention limits at ten (10) years, undesired tunnelling being one of the primary causes of data loss. If the device is unpowered, gradual loss of charge is continuous due to the potential difference between the floating gate 18 and the drain of the floating gate tunnel capacitor 10. If a device is powered, the field across the tunnel dielectric depends in part on the voltage difference between the control gate 16 and drain of floating gate tunnel capacitor 10. In theory this field could be minimized by maintaining an appropriate voltage on the control gate 16. That solution is not satisfactory, however, due to the connection of the drain of floating gate tunnel capacitor 10 to the node 20. The voltage on node 20 changes depending on the voltage level on the product term 22, on the state of charge on the floating gate 10, and on whether or not the cell is selected for read (the state of the input term 24). Since it is not very practical to include circuitry within every cell to adjust the control gate voltage according to all these conditions, typically an intermediate value for V cg is chosen and gradual charge loss is tolerated. The problem exists in EEPROMs too, but it is much worse in EEPLDs for two reasons. First, note that read disturb is most severe when a cell is selected since the voltage V d will typically be at least about one volt above or below V cg , depending on the product term voltage. This may be tolerable in an EEPROM, since only one cell on each product term (bit line) is selected at a time. In an EEPLD, however, each input term has a corresponding input term. At all times, therefore, about half the cells in the array are selected. The probability that a given cell will be selected at any given time is therefore much greater in an EEPLD, making the potential for read disturb correspondingly greater. Secondly, the nature of EEPROMs is such that they will be re-programmed much more frequently than will electrically erasable programmable logic devices. Typically EEPROMs are specified for 100 times the number of writes as EEPLDs. Since the data retention period begins anew each time the array is reprogrammed, the data retention period is much less likely to play an important role toward the end of the lifetime specified for an EEPROM than for an EEPLD. U.S. Patent No. 4,545,454 to Gupta discloses at Fig. 3 an electrically erasable programmable memory cell circuit for use as an enabling element for a redundant row or column of memory cells in a semiconductor memory array. While the Gupta cell may alleviate some of the problems of other prior art cells, it does not solve them completely. For example, during read mode, there is no access to the control gates of unselected cells since the transistors 214 are turned off. Control of the field across the tunnel dielectric is therefore not permitted when a cell is unselected. We will now describe an electrically erasable memory cell which alleviates the above problems. We will describe an electrically erasable programmable cell which minimizes read disturb. We will describe an electrically erasable programmable cell which minimizes the potential across the tunnel dielectric in the worst case during the read mode. We will describe an EEPLD having programmable cells with minimized read disturb. Reference may be made to US-A-4 695 979 which discloses a memory apparatus comprising an array of memory cells, as indicated in the preamble of claim 1. A similar memory apparatus is disclosed in US-A-4 663 740. It provides, instead of a floating gate tunnel capacitor, a second floating gate transistor, and further does not include connecting means for controlling write accesses to the first floating gate transistor. SUMMARY OF THE INVENTION The present invention provides non-volatile memory apparatus as specified in claim 1. It comprises an array of memory cells, each of said cells in said array comprising a floating gate tunnel capacitor, and including means for connection to an input term, means for connection to a product term said array being organized into N words of M cells each, said array comprising a plurality of input terms each connected to all of the cells in a respective word, a plurality of product terms each connected to a corresponding cell in all of said words, each of said cells including means for connection to a write select line, means for connection to a write data line and, a floating gate read transistor having a floating gate connected to the floating gate of the floating gate tunnel capacitor, said floating gate tunnel capacitor and said floating gate read transistor each having control gates connected together, a plurality of write select lines are provided, each connected to all of the cells in a respective word N, a plurality of control gate lines are provided each connected to all of the floating gate tunnel capacitors and floating gate read transistors in a respective word N, a plurality of write data lines are provided, each connected to a corresponding cell in all of said words, and said input term for each given one of said words being distinct from said write select line for said given one of said words. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with respect to specific embodiments thereof. Other objects, embodiments and features of the invention will be apparent from a reading of the detailed description in conjunction with the drawings, in which: Fig. 1 schematically shows a prior art cell; Fig. 2 is a table showing typical bias voltages for use with the cell shown in Fig. 1; Fig. 3 shows an electrically erasable programmable logic device in which the invention may be implemented; Fig. 4 schematically shows a cell constructed according to the invention; Fig. 5 is a table showing typical bias voltages for use with the cell shown in Fig. 4; Fig. 6a shows a plan view of a layout which may be used to fabricate the cell shown in Fig. 4; Figs. 6b and 6c are cross-sectional views of the layout of Fig. 6a, taken along, respectively, planes b-b′ and c-c′; and Fig. 7 is a plot useful for explaining the advantages of the cell of Fig. 4 over the cell of Fig. 1. DETAILED DESCRIPTION Shown in Fig. 3 is a typical EEPLD architecture for PLA applications incorporating the present invention. It includes an AND array 100 having a plurality of lines controlled by control circuitry 102. The control circuitry 102 has N input pins, labeled i₀ through i N-1 , and the AND array 100 has M product outputs, labeled P₀ through P M-1 . The product outputs P₀-P M-1 are fed to inputs of an OR array 104, the outputs of which constitute outputs of the EEPLD. Though the illustration in Fig. 3 shows the OR gates in OR array 104 having inputs connected to fixed subsets of the product outputs P₀-P M-1 , it will be understood that the selection of these subsets may be made programmable themselves, by means which may or may not themselves incorporate the present invention. Similarly, the outputs or OR array 104 may be further connected to output circuitry incorporating registers or programmable output logic macro cells, not shown, and may or may not include feedback paths to the input pins i₀-i N-1 . AND array 100 comprises an array of cells 110, shown as circles in Fig. 3. These cells are arranged into N words of M cells each, each word being shown as a vertical column in the drawing of Fig. 3. Corresponding cells in the different words are arranged in a horizontal row. Though the organization of the AND array 100 may be referred to herein according to rows and columns, it will be understood that words of cells need not be organized physically as such as long as logical words are maintained. Three different lines are connected to all the cells in each word. These lines are referred to as an input term (IT), a write select line (WSL), and a control gate line (CGL). Similarly, three different lines are connected to all the cells in each corresponding position of all the words. These lines are referred to herein as the write data line (WDL), the product term (PT), and a source potential V ss . The purpose of these six lines will be explained in more detail below in connection with the detailed description of a cell embodiment. At this point, however, it is worthwhile noting that the control circuitry 102 can operate the AND array in either a sense mode or a write mode. In the sense mode, the input terms (IT) carry signals corresponding to the input signals on i₀-i N-1 and the product terms (PT) carry the product terms. In the write mode, the write select lines (WSL) carry signals indicating which word or words are to be written, while the write data lines (WDL) and control gate lines CGL carry the necessary charging or discharging potentials. The product terms (PT) are each connected to the input of a sense amplifier 112, the outputs of which constitute the P₀-P M-1 outputs of AND array 100. It should be noted that the diagram of Fig. 3 is only illustrative, it being intended only to provide a context in which the inventive cell may be used. In Fig. 4 there is shown a cell 110 according to the invention. It comprises a floating gate tunnel capacitor 130 having a source 132, a drain 134, a control gate 136 and a floating gate 138. A floating gate read transistor 140 is also provided, having a source 142, a drain 144, a control gate 146 and a floating gate 148. The floating gate 148 of the floating gate read transistor 140 is connected to the floating gate 138 of the floating gate tunnel capacitor 130, and the control gate 146 of the floating gate read transitor 140 is connected to the control gate 136 of the floating gate tunnel capacitor 130. The two control gates 136 and 146 are also connected to the control gate line CGL for the cell. Connected to the drain 144 of the floating gate read transistor 140 is the source 152 of a read select transistor 150. A drain 154 of the read select transistor 150 is connected to the product term for the cells, and a gate 156 of the read select transistor 150 is connected to the input term IT for the cell. Connected to the drain 134 of floating gate tunnel capacitor 130 is the source 164 of a write select transistor 160. A drain 162 of the write select transistor 160 is connected to the write data line for the cell, and a gate 166 of the write select transistor 160 is connected to the write select line for the cell. The source 142 of floating gate read transistor 140 is connected to the V ss line for the cell, and the source 132 of floating gate tunnel capacitor 130 is left unconnected. Fig. 5 is a table showing typical potentials for operating the cell of Fig. 4. As in the conventional cell, data is written into the array first by charging all the cells in the array and then discharging selected cells, word by word. The global charge is accomplished by raising all the control gate lines CGL to V pp while the drains 134 of all of the floating gate tunnel capacitors 130 are held at ground. The drains 134 are held at ground by holding all the write data lines WDL at ground and raising the write select lines WSL for all cells to some potential above the V T of the write select transistor 160. During this time, the V ss and product term lines PT are held at ground while the input terms IT are raised to V cc . Alternatively during this time, the product terms can be raised to some voltage and the input terms raised to a voltage at least one V T higher, so that the coupling from drain 144 of floating gate read transistor 140 to the floating gate 148 can help increase the charging field across the tunnel dielectric in the capacitor 130. V ss should float if the latter alternative is used so as to prevent large current flow through the read select transistor 150 and the floating gate read transistor 140. In another alternative during this time, V ss may be raised to some potential to increase the charging field while the input terms are held at ground level to prevent large current flow. Selective discharge is accomplished one word at a time. The control gate lines CGL for all cells are brought to ground, while the drains 134 of the floating gate tunnel capacitors 130 for only the selected cells in the selected words are raised to V pp . The latter function is accomplished by raising the write select line WSL for the selected word to V pp plus one V T for the write select transistor, and by raising the WDL for the selected cells to V pp . Any cell whose write select line is at ground, or whose write select line is at V pp + V T but whose write data line is at ground, is unselected and not discharged. All product terms are kept at 0V during selective discharge, and all input terms kept at least one V T (of read select transistor 150) above ground. V ss may be at ground or floating. Typically, the programming potential V pp may be between 13 and 20 volts depending on the technology used, and V T is approximately 1 volt. Several variations of the above typical programming potentials are possible. For example, since the purpose of placing a high voltage on the write select line is only to provide a conduction path between the drain 134 of the floating gate tunnel capacitor 130 and the write data line, it can be seen that if the cell is to be charged (with WDL = 0 volts), then the write select line need be brought only to V T . An intermediate value between V T and V pp , such as V cc , would also suffice. It should be noted that unlike the conventional cell shown in Fig. 1, the cell of Fig. 4 includes two separate cell data lines PT and WDL. In this approach, therefore, no high programming voltages V pp need be applied to the read select transistor 150 or to the floating gate read transistor 140. Consequently, the channel lengths of these devices can be made shorter thus reducing read product term capacitance, increasing cell current gain and substantially improving the circuit's speed performance. Referring again to the table of Fig. 5, typical potentials for using the cell of Fig. 4 in the sense mode will now be described. The device will spend most of its life in the sense mode, so it is here where charge loss from or gain to the floating gate must be minimized. When the device is in the sense mode, the product terms are all biased initially at a bias voltage V PT . In a 5-volt device, V PT may be approximately 2 volts. Additionally, all the control gate lines CGL are held at a read voltage V cg , chosen to be at a value between the charged and discharged threshold values of the floating gate read transistor 140. A higher V cg (closer to V Tc ) yields a stronger gate drive, thereby permitting a larger current flow on sense. On the other hand, a higher V cg also reduces the margin for process variations and for charge loss. Advantageously, as explained in more detail below, the floating gate read transistor 140 may be a near intrinsic transistor, in which case V cg may be approximately 1 volt. To complete the sense operation, the V ss lines for all cells are brought to ground while the input term for only the selected cells (i.e., all "input" terms) are brought to V cc . The remainder of the input terms (i.e., all " input " terms) are held at 0 volts. Therefore, in order for a particular cell to pull its product term toward ground, channels must be induced in both the read select transistor 150 and the floating gate read transistor 140. This cannot happen if the floating gate 138, 148 in the cell is charged, and the read potential V cg is less than the threshold voltage V Tc for a charged transistor. If the floating gate 138, 148 is discharged, however, the read voltage V cg will provide added gate drive to potential already existing on the floating gate and a channel will exist between the source and drain of floating gate read transistor 140. In this situation, whether the PT is pulled low depends almost entirely on the voltage of the input term (i.e., the input signal). That is, if the input signal is high, PT will be pulled low. If the input term IT is low, the cell will have no effect on PT. Since the write data line is not needed for the sense operation, it is available to help control the voltage potentials on the floating gate tunnel capacitor 130. According to the invention, while the device is in the sense mode, all the write data lines WDL are kept at a constant voltage V WDL . That potential is transmitted to the drain 134 of floating gate tunnel capacitor 130 through a channel created under write select transistor 160 by keeping the write select line at at least V WDL plus one V T of the program select transistor 160. Advantageously, V WDL = V cg , and for convenience the write select line WSL is kept at V cc . The drain 134 and control gate 136 of the floating gate tunnel capacitor 130 are thereby maintained at the same voltage and, as is shown below, this reduces the worst-case net electric field across the tunnel dielectric. It can be seen that in the writng and sensing operations described herein, all the control gate lines CGL at any given time are at the same voltage. In a preferred embodiment, therefore, all of the control gate lines are permanently connected together with a metal interconnect. As previously mentioned, it is advantageous but not essential that the floating gate read transistor 140 be a substantially intrinsic transistor. This permits fabrication of a device with one fewer masking step, since no depletion or enhancement implant is required. The only channel doping which causes this transistor to differ from a truly intrinsic transistor is the light doping, usually p-type, provided in the bulk substrate. Additionally, for a substantially intrinsic floating gate transistor, the charged and discharged threshold values V Tc and V Td will form a window centered approximately about zero (0) volts. This permits using a control gate read voltage V cg of no more than about 1 volt, thereby minimizing the long-term stress on the tunnel dielectric layer. Formation of the thin tunnel dielectric is a difficult step in the manufacturing process, and a reduction in long-term stress here permits a greater margin for processing. If the floating gate read transistor 140 does have some channel doping, the values of V cg and V WDL are altered accordingly. Fig. 6a shows a plan view of a cell manufactured according to the invention. Fig. 6b is a cross section taken from plane b-b′, and Fig. 6c is a cross section taken from plane c-c′. The device may be fabricated in any known manner, but the method set forth in the related application is preferred. As fabricated, the read select transistor 150 is formed with N⁺ drain and source regions 154 and 152, respectively, under a select gate 156 formed with a poly-2 layer. Similarly, write select transistor 160 is formed with N⁺ source and drain regions 162 and 164, respectively, formed under a poly-2 select gate 166. Floating gate read transistor 140 consists of N⁺ source and drain regions 142 and 144, respectively, the N⁺ region forming the drain 144 of the floating gate read transistor 140 being common with the N⁺ region forming the source 152 of read select transistor 150. The tunnel capacitor 130 includes N⁺ source and drain regions 132 and 134, and N-doped tunnel implant region 210, and a gate structure. The gate structure comprises a first dielectric layer (not shown specifically) having a thin tunnel dielectric region 220, floating gate 138 formed in a poly-1 layer, an interpoly dielectric (not shown) and a control gate 136 formed in the poly-2 layer. The poly-1 and poly-2 layers forming respectively the floating gate 138 and control gate 136 of the tunnel capacitor 130 extend across to the floating gate read transistor to form, respectively, the floating gate 148 and control gate 146 thereof. The N⁺ region forming drain 134 of tunnel capacitor 130 is the same as the N⁺ region forming source 164 of the write select transistor 160. The tunnel capacitor/floating gate read transistor combination shown in Fig. 4 may be fabricated using the same technology, dimensions and doping levels as the tunnel capacitor/floating gate read transistor shown in Fig. 1. Assuming that is done, the improvement made possible by the invention may be quantified using a simplified analysis set forth below. For the purposes of this analysis, the following capacitances are defined (CG = control gate; FG = floating gate): C g = CG to FG capacitance C tunn = tunnel region drain to FG capacitance C ch = read transistor channel to FG capacitance C subs = substrate to FG capacitance. Since the capacitor forming C subs crosses the thick field oxide between the tunnel capacitor and the floating gate read transistor, C subs is small and may be ignored in this first order calculation. The following coupling coefficients are also defined: CG to FG coupling: α g = C g C g + C tunn. + C ch Tunnel region drain to FG coupling: α tunn = C tunn C g +C tunn +C ch Read transistor channel to FG coupling: α ch = C ch C g + C tunn + C ch It should be noted that C ch is larger when the floating gate read transistor is on than when it is off. This is because when the transistor is on, the depletion region extends all the way from source to drain. The capacitor is therefore formed between the floating gate and the entire channel. When the transistor is off, the depletion region is much smaller. The capacitor is therefore formed over a significantly smaller area. The coupling ratio α ch is therefore larger for an "on" transistor than for an "off" transistor. The other coupling ratios α g and α tunn also depend on the state of the floating gate read transistor, but by a much smaller amount since the denominator of the fractions defining these quantities is much larger than the range by which C ch varies. Using the above definitions, the following voltages are present on the floating gate in the conventional cell of Fig. 1 during sensing. The floating gate read transistor is assumed to have an intrinsic threshold (with no charge on the floating gate) of V T0 ≈0. The charged threshold value V Tc is therefore greater than zero and the discharged threshold value V Td is less than zero. (a) Conventional cell, discharged state, threshold=V Td : V F =α g V T0 + α g V cg + V d (α tunn + α ch ) + α g |V Td | (b) Conventional cell, charged state, threshold = V Tc : V F =α g V T0 + α g V cg + V d (α tunn + α ch ) - α g V Tc Note that as previously explained, V d varies in this conventional cell depending on whether or not the cell is selected (IT = V cc , for example) and whether or not another cell connected to the product term is pulling it down. Typically V d ranges between 0 and 2 volts. Similarly, the following voltages are present on the floating gate in the cell of Fig. 4 during sensing. The floating gate read transistor 140 is again assumed to have an intrinsic threshold voltage of V T0 ≈ 0. As previously explained, in accordance with the table of Fig. 5, WDL and hence the drain 134 of the floating gate tunnel capacitor 130 is assumed for the purposes of this illustration to have a voltage equal to the read voltage (V cg ) on the control gate line. (c) Inventive cell, discharge state, threshold = V Td : V F = α g V T0 + α g V cg + α tunn V cg + α ch V d + (α g + α tunn )|V Td | (d) Inventive cell, charged state, threshold = V Tc : V F = α g V T0 + α g V cg + α tunn V cg + α ch V d + (α g + α tunn )(-V Tc ) V d varies in the inventive cell to the same extent that it varies in the conventional cell, but the differences in the equations render the effect of V F slight. Illustratively, for a competitive technology, the following process parameters may be used to fabricate either the conventional or inventive cell: CG/FG common area = 56µm² Effective tunnel dielectric area = 1.4µm² Effective tunnel capacitor area (less tunnel dielectric area) = 2.2µm² FG read transistor: FG/effective transistor area = 5.92µm² FG read transistor effective channel width = 3.7µm Tunnel dielectric thickness = 80Å FG to substrate gate oxide thickness = 295Å CG to FG interpoly dielectric equivalent oxide thickness = 420Å The above parameters yield the following coupling coefficients: α g = 74.6% α tunn = 14.0% α ch = 1.4% (charged cell) α ch = 5.3% (discharged cell) Inserting these values into the equations above for V F , and subtracting the voltage of the drain of the tunnel capacitor (V d for the conventional cell and V cg for the inventive cell), equations may be obtained for the voltage ΔV TunnOx across the tunnel dielectric as a function of the charged and discharged threshold voltages V Tc and |V Td |. These equations are plotted in Fig. 7. Only two curves are shown for the inventive cell, whereas four are shown for the conventional cell, because the coupling between V d and the floating gate in the inventive cell is very small. Two additional curves are necessary to describe the conventional cell since the change in V d has a much greater effect on ΔV TunnOx . It is assumed that V d = 0V when the cell is unselected and V d = 2V when the cell is selected. For the purpose of comparing two cell structures for data retention, it is necessary to compare the worst-case situation of each. Fig. 7 shows that for a discharged conventional cell, there is a stronger electric field across the tunnel dielectric if the cell is unselected than if it is selected. The unselected cell is therefore the worst case since electrons tunnel across the tunnel dielectric more freely. Similarly, for a charged conventional cell, the worst case occurs when the cell is selected. It can be seen that the electric field across the tunnel dielectric is always significantly weaker in the inventive cell than it is under the worst-case conditions in the conventional cell. This is true for at least all |V T | above 1 volt, the lowest |V T | that can be expected during the life of the part. The inventive cell will therefore retain its programmed data for a longer period of time than the conventional cell operating under worst-case conditions. Additionally, it has been found that in all floating gate cells using Fowler-Nordheim tunnelling, the values of V Tc and V Td tend to decay over the life of the device due to various phenomena which are mostly dependent on the magnitude of the electric field across the tunnel dielectric. The weaker electric field therefore also provides the additional advantage of reducing the rate of this decay. The manufacturer of a device incorporating the inventive cell may therefore specify a longer lifetime for the part. Alternatively, if the specified lifetime of the device is not increased, the V Tc /V Td window will be larger than in the conventional cell at the end of the part's specified life. A larger end-of-life window permits greater design margin and greater tolerance to variations in tunnel dielectric thickness. It also results in a larger distribution of higher-speed parts, because of increased gain in the floating gate read transistor and reduced capacitance on the product term. Fig. 7 shows that even when the threshold voltages have decayed to V Tc = 1.5V and V Td = -1V, which are typical end-of-life values for the conventional cell, the inventive cell still has a significantly smaller ΔV TunnOx and tunnel dielectric electric field than the conventional cell in the worst case. As previously mentioned, the voltage V WDL on the write data line of the inventive cell during sense mode may be a constant voltage other than V cg . It can be seen that different values for V WDL have the effect of raising or lowering the dashed lines in Fig. 7. Thus, the inventive cell may be adapted for the particular needs of the manufacturer. For example, if some other mechanism is provided to prevent charge loss in a charged cell, or if charge loss from a charged cell is prevented inherently in the fabrication process, the chip design may be optimized to prevent charge gain in a discharged cell by selecting an appropriate V WDL . The invention has been described with respect to particular embodiments thereof. Numerous variations are possible as will be apparent to a person of ordinary skill after reading the present specification. For example, though all transistors shown or described herein are N-channel transistors in a P-type substrate, it will be understood that P-channel transistors in an N substrate may be used instead. As another example, though the inventive cell is shown herein as being used in an AND array of an EEPLD, it will be understood that it may also be used to accomplish programmability in the OR array or in other programmable components of the EEPLD such as an output logic macrocell. It may also be used for redundancy fuses, and in non-EEPLD devices including EEPROMs. As another example, though Fig. 6 shows a double poly construction of the inventive cell, the invention applies equally to other technologies including a single poly technology where the control gate of the tunnel capacitor is formed from a source drain diffusion. Additionally, though the write process has been described as a global charge followed by a selective discharge, the invention works equally well for any write process. For example, a global discharge followed by a selective charge will work, as will selective charge and discharge of individual cells. Moreover, whereas the above description uses V WDL to control the voltage of the tunnel capacitor drain, it will be understood that V WDL may instead be kept at a high voltage and V WSL varied appropriately. The voltage of the tunnel capacitor drain is then V WSL -V T . All these variations and others are intended to be within the scope of the present invention as defined by the claims.

Claims: Non-volatile memory apparatus comprising an array (100) of memory cells (110), each of said cells in said array comprising a floating gate tunnel capacitor (130), a floating gate read transistor (140) having a floating gate connected to the floating gate of the floating gate tunnel capacitor (130), said floating gate tunnel capacitor (130) and said floating gate read transistor (140) each having control gates connected together, first connecting means (150) controlled by an input term (IT), for connecting the floating gate read transistor (140) to product term (PT); second connecting means (160) for connecting the floating gate tunnel capacitor (130) to a write data line (WDL), said array being organized into N words of M cells each, said array comprising a plurality of said input terms (IT₀-IT N-1 ) each connected to all of the cells in a respective word, a plurality of said product terms (PT₀-PT M-1 ) each connected to a corresponding cell in all of said words, characterized in that said second connecting means (160) is controlled by a write select line (WSL); a plurality of said write select lines (WSL₀-WSL M-1 ) are provided, each connected to all of the cells in a respective word, a plurality of said control gate lines (CGL) are provided each connected to all of the floating gate tunnel capacitors and floating gate read transistors in a respective word, a plurality of said write data lines (WDL₀-WDL M-1 ) are provided, each connected to a corresponding cell in all of said words, and said input term (IT) for each given one of said words being distinct from said write select line (WSL) for said given one of said words. Apparatus according to claim 1, wherein said product term for each given one of said corresponding cells in all of said words is distinct from said write data line for said given one of said corresponding cells in all of said words. Apparatus according to claim 2, wherein said floating gate tunnel capacitor in each of said cells in said array comprises a drain (134), a floating gate (138) and a control gate (136). Apparatus according to claim 1, wherein each of said cells in said array further comprises: said floating gate read transistor (140) having a source (142), a drain (144), a floating gate (148) and a control gate (146), said first connecting means comprising a read select transistor (150) having a source (152), a drain (154) and a select gate (156), said source of said read select transistor in said cell being coupled to said drain of said floating gate read transistor in said cell, said drain of said read select transistor in said cell being coupled to the product term (PT) for said cell and said select gate of said read select transistor in said cell being coupled to the input term (IT) for said cell; and said second connecting means comprising a write select transistor (160) having a drain (162), a source (164) and a select gate (166), said source of said write select transistor in said cell being coupled to said drain of said floating gate tunnel capacitor (130) in said cell, said drain of said write select transistor in said cell being coupled to the write data line (WDL) for said cell and said select gate of said write select transistor in said cell being coupled to the write select line (WSL) for said cell. Apparatus according claim 4 , further comprising control circuitry (102) having: a read word output corresponding to and coupled to each of said input terms (IT) in said array; a write word output corresponding to and coupled to each of said write select lines (WSL) in said array; a write data output corresponding to and coupled to each of said write data lines (WDL) in said array; and a control gate output corresponding to each given one of said words and coupled to the control gates of the floating gate tunnel capacitor (130) of all the cells in such given one of said words, said control circuitry (102) having at least a sense mode and a write mode, said control circuitry when operating in said write mode providing write select signals at said write word output and providing writing potential differences across desired ones of said control gate outputs and said write data outputs, and said control circuitry when operating in said sense mode providing said read select signals at said read word outputs, said control circuitry when operating in said sense mode further providing a potential at all of said write word outputs sufficient such that the potential of the drain of the tunnel capacitor in each given cell in said array is substantially equal to the potential of the drain of the write select transistor of said given cell, and said control circuitry when operating in said sense mode further providing a read potential at all of said control gate outputs and the same read potential at all of said write data outputs. Apparatus according to claim 5 wherein said control circuitry (102) further comprises a conductor connecting together all of said control gate outputs. Apparatus according to claim 5 said array being a programmable AND array in which said read word outputs of said control circuitry constitute inputs to said AND array, said product terms constitute product term outputs of said AND array and the pattern of programmed data in said cells in said AND array indicate which of said inputs will be wire-ANDed together to form each of said product terms, said apparatus further comprising logical OR means for providing a signal indicative of the logical OR of a particular subset of said product terms. An apparatus according to claim 1, wherein said second connecting means comprises writing means (160) for writing desired charge levels to said floating gates during a writing operation; wherein said first connecting means comprises sense means (140, 150) for sensing the charge levels on selected ones of said floating gates during a sense operation, and further comprising means for applying during said sense operation a predetermined reference voltage to the source (142) of said floating gate read transistor (140), and a predetermined sense mode drain voltage different from said reference voltage to the drain (134) of said floating gate tunnel capacitor (130), independently of the voltage at the drain of said floating gate read transistor. Apparatus according to claim 8, further comprising means for applying said sense mode drain voltage to said control gates during said sense operation, and wherein said sense mode drain voltage is between the charged and discharged threshold voltages of the floating gate read transistor in each of said cells. An apparatus according to claim 8, wherein said sense means includes circuitry applying a non-zero sense mode drain voltage to the drain of the floating gate tunnel capacitors in all of said cells. Apparatus according to claim 8, wherein said sense means further includes circuitry applying said sense mode drain voltage to the control gates of all of said cells, and wherein said sense mode drain voltage is between the charged and discharged threshold voltages of the floating gate read transistor in all of said cells.

Inventors: BRINER MICHAEL, RADJY NADER, BRINER, MICHAEL, RADJY, NADER
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1989
Main classification: G11C16
IPC codes: H01L27, G11C17, G11C16