INTEGRATED CIRCUIT COMPRISING A VERTICAL TRANSISTOR

Abstract: The invention relates to an integrated circuit comprising a vertical transistor having an emitter comprising at least one zone (12), a base (2) having a base contacting region (15) adjoining a major surface of the integrated circuit, and a collector (5). An improved inverse current amplification is obtained in the case in which the overall thickness of the base is less than or equal to the diffusion length of the minority charge carriers in these regions, when the ratio between the surface Sx of a base contacting region (15) and the surface SM of a base contact window region is at least equal to 10, and when the base contacting region (15) has a surface smaller than 5 times that of the emitter region.

Description: Integrated circuit comprising a vertical transistor. The invention relates to a semiconductor device comprising a semiconductor body with an integrated circuit having a vertical transistor comprising a collector zone of a first conductivity type, a base region of a second conductivity type disposed on at least a part of the collector region and an emitter region comprising at least one zone of the first conductivity type included in a part of the base region adjoining a major surface of the semiconductor body. In known bipolar transistors, the inverse current amplification ? defined as the ratio between the emitter current Ig and the base current I B when the collector-base junction is polarized in the inverse sense is usually not very high. However in certain applications, it is desirable to have available transistors having a high inverse current amplification β of, for example several tens. In that case, it is possible to improve the collector-base voltage V CEsat of the transistor in saturation or, whilst utilizing the transistor in the inverse sense, to realize a multi- collector transistor. The invention has for its object to provide for a semiconductor device comprising an integrated circuit with such a vertical transistor. The invention is based on the recognition that, in case the overall thickness of the base is smaller than or equal to the diffusion length of the minority charge carriers in this region, the phenomena of injection of charge carriers obey quite different rules from those admitted by the conventional theories. According to the invention a semiconductor device of the kind described in the opening paragraph is characterized in that the overall thickness of the base is smaller than or equal to the diffusion length of the minority charge carriers in this region, in that the base region comprises at least one base contacting zone having at least one contact area adjacent to the said zone of the emitter region, this base contacting zone being covered by an isolating layer having a window, through which a contact is provided to the contact area, the ratio between the surface area of the base contacting zone and the surface area of the window being at least equal to 10, and in that the base contacting zone has a surface area smaller than 5 times the total surface area of the emitter region. These dimensional ratios assure the realization of amplification values which are interesting in practice. More particularly, and paradoxically, said contact provides an improvement of the amplification which is more striking in proportion as its area in contact with the contacting zone is smaller. According to a first embodiment, the base contact area is enclosed by a unique zone constituting the emitter region. According to a second embodiment, the emitter region has at least two zones enclosing at least one surface of the said base contacting region. According to a third advantageous embodiment, the emitter region has at least two pairs of zones, the two zones of one pair enclosing a surface of said base contacting region. According to a preferred embodiment, the base region has a plurality of branches, each branch comprising a zone of the emitter region, while the base contact area is disposed in a central region with respect to the branches. The invention will be more clearly understood after reading the following description given by way of non- limitative example in conjunction with the drawings, in which: - Figures la and lb show in plan view and in sectional view, respectively, a first embodiment of the invention; - Figures 2a and 2b show in plan view and in sectional view, respectively, a second embodiment of the invention; Figures 3a and 3b show a preferred embodiment of the invention; - and Figure 4 shows a third embodiment of the invention. According to Figures la and lb, an integrated circuit in accordance with the invention comprises a p_-type substrate 1, on which a buried n + layer 5 forming the collector of the vertical transistor and then a p_-type base region 2 are provided. The buried layer 5 and the base region 2 may be formed by epitaxial growth on the substrate 1 A layer 3 of deep oxide limits on the one hand a first island 4 for the vertical transistor and on the other hand a second n + island 6 for collector contacting on the major surface of the circuit. The layer 3 of deep oxide is slightly deeper than the epitaxial layer 2. Into the base region 2 are diffused two n-type emitter regions 12, which are separated from each other and form the emitter of the transistor. The space 15 of the base 2 situated between the two zones 12 serves for base contacting. The part of the base region (2) beneath the emitter zones (12) constitutes the active base. An isolating layer 10, for example a thin oxide layer, formed on the whole surface of the integrated circuit has windows, through which the emitter regions 12, the base region 2 and the collector region 6 are contacted by a conductive layer 14, 11, 13. The base 2 is such that its overall thickness A, which in this case corresponds approximately to the thickness of the epitaxial layer, is smaller than or equal to the diffusion length of the minority charge carriers in these •regions. In this case, the Inventor has been able to recognize that the phenomenon of vertical injection can be modelled in a manner quite different from the conventional theories. In the inverse mode of operation, the collector- base junction is forward biassed, while the emitter-base is either reverse biassed or at zero voltage. The inverse amplification β j _ is the ratio between the emitter current I E and the base current Ig. The two zones 12 forming the emitter each have a width HJJ, a length L E and a surface area S E . The base region 2 adjoins at region 15 the major surface of the circuit, of which a part lying under the base window has a surface Srø and of which the other part situated under the isolating layer 10 has a surface S x . This region 15 forms a base contacting region. The injected currents are represented in Figure lb and their values partly depend upon the base-collector voltage V B C and upon the dimension of the relevant zones. The emitter current has the value: !„ = 2 S E o(e V π—Bc) e = exponential The current Irø injected under the base contact (injection under metal) has the value: The current I x injected under the oxide covering the base has the value: * * - "A < --* The current I SU b to the substrate has the value: S ub= 2S E +S X +S M> < e τ -D *V 2S E +S X> <*ΨΓ - χ) J 0-» J M' J x an( J s designate the current densities injected into the emitter, under a metallic layer into the base region, under an oxide layer into the base region and to the substrate, respectively. The recombination current in the buried layer 5 is neglected. An example is: J 0 = 500 10~ 21 A/μm 2 J M = 50 10" 21 A/μm 2 J x = 1,3 10~ 21 A/μm 2 J s = 3,5 10~ 21 A/μm 2 Assuming » 1 and V τ = 26 mV, the inverse current amplification can be expressed as: I W±th X B - I χ + Im + Isub From this equation results that, in order to have a high value of S , it is necessary that the surface S m is as small as possible, because the preponderant term of the denominator is the term of J M , which in this case largely exceeds J x and J s , and it is also necessary that S x is small with respect to S E . The inverse of the amplification 1/βχ can be expressed as: 1_ _ fx_ < J x ÷ J s> + !M_ i + £s ^1 2S E J o 2S E J o J o i.e. with the numerical values of J s , J x , J M and J 0 given above: Ϊ 1 0 0 0° (0 ' 7 + °' 48 i S fE + 5 ' s S E ) It appears that, for S M < 1/10 S x , the last term has a weight smaller than or equal to that of the foregoing but one. It is also necessary that the ratio S X /S E is chosen small in order that the value of the amplification 3 is sufficiently high. The base contacting zone must therefore have a surface area smaller than approximately 5 times the total area of the emitter (2 S in the example given above) . Let it be assumed that: H E = width of an emitter zone, L-g = length of an emitter zone, H x = width leaving room for a base contact, L jζ = length of a base contact zone. Let it be assumed that S x = H x 1^ (for SJJ < <S X ) ; let it be assumed that H x has the minimum value permitted by the method, for example 14 μm. Let it be assumed that Lg » L JJ = 25 μm and S M = 10 μm 2 . Then there is: Then the variation of J j as a function of H E is obtained. In the above example, an emitter width H E equal to 10 μm guarantees an inverse amplification S j exceeding 50. For H E •= 10 μm and L E w L JJ , the influence of L E is considered. There is: _!_ 1 β ~ 100 (1,4 + _-\ The length L E of the emitter zones has much less influence than the width of said zones. This shows that a very favourable form is that of elongate emitters. This is logical because, when Lj? is increased, S x also increases. Now the ratio of the surfaces is preponderant. The best results for β are therefore obtained for S M , L and L^ having the minimum value permitted by the method, and H E has the highest possible value attainable in practice, which corresponds to a form of transistor having elongate emitters in one or several favourable directions. Figures 3a and 3b also show a structure in the form of a cross of four branches (20 to 23) having an emitter comprising four zones 12 interconnected by a metallization strip indicated by a dotted line. Another favourable form corresponds to the case shown in Figures 2a and 2b, in which the emitter has the form of a belt closed in itself and entirely surrounding the base which has the minimum sides permitted by the method, i.e. for example: S M = 10 μm 2 S x = 120 μm 2 H E = 10 μm where: L' ■ = 11 μm The surface of the emitter then has the value: S E = 4L' E H E + 4H E = 840 μm 2 Λ . = rendering J s J x J s S x J M„ s m J o J o S„ E J o S E„ This yields a value of about JSJ = 106, with the values of J s , J jl and J Q given hereinbefore by way of example. Also this structure yields therefore a high amplification. It moreover has a lower base resistance, and a lower value with equal amplification of the junction capacitance, which renders this structure particularly advantageous. A variation shown in Figure 4 comprises a plurality of structures arranged in parallel having alternately an emitter zone, a base zone, two emitter zones, a base zone, etc. Another form having a lower inverse amplification consists in the alternation of an emitter zone and of a base zone. The invention is not limited to the embodiments described and shown. In particular, although it has been described for the case of npn transistors, it may also be used for pnp transistors.

Claims: CLAIMS : 1. A semiconductor device comprising a semiconductor body with an integrated circuit having a vertical transistor comprising a collector zone of a first conductivity type, a base region of a second conductivity type disposed on at least a part of the collector region and an emitter region comprising at least one zone of the first conductivity type included in a part of the base region adjoining a major surface of the semiconductor body, characterized in that the overall thickness of the base (2, 15) is smaller than or equal to the diffusion length of the minority charge carriers in this region, in that the base region (2) comprises at least one base contacting zone (15) having at least one contact area adjacent to the said zone of the emitter region, this base contacting zone being covered by an isolating layer (10) having a window (10 1 ), through which a contact (11) is provided to the contact area, the ratio between the surface area of the base contacting zone (15) and the surface area of the window (10') being at least equal to 10, and in that the base contacting zone (15) has a surface area smaller than 5 times the total surface area of the emitter region (12) . 2. An integrated circuit as claimed in Claim 1, characterized in that the base contact area comprises a contact area surrounded by a unique zone (12) constituting the emitter region. 3. An integrated circuit as claimed in Claim 1, characterized in that the emitter region (12) comprises at least two zones enclosing at least one surface of the said base contacting region (15) . 4. An integrated circuit as claimed in Claim 3, characterized in that the emitter region comprises at least two pairs of zones, the zones of each pair enclosing a different base contacting region (Figure 4) . 5. An integrated circuit as claimed in Claim l. characterized in that the base region has a plurality of branches (20 to 23) , each branch comprising a zone of the emitter region (12) , and in that the base contacting region (15) has a contact area provided in a central region with respect to the branches (20 to 23) .

Inventors: LEDUC PIERRE, LEDUC, PIERRE
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1989
Main classification: H01L29
IPC codes: H01L21, H01L27, H01L29