Matrix memory, comprising standard blocks, standard sub-blocks, a redundant block, and redundant sub blocks, and integrated circuit comprising a plurality of such matrix memories

Abstract: An integrated matrix memory is described which comprises standard sub-blocks and a redundant block. Each of the standard sub-­ blocks comprise a fixed number of standard sub-blocks. The redundant block comprises one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, delay is minimized.

Description: "Matrix memory, comprising standard blocks, standard sub-blocks, a redundant block, and redundant sub-blocks, and integrated circuit comprising a plurality of such matrix memories." The invention relates to an integrated matrix memory, comprising a series of p standard blocks, each of which comprises a uniform first number of i standard sub-blocks, each of which comprises a uniform second number of n storage columns, each sub-block in any block being connected, via a column selector, to a sub-bus which is exclusively assigned to each respective sub-block within the latter block, and which also serves for further sub-blocks of the same rank in other blocks, a bus selector being provided between respective sub-buses and an external data terminal. When the matrix memory is addressed, normally a single standard block is activated, the other blocks not being activated. As a result, only part of the memory dissipates energy and the remainder does not dissipate energy. Within the activated standard block only one standard sub-block is addressed and, moreover, provided with a row address. In each column one bit position is then addressed. The column selector selects only a sub-set of the columns in the sub-block for connection to the associated sub-bus; thus, all sub-buses together address one memory location whose capacity depends on the proportioning of the memory. Finally, there is provided a bus selector for selecting only a single sub-bus, and hence a single bit location. The foregoing holds good for a read operation as well as for a write operation. In the prior art document GB-A-2 195 480, a spare block can replace a faulty standard block, wherein upon detection of a faulty standard block address, an error address detecting means activates only the spare block. In Document US-A-4 599 709 a spare bit line can replace any faulty bit line on any bus, this being achieved firstly by a spare decoder and secondly by blowing the appropriate fusible links to disconnect a faulty bit line from the bus and connect the spare bit line to the corresponding bus line of the faulty bit line. It is inter alia an object of the invention to provide a memory of the kind set forth which can be repaired by way of redundancy in that there are provided redundant sub-blocks, offering a high degree of freedom as regards the mapping of a faulty sub-block on a substitute redundant sub-block, the selection between respective sub-blocks during a read operation taking place at the output side so that a comparatively large amount of time is available for the detection of an error address, the amount of redundancy being selectable by determination of the number of redundant sub-blocks. The latter number may in principle be arbitrary. The invention is as defined in claim 1. In accordance with the foregoing, the organization is such that during reading hardly any or no delay occurs because of the parallel operation between normal addressing and that of a reduandant sub-block. The procedure is also suitable for writing, because on the one hand a delay is usually built in for the data in view of the negative set-up time usually built in for that purpose, and on the other hand because the selection at the level of the standard sub-block/redundant sub-block can be made sufficiently quickly, and hence also the selection of said sub-bus. In view of the latter it is advantageous to provide a block decoder which is subdivided into a predecoder and a main decoder, said error address detector being fed by output signals of the predecoder and also by primary sub-bus selection signals in order to activate, upon detection of said error address, secondary sub-bus selection signals as substitutes for primary sub-bus selection signals prevailing at that instant. The error address is then detected in parallel with the indication of the intended sub-block by decoding. If the latter sub-block were to contain an error, a redundant sub-block would be activated as yet, but because of the parallellism the speed of operation is substantially independent of whether or not an error address is detected. The invention also relates to an integrated circuit comprising a second series of matrix memories, each matrix memory comprising a separately adjustable error address detector. The flexibility is thus enhanced. Further attractive aspects of the invention are recited in dependent Claims. The invention will be described in detail hereinafter with reference to some Figures. Therein Fig. 1 shows a block diagram of a memory in which the invention can be used, and Fig. 2 shows a more detailed block diagram of said memory. Fig. 1 shows a block diagram of a memory in which the invention can be used; however it does not show the facilities in accordance with the invention. The reference numeral 100 denotes the outline of a memory as realized in an integrated circuit. The memory 100 consists of four identical matrices 102 ... 108. The broken lines signify that the matrix 106 is shown in detail (at an enlarged scale). From this enlargement it appears that the matrix 106 consists of 16 blocks, only the block 110 of which is numbered. Further broken lines signify that the block 110 is shown in detail again at an enlarged scale. From this enlargement it appears that the block 110 consists of four sub-blocks, each of which consists of 8 columns of bit cells. Each column contains 128 bit cells. The total capacity of this memory thus amounts to 4 x 16 x 32 x 128 = 256 kbits. The invention, however, is not restricted to such a capacity. Fig. 1 does not show the facilities for accessing the memory the redundant storage capacity and the associated selection, mechanism. Fig. 2 is a more detailed block diagram of a part of the matrix memory of Fig. 1, the selection and redundancy also being shown. Only one of the matrices described above is indicated, for example only a part of the matrix 106. The intended storage capacity is achieved by way of a series of p standard blocks 20, 22. In the present example, p = 16, but only 2 blocks are shown. The storage capacity per standard block is achieved by way of a first number of i standard sub-blocks per standard block 26, 28 ... 40. In this case i = 4, but the number may also be smaller (for example 2) or larger (for example, 8). The storage capacity per standard sub-block is realized by way of a second number of n storage columns which extend from left to right in the Figure. In this case n = 8 (so 32 columns per standard block), but a larger or smaller number is also possible. There is also provided a single redundant block 24 which comprises j redundant sub-blocks. In this case j = 2, but another number is also possible. For i = 4, j may have all values 1, 2, 3, 4. For i = 2, j may have the values 1, 2 and so on for other values of i. The standard sub-blocks are composed in the same way as the redundant sub-blocks, i.e. they comprise the same numbers of rows and columns. Each of the standard sub-blocks and redundant sub-blocks also comprises a column selector 46 ... 64. Each column selector is connected to a sub-bus 66 ... 72. Within each standard block and within the redundant block all column selectors are connected to a unique sub-bus. The number of column selectors per sub-bus amounts to 2 or 3 in the present example; thus, the column selectors 52, 60 are assigned to the sub-bus 66, and the column selectors 46, 54, 62 are assigned to the sub-bus 72. Alternatively, for each sub-bus the same number of columns selectors may be provided. All sub-buses can be connected to external data terminal 76 via a bus selector 74. The matrix memory also comprises the following parts: an address input 78, a predecoder 80, an error address detector 84, a correction element 86, two predecoders 202, 204, a standard block address decoder 94, an activator 96 for the redundant block 24, and a further predecoder 210. The following sub-operations take place when the matrix is accessed. In the preferred embodiment the two most-significant address bits are used for selecting one of the four matrices. For the part of the memory which is shown in Fig. 2, the decoding result acts as the enable result; this is not elaborated. 16 address bits then remain. 7 of these 16 bits are necessary for selecting the row. These bits are applied in parallel to the row selection decoder 200 which selects one of the 128 rows. The path width of the bundle 212 (= 128), therefore is only shown symbolically. In the set-up shown in Fig. 1, four of the nine remaining address bits are necessary for selecting the relevant block. To this end, they are applied to the predecoders 202, 204 in groups of two, each predecoder converting the binary code into a one-out-of-four code. The two one-out-of-four codes are applied to the standard block main decoder 94. For example, for each of the 16 standard blocks this main decoder comprises an AND gate which receives a unique combination of the bits formed by the predecoders 202, 204, so that always at the most one standard block is activated. The two one-out-of-four codes are also applied to the error address detector 84 via a line 206. Furthermore, three address bits are required for selecting the column to be addressed in an addressed sub-block. These three address bits can be applied to the column selectors 46 ... 64 which in that case always receive the same input signals. Another (preferred) possibility consists in that these 3 bits are applied to a further predecoder 210 which forms a 1-out-of-8 code: the line 98 has a width of 8 bits and the column selectors act only as switches. Even though the set-up shown in fig. 2 would allow for a smaller number, in the foregoing use has been made of the numbers of bits which relate to the embodiment shown in Fig. 1. Assume that in the described case a bit must be selected from the standard block 20. Via the decoders last described and via control by mode signal (R/ WR ) and clock/enable signals (CL, CE), one respective column is addressed via each of the column selectors 46 ... 52. In a preferred embodiment the absence of the chip select signal acts as a disenable signal for the address buffers at the inputs of the respective address (pre)decoders. Furthermore, two bits are applied to input 78 for the selection of the standard sub-block in the block to be selected. These two bits are translated into a one-out-of-four code which is applied to the elements 86 and 84. The error address detector 84 receives the one-out-of-four code from the decoder 80 and the two one-out-of-four codes from the predecoders 202, 204. The error address detector 84 detects whether a given code received corresponds to a correct sub-block or to a faulty sub-block. A relevant circuit is described in the previous European Patent Application 87202286.8, corresponding United States Patent Application Serial No 265640. Such a detector can be set, for example by means of fuse elements, for programming the detector in series with an activation element which indicates whether the detector may anyhow be activated. When the address received (3 x 1-out-of-4) indicates a correct sub-block, on line 208 a signal appears which activates the decoder 94 and which deactivates the activator 96. On the line 90 a two-bit signal appears which renders the element 86 conductive for the one-out-of-four code formed by the decoder 80. The latter code sets the switch 74 to the position corresponding to the sub-bus 66, 68, 70, 72 to be activated, which bus thus communicates with the external terminal 76. In the described case the detector 84 comprises two separate, separately programmable elements: one each for the two redundant sub-blocks 42, 44. In the case of a different number of redundant sub-blocks, the number of detector elements is higher/lower accordingly. When a faulty sub-block is accessed, one of the two detector elements in the error detector 84 outputs a positive signal. The positive signals are combined on the line 208, for example in an OR function (not separately shown). For the activator 96 this signal acts as an activation signal; for the decoder 94 it acts as a deactivation signal. The element 96 does not perform a selection between redundant sub-blocks 42, 44 but acts only for activating these sub-blocks, be it together or not. Contrary to the previous situation, an activation signal then appears on the lines 90. This is, for example one bit which represents the activation and one bit which performs a selection between the sub-bus 70 (redundant sub-block 44) and the sub-bus 72 (redundant sub-block 42). According to another possibility, each of the two lines of the connection 90 activates one of the redundant sub-blocks. In the latter case both wires of the connection 90 are combined in an OR-function, the output of this OR gate disenabling all connections of the line 82. The respective lines of the connection 90 are again combined, in an OR-function, together with the control connection for the associated sub-bus. Given attractive aspects of the invention are apparent directly from the Figure. During a read operation the check as regards addressing of a "faulty" standard sub-block is executed in parallel with the selection of the sub-block itself. The locations within this standard sub-block and the locations within a redundant sub-block to be possibly addressed are also determined in parallel. As if it were at the "very last instant" the correction is then performed by way of signals on the lines 90 and 208 upon detection of a faulty standard sub-block. Thus, hardly any delay occurs when a redundant sub-block is to be addressed instead of a standard sub-block during a read operation. In view of the negative set-up time, for example upon a change-over from a read mode to a write mode, in the case of a write operation the data are usually already slightly delayed because of a unidirectional delay (not shown) which does not occur during reading. In that case it is not objectionable that the switch 74 could be switched over at the beginning of the data path to the sub-block to be addressed. Because the substitute redundancy is activatable on the basis of sub-blocks, a high degree of flexibility is achieved: if necessary, a plurality of sub-blocks which can be selected at random with respect to one another can be replaced. The memory described with reference to Fig. 2 may form part of a parallel connection in order to realize a wider data path. Another possibility in this respect consists in that, for example for each sub-block each time two columns can be selected; for example, 8 sub-buses are then arranged in parallel and two switches 74.

Claims: An integrated circuit memory, comprising a communication bus constituted by i parallel sub-buses (66, 68, 70, 72), a block address decoder (94), and p standard blocks (20, 22) that each comprise a uniform number of storage columns, each column being connected via a column selector (46-60) to a single one of said i sub-buses, so that each sub-bus (66, 68, 70, 72) serves a substantially uniform plurality of columns in a standard block, a bus selector (74) being provided between said i sub-buses and an external terminal (76) connecting one of the i sub-buses to the external terminal, a plurality of redundant columns being provided which are connected via said column selector to a single one of said i sub-buses and an error address detector (84) for detecting an address appertaining to a memory fault, an output of said error address detector (84) controlling a replacement means (86) for so connecting a redundant column instead of a storage column from said standard blocks to the relevant sub-bus, wherein in each of said p standard blocks said storage columns are grouped into i standard sub-blocks (26-40) of uniform size of n columns each, the n columns of each standard sub-block (26-40) being connected via said column selector to a unique one of the sub-buses (66-72) different from the one of the i sub-buses the n columns of the other standard sub-blocks in the same standard block are connected to, and said redundant columns are grouped into redundant sub-blocks (42, 44) of said uniform size as well, a redundant block (24) being so provided containing j redundant sub-blocks (42, 44), where j ≦ i, wherein the n columns of each redundant sub-block (42, 44) are connected via said column selector to a unique one of the i sub-buses different from the one of the i sub-buses the n columns of the other redundant sub-blocks in the same redundant block are connected to, said error address detector (84) being arranged to detect at least two different sub-block error addresses, each such error address pertaining to a respective faulty standard sub-block (26-40), and being arranged for each such faulty standard sub-block to provide a disactivation signal (208) for that faulty standard sub-block and to provide a unique address of a redundant sub-block as well as an associated selection signal (line 90) to said replacement means (86) indicating the relevant sub-bus (66, 68, 70, 72) connected to the relevant redundant sub-block (42, 44), wherein said replacement means controls bus selector to connect the relevant sub-bus to the external terminal. An integrated circuit memory as claimed in Claim 1, characterized in that there is provided a block decoder which is subdivided into a predecoder (202,204) and a main decoder (94), said error address detector being fed by output signals of the predecoder (202,204) and also by primary sub-bus selection signals (82) in order to activate, upon detection of said sub-block error addresses, secondary sub-bus selection signals (90) as substitutes for primary sub-bus selection signals prevailing at that instant. An integrated circuit memory as claimed in Claim 2, characterized in that said primary sub-bus section signals are supplied by a sub-bus selection decoder (80). An integrated circuit memory as claimed in Claim 1 or 2, characterized in that the number of redundant sub-blocks is smaller than the number of standard sub-blocks per standard block. An integrated circuit memory as claimed in Claim 1, 2 or 3, characterized in that the number of redundant sub-blocks is equal to the number of standard sub-blocks per standard block. An integrated circuit memory as claimed in any one of the Claims 1 to 5, characterized in that the column selector selects a single column from the associated standard or redundant sub-block. An integrated circuit memory, comprising a second series of integrated circuit memories as claimed in any one of the Claims 1 to 6, each one of second series of integrated circuit memories comprising a separately adjustable error address detector.

Inventors: DAVIES THOMAS JAMES, O'CONNELL CORMAC MICHAEL, ONTROP HANS, PFENNINGS LEONARDUS CHRITIEN M, PHELAN CATHAL GERARD, VOSS PETER HERMANN, DAVIES, THOMAS JAMES, O'CONNELL, CORMAC MICHAEL, ONTROP, HANS, PFENNINGS, LEONARDUS CHRITIEN MATHEUS GIELLAUMES, PHELAN, CATHAL GERARD, VOSS, PETER HERMANN
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1989
Main classification: G06F11
IPC codes: G11C29