Semiconductor integrated circuit

Abstract: A semiconductor integrated circuit equipped with an input buffer error operation preventing circuit is disclosed which comprises a data output signal level detector circuit (6) for detecting at least one of a variation from a low level from a high level and that from a high level to a low level of a signal of a cir­ cuit of a stage preceding an output buffer (4) and for generating a clock pulse and an input buffer signal ter­ minal control circuit (17) for controlling the terminal level of a firststage gate in a input buffer through the use of a clock pulse so as to cancel a fall in an input level detection margin of the input buffer which is caused when the output data of the output buffer varies from a "0" level to a "1" level and vice versa.

Description: The present invention relates to a semiconductor integrated circuit including an input buffer operation error preventing circuit, comprising: a data signal generator for generating a logic level data output signal having a first or second logic level; an output control circuit for receiving the logic level data signal from the data signal generator and for generating a data output signal; an output buffer, connected across first and second potential supply means, for receiving the data output signal from the output control circuit and for generating a logic level output buffer signal having a third or fourth logic level in accordance with the first or the second logic level of the data output signal; an input buffer, connected across the first potential supply means and the second potential supply means, for receiving an input signal of a predetermined level; and input buffer terminal control means responsive to a detection signal of a level transition detection means for controlling the input buffer. From document EP-A-0 181 177 a semiconductor memory device is known which is operatively connected to a power source (Vcc, Vss) and which includes a reference potential line operatively connected to receive a reference potential from the power source. An input circuit which is connected to the reference potential line and receives an external input signal having a logic level defined with respect to the reference potential to be supplied to the reference potential line, an output circuit having an external output terminal which may be connected to the reference potential line, for generating an output to the external output terminal and an inhibiting circuit for inhibiting a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes. A detection signal of a level transition detection means controls the input circuit by switching means selectively coupling one supply means to an output of the input circuit. If in a semiconductor integrated circuit for obtaining a high speed access time the drive power of a data output buffer is increased to allow a high speed rise and fall in an output data signal, then a noise signal is generated in a power supply line including a ground line due to a temporary large current through the output buffer. In this case, the output noise induces an input level detection error at, for example, a signal input buffer, causing a problem as will be set forth below. Figs. 1 and 2 show an output buffer and input buffer, respectively, and Fig. 3 shows the state of a typical error detection operation of the input buffer at the time when the output data of the output buffer varies. That ist, at a "0" level output time of the output buffer, a noise signal is induced on a Vss line (a ground line) due to a drive peak current of an N-channel transistor TN in the output buffer, resulting in a potential variation. At this time, if in the input buffer an input signal of the TTL (transistor-transistor logic) level is a high level and there is a small margin in the input signal level, an input buffer of a first stage temporarily assumes the same state as upon receipt of a TTL input signal of a low level, due to an influence of a noise signal of a "V SS potential" level, causing an output node A of a first stage in the input buffer to go high temporarily. On the other hand, if at a "1" output level of the output buffer a noise signal is induced on the V DD power supply by a drive peak current of a P-channel transistor TP at the output buffer. If, at this time, the TTL input signal is at a low level in the input buffer and there is a small margin in that input level, the input buffer of the first stage temporarily assumes the same state as upon receipt of a TTL input signal of a high level, due to an influence of a noise signal of a "V DD " potential level, causing the output node A of the first stage in the input buffer to go low temporarily. In order to prevent the aforementioned problem, that is, prevent an operation error of the input buffer resulting from the output noise upon a variation in the output data, the usual practice is to reduce the drive power of the output buffer and hence to reduce an amount of output noise generated or, in a memory of a multi-bit structure, to reduce an amount of output noise generated, by displacing each bit output a corresponding time little by little. These methods present a problem because they are used at the sacrifice of a data read-out speed. Another method is by, prior to an output varying at an output buffer, shorting input and output terminals of an output buffer of a final stage so that, with the output waveform made less sharp, an output noise component may be reduced. For this, reference is invited to Wada, T., et al., "A 34ns 1Mb CMOS SRAM using Triple Poly", ISSCC DIGEST OF TECHNICAL PAPERS, pp 262 to 263; Feb., 1987. According to this method, the input and output terminals of the output buffer are forced into conduction, offering a risk of inducing a large current therethrough or rather inducing a power supply potential variation. Furthermore, there is also a risk that the aforementioned conduction operation will be performed at the sacrifice of a data read-out speed. It is accordingly the object of the present invention to provide a semiconductor integrated circuit having an input buffer operation error preventing circuit, which, without the sacrifice of any data read-out speed, can prevent any input buffer's error detection operation caused upon an output noise occurred by a variation in output data which would otherwise be involved in a conventional semiconductor integrated circuit. According to the present invention, a semiconductor integrated circuit equipped with an input buffer error operation preventing circuit comprises a data signal level transition detector for detecting at least one of a variation from a low level to a high level and that from a high level to a low level of a signal of a circuit of a stage preceding an output buffer and for generating a clock pulse and an input buffer terminal control circuit for controllably adding a capacitor to an input terminal or output terminal of a firststage gate in an input buffer through the use of the clock pulse generated by the data output signal level transition detector circuit so as to cancel a fall in an input level detection margin of the input buffer which is caused when the output data of the output buffer varies from a "0" level to a "1" level and vice versa. According to the semiconductor integrated circuit having an input buffer's error operation preventing circuit, when an input level detection margin of the input buffer is to be decreased by a variation of the power supply potential caused by an output noise upon a variation in the output data of the output buffer, since the capacitor is added to the input or output terminal of the first stage gate of the input buffer, thereby preventing the logical level of the input signal from being erroneously detected. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 shows an output buffer and output control circuit for explaining an input signal level detection error at an input buffer upon a variation in the output data of an output buffer in a semiconductor integrated circuit; Fig. 2 is a circuit diagram showing an input buffer in the semiconductor integrated circuit of Fig. 1; Fig. 3 is a timing chart showing an input level detection error operation of a TTL input signal to an input buffer (Fig. 2) upon a variation in the output data of the output buffer in the semiconductor integrated circuit; Fig. 4 is a circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention which includes an input buffer operation error preventing circuit; Fig. 5A is a circuit diagram showing a second data signal level transition detector in the semiconductor integrated and Fig. 5B shows another second data signal level transition detector circuit in the semiconductor integrated circuit of Fig. 4; Fig. 6A shows a first data signal level transition detector in the semiconductor integrated circuit of Fig. 4 and Fig. 6B shows another variant of the second data signal level transition detector of Fig. 4; Fig. 7A shows a delay circuit as shown in Figs. 5A and 5B and 6A and 6B and Fig. 7B shows another variant of the delay circuit as shown in Figs. 5A, 5B, 6A and 6B; Fig. 8 is a timing chart of the semiconductor integrated circuit having an input buffer operation error preventing circuit of Fig. 4; Fig. 9 shows a semiconductor integrated circuit according to another embodiment of the present invention, including an input buffer operation error preventing circuit; Fig. 10 is a timing chart showing an operation of the semiconductor integrated circuit of Fig. 9; Fig. 11 is a circuit showing a semiconductor integrated circuit according to another embodiment of the present invention, including an input buffer operation error preventing circuit; Fig. 12 is a timing chart showing an operation of the semiconductor integrated circuit of Fig. 11; and Fig. 13 is a circuit showing a semiconductor device according to another embodiment of the present invention, including an input buffer operation error preventing circuit. The semiconductor integrated circuit according to the embodiments of the present invention will be explained below with reference to the accompanying drawings. In the semiconductor memory integrated circuit shown in Fig. 4, reference numeral 1 shows an address input pad; 2, an input buffer; 3, an output control circuit, 4, an output buffer; 5, a data output pad and 6, an operation error presenting circuit, noting that DG shows a data signal generator and that V DD and V SS represent a power supply potential and reference potential (ground potential), respectively. The input buffer 2 comprises CMOS type two-input NOR gates with one input supplied with a TTL level input signal coming from an external source via an input pad 1 and with the other input supplied with a chip-enable "0" level input control signal. The output control circuit 3 comprises a NAND gate 7 and NOR gate 8 supplied at one terminal with data output signal Dout coming from the data signal generator DG, series circuit of CMOS inverters 9 and 10 connected to the output of the NAND gate 7, series circuit of CMOS inverters 11 and 12 connected to the output of the NOR gate 8, and CMOS inverter 13 for supplying a "0" level output control signal at a read time and "1" level output control signal at a write time to the other input to the NAND gate 7 in an inverted fashion, the output control signal being supplied to the other terminal of the NOR gate 8. A series circuit of a p channel transistor T p and N channel transistor TN is connected between the power supply line V DD and the ground terminal V SS , and common junction of the drains of the transistors TP and TN is connected to a data output pad 5. An operation error preventing circuit 6 comprises first data signal level transition detector F and second data signal level transition detector R for detecting signal level transition on output nodes B and C of a preceding circuit (for example, the NAND gate 7 and NOR gate 8 in the output control circuit 3) of the output buffer 4, delay circuit DL1 connected in series to the output of the first detector F, series circuit of a delay circuit DL2 and CMOS inverter IV connected to the output of the second detector R. An input buffer signal terminal control circuit 17 comprises a series circuit of a capacitor CP1 and a P channel transistor P1 connected across the power supply terminal V DD and the output terminal A of the input buffer 2 and series circuit of an N channel transistor N1 and a capacitor CN1 connected across an output terminal A and ground terminal V SS . An output  p of the delay circuit DL1 and output  N of the inverter IV are supplied to the gates of the P channel transistor P1 and N channel transistor N1 in the control circuit 17 respectively. The detector R detects the time of a transition in the data output signal of the data signal generator DG, that is, a time immediately preceding a variation of the N channel transistor TN from OFF to ON (immediately preceding a variation of the ground potential V SS ) and generates a "0" level clock pulse  Rout . The second data output signal level detector R is of such a type as shown, for example, in Fig. 5A or 5B. That is, in the circuit shown in Fig. 5A, a data output signal from the second detector R is supplied to one input of a NOR gate 22 via a delay circuit 21 and to the other input of the NOR gate 22 via an inverter 23 and output of the NOR gate 22 is inverted by an inverter 24 to generate a clock pulse  ROUT . In the circuit shown in Fig. 5B, an input signal is supplied to one input of a NAND gate 27 via a series circuit of an inverter 25 and delay circuit 26 and directly to the other input of the NAND gate 27, and the output of the NAND gate 27 is output as a clock pulse  ROUT . The first data signal level transition detector F detects the time of a transition in the data output signal of the data signal generator DG, that is, a time immediately preceding a variation of a p channel transistor TP of the output buffer 4 from OFF to ON in this case (immediately preceding a variation of the power supply potential V DD ) and generates a "0" level clock pulse  FOUT . The circuit F is of such a type as shown, for example, in Fig. 6A or 6B. That is, the circuit of Fig. 6A is the same as that of Fig. 5B except that a series circuit of a NOR gate 31 and inverter 32 is connected in place of the aforementioned NAND gate 27. The circuit of Fig. 6B is the same as that of Fig. 5A except that a NAND gate 33 is used in place of the aforementioned series circuit of the NOR gate 22 and inverter 24. The delay circuits 21 and 26 as shown in Figs. 5A, 5B, 6A and 6B comprise an even number of series-connected inverters IV1, ..., IVn and capacitors C1, ..., Cn with each output connected relative to the ground terminal, as shown in Fig. 7A or 7B, as required. The delay circuits DL1 and DL2 are of such a type as shown, for example, in Fig. 7A and 7B. The delay circuits DL1 and DL2 delay the aforementioned clock pulses  FOUT and  ROUT by a predetermined time and adjusts the switching operation timing of the P channel transistor P1 and N channel transistor N1. The series circuit of the capacitor CP1 and P channel transistor P1 and N channel transistor N1 and capacitor CN1 controllably add the capacitor CN1 or the capacitor CP1 to the output terminal A of the input buffer 2 in a direction toward cancelling a fall in the input level detection margin of the input buffer 2 which is caused by an output noise (power supply potential variation) upon a variation in the output data of the output buffer 4 from "0" to "1" and from "1" to "0". The output signal of the input buffer 2 is input to an address decoder via an inverter 14. Referring to the voltage waveform of Fig. 8, an explanation of the semiconductor integrated circuit will be set forth below in connection with the input buffer operation error preventing operation involved upon variation in the data output of the output buffer. That is, upon a "0" read operation of the output buffer 4, for example, the node C of the output control circuit 3 varies from a low level to a high level and hence the second data signal level transition detector R generates a "0" level clock pulse  ROUT . The clock pulse  ROUT has its timing adjusted past the delay circuit DL2 and inverter IV, generating a "1" level clock pulse  N . The clock pulse  N is supplied to the gate of the N channel transistor N1. If, at this time, the TTL level input signal of the input buffer 2 is at a low level, no problem arises. If, on the other hand, the TTL level input signal is at a high level VIH and there is less detection margin, there is a risk that a detection error operation will occur. At this time, the N channel transistor N1 is temporarily turned ON by a clock pulse  N and, due to the capacitor CN1 added between the output terminal A of the input buffer 2 and the ground terminal, a potential on the output terminal A is lowered to the ground potential side, an operation which tends to cause the output terminal A to vary to a high level side is made less active, failing to cause a potential on the output terminal A of the input buffer 2 to go high temporarily. It is thus possible to improve a detection margin against a high level VIH of the TTL level input signal. If, on the other hand, a "1" data is read out of the output buffer 4, a potential on the node B of the output control circuit 3 varies from the high level to the low level and hence a "0" level clock pulse  FOUT is produced from the first data signal level transition detector F. The clock pulse  FOUT has its timing adjusted past the delay circuit DL1 to generate a clock pulse  P . The clock pulse  P is supplied to the gate of the P channel transistor P1. If, at this time, the TTL level input signal of the input buffer 2 is at a high level, no problem is encountered because there is an adequate detection margin. If, however, a TTL level input signal is at a low level VIL and there is less detection margin, there is a risk that the aforementioned detection error will occur. In this embodiment, the P channel transistor P1 is rendered ON temporarily and, due to a capacitance CP1 between the output terminal A of the input buffer 2 and the power supply terminal, the potential level on the output terminal A is raised, causing an operation which tends to cause the output terminal A to vary to a low level side. As a result, the situation under which the potential on the output terminal A of the input buffer 2 goes low temporarily is avoided, increasing a detection margin against the low level VIL of the TTL level input signal. The present invention is not restricted to the aforementioned embodiment. For example, the p channel transistor P1 and capacitor CP1, as well as the N channel transistor N1 and capacitor CN1, may be rearranged in a proper fashion. As shown in Fig. 9, in place of an output terminal A of an input buffer 2, a capacitor CP2 a P channel transistor P2 are connected between an input terminal D of an input buffer 2 and a power supply terminal V DD and a capacitor CN2 and an N channel transistor N2 are connected between the input terminal D and a power supply terminal V SS , a clock pulse  P being supplied to the gate of the P channel transistor P2 and clock pulse  N being supplied to the gate of the N channel transistor N2. The operation error preventing operation is performed in a manner similar to that as set forth above, the waveform of it being shown in Fig. 10. If the N channel transistor N2 is turned ON with the presence of the capacitor CN2, an input signal level on the input terminal D is raised together with a level on the power supply terminal V SS and hence a VIH detection margin is improved. If the P channel transistor P2 is turned ON with the presence of the capacitor CP2, an input signal level on the input terminal D is lowered together with a level on the power supply terminal V DD , increasing a VIL detection margin. An embodiment of Fig. 11, a combination of the embodiments shown in Figs. 4 and 9, is of such a type that, as shown in Fig. 11, transistors P1, N an capacitors CP1, CN1 are provided on the output terminal A side of an input buffer 2 and transistor P2, N2 and capacitors CP2, CN2 are provided on the input terminal D side of the input buffer 2. This embodiment can obtain the same advantage as those of the aforementioned embodiments, noting that the waveform of respective parts are shown in Fig. 12. Fig. 13 shows another embodiment of the present invention. In this embodiment, a transistor 22 is connected across a junction between a capacitor CP1 and a transistor P1 and a power supply terminal V DD and a signal  P is coupled from a delay circuit DL1 via an inverter 20 to the gate of the transistor 22, and an N channel transistor 23 is connected across a junction between a capacitor CN1 and a transistor N1 and a ground potential V SS and a signal  N coupled from an inverter IV to the gate of a transistor 23 via an inverter 21. A signal variation detection node of an output control circuit 3 may be located at any proper places in place of points B and C. For example, a rise variation on the output node of an inverter 9 and fall variation on an inverter 11 may be detected. In the respective embodiments, the rise variation and fall variation of the output data are detected, thereby preventing a fall on the detection margin of the corresponding input signal. As the case may be, however, the capacitor CP1 and/or CP2 or capacitors CN1 and/or CN2 may be added only on the power supply terminal side or the ground terminal side. In this case, only the rise variation of the output data or only the fall variation may be detected, thereby preventing a fall in the detection margin of the input signal. Furthermore, the semiconductor integrated circuit including an input buffer operation error preventing circuit can generally be applied to a semiconductor integrated circuit including input and output buffers.

Claims: A semiconductor integrated circuit including an input buffer operation error preventing circuit, comprising: a data signal generator (DG) for generating a logic level data signal having a first or a second logic level an output control circuit (3) for receiving the logic level data signal from the data signal generator and for generating a data output signal; an output buffer (4), connected across first and second potential supply means (V DD ) and (V SS ), for receiving the data output signal from the output control circuit and for generating a logic level output buffer signal having a third or a fourth logic level in accordance with the first or the second logic level of the data output signal; an input buffer (2), connected across the first potential supply means (V DD ) and the second potential supply means (V SS ), for receiving an input signal of a predetermined level; and input buffer terminal control means (17) responsive to a detection signal of a level transition detection means for controlling the input buffer (2), characterized in that said level transition detection means consists of a data output signal level transition detector means (6), located at a predetermined place on a current path of the data output signal in the output control circuit (3), for detecting at least one of a transition of the data output signal from the first logic level to the second logic level and that of the data output signal from the second logic level to the first logic level and for generating a first or a second detection signal; and in that said input buffer terminal control means (17), responsive to the first or the second detection signal, comprises switchable capacitors (CP1, CN1, CP2, CN2) selectively coupling the first or second supply means (V DD , V SS ) to the input and/or the output of the input buffer (2). The semiconductor integrated circuit according to claim 1, characterized in that said data output signal level transition detector means (6) detects a transition of said data output signal from a first logic level to a second logic level or from the second logic level to the first logic level prior to a transition of said output buffer (4) from a third logic level to a fourth logic level or from the fourth level to the third logic level and generates said first or second detection signal. The semiconductor integrated circuit according to claim 2, characterized in that said data output signal level transition detector means (6) comprises a first data signal level transition detector (F) for detecting a transition of said data output signal from a first logic level to a second logic level and for generating said first detection signal, first delay circuit (DL1), a second data signal level transition detector (R) for detecting a transistion of said data output signal from the second logic level to the first logic level and for generating a second detection signal, second delay circuit (DL2) and first inverter (IV). The semiconductor integrated circuit according to claim 3, characterized in that said first data signal level transition detector (F) comprises a first NOR gate (31) for receiving said data output signal at one input terminal and said data output signal at the other input signal via a second inverter (25) and a third delay circuit (26); and a third inverter (32) connected to an output terminal of the first NOR gate (31). The semiconductor integrated circuit according to claim 3, characterized in that said first data signal level transition detector (F) comprises a first NAND gate (33) for receiving said data output signal at one input terminal via a fourth inverter (23) and said data output signal at the other input terminal via a fourth delay circuit (21). The semiconductor integrated circuit according to claim 3, characterized in that said second data signal level transition detector (R) comprises a second NOR gate (22) for receiving said data output signal at one input terminal via fifth inverter (23), said data output signal at the other input terminal via a fifth delay circuit (21) and a sixth inverter (24) connected to an output terminal of the second NOR gate (22). The semiconductor integrated circuit according to claim 3, characterized in that said second data signal level transition detector (R) comprises a second NAND gate (27) for receiving said data output signal at one input terminal and said data output signal at the other input terminal via a seventh inverter (25) and sixth delay circuit (26). The semiconductor integrated circuit according to one of claims 4 to 7, characterized in that said third to sixth delay circuit comprises a plurality of series-connected inverters (lV1,...,lVn). The semiconductor integrated circuit according to claim 1, characterized in that said input buffer terminal control means comprises a first transistor (P1) of a first channel type, first capacitor (CP1), second transistor (N1) of a second channel type and second capacitor (CN1) which are connected across said first potential supply means (V DD ) and said second potential supply means (V SS ), and said first and second transistors (P1) and (N1) are controlled by said first and second detection signals respectively so that, during a period of time in which the first and second detection signals are output at a time of a transition of the data output signal from a first logic level to a second logic level or from the second logic level to the first logic level, an output terminal voltage of said input buffer (2) is varied. The semiconductor integrated circuit according to claim 9, characterized in that a current path is provided between said first transistor (P1) and said second transistor (N1) and connected to an output terminal of said input buffer (2). The semiconductor integrated circuit according to claim 1, characterized in that said input buffer terminal control means (17) comprises a third transistor (P2) of a first channel type, a third capacitor (CP2), a fourth transistor (N2) of a second channel type and a fourth capacitor (CN2) which are connected across said first potential supply means (V DD ) and said second potential supply means (V SS ), and said third and fourth transistors (P2) and (N2) are controlled by said first arid second detection signals (ØP, ØN), respectively so that, during a period of time in which the first and second detection signals (ØP, ØN) are output at a time of a transition of the data output signal from a first logic level to a second logic level or from the second logic level to the first logic level, an output terminal voltage of said input buffer (2) is varied, wherein a current path is provided at each of said third transistor (P2) and said fourth transistor (N2) and connected to an input terminal (D) of said input buffer (2). The semiconductor integrated circuit according to claim 1, characterized in that said input buffer terminal control means comprises: a first input buffer terminal control circuit (17a), connected across said first potential supply means (V DD ) and said second potential supply means (V SS ), for controlling a voltage on an output terminal of said input buffer; and a second input buffer terminal control circuit (17b) connected across said first potential supply means (V DD ) and said second potential supply means (V SS ), for controlling a voltage on an input terminal of said input buffer (2). The semiconductor integrated circuit according to claim 12, characterized in that said first input buffer terminal control circuit (17a) comprises a series circuit of a first capacitor (CP1) and a first transistor (P1) of a first channel type and a second transistor (N1) of a second channel type and second capacitor (CN1), and a current path is provided between said first and second transistor and connected to an output terminal of said input buffer (2). The semiconductor integrated circuit according to claim 12, characterized in that said second input buffer terminal control circuit (17b) comprises a series circuit of a third capacitor (CP2) and a third transistor (P2) of a first channel type and a fourth transistor (N2) of a second channel type and fourth capacitor (CN2), a current path between the third transistor (P2) and the fourth transistor (N2) being connected to an input terminal of said input buffer (2). The semiconductor integrated circuit according to claim 1, characterized in that said first and second detection signals are clock pulses.

Inventors: OOTANI TAKAYUKI C O PATENT DIV, OOTANI, TAKAYUKI C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H03K19
IPC codes: H03K17, H03K19