PUSH-PULL OUTPUT CIRCUIT WHICH IS FREE FROM HOT CARRIER STRESS

Abstract: A push-pull output circuit which is powered by a 5-V supply voltage and in which the push part comprises a PMOS transistor (P1) and the pull part comprises a PMOS transistor (P2) and an NMOS transistor (N1), the NMOS transistor (N1) being driven via a detection circuit (P3, P4, N2, N3) so that no hot carrier stress occurs in the NMOS transistor.

Description: The invention relates to a Push-pull output circuit which is free from hot carrier stress, and in particular to a push-pull output circuit in which current channels of a first and a second output transistor are connected between a first power supply terminal and an output terminal and between the output terminal and a second power supply terminal, respectively, the first output transistor being a p-type transistor, a first and a second input terminal being coupled to a control electrode of the first and the second output transistor, respectively, which input terminals receive a logic input signal and the inverse thereof, respectively. A circuit of the kind set forth is known from European Patent Specification 0 174 266, which describes a push-pull output circuit in which the output transistors are of a mutually different conductivity type. In the case of a voltage difference which exceeds a value U STRESS across the main electrodes of an n-type transistor, a substantial risk of so-called hot carrier stress arises because of the resultant field strength near the first main electrode. As the lengths of the current channels decrease, the value U STRESS , being the maximum voltage to prevent hot carrier stress in n-type transistors, also decreases. The value U STRESS depends not only on the length of the current channel but also on the steepness of the dope profiles of the implanted regions forming the input and output regions of a transistor, steeper dope profiles implying a reduction of the value U STRESS . In integrated circuits in which channel lengths of transistors amount to approximately 1 µm or less than 1 µm (sub-micron), the dope profiles of the input and output regions of transistors are steep in order to enable still the realization of current channels between the input and output regions. In an integrated circuit in which mainly submicron transistors are implemented preferably the same process technology is used for the realization of transistors having channel lengths greater than 1 µm, so that additional process steps or separate masks which usually have a cost-increasing effect can be dispensed with. For transistors having channel lengths in excess of 1µm this means that the input and output regions also have steep dope profiles, implying a small value U STRESS . The circuit described in the cited Patent Specification has the drawback that hot carrier stress can occur in n-type transistors in the case of channel lengths which are approximately equal to or smaller than 1 µm, but also in n-type transistors produced in a submicron process without additional steps or operations with channel lengths in excess of 1 µm when a standard supply voltage of, for example 5 V is used. Decreasing the supply voltage of the said circuit to, for example 3.3 V would preclude hot carrier stress, but would also lead to a switching speed of the output circuit which is lower than desirable. Hot-carrier phenomena in submieron VLSIs, particularly in large scale DRAMs are described more detail in an article by E. Takeda entitled "Hot-carrier and wear-out phenomena in submicron VLSI's", published in "Proceedings of the VLSI symposium, Kobe, 1985, pages 2-5. It is an object of the invention to provide an output circuit in which the risk of hot carrier stress is minimum, despite the use of short channel lengths (approximately 1 µm) in the output transistors, even when the circuit operates with a customary standard power supply voltage (for example 5 V). It is a further object of the invention to enable the output circuit to drive transistor-transistor logic (TTL) as well as complementary-MOS (CMOS) logic. To achieve this, a push-pull output circuit in accordance with the invention is characterized in that the second output transistor is also a p-type transistor and in that parallel to the current channel of the second output transistor there is connected a current channel of a third output transistor of the n-type, to the output terminal there being connected detection means for turning on the third output transistor when the voltage on the output terminal drops below a predetermined voltage level. A push-pull output circuit in accordance with the invention offers the advantage that said hot carrier stress does not occur, because the maximum permissible voltage U STRESS is not exceeded; this is because p-type transistors are not as susceptible to hot carrier stress as n-type transitors since the mobility of holes in p-type transistors is less than that of electrons in n-type transistors and, moreover, said circuit has a higher switching speed than circuits powered by a supply voltage which is lower than usual, for example 3.3 V. The n-type output transistor is not conductive when a voltage difference across the main electrodes is larger than the value U STRESS ; it is only in the case of a voltage difference which is smaller than the value U STRESS that the n-type transistor is turned on or not, depending on the input signals. An embodiment of a push-pull output circuit in accordance with the invention is characterized in that the detection means comprise a p-type detection transistor, whose first main electrode is connected to the first pwer supply terminal, its control electrode being connected to the output terminal and its second main electrode being connected to the control electrode of the third transistor. Said detection transistor detects the voltage on the output terminal and turns on the third transistor as soon as the voltage on the output terminal has decreased to the voltage on the first power supply terminal minus the threshold voltage of the detection transistor, at which voltage the third transistor no longer experiences hot carrier stress. When the third transistor still experiences hot carrier stress when the voltage on the output terminal is equal to the voltage on the first power supply terminal minus the threshold voltage of the detection transistor, for example because of a high supply voltage or because of a transistor with an associated low value U STRESS , one or more transistors can be connected as a diode between the first main electrode of the detection transistor and the first power supply terminal, so that the third transistor is turned on only after the voltage on the output terminal has decreased to the voltage on the first power supply terminal minus the threshold voltage of the detection transistor minus the threshold voltage (threshold voltages) of the transistor (transistors) connected as a diode. Another embodiment of a push-pull output circuit in accordance with the invention is characterized in that between the first main electrode of the detection transistor and the first power supply terminal there is connected the current channel of a fourth transistor of the p-type whose control electrode is coupled to the first input terminal, between the second main electrode of the detection transistor and the second power supply terminal there being connected the current channel of a fifth transistor of the n-type whose control electrode is coupled to the first input terminal. During a signal transition on the first and the second input terminal from logic low to logic high and from logic high to logic low, respectively, said fourth and fifth transistor quickly turn off the third transistor in order to ensure that during the signal transition on the first and the second input terminal no short circuit current can flow from the first to the second power supply terminal via the first and the third transistor. Embodiments in accordance with the invention will be described in detail hereinafter, by way of example, with reference to the drawing; therein: Figure 1 shows an embodiment of a push-pull output circuit in accordance with the invention, and Figure 2 shows a preferred embodiment of a push-pull output circuit in accordance with the invention. Figure 1 shows an embodiment of a push-pull output circuit in accordance with the invention, comprising a first and a second PMOS transistor P1 and P2, respectively, a third NMOS transistor N1, and a subcircuit D. The drain and the source, respectively, of the transistors P1 and P2, respectively, connected to an output terminal OUT, to the drain of the transistor N1 and also to a first connection terminal of the subcircuit D. The drain and the source, respectively, of the transistor P2 and the transistor N1, respectively, are connected to the second power supply terminal U2 and to a second connection terminal of the subcircuit D. The source of the transistor P1 is connected to the first supply terminal U1 and to a third connection terminal of the subcircuit D. The fourth and the fifth connection terminal of the subcircuit D are coupled to the gate of the third transistor N1 and to a first input terminal IN, respectively. The control electrode of the transistor P1 and the transistor P2 is coupled to the second input terminal IN and the first input terminal IN, respectively. A capacitive load C LOAD can be connected between the output terminal OUT and the second supply terminal U2. The circuit shown in Figure 1 operates as follows: the subcircuit D comprises detection means for the detection of the voltage level on the output terminal OUT and for turning on the transistor N1 when the voltage on the output terminal OUT drops below a predetermined voltage level U STRESS . In the case of a logic high input signal IN, the transistor P1 will be turned on and the transistors P2 and N1 will be turned off. Because of the charging of the capacitive load C LOAD , the voltage on the output terminal OUT becomes logic high. In the case of a logic low input signal IN, the transistor P1 will be turned off and the transistor P2 will be turned on. The transistor N1 remains turned off for the time being. The voltage on the output terminal OUT will decrease due to the turned-on state of the transistor P2. Because of its turned-off state, the transistor N1 will not experience hot carrier stress. After the voltage on the output terminal OUT has decreased to a value below U STRESS , below which value the transistor N1 will no longer experience hot carrier stress in its turned-on state, the transistor N1 will be turned on via the subcircuit D, so that the output load capacitance C LOAD is discharged via the transistors P2 and N1. Below a voltage on the output terminal OUT which amounts to the sum of the threshold voltage V THP2 and the voltage on the input terminal IN, where V THP2 is the threshold voltage of the transistor P2, the transistor P2 will be turned off. The transistor N1, however, remains turned on so that the capacitive load C LOAD is fully discharged. Figure 2 shows a preferred embodiment of a push-pull output circuit in accordance with the invention which corresponds to that shown in Figure 1, so that corresponding reference symbols are used to denote corresponding parts. The subcircuit D is now composed of two NMOS transistors N2 and N3 and two PMOS transistors P3 and P4. The source of the transistor P3 is connected to the first power supply terminal U1 and to the control electrode of the transistor N2. The source and the drain of the transistor P4 are coupled to the drain of the transistor P3 and the drain of the transistor N2, respectively. The source of the transistor N2 is connected to the drain of the transistor N3 and the source of the transistor N3 is coupled to the second supply supply terminal U2. The control electrodes of the transistors P3 and N3 are connected to the first input terminal IN, the control electrode of the transistor N1 being connected to the drains of the transistors P4 and N2. The control electrode of the transistor P4 is connected to the output terminal OUT. The operation of the circuit shown in Figure 2 is as follows: in the case of a logic high input signal on the first input terminal IN, the transistor N3 will be turned on and the transistors P2 and P3 will be turned off; because of a logic low input signal IN on the control electrode of the transistor P1, the transistor P1 will be turned off. The transistor N2 will be turned on, so that the control electrode of the transistor N1 receives a low voltage and hence the transistor N1 is turned off. The output load capacitance C LOAD is charged via the transistor P1. When the signal on the first and the second input terminal changes from logic high to logic low and from logic low to logic high, respectively, the transistor P1 will be turned off and the transistor P2 will be turned on. The transistor P4 is turned off because the voltage difference between the control electrode and the source of the transistor P4 is smaller than the threshold voltage V THP4 of the transistor P4, so that the transistor N1 also remains turned off. The voltage on the output load capacitance C LOAD will decrease due to the turned-on state of the transistor P2. When the latter voltage decreases to U1-V THP4 , where V THP4 is the threshold voltage of the transistor P4, the transistor P4 will be turned on, so that the control electrode of the transitor N1 receives a high signal and the transistor N1 is turned on. Consequently, the output voltage V OUT will decrease faster. As soon as the voltage on the output terminal OUT has decreased to a value V IN +V THP2 , where V THP2 is the threshold voltage of the transistor P2, the transitor P2 will be turned off. The transistor N1, however, will remain turned on, so that the output load capacitance C LOAD is fully discharged. The transistor N2 serves to protect the transistor N3 in order to ensure that the voltage on the drain of the transistor N3 cannot exceed the voltage on the first supply terminal U1 minus the threshold voltage V THN2 of the transistor N2, so that no hot carrier tress occurs in the transistor N3. It is to be noted that PMOS transistors are less susceptible to hot carrier stress than NMOS transistors, because of the fact that the mobility of holes in PMOS transistors is less than that of electrons in NMOS transitors. To those skilled in the art it will be apparent that the subcircuit D can also be composed by means of other components, for example a subcircuit as shown in Figure 2 in which, however, the transistors N2 and N3 are replaced by a resistor. However, on the one hand a desirable low stationary power dissipation then implies a higher resistance, while on the other hand in view of a desirable short RC discharging time a low resistance value is required for a fast discharge of the control electrode-source capacitance of the transistor N1 when the signal on the first input terminal changes from logic high to logic low. A push-pull output circuit in accordance with the invention is suitable for driving TTL as well as CMOS logic when suitable values are chosen for the dimensions of the transistors P1, P2 and N2. For TTL drives (where the load resistance to the first supply terminal is approximately twice the load resistance to the second supply terminal) the output circuit should deliver a logic high level and a logic low level of at least 2.4 V and at the most 0.4 V, respectively. In the case of a 5-V supply voltage a suitable choice of the width/length ratios W/L of an output circuit comprising MOS transistors is 200/1.2, 300/1.2 and 400/1.1 for the transistors P1, P2 and N2, respectively. Push-pull output circuits according to the invention are advantageously comprised in integrated memory circuits.

Claims: 1. A push-pull output circuit in which current channels of a first and a second output transistor are connected between a first power supply terminal and an output terminal and between the output terminal and a second power supply terminal, respectively, the first output transistor being a p-type transistor, a first and a second input terminal wbeing coupled to a control electrode of the first and the second output transistor, respectively, which input terminals receive a logic input signal and the inverse thereof, respectively, characterized in that the second output transistor is also a p-type transistor and in that parallel to the current channel of the second output transistor there is connected a current channel of a third output transistor of the n-type to the output terminal there being connected detection means for turning on the third output transistor when the voltage on the output terminal drops below a predetermined voltage level. 2. A push-pull output circuit as claimed in Claim 1, characterized in that the detection means comprise a p-type detection transistor whose first main electrode is connected to the first power supply terminal, its control electrode being connected to the output terminal, and its second main electrode being connected to the control electrode of the third transistor. 3. A push-pull output circuit as claimed in Claim 2, characterized in that between the first main electrode of the detection transistor and the first power supply terminal there is connected the current channel of a fourth transistor of the p-type whose control electrode is coupled to the first input terminal, between the second main electrode of the detection transistor and the second power supply terminal there being connected the current channel of a fifth transistor of the n-type whose control electrode is coupled to the first input terminal. 4. A push-pull output circuit as claimed in Claim 3, characterized in that between the second main electrode of the detection transistor and the first main electrode of the fifth transistor there is connected the current channel of a sixth transistor of the n-type whose control electrode is coupled to the first power supply terminal. 5. A push-pull output circuit as claimed in any one of the Claims 1, 2, 3 or 4, characterized in that an n-type transistor is an n-channel field effect transistor, a p-type transistor being a p-channel field effect transistor. 6. A push-pull output circuit as claimed in any one of the Claims 1, 2, 3, 4 or 5, characterized in that it is part of an intergrated memory circuit.

Inventors: DAVIES, THOMAS JAMES, O'CONNELL, CORMAC MICHAEL, ONTROP, HANS, PFENNINGS, LEONARDUS CHRITIEN MATHEUS GIELLAUMES, PHELAN, CATHAL GERARD, SEEVINCK, EVERT, VOSS, PETER HERMAN
Applicants: N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1989
Main classification: H03K19
IPC codes: H03K19, H03K17