Electrically erasable and programmable read only memory

Abstract: An electrically erasable and programmable read only memory includes a memory cell array (100) including a plurality of memory cells (1₁-1 n , 2₁-2 n ) coupled to bit lines (BL1-BLn) and word lines (WL1-WL3). Each of the memory cells includes a select transistor (15-18), a memory transistor (11-14) having a control gate (5), and a drive transistor (31-33) of the enhancement type applying a control gate voltage (V CG , PL) to the control gate of the memory transistor. The read only memory further includes select means (41, 42, 46) for selecting at least one of the bit lines and one of the word lines. When the select means selects one (WL1) of the word lines at the time of reading out data stored in the memory cells (1₁-1 n ) coupled to the selected word line, the drive transistor (31) relating to the selected word line is turned ON so that the control gate voltage (V CG , PL) is applied to the control gates of the memory transistors through the turned-ON drive transistor and thereby drives the corresponding memory transistors.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to a semiconductor memory and, more particularly, to an electrically erasable and programmable read only memory (EEPROM) having an insulating film through which a charge is transferred so that the content of a memory cell is electrically rewritten. Recently, two different types of EEPROM have been proposed, one of which has a configuration which utilizes a trap formed at an interface between insulating films of different types, and the other type has a configuration which utilizes a floating gate. The two types of EEPROM utilize the tunnel effect in data write and erase. Thus, current generated at the time of data write or erase is extremely small. As a result of small current, a variety of EEPROMs have been developed. For example, an EEPROM has a mode in which data relating to all bits can be erased at the same time, or alternatively has a mode in which data can be written or erased per page unit. Generally, an erasable and programmable ROM (EPROM) is mounted on a printed circuit board after writing data therein. On the other hand, an EEPROM is subjected to data rewrite in a state where it is mounted on a printed circuit board. For this reason, an endurance (the possible number of times that data is repeatedly rewritten) is an important factor. A conventional EEPROM is illustrated in FIGS.1A, 1B, 1C and 2. Referring to FIG.1A, there is illustrated a structure of a memory transistor of EEPROM. The illustrated EEPROM 1 includes a semiconductor substrate 2, in which a source region 3 and a drain region 4 are formed. A control gate 5 is formed of polysilicon and is electrically insulated from the substrate 2. A floating gate 6 is formed between the control gate 5 and the drain region 4. A thin oxidation film (tunnel oxidation film) 7 having a thickness of about 100 angstroms is formed between the drain region 4 and the floating gate 6. Referring to FIG.2, memory transistors 11 - 14 each have the transistor structure shown in FIG.1A. The memory transistors 11 and 13 are connected to a bit line BL1, and the memory transistors 12 and 14 are connected to a bit line BLn. Select transistors 15 - 20 select the memory transistors 11 - 14, respectively. Drive transistors 21 - 23 apply a predetermined voltage to the gates (control gates) of the corresponding memory transistors to thereby drive them. The drive transistor 21 drives the control gates of the memory transistors 11 and 12, and the drive transistor 22 drives the control gates of the memory transistors 13 and 14. It is noted that the drive transistors 21 - 23 are formed of the depletion type in order to suppress a voltage drop occurring at the time of data write. As indicated by a block of a broken line having a reference numeral 1₁, 1 n , 2₁ or 2 n (n is an integer), one memory transistor and one select transistor configure one bit. A one-dotted chain line which includes the one-bit blocks 1₁ - 1 n correspond to one byte. WL1 - WLn indicate word lines, BL1 - BLn indicate bit lines, and PL indicates a program line for controlling the control gates of the memory transistors 11 - 14. V CG is a voltage of the program line PL. V SS is a low-potential side power source or indicates the voltage thereof (ground (GND) for example). One byte indicated by the one-dotted chain line is selected as follows. The word line WL1 is turned ON, and the bit lines BL1 - BLn are set to a predetermined potential. In response to this change of the word line WL1, the select transistors 15 and 16 and the drive transistor 21 are turned ON, and a voltage is applied to the drains of the select transistors 15 and 16. When the predetermined voltage V CG is applied to the program line PL, this voltage is applied to the control gates of the memory transistors 11 and 12. At this time, the drive transistor 21 is ON because the word line WL1 is ON. Data read is executed by making a decision on whether currents pass through the memory transistors 11 and 12. However, the aforementioned EEPROM has disadvantages arising from an arrangement that the voltage V CG is applied to not only the selected memory transistors but also non-selected memory transistors when data is read out. The disadvantages caused by the above-mentioned arrangement will be described in detail below. As described previously, the drive transistors 21 - 23 for driving the control gates of the memory transistors 11 - 14 are of the depletion type (normally ON). Thus, when it is requested to read out data from the memory transistors 11 and 12 and the voltage V CG (2 - 4 volts for example) is applied to the program line PL, not only the drive transistor 21 relating to the selected memory transistors 11 and 12 but also the drive transistors 22 and 23 relating to the non-selected memory transistors are turned ON. As a result, the voltage V CG is applied to the control gates of the non-selected memory transistors 13 and 14. If data stored in the memory transistor 13 causes it to maintain ON, a voltage of 0 volt is applied to the source and drains thereof when V SS = 0 volt. At this time, voltages shown in FIG.1B are applied to the control gate 5 and the drain region 4 of the memory transistor 13 although it is not selected. Even in a standby state, a voltage is applied to the control gates of all the memory transistors as shown in FIG.1B. The state of the memory transistor 11 observed at this time is schematically illustrated in FIG.1C. In FIG.1C, C1 is a coupling capacitance between the control gate 5 and the floating gate 6, C2 is a coupling capacitance between the floating gate 6 and the drain region 4, and Q is an accumulated charge. A voltage V applied to the thin oxidation film 7 is calculated as follows. First, following formula (1) is obtained due to the fact that the accumulated charges must be conserved: C1 x (V CG - V) + Q = C2 x (V - V D ) where V CG is the voltage of the control gate, and V D is the drain voltage. From formula (1), the voltage (V - V D ) applied to the thin oxidation film 7 is represented as follows: V = (C1V CG + C2V D + Q)/(C1 + C2) V - V D = [Q + C1(V CG - V D )]/(C1 + C2) It can be seen from formula (2) that the larger the potential difference |V CG - V D |, the larger the voltage V applied to the thin oxidation film 7. When the storage data of a non-selected memory transistor causes it to maintain ON, the charge Q is a positive charge. When the voltage V CG equal to 3 volts and the voltage V D equal to 0 volt are being applied to the non-selected memory transistor, a considerably high voltage is applied to the thin oxidation film 7 thereof. In this state, the positive charge Q is liable to pour into the drain region 4 through the thin oxidation film 7. This effect functions to decrease the data holding time of the non-selected memory transistor. FIG.3 is a graph illustrating the relationship between a variation Δ Vth of the threshold voltage Vth of a memory transistor and the bias applying time. It can be seen from the graph of FIG.3 that the larger the voltage difference |V CG - V D |, the larger a variation ΔVth where ΔV th is the difference between an threshold voltage in the initial state and a threshold voltage in the data erase or write state as shown in FIG.5. FIG.4 is a graph illustrating the relationship between the data holding time (log. scale) and the voltage difference |V CG - V D |. It can be seen from the graph of FIG.4 that the data holding time decreases with an increase of the voltage difference |V CG - V D |. It can be seen from the above discussion that a reduction of the variation ΔVth with respect to the data readout time contributes to an improvement of the data holding time. FIG.6 is a graph illustrating the relationship between the data holding time and the number of times that data is repeatedly rewritten. It can be seen from the graph of FIG.6 that the data holding time decreases with an increase of the number of times that data is repeatedly rewritten. As described above, since the voltage difference |V CG - V D | is large in the non-selected memory transistor at the time of data read and in the standby state, it is difficult to improve the data holding time and provide an increased number of times that data can be erased or written. It is therefore desirable to provide an improved EEPROM in which the above-mentioned disadvantages are eliminated. In particular, it is desirable to provide an EEPROM having an improved data holding time and an increased number of times that data can be rewritten. EP-A-0 154 379 discloses an EEPROM according to the preamble of accompanying claim 1. According to the present invention, there is provided an electrically erasable and programmable read only memory comprising: a memory cell array including a plurality of memory cells coupled to bit lines and word lines, each of said memory cells including a select transistor controlled by one of said word lines, and a memory transistor having a drain coupled to one of said bit lines through said select transistor and having a control gate; select means for selecting at least one of said bit lines and one of said word lines on the basis of an address supplied from an external device, and including drive transistors each having a gate coupled to a respective one of the word lines and applying a control gate voltage supplied through a program line to the control gates of the memory transistors of the memory cells associated with the respective word line; and sense amplifier means for outputting data stored in said memory cell array; wherein said drive transistors are of the enhancement type, and wherein said select means is arranged such that when it selects one of said word lines at the time of reading out data stored in the associated memory cells the respective drive transistor is turned ON due to a level change of said selected word line so that said control gate voltage is applied to said control gates of said memory transistors through said turned-ON drive transistor and thereby drives the corresponding memory transistors, and the other memory transistors associated with the non selected word lines are provided with no control gate voltage through the corresponding drive transistors being held OFF; characterised in that said select means is arranged to de-select the word line after the program line and the bit lines have been discharged. Reference is made, by way of example, to the accompanying drawings in which: FIGS.1A, 1B and 1C are diagrams illustrating a conventional EEPROM and disadvantages thereof; FIG.2 is a circuit diagram of a conventional EEPROM; FIG.3 is a graph illustrating the relationship between a variation ΔVth of the threshold voltage Vth of a memory transistor and the bias applying time; FIG.4 is a graph illustrating the relationship between the data holding time and a voltage difference |V CG - V D |; FIG.5 is a graph illustrating a variation ΔVth of the threshold voltage when the memory transistor is switched to the write state or the erase state from the initial state; FIG.6 is a graph illustrating the relationship between the data holding time and the number of times that data is repeatedly rewritten; FIG.7 is a circuit diagram of a preferred embodiment of the present invention; FIG.8 is a waveform diagram of signals at different parts of the circuit shown in FIG.7 when reading out data; FIG.9 is a block diagram of a peripheral circuit of a memory cell array according to the embodiment of the present invention; FIG.10 is a timing chart of signals at different parts of the memory cell array and the configuration shown in FIG.9; FIG.11A is a circuit diagram of a memory cell and its peripheral circuit; FIG.11B is a circuit diagram of a circuit which outputs a sense output; and FIG.11C is a circuit diagram of a reference generator shown in FIG.9. DESCRIPTION OF THE PREFERRED EMBODIMENTS A description is given of a preferred embodiment of the present invention with reference to FIGS.7 and 8. In FIG.7, those parts which are the same as those in the previous figures are given the same reference numerals. Referring to FIG.7, there is illustrated a part of a memory cell array 100. Driving transistors 31, 32 and 33, which are substituted for the driving transistors 21, 22, and 23 shown in FIG.2, drive the control gates of the corresponding memory transistors 11 - 14. It is noted that the driving transistors 31, 32 and 33 are formed by enhancement type transistors (normally OFF). The use of enhancement transistors is intended not to apply a voltage to the control gates of non-selected memory transistors. It is noted that a simple replacement of the depletion type driving transistors 21, 22, and 23 with the enhancement type driving transistors 31, 32 and 33 causes some problems as will be described later. Thus, according to the embodiment, some improvements in data readout timing are provided. Data readout is executed for every byte. For example, the word line WL1 is set ON and the word lines WL2 and WL3 are set OFF. Further, the voltage V D is applied to the bit lines BL1 - BLn equal to one byte. The sources are set to the floating state or zero volt, and the voltage V CG is set to V G . In this state, voltages are applied only to the control gates and drains of the selected memory transistors equal to one byte and, on the other hand, the control gates and drains of the non-selected memory transistors are set to the floating state. Voltage values in this condition is listed in the following table. It is noted that if the word line WL1 being ON is turned OFF at the same time as data readout is completed, charges are shut in the control gates and/or drains of the memory transistors 11 - 14. Thus, a voltage is being applied to the drains and/or control gates even after the completion of data readout. Similarly, if the bit lines BL1 - BLn being ON are turned OFF at the same time as data readout is completed, charges are shut in the control gates of the memory transistors 11 - 14. Thus, it is necessary to turn OFF the word line WL1 after setting the voltage V CG applied to the control gates and the voltage V BL of the bit lines BL1 - BLn to zero volt. That is, as shown in FIG.8, the control gate voltage V CG is decreased to zero volt and the voltage V BL of the bit lines BL1 - BLn is decreased to zero volt, and thereafter the word line WL1 is turned OFF, or in other words, the voltage V WL1 of the word line WL1 is set to zero volt (discharged). As will be describe later, when a sense amplifying operation is completed, the control gate voltage V CG and the bit line voltage V BL are set to zero volt, and thereafter the word line voltage V WL1 is set to zero volt with a predetermined delay of time equal to 1 ns, for example. With such dynamic readout timing, it becomes possible to discharge the charges accumulated in the control gates of the memory transistors so that no voltages are applied to the memory transistors during a time other than data readout time. In the standby mode, all the word lines WL are OFF, and no voltages are applied to the drains and control gates. It is preferable that the control gate voltage V CG be equal to the bit line voltage V BL . For example, (V CG , V D ) = (1V, 1V), (2V, 2V), (3V, 3V) or the like. Advantages presented by this setting of V CG and V BL can be seen from the graph of FIG.4. A description is given of a peripheral circuit the memory cell array 100. Referring to FIG.9, there is illustrated a peripheral circuit of the memory cell array. An address buffer 41 receives an address ADD supplied from an external device (not shown) such as a central processing unit, and generates a detection signal ATDa when the received address ADD changes. A chip enable buffer 42 receives a chip enable signal CE which is a low-active signal, and outputs a low-active detection signal ATDCE . An address transition detection signal generator 43 (hereinafter simply referred to as an ATD generator) receives the signals ATDa and ATDCE , and generates an address transition detection signal (hereinafter simply referred to as an ATD signal (or signal ATD) as shown in (c) of FIG.10. A sense amplifier controller 44 receives the ATD signal, and generates an n-channel active signal (hereinafter simply referred to as a NACT signal or signal NACT), a low-active p-channel active signal (hereinafter simply referred to as a PACT signal or signal PACT ), and a delayed n-channel active signal (hereinafter simply referred to as a DNACT signal or signal DNACT). As shown in (d) and (e) of FIG.10, the NACT signal has a pulse wider than that of the PACT signal. As shown in (e) and (f) of FIG.10, the DNACT signal has a pulse wider than that of the NACT signal. The leading edges of the signals PACT , NACT and DNACT are in synchronism with the leading edge of the ATD signal. A reference generator 45 receives the NACT signal, and generates a sense amplifier reference voltage signal (hereinafter simply referred to as an SREF signal or signal SREF), a program line signal corresponding to the aforementioned voltage V CG (hereinafter simply referred to as a PL signal or signal PL), and a program line dummy signal (hereinafter simply referred to as a PLD signal or signal PLD). The SREF signal is shown in (g) of FIG.10, and the PL signal and PLD signal are shown in (h) of FIG.10. The SREF signal has the same pulse width as the NACT signal, and has a reference level (3 volts for example) lower than the positive power source voltage V DD (5 volts for example). Each of the signals PL and PLD has the same pulse width and has a potential (about 2 volts for example) lower than the reference level of the SREF signal. As will be described, the potential of the PLD signal is set slightly lower than that of the PL signal. A detailed configuration of the reference generator 45 will be described later. A decoder 46 decodes the address ADD supplied from the address buffer 41, and generates a row address Xn (1 - n) and a column address Ym (1 - m). FIG.11A illustrates a part of the EEPROM according to the embodiment of the present invention. The illustrated configuration includes a bit line BL to which a memory cell 62 is coupled, a dummy bit line BLD to which a reference (dummy) memory cell 68 is coupled, a word line WL to which the memory cell 62 and the dummy memory cell 68 are coupled, and a sense amplifier 51 provided for the bit line BL and the dummy bit line BLD which are paired. The memory cell 62 includes a drive transistor 62a of the enhancement type, a select transistor 62b and a memory transistor 62c having a floating gate, which correspond to the aforementioned transistors 31, 15 and 11, respectively. The reference (dummy) memory cell 68 includes a drive transistor 68a, a select transistor 68b and a memory transistor 68c which does not have a floating gate but a normal gate. The sense amplifier 51 includes a flip-flop 52, which is made up of two p-channel MOS transistors 52a, 52b and two n-channel MOS transistors 52c and 52d. The state of the flip-flop 52 is based on the difference in potential between nodes NR and ND. The sources of the transistors 52a and 52b are coupled to the positive power source V DD through a p-channel MOS transistor 53, and the sources of the transistors 52c and 52d are coupled to the negative power source V SS (ground) through an n-channel MOS transistor 54. The gates of the transistors 53 and 54 are supplied with the signals PACT and NACT, respectively. The nodes NR and ND are coupled to the bit line BL and the dummy bit line BLD through n-channel MOS transistors 55 and 56, respectively. The gates of the transistors 55 and 56 are supplied with the PACT signal. An n-channel MOS transistor 57 is connected across the nodes NR and ND. The gate of the transistor 57 is supplied with the ATD signal. The positive power source voltage V DD is applied to the bit line BL through three n-channel MOS transistors 58, 59 and 60 connected in series. Similarly, the positive power source voltage V DD is applied to the dummy bit line BLD through three n-channel MOS transistors 64, 65 and 66 connected in series. The transistors 60 and 66 form a column gate. The ATD signal is supplied to the gates of the transistors 58 and 64. The SREF signal is supplied to the gates of the transistors 59 and 65. The row address Xn is applied to the word line WL, and the column address Ym is applied to the gate of the transistor 60 through an n-channel MOS transistor 63 provided in the program line PL. The gate of the transistor 66 is supplied with the positive power source voltage V DD through an n-channel MOS transistor 69 provided in the dummy program line PLD. An n-channel MOS transistor 61 is provided between ground and the connection node of the transistors 55 and 59. Likewise, an n-channel MOS transistor 67 is provided between ground and the connection node of the transistors 57 and 67. A circuit shown in FIG.11B is connected across the nodes NR and ND. The circuit shown in FIG.11B is made up of NAND gates 71a, 71b, 71c and 71d, and inverters 71e and 71f. The DNACT signal is applied to the NAND gates 71a and 71b, which are connected to the nodes NR and ND, respectively. A sense output is drawn from the inverters 71e and 71f. FIG.11C is a circuit diagram of the reference generator 45 shown in FIG.9. The reference generator 45 is made up of a p-channel MOS transistor 45a, and n-channel MOS transistors 45b - 45h. The MOS transistor 45b is of the depletion type. The NACT signal is applied to the gates of the transistors 45a, 45e and 45f. The potential of the gate of the transistor 45g is equal to a potential obtained by subtracting the threshold voltages of the transistors 45a and 45b from the positive power source voltage V DD . With V DD equal to 5 volts, the gate voltage of the transistor 45g is approximately 3 volts. This voltage forms the aforementioned SREF signal. The PL signal is drawn from the connection node of the transistors 45g and 45h. The potential of the PL signal corresponds to a potential obtained by subtracting the threshold voltage of the transistor 45g from the potential of the SREF signal. With the SREF signal equal to 3 volts, the voltage of the PL signal is approximately 2 volts. The reference generator 45 further includes a circuit which is identical to that shown in FIG.11C and generates the PLD signal. It is preferable that the voltage of the PLD signal, V PLD satisfy the following formula: V PLD ≒ C R V PL where V PL is the potential of the program line PL and C R is a cell capacitance ratio. In operation, when the address ADD changes (FIG.10(a)), the ATD generator 43 shown in FIG.9 generates the ATD signal (FIG.10(c)). Assuming that the bit line BL and the word line WL shown in FIG.11A are selected. In synchronism with the rise of the ATD signal, the signals PACT and SREF rise (FIG.10(d), (g)), and the signals NACT and DNACT fall (FIG.10(e), (f)). At this time, the transistors 58, 59 and 60 are turned ON so that the bit line BL is charged up. Similarly, the transistors 64, 65 and 66 are turned ON so that the dummy bit line BLD is charged up. Further, the program line BL and the dummy program line BLD are charged up. When the PACT rises, the flip-flop 52 is disconnected from the positive power source V DD and the negative power source V SS (ground). Further, the flip-flop 52 is connected to the bit line BL and the dummy bit line BLD, and the nodes NR and ND are short-circuited so that the potential of the node NR is set equal to that of the node ND. When the ATD signal falls, charging-up of the bit line BL and the program line PL is terminated. Then a slight potential difference between the bit line BL and the dummy bit line BLD occurs (FIG.10(i)). When the memory transistor 62c has data "1", the potential of the bit line BL is higher than that of the dummy bit line BLD. On the other hand, when the memory transistor 62c has data "0", the potential of the bit line BL is lower than that of the dummy bit line BLD. The potential difference between the bit line BL and the dummy bit line BLD gradually increases. When the PACT signal falls, the flip-flop 52 is disconnected from the bit line BL and the dummy bit line BLD. The flip-flop 52 functions to amplify the potential difference between the bit line BL and the dummy bit line BLD (FIG.10(j)). Then the NACT signal rises, and the signals SREF, PL and PLD fall. Thereby, the bit line BL and the dummy bit line BLD are discharged through the transistors 61 and 67, respectively, and the program line PL and the dummy program line PLD are set to zero volt. After that, the NACT signal rises and the sense output drawn from the inverters 71e and 71f shown in FIG.11B is settled (FIG.10(j)). Then the voltage V WL of the word line WL is decreased to zero volt (FIG.10(b)). It is noted that at the time of data readout, the bit line BL and the program line PL (control gate of the transistor 62a) are set to zero volt before the word line WL is turned OFF. It is Further noted that the potential of the bit line BL is set approximately equal to the potential of the program line PL (control gate). These timing arrangements are based on the employment of the enhancement type transistors which form the drive transistors of the memory cells. The present invention is not limited to the aforementioned embodiments, and variations and modifications may be made without departing from the scope of the present invention.

Claims: An electrically erasable and programmable read only memory comprising: a memory cell array (100) including a plurality of memory cells (1₁-1 n , 2₁-2 n ) coupled to bit lines (BL1-BLn) and word lines (WL1-WL3), each of said memory cells including a select transistor (15-18) controlled by one of said word lines, and a memory transistor (11-14) having a drain coupled to one of said bit lines through said select transistor and having a control gate (5); select means (31-33, 41-46) for selecting at least one of said bit lines and one of said word lines on the basis of an address (ADD) supplied from an external device, and including drive transistors (31-33) each having a gate coupled to a respective one of the word lines and applying a control gate voltage (V CG , PL) supplied through a program line (PL) to the control gates of the memory transistors of the memory cells associated with the respective word line; and sense amplifier means (51) for outputting data stored in said memory cell array; wherein said drive transistors (31-33) are of the enhancement type, and wherein said select means is arranged such that when it selects one (WL1) of said word lines at the time of reading out data stored in the associated memory cells (1₁-1 n ) the respective drive transistor (31) is turned ON due to a level change of said selected word line so that said control gate voltage (V CG , PL) is applied to said control gates of said memory transistors through said turned-ON drive transistor and thereby drives the corresponding memory transistors, and the other memory transistors (2₁-2 n ) associated with the non-selected word lines (WL2, WL3) are provided with no control gate voltage through the corresponding drive transistors (32,33) being held OFF; characterised in that said select means (31-33, 41-46) is arranged to de-select the word line (WL1) after the program line (PL) and the bit lines (BL1-BLn) have been discharged. A memory as claimed in claim 1, wherein said select means further comprises generating means (43-45) for generating said control gate voltage (V CG , PL) in response to a transition of said address (ADD). A memory as claimed in claim 2, wherein said generating means (43-45) is arranged to stop generating said control gate voltage (V CG , PL) before a next transition of said address occurs. A memory as claimed in claim 2 or 3, wherein said generating means (43-45) is arranged to generate said control gate voltage (V CG , PL) which is equal to a potential (V BL ) of said bit lines when said bit lines are selected by said select means. A memory as claimed in any of claims 2 to 4, further comprising a transistor (59) provided for each of said bit lines (BL), said transistor having a gate and coupling the corresponding bit line to a power source (V DD ), and wherein said generating means (43-45) is arranged to generate a voltage signal (SREF) to be applied to said gate of the transistor (59), wherein the potential (V BL ) of each of said bit lines is based on said voltage signal applied to said transistor (59). A memory as claimed in claim 5, wherein said generating means (43-45) is arranged to generate said voltage signal (SREF) in response to a transition of said address (ADD), and to stop generating said voltage signal before a next transition of said address occurs. A memory as claimed in any of claims 2 to 6, wherein said generating means (43-45) derives said control gate voltage (V CG , PL) from a predetermined positive power source voltage (V DD ) in response to said transition of said address (ADD). A memory as claimed in any preceding claim, further comprising discharging means (61) for discharging said selected bit line after a predetermined time has passed from a transition of said address and for stopping discharging said bit line before a next transition of said address occurs. A memory as claimed in any preceding claim, further comprising a transistor (63) provided in said program line (PL), wherein said transistor (63) is turned ON when the corresponding one (BL) of said bit lines is selected by said select means. A memory as claimed in any preceding claim, wherein said memory cell array (100) comprises a plurality of dummy memory cells (68) coupled to said word lines (WL) and dummy bit lines (BLD) which are paired with said bit lines (BL). A memory as claimed in claim 10, wherein said sense amplifier means (51) includes means provided for each of the pairs of said bit lines (BL) and dummy bit lines (BLD), for sensing and amplifying a potential difference between said pair of the bit line and dummy bit line. A memory as claimed in any preceding claim, wherein said memory cell array (100) is divided into a plurality of blocks each including a predetermined number of said memory cells (1₁-1 n ). A memory as claimed in claim 12, wherein said select means (31-33, 41-46) selects one of said word lines (WL1-WL3) and said bit lines having the same number as said memory cells contained in each of said blocks so that said memory cells are selected per block unit. A memory as claimed in any preceding claim, wherein said select means (31-33, 41-46) is arranged to supply said control gate and drain of said memory transistor of said selected one of said memory cells with a substantially equal voltage when reading out said information stored therein.

Inventors: EMA TAIJI, NAKAHARA MASAHIRO, EMA, TAIJI, NAKAHARA, MASAHIRO
Applicants: FUJITSU LTD, KYUSHU FUJITSU ELECTRONIC, FUJITSU LIMITED, KYUSHU FUJITSU ELECTRONICS LIMITED
Application year: 1989
Main classification: G11C16
IPC codes: G11C16