Fabrication of silicon structures by single side, multiple step etching process

Abstract: Three dimensional silicon structures are fabricated from {100} silicon wafers by a single side, multiple step ODE etching process. All etching masks (26, 28) are formed one on top of the other prior to the initiation of etching, with the coarsest mask (28) formed last and used first. Once the coarse anisotropic etching is completed, the coarse mask is removed and the finer anisotropic etching is done. The three dimensional structure may be a thermal ink jet channel plate, in which case the etching process is a two-step process in which the coarse etching step provides the ink reservoir (30) and the fine etching step provides the ink channels (32).

Description: This invention relates to an orientation dependent etching process for the fabrication of three dimensional structures from silicon, and more especially to the use of such a process for the production of ink jet printheads. A fundamental physical limitation of orientation dependent etching (ODE) in silicon is that {111} crystal planes etch very slowly, while all other crystal planes etch rapidly. Consequently, only rectangles and squares can be generated in {100} silicon material or wafers with a high degree of precision. Even with rectangles and squares, the dimensional precision of the etched recesses or holes requires that the edges of the mask defining the rectangles or squares be aligned with the intersection of the {111} and {100} crystal planes. In the semiconductor industry, it is frequently desirable to generate large recesses or holes in association with relatively shallow recesses, which may or may not interconnect. For example, an ink jet printhead may be made of a silicon channel plate and a heater plate. Each channel plate has a relatively large ink manifold/reservoir recess or opening and a set of parallel, shallow, elongated channel recesses connecting to the reservoir at one end and open at the other end. When aligned and bonded with the heater plate, the recesses in the channel plate become the ink reservoir and the ink channels, as described more thoroughly in U.S. patent Re. 32,572 discussed below. In such printheads, it is frequently desirable to generate a large reservoir, which is often etched completely through a 15 to 20 mil (0.38 to 0.5 mm) thick wafer, with small perpendicularly connecting channels which may be only 1 or 2 mils (0.025 to 0.05 mm) deep on the same silicon substrate. A major difficulty associated with fabrication of such a structure is that the channels and reservoir must be separately etched and then subsequently joined by a variety of methods, such as isotropic etching, dicing away the silicon material between the reservoir and channel, or use of a thick film layer on the heater plate that is patterned and etched to form ink flow bypasses. Generally, such a structure is formed by etching a plurality of reservoirs in a {100} silicon wafer first, and then accurately aligning the channels to the edge of the reservoir in a second lithography step, followed by etch mask delineation and a second short ODE step sufficient to etch the depth of the plurality of sets of associated channels. An advantage of such a process is that control of channel dimension would be very high because the mask defining the channels will be undercut about 1/10 as much as would be the case when the channel and reservoir are delineated simultaneously. This is because the {111} planes have a finite etch rate and the etch time for channels for the two cases is about a factor of 10 different. In fact, in order to etch through 508 µm (20 mils) of silicon in a short time, the etch is optimized for rapid etching and etch anisotropy suffers. If the shallow depth etch was done in a separate step, anisotropy could be increased from 1:100 to 1:400 or higher, depending on desired accuracy. The problem with such a two-step process is that it is difficult or impossible to do a second lithography step on an ODE etched wafer due to the large steps and/or etched through holes. The resist mask is very non-uniform and cannot be exposed for many reasons. Reissue patent Re. 32,572 to Hawkins et al discloses a thermal ink jet printhead and method of fabrication. A plurality of printheads may be concurrently fabricated by forming a plurality of sets of heating elements with their individual addressing electrodes on one silicon wafer or other substrate and etching corresponding sets of grooves which may serve as ink channels with a common reservoir in another silicon wafer. The two wafers are aligned and bonded together, so that each channel has a heating element. The individual printheads are obtained by milling away the unwanted silicon material in the channel wafer to expose the addressing electrode terminals on the heating element wafer and then dicing the heating element wafer to obtain separate printheads. U.S. 4,612,554 to Poleshuk discloses an ink jet printhead comprising two identical parts and a method for producing it. A plurality of V-shaped grooves are anisotropically etched on each part of the printhead between a linear array of heating elements. The grooves allow the parts to be mated in an automatically self-aligned manner. U.S. 4,638,337 to Torpey et al discloses a two-part ink jet printhead comprising a channel plate and a heater plate. A thick film insulative layer is placed over the passivation layer for the circuitry on the heater plate and etched to open recesses therein above the heating elements and electrode terminals. This effectively places the heating elements in a pit, the walls of which inhibit bubble growth in the direction parallel with the direction of ink flow in the channels and promotes the bubbles growth in a direction normal to the heating elements. The net result is that "blow out" of the bubble is eliminated and the consequent ingestion of air prevented. U.S. 4,639,748 to Drake et al discloses a two-part ink jet printhead comprising a channel plate and a heater plate. The manifold recess in the channel plate has an internal chamber recess provided by an enclosing wall inside of and surrounded by the manifold recess with the internal chamber wall having small passageways at its upper end, so that, when mated with the heater plate, ink is filtered when it flows from the internal chamber to the manifold through the small passageways because each of the small passageways have a flow area smaller than each of the nozzle flow areas. However, the total flow area of the small passageways is greater than the total flow area of the nozzles. EP-A-0 322 228 discloses a large pagewidth array ink jet printhead comprising a heater plate and a channel plate. The channel plate is composed of a juxtaposed plurality of identical silicon sub-units, each having parallel opposite sides formed along the {111} crystal planes which permit accurate end-to-end assembly to produce the pagewidth channel plate. WO-A-85/03580 discloses a process for forming slots of different types in self aligned relationship using a latent image mask. In one embodiment an oxide of the semiconductor material (SiO 2 ) (11) is used as a unitary masking layer. In another embodiment, at least a dual layer latent image mask is used in which two materials (31, 32) have different etch properties. One layer (31) is used as a stop etch layer during fabrication of one of the slot types (34). The present invention is concerned with facilitating the production of three-dimensional structures from silicon wafers. The present invention provides a method of fabricating a three dimensional structure from a silicon wafer whose surface is specifically oriented with respect to the {100} and {110} crystal planes of the wafer comprising the steps of: (a) forming a first layer of etch resistant material on both sides of the wafer; (b) patterning the first layer of etch resistant material on one side of the wafer to produce at least one precisely located via therein for subsequent orientation dependent etching (ODE) of at least one recess, so that said recess(es) will be bounded by walls lying along the {111} planes of the wafer; (c) forming a second layer of etch resistant material on both sides of the wafer and over the first layer of etch resistant material including the via(s) therein; (d) patterning the second layer of etch resistant material on the same side of the wafer as the patterning on the first layer of etch resistant material to produce at least one via within the boundary of the via in said first layer of etch resistant material, for subsequent production of relatively deep recesses in the wafer by ODE; (e) placing the wafer into an anisotropic etchant medium to produce at least one relatively deep coarse recess in the wafer through the via(s) in the second layer of etch resistant material; (f) removing the second layer of etch resistant material ; and (g) replacing the wafer into the anisotropic etchant medium to produce at least one relatively shallow, fine recess in the wafer through the via(s) in the first layer of etch resistant material. The wafer surface may be in the{100} crystal plane of the wafer. Alternatively, the wafer surface may be at a precise angle  with respect to the {100} plane of the wafer and toward the {110} plane, so that anisotropic etching produces trapezoidal shaped recesses in the wafer. If required, one or more additional etch resistant layers may be formed on the wafer and patterned before the wafer is placed into an anisotropic etchant medium, each layer being more coarsely patterned than the previously-formed layer to create a multi-layer sequential etching structure. The first and second layers may be, respectively, a thermally grown oxide (SiO 2 ) having a thickness of about 500 nm (5000Å), and silicon nitride (Si 3 N 4 ) having a thickness sufficient to provide the desired robustness to the wafer. A method in accordance with the invention may be used to fabricate a plurality of channel plates for assembly with a plurality of heater plates to produce a quantity of ink jet printheads. In such a method described herein, the said at last one via in the second layer is so positioned within the boundary of the via in the first layer that a predetermined border exists between the edges of the vias in the first and second layers. In that method, the said at least one via in the first layer has a plurality of parallel extensions which will enable the production of ink channel recesses connected directly to an associated ink reservoir recess. When a method in accordance with the invention is being carried out, a silicon wafer assembly is formed comprising a silicon wafer and at least two layers of etch resistant material on one side of the wafer, said layers being patterned to produce a via in the layer for the subsequent production in the wafer of a recess by etching, wherein the via in one layer is located within the boundary of a via in the previously-formed layer, characterised by said layers being formed on both sides of the wafer, by one layer being removable for the subsequent production in the wafer of a further recess less coarsely patterned than the recess first etched, and in that the recesses are produced by orientation independent etching. By way of example, methods in accordance with the invention will now be described with reference to the accompanying drawings, in which: Figure 1 is an enlarged, partially shown, plan view of a prior art ODE etched channel plate, showing a deep reservoir recess and its associated shallow elongated channel recesses. Figure 2 is a cross-sectional view of Figure 1 as viewed along view line 2-2. Figure 3 is a partially shown, schematic plan view of a mask delineated wafer formed during a method according to the present invention, the underlying SiO 2 patterned via being shown in dashed line. Figure 4 is an enlarged, cross-sectional view of the wafer of Figure 3, as viewed along view line 4-4. Figure 5 is an enlarged, cross-sectional view of the wafer of Figure 3, as viewed along view line 5-5. Figure 6 is similar to Figure 4, but after the second etching process and with the heater plate added in dashed line. Figure 7 is similar to Figure 5, but after the second etching process. Figure 8 is a schematic isometric representation of a silicon wafer showing intentional misorientation of a {100} wafer. Figure 9 is a schematic plan view of a silicon wafer wherein intentional misorientation of {100} wafer creates trapezoidal recesses when anisotropically etched. From the prior art (see e.g. US patent Re 32 572), it is known to produce a thermal ink jet printhead by aligning and bonding an ink directing channel plate to a heater plate. A typical prior art type silicon channel plate 10 is shown in Figure 1 in a partially fabricated state and in an enlarged plan view. A plurality of parallel, elongated shallow recesses 12 and one relatively large deep recess 14 have been anisotropically or orientation dependently etched (ODE). The large recess could optionally have been etched entirely through the channel plate. In the configuration shown, an inlet means to recess 14 is yet to be provided. The inlet means may be produced by any well known means such as by etching techniques disclosed in the above references. Both the shallow recesses 12 and the large recess 14 have walls 13, 15 respectively, that lie along the {111} planes of the silicon channel plate. Figure 2 is a cross-sectional view of the partially constructed channel plate shown in Figure 1 as viewed along view line 2-2 therein and mated with a heater plate 16 shown in dashed line. The silicon material 17 intermediate the shallow recesses 12 and large deep recess 14 may be removed by dicing or isotropic etch, to provide communication between the shallow and deep recesses. A typically etched inlet 11 is shown in dashed line and a prior art printhead is readily recognized. Fabrication of the prior art printhead is complete with a dicing cut along dashed line 20 located a predetermined distance from heating element 18 also shown in dashed line. Figure 3 shows a simplified schematical plan view of a portion of a silicon wafer surface 22, having two sequentially formed etch masks 23, 24 thereon in accordance with the present invention. Precise three dimensional structures in silicon having both shallow and deep recesses may be formed by sequential ODE processing. It is enabled by the use of two or more masks which are successively deposited and delineated on a single side of the silicon wafer. The top mask is for the deeper or coarser anisotropic etching. The first etching is followed by stripping of the outer mask and then a next anisotropic etching step is performed. The sequential etching is accomplished by conducting the deepest or coarsest etch first and proceeding successively from the coarsest to the finest etched features of the structure. After each etch, its mask is stripped exposing the next mask, followed by another anisotropic etch. Therefore, the need to create a lithographically delineated mask between etching processes is eliminated. The high tolerance fine or precise features are better preserved and protected by the coarser mask. The embodiment of the invention described below relates to a thermal ink jet printhead component, namely, the channel plate 21 (see Figure 6). However, the application of the described method is much broader and relates also to the fabrication of other three dimensional silicon structures such as dimensionally true channel plate subunits suitable for abutting assembly to form a full pagewidth printhead or read-in scanner (RIS) arrays. In Figures 3 through 5, a {100} silicon wafer 19 is partially shown with a thermally grown oxide layer (SiO 2 ) 26 on both sides which is about 500 nm (5000Å) thick. It is lithographically processed to form a via 23 therein shown in dashed line. This via enables the production of the ink channels and connected reservoir. Although the via shows only three parallel extensions 25 which represent the future ink channels, there are 300 to 600 per inch in an actual printhead. The small number of extensions shown is for ease of explanation, it being understood that the same principle applies for an actual printhead. A silicon nitride (Si 3 N 4 ) layer 28 is then deposited over the patterned SiO 2 layer and exposed silicon wafer surface 22. The thickness of the Si 3 N 4 layer is sufficient to assure adequate robustness to prevent handling damage during subsequent processing steps. The Si 3 N 4 layer 28 is then lithographically processed to produce via 24, so that via 24 exposes the bare silicon surface 22 of wafer 19. Note that a border 29 of Si 3 N 4 (see Figure 5) is left about 25,4 µm (1 mil) wide inside of the SiO 2 via 23 both for protection and limitation of undercutting during subsequent ODE processing. When the wafer is anisotropically etched, the silicon is etched through where exposed by via 24 to form reservoir recesses 30. Figure 4 is a cross sectional view of Figure 3 as viewed along view line 4-4 thereof and after a first anisotropic etching, so that the reservoir recess 30 is shown together with via 23 along the length of an extension 25. Figure 5 is a cross sectional view of Figure 3 as viewed along view line 5-5 thereof and after a first anisotropic etching to form reservoir recesses 30. The walls 31 of the anisotropically etched reservoir recess 30 lie in the {111} crystal planes of the wafer. A border 29 of Si 3 N 4 prevents undercutting of the closer tolerance etch mask or via 23 during the coarser etching of the reservoir recesses 30. Referring to Figure 6, the Si 3 N 4 layer 28 is then stripped and the wafer cleaned, and it is ODE processed again using the SiO 2 layer 26 as a mask to etch the channel recesses 32. Concurrently with the channel etching, the border 29 is etched enlarging the reservoir slightly, while maintaining its {111} crystal plane walls 31. Figure 6 is a view similar to that of Figure 4 showing the cross sectional view of the wafer 19 after the channel recesses 32 have been etched and the reservoir enlarged. Heater plate 16 has been added in dashed line for ready comparison with the prior art channel plate of Figure 2. Note that the channel recesses 32 are already connected to the reservoir recess 30. Figure 7 is a view similar to that of Figure 5, but also after the second etching process. Before the channel plate wafer 19 and heater plate wafer 16 are aligned, bonded and diced, the SiO 2 layer 26 is totally removed or removed only from the bottom 34 of the reservoir 30 to permit ink access thereto, as shown in dashed line in Figures 6 and 7. The method just described is a two step etch process applied on {100} oriented wafers to produce small rectangular or square features with precise dimensional control on the same substrate with large features that are typically etched most or all the way through a wafer. A similar method allows formation of trapezoidal shaped recesses 36 in a silicon wafer 35, as shown in Figure 9. If the surface 37 of the silicon wafer 35 in Figure 8 is intentionally misoriented to a precise number of degrees off {100} plane in the {110} plane direction, as shown by angle Θ in Figure 8, trapezoidal shapes 36 can be constructed by the same two step etch process. Figure 8 shows the configuration for intentional misalignment of the wafer, and Figure 9 shows the resultant shapes created. The methods described enable batch fabrication of three dimensional silicon structures by a single side, multi-step ODE processing technique without the need for additional intermediate lithographic steps and etch mask delineations for each subsequent ODE process.. All masks are formed one on top of the other prior to etching, with the coarsest mask used first and the highest tolerance or finest mask used last. Once the coarse anisotropic etching is completed, the coarse mask is removed and the fine anisotropic etching is done. Because anisotropy can be adjusted for fast or slow etch rates, the fabrication of structures having both large, coarse features and small, precise features (for example, both large deep recesses or large through holes and shallow high tolerance recesses) can be done much faster and the mask undercutting greatly reduced. All lithography is conducted prior to the first etch step. An obvious extension of the methods is to add more than two etch steps to the process. A good example of a three dimensional silicon structure is a channel plate for a thermal ink jet printhead of the type described in U.S. Reissue patent Re. 35,572 to Hawkins et al. Through the use of a method as described above, a channel plate can be produced by a single side, multi-step ODE etching process. In the described method, a deep, through-wafer etch and associated shallow recess are both sequentially carried out on the same side of the wafer. Deep and shallow etches are usually required for ODE formation of thermal ink jet channel plates. In the channel plate example, a 500 nm (5000 Å) thick thermal oxide (SiO 2 ) is grown on a {100} silicon wafer. Lithography is performed to delineate an array of channels, a connected reservoir, and alignment marks on one side. The wafer is cleaned and a silicon nitride (Si 3 N 4 ) layer of sufficient thickness to assure robustness is deposited. The silicon nitride is delineated by a second lithographic process to form the reservoir via only, so that the edge of the silicon nitride completely borders on the exposed silicon created by the lithographic process of the thermal oxide layer. The wafer is ODE etched until the entire wafer is etched through to form the reservoir with the bottom available as an ink inlet thereto. Next, the silicon nitride is selectively stripped by any of several well known methods, and the wafer is further ODE etched to a depth necessary to form the channels. The thermal oxide layer can be left on or removed by a selective wet etch. A similar process could be used for the case where alignment holes and other deep etched holes are desired in a silicon wafer. For example, use a double layer of SiO 2 /Si 3 N 4 and remove SiO 2 only over the alignment holes, ODE etch approximately 50,8 µm (2 mils), etch off the rest of the SiO 2 , then ODE etch the rest of the way through the wafer. As an alternative the surface of a silicon wafer is intentionally misoriented a precise number of degrees off the {100} plane in the {110} plane direction, so that the single side, multi-step ODE processing technique produces trapezoidal shaped recesses. Although the foregoing description illustrates the fabrication of a thermal ink jet channel plate, it will be appreciated that the fabrication of other three dimensional silicon structures is possible in a similar manner.

Claims: A method of fabricating a three dimensional structure from a silicon wafer (19) whose surface is specifically oriented with respect to the {100} and {110} crystal planes of the wafer comprising the steps of: (a) forming a first layer (26) of etch resistant material on both sides of the wafer; (b) patterning the first layer of etch resistant material on one side of the wafer to produce at least one precisely located via (23) therein for subsequent orientation dependent etching (ODE) of at least one recess, so that said recess(es) will be bounded by walls lying along the {111} planes of the wafer; (c) forming a second layer (28) of etch resistant material on both sides of the wafer and over the first layer (26) of etch resistant material, including the via(s) (23) therein; (d) patterning the second layer of etch resistant material on the same side of the wafer as the patterning on the first layer of etch resistant material to produce at least one via (24) within the boundary of the via in said first layer of etch resistant material, for subsequent production of relatively deep recesses in the wafer by ODE; (e) placing the wafer into an anisotropic etchant medium to produce at least one relatively deep coarse recess (30) in the wafer through the via(s) in the second layer of etch resistant material; (f) removing the second layer of etch resistant material; and (g) replacing the wafer into the anisotropic etchant medium to produce at least one relatively shallow, fine recess (32) in the wafer through the via(s) in the first layer of etch resistant material. The method of claim 1, wherein the wafer surface is in the {100} crystal plane of the wafer. The method of claim 1, wherein the wafer surface (37) is at a precise angle  with respect to the {100} plane and toward the {110} plane, so that anisotropic etching produces trapezoidal shaped recesses (36) in the wafer. The method of any one of the preceding claims, wherein one or more additional etch resistant layers are formed on the wafer and patterned before the wafer is placed into an anisotropic etchant medium, each layer being more coarsely patterned than the previously-formed layer to create a multi-layer sequential etching structure. The method of any one of the preceding claims, wherein the first layer (26) of etch resistant material is a thermally grown oxide (SiO 2 ) having a thickness of about 5000Å (500nm), and wherein the second layer (28) of etch resistant material is silicon nitride (Si 3 N 4 ) having a thickness sufficient to provide the desired robustness to the wafer. The method of any one of the preceding claims, wherein the three dimensional structure is a plurality of channel plates for assembly with a plurality of heater plates to produce a quantity of ink jet printheads, and wherein the said at least one via in the second layer is so positioned within the boundary of the via in the first layer that a predetermined border exists between the edges of the vias in the first and second layers. The method of claim 6, wherein the said at least one via in the first layer has a plurality of parallel extensions which will enable the production of ink channel recesses connected directly to an associated ink reservoir recess.

Inventors: HAWKINS WILLIAM G, HAWKINS, WILLIAM G.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1989
Main classification: H01L21
IPC codes: B41J2, G02B6, H01L21, C30B29, B81B1