Digital-to-analogue conversion

Abstract: The converter incorporates a transversal filter. The filter delays are implemented in digital form prior to conversion into analogue signals (preferably using switched capacitor techniques). One form of switched capacitor converter (with or without filtering) employs a single capacitor, common to a plurality of bits, appropriate weighting of the bits being achieved by controlling the switching.

Description: The present invention relates to digital-to-analogue converters incorporating a filtering function and particularly with their implementation using switched-capacitor techniques. A typical, conventional filtering arrangement is shown in Figure 1, where successive sample values of a w-bit digital word [b₀b₁...b i ...b w-1 ] are supplied to a digital-to-analogue converter (DAC) 1 followed by an analogue FIR (finite impulse response) filter 2, based on a conventional tapped delay line structure with delays z⁻¹, filter coefficient multipliers h₀...h N-1 and an adder A (or of course a parallel structure may be used). The coefficients are selected to give any desired filter response; in general this will be a baseband response from DC to half the sampling frequency F s , followed by some rejection of unwanted frequencies above F s /2. The DAC may employ switched capacitor techniques (as described for example in Roubik Gregorian - "High Resolution Switched Capacitor D/A Converter" - Microelectronics Journal, Vol. 12, No. 2, 1981 Mackintosh Publ. Ltd); in the filter, the analogue delays may also be realised by switched-capacitor elements. The realisation of the analogue delays may however not be ideal. Alternatively, the delays may be achieved digitally as described in US Patent No. 3,543,009 (Voelcker). An arrangement using this principle shown in Figure 2 and receives, as does that of Figure 1, successive w-bit digital samples of a signal to be converted. The digital words are fed to a chain of N w-bit wide D-type bistable flip-flops DO...DN-1 which are clocked at sampling rate F s with clock pulses , so that a digital word, delayed by a respective number of sample periods, is available at the output of each flip-flop. These outputs are converted into analogue form by digital-to-analogue converters XO...XW-1 which produce at their outputs successive analogue samples corresponding to the digital samples supplied to them. The analogue outputs are multiplied by respective filter coefficients h o ...h N-1 ; multipliers MO...MN-1 are shown though in the US patent resistors are used. The weighted analogue values are then summed in an adder A. According to one aspect of the present invention there is provided an apparatus for producing a filtered analogue output signal from a digital signal in the form of a sequence of digital signal samples each having a plurality of bits comprising digital delay means for producing further sequences of digital signal samples, each being a replica of the first sequence delayed with respect thereto by a respective delay period, and means for forming an analogue signal representing the sum of the mutually delayed signal samples weighted in accordance with a desired filter response, in which the means for forming the analogue signal comprises (a) a plurality of switched capacitor arrangements, each connected to receive a respective one of the said sequences of digital signal samples; each switched capacitor arrangement having at least one capacitor and switching means for supplying, in dependence on the states of bits of each received sample, charge thereto, such that the total charge received depends on the value represented by that sample; the totals each being weighted by a respective one of a set of coefficients corresponding to the desired filter response; and (b) common summing means for receiving the charges from all the switched capacitor arrangements and forming an analogue output sequence representing the sum of those charges. Each switch capacitor arrangement may have a plurality of capacitors with values weighted accorded to the significances of the respective sample bits; or each may have a single capacitor with switching means arranged to supply a predetermined quantity of change a respective different number of times. The desired filter response may be achieved by choosing the values of the capacitor(s) in one (or more) switched-capacitor arrangements to have value(s) different from the corresponding capacitor(s) in another. Some embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:- Figure 3 is a circuit diagram of a known switched-capacitor unit; Figure 3a illustrates clock pulses used by the unit of Figure 3; Figure 4 is a block diagram of a further embodiment of filtered digital-to-analogue converter; Figure 5 is a modified version of part of Figure 3, for implementing negative filter coefficients; Figure 6 is a circuit diagram of a digital-to-analogue converter unit; Figure 7 illustrates the clock and switching pulses employed in the unit of Figure 6; Figure 8 is a block diagram of a filtered digital-to-analogue converter employing converter units of the type shown in Figure 6; Figure 9 is a modified version of part of Figure 6, for implementing negative filter coefficients; Figure 10 illustrates a practical implementation of the converter of Figure 8; Figure 11 is a block diagram of a pulse generator for driving the converter of Figure 10; and Figure 12 is a state diagram illustrating the operation of the generator of Figure 10. First, the operation of a known type of switched capacitor digital-to-analogue converter will be described with reference to Figure 3, where the input bits of a w-bit digital word are designated b o ...b w-1 and each serves to switch, according to its binary value, an electronic switch CSO...CSw-1 (shown schematically) between zero volts (referred to below as "ground") and a reference voltage V R . The converter contains a number of electronic switches controlled by the non-overlapping two-phase clock pulses ₀, ₁ at the sampling frequency F s , which are shown in Figure 3a. In Figure 3 and elsewhere, the switches are shown as rectangles containing 0 or 1 indicating that the switch is closed during clock phase 0 or 1 respectively. Using the suffix i to indicate generically the components handling signals from one bit (b i ) of the input bits b o ...b w-1 , the output of each switch CSi is connected via a switch Sli controlled by ₁ to one side of a capacitor CPi, which is also connected to ground via a switch SOi controlled by  o . The other side of each capacitor CPi is connected to a common node ND, also connected to ground by a switch S1 controlled by ₁. The capacitors have binary weighted values - i.e. the capacitance of the capacitor CPi is 2 i .C where C is the value of the smallest capacitor CPO. The node ND is also connected via a switch SO controlled by  o to the input of a high gain inverting amplifier OA which has a negative feedback path consisting of a capacitor C F in parallel with a switch S1F controlled by ₁. During clock phase 1, the capacitor C F is discharged via S1F. Also, each capacitor CPi is charged or discharged via switches S1i and S1 to the voltage (O or V R ) determined by the respective switch CSi. During clock phase  o , the total charge on the capacitors CPi is transferred to the capacitor C F so that the output of the converter is Figure 4 shows a filtered digital-to-analogue conversion apparatus according to a first embodiment of the invention where the node ND, switches S0, S1, S1F, capacitor C F and amplifier OA are common to the N converters. The flip-flops DO...DN-1 are as in Figure 2, whilst the capacitor/switch array units CSAO...CSAN-1 correspond to the components enclosed in the broken line box in Figure 3. In this embodiment, the capacitor values in each array are chosen to weight the contribution of that array to the final output by a factor corresponding to the appropriate one of the desired filter coefficients h o ...h N-1 . To accommodate negative coefficients, the array is modified by the transposition of the clock pulses illustrated in Figure 5 by transposition of switches S0i and Sli. The nth array (n=0,....,N-1) has capacitors with values 2 i .C n where C n = |h n | .C* (C* being a constant), so that the contribution of this array to the total output voltage is where z is the z-transform variable and b i,n is the value of the ith bit of the digital word at the output of the nth D-type flip-flop. The contribution of all N words for an FIR filter of length N is If we set C F =2 w .C* then the output voltage is If the smallest capacitance value C n is C, and the corresponding value of h n is h n min then the remaining capacitor values are given by C n = |h n | .C |h n | min and C F = 2 w .C |h n | min Since C F is usually the largest capacitor in the circuit, we obtain a maximum capacitance spread of C F C n min = 2 w |h n min | and a total capacitor area of For an example of FIR filtering function with equal coefficients and unity DC gain (h n =1/N, n=0, ..., N-1) the above results lead to a capacitance spread of C spread = N.2 w and a total capacitor area of C total = N.(2 w+1 -1).C. The embodiment of Figure 4 requires (N.w)+1 capacitors and (2N.w) +3 switches, increasing with both the bit resolution w of the conversion and the length N of the desired filter impulse response. This means that, even for a medium bit resolution and short filter responses, the resulting silicon area required for an integrated circuit implementation can become rather large. An alternative converter is however now proposed, having reduced number of capacitors and switches. Figure 6 shows a switched capacitor digital-to-analogue converter (without filtering). It can, as will be described in more detail below, be used to replace the converters X0..XN-1 of Figure 2, in the same manner as was the converter of Figure 3. Input bits b i and switches CSi perform the same functions as in Figure 3, as do switches S1, S0, SF, capacitor C F and amplifier OA. However, the capacitors CPi and switches S0 i are replaced by a single capacitor CP and switch S0A. The binary weighting of contribution of the w input bits is instead determined by the waveforms applied to the switches S1i (now designated SA0....SAi...SAw-1). Effectively the capacitor CP is multiplexed between the input bits. A set of switching waveforms ′₁, ′ o and A o .. A w-1 for w=4 is illustrated in Figure 7. Note that there are now 2 w-1 clock pulses ₁′ (or  o ′) in one conversion period. The waveforms A o ...A w-1 contain 1, 2, 4 etc pulses synchronous with ₁′ - ie in general the waveform A i contains 2 i pulses. At the beginning of each conversion period, the feedback capacitor C F is reset by the switch SF controlled by pulse A o . Pulse A o also closes switch SAO and the capacitor C assumes a voltage of 0 or V R according to the state of bit b o . On the following clock pulse  o ′ this charge is transferred to C F . This process is repeated by pulse A₁ for bit b₁; however, this occurs twice, as A₁ contains two pulses, and so forth, the D/A conversion being performed sequentially from bit b o to bit b w-1 . The converted output is available during pulse  ′ / o following the last pulse of A w-1 , prior to resetting of C F by a further pulse A o . Of course it is not actually necessary that the bits be processed in any particular sequence, or indeed that all the pulses for one particular bit be generated before those of another bit (though obviously the pulses must not coincide). The equivalent bit voltage V i corresponding to each bit of the digital word is determined by the number of pulses of the corresponding switching waveform A i and can thus be expressed by V i = V R .b i .2 i and therefore the converted output is Assuming [V₀ max /V R .(1-2 -N )] = 1, we can easily see from the above expression that the capacitance spread of the converter in Figure 6 is equal to the capacitance spread of the conventional converter of Figure 3, ie (C F /C)=2 w . However, the total capacitor area is now only (2 w +1).C, compared to 2 w+1 .C in a conventional converter, and the total number of capacitors has also been reduced from (w+1) to only 2. An additional significant advantage of this new architecture is that, unlike conventional converters, the accuracy of the capacitance ratio C F /C does not affect the required bit resolution, which depends solely on the number of time slots of each switching waveform. Thus, we can easily apply to the converter of Figure 6 a number of well known design techniques than can significantly reduce the capacitance spread in a switched-capacitor network (eg capacitive-T network), even though this also brings an inherent reduction of the resulting accuracy of the capacitance ratios. This makes it practical to implement high resolution converters using simple switched capacitor networks occupying a small area of silicon. It is observed that, for a given maximum switching frequency, the conversion rate (and hence sampling rate of the digital words that can be accommodated) is reduced by a factor of (2 w -1) relative to Figure 3; however the reduction in capacitor area and required capacitance ratio accuracy make this embodiment particularly useful for high resolution conversions at lower frequency. An implementation of a combined digital-to-analogue converter and FIR filter based on the binary-weighted time slot array architecture described above is illustrated in Figure 8. The flip-flops Dn are shown as for Figures 2 and 4. The converters Xn of Figure 2 are replaced by time slot arrays TAO to TAN-1, followed by common components S1, S0, OA, C F and SF which are identical to those shown in Figure 6. Each time slot array TAi is either in the form indicated in the dotted rectangle in Figure 6 (for positive h n ) or, for negative h n is structurally the same but is supplied with different pulses. Thus switches SAn supplied by pulses A n and switch SOA supplied with pulses ₀′ are replaced by switches SBn and S1A supplied with pulses B n and ₁′, as shown in Figure 9. Pulses B n (n=0...n-1) take the same form as pulses A n but are synchronous with ₀′ instead of ₁′. As in the case of the architecture of Figure 2, we can easily see that the normalised output voltage conversion level corresponding to all N digital words is also expressed by where C n = |h n | .C F 2 w in order to preserve the gain constant of the FIR transfer function. After normalisation, we obtain C nmin = C C n = |h n | |h n min | .C C F = 2 w .C |h n min | yielding a maximum capacitance spread of C spread = CF /C = 2 w |h n min | and for the total capacitor area. For many practical situations where the FIR filter is designed such that the above expression for C total shows a reduction of about 50% over the total capacitor area obtained with the previous realisation. Two additional advantages of the architecture with binary-weighted time slot arrays are obtained firstly with respect to the total number of capacitors, which has been reduced from (N.w+1) to only (N+1), and, secondly, with respect to the required capacitance ratio accuracy of the impulse response coefficients of the FIR filter. Figures 10 and 11 illustrate a simple practical implementation of the type of combined digital-to-analogue converter decribed above with reference to figure 8. It has 4-bit resolution and four equal FIR filter coefficients. The filter impulse response (in z-transform notation) is H (z) = 1 4 (1 + z⁻¹ + z⁻² + z⁻³). There are four 4-bit wide D-type flip-flops D0, D1, D2, D3. Note that the fist of these is (as in the other figures) not strictly necessary but is included to ensure accurate timing. Also the switches CSi are omitted (on the basis that, for a 4-bit implementation, the voltages output directly from the flip-flops are themselves sufficiently consistent). There are three stages TAN0 ... TAN3, of the type shown in figure 6, with equal capacitor C0 ... C3 (= capacitance C) representing the four equal coefficients. Components S0, S1, SF, CF and OA are as shown in figure 6, whilst two simple sample and hold circuits SW1, CH1, OA1, SW2, CH2, OA2 are included to sample the output (A₀ being applied to switches SW1, SW1) when conversion is completed, to eliminate any output transients during conversion. C F is equal to 64C for Vomax/V R (1 - 2 -N ) = 1. The switching waveforms A₀, A₁, A₂, A₃ are generated by means of the generator shown in figure 11. A square-wave oscillator OSC drives a non-overlapping phasing generator consisting of an invertor I1, cross-coupled NAND gates N1, N2, and inverters I2, I3 to produce pulses  ′ / o,  ′ / 1. A modulo 8 binary down-counter Z is clocked by  ′ / 1. The '1111' state is designated as an idle-state in which the counter is locked by an and-gate AND1 which decodes this state to an end of conversion pulse EOC and inhibits clock pulses via a switch SWI in the oscillation circuit. The generation of the required (2 w -1) = 15 pulses of the switching waveforms A₀ ... A₃ is indicated by an external pulse SOC (synchronous with the digital input data to be converted) which is applied to a paralled load input PE of the counter Z1 to load count '1110' into the counter. The counter is then decremented by pulses  ′ / 1 through its states to 000, during which period the counter states are decoded by inverters I4 ... I7 and and-gates AND2 ... AND4 to produce the pulses A₀ ... A₃ as illustrated in the sequence diagram in figure 12. The sixteenth pulse  ′ / 1 returns the counter to the '1111' state where it remains locked until a further start pulse SOC is received. Note that in this converter, pulses B i are not required (since the filter coefficients are all positive) but could of course be generated by a second counter and decoding logic similar to the arrangements for A i . A discrete component version of this converter can be constructed using amplifiers type LF353, CMOS analogue switches type CD4016, and standard CMOS logic circuits, although in practice an integrated circuit implementation is to be preferred. Typical capacitor values are C = 40pF and C F = 2700pF (with ± 0.2% of the nominal values) may be used.

Claims: An apparatus for producing a filtered analogue output signal from a digital signal in the form of a sequence of digital signal samples each having a plurality of bits comprising digital delay means (D0...DN-1) for producing further sequences of digital signal samples, each being a replica of the first sequence delayed with respect thereto by a respective delay period, and means for forming an analogue signal representing the sum of the mutually delayed signal samples weighted in accordance with a desired filter response, characterized in that the means for forming the analogue signal comprise a plurality of switched capacitor arrangements (CSAO...CSAN-1 or TAO...TAN-1), each connected to receive a respective one of the said sequences of digital signal samples; and in that each switched capacitor arrangement has at least one capacitor (CPO...CPw-1 or C) and switching means (CSO...CSw-1) for supplying, in dependence on the states of bits of each received sample, charge thereto, such that the total charge received by the capacitor(s) of each switched capacitor arrangement depends on the value represented by that sample; the total charge of each switched capacitor arrangement being weighted to weigh the contribution of each switched capacitor arrangement to the analogue output by a factor corresponding to a respective one of a set of coefficients corresponding to the desired filter response; and common summing means (S0, S1, SIF or SF, CF, OA) for receiving the charges from all the switched capacitor arrangements and forming an analogue output sequence representing the sum of those charges. An apparatus according to Claim 1 characterised in that each switched capacitor arrangement has a plurality of capacitors (CPO...CPw-1) with values weighted according to the significances of respective bits of the samples. An apparatus according to Claim 2, characterised in that the capacitors in at least one of the switched capacitor arrangements differ in value from the corresponding capacitors in another of the switched capacitor arrangements, such as to weight the charges by factors corresponding to the said coefficients. An apparatus according to Claim 1 characterised in that each switched capacitor arrangement has a single capacitor (C) and switching means (CS1...CSw-1) for supplying, in dependence on the states of the bits of each received sample, charge to the single capacitor (C), the switching means being arranged to supply a predetermined quantity of charge to the capacitor a respective different number of times such that the charges supplied for respective bits of the sample are weighted according to the significances of those bits, thereby forming a total charge dependent on the value represented by the sample. An apparatus according to Claim 4, characterised in that the capacitor in at least one of the switched capacitor arrangements differs in value from the corresponding capacitor in another of the switched capacitor arrangements, such as to weight the charges by factors corresponding to the said coefficients.

Inventors: DA FRANCA JOSE DE ALBUQUERQUE, LEME CARLOS MEXIA DE ALMEIDA D, VITAL JOAO PAULO CALADO CORDEI, DA FRANCA, JOSE DE ALBUQUERQUE EPIFANIO, LEME, CARLOS MEXIA DE ALMEIDA DE AZEREDO, VITAL, JOAO PAULO CALADO CORDEIRO
Applicants: BRITISH TELECOMM, BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY
Application year: 1989
Main classification: H03H17
IPC codes: H03M1, H03H19, H03H17