Driving device and display system

Abstract: There is disclosed a display system provided with: A. a display panel provided with matrix electrodes composed of scanning lines and information lines; B. a first unit for transferring scanning line address information and image information corresponding to the writing into pixels of a scanning line; C. a second unit for delaying the transfer of the received image information and then latching the image information of a scanning line; D. a third unit for designating a scanning line based on the received scanning line address information, and storing the designation information of the designated scanning line; and E. a fourth unit for so controlling the second and third units, when the third unit designates a scanning line based on the received scanning line address information, as to synchronize the selective drive of the scanning line designated by the immediately preceding stored information for designating the scanning line with the drive of the information lines based on the image information latched by the second means, and to selectively drive the scanning line designated according to the scanning line address information within the period of the synchronization mentioned above.

Description: The present invention relates to a driving device for a display device equipped with matrix electrode structure, and in particular to a driving device for a ferroelectric liquid crystal display device and a display system utilizing the same. The ferroelectric liquid crystal display devices are driven by multiplexing drive methods as already proposed in the U.S. Patents US-A-4,655,561 of Kanbe et al., US-A-4,638,310 of Einriffe, US-A-4,715,688 of Harada et al., US-A-4,701,026 of Yazaki et al., US-A-4,725,129 of Kondo et al., and US-A-4,711,531 of Masubuchi et al. In these drive methods, a voltage signal of a pulse duration and a peak value sufficient for generating black or white display state in a pixel of a scanning line is applied within a period selected for scanning. Such voltage signals are applied in succession for each scanning line, and an image frame is formed by repeating such signal supply. Consequently, the above-mentioned driving methods have been associated with a drawback that the frame frequency becomes inevitably lower with the increase in the number of scanning lines. The above-mentioned drawback has been solved by driving methods proposed in the Japanese Laid-open Patent Sho 60-172029 of Kanbe et al., and the U.S. Patent US-A-4,770,502 of Kitajima et al. In these driving methods, after the pixels of a scanning line are simultaneously erased to black (or white) display state, signal writing to said pixels is conducted by the application of writing voltage signal, and at the same time the pixels of a scanning line to be written next are simultaneously erased. These methods allow to increase the frame frequency. In such methods, the selected periods for two scanning lines mutually overlap in such a manner that, while a scanning line is subjected to writing operation, the next scanning line is subjected to erasing operation. Consequently, if there is an interruption display (for example frame display drive, which is a scanning at regular intervals for forming a frame display) or a change in the display conditions due to a temperature change in the course of display drive, such interruption display or change of driving conditions is initiated after a scanning operation so that the scanning line to be selected next remains in the erased state. EP-A-0 308 927 discloses a display device in which serial image information is converted into parallel information, the parallel image information being stored in a memory before being displayed. The scanning lines are selected according to an address signal stored in an address signal memory. An object of the present invention is to provide a driving device not associated with the above-mentioned drawbacks. Another object of the present invention is to provide a driving device capable of providing a high frame frequency and enabling smooth transition to an interruption display drive. The present invention is featured by a driving device as set out in the appended claims. Fig. 1 is a block diagram of the driving device of the present invention; Figs. 2A to 2H are timing charts of a normal display operation; Fig. 3 is a detailed block diagram of a drive control circuit employed in the driving device of the present invention; Figs. 4A to 4H are timing charts thereof; Fig. 5 is a wave form chart of scanning signal in the normal display operation; Figs. 6A to 6I are timing charts in an interruption display drive; Fig. 7 is a wave form chart of scanning signal in said drive; Figs. 8A to 8I are timing charts when one-line partial rewriting is conducted consecutively; Fig. 9 is a wave form chart of the scanning signal in such state; Fig. 10 is a flow chart of the microprocessor in the normal display operation; and Figs. 11A to 11D are wave form charts of the driving voltage employed in the present invention. Now the present invention will be clarified in detail by embodiments thereof shown in the attached drawings. Fig. 1 is a block diagram of the driving device of the present invention, wherein provided are a delay circuit 1 for delaying the transfer of image information corresponding to the writing into the pixels on the scanning line; a drive control circuit 2 composed of a one-chip microcomputer; an address detection circuit 3 for detecting address information, for designating the scanning line, from the information from an internal graphic controller 11; a shift register 4 for serial-parallel conversion of the image information; a line memory 5 for storing image information corresponding to the writing into the pixels of a scanning line; and information signal generating circuit 6 for generating drives voltages based on the image information; a decoder 7 for decoding the scanning line address information detected by the address detection circuit 3 thereby designating the scanning to be selected; a memory 8 for storing the designated scanning line information from the decoder 7; a scanning signal generating circuit 9 for generating driving voltages for driving the scanning line designated by the designated scanning line information from the decoder 7 and the memory 8; and a display panel 10 equipped with matrix electrodes composed of scanning lines and information lines and ferroelectric liquid crystal. Fig. 2 is a timing chart of the driving operation. In the following there will be explained the function in the normal drive with reference to Figs. 1 and 2. The device of the present invention receives the image information and the scanning line address information from the graphic controller 11, by the hand-shake method. The microcomputer in the drive control circuit 2 indicates to the graphic controller 11 that reception of data is possible, by shifting a signal HSYNC to the L-level. Upon detecting the downshift of said signal, the graphic controller 11 transfer signals AH/DL and PD0 - PD7 (image information and scanning line address information) in synchronization with a clock signal CLK. Since the image information and the scanning line address information are transmitted through a same transmission channel, the AH/DL signal is used as the identification signal therefor. More specifically, the PD0-PD7 signal represents the scanning line address information or the image information respectively when said AH/DL signal is at the H- or L-level. Fig. 3 is a detailed block diagram of the drive control circuit 2 shown in Fig. 1, and Fig. 4 is a timing chart thereof. A microcomputer 31 serves to transfer the HSYNC signal to the graphic controller 11, receives the AH/DL signal, and controls the transmission of an AH/DL signal, a microcomputer trigger signal and a selection signal to a delay enable/trigger selection circuit 32. There are also provided a delay enable generating circuit 33, an address counter 34, a R/W signal generator 35, and a 1/2 frequency divider 36. The microcomputer 31 can select either the AH/DL signal or the microcomputer trigger signal for effecting the delay enable triggering. The selected signal is supplied to the delay enable generator 33, and said signal and a clock signal obtained by 1/2 frequency division of the clock signal CLK from the graphic controller to generate a delay enable signal which is supplied to the delay circuit. At the same time the address counter 34 is reset to renew the data in the memory. When the rewriting of the memory proceeds to a predetermined address, the address counter 34 sends a memory stop signal to the delay enable generator 33, whereby the memory enable signal is shifted to the H-level to terminate the function of the delay circuit 1. The circuit 2 enables the rewriting of the delay circuit without the information transfer from the graphic controller 11. In the normal drive, the selection signal supplied from the microcomputer 31 of the drive control circuit 2 to the delay enable/trigger selection circuit 32 is such that the AH/DL signal is used as the delay enable trigger signal. In a period T1 shown in Fig. 2, the microcomputer 31 maintains the HSYNC signal at the L-level, whereby the image information Ld (Ld0-7, Ld8-11, ..., Kd2552-2559) from the graphic controller 11 is transferred to the delay circuit 1 in synchronization with the clock signal CLK. At the same time the input information PD0-7 is supplied to the address detection circuit 3 for detecting the scanning address information (La0-7, La8-11, Ma0-7, ...). Thus the microcomputer 31 releases a drive start signal (line (b) in Fig. 1), thus latching the content of the shift register 4 in the line memory 5. Simultaneously the scanning line address information La is transferred from the address detection circuit to the decoder 7 and decoded therein to designate a line to be erased. Said period T1 corresponding to a horizontal scanning period 1H, or the time for rewriting a line. In a period T2, the drive is started by a drive start signal released from the microcomputer 31. In this state, the scanning line to be erased is designated by the decoder 7 (scanning line L in this example), and the pixels to be written in the scanning line (scanning line K in this example) are those set in the memory 8. Said lines L and K are simultaneously driven by the scanning signal generator 9. The driving voltage supplied to the scanning line L corresponds to an "erase phase" shown in Fig. 5, and that supplied to the line K corresponds to a "write phase" shown in Fig. 5. In Fig. 5 there are shown a selection signal with voltage levels V1, V2 and V3, and a non-selection signal with voltage 0. On the other hand, the microcomputer 31 shifts the HSYNC signal to the L-level, for receiving next information PD0-7 from the graphic controller 11. The image information Md is transferred to the delay circuit 1 as explained above, and the preceding image information Ld is transferred to the shift register 4. The address detection circuit 3 detects the scanning line address information Ma. Then the microcomputer 31 releases the drive start signal, thus latching the image information Ld of the shift register 4 in the line memory 5. At the same time, the scanning line address information Ma is transferred, in synchronization, to the decoder 7, and the designation of the scanning line L is set in the memory 8. Thus, in a period T3, the pixels on the scanning line M are erased, and the pixels on the scanning line L are rewritten into black or white according to the image information Ld stored in the line memory 5. Also the microcomputer 31 shifts the HSYNC signal to the low level whereby the image information Nd is transferred to the delay circuit 1, and the image information Md is transferred to the shift register 4. The address detection circuit 3 detects the scanning line address information Na, and, in response to the drive start signal, the designation of the scanning line N is set in the decoder 7 while the designation of the scanning line M is set in the memory 8. The normal drive is thus conducted in succession according to the above-explained procedure. Fig. 10 is a flow chart showing the control sequence of the microcomputer 31 in the above-explained procedure. In the following there will be explained the procedure of an interruption drive, for modifying the drive wave form in the course of a drive, or for a partial rewriting. Fig. 6 is a timing chart of this drive. It is assumed that the microcomputer 31 detects, in a period T1, the necessity for temperature compensation or for a frame drive. More specifically, the microcomputer 31 is equipped with a counter for counting the number of scan designation, and constantly compares said number with the number of scan designations at which the temperature compensation or the frame drive has to be conducted. Thus the microcomputer 31 can recognize, at the reception of the information LD0-7, the necessity for temperature compensation or frame drive. The address detection circuit 3 detects the scanning line address information La, and the delay circuit 1 stores the image information Ld. Thereafter, in response to the drive start signal, the image information Kd is set in the line memory 5, the scanning line address information La is set in the decoder 7, and the designation information of the scanning line K, designated in the period T1, is set in the memory 8. In the period T2, the writing is conducted in the scanning line K while the scanning line L is erased. In the device of the present invention, in order to prohibit the information transfer from the graphic controller 11, the microcomputer 31 maintains the HSYNC signal at the H-level. Then the delay enable/trigger selection circuit 32 of the drive control circuit 2 is switched from the AH/DL signal to the microcomputer trigger. In order to transfer, to the shift register 4, the image information Ld which remains stored in the delay circuit 1 because the scanning line L remains erased, the microcomputer 31 releases a delay enable trigger (microcomputer trigger) signal through a line (c) in Fig. 1. In response to said signal, the image information from the delay circuit 1 is transferred to the shift register 4 without reception of information from the graphic controller 11. The address detection circuit 3 does not detect the scanning line address information, and the microcomputer 11 releases a non-selection signal (line (a) in Fig. 1) indicating the absence of selection of all the scanning lines. Thus, in response to the drive start signal, the designation of all the scanning lines is set in the decoder 7. Also the designation of the scanning line L is set in the memory 8. The image information Ld is latched in the line memory 5. In the period T3, there is only conducted the writing of the scanning line L. There is not scanning line to be erased, as the decoder 7 sets, in the period T2, the non-selection signal which disables all the chip selections of the decoder 7. Also in said period T3, the next information is received from the graphic controller 11 and stored in the delay circuit 1. Then in a period T4, there is conducted the change in wave form or the frame drive. After said operation, the drive start signal is released to set the scanning line address information Ma in the decoder 7. In the memory 8 there is set the designation of non-selection for all the scanning lines. In a period T5, there is conducted preparation for re-starting the normal drive, and the scanning line M to be written after said re-start is erased, but the writing is prohibited. In a period T6 and thereafter, the normal drive with simultaneous erasure and writing is executed. Fig. 7 shows the driving wave form. In the following there will be explained the procedure when one-line partial re-writing is successively executed. Fig. 8 is a timing chart of said procedure. There is shown a case in which the scanning line L is successively designated. In the period T1 there is executed the normal drive, in which the scanning line address information La1 designating the scanning line L is detected. Then in response to the drive start signal, the scanning line address information La1 is set in the decoder 7, and the scanning line K, detected in the preceding period, is designated by the memory 8. In the period T2, the address detection circuit 3 detects the scanning line address information La2 designating the scanning line L same as that detected in the period T1. In the normal drive, in response to the drive start signal, the scanning line address information La2 is set in the decoder 7, while the scanning line address information La1 is set in the memory 8, whereby the erasure and the writing are conducted simultaneously on a same line. Thus the normal drive cannot be conducted in this case. However the microcomputer 31 stores the preceding address and compares it with the scanning line address information La2 detected in this period, and recognizes that a same scanning line has been designated twice in succession. In response to said recognition, the microcomputer 31 releases a non-selection signal, indicating the non-selection of all the scanning lines, instead of the scanning line address information La2, and said non-selection signal is set in the decoder 7 in response to the drive start signal. The scanning line address information La1 is set in the memory 8. In the period T3, there is only conducted the writing of the scanning line L, because of the function in the period T2. In the period T3, the microcomputer 31 prohibits the transfer of next information from the graphic controller 11, and supplies the scanning line address information La2, which is set in the decoder 7 in response to the drive start signal. The memory 8 stores the non-selection state for all the scanning lines. In the period T4, there is only conducted the erasure of the scanning line L. The next information is transferred in this period, so that the image information Ld2 is entered into the shift register 4. Also in response to the drive start signal, the image information Ld2 is set in the line memory 5 while the scanning line address information Ma is set in the decoder 7, and the memory 8 releases information designating the scanning line L. The normal drive is restored in the period T5. However, if the address is again La in the period T4, there is conducted, in the period T5, an operation same as that in the period T3. Fig. 9 shows the driving wave form. Figs. 11A to 11D show the scanning selection signal, scanning non selection signal, white and black information signals employed in the present invention. The sequence of the scanning selection signal is same as shown in Fig. 5. The broken line portion of the information signal shown in Fig. 11C or 11D indicates a part of the preceding information signal. In the present invention there may be employed a ferroelectric liquid crystal element disclosed, for example, in the U.S. Patent No. 4,639,089 of Okada et al., No. 4,709,994 of Kanbe et al., or No. 4,712,873 of Kanbe et al. As explained in the foregoing, there are provided a control device for prohibiting the input of the transferred information, a control circuit for enabling readout of the image information of at least a scanning line at an arbitrary time, and a circuit for selecting a non-selection state for all the addresses thereby interrupting the erasure of scanning line during the scanning period of a horizontal scanning line, whereby the scanning line to be selected next does not remain erased during the variation of the driving wave form or the frame drive. It is therefore rendered possible to prevent the presence of a black visible line, so that the correction of temperature characteristics, change of display mode or frame drive can be smoothly achieved in a display method in which at least two lines are simultaneously driven. Also there may be additionally provided a comparator for storing the preceding scanning line and comparing the same with the currently scanned line to achieve smooth drive in case one-line partial writing is required in succession, by switching from the erasure-writing simultaneous drive to the single-line drive. Also in the present invention, since the erased scanning line is memorized, there can be smoothly conducted for example interlaced scanning.

Claims: A driving device, comprising: matrix electrodes composed of scanning lines (K o , L o , M o , N o ) and information lines; an information line driving circuit having a serial-parallel converting circuit (4) and a first memory (5) for storing image information (Kd, Ld, Md, Nd) from said serial-parallel converting circuit (4); a scanning line driving circuit; and control means (2) for controlling said information line driving circuit and said scanning line driving circuit, said driving device being characterized in that said information line driving circuit further has a delay circuit (1) for delaying the transfer of image information (Kd, Ld, Md, Nd) to be written into pixels of a scanning line (K o , L o , M o , N o ) to said serial-parallel converting circuit (4), said scanning line driving circuit has a scanning line designating circuit (7) for generating scanning line information which designates a scanning line and a second memory (8) for storing the scanning line information generated by said scanning line designating circuit (7); said control means (2) controls said information line driving circuit and said scanning line designating circuit so that the image information (Kd, Ld, Md, Nd) stored in said first memory (5) which is used for Nth line scanning, the scanning line information from said scanning line designating circuit (7) which is used to designate a scanning line (K o , L o , M o , N o ) for (N+1)th line scanning, and the scanning line information stored in said second memory (8) which is used to designate a scanning line (K o , L o , M o , N o ) for Nth line scanning are synchronously output, and said scanning line information used to designate the scanning line (K o , L o , M o , N o ) for (N+1)th line scanning is output during outputting of the scanning line information for Nth scanning, and pixels on the scanning line designated by the scanning line information used to designate the scanning line (K o , L o , M o , N o ) for (N+1)th line scanning are erased, and pixels on the scanning line (K o , L o , M o , N o ) are written according to said scanning line information used to designate the scanning line (K o , L o , M o , N o ) for Nth line scanning and said image information (Kd, Ld, Md, Nd) stored in said first memory (5) used for Nth line scanning. A driving device according to claim 1, characterized in that said control means (2) further comprises means (32; 33) for controlling said information line driving circuit and said scanning line driving circuit, when the number of designations of the scanning lines (K o , L o , M o , N o ) reaches a predetermined value, so as to prohibit the transfer of image information (Kd, Ld, Md, Nd) to said delay circuit (1), and during the application of the writing voltage signals to the pixels of the scanning line (K o , L o , M o , N o ) designated according to the information from said second memory (8), to apply a non-selection signal to the other scanning lines (K o , L o , M o , N o ). A driving device according to claim 2, characterized in that said control means (2) comprises a counter (34) for counting the number of designations of the scanning lines (K o , L o , M o , N o ). A driving device according to claim 1, charcterized in that said control means (2) further comprises means (32, 33) for controlling said information line driving circuit and said scanning line driving circuit, in case the same scanning line (K o , L o , M o , N o ) is designated in succession, so as to prohibit the transfer of the image information (Kd, Ld, Md, Nd) to said delay circuit (1) and, during the application of the writing voltage signals to the pixels of the scanning line (K o , L o , M o , N o ) designated according to the information from said second memory (8), to apply a non-selection signal to the other scanning lines (K o , L o , M o , N o ). A driving device according to claim 4, characterized in that said control means (2) comprises means (31) for comparing the content of the entered scanning like address information (Ka, La, Ma, Na). A driving decive according to any of the preceding claims 1 to 5, characterized in that a ferroelectric liquid crystal is disposed between the scanning line (K o , L o , M o , N o ) and the information line. A display system, comprising: a display panel (10) comprising matrix electrodes composed of scanning lines (K o , L o , M o , N o ) and information lines; first means (11) for transferring scanning line address information (Ka, La, Ma, Na) and image information (Kd, Ld, Md, Nd) corresponding to the writing into pixels of a scanning line (K o , L o , M o , N o ); said display system being characterized by further comprising second means (1) for delaying the transfer of the image information (Kd, Ld, Md, Nd) received from said first means and then latching the image information (Kd, Ld, Md, Nd) of a scanning line (K o , L o , M o , N o ); and third means (7) for designating an erase scanning line (K, L, M, N) by decoding the received scanning line address information (Ka, La, Ma, Na) as a first signal and by out-putting the first signal to a scanning line generation circuit (9), for simultaneously storing said first signal into a memory (8) and for designating a picture scanning line by outputting a second signal previously stored into said memory (8) to said scanning line generation circuit (9). A display system according to claim 7, characterized in that said display panel (10) has a memory effect. A display system according to claim 7, characterized in that said display panel (10) comprises a ferroelectric liquid crystal. A display system according to claim 7, characterized in that said third means (7) further comprises means for effecting selective drive for uniformly erasing, in the period of said synchronization, the pixels of the scanning line designated according to said scanning line address information (Ka, La, Ma, Na). A display system according to claim 7, characterized by further comprising fourth means (2) for disenabling a signal designating the erase scanning line when the number of designated picture scanning lines reaches a predetermined value. A display system according to claim 7, characterized in that said third means (7) for designating an erase scanning line by decoding the received scanning line address information (Ka, La, Ma, Na) as a first signal and by outputting the first signal to a scanning line generation circuit (9), simultaneously for storing said first signal into a memory (8) and for outputting a second signal designating a picture scanning line previously stored into said memory (8) to said scanning signal generation circuit (9) during output of said first signal, and further comprising fourth means (2) for disenabling a signal designating the erase scanning line when the number of designated picture scanning lines reaches a predetermined value. A display system according to claim 7, characterized in that said third means (7) for designating an erase scanning line by decoding the received scanning line address information (Ka, La, Ma, Na) as a first signal and by outputting the first signal to a scanning line generation circuit (9), simultaneously for storing said first signal into a memory (8) and for designating a picture scanning line by outputting a second signal previously stored into said memory (8) to said scanning line generation circuit (9), and further comprising fourth means (2) for controlling said second (1) and third means (7) in a manner that the scanning line designated by a signal designating the erase scanning line is non-selectively driven when the designation of the same picture scanning line occurs in succession. A display system according to claim 7, characterized in that said third means (7) for designating (a) an erase scanning line by decoding the received scanning line adress information (Ka, La, Ma, Na) as a first signal and by outputting the first signal to a scanning line generation circuit (9), simultaneously for storing said first signal into a memory (8) and for outputting a second signal designating a picture scanning line previously stored into said memory (8) to said scanning signal generation circuit (9) during output of said first signal; and further comprising fourth means (2) for disenabling a signal designating the erase scanning line when the number of designated picture scanning lines reaches a predetermined value.

Inventors: INOUE HIROSHI, MIYAMOTO KATSUHIRO, INOUE, HIROSHI, MIYAMOTO, KATSUHIRO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1989
Main classification: G09G3
IPC codes: G09G3, G02F1