Semiconductor device having compound semiconductor fet of E/D structure with high noise margin

Abstract: The semiconductor device of the present invention includes a first transistor includes on one and the same substrate a first transistor having a first semiconductor layer with high-impurity density on which is provided a second semiconductor layer with low-impurity density, where the first semiconductor layer being of N type and having electron affinity greater than that of the second semiconductor layer, and is equipped with a control electrode provided on the second semiconductor layer and at least two ohmic electrodes that are electrically connected to the first semiconductor layer on both sides of the control electrode, and a second transistor having a third layer with low-impurity density provided on top of the second semiconductor layer on the first semiconductor layer, and is equipped with a control electrode provided on the third semiconductor layer and at least two ohmic electrodes that are electrically connected to the first semiconductor layer on both sides of the control electrode. Further, by setting the first semiconductor layers to be a P-type semiconductor havin the sum of the electron affinity and the energy gap smaller than the sum of the electron affinity and the energy gap of the second semi­ conductor layer, there can be obtained a semiconductor using holes as carriers. The semiconductor device described above can be manufactured by sequentially gorwing crystals of the first, second, and third semiconductor layers on the substrate, selectively removing the third semiconductor layer, forming the first transistor on the second semiconductor layer in the removed part, and forming the second transistor on the third semiconductor layer in the portion other than the removed part of the third semiconductor layer.

Description: The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a compound semiconductor field-effect transistor (FET) of E/D structure which can realize a direct coupled FET logic (DCFL) circuit with a high noise margin. In recent years, research and development on integrated circuits using compound semiconductor such as GaAs is being pursued vigorously with a view to increasing the speed of operation. In this connection it has generally been recognized that the so-called DCFL with E/D structure which is constituted by enhancement-mode FETs (E-FETs) and depletion-mode FETs (D-FETs) has low power consumption so that it is suited for increasing the level of integration, and moreover, has a high speed of operation. In fact, research and development is being engaged actively attempting to realize a DCFL circuit by the use of GaAs MESFETs. However, the conventional GaAs MESFET has a relatively low Schottky barrier height of about 0.75 V so that there has been a problem that it is not possible in reality to secure a sufficient operational noise margin of the circuit. In addition, because of the dispersion in the threshold voltage due to the use of ion implantation in forming E-FETs and D-FETs, there has been a problem that a sufficient operational noise margin of the circuit cannot be secured either. On the other hand, investigation of DCFL circuits using E type and D type high electron mobility transistors is also being pursued (see, for example, Technical Digest of GaAs IC Symposium, 1984, p. 125). However, in realizing a DCFL circuit of E/D structure by the use of high electron mobility transistors, it is usual to vary the film thickness of the n-type semiconductor layer with doped impurities, and further, selective crystal etching is required twice because of its recessed gate structure, so that there is a problem that the element characteristics tend to have a dispersion under the influence of the manufacturing processes. Further, in a DCFL circuit, in spite of a need for a large operational noise margin, the high electron mobility transistor has, due to its intrinsic structure, a semiconductor layer with doped impurities situated immediately beneath the gate electrode, so that it is essentially impossible to increase the forward breakdown voltage V f , of the gate, which makes an improvement of the noise margin difficult to achieve. Moreover, in the manufacturing method disclosed in the above-mentioned reference, dry etching for semiconductor layer is given after the gate part is opened, so that it is difficult to set dry etching conditions which satisfy simultaneously control of the width of the gate opening and protection against its damage. This is due to the circumstance that when an anisotropic treatment (here it is a vertical treatment) is attempted in order, for example, to restrain the width of the gate opening to a possible minimum and to suppress an increase in the parasitic resistance, it becomes necessary to intensify ionic etching which tends to give damages to the surface to be etched. Conversely, in order to suppress damages it becomes necessary to utilize reactive treatment by radicals instead of the ionic treatment in which case the treatment involved is isotropic so that the width of the gate opening becomes increased and reduction of the parasitic resistance becomes difficult. It is, therefore, an object of the present invention to provide a semiconductor device having a compound semiconductor FET of E/D structure which has high speed and possesses a large noise margin. A device according to the present invention is defined in Claim 1. The fundamental transistor in the semiconductor device of the present invention includes a heterojunction between the control electrode and the channel and the semiconductor material directly below the control electrode has high resistance as a rule, as disclosed in JP-A-62-209866, JP-A-62-248263 and JP-A-62-274783, so that it is possible to have both of the depletion layer modulation mode and the charge accumulation mode as its operational modes. Accordingly, the channel charge quantity that is controllable can be made large, the current driving capability can be improved, and is possible as a result to increase the speed of the element. Further, the voltage (V r ) at which the current between the control electrode and the ohmic electrode rises is high, and hence, the apparent Schottky barrier becomes high, so that the operational noise margin, for example, of an integrated circuit using a DCFL circuit can be increased. Moreover, since the channel aspect ratio can be chosen large, it is possible to suppress the short-channel effect, and can readily realize a high-performance short-channel element. The semiconductor device makes use of controllability of current threshold voltage of the element by adjusting in principle the film thickness of the high-resistance semiconductor layer in the surface of the element, so that it is possible, for example, to give action and effects which are intrinsic to the integration of enhancement mode and depletion mode element. In this case, the semiconductor layer whose thickness is to be adjusted is a high resistance semiconductor layer undoped with impurities, different from a high electron mobility transistor, variations in the current due to threshold voltage can be reduced substantially even for the variations in the surface film thickness that occur during various processes. In a device according to the present invention, it is possible to substantially increase the transconductance of the D-FETs by adding impurities in part of the surface on the D-FET side. Further, since it becomes possible in this case to increase the degree of freedom of independent control of the current threshold voltage of the D-FET, and the forward rising voltage V r of the gate is different for the E-FET and the D-FET, it becomes possible to realize two kinds of level shift diodes, enabling to expand the degree of freedom in circuit design. In addition, the method of improving the breakdown voltage of the high electron mobility transistor by the insertion of an undoped semiconductor layer in the surface is disclosed in H. Hida et al., IEEE Trans. Electron Devices, Vol. ED-33, No. 5, p. 601 (1986). Document JP-A 61 168 965 and patent abstract of Japan Vol. 10, no. 376 (E-414) [2433], Dec. 1986, discloses a device including a single channel layer common to a D-FET and an E-FET. The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a sectional view of the structure of the important parts of a first embodiment of the semiconductor integrated device not covered by the present invention; Fig. 2 is a sectional view of the structure of the important parts of the embodiment of the semiconductor integrated device of the present invention; Fig. 3 is a sectional view of the structure of the important parts of a further embodiment of the semiconductor integrated device not covered by the present invention; Fig. 4 is a sectional view of the structure of the important parts of a further embodiment of the semiconductor integrated device not covered by the present invention; Fig. 5 is a sectional view of the structure of the important parts of a further embodiment of the semiconductor integrated device not covered by the present invention; Fig. 6(a) to Fig. 6(c) are sectional views for illustrating a further embodiment not covered by the present invention; and Fig. 7(a) to Fig. 7(c) are sectional views for illustrating a further embodiment not covered by the present invention. (First Embodiment) Referring to Fig. 1, an undoped GaAs layer 1 with thickness of 500 nm (5000 Å) is provided on a semi-insulating substrate 9, an N-type GaAs layer 2 with thickness of 10 nm (100 Å) with high-impurity density of 2 x 10 18 cm -3 is provided on the GaAs layer and an undoped Aℓ 0.3 Ga 0.7 As layer 3 with thickness of 25 nm (250 Å) is provided on the GaAs layer 2. On the Aℓ 0.3 Ga 0.7 As layer 3 on the right-hand side, there is provided an undoped GaAs layer 4 with thickness of 25 nm (250 Å). On the Aℓ 0.3 Ga 0.7 As layer 3 on the left-hand side and on the GaAs layer 4 on the right-hand side, there are provided control electrodes consisting of WSi 6 and 7, respectively. On both sides of the respective control electrodes 6 and 7 high-impurity density regions 8 of N-type are provided reaching as far as the GaAs layer 1, with the high-impurity density regions 8 between the control electrodes 6 and 7 being in the mutually joined manner. The N-type high-impurity density regions 8 are formed by implanting silicon ions under the conditions of a dosage of about 5 x 10 13 cm -2 and an acceleration voltage of about 50 keV, and then giving a short heat treatment at 900°C. On top of the Aℓ 0.3 Ga 0.7 As layer 3 on both sides of the control electrode 6, there are provided ohmic electrodes 561 and 562 consisting of AuGe/Ni electrically connected to the high-impurity density regions 8, thereby forming an E-FET 201. On the GaAs layer 4 on both sides of the control electrode 7, there are provided ohmic electrodes 571 and 572 consisting of AuGe/Ni electrically connected to the high-impurity density regions 8, thereby forming a D-FET 202. The ohmic electrodes 562 and 571 are provided mutually joined together. The channel layers for the E-FET 201 and the D-FET 202 are offered by the GaAs layer 2 for both, and the current threshold voltage for each is adjusted by the presence or the absence of the GaAs layer 4. The representative performance indices of the E-FET 201 and the D-FET 202 of the first embodiment not covered by the present invention are as shown in Table 1 below. Performance Index E-FET 201 D-FET 202 Length of Control Electrode (Gate Length) Lg (µm) 1 1 Threshold Voltage Vt (V) 0.2 -0.6 Transconductance gm (mS/mm) 350 300 Gate Forward Turn-on Voltage Vr (V) 1.15 1 Gate Breakdown Voltage BVg (V) 8 8 Referring to Table 1, the forward turn-on voltage Vr for the gate is about 1V for both of the E-FET 201 and the D-FET 202, showing an improvement of about 0.4 V over the conventional GaAs MESFETs. In addition, the gate breakdown voltage is also about twice that of the conventional GaAs MESFET. Further, the transconductance gm which is the index of the high-speed performance of the semiconductor integrated device is also sufficiently large. An inverter with the DCFL circuit structure using the semiconductor integrated device of this embodiment and a ring oscillator using the inverter were fabricated. It was found that the oscillator showed a satisfactory result with a noise margin of about 0.4 V, a no-load gate delay time of 25 ps/s and a power consumption per gate of 0.6 mW. Further, it was confirmed that the oscillator operated satisfactorily at temperatures near 100°C and that the semiconductor device of the present invention possesses a sufficient operation noise margin for the circuit, working at high speed with low power consumption. It is to be noted that an N-type high-impurity density regions 8 were formed in the present embodiment by means of the ion implantation method. However, the regions may be formed by some other method, for example, a method in which an N-type high-impurity density semiconductor layer (for instance, N-GaAs layer) is selectively grown epitaxially by the use of the organometallic chemical vapor growth method (MOCVD method). (Embodiment of the present invention) Referring to Fig. 2, an undoped GaAs layer 21 with thickness of 500 nm (5000 Å) is provided on a semi-insulating substrate 9, an undoped Aℓ 0.3 Ga 0.7 As layer 22 with thickness of 100 nm (1000 Å) is provided on the GaAs layer 21 an undoped GaAs layer with thickness of 100 nm (1000 Å) is provided on the Aℓ 0.3 Ga 0.7 As layer 22, an N-type GaAs layer 2 with thickness of 10 nm (100 Å) with impurity density of 2 x 10 18 cm -3 is provided on the GaAs layer 2 and an undoped Aℓ 0.3 Ga 0.7 As layer 3 with thickness of 25 nm (250 Å) is provided on the GaAs layer 2. On the Aℓ 0.3 Ga 0.7 As layer 3 on the right-hand side, there is provided an N-type GaAs layer 24 with thickness of 10 nm (100 Å) and an impurity density of 2 x 10 18 cm -3 , and an undoped GaAs layer 25 with thickness of 10 nm (100 Å) is provided on the GaAs layer 24. On the Aℓ 0.3 Ga 0.7 As layer 3 on the left-hand side and on the GaAs layer 25 on the right-hand side, there are provided control electrodes consisting of WSi 6 and 7, respectively. On both sides of the respective control electrodes 6 and 7, there are provided N-type intermediate-impurity density regions 26, reaching the depth as far as the GaAs layer 23. On the outside of the intermediate-impurity density regions 26 provided on both sides of the electrodes 6 and 7, high-impurity density regions 8 of N-type are provided reaching even the GaAs layer 23 and to beyond the intermediate-impurity density regions 26, while the high-impurity density regions 8 between the control electrodes 6 and 7 are provided mutually joined. The high-impurity density regions and the intermediate-impurity regions 26 are fabricated as in the following. First, after depositing and treating WSi which is to become the gate metal, SiO 2 is deposited all over the surface to the thickness of 300 nm (3000 Å) by means of a CVD method, an anisotropic dry etching using gaseous CF 4 is applied to leave SiO 2 only on the sidewalls of the gate metal. Next, silicon ions are implanted with the dosage of about 5 x 10 13 cm -2 under the condition of acceleration voltage of about 5 keV. Then, after removing the SiO 2 sidewalls with an acidic solution, silicon ions are implanted again with the dosage of about 1 x 10 13 cm -2 under the condition of acceleration voltage of about 30 keV. Subsequently, a short heat treatment at 900°C is given. On top of the Aℓ 0.3 Ga 0.7 As layer 3 on both sides of the control electrode 6, there are provided ohmic electrodes 561 and 562 consisting of AuGe/Ni connected electrically to the high-impurity regions 8, forming an E-FET 201. On top of the GaAs layer 25 on both sides of the control electrode 7, there are provided ohmic electrodes 571 and 572 consisting of AuGe/Ni connected electrically to the high-impurity density regions 8, forming a D-FET 202. The ohmic electrodes 562 and 571 are provided mutually joined. The representative performance indices of the E-FET 201 and the D-FET 202 of the present embodiment are as shown in Table 2 below. Performance Index E-FET 201 D-FET 202 Length of Control Electrode (Gate Length) Lg (µm) 1 1 Threshold Voltage Vt (V) 0.2 -0.6 Transconductance gm (mS/mm) 350 400 Gate Forward Turn-on Voltage Vr (V) 1.15 0.9 Gate Breakdown Voltage BVg (V) 10 8 In the present embodiment, there are two channel layers 2 and 24 on the D-FET side, and the N-type GaAs layer 24 is provided so that the distances between the control electrode 7 and the channel layers 2 and 24 are short, gm of the D-FET is increased, which are more advantageous for increasing the speed of operation. Namely, to realize a high-speed integrated circuit, it becomes important to increase the speed of the basic integrated circuit in the interior and the input and output buffer integrated circuit. In particular, the latter condition requires a large load driving capability so that it is usually frequent to employ a D-FET with high gm value. Accordingly, an improvement of gm of a D-FET is effective for increasing the operating speed of the integrated circuit as a whole. Further, the forward turn-on voltage Vr of the gate becomes small compared with that of the first embodiment, differing substantially from Vr of the E-FET so that the formation of two level shift diodes become feasible. In other words, in order to give interchangeability with the voltage level of other integrated circuit such as an ECL circuit, there may occur a case of need for carrying out level shifting by the use of a BFL (buffered FET logic) circuit, for example, in which case it is usual to utilize the turn-on voltage Vr of the diode. It means in the case of the present embodiment that the degree of freedom of design can be improved since Vr values for the E-FET and the D-FET are different. Moreover, since the so-called LDD (lightly doped drain) structure is adopted by providing N-type intermediate-impurity density regions 26 in the vicinity of the control electrodes 6 and 7, the short-channel effect can be constrained and the gate breakdown voltage can be increased. In addition, since, a hetero-buffer layer 22 consisting of AℓGaAs is provided, the short-channel effect can be reduced and satisfactory characteristics can be secured even for an elements with short channels. Still further, an inverter with DCFL circuit structure and a ring oscillator using the DCFL circuit were manufactured using the semiconductor integrated device of the present invention. It was formed that there was obtained a satisfactory result with a noise margin of about 0.4 V, a no-load gate delay time of 25 ps/s and a power consumption per gate of 0.6 mW. In addition, the oscillator operated satisfactorily at high temperatures in the vicinity of 100°C, confirming that the semiconductor integrated device of the present invention has a sufficient noise margin of the circuit, and that it can be operated at high speed with low power consumption. It should be noted in the first and the second embodiments in the above that in order to suppress the step difference due to integration of the E-FET 201 and the D-FET 202 to a possible minimum, set the threshold voltages of both FETs to desired values, and further, to avoid spoiling the element performance, the following conditions are desirable to be satisfied. Namely, the impurity density be in the range of 5 x 10 17 - 5 x 10 18 cm -3 and the thickness be in the range of 5-50 nm (50 - 500 Å) for the GaAs layer 2, the impurity density in the range of 1 x 10 13 - 1 x 10 17 cm -3 and the thickness in the range of 5-100 nm (50 - 1000 Å) for the Aℓ 0.3 Ga 0.7 As layer 3, the impurity density in the range of 1 x 10 13 - 1 x 10 17 cm -3 and the thickness in the range of 5-100 nm (50 - 1000 Å) for the GaAs layer 4 and the impurity density in the range of 1 x 10 17 - 5 x 10 18 cm -3 and the thickness in the range of 5-50 nm (50 - 500 Å) for the GaAs layer 24. (Further Embodiment not covered by the present invention) Referring to Fig. 3, an undoped GaAs layer 101 with thickness of 500 nm (5000 Å) is provided on a semi-insulating substrate 111, an N-type GaAs layer 102 with thickness of 10 nm (100 Å) and an impurity density of 2 x 10 18 cm -3 is provided on the GaAs layer 101, an undoped Aℓ 0.3 Ga 0.7 As layer 103 with thickness of 20 nm (200 Å) is provided on the GaAs layer 102 and an undoped GaAs layer 104 with thickness of 5 nm (50 Å) is provided on the Aℓ 0.3 Ga 0.7 As layer 103. An undoped Aℓ 0.3 Ga 0.7 As layer 105 with thickness of 5 nm (50 Å) is provided on the GaAs layer 104 on the right-hand side, and an undoped GaAs layer 106 with thickness of 20 nm (200 Å) is provided on the Aℓ 0.3 Ga 0.7 As layer 105. Control electrodes 108 and 109 consisting of WSi are provided on the GaAs layer 104 on the left-hand side and the GaAs layer 106 on the right-hand side, respectively. On both sides of the control electrodes 108 and 109, there are provided N-type high-impurity density regions 110 reaching the GaAs layer 101, with the high-impurity density regions 110 between the control electrodes 108 and 109 being provided to be joined with each other. The N-type high-impurity density regions 110 are formed by giving a short heat treatment at 900°C after implantation of silicon ions under the conditions of a dosag of about 5 x 10 13 cm -2 and an acceleration voltage of about 50 keV. On top of the GaAs layer 104 on both sides of the control electrode 108, there are provided ohmic electrodes 781 and 782 consisting of AuGe/Ni, connected electrically to the high-impurity density regions 110, forming an E-FET 201. On top of the GaAs layer 106 on both sides of the control electrode 109, there are provided ohmic electrodes 791 and 792 consisting of AuGe/Ni, connected electrically to the high-impurity density regions 110, forming a D-FET 202. The ohmic electrodes 782 and 791 are provided joined with each other. The channels for the E-FET 201 and the D-FET 202 are offered by the GaAs layer 102. In the present embodiment, the surface of the E-FET 201 is constructed with a stable undoped GaAs layer 104 so that it is possible to reduce the ohmic resistance. The representative indices of the E-FET 201 and the D-FET 202 are as shown in Table 3 below. Performance Index E-FET 201 D-FET 202 Length of Control Electrode (Gate Length) Lg (µm) 1 1 Threshold Voltage Vt (V) 0.2 -0.6 Transconductance gm (mS/mm) 350 300 Gate Forward Turn-on Voltage Vr (V) 1 1 Gate Breakdown Voltage BVg (V) 8 8 Referring to Table 3, the forward turn voltage Vr of the gate is about 1V for both types of FETs, with an improvement of about 0.25 V over the conventional GaAs MESFETs. Further, the gate breakdown voltage is also about twice as large that of the conventional GaAs MESFET. The value of gm which is the index of the speed of the integrated device was also sufficiently large. An inverter with DCFL circuit structure using the semiconductor integrated device of the present embodiment, and a ring oscillator utilizing the inverter were fabricated. It was found from the measurement on the oscillator that a satisfactory result was obtained with about 0.35 V of the noise margin, a no-load gate delay time of 25 ps/s, and a power consumption per gate of 0.6 mW. Further, it was confirmed that the oscillator performed satisfactorily at high temperatures in the vicinity of 100°C, and that the semiconductor integrated device of the present invention has a sufficient operational noise margin of the circuit, and moreover, that it can be operated at high speed with low power consumption. Further, in the present embodiment, the N-type high-impurity density regions 110 were formed by ion implantation. However, the regions can also be formed by other method such as one in which N-type high-impurity density semiconductor layers (N-GaAs, for example) can be selectively grown epitaxially by means of the organometallic vapor growth method (MOCVD method). (Further Embodiment not covered by the present invention) Referring to Fig. 4, an undoped GaAs layer 121 with thickness of 500 nm (5000 Å) is provided on a semi-insulating substrate 111, an undoped Aℓ 0.3 Ga 0.7 As layer 122 with thickness of 100 nm (1000 Å) is provided on the GaAs layer 121, an undoped GaAs layer 123 with thickness of 100 nm (1000 Å) is provided on the Aℓ 0.3 Ga 0.7 As layer 122, an N-type GaAs layer 102 with thickness of 10 nm (100 Å) and impurity density of 2 x 10 18 cm -3 is provided on the GaAs layer 123, an undoped Aℓ 0.3 Ga 0.7 As layer 103 with thickness of 20 nm (200 Å) is provided on the GaAs layer 102, an undoped GaAs layer 104 with thickness of 5 nm (50 Å) is provided on the Aℓ 0.3 Ga 0.7 As layer 103 and an undoped Aℓ 0.5 Ga 0.5 As layer 105 with thickness of 10 nm (100 Å) is provided on the GaAs layer 104. An undoped GaAs layer 106 with thickness of 15 nm (150 Å) is provided on the Aℓ 0.5 Ga 0.5 As layer 105 on the right-hand side. Control electrodes 108 and 109 are provided on top of the Aℓ 0.5 Ga 0.5 As layer 105 on the left-hand side and on top of the GaAs layer 106 on the right-hand side, respectively. On both sides of the control electrodes 108 and 109, there are provided N-type intermediate-impurity density regions 124 reaching even the GaAs layer 123. On the outside of the intermediate-impurity density regions 124 on both sides of the control electrodes 108 and 109, there are provided N-type high-impurity density regions 110 reaching even the GaAs layer 123, and moreover, deeper than the intermediate-impurity density regions 124, and the high-impurity density regions 110 between the control electrodes 108 and 109 are provided joined with each other. The high-impurity regions 110 and the intermediate-impurity regions 124 are manufactured as in the following. First, after deposition and treatment of WSi which is to become the gate metal, SiO 2 is deposited to a thickness of 300 nm (3000 Å) all over the surface by CVD process, and SiO 2 is left only on the sidewalls of the gate metal by an anisotropic dry etching using CF 4 gas. Next, silicon ions are implanted under the conditions of dosage of about 5 x 10 13 cm -2 and an acceleration voltage of about 50 keV. Then, after removing the SiO 2 sidewalls using an acidic solution, silicon ions are implanted again under the conditions of dosage of about 1 x 10 13 cm -2 and an acceleration voltage of about 30 keV. Subsequently, a short heat treatment is given at 900°C. Ohmic electrodes 781 and 782 consisting of AuGe/Ni are provided on top of the Aℓ 0.5 Ga 0.5 As layer 105 on both sides of the control electrode 108, connected electrically to the high-impurity density regions 110, forming an E-FET 201. Ohmic electrodes 791 and 792 consisting of AuGe/Ni are provided on top of the GaAs layer 106 on both sides of the control electrode 109, connected electrically to the high-impurity density regions 110, forming a D-FET 202. The ohmic electrodes 782 and 791 are provided joined with each other. The representative insides of the E-FET 201 and the D-FET 202 of the present embodiment are as shown in Table 4 below. Performance Index E-FET 201 D-FET 202 Length of Control Electrode (Gate Length) Lg (µm) 1 1 Threshold Voltage Vt (V) 0.2 -0.6 Transconductance gm (mS/mm) 350 300 Gate Forward Turn-on Voltage Vr (V) 1.15 1 Gate Breakdown Voltage BVg (V) 10 10 In this embodiment, channels for the E-FET 201 and the D-FET 202 are provided by the GaAs layer 102, and the current threshold voltage is adjusted by the presence or absence of the semiconductor layer 106 above the layer 102. Further, since the control electrode 108 of the E-FET 201 is formed on the Aℓ 0.5 Ga 0.5 As layer 105 which has an energy gap greater than that of the GaAs layer, the forward rise voltage Vr of the gate is further raised compared with the case of Third Embodiment. Moreover, the control electrodes 108 and 109 are given the so-called LDD structure by providing N-type intermediate-impurity density regions 124 in their vicinity, so that the short-channel effect is suppressed and the gate breakdown voltage is increased also. Still further, a hetero buffer layer 122 consisting of AℓGaAs is provided so that the short-channel effect can be reduced and it was possible to obtain satisfactory characteristics even for elements with short channel length. In addition, an inverter with DCFL circuit structure using the semiconductor integrated device of the present embodiment, and a ring oscillator utilizing the inverter were fabricated. There was obtained a satisfactory result in which the noise margin was about 0.4 V, the no-load gate delay time of 25 ps/s and the power consumption per gate of 0.6 mW. Further, it was confirmed that the oscillator operated satisfactorily even at temperatures in the vicinity of 100°C, and that the semiconductor integrated device of this embodiment possesses a sufficient operational noise margin of the circuit, and it can operate at high speed with low power consumption. It should be noted that the ohmic electrodes 781 and 782 on the E-FET side are formed on the Aℓ 0.5 Ga 0.5 As layer 105. However, it is possible to form the electrodes on the GaAs layer 104 by removing the layer 105 in the region near the ohmic electrode. (Further Embodiment not covered by the present invention) Referring to Fig. 5, an undoped GaAs layer 101 with thickness of 500 nm (5000 Å) is provided on a semi-insulating substrate 111, an N-type GaAs layer 102 with thickness of 10 nm (100 Å) and impurity density of 2 x 10 18 cm -3 is provided on the GaAs layer 101, an undoped Aℓ 0.3 Ga 0.7 As layer 103 with thickness of 20 nm (200 Å) is provided on the GaAs layer 102 and an undoped GaAs layer 104 with thickness of 5 nm (50 Å) is provided on the Aℓ 0.3 Ga 0.7 As layer 103. An undoped Aℓ 0.3 Ga 0.7 As layer 105 with thickness of 5 nm (50 Å) is provided on the GaAs layer 104 on the right-hand side, an N-type GaAs layer 131 with thickness of 10 nm (100 Å) and impurity density of 2 x 10 18 cm -3 is provided on the Aℓ 0.3 Ga 0.7 As layer 105 and an undoped GaAs layer 132 with thickness of 5 nm (50 Å) is provided on the GaAs layer 131. A semiconductor layer 156 is formed by the combination of the GaAs layer 131 and the GaAs layer 132. Control electrodes 108 and 109 consisting of WSi are provided on top of the GaAs layer 104 on the left-hand side and on the GaAs layer 132 on the right-hand side. High-impurity density regions 110 of N-type are provided on both sides of the control electrodes 108 and 109 reaching even the GaAs layer 101, and the high-impurity density regions 110 between the control electrodes 108 and 109 are provided joined with each other. The N-type high-impurity density regions 110 are formed by a short heat treatment at 900°C after implantation of silicon ions under the conditions of a dosage of about 5 x 10 13 cm -2 and an acceleration voltage of about 50 keV. Ohmic electrodes 781 and 782 consisting of AuGe/Ni are provided on top of the GaAs layer 104 on both sides of the control electrode 108, connected electrically to the high-impurity density regions 110, forming an E-FET 201. Ohmic electrodes 791 and 792 consisting of AuGe/Ni are provided on top of the GaAs layer 132 on both sides of the control electrode 109, connected electrically to the high-impurity density regions 110, forming a D-FET 202. The ohmic electrodes 782 and 791 are joined with each other. The representative indices of the E-FET 201 and the D-FET 202 of the present embodiment are as shown in Table 5 below. Performance Index E-FET 201 D-FET 202 Length of Control Electrode (Gate Length) Lg (µm) 1 1 Threshold Voltage Vt (V) 0.2 -0.6 Transconductance gm (mS/mm) 350 400 Gate Forward Turn-on Voltage Vr (V) 1 0.9 Gate Breakdown Voltage BNg (V) 8 7 The D-FET 202 of the present embodiment has two channel layers 102 and 131 so that the value for gm is large compared with that of the embodiment described with reference to Fig. 3. Further, N-type GaAs layer 131 is provided on the D-FET 202 side so that the distances between the control electrode and the channel layers 102 and 131 are made short with an increased value for gm, making it advantageous for increasing the speed of operation. Namely, in order to realize a high-speed integrated circuit, it becomes important to increase the speed of the internal basic integrated circuit and to increase the speed of the input and output buffer integrated circuit. In particular, a large load driving capability is required for the latter purpose so that it is usually frequent to employ a D-FET with high gm value. Accordingly, an enhancement of gm of a D-FET 202 is effective for operating the whole integrated circuit at high speed. Further, the gate forward turn-on voltage Vr can be reduced compared with that of the embodiment described with reference to Fig. 3, being significantly different from V r for the E-FET 201, so that there arises a possibility of forming two level shift diodes. In other words, there may arise the necessity of executing level shifting by the use, for example, of a BFL circuit in order to realize interchangeability of the voltage level with other integrated circuit such as an ECL circuit, in which case it is usual to utilize the rise voltage V r of the diode. In the case of the present invention, V r values differ for the E-FET and for the D-FET so that it becomes possible to improve the degree of freedom in designing the circuit. It is to be noted in the embodiments described with reference to Figs 3-5 that in order to regulate the step difference between the E-FET 201 and the D-FET 202 due to device integration to a possible minimum, and yet to set the threshold voltages for both FETs to desired values, and further, to avoid spoilage of the element performance, it is desirable to satisfy the following conditions. Namely, the impurity density of the GaAs layer 102 is to be found in the range of 5 x 10 17 - 5 x 10 18 cm -3 and its thickness is to be found in the range of 5-50 nm (50 - 500 Å), the impurity density of the Aℓ 0.3 Ga 0.7 As layer 103 in the range of 1 x 10 13 - 1 x 10 17 cm -3 and its thickness in the range of 5-100 nm (50 - 1000 Å), the impurity density of the GaAs layer 104 in the range of 1 x 10 13 - 1 x 10 17 cm -3 and its thickness in the range of 1-50 nm (10 - 500 Å), the impurity density of the Aℓ 0.3 Ga 0.7 As layer 105 in the range of 1 x 10 13 - 1 x 10 17 cm -3 and its thickness in the range of 5-50 nm (50 - 500 Å), the impurity density of the GaAs layer 106 in the range of 1 x 10 13 - 1 x 10 17 cm -3 and its thickness in the range of 5-100 nm (50 - 1000 Å) and the impurity density of the GaAs layer 131 in the range of 1 x 10 17 - 5 x 10 18 cm -3 and its thickness in the range of 5-50 nm (50 - 500 Å). In the above embodiments, description has been presented in conjunction with semiconductor devices that utilize electrons as the carriers. However, the present invention is similarly applicable to the case of utilizing holes as carriers. Therefore, embodiments of semiconductor integrated devices that utilize positive holes are carriers will be described next. (Further Embodiment not covered by the present invention) The sectional view for the important parts of the semiconductor integrated device of the present embodiment is similar to that of Fig. 1. Namely, in Fig. 1, use are made respectively of an undoped GaAs layer with thickness of 500 nm (5000 Å) as the semiconductor layer 1 on a semi-insulating substrate 9, a P-type Ge layer with thickness of 10 nm (100 Å) and impurity density of 2 x 10 18 cm -3 as the semiconductor layer 2, an undoped Aℓ 0.3 Ga 0.7 As layer with thickness of 25 nm (250 Å) as the semiconductor layer 3, an undoped Ge layer with thickness of 25 nm (250 Å) as the semiconductor layer 4, AuZn as the ohmic electrodes 561, 562, 571 and 572, and WSi is used for the control electrodes 6 and 7. In addition, the P-type high-impurity density regions 8 are formed by a short heat treatment at 900°C after implantation of beryllium ions under the conditions of a dosage of about 5 x 10 13 cm -2 and an acceleration voltage of about 50 keV. In the present embodiment, analogous to the case of utilizing electrons as carriers, there was observed an improvement, especially in the forward turn-on voltage Vr of the gate, over the conventional GaAs MESFET. Further, it was confirmed that the semiconductor device in accordance with this embodiment possesses a sufficient operational noise margin and that it can be cperated at high speed with low power consumption. The present embodiment is what will form a pair with the semiconductor device of the first embodiment that utilizes electrons as carriers. However, considering the principle of the present invention it is obvious that it is feasible to obtain a semiconductor integrated device utilizing holes as carriers that corresponds to the embodiment described with reference to figure 2. (Further Embodiment not covered by the present invention) The sectional view for the important parts of the semiconductor device of the present embodiment is analogous to that of Fig. 3. Namely, in Fig. 3, use are made respectively of an undoped GaAs layer with thickness of 500 nm (5000 Å) as the semiconductor layer 1 on a semi-insulating substrate 11, a P-type Ge layer with thickness of 10 nm (100 Å) and impurity density of 2 x 10 18 cm -3 as the semiconductor layer 102, an undoped Aℓ 0.3 Ga 0.7 As layer with thickness of 20 nm (200 Å) as the semiconductor layer 103, an undoped Aℓ 0.3 Ga 0.7 As layer with thickness of 5 nm (50) Å as the semiconductor layer 105, an undoped GaAs layer with thickness of 20 nm (200 Å) as the semiconductor layer 106, AuZn as the ohmic electrodes 781, 782, 791 and 792, and WSi as the control electrodes 108 and 109. Further, the P-type high-impurity density regions 110 are formed by a short heat treatment after implantation of beryllium ions under the conditions of a dosage of about 5 x 10 13 cm -2 and an acceleration voltage of about 50 keV. In the present embodiment, an improvement especially with respect to V r over the conventional GaAs MESFET was obtained analogous to the case of using electrons as carriers. Further, it was confirmed that the semiconductor integrated device of this embodiment possesses a sufficient operational noise margin for the circuit, and that it can be operated at high speed with low power consumption. The present embodiment is what will form a pair with the embodiment described with reference to figure 3 of the semiconductor device that utilizes electrons as carriers. However, considering the principle of the present invention, it is obvious that semiconductor devices having holes as carriers that correspond to the embodiment of the present invention are feasible. In the embodiments described in the above, use was made of GaAs, AℓGaAs and Ge as semiconductor materials, but it is also possible to use other semiconductor materials such as InGaAs, InAℓAs, InP, GaSb, InSb and Si. It is to be noted that in order to suppress the leak current after current cut-off and to suppress malfunctions and power consumption of the integrated circuit, the impurity density of the high-resistance buffer layer (semiconductor layer below the channel layer) is desirable to be less than 1 x 10 16 cm -3 for an impurity with the same conductivity type as that of the channel or less than 5 x 10 17 cm -3 for an impurity with the opposite conductivity type. (Further Embodiment not covered by the present invention) Referring to Fig. 6(a), an undoped GaAs layer with thickness of 500 nm (5000 Å) as the semiconductor layer 1 on a semi-insulating substrate, an N-type GaAs layer with thickness of 10 nm (100 Å) and impurity density of 2 x 10 18 cm -3 as the semiconductor layer 2, an undoped Aℓ 0.5 Ga 0.5 As layer with thickness of 25 nm (250 Å) as the semiconductor layer 3 and an undoped GaAs layer with thickness of 25 nm (250 Å), are grown sequentially by molecular beam epitaxial (MBE) method. Next, the region which is to become the D-FET is masked with a photoresist 31, the undoped GaAs layer 4 is removed selectively by dry etching with a mixed gas 32 of CCℓ 2 F 2 and He, as shown in Fig. 6(b), to form the region of E-FET. In this case, use is made of isotropic etching conditions which have low self bias voltage and give small damages to the device. Next, the photoresist 31 is removed, WSi is deposited by sputtering and it is treated by dry etching as shown in Fig. 6(c). Then, silicon ions 43 are implanted under the conditions of a dosage of about 5 x 10 13 cm -2 and an acceleration voltage of about 50 keV, and a short heat treatment at 900°C is given. Subsequently, AuGe/Ni is deposited as ohmic electrodes are deposited and alloied by heat treatment. Finally, wirings between the elements are given, completing the manufacture. The standard deviation σ Vt of the threshold voltage Vt of the elements obtained by the present invention was a satisfactory value of about 20 mV. Further, a circuit manufactured with DCFL circuit structure gave a confirmation that it possessed a satisfactory performance similar to that of the first embodiment. Moreover, uniformity and reproducibity of elements were also excellent. (Further Embodiment not covered by the present invention) Referring to Fig. 7(a), an undoped GaAs layer with thickness of 500 nm (5000 Å) as the semiconductor layer 101 on a semi-insulating substrate, an N-type GaAs layer with thickness of 10 nm (100 Å) and impurity density of 2 x 10 18 cm -3 as the semiconductor layer 102, an undoped Aℓ 0.3 Ga 0.7 As layer with thickness of 20 nm (200 Å) as the semiconductor layer 103, an undoped GaAs layer with thickness of 5 nm (50 Å) as the semiconductor layer 104, an undoped Aℓ 0.3 Ga 0.7 As layer with thickness of 5 nm (50 Å) as the semiconductor layer 105 and an undoped GaAs layer with thickness of 20 nm (200 Å) as the semiconductor layer 106, are grown sequentially by means of the MBE method. Next, the undoped GaAs layer 106 is removed selectively by means of dry etching with a mixed gas 142 of CCℓ 2 F 2 and He using photoresist 141 as a mask on the region to become a D-FET, to form the region for an E-FET, as shown in Fig. 7(b). In this case, use is made of isotropic etching conditions having low self-bias voltage and giving small damages to the device. Next, the Aℓ 0.3 Ga 0.7 As layer 105 in the region for the E-FET is removed with phosphoric acid etching solution. After removal of the photoresist 141, WSi is deposited by the sputtering method, and treated with the dry etching method. Then, silicon ions 143 are implanted under the conditions of a dosage of about 5 x 10 13 cm -2 and an acceleration voltage of about 50 keV, and a short heat treatment at 900°C is given. Subsequently, AuGe/Ni is deposited as ohmic electrodes and alloyed by heat treatment. Finally, wirings are given between the elements, completing the manufacture of the device. The standard deviation σVt of the threshold voltage Vt of the elements was a satisfactory value of about 20 mV. Further, manufacture of a circuit using the DCFL circuit structure confirmed that the circuit possesses a satisfactory performance. Moreover, the uniformity and the reproducibility of the element characteristics were excellent. It should be noted that the Aℓ 0.3 Ga 0.7 As layer 105 for the E-FET region was removed using a phosphoric acid solution. However, WSi may be deposited and treated by leaving the semiconductor layer as is. In this case, there is obtained an improvement of V r . Further, in the latter two embodiments it is possible to use a mixed gas which is a combination taken from a group of gases such as O 2 , Cℓ 2 , CCℓ 4 , CBrF 3 , CF 4 , SiCℓ 4 , SF 6 , HCℓ and HB r , as a gas 32 or 142 for dry etching. Moreover, tartaric acid, ammonium fluoride solution or the like may be used in place of the dry etching gases 32 and 142. Moreover, these embodiments represent manufacturing methods of semiconductor integrated devices which use electrons as carriers. However, it is obvious by considering the principle of the present invention that these are similarly applicable, as a rule, also to the manufacture of semiconductor devices that utilize holes as carriers.

Claims: A semiconductor device having an enhancement-mode FET (201) and a depletion-mode FET (202), said semiconductor device comprising: a semiconductor substrate (9, 21, 22, 23); a first semiconductor layer (2) provided on said semiconductor substrate; a second semiconductor layer (3) provided on said first semiconductor layer; said second semiconductor layer having a first upper surface portion and a laterally adjacent second upper surface portion, said first upper surface portion having laterally adjacent second, first and third parts, said first part intervening between said second and third parts; a first control electrode (6) provided on said first part of said first upper surface portion of said second semiconductor layer; first and second electrodes (561; 562) of said enhancement-mode FET (201) provided respectively on top of said second and third parts of said first upper surface portion of said second semiconductor layer and forming ohmic contacts to respective portions of said first semiconductor layer under said second and third parts; a fourth semiconductor layer (24) formed on said second upper surface portion of said second semiconductor layer; a third undoped semiconductor layer (25) formed on said fourth semiconductor layer (24), said third semiconductor layer having laterally adjacent, fifth, fourth and sixth surface parts, said fourth surface part intervening between said fifth and sixth surface parts; a second control electrode (7) of said depletion-mode FET (202) provided on said fourth surface part of said third semiconductor layer; and third and fourth electrodes (571; 572) of said depletion-mode FET provided respectively on top of said fifth and sixth surface parts of said third semiconductor layer and forming ohmic contacts to respective portions of said first and fourth semiconductor layers under said fifth and sixth surface parts ; wherein said first semiconductor layer (2) is either N-type with high impurity density and has an electron affinity greater than that of said second semiconductor layer or said first semiconductor layer (2) is P-type with high impurity density and has a sum of electron affinity and energy gap smaller than the sum of electron affinity and energy gap of said second semiconductor layer, wherein said second semiconductor layer is an undoped semiconductor layer, and wherein said fourth semiconductor layer (24) is a high impurity density semiconductor layer of the same impurity type as said first semiconductor layer. The device as claimed in claim 1, wherein said semiconductor substrate includes, at an interface with said first semiconductor layer, a high-resistance buffer layer (23). The device as claimed in claim 1 or 2, wherein said second and third electrodes (562, 571) are electrically connected with each other. The device as claimed in claim 2 wherein said first semiconductor layer is N-type, said device further comprising first and second N-type high impurity density regions formed in contact respectively with said first and second electrodes and extended from the surface of said second semiconductor layer to said high-resistance buffer layer and third and fourth high-impurity regions formed in contact respectively with said third and fourth electrodes and extended from the surface of said third semiconductor layer to said high-resistance buffer layer. The device as claimed in claim 2, wherein said semiconductor substrate further comprises a fifth undoped semiconductor layer (22) underlying said high-resistance buffer layer (23), said fifth semiconductor layer having an electron affinity smaller than that of said high-resistance buffer layer.

Inventors: HIDA HIKARU, HIDA, HIKARU, HIDA, HIKARU C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: H01L27
IPC codes: H01L27, H01L21