Neuron architecture

Abstract: Neuron architecture in which input analog data is applied in parallel to a plurality of neuron units (Fig. 2; Fig. 4 U1 to U5) in a time division manner. The analog input data is multiplied (3) by digital weight data which can be changed in accordance with the data of the interconnection between units. The product of the time division analog input data and the digital weight data are added in an integrator (4). While the sum of the products is output with regard to the present result, the previous sum of the product is output through a non-linear function forming means (6) simultaneously with the present data, thereby enabling operations for the sum of product in a neuron unit in an intermediate layer (e.g. U1, U2, U3) simultaneously with operations in a neuron unit in an output layer (e.g. U4, U5) and thereby providing outputs in a pipe-line manner. When a first neuron unit (e.g. U1) in a layer produces an output (y1) on an analog bus (A), a second neuron unit (e.g. U2) in the same layer is able to produce an output (y2) such that the outputs (y1, y2, y3) of the first layer are produced on the output analog bus (A) in a time division manner. An analog neuron unit or chip includes a plurality of operational amplifiers. The offset thereof is cancelled by offset cancelling means (8). The above analog neuron unit may be used to provide an intermediate layer and an output layer, so that a neuron system is provided which operates in the form of a layered structure (Fig. 4). One layer comprising a plurality of neuron units (U1, U2, U3) can be repeatedly used by feeding back the output of one layer to the input of another layer to form a neuron system with a layered structure.

Description: The present invention relates to neuron architecture for processing signal information. A neuron or neural network includes a plurality of neuron units which are interconnected to process signal information. Each neuron unit is a processor which combines multiple inputs to which the processor applies different weights or connection strengths. The weights may be stored in a memory and adjusted in a desired manner. A neural network can be utilized for pattern recognition of a character image, or voice pattern recognition, control of a robot in machine control, applications for expert systems in knowledge processing, compression and decompression of images in signal processing and so on. By connecting the neuron units in the network, the neuron units can perform superparallel processing and data processing of highly developed technology in which a learning function can be achieved. Therefore, neural networks are expected to be used widely. At present, neural networks are executed by simulation software, using personal computers. However, as the size of the network increases, the software becomes more complex and the processing time increases. It is foreseeable that the neuron units could be made of hardware, but as the number of inputs and the size of the memory increase, the cost and complexity of such hardware increases significantly. When a neural network is realized in the form of an integrated circuit, it becomes important to consider a system of interconnecting or linking respective neuron units or respective processing units with other units, a system of determining weights, a large scale circuit, a highly accurate circuit and a high speed processing system. The problems in developing such integrated circuitry will be seen in the following brief description of known neural networks. Figure 1 shows a conventional layer-type neural network. Each unit 1A, representing a neuron unit, is connected (1B) by a connection or arc for a synapse connection. Units I1 to I5 are for an input layer, units H1 to H10 are for a hidden layer, and units O1 to O4 are for an output layer. Each of the units I1 to I5 in the input layer is connected in common to each of the units H1 to H10. For example, unit I1 is connected to all units H1 to H10. As stated here, the neural network circuit is formed of several layers. A neural network utilizes a rule of learning through an error back propagation algorithm by changing the weight of the connection from the output layer to the input layer so that error between a teacher signal and the output signal at the output layer can be minimized. Namely, upon learning, an appropriate value is given as a weight in the connection, for example, and if the output value produced by the network is not the value of the object, the weight value can be changed so as to decrease the error. In the neural network,all the units in one layer are connected to each unit in another different layer and the strength of connection is determined by changing the weights between the connections of two units. It is difficult to realize a large-scale neural network which requires a lot of units and many connections between units. When a neuron unit is constructed with an operational amplifier in the respective processing units within the neuron units, it has the problem of offset voltage of the operational amplifier. Namely, for zero input voltage, a small voltage *V is produced as an output voltage. Therefore, a large-scale highly accurate neural network cannot be constructed. In the learning process using the neural network, it is necessary to change the weight of the synaptic connection. Therefore, a highly accurate neural network cannot be constructed using a voltage-control-type resistor. Considering this and under such background, learning and problem solving by the neural network has been executed by a simulation using a sequential computer in the prior art. Thus, a large-scale neural network made by using hardware has not been realized. The object of the invention is a neuron architecture as set out in claim 1, and a neuron network comprising said architecture as set out in claim 24. An embodiment of the present invention can provide for execution of a time division analog input and output process by using an analog neuron circuit with an offset-cancellation function, which can decrease the number of connections of respective units as well as can change the weights. An embodiment of the present invention can provide a neuron network including a plurality of neuron units which are operated sequentially within a layer, so that they produce outputs to a bus connected to the layer in a time division multiplexed manner. An embodiment of the present invention can provide for performance of an input operation to a neuron unit which performs sum of products of input signals with weights, simultaneously with the output operation from the neuron unit, thereby executinq a pipe line operation. An embodiment of the present invention can provide a neuron network of a layered type, or a feedback type, by using a neuron architecture. An embodiment of the present invention can provide for increased operation speed of a neuron network. An embodiment of the present invention can provide a neuron network which processes multiple signals on common buses. One embodiment of the present invention provides a neuron architecture comprising a plurality of first neuron units arranged sequentially, for producing respective output signals in a time division multiplexing manner, a common bus, connected to said first plurality of neuron units, for sequentially transferring said respective output signals of said first neuron units in a time division multiplexing manner, and second neuron units, connected to said common bus, for receiving the output signals from said first neuron units in a time division multiplexing manner. Another embodiment of the present invention provides such a neuron architecture employing a linked control including means for receiving a linked input control signal from a previous neuron unit and outputting a linked output control signal to the next neuron unit, and a control block for transmitting a first linked control input signal CSo to a first neuron unit and receiving a last linked control output signal CSn from a last neuron unit, whereby a linked control input signal is input to a neuron unit and after an output operation from the neuron unit is completed, the unit produces a linked output control signal. A further embodiment of the present invention provides such a neuron architecture comprising a layered structure neural network including a plurality of analog neuron units comprising each a multiplying unit for providing products of the input values and weight data corresponding to the input, adding means for summing the output of said multiplying unit, non-linear function operating means for performing a threshold value calculation function corresponding to the output from said adding means, first storing means connected to the adding means for storing a first intermediate value of an input pattern from the previous stage circuit, and second storing means connected to the non--linear operating means for storing a second intermediate value to be transmitted to the following stage circuit, whereby during the time period when the result of the calculation of the second intermediate value is outputted to the following stage, the first intermediate value is calculated simultaneously, thereby to provide a pipe line processing. A further embodiment of the present invention provides such a neuron architecture having a neural network of a layer structure for connecting a plurality of neuron units to each other, comprising a single layer unit set means for forming a unit set of a single layer by providing a plurality of neuron units for providing the product of time division analog signals and digital weight data, means for performing an integration by adding the products into a capacitor in a time division multiplexing manner, thereby providing an output voltage through the non linear output function in a time division multiplexing manner, feedback means for feeding back the output of said single layer unit set means to the input unit of the same single unit set means, control means for performing a time division multiplexing of an analog signal from respective units outputted from said single layer unit set means and executing a control for using said single layer unit-means through said feedback means in a time division multiplexing manner, whereby said single layer unit set means used in a time division multiplexing manner equivalently provides a layer-structure neural network. A further embodiment of the present invention provides such a neuron architecture having a neuron network for connecting a plurality of neuron units to each other comprising unit set means for producing a product of an input analog signal and digital weight data, and for performing an integration by adding the product to a capacitor in a time division multiplexing manner and producing a voltage through a non-linear output function, feedback means for feeding back an output of said unit set means to the input part of the same unit set means, and control means for providing the analog signal outputted from respective units of said unit set means in a time division multiplexing manner and controlling said unit set means to be used in a time division multiplexing manner, through said feedback means. A further embodiment of the present invention provides such a neuron architecture comprising an apparatus for speeding up a continuous multiplication, comprising D/A converter means for multiplying time division analog data having irregular positive and negative value by time division serial digital data having irregular positive and negative values, sign operating means for performing a sign operation to selectively invert or non-invert the sign of the analog data to enable the operation result to be output at the reference voltage terminal of the D/A converter, and control means for first applying an input sign bit of the digital data to said sign operation means and then applying said digital data to the data terminal of said D/A converter. Reference is made, by way of example, to the accompanying drawings, in which:- Figure 1 is a diagram showing a prior art neural network of a layered type, Figure 2 is a block diagram of a neuron unit according to the present invention, Figures 3A and 3B show explanatory views of a general neuron unit, Figure 4 shows a diagram showing a neural network of a layered type according to the present invention, Figures 5A and 5B show transmission waveforms of the neural network according to the present invention, Figure 6 shows a diagram of an input block of a neuron unit of the present invention, Figure 7 shows a diagram of a multiplication block of a neuron unit of the present invention, Figure 8 represents a diagram of an addition block of a neuron unit of the present invention, Figure 9 shows a diagram of a sample/hold block of a neuron unit of the present invention, Figure 10 shows a diagram of a sigmoid function generator of a neuron unit of the present invention, Figure 11 is a diagram of the output block of the present invention, Figure 12 is a detailed circuit of an embodiment of a neuron unit of the present invention, Figure 13 is a detailed circuit of another embodiment of a neuron unit of the present invention, Figure 14 is a timing chart showing a sample/hold operation of the circuit shown in Figure 12, Figure 15 is a detailed circuit of the sigmoid generator shown in Figure 12, Figure 16 is a timing chart of the circuit shown in Figure 12, Figure 17A is a diagram showing a connection of the neuron units for an explanation of a chaining operation, and Figure 17B shows a relation between a chain control signal and an operation of the respective processing units. Figure 18 is a timing chart of a connection of the neuron units shown in Figure 17B, Figure 19 is a timing chart of a connection of the neuron units of Figure 16, Figure 20A is a block diagram of a neuron unit of the present invention for explaining a pipe line operation, and Figure 20B is another block diagram of neuron units of the present invention for explaining a pipe line operation, Figure 21 is a timing chart of the block diagram of Figure 20B, Figure 22 is a diagram showing a block diagram of a neural network of the present invention for explaining a pipe line operation, Figure 23 is a block diagram of another embodiment of a neural network of the present invention, Figure 24 is a timing chart of the embodiment shown in Figure 23, Figure 25 is a block diagram of a neural network of a layered type which is equivalent to the neural network shown in Figure 23, Figure 26 is a timing chart of the embodiment of Figure 23, Figure 27 is a block diagram of a further embodiment of a neural network of the present invention, of a feedback type, Figure 28 is a timing chart of the embodiment shown in Figure 27, Figure 29 is a block diagram of a neural network of a feedback type according to a further embodiment of the present invention, Figure 30 is a timing chart of the embodiment shown in Figure 29, Figure 31 is a detailed circuit of the embodiment of the neural network of the layered type shown in Figure 23, Figures 32A and 32B are timing charts of the embodiment shown in Figure 31, Figure 33 is a detailed circuit of the embodiment of the neural network of the feedback type shown in Figure 27, Figures 34A and 34B is a timing chart of the embodiment shown in Figure 33, Figure 35A is a block diagram of a still further embodiment of a neuron unit of the present invention, and Figure 35B is a detailed block diagram of the embodiment shown in Figure 35A, Figure 36 is a timing chart of the embodiment shown in Figure 35B, Figure 37 is a block diagram of a digital data control circuit of the embodiment shown in Figure 35B, Figure 38 is a block diagram of another digital data control circuit of the embodiment shown in Figure 35B, and Figure 39 is a block diagram of a total neural network. Figure 2 shows a block diagram of a neuron unit comprised in the neuron architecture of the present invention, and thus indicates structure of respective neuron units in a neural network formed by interconnecting neuron units. Figure 2 shows input block 2, which receives an analog voltage which is outputted from a plurality of neuron units in a previous stage (not shown in Figure 2) in a time division multiplexed manner. Multiplying block 3 executes a switching of the kind of time division multiplexed analog input signal by using a sign bit (weighted input) of digital weight data supplied from an external circuit. Multiplying block 3 then selects the path of the weighted current converted from the voltage value of the time division multiplexed analog signal by selecting the numeral bits of the digital weight data. Next, it provides the products of the voltage value of the time division multiplexed analog signal and digital weight data to adding block 4 for performing an integration operation by supplying a product of the time division multiplexed analog signal and the digital weight data to a capacitor. Sample and hold block 5 samples the output of the adding block 4. Non linear function producing block 6 forms a non linear output which approximates a desired relationship. Output block 7 produces an analog output voltage to be supplied to the next stage, in a time division manner and at an appropriate timing. Offset canceling block 8 cancels the offset voltage of a circuit constituting the above respective blocks 2, 3, 4, 5, 6 and 7 when the input signal is at zero. A neural network of the present invention performs a time division multiplexing of the outputs from the neuron units in the previous stage. The number of neuron units corresponds to the number of pulses in a unit of time. The outputs constitute the product of the analog signal and digital weight data using the multiplying block 3. The neural network also provides an offset canceling circuit, determines the weight, and can be made in a large scale circuit with high accuracy. Figure 3A is a block diagram of a neuron unit as in the present invention. The neuron unit is an element for processing an element corresponding to the respective nodes of the neural network, and is called a unit. The quantity which holds a weight is added to the respective connections. This weight is a parameter representing the strength of mutual connection between units, and the weight wih designates a connection from the unit h to the unit i or the weight of the connection. The learning of the network is usually realized by changing this weight. The internal state of all the units in the neural network is called a state of the network; xi designates an internal state called an internal active level within respective units. Respective units receive the weighted input from the unit in the previous stage and calculate the total, and the appropriate non-linear function f is applied to the total. As shown in Figure 3A, the neuron units applies the following processing to the output yh from the other neuron units, that is, the other unit, yi = f(xi) where yh is the output of unit h, yi is the output of unit i, Wih is the weight of the link between unit i and unit h, f is a sigmoid or a non-linear function ( is the threshold value). A neural network is formed by connecting these units in a network. When respective units determine the next new state based on the total input, namely, the output, it follows a sigmoid function. The sigmoid function obtains the output yi when the total xi of the input is obtained as shown in the following equation. yi = 1 /(1 + exp(-xi)) The sigmoid function becomes closer to 1 as shown in Figure 3B when the input becomes larger and the form of the function graph changes in accordance with . There are various learning methods which use neural networks, for example, error correcting methods. According to these methods, a certain weight pattern corresponding to a connection is applied to the network, and when the error is large the weight of the connection is corrected. Repetition of this process finally provides the correct weight data. When the pattern at timing T is input, the weight Wih is changed so that the error becomes small if the solution of the unit at the final output layer is not the desired one. Thus, a learning process is performed. When the network outputs the same result as the correct solution in the learning process, the connection is not changed. If the network produces 0 when the correct solution is "1", the connection of the unit is increased by for example, a 1 and the output of the network is corrected so that the output becomes 1. Thus, it is very important to the learning process that the weight Wih can be changed with discretion. The weight of the connection is corrected such that the difference between the output from the network and the correct solution becomes small. In a neural network comprising a complete graph in which all the units in the network are connected to other units, or in a neural network comprising a graph of the complete connection type in which respective units in one layer are connected to all the units in the layer in the next stage, the number of interconnection between the units are very large. This makes a large-scale neural network difficult to construct. Interconnection between the units must be decreased. A single wire connects unit pulses of different voltages and transmits them from the previous stage unit to the following stage unit in a time division manner. The amplitude of the voltage is transmitted in accordance with a weight, thereby enabling an integrated circuit to be constructed in a form which does not use a complete connection type graph. This enables many units to be connected in an equivalent manner. The present invention performs a time division processing for the analog voltage or for use in transmission between units. The time division processing is explained by referring to the drawing. Figure 4 shows the structure of a neural network according to the present invention. U1, U2 and U3 are the units in the previous stage, and U4 and U5 are the units at the following stage. The signals y1, y2 and y3 outputted from respective units in the previous stage are connected to bus "A", which is connected to units U4 and U5 in the following stage. Similarly, the signals y4 and y5 outputted from units U4 and U5 in the following stage are commonly connected to bus B. Therefore, the units in the previous stage are connected to the units in the post-stage through bus A only. This greatly decreases the wiring, thus, greatly increasing the possibility of realizing a neural network as a hardware circuit. When the signal is transmitted from the units in the previous stage to the units in the following stage, the analog pulse voltages with an amplitude corresponding to the weight are transmitted in a time division manner. Figure 5A shows a transmission waveform of a neural network according to the present invention. Figure 5A shows the signal on bus "A" in the neural network shown in Figure 4 and Figure 5B shows the signals on bus "B" of the output line. The voltage output from unit U1 in the previous stage is positive and has a large amplitude. It provides voltage with an amplitude y1 and a period Δt. A negative voltage with an amplitude y2 is output from unit U2; y3 is the output voltage from unit U3 and it has a positive pulse value. The positive signal means that the neuron in the neural network is excited and the negative signal means that it is suppressed or inhibited. When these time division signals are supplied to unit U4 in the following stage, unit U4 outputs to bus "B" an excited pulse with an amplitude of y4 and a duration of Δt. Thereafter, after a small delay and in the next timing, unit U5 in the following stage provides on bus "B" a pulse with an amplitude of y5. Therefore, in the present invention, a transmission between neurons is conducted in the form of a time division multiplexing analog signal. Figure 6 is a block diagram of an input block of the neuron unit shown in Figure 2. The input signal is a time division analog signal outputted from a plurality of units in the previous stage. The input has an infinite input impedance and "0" output impedance enabling it to provide a unity gain amplifier, namely, buffer 9. In the present invention, this input unit has a path of an offset canceling function. When an offset control signal is supplied by offset canceling control block 10, "0" voltage is compulsorily input to buffer 9 through offset canceling generation block 11 and an offset voltage is produced as the output from the operational amplifier at various portions connected at the next stage. The offset can be canceled in accordance with a later described function. Figure 7 is a block diagram of a multiplying block of the neuron unit. Respective time division analog signal pulse voltages outputted from the input unit of Figure 6 are entered into positive-negative switch circuit 12, which switches the positive excited voltage or negative suppressed voltage in accordance with the code bit (sine bit) of the digital wave data to be input to D/A converter 13. From MSB to LSB of the numeral value, a bit of digital wave data is input to D/A converter 13 and the voltage output from the positive and negative switching circuit 12 is applied to the resistors of the R-2R type provided within D/A converter 13. Therefore, the weight current corresponding to the numeral bit flows through the resistor R-2R method. As a result, the output from D/A converter 13, the product of the analog signal and digital weight data is formed to provide the output produced from buffer 14. The recording of the function of this multiplying unit, and the weight between neurons can be changed in this invention and it is possible to dynamically change the characteristic of a neural network and learn something by the neural network in accordance with external control. Figure 8 shows a block diagram of an adding unit of the neuron chip. The result of the multiplication unit in Figure 7, namely, the product of the time division multiplexing analog signal and digital weight data, is input to integration apparatus 16. In the present invention the input signals are voltages of different amplitudes and these input signals are supplied in a time division manner. Therefore, in accordance with control by a time division adding control block 15, the product of analog signal and digital weight data is stored as a sum thereof in a capacitor of an integrating apparatus 16 of the next stage in accordance with a control of a time division adding control block 15. Further, the voltage of the capacitor is reversed by a switch in accordance with a command of the offset canceling control block 17. By subtracting an offset voltage produced upon the "0" input voltage from the result of the addition of the actual input, the offset voltage is canceled. This circuit maintains an accuracy of the network. Figure 9 is a block diagram of a sample holding block of the neuron chip according to the present invention. The output of the integrating apparatus shown in Figure 8 is input to the sample threshold block 18 in Figure 9 and the value of the output of the integrator is held in the capacitor, thereby performing an offset canceling function. In accordance with a control of the offset canceling control block 20, the offset voltage of an operational amplifier produced in the circuit in the next stage is canceled. Figure 10 is a block diagram of a sigmoid function generating circuit of the neuron chip according to the present invention. The sum of the products of the analog signals subjected to the sample hold operation in the sample hold block in Figure 9 and the digital weight data, is input to the sigmoid function circuit 21. The present invention accurately forms the sigmoid function by an approximation operation by the segmented linear function using an analog signal and determines whether or not the signal should be passed through the sigmoid function under the control of the non-linear circuit selecting control block 22. The present invention can realize a quantizing apparatus which is very close to the sigmoid function, by using an approximating function by a segmented linear function using the analog signal, to provide a high-accuracy and high-capability circuit. Figure 11 shows a block diagram of the output unit of the neuron chip according to the present invention. In the present invention the analog voltage of the time division analog signal is transmitted between the units of a neural network. Therefore, the output controlled input signal inputted from the output control block 23 controls the output voltage produced by the sigmoid function of Figure 10 such that it is outputted by time division analog output block 24 at an appropriate time. To control the time interval between units, an output control signal is transmitted to the outside. As transmission between units is carried out by the transmission of the time division multiplex analog signal, the neuron network need not form a complete-connection-type graph. Therefore, the system of the neuron network is extremely simple. Figure 12 shows make up the unit of the neuron chip shown in Figure 2 in detail. The unit of the present invention comprises input block 2, multiplying block 3, adding block 4, sampling/holding block 5, non-linear function block 6 and output block 7. The input block 2 comprises offset canceling producing circuit 11 and unity gain buffer 9. Unity gain buffer 9 feeds back the output of its operational amplifier to the minus terminal thereof and input voltage is applied to the plus terminal. The data input is a pulse signal of a time division analog signal. OC represents an offset control signal. When this control signal is "1" the analog switch 26 is turned on and "0" voltage is compulsorily applied to the unity gain buffer 9. On the other hand, when offset control signal OC is "0", the analog switch 26 is turned off and another analog switch 25 is turned on, and the data is inputted to unity gain time buffer 9. Namely, when offset control signal OC is "1", "0" volts is compulsorily applied to the unit of the neuron chip, thereby canceling the offset voltage produced in the output of the operational amplifier of the circuit in the following stage. Analog switches 25 and 26 control a switching of the OC signal in a positive phase or in a negative phase. This phase control prevents the circuits from being turned on simultaneously to each other. Hereinafter, this will be referred to as stating that the "OC" is subjected to phase control. Positive and negative switching circuit 12 is formed by combining an amplifying block in cascade form. The amplifying block comprises an input resistor (10 kΩ) and feedback resistor (10 kΩ) to provide 10/10' =1 times the voltage in a reversed manner. The sign of the analog voltage is determined depending on whether the signal passes through one or two stages of the amplifying block. The control voltage is a sign bit( SIGN ) of the digital weight data and this sign bit is connected to the gate of MOS switches 27 and 30. The control signal of sign bit( SIGN ) is also subjected to a phase control. When the sign bit( SIGN ) is 1, the input voltage from the input block is reversed by the amplifying block including amplifier 31A in the first stage as switch 30 turns on and it passes through the amplifying block including amplifier 31B in the following stage as the switch 27 is turned on, thereby providing a positive phase signal. Where the sign bit( SIGN ) is 0, switch 29 is turned on by the reverse circuit 28. Then, as the switches 27 and 30 are turned off, the input signal from the input block is applied to the minus terminal of operational amplifier 31B at the post stage through switch 29. Therefore, an operational amplifier with resistor 32 in the previous stage and resistor 33 for feedback of the operational amplifier constitute an amplifying block which is a unity gain inverter. Namely, the input of the input unit is formed to be positive when the sign bit is negative, and vice versa. This provides a voltage according to whether the synapse connection is excited or suppressed. An output from the positive and negative switching circuit 12 is supplied to point, namely, a reference voltage terminal 35 of R-2R-resistor circuit network of D/A converter 13. The D/A converter of the R-2R system will now be explained. The internal switch is turned on or off depending on the digital weight data from MSB to LSB. When the digital value is 1, the current flows through switch 35 into an imaginary ground 37' of operational amplifier 36. The imaginary ground 37' of operational amplifier 36 is controlled to have the same voltage as the plus terminal of the amplifier 36. Thus, the plus terminal of the amplifier 36 is grounded so that the imaginary ground 37' is imaginary 0. In a D/A converter, R represents 10 kΩ and 2R represents 20 kΩ. A currents flow resistor 2R regardless of the state of the switch. It is determined based on the value of the digital data, whether or not the weight current flowing through the resistor 2R (20 kΩ) flows toward the imaginary ground 37'. When the current flowing through the right-most resistor 2R is determined to be I, the vertical current flowing 2R corresponding to LSB located second from the right is provided as (2R x i)/ 2R =I by dividing the voltage applied to the right-most resistor 2R by 2R. Therefore, the current 2i flows to the horizontal right-most resistor R. The voltage 2R x I + R x 2I is applied to the vertical resistor third from the right and the voltage is divided by 2R to provide the current 2I. Therefore, similarly the currents through the vertical resistor 2R (20 kΩ) become 4I, 8I, 16I, ..., and therefore increases at a rate of the second power of I. The data from MSB to LSB determines whether or not the weight current of the second power of I flows into the minus terminal of the operational amplifier. Therefore, the current corresponding to the digital weight data flows into the imaginary ground within an amplitude of the second power of I. As the input impedance of the operational amplifier is infinite, and the current flowing toward the imaginary ground 37' flows through a feedback resistor 37 of operational amplifier 36, the output voltage Vout of the D/A converter is as follows, V out = -(Es/2n) x (D0+ 2xD1 + 2 2 xD2 + ... + 2 n-1 xDn-1) where Es is the input voltage, D0 is the LSB and Dn-1 is the MSB. Namely, the output of the multiplying block 3 is the value obtained by multiplying the input voltage by a weight. The weight coefficient is controlled by the digital value from MSB to LSB. On the other hand, adding block 4 uses a mirror integrator for respective products of the time division multiplexing analog signal and the digital weight data in a time division manner, to carry out an accumulation and an adding operation. Sampling/holding block 5 performs sampling/holding of the addition result. Adding block 4 is an integrator comprising resistor RT 38 and capacitor CT. The input unit of the adding block 4 has time division adding control block 15 and when the sample/hold signal is 1, the output of the multiplying block 3 is input to an imaginary ground 39' of operational amplifier 39. When the S/H (sample/hold) signal is 0, the inverter 40 turns on switch 41 and the output of the multiplying block is connected to ground through the resistor RT. Thus, the input is not added to the capacitor CT of adding block 4 when the S/H signal is 1. The output voltage of the multiplying block 3 is input to the minus terminal of operational amplifier 39 through a resistor RT 38. The current obtained by dividing the input voltage by resistor RT 38 is input to capacitor CT through an imaginary ground to perform an integration. Thereafter, when the S/H signal becomes 0 and multiplying block 3 is disconnected from adding block 4, multiplying block 3 can multiply the next signal by the weight data. The circuit 42 of an integration circuit including capacitor CT is provided with an offset canceling function by using four switches. When the sampling hold signal is 0 and offset control signal OC is 1, the switches 43 and 44 are turned on and switches 45 and 46 are turned off, thereby reversing the voltage stored in the capacitor CT. When the offset control signal OC is 0, an input voltage is applied to the data input terminal of data input block 2 and the corresponding output of multiplying block 3 is applied to capacitor CT through resistor RT. Then, switches 45 and 46 are turned on and the capacitor CT has a positive polarity on the side connected to the minus terminal 39' of the operational amplifier 39 and has positive polarity on the side connected to the output of operational amplifier 39. When the offset control signal OC becomes 1 and the capacitor which stores the voltage including in the offset voltage is reversed, data input is compulsorily made 0. In this case, if the offset does not exist even if the input signal is transferred through positive and negative switching circuit 12 and multiplying block 3, the output of the D/A converter becomes 0. However, as the operational amplifiers are employed and the offset voltage is activated, the offset voltage is added to capacitor CT with a reversed voltage and is consequently stored. As a result the offset voltage is canceled. The offset voltage occurring after the capacitor CT receives the input signal is canceled by changing offset control signal OC to "1" to change the polarity of capacitor CT. When offset control signal OC is 0, input voltage is applied to the data input DATA-INPUT and the corresponding output from the multiplying block is applied to the capacitor CT through the resistor RT. The present invention achieves an offset canceling function in an equivalent manner by reversing the polarity of the capacitor CT. After the offset is canceled, the offset control signal OC becomes 0 and the capacitor returns to its original state. Switch 47 is controlled by a reset signal. When the reset signal is received, the voltage of the capacitor CT is made 0 and the output of the adding block is compulsorily 0 as it is a resetting operation. This offset control signal OC is also subjected to phase control. The output of adding block 4 is supplied to a sample holding block 5 in which the output of adding block 4 is stored in capacitor Ch through switch 48 when the phase-controlled sample hold control signal S/H out is 1. When the S/H out signal is 1, a control signal of switch 50 is turned to 0 by inverter 54' and if one terminal of capacitor Ch is not grounded, the signal of a final output data is applied to capacitor CR through switch 51. Namely, the final output signal at that time is fed back to the lower side of capacitor Ch. Therefore, capacitor Ch stores the voltage obtained by subtracting the final output data from the output of the adding block 4. At this time switch 52 is turned on and a plus terminal of operational amplifier 53 is compulsorily 0, thereby causing the final output data to be an offset voltage. Therefore, capacitor Ch stores the voltage obtained by subtracting the offset voltage from the output of the adding block 4 beforehand. On the other hand, where the S/H out signal is 0, switches 49 and 50 are turned on and the lower side of capacitor Ch is grounded. As a result, the voltage stored in capacitor Ch is applied to the plus terminal of the unity gain operational amplifier 53 through switch 49. The offset component is already subtracted and the offset component is canceled. The output of the operational amplifier 53 is input to the sigmoid function block 6 through operational amplifier 53. As described above, when the S/H control signal is turned to 1, switch 48 is turned on and capacitor Ch receives the difference between the output value from the adding block and the final output value. As, at this time, switch 51 is turned on, 0 volts are compulsorily applied to the operational amplifier 53. At this time, DATA-OUTPUT produces an offset voltage ΔV through the sigmoid function block 6 and operational amplifier 56. The offset voltage is applied to the lower side of capacitor Ch through switch 51. Therefore, when the S/H out control signal is 0, namely, switch 49 is turned on and switch 52 is turned off, the voltage stored in the capacitor Ch is finally outputted through amplifier 53 and sigmoid function block 6 as the value obtained by subtracting the offset voltage data V from the output of the adding unit 4. When the S/H out signal is turned to 1, the offset voltage formed at this timing becomes ΔV. As a result, the offset voltage is canceled. The non-linear functional block for forming a sigmoid function block comprises non-linear circuit selection circuit 22. The phase control SEL SIG signal is turned to 1, switch 55 is turned on and the output of the sigmoid function block 6 is applied to operational amplifier 56. However, when SEL SIG signal is 0, it forms the control signal of switch 58 which is made 1 through inverter 57, and the output of the sigmoid function is cut. The output voltage of the sample and hold block 5 is directly input to operational amplifier 56 without going through a sigmoid function. In this case, the neuron unit shown in Figure 12 can be used for an adaptive filter or for a linear neuron network and further it becomes easy to be tested as to its operation characteristic. Operational amplifier 56 is basically a unity gain operation amplifier for directly feeding back the output to the minus terminal, and is operated as a buffer. Therefore, this acts as a buffer in order to make the output impedance 0. Output block 7 is connected to time division output block 24 and output control block 23. When CS in is "1", switch 59 is turned on and switch 51 is turned on. The final output operational amplifier 56 outputs the final output at data output DATA-OUTPUT, which is then fed back to the minus terminal of the operational amplifier 56. The final output value is simultaneously input to sample/hold block 5. On the other hand, when CS in is 0, switch 60 is turned on and switch 61 is turned off. Therefore the output of amplifier 56 is not produced on a DATA-OUTPUT data line. However, as switch 60 is turned on to provide unity gain buffer voltage, the following operation of operational amplifier 56 is not disturbed, but is carried out. Output control circuit block 23 determines whether the output pulse voltage is transmitted by control signal CS in for a daisy chain operation. CS in is outputted as CS out through a delay circuit 23' and the timings of the output analog signals from other adjacent neuron units in the same layer is determined. Therefore, the present invention transmits an analog signal in a time division manner from output block 7. This does not conflict with other output signals from other neuron units. In accordance with control signals CS in and CS out , phase control shown in Figure 13 is realized by forming offset cancellation OC, sign SIGN , sample hold S/H, sample hold S/H out , sigmoid selection signal SEL SIG, DG change signal CSI in Figure 12 by two signals namely OC0 and OC1, PN and minus PN, SH11 and SH10, SH21 and SH20, minus SIGN and SIGN, and CS and minus CS, respectively. One control signal is formed by two signals comprising a positive phase and a negative phase, and is shifted by shifting the phase of the respective signals so that the positive phase of the control signal does not turn the switch on at the same time as the negative phase of the control signal turns on a different switch. The Rf connected to the output terminal of D/A converter 13 makes a feedback signal from operation amplifier 36 to be matched with an operation speed of the D/A converter and D/A converter 13 receives digital input from DT terminal. Parts in Figure 13 which are the same as in Figure 12 are given the same numbers. Therefore, their explanation is omitted. Figure 14 shows a timing chart for an integrator. The data clock DCLK and weight clock WCLK are basic operation clocks. When data clock DCLK is high, a high-speed weight clock WCLK is outputted during a half period of the data clock DCLK. Weight clock WCLK is a synchronizing clock for inputting serial weight data to the integrator. Data clock DCLK is a basic clock for processing an analog input signal. Synchronizing signal SYNC can achieve synchronization of respective analog neuron units within respective layers. The operation of the output voltage of the integrator is shown by a triangular waveform in the lower part of the drawing. The integration waveform is controlled by a pulse signal of sample/hold control signal S/H. During the period of high sample/hold control signal S/H, an integration is carried out. Namely, a charge is applied to capacitor CT of the integrator path. During the period when the sample/hold control signal S/H pulse is high, this charge is gradually accumulated in the capacitor CT in order to increase the voltage. When the sample/hold control signal S/H pulse is low, the charging operation is terminated. Therefore, during the scope of the integration integral time, only the charging period is of importance. Thus, the pulse width of the sample/hold control signal is controlled to expand or compress the scope of the integration period. Therefore, even if the input signal is the same, the output of the integrator becomes the charge voltage Va when the sample/hold control signal S/H has a pulse width P and it becomes the charging voltage Va' when the sample/hold control signal S/H has a pulse width W. When the sample/hold control signal S/H is low, and the offset control signal OC is raised the polarity of the capacitor CT of the integrator is changed and the integration output, to which an offset component is added, is reversed. When the offset control signal OC is high and the sample/hold control signal S/H is also high, the offset voltage Vb (Vb') is added to the capacitor CT. When the S/H signal becomes low again, and off-set canceling signal becomes low, then the polarity of the capacitor is again reversed to have an original polarity and the integral output value Va - Vb (Va' - Vb') in which the offset component is canceled is subjected to a sample/hold operation. After the output of the integrator is reversed the polarity of the output of the integrator is returned to its original state. Figure 15 is a transistor circuit for realizing the sigmoid function. The sigmoid function designates continuous and monotonically decreasing function and does not exclude a linear function. The transistor circuit comprises, for example, six units each comprising a current mirror circuit, differential amplifier and resistors. In Figure 15, transistors 343, 356, 378, 390, 298 and 314 and the transistors therewith constitute a differential amplifier. A group of transistors connected to respective collector sides of the differential amplifiers form current mirror circuit, respectively. A collector current flowing through a left transistor of the differential amplifier is an output current. The current mirror circuit produces an output after changing a direction of the current. The current flows into resistor 336 connected to the output V0 and resistor 336 converts the current into a voltage. As a driving capacity of this sigmoid function circuit is insufficient, the output thereof is connected to an operation amplifier having a high impedance. A circuit positioned at an input side of transistors 337 and 339 forms a bias circuit. A segmented linearization method is utilized to realize a sigmoid function. Namely, a curve of a sigmoid function can be expressed by six segments corresponding to the outputs of six units 1 to 6, as the respective outputs of six units have different slopes. A slope in the respective segments corresponding to each of the outputs of units 1 to 6 in a sigmoid function circuit which is constructed according to a segment linearization method is determined by a ratio of emitter resistor 344 to output resistor 336. The emitter resistor of the transistor 343 also affects the slope in the respective segments for the sigmoid function. The gain of the respective differential amplifiers are different. A breaking point at which a segmental linear curve changes a slope is determined by saturation characteristics of the respective differential amplifiers. The saturation characteristics of the respective differential amplifiers differ. The characteristics of respective amplifiers are selected such that the value of the total sum of the current outputted from the respective amplifiers represent a sigmoid function at an output point V0. Transistor 345 and resistor R1 forms a current source. Transistor 346 and resistor R2, and transistor 353 and resistor R3 are respectively current sources which supply the same value of the current. In other words, the resistance of the resistors are determined such that the same value of a current flows. As the collector of transistors 345 and 346 is connected, the sum current flows through a crossing point of terminals of resistors 344 and 347. The collector currents of transistors 343 and 348 become the same when the current mirror circuit is balanced. Transistor 351 is provided to improve current mirror characteristics of transistor 351. Transistor 350 is formed of a diode-connection. To change a direction of a current by a current mirror circuit means that there are a case where a current is drawn in from an output terminal and a case where a current is drawn out to an output terminal. As shown in Figure 15, a current flows outwardly from a collector of transistor 351 of the current mirror circuit. Although it seems that there are many transistors in a lower part of Figure 15, the transistors whose emitters and collectors are respectively connected at the same point are the same ones. For example, transistor 358 is the same as transistor 360 and these transistors 358 and 360 are the same as transistor 345. Transistors 359 and 361 are the same and correspond to transistor 346. Transistors 368 and 369 are the same and correspond to transistor 353. The same is applied to the other transistors. As stated above, the sigmoid function circuit comprises six circuit units each of which enables an operational amplifier with a constant current source to change a direction of a current in accordance with the positive and negative polarity of the output voltage, the constant current source being driven by the same current. Transistors 337 and 338 are for level shift and transistors 330 and 327 are also level shifts. The level shift circuit makes an operation scope to be the same regardless of the positive and negative polarities of the sigmoid function. Transistor 352 is for correction so that a collector current of transistor 351 is made equal to that of transistor 353. The same function is conducted by transistors 367, 385, 287 and 307. The plus and minus terminals of sigmoid function block 6 of Figure 12 correspond to the terminals + in and - in of the sigmoid circuit of Figure 15 which form inputs of operation amplifiers after subjecting to level shifting. The timing chart of the present invention will be explained. Figure 16 is a timing chart for a unit found in the present invention. D-SYNC and D-CLK are synchronization signals. W-CLK is a timing signal for providing a digital signal to the D/A converter, and the respective bits of weight data are synchronized with W-CLK. For example, in Figure 16, a pattern of all 1, corresponding to -127, is applied and thereafter pulses of 01100100 corresponding to 100 are applied. An S/H signal is applied to a time division adding control block 15 provided at an input to the adding block 4. When the S/H signal is "1", the output of the multiplying block 3 is applied to the capacitor CT of the integrator. When the first rising edge of the S/H signal data input is received, the output of the multiplying block, namely, the sum of the input pulse voltages, is added to the capacitor CT of the adding block. At this time, data applied to the D/A converter is -127 and the input data corresponding to -127 is provided as a positive voltage with a waveform 70. This positive voltage is stored in capacitor CT. When the offset control signal OC is provided as shown in waveform 71, the capacitor CT is reversed. The offset concealing generating block of the input block makes the input 0 volts, and when the S/H signal is high, the corresponding offset voltage is applied to a capacitor CT in the adding block. The capacitor's polarity is then reversed. The offset component of the voltage set at a previous rise of the S/H signal is canceled and when offset cancellation OC is 0, the capacitor CT returns to its original state. As stated above, when the voltage is held in capacitor CT, the input from a different neuron unit is multiplied by the weight 100 at respective timings of the weight clock W-CLK and the product is applied to the adding block. When the output of the positive and negative switching circuits are positive, and positive weights are applied to the D/A converter, the output of the multiplying block 3 is reversed to provide a negative voltage. The negative output voltage is stored in capacitor CT, and is then added to the voltage stored in the previous timing. Then, this is also reversed by or the adding block 4 or the integrator. Therefore, the sum of the products of the input and the weight is stored in the capacitor CT in a time division manner. When CS in is input, the voltage stored in capacitor CT is outputted as data-output through a sigmoid function. CS out is outputted after a delay time from the end of CS in , and CS out is also transmitted to adjacent units within the same layer to perform a daisy chain control which is explained later. When S/H out is turned from a low level to a high level, a voltage stored in the capacitor CT of the integrator is sampled in capacitor Ch. When S/H out falls to a low level again and CS in =1, the voltage held in the capacitor Ch is output through the sigmoid function circuit. Figure 17A is a block diagram of a connection of neuron units according to another embodiment of the present invention. In Figure 17A, U1, U2, ..., Un are units in the intermediate layer. The units of the input layer are not shown. The signal outputted from respective units in the previous stage are applied to bus A of DATA-INPUT and bus A is connected to n units in the post stage. Similarly, the output from units U1, U2...Un in the first stage are commonly connected to the bus B of DATA-OUTPUT. Therefore, the units in the previous stage are connected to the units in the following stage only through bus A. Therefore, the amount of wiring can be minimized and the potential for realizing a neuron unit and an integrating circuit becomes very high. When the signal is transmitted from the units in the previous stage to the units in the post stage, the analog pulse voltages having amplitudes corresponding to the weights, are transmitted in a time division manner. In Figure 17A, DATA-INPUT is a time division input of the analog data and DATA-OUTPUT is a time division analog output. CS0 to CSn are daisy chain output control signals and W-DATA1 to W-DATAn are weight data. Processing units U1 to Un in the embodiment execute the process independently. The processing unit Ui receives a control signal from the previous processing unit Ui-1 and outputs a control signal to the next processing unit Ui+1. The process control block 1-2 transmits the first control signal to the first processing unit Ui, and receives the signal designating the end of all the processing units as the control output from the last processing unit (Un). Namely, as shown in Figure 17B, the sequential generating of daisy control signals CS0, ..., CSi-1, CSi, CSi+1, ..., CSn-1 and CSn enable the processing units 1, ..., i, i+1, i+2, ..., n and control block 1-2 to perform the operations. In this embodiment it is not necessary for control block 1-2 to be connected to all the processing units. Therefore, control block 1-2 can be simply made. Adjacent processing units are connected to each other, thereby simplifying the wiring. Figure 18 shows a timing chart of the neural network shown in Figure 17A. The outputs yh1 and yh2 from units H1, and H2, not shown, are received from DATA-INPUT in a time division manner and weights W11 and W12 are sequentially received by unit U1. The process represented by the above equations (1) and (2) are executed in unit U1. In parallel with this operation, the output yh1 and yh2, and weights W21 and W22, ..., Wn1 and Wn2, are supplied to units U2 to Un, to perform the same function as unit U1. Control block 1-2 applies a daisy chain output control signal CS0 to unit U1 and the output yi1 of unit U1 is applied to the DATA-OUTPUT. Next, unit U1 outputs CS1 to unit U2 and unit U2 transmits output yi2 to the DATA-OUTPUT. This sequence is linked until finally unit Un transmits the Csn to control block 1-2 and completes the process series. It also executes a time division process of the neural network. Figure 19 is a timing chart of a unit as shown in Figure 17A. W-data is a digital signalinput to the D/A converter of multiplying block 3 and respective bits of weight data are synchronized with W-CLK (not shown). For example, the pulse pattern corresponding to W1 is first applied and thereafter pulse patterns W2 and W3 are applied. S/H signal not shown in Figure 19 is a signal to be applied to the time division adding control block 15 provided at the input of adding block 4. When the S/H signal is 1, the output of the multiplying block is input to capacitor CT of the integrator. When the first S/H signal rises, the output data from the multiplying block, namely, the products of the pulse signals, are applied to capacitor CT of adding block 4. Then, the digital amount which is W1 is applied to the D/A converter 13 of the multiplying block 3 and the input data corresponding to W1 is provided as positive voltage as shown in the waveform D1. In this manner, the stored voltage is held in capacitor CT and inputs D2 and D3 from different neuron units are respectively multiplied by weights W2 and W3 at different timings of W-CLK, thereby being applied to adding block 4. Therefore, the sum of the products of the input and the weight is stored in capacitor CT in a time division manner and when CS in is input, the voltage stored in capacitor CT is outputted as data output through a sigmoid function and CS out outputted after CS in is finished and CS out is transmitted to the adjacent neuron unit within the same layer. The data DATA-INPUT is applied in the sequence D1 → D2 → D3 in a time division manner to a neuron unit. When D1 is input, the weight data (W1 data) is also input and the process represented by equation 1 is conducted within the neuron unit. For the following input D2, the weight data W2 corresponding to the data D2 are input to the neuron unit and are subjected to the sum of the product, namely, (D1 x W1 + D2 x W2 + D3x W3), and the sum of the product is processed through the sigmoid function processing block. As described above, the operation of the neuron unit is completed and the daisy chain output control signal CS in controls the output in a time division manner and after the process is completed, the daisy chain output control signal CS out is produced. This embodiment is specifically useful for the output part of the neuron unit. This makes it very easy to control the signal outputted from the neuron unit. Figure 20A shows a block diagram of another embodiment. Multiplying block 3 multiplies respective inputs for the plurality of units connected to each other by the weight. The weight is read from a memory, which is not shown in Figure 20A. Adding block 4 accumulates all the products of the input value and the weight. Sigmoid function block 6 performs a non-linear function, for example, the above recited sigmoid function, by using the output of adding block calculates threshold values for the respective neuron units. The first and second memory blocks 81 and 82 store a first intermediate value obtained from the previous circuit and a second intermediate value which is transmitted to the following stage circuit respectively. The first memory block 81 corresponds to the capacitor CT in the integrator and the second memory block 82 the capacitor Ch. The output of the present neuron unit is applied to respective neuron units constituting the layer next to the layer to which the present unit belongs. In a layer structure neuron network using an analog LSI as a neuron unit the neuron unit multiplies an input value to the LSI by the weight to be input at terminal 3' and the sum of the outputs of the multiplying block 3 which is obtained with regard to a plurality of inputs to the analog LSI. Here the first memory block stores the result of the addition. The second memory block 82 stores the input and output of the non-linear-type function block for the output of the first memory block 81. The sum of the products of the input signal from the previous stage and the weight data transmitted from the outside is stored in the first memory block and simultaneously, the second memory block transmits the output analog signal to the following stage unit. Thus, the analog pipe line operation is conducted. In the neuron network, equations (1) and (2) can be used to calculate the outputs of the respective units in the intermediate layer and the output layer. When an input pattern is applied to multiplying block 3 and adding block 4, the output value is calculated using equation (1) in accordance with the sigmoid function block. The above calculation is not conducted serially for the respective units in an intermediate layer, but rather in parallel. Upon completion of the calculation, the output value corresponding to the next input pattern is immediately calculated for the respective units, also in parallel. The output of the intermediate layer for the input pattern is applied to the output layer and is used as the output value to calculate the output value for the respective units at the output layer. The value of the unit in the intermediate layer is stored in the first and second memory blocks 81 and 82 and can be output when necessary. In this embodiment, a different intermediate result is stored in two memory blocks. Therefore, the network process can be conducted using a pipe line operation. Figure 20B shows a block diagram of an embodiment of an intermediate layer of a neural network. The intermediate layer is comprised of n neuron units 90a, ..., 90n. Respective units are comprised of multiplying blocks 3a to 3n and adding blocks 4a to 4n corresponding to adding block 4, sigmoid function blocks 6a to 6n corresponding to the sigmoid function block 6 and, the memory 81a to 81n and memory 82a to 82n corresponding to the first and second memory blocks 81 and 82. A memory region is provided for storing a weight which connects the two units in the network. Figure 20B shows a memory region for the intermediate layer but a similar memory region is used for the output layer. This memory region comprises m x n regions 84a to 84n corresponding to n units H1 to Hn of the intermediate layer and m units of the input layer. The weight value is previously stored in this area through the write registers 85a to 85n in respective units. The process corresponding to respective units 90a to 90n are explained by referring to the timing chart in Figure 21. The first input pattern to the intermediate layer, namely, the input from respective units in the input layer, starts to be processed. The input yi from unit I1 in the input layer is simultaneously applied to respective units 90a to 90n (H1 to Hn) in the intermediate layer, and the operations of respective units start simultaneously. The weights of the connections between unit I1 and respective units in the intermediate layer are stored in memory regions 84a to 84n and are applied to the multiplying blocks 3a to 3n of the respective units through read registers 86a to 86n, in order to provide a product of a weight and the input y1. The products are applied to adders 4a to 4n. Then, a similar operation is applied to the input y2 from unit I2 of the input layer and the products of the weights and inputs y1, y2, ... are applied to adders 4a to 4n which are to accumulate these products. The similar calculation is applied to all the inputs from respective units in the input layer. The sum of the products for the input ym is obtained from the last unit Im, and the result is stored in the first memory 81a. The content of the first memory is transferred to the second memory 82a and the result is transmitted through the sigmoid function block 6a. In this instance, the content of the first memory is already used and thus, the second pattern is immediately applied to respective units 90a to 90n in the intermediate layer. The same operation as that to the first input is applied to the second input and the result is again stored in the first memory 81a. The content of the second memory 82a is simultaneously transmitted through the sigmoid function block 6a or withoutgoing through the sigmoid function block 6a, to the output layer. Then, the unit 01 to 0p in the output layer starts the process, and input y1 is supplied to respective units in the output layer from intermediate unit 90a. The sum of the products between the inputs y1 and weights for connection between the intermediate layer and the output layer are then stored in the memory regions. Next, the same operation is applied to input y2 from unit 90b(H2) of the intermediate layer. Input y2 is supplied from the second memory 82b in unit 90b(H2). Thus, up to this time, the output value can be maintained. Simultaneously, the sum of the products is applied to the input from the second memory 82n of the unit 90n(Hn) of the intermediate layer and is transferred to the first memory within the unit in the output layer. When the data is transferred to the second memory and is subjected to the sigmoid function, the process in the output layer for the first input pattern is completed and thereafter the second input pattern can be processed. Figure 22 shows an embodiment of a neural network utilizing an analog neuron unit. The input layer is comprised of ten units and the intermediate layer is comprised of four neuron units 100a to 100d. The output units are comprised of the two neuron units 101a to 101b, forming the neural network. In the drawing, ten input data are input from the ten neuron input layer. The neuron unit in the intermediate layer has a capacitor C1 and the neuron unit of the output layer has a capacitor C1. The capacitor C1 corresponds to the first memory. The capacitor C1 stores the data of the sum of the products. Capacitor C2 corresponding to the second memory stores the result of the first memory. The capacitor C2 is used for sample holding. Figure 22 uses the four neurons 20a to 20d in the intermediate layer which complete a sum of the products operation for the ten input data and the result is stored in the capacitor C1 as its terminal voltage. The result is then transferred to the capacitor C2 and the circuit before capacitor C1 is separated from the circuit after capacitor C2 in an analog manner. The output of the capacitor C1 is applied to C2. Namely, the result of the sum of the products is applied to the sigmoid function in the intermediate layer. At this time the output layer starts processing the signals and the output operation of the intermediate layer is conducted in both a sequential manner and a time division manner. Neuron units 101a and 101b in the output layer conduct the operation of the sum of the products. Thereafter, the operation is repeated in a sequence of 100b, 100c and 100d. The sum of the products is stored in capacitor C1 in the output layer. As described, by storing the output of the neuron unit from the intermediate layer in the capacitor C2 in the output layer it is not necessary to maintain the result of the sum of the products in capacitor C1. Thus, when the process in the output layer starts, the input data to the intermediate layer can begin to be processed. Therefore, in the above embodiment, the process in the intermediate layer and output layer can be conducted in a pipe line manner, to achieve a high-speed network operation. Figure 23 is a block diagram of a neuron network of a layer structure. In the drawing, neuron units U1, U2 and U3 are provided in a single layer. The output signal produced by each respective neuron unit is fed back to the same bus through feedback line 110 in order to constitute the inputs of the same neuron units. The present embodiment controls units U1 to U3 in a single layer in a time division multiplexing manner by control signals CS in and CS out from control block 111, thereby to provide an equivalent neuron network with a layered structure. Figure 24 shows a timing chart of input and output voltages of the units of this embodiment. The units in this embodiment receive the voltages (D1, D2 and D3) with the amplitude of the previous output and the weight data (W1, W2 and W3) to provide the sum of the products (W1D1 + W2D2 + W3D3) and, then, apply a non-linear function operation to the sum of products. When CS in is at a high level, D out is produced, and after that, output control signal CS out results. This embodiment repeatedly uses the units U1, U2 and U3 in the single layer to provide an equivalent multi-layered structure. Figure 25 shows an equivalent layer structure neural network which is realized by the neural network shown in Figure 23. Figure 26 shows a timing chart of the neural network shown in Figure 23. W-DATA1, W-DATA2 and W-DATA3 are inputted to units U1, U2 and U3, respectively, as variable weight data. As shown in the time chart of Figure 26, the data input line provides data YD1, YD2 and YD3 to units U1, U2 and U3, respectively, and weight data W1, W2 and W3 are simultaneously applied to units U1, U2 and U3 respectively, in a time division manner. That is, W1 data is applied to unit U1 simultaneously with data YD1 at the timing T0. At the next timing T1,YD2 and W2 are applied to unit U2. At the following timing T2, YD3 and W3 are applied to unit U3, thereby enabling the products thereof to be calculated and to be applied to the sigmoid function block. When the present embodiment, shown in Figure 23, is compared with the layer structure of the neural network of Figure 25, the neuron units I1, I2 and I3 of the input layer correspond to units U1, U2 and U3 of this embodiment, and the product of the input voltage and weight voltage are obtained by units I1,I2 and I3. Unit I1 in Figure 25 calculates the product of YD1 and W1, and provides an output YI1 after the sigmoid function. This output is simultaneously applied to the units H1 and H2 of the hidden layer or the intermediate layer, and the operation of the hidden layer in this embodiment can also be carried out in units U1 and U2. The output YI1 from the unit U1 which corresponds to unit I1 is fed back through a feedback line 110 and then applied to units U1 and U2 corresponding to the hidden units H1 and H2 at time T3. At this time, weight data W1 and W2 are applied to units U1 and U2 which correspond to the units H1 and H2 in the hidden layer together with YI1. Similarly, in Figure 25, the product of YD2 and W2 is calculated by unit I2 in order to output the data YI2 through the sigmoid function to be applied to units H1 and H2. When this operation is explained by referring to Figure 23, the process of unit I2 is conducted by unit U2 and data YI2 output from unit U2 is fed back through a feedback line and is simultaneously applied to units U1 and U2 corresponding to units H1 and H2 at a time T4. Similarly, the sigmoid function output value of the product of YD3 and W3 is executed by unit I3, thereby outputting data YI3 is simultaneously applied to units U1 and U2 at timing T5, which correspond to H1 and H2 in the hidden layer, as illustrated in Figure 26. In Figure 25, the input YI1, YI2 and YI3 to unit H1 and H2 are respectively multiplied by data W1 and W2. As shown in Figure 26, an operation of these multiplications is carried out at different times T3, T4 and T5. The output value provided after the sum of the products through the sigmoid function in unit H1 is YH1. Input YI1, YI2 and YI3 to unit H2 are multiplied by W2, and the sum of the products is calculated by unit H2 in order to provide the output YH2. This operation can be conducted in a time division manner. Namely in the latter case, the products of YI1 and W2, YI2 and W2, and YI3 and W2, are obtained in unit H2, which corresponds to unit U2, at times T3, T4 and T5, respectively. The sum of the products is outputted from unit U2 through the sigmoid function block. The timing T7 when YH2 is outputted is different from the timing T6 when YH1 is outputted. According to this embodiment, units U1 and U2 are used for units H1 and H2 to facilitate the operation of a time division process. The output layer O1, O2 and O3 are similarly executed by using units U1, U2 and U3 in this embodiment. Namely, as shown in Figure 26, the analog voltage YH1 produced from unit U1 corresponding to H1, is input to I1, U2 and U3 each corresponding to O1, O2, and O3 at time T6. The output YH2 from unit U2 corresponding to unit H2 is provided to O1, O2 and O3 at time T7. That is, in this present embodiment, units H1 and O1 comprise the same unit U1, and units H2 and O2 comprises the same unit U2, and unit O3 corresponds to unit U3. The products of YH1 and the weight data can be simultaneously obtained at units U1, U2 and U3 which correspond to units O1, O2 and O3, respectively. The products of YH2 and the weight data are simultaneously obtained in units U1, U2 and U3, which again correspond to units O1, O2, and O3, at time T7 (different from the time T6). In units U1, U2 and U3 which correspond to output units O1, O2 and O3, the sum of the products is calculated at time T6 and T7 while the output values through the sigmoid function is outputted as YO1, YO2, and YO3 at times T8, T9, and T10. The control signals CS1, CS2, CS3, and CS4, shown in Figure 26, facilitate the calculation of the multiplication of the input signal and the weight data and the sigmoid function to be carried out, thereby producing the result of the calculation. For example, CS1 becomes "1" when the unit U1 is in an output state. Therefore, YI1, YHI1, YO1 are input to the next stage at times T3, T6 and T8, respectively in a feedback manner. The corresponding weight data are input to unit U1 and the result of the previous sum of products after a non-linear function is output from unit U1, when the pulse signal CS1 is "1". Similarly, when a pulse signal CS2 becomes "1", YI2, YH2 and YO2 are input to the next stage in a feedback manner and the result of the previous sum of products after a non-linear function is output from unit U2. When a pulse signal CS3 becomes "1", YI3, YH3 and YO3 are input to the next stage in a feedback manner and the result of the previous sum of the products after a non-linear function is output from unit U3. The control signal CS4 is outputted from unit U3, after unit U3 outputs signals. Accordingly, the operation of units U1 to U3 in the embodiment constitutes, a neural network of an equivalent layer structure by using a single layer unit in a time division multiplexing manner. Figure 27 shows the structure of another embodiment of a neural network. The output signals from respective neuron units U0, U1 and U2 are fed back by the same bus 120 and are entered in the same units. The present invention provides a Hopfield type network in which units U0 to U2 are used in a time division multiplexed manner and the weight between the units can be changed. Figure 28 shows a timing chart for a wave form of the input voltage for the unit. A pulse voltage (D0, D1, D2) has an amplitude corresponding to the sum of the products while the weight data (W0, W1, W2) are input in a time division manner. The sum of the products (W0D0 + W1D1 + W2D2) is obtained inside the unit and is subjected to a non-linear function operation. When CS in is at a high level, the result D out is outputted, and thereafter CS out is outputted as an output control signal. In this embodiment, the operation is repeated within the network until the output of the network becomes stable. Figure 29 is a block diagram of a neural network according to the present embodiment. Figure 30 is a detailed timing chart of a waveform of a neural network which uses multi division multiplexing according to the block diagram shown in Figure 27. As shown in Figure 27, W0, W1 and W2 are weight data to be supplied to the units U0, U1, U2, respectively. Figure 29 realizes a Hopfield type network shown in Figure 27 and uses unit 0 of Figure 27 in order to produce the input yi in Figure 29. Namely, the weight 0 of unit 0 is determined such that it always has 0 weight data and that the output of unit 0 is kept constant, for example, by storing a constant voltage in the capacitor Ch, and is applied to units U1 and U2 as an input yi. The timing chart shown in Figure 30 illustrates outputs yi, Y01 and Y02 from units U0, U1 and U2 which are given, and weight data W0, W1 and W2 are respectively applied to units U0, U1 and U2 in a time division manner. Namely, at a time T0, Wi1 of W1 data and yi are applied to unit U1. Wi2 is made to correspond to W2. At the next time T1, YO1 and W11 are input to unit U1, and Y01 and W12 are supplied to unit U2. At the next time T2, Y02 and W21 are applied to unit U1, Y02 and W22 are applied to unit U2. Therefore, respective products are calculated and put through the sigmoid function in each unit. The operations of T0 to T2 are repeated in the sequence of T3 to T5, and T6 to T8, .... When the energy function of the network is at a minimum or at a local minimum, the output of the network becomes stable and will not be changed, thereby finishing the repetition of this operation, as the output of the network does not change. The control signal CS0, CS1, CS2, CS3 shown in Figure 30 enables a calculation of the products of the input signal and the weight data, and the sigmoid function, to be outputted. For example, CS0 is a pulse which becomes "1" when the unit U0 is in outputting state. Therefore, yi is input to the other unit from a unit U0 at times T0, T3, T6 and T9 and when the corresponding weight data is input to the other unit, CS0 will become "1". Similarly, CS1 is a pulse which becomes "1" when YO1 is output from unit U1 and CS2 is a pulse signal which becomes 1 when Y02 is output from unit U2 after unit U2 produces the output. The present embodiment provides a neural network which uses a plurality of units in a time division and multiplexing manner. Figure 31 is an example in which a neuron computer can be realized through a feedback type to network which operates in a layer-type network. For the time division analog input signal from analog input ports 1 and 2, a sum and product operation is conducted at ANP1, 2 and 3 (a neuron unit as shown in Figure 12 is hereinafter called as ANP(Analog Neuron Processor)). ANP1, 2 and 3 operate as an intermediate layer and produce a time division output to analog bus B2. The output signal is fed back to the analog bus B1 through analog common bus CB and again ANP1, 2 and 3 calculate the product at three operations for the feedback signal, thereby enabling ANP1, 2, 3 to operate as an output layer and realize a layer-type network by using a single ANP1,2 3. The max value node circuit 187 produces a dummy signal to analog bus B2 after receiving DCS output of the master control block 181 and produces a dummy signal to the analog bus B2. DCLK and WCLK are input to a daisy chain circuit 171 from the master control block 181 at the timing of the rise and fall of the CSI signal. Figure 32A is a timing chart of a feedback type layer network shown in Figure 31. During a period when DCLK is high, WCLK is produced and the analog signal becomes constant. Once the weight data is input serially, CSO1 from the master control block 181 is input to daisy chain circuit 171, as shown, and rises as illustrated in 1 ○ at a timing before the serial input data is converted to parallel data. At this time the analog signal maintained at the sample and hold S/H by analog input port 1, appears on analog bus B1 through analog switch 175. This enables ANP 1, 2, 3 to execute a product and sum operation. Next, when DCLK is input, CSI supplied to a daisy circuit 172 rise as shown in 2 ○ and the sample hold circuit S/H signal maintains the input signal from the analog input port which appears on the analog bus through an analog switch. This enables a second product and sum operation at ANPs1, 2, and 3. Further, at the next timing, when DCLK is input, the master control block 181 produces dummy signal DCS as shown in 3 ○ and ANPs1, 2, and 3 perform a third product from the operation for fixed voltage. During the rise of the synchronization signal, the output layer of ANPs 1,2, 3 performs a sum of product operation. When address count prohibiting signal rises slightly the signal of the address signal to a weight memory 185 also rises. WCLK is then able to operate the address counter. At times, other than the above, the count is suppressed. Next, when the CSO2 is applied to the ANP1 from master control block 181, ANP1 produces the result of the sum of the products of the previous timing to analog bus B2. This enables the output to be fed back to analog bus B1 through the analog common bus CB and performs the sum product operation at ANPs1, 2, and 3 again, as shown 4 ○. After a predetermined delay is applied to the CSO2 by a daisy chain circuit 172, the input signal CSI is added to ANP2 as shown by 5 ○. At this timing, the output signals from ANP2 again added to analog bus B1 through common bus CB and analog bus B2 are again supplied to the ANP1. Thus, the sum and product operations are performed. Similarly, CS0 from ANP2 is delayed by a predetermined timing to provide a CSI signal of ANP3 and when the CSI signal rises as shown as 6 ○, the output signal from ANP3 is fed back to ANP1, 2, 3 through analog bus B2, common bus CB and analog bus B1, thereby performing a product of sum operation. Similarly, when the signal DSC from the dummy node of master control block 181 rises7 ○,the summing operation is conducted for respective fixed voltages by ANPs 1, 2 and 3. Upon the rise of the CSO2 signal, ANPs 1 and 2 produce output as shown by 8 ○ and 9 ○ through S/H 178 and 178'. The output is not produced from analog output port 2. At times 1, 2 and 3, ANP1, 2, 3 operate as an intermediate layer, at time 4, 5 and 6, ANP1, 2, and 3 operate as an output layer. Therefore, according to this embodiment, only a single layer of ANP1, 2 and 3 are required to constitute a layer type network by using the respective ANP for different functions at different times. S/H 177, multiplexer 179, A/D converter 180, MPU 182, memory 183 and communication interface 184 are also shown in Figure 31. Figure 33 shows an embodiment in which an analog neuron computer is formed by a Hopfield type feedback network. Figures 34A and 34B show a timing chart. The output from the memory address terminal and mode terminal of master control block 181 is added to weight memory block 185 and B10 of the data output from the weight memory block 185 which is connected to ANP1, B11 ANP2 and B12 ANP3. The output signal from the terminal for CSO1 of the master control block 181 is applied to daisy chain circuit 171 and analog switch 175. The output from the sample/hold circuit 173 from the analog input port 1 is provided on analog bus B1. Then, this signal is delayed by a predetermined time by daisy chain circuit 171, CSO output is produced, and this is applied to daisy chain circuit 172 as CSI. The signal of sample/hold circuit 174 connected to analog input port 2 is provided on analog bus B1 through switch 176. The output signal CSO of daisy chain circuit 172' simultaneously opens the output switch 176' of the sample hold circuit 174' which is connected to analog input port 3 and the signal output from the output switch 176' is provided on analog bus B1. ANP1 performs a single product and sum operation during the period of a DCLK signal and when the DCLK signal is high, the weight clock is driven and the digital weight data is inputted in synchronization with the weight clock which is multiplied by the analog input signal. When the latter part of the DCLK is low, the sample/hold signal S/H becomes high, enabling a capacitor integrator to perform a summing operation. During period 1 ○, when CSO1, namely, CSI of the daisy chain circuit 171, is high, ANPs 1, 2, and 3 perform a product and sum operation for the analog signal on bus B1. When the OC signal from the master control block 181 becomes high, ANPs1, 2, and 3 perform an offset cancellation and a sample hold operation. This results in a completion of one cycle of the product and a sum operation. Next, when input signal CSI reaches the second daisy chain circuit 172, it becomes high as shown by 2 ○, and ANP1, 2, 3 perform a product and sum operation for the input signal from the analog input port. When the product sum operation period is completed, the CSI signal is input to daisy chain circuit 172' and the output signal is produced from sample/hold circuit 174' and as shown by 3 ○, the third product sum operation cycle is cut. Next, CSO2 signal 4 ○ is produced from master control block 181 and the signal formed in the previous product and sum cycle from ANP1 is fed back to analog bus CB. The product and sum operation are simultaneously conducted by ANPs 1, 2 and 3 for the feedback signal. Next, after being delayed by a predetermined timing, CSO output signal from ANP1 is applied to ANP2 as shown by 5 ○. The signals stored in the timing of the product and sum cycle of the previous timing are outputted from ANP2 in a daisy chain like manner. The signal is fed back to ANP1, 2 and 3 through the analog bus CB and the product sum operation is facilitated as shown by 5 ○. Simultaneously, after delaying the signal period by a predetermined time period, CSO of ANP2 is added to ANP3 as shown by 6 ○ and the output from ANP3 is fed back to ANPs1, 2 and 3 through analog bus CB to perform a product and sum operation at 6 ○. As shown in Figures 34A and 34B, the feedback type network, and the output from 3ANPs, perform six product and sum operations which are output to analog output ports 0, 1, 2, 3 through sample/hold circuits 177, 178 and 178'. The output signals from the sample/hold circuit 177, 178 and 178' are selectively output by multi-analog multiplexer 179 and are supplied to the digital control circuit comprising MPU182, memory 183, and communication interface 184 through A/D converter 180. MPU 182 determines whether the neuron output state at the present time is the same as the neuron output state of the previous time. If they are in the same time status, the system can be considered to become stable. Therefore, the operation is carried out by using a single common analog bus CB through the feedback operation and is repeated to reach a stable resolution which is deemed as a final output. Figure 35A shows a block diagram of another embodiment of the present invention. Sign operation block 131 is provided before D/A converter 132 and digital data control block 133 controls the sign operation block 131 and D/A converter 132 by applying an operation control signal and a data bit train to them, respectively. Figure 35B is a block diagram of an analog neuron circuit. Figure 35B shows DAC 141, operational amplifiers 142, 143, 144, analog switches 145, 146, 147, an inverter 148 and a digital data control circuit 149. This forms a multiplying circuit (within the dotted line). In addition, it shows an input buffer 150 for analog data, another circuit 151 comprising an integrator for obtaining a sum of the input and the weight data, a non-linear function circuit 152 for determining the output of the product sum from the integrator, and an output buffer 153. In the embodiment as described above, the time division analog data which varies irregularly to have both positive and negative values, is serially multiplied by time division digital data which changes irregularly and has positive and negative values. An operation of the multiplication will be explained by referring to the time chart shown in Figure 36. The first clock DCLK determines the timing of one multiplication and the second clock WCLK determines the input timing of digital weight data inputted one bit at a time. In Figure 35B, the input voltage to the data input terminal of DAC 141 is made 0 and the output voltage is also made 0, as shown in 2 in Figure 36. For the first time, the MSB of the digital data is input to digital data control circuit 149 then the sign operation control signal(SIGN) is provided to analog switches 145 and 146. Namely, if the digital data is negative, the analog switch 147 is turned on, and the switches 145 and 146 are turned off. Conversely if the sign of the digital data is positive, the analog switch 147 is turned off and analog switches 145 and 146 are turned on. When the operation control signal from digital data control circuit 149 is conducted, MSB of digital data is used and if the sign of the digital data is positive, the operation control signal becomes "0" and if the sign of the digital data is negative, the sign of the operation control signal becomes "1" as an output from the digital data control circuit 149. Input analog data flow through input buffer 150 is applied to the terminal of DAC 141 after it is determined whether or not the polarity is to be reversed based on the status of the analog signal switches. Namely, if the sign of the digital data is negative, the input analog data only passes through operational amplifier 143, and if the sign of the digital data is positive, the analog data passes through bus operational amplifiers 143 and 144. After the signal is output from DAC 141, the output from DAC 141 flows through operational amplifier 142, thereby reversing the polarity of the signal which is again reversed in an adder. If the sign of digital signal is positive, the input analog data goes through four operational amplifiers, thereby enabling the polarity of the input analog data to be unchanged. When the sign of the digital data is negative, the input analog data goes through three operational amplifiers, thereby enabling the polarity to be reversed. Analog input data flows through operational amplifier 143 or operational amplifiers 143 and 144, and therefore, due to the through rate of the operational amplifiers the input of the analog data to DAC 141 is delayed. However, during the delay time a serial input of all the digital bit data is input in parallel to the digital data control circuit 149. Thereafter, the output of DAC 141 is stable after the delay time corresponding to the setting time of DAC 141. This is shown by 1 ○ in Figure 36. As described above, before analog data and digital data are input, the output of DAC 141 is made 0 and the maximum variation of the output is not six volts between the positive (maximum 3 volts) and negative (maximum negative 3 volts) voltages but half of six volts, namely, 3 volts. Thus, the settling time of DAC 141 can be reduced. Figure 37 is a block diagram of an embodiment of the digital data control circuit 149. This circuit is comprised of counter circuit 155 to which the first clock (CLK) and second clock are input, reset control circuit 156 to which the first clock and the timing signal designating compression of addition are input, shift circuit 157 to which the second clock digital data and the shift control signal from counter circuit 155, flip flop 158 to which MSB of the digital data and the sign latch control signal from counter 155 are input, flip flop 159a, 159b, ..., 159n to which signal from shift circuit 157 is input, data latch control signal from counter 155 and reset control signal from reset control circuit 156 are input. As shown in Figure 37, before the digital data is input to digital data control circuit 149 for starting a multiplication, the first clock becomes 0 and the addition at the adding circuit in Figure 36 ends and a timing signal for completing an addition becomes 0. Then, all the flip flops 159a to 159n are reset by a reset control signal from reset control circuit 156. This is input to the data input terminal of DAC 141 and the output of the DAC 141 becomes 0 as shown by 2 in Figure 36. Thereafter, the digital data is serially input bit by bit to digital data control circuit 149. When the MSB of the digital data is input, the data is latched by flip flop 158 by a signed latch control signal outputted from counter 155 in synchronization with the second clock and is provided to operational amplifiers 144, 143 and 142 for performing a sign operation. The digital data as bit MSB is sequentially shifted in shift circuit 157 in accordance with the shift control signal outputted from counter 155. This is done in synchronization with the second clock and is simultaneously latched by a plurality of flip flop 159a to 159n by the data latch control signal outputted from the counter 155 when all the bit are input and is outputted to the data input terminal at DAC 141. In order to shorten the settling time of DAC 141, all the data are not simultaneously latched by a plurality of flip flops 159a to 159f after a completion of the serial input of all the digital data. It is preferable to output the data at the data input terminal of a bit position corresponding to DAC 141 every time a bit of digital data is provided. A digital data control circuit for performing this operation is shown in a block diagram of this embodiment in Figure 38. The structure of Figure 38 is similar to that of Figure 37 but it does not make use of a shift circuit. In addition, the signal from counter 160 does not directly produce a sign and a data latch control signal but rather is input to decoder circuit 161 to be latched by flip flop 163 and a plurality of flip flops 164a to 164n. All the flip flop 164a to 164n are reset by a reset control circuit 162 as shown in Figure 37 and all the flip flops 164a to 164n are reset after the output of DAC becomes 0, and the digital data is input. When the MSB of the data is input, the counter circuit 160 synchronized with the second clock enables the sign latch control signal to be outputted from the decoder circuit 161 to flip flop 163, thereby enabling flip flop 163 to latch the content of the sign bit and to provide both a sign and an operational control signal. The data bit train of the digital data is input sequentially one bit at a time and the output of the counter circuit 160 progresses at every input bit, and is decoded by decoder 161. This enables the data latch control signal to be sequentially input at one of the flip flops 164a to 164n, thereby latching the input data which is supplied to the corresponding input DAC 141. Figure 39 shows a block diagram of a neuron board according to another embodiment of the present invention. An interface unit 165 provides an interface between the neuron board and the system. An input and output control unit 166 controls input and output of data to and from the network unit. A neural network 167 uses a time division multiplexing signal by a set of units, memory 168 stores the digital weight data of the neural network and a control unit 169 outputs the synchronization control signal for performing a time division multiplexing operation for the network. The neuron board according to the present embodiment determines a network structure by using all the units through network control unit 169 and the weight of the unit is outputted from memory 168. The weight between the units can be changed by changing the content of the memory. As a result, the data input and output from network 167 is carried out by the input and output control unit 169. The operation of the neuron computer can be executed by the this neuron board. In the present invention a neuron architecture is employed as a processing apparatus. An input analog data is applied in parallel to a plurality of neuron units in a time division multiplexing manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The product of the time division analog input data and the digital weight data are added in an integrator. While the sum of the products is output with regard to the present result, the previous sum of the product is outputted through a non-linear function forming means simultaneously with the present data, thereby enabling the operation of the sum of product in the unit in the intermediate layer simultaneously with that in the unit in the output layer and thereby providing outputs in a pipe-line manner. When the output of the first neuron in the same layer produces the output analog bus, the second neuron in the same layer is able to produce an output such that the output of the first layer is produced on the output analog bus in a time division multiplexing manner. An analog neuron chip includes a plurality of operational amplifiers. The offset thereof is canceled by an offset canceling means. The above analog neuron unit constitutes an intermediate layer and an output layer, so that the neuron system operates in the form of a layered structure. One layer comprising a plurality of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer to form a neuron system with a layered structure.

Claims: A neuron architecture comprising: a plurality of first neuron units (U1, U2, U3) for producing respective ouput time division analog signals (y1, y2, y3; DATA-INPUT, yh1, yh2) in a time division multiplexing manner, a common bus (A; 110; 120), connected to said first plurality of neuron units (U1, U2, U3), for sequentially transferring said respective output time division analog signals (y1, y2, y3; DATA-INPUT, yh1, yh2) of said first neuron units in a time division multiplexing manner, and a second neuron unit (U4, U5; Ul, U2, Un; Ul, U2, U3), connected to said common bus (A; 110; 120), for receiving said output time division analog signals (y1, y2, y3; DATA-INPUT, yh1, yh2) from said first neuron unit (U1, U2, U3) in a time division multiplexing manner, and said second neuron unit performing a neuron function to provide an output thereof (y4, y5; yi1, yi2, yin). A neuron architecture according to claim 1, in which said second neuron unit (U4, U5; U1, U2, Un) receives in a time division multiplexing manner analog input signals (y1, y2, y3; DATA-INPUT, yh1, yh2) transmitted from the plurality of first neuron units (U1, U2, U3), and wherein said second neuron unit (U4, U5; U1, U2, Un) comprises:- means (3; 3a, 3n; 12, 13, 14) for multiplying said analog input signals by corresponding weight data (WEIGHT INPUT; Wih; WEIGHT DATA, SIGN, MSB; LSB; W-DATA; w-DATA1, w-DATA2, w-DATAn; WEIGHT; WEIGHT VALUE: W-DATA, W0, W1, W2, W3; Wi1, Wi2, W11, W12, W21, W22) to provide a plurality of products thereof, means (4; 4a, 4n; 15; 151) for adding said products to provide a sum thereof, and means (16, 17) for outputting the sum in a time division multiplexing manner. The neuron architecture according to claim 2, wherein the analog input signals (y1, y2, y3; DATA-INPUT, yh1, yh2)) have amplitudes corresponding to respective neuron units (U1, U2, U3) which transmitted the signals and have negative or positive values which control said second neuron unit (U4, U5; U1, U2, Un; U1, U2, U3) to be excited or inhibited. An offsetting device for the neuron architecture according to claim 1, comprising: means (11) for inputting an offset control signal to an operational amplifier (9), included in each neuron unit ((U1, U2, U3, U4, U5; U1, U2, Un), and means (10) for producing a signal for cancelling said offset control signal at an output of said operational amplifier (9). The neuron architecture according to claim 1, comprising: offset cancelling means for detecting an offset voltage appearing in respective circuits when an input signal is made 0; means for cancelling an input converting value of the offset voltage; and means for offset cancelling to cancel the offset voltage to affect the analog input voltage of a time division multiplexing signal upon performing an arithmetic operation. A multiplying device for use in the neuron architecture according to claim 1 that has a plurality of neuron units for forming an intermediate connection to be made to each other for operative neurons, comprising: an input means (9, 10, 11) for receiving signals (DATA-IN), representing data from operative neuron units, in a multiplexed and time division manner, a multiplying means (12, 13) operable to switch between a positive state and a negative state in relation to time division multiplexed, analog input signals (DATA-IN) by using digital weight data (WEIGHT DATA), in particular a sign bit (SIGN) of the digital weight data, input from an external circuit, and operable to select paths (R-2R) of currents (I, 2I, 4I, ...), with weights obtained by converting respective voltages of the time division multiplexed analog signals in accordance with selected numeral bits (MSB, ..., LSB) of the digital weight data and thereby to provide the products of the respective voltages of the time division multiplexing analog signals with the digital weight data (c.f. Fig. 12, Fig. 6, Fig. 7). The neuron architecture according to claim 1 for connecting a plurality of neuron units to each other comprising: input means (4) for inputting an analog voltage outputted from a plurality of neuron units in the previous stage in a time division multiplexed manner, a capacitor (CT), and adding means (4) for carrying out an integration operation by time divisionally adding to the capacitor (CT) respective voltages of the time division multiplexed analog signal and said digital weight data. The neuron architecture according to claim 1 for connecting a plurality of neuron units to each other, comprising: an input means (9, 10, 11) for inputting analog signals (INPUT; DATA INPUT) outputted in a time division multiplexing manner from operating neuron units, and multiplying means (12, 13) for performing positive or negative switching (12) of said time division multiplexed analog input signals by using a sign bit (SIGN) of digital weight data (WEIGHT DATA) input supplied from an external circuit and selecting a path (R-2R) for the weighted current obtained by converting said time division multiplexing analog signals into weighted currents (I, 2I, 4I, ...) by using numeral values (MSB, ..., LSB) of said digital weight data (WEIGHT DATA) and producing a product of respective voltages of the time division multiplexing analog signal (INPUT; DATA INPUT) and the digital weight data (WEIGHT DATA), adding means (15, 16) for carrying out an integration operation by adding the respective products of the respective analog voltage of the time division analog signal and said digital weight data to a capacitor (CT) in a time division manner, sampling/holding means (18, 5) for performing sampling and holding operations on the output of the adding means (15, 16); non-linear function forming means (21, 22; 6) for forming non-linear functions formed by the segmented line approximation technology; and output means (23, 24) for outputting the analog output signal produced to the neuron units of the following stage, and offset cancelling means (10, 11, 17, 18, 19, 20; 25, 26, OC, 42, 43 to 47, 48 to 52, CT, Ch) for detecting an offset voltage appearing in respective circuits when an input signal is made 0, and for cancelling an offset voltage appearing in a circuit by affecting the input voltage by using the first offset voltage upon an operation (c.f. Figs. 6 to 11 and 12) An analog parallel computer using the neuron architecture according to claim 8, wherein a plurality of the neuron architectures are arranged to perform a computing operation. The neuron architecture according to claim 8, wherein said non-linear function forming means (21, 22; 6) comprises a plurality of amplifying units connected in cascade to provide a desired non-linear output (c.f. Fig. 15). The neuron architecture according to claim 8, wherein, when the input means (9, 10, 11) receives an offset control signal (OC), the input voltage is compulsorily input to an operational amplifier (9) through said offset cancelling means (11, 25, 26), and an offset voltage is produced at an output of an operational amplifier at respective portions of the next stage (c.f. Fig. 12). The neuron architecture according to claim 8, wherein, said multiplying means (12, 13) comprises positive and negative switching means (12) for switching respective analog voltages of a time division multiplexing signal output from said input means (9, 10, 11) to either a positive voltage for excitation or a negative voltage for inhibition, in accordance with the sign bit (SIGN) of the digital weight data (WEIGHT DATA), and means for flowing weight currents (I, 2I, 4I, ...) through respective resistors (R-2R) provided inside a D/A converter (13), based on the voltage obtained from the said positive and negative switching means (12), and selecting the weight current (I, 21, 4I, ...) corresponding to a numeral bit (MSB, ..., ..., LSB) of the digital weight data (WEIGHT DATA), thereby providing a product of the time division analog signal (INPUT; DATA-INPUT) and the digital weight data (WEIGHT DATA) (c.f. Fig. 12). The neuron architecture according to claim 8, wherein said adding means (15, 16, 17; 4) comprises an analog integrator (39, 42, CT, RT) which adds an analog signal obtained from said multiplying means (12, 13) to a capacitor (CT) upon an input of a first sample hold signal (S/H) and cancels the offset voltage occurring at respective means in accordance with 0 input signal voltage by reversing the polarity of the capacitor (CT) (c.f. Fig. 12) The neuron architecture according to claim 8, wherein said sampling/holding means (18, 19, 20; 5) includes means (Ch, 48 to 51,-59) for holding the voltage obtained by subtracting the offset voltage appearing at the final output (DATA-OUTPUT) when the input voltage to an operational amplifier (53) is made 0, from the output voltage of said adding means (15, 16, 17; 4) when a second sample hold signal (S/H OUT) is input, and means (48 to 51, 59) for cancelling said offset voltage equivalent by inputting said voltage into said amplifier (53) by reversing said second sample hold signal (S/H OUT) (c.f Fig. 12). The neuron architecture according to claim 8, wherein said non-linear function forming means (6) produces a sigmoid function formed by common connection of the outputs from a plurality of current switching type circuits (c.f Fig. 15), and includes means (22) for selecting whether or not the signal should be passed through this non-linear function circuit (6) (c.f Fig.12). The neuron architecture according to claim 8, wherein said output means (23, 24) transmits an output (DATA-OUTPUT) from a buffer (56) externally when a final offset output signal has been fed back to the sampling/holding means (18, 19, 20; 5) and the output signal (DATA-OUTPUT) is produced after the output control signal (CSIN) is delayed (CSOUT) by a predetermined time (DELAY 23') (c.f. Fig. 12). A neuron architecture as claimed in claim 1, employing a linked control method comprising the steps of: receiving linked input control signals (CSIN; CS1) from a previous neuron unit (U1) and outputting linked output control signals (CSOUT; CS2) to the next neuron unit (U2), and transmitting a first linked control input signal (CSO) to a first neuron unit (U1) and receiving a linked control output signal (CSn) from a last neuron unit (Un), whereby a linked-control input signal (CSIN; CS0, CS1, CS2) is input to a neuron unit (U1, U2) and after the output operation from said neuron unit (U1, U2, Un) is completed, said neuron unit (U1, U2, Un) produces a linked control output signal (CSOUT; CS1, CS2) (c.f. Fig. 12, Fig. 17A, Fig. 23, Fig. 25). A neuron architecture as claimed in claim 17, the linked control method further comprising the steps of calculating the products of time division multiplexed analog input data and weight data, adding said products, providing the result of the addition in a time division multiplexing manner through a non-linear function means (6), inputting and outputting said linked control signals (CSIN, CSOUT) at an output control unit (23), outputting a result upon receiving said linked input control signal (CSIN; CS0, CS1, CS2) and outputting the linked control output signal (CSOUT; CS1, CS2) after the output processing is completed (c.f. Fig. 12, Fig. 17A, Fig. 23, Fig. 25). A neuron architecture as claimed in claim 17, wherein in the linked control method a linked control signal (CSOUT) is output from a delay circuit (23') having a predetermined delay amount (c.f. Fig. 12). A neural architecture as claimed in claim 1 comprising a layered structure neural network including a plurality of analog neuron units (90a, 90n; 100a to 100d, 101a, 101b) each comprising: multiplying means (3a, 3n; 3) for providing products of the input values (INPUT VALUE(m); INPUT) and weight data (WEIGHT VALUE; WEIGHT) corresponding to the input values, adding means (4a, 4n; 4) for summing the output of said multiplying means (3a, 3n; 3), non-linear function operating means (6a, 6n; 6) for providing a non-linear function value corresponding to the output from said adding means (4a, 4n; 4), first (81a, 81n; 81; CT; C1) and second (82a, 82n; 82; Ch; C2) storing means storing a first intermediate value (INPUT DATA 10) obtained from a previous stage circuit on the input side, and a second intermediate value to be transmitted through the following stage circuit, respectively, whereby the output values of the plurality of units (90a, 90n; 100a to 100d, 101a, 101b) are calculated in parallel for all respective inputs in a plurality of units in respective layers and during the time period when the result of the calculation is outputted to the next stage, the intermediate value of the input pattern is calculated simultaneously to provide an analog pipe line operation (c.f. Fig. 12, Fig. 20A, Fig. 20B, Fig. 22). The neural architecture according to claim 20, wherein said first intermediate value is the output from said adding means (4a, 4n; 4) and said second intermediate value is a non-linear function input corresponding to an output of said first storing means (81a, 81n; 81; C1; CT) wherein, an operation of storing said first intermediate value in said first storing means (81a, 81n; 81; C1; CT) is simultaneously conducted with an operation of transmitting an analog output signal corresponding to said second intermediate value stored in said second storing means (82a, 82n; 82; Ch; C2) to a unit in the next stage (c.f. Fig. 12, Fig. 20A, Fig. 20B, Fig. 22). A neural architecture according to claim 20, in which said first storing means comprises a capacitor (CT; C1) (c.f. Fig. 12, Fig. 22). A neural architecture according to claim 20, in which the second storing means comprises a capacitor (Ch; C2) within a sample hold circuit (5) connected to said adding means (4) (c.f. Fig. 12, Fig. 22). A neural network formed by the neuron architecture according to claim 1, in which said second neuron unit (U1, U2, U3) is one of said first neuron units (U1, U2, U3), comprising: a single layer unit set means for forming a unit set of a single layer with said first neuron units (U1, U2, U3) for providing the product of time division analog signals and digital weight data, means (4) for performing an integration by adding the products into a capacitor (CT) in a time division multiplexing manner, thereby providing an output voltage through the non-linear output function (6) in a time division manner, feedback means (110; 120) for feeding back the output of said single layer unit set means to the input unit of the same single unit set means, control means (111; 121) for performing a time division multiplexing of an analog signal from respective units outputted from said single layer unit set means and executing a control for using said single layer unit means through said feedback means (110; 120) in a time division multiplexing manner, whereby said single layer unit set means used in a time division multiplexing manner equivalently provides a layer-structure neural network (c.f. Fig. 12, Fig. 25, Fig. 27). The layer-structure neural network according to claim 24, wherein the weight data for connecting respective units can be changed. A neural network formed by the neuron architecture according to claim 1, in which said second neuron unit (U1, U2, U3) is one of said first neuron units (U1, U2, U3), comprising unit set means including said first neuron units for producing a product of an input analog signal and a digital weight data, and for performing an integration by adding the product to a capacitor (CT) in a time division multiplexing manner and producing a voltage through a non-linear output function (6), feedback means (110; 120) for feeding back an output of said unit set means to the input part of the same unit set means, and control means (111; 121) for providing the analog signal outputted from respective units of said unit set means in a time division multiplexing manner and controlling said unit set means to be used in a time division multiplexing manner, through said feedback means (110; 120) (c.f. Fig. 12, Fig. 25, Fig. 27). The neural network according to claim 26, wherein the weight data connecting respective units can be changed. A neuron architecture as claimed in claim 1, comprising a system for speeding up a continuous multiplication, comprising: means (132; 141 to 149) for multiplying time division analog data (ANALOG DATA) having irregular positive and negative values by time division serial digital data (DIGITAL DATA) having irregular positive and negative values, sign operation means (131; 144 to 148) for performing a sign inversion operation to selectively invert or non-invert the sign of the analog data (ANALOG DATA) to enable the operation result to be output at the reference volt terminal of a D/A converter (132; 141), and digital data control means (133; 149) for outputting an operation control signal (ACCUMULATION CONTROL SIGNAL) to said sign operation means (131; 144 to 148) by first using an input sign bit out of the digital data (DIGITAL DATA), and an input data bit sequence (DATA BIT TRAIN; PARALLEL) input after the sign bit from said digital data (DIGITAL DATA) to the data terminal of said D/A converter (132; 141) (c.f. Fig. 35A, Fig. 35B). A neuron architecture as claimed in claim 28, wherein said digital data control means (133; 149) outputs the data bit sequence (DIGITAL BIT TRAIN; PARALLEL) to the data input terminal of said D/A converter (132; 141) in a sequence of every input of each bit constituting the data bit sequence (c.f. Fig. 35A, Fig. 35B). A neuron architecture as claimed in claim 28, wherein said digital data control means (149) outputs a "0" to the data input terminal of said D/A converter (141) before outputting the data bit sequence (PARALLEL) (c.f. Fig. 35A, Fig. 35B). A neuron architecture as claimed in claim 28, wherein said digital data control means (149) outputs the data bit sequence to the data input terminal of said D/A converter (141) in a sequence of every input of each bit constituting the data bit sequence (PARALLEL) and outputs a "0" to the data input terminal of said D/A converter (141) before outputting the data bit sequence (c.f. Fig. 35A, Fig. 35B).

Inventors: ASAKAWA KAZUO, ENDO HIDEICHI, ICIKI HIROKI, ISHIKAWA KATSUYA, IWAMOTO HIROMU, KATO HIDEKI, KAWASAKI TAKASHI, MATSUDA TOSHIHARU, SUGIURA YOSHIHIDE, TSUCHIYA CHIKARA, TSUZUKI HIROYUKI, YOSHIZAWA HIDEKI, ASAKAWA, KAZUO, ENDO, HIDEICHI, ICIKI, HIROKI, ISHIKAWA, KATSUYA, IWAMOTO, HIROMU, KATO, HIDEKI, KAWASAKI, TAKASHI, MATSUDA, TOSHIHARU, SUGIURA, YOSHIHIDE, TSUCHIYA, CHIKARA, TSUZUKI, HIROYUKI, YOSHIZAWA, HIDEKI, ASAKAWA, KAZUO FUJITSU LIMITED, ENDO, HIDEICHI FUJITSU LIMITED, ICIKI, HIROKI FUJITSU LIMITED, ISHIKAWA, KATSUYA FUJITSU LIMITED, IWAMOTO, HIROMU FUJITSU LIMITED, KATO, HIDEKI FUJITSU LIMITED, KAWASAKI, TAKASHI FUJITSU LIMITED, MATSUDA, TOSHIHARU FUJITSU LIMITED, SUGIURA, YOSHIHIDE FUJITSU LIMITED, TSUCHIYA, CHIKARA FUJITSU LIMITED, TSUZUKI, HIROYUKI FUJITSU LIMITED, YOSHIZAWA, HIDEKI FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: G06F15
IPC codes: G06N3