Predictive coding device

Abstract: A predictive coding device has an input terminal through which a sampled value (x i ) is input, a predicting circuit for outputting a predicted value (x and) i for the sampled value which has been input through the input terminal, and a look-up table (12) arranged to receive, as a readout address, the sampled value (x i ) input through the input terminal and the predicted value (x and i ) and then to output a predictive coded value ( x i ). On the basis of the input sampled value (x i ) and the predicted value (x and i ), the predictive coding device determines the readout address for the look-up table (12) which stores a table providing the predictive coded value.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a high-definition television image data processing apparatus having at least one device for predictively coding the image data. Such apparatus is suitable for use in digital transmission of an image. Description of the Prior Art It has been proposed to provide various coding methods in order to reduce the amount of data transmitted during digital transmission of information such as image or voice information. Differential pulse-code modulation (hereinafter referred to as "DPCM") is one known example of such a coding method in which the amount of information is reduced by utilizing the correlations between adjacent sampled values. As is well known, in DPCM, a coded sampled value is decoded, the decoded value is then used to obtain a predicted value for the succeeding sampled value to be coded, and then the error between the predicted value and the succeeding actual sampled value is quantized and coded. Fig. 1 is a block diagram showing the construction of a DPCM coding device based on first-order prediction, which is the most simple. A sampled value X i is input through an input terminal 1 and applied to a subtractor 2, where a predicted value (in this example, a first-order decoded value) which will be described later is subtracted from the sampled value X i . A quantizer 3 quantizes the differential value output from the subtractor 2 and supplies the quantized differential to an output terminal 8 as a DPCM code Y i . Simultaneously, the DPCM code Y i is applied to an inverse quantizer 4. The inverse quantizer 4 decodes the DPCM code Y i into the differential value and applies it to an adder 5. In the adder 5, the first-order predicted value applied to the subtractor 2 is added to the differential value, and thus the original sampled value is recovered from the differential value. A limiter 6 limits the amplitude of the output of the adder 5 within a predetermined range and supplies the result to a D-type flip flop 7. The output of the D-type flip flop 7 is supplied to the subtractor 2 and the adder 5 as the predicted value for the succeeding sampled value. In general, the distribution of differential values with respect to first-order predicted values is biased to a small-value portion. Accordingly, if the differential values are coded and transmitted, information can be transmitted in a compressed form. However, in a case where signals of high sampling frequencies such as HDTV (high-definition television) signals are handled, even if a high-speed logic IC is used, it is impossible to complete, within one sampling period, the requisite arithmetic operations within a DPCM loop (the loop from the input of the sample value X i to the finding of a local decoded value which is the input to the D-type flip flop 7). For this reason, in order to handle such signals of high sampling frequencies, it is necessary to incorporate parallel processing. For example, for the case of a sampling frequency of 48.6 MH z , the sampling period is 20.5 ns. In this case, even if "FAST" which is a high-speed TTL-IC is used as a logic IC and even if a high-speed PROM is used as the quantizer 3, approximately 165 ns will be needed as the time interval for completing all the arithmetic operations within the, DPCM loop. Since 165/20.5=8.05, the number of parallel processings is nine, that is to say, nine identical circuits are required. As a matter of course, if even more complex processing is to be performed, the number of parallel processings must be increased even further. In addition, if the parallel processing is adopted, a circuit for dividing a signal into nine phases and a circuit for multiplexing the nine signals thus divided would also be required. As a result, the construction of the requisite hardware becomes complicated and the scale thereof extremely large. Furthermore, if the quantizing characteristics of the quantizer are to be altered so that a coding device having the above-described arrangement may be adapted to various applications, the hardware construction of the quantizer itself must also be changed. Accordingly, it has heretofore been very difficult to change the quantization characteristics. As mentioned above, the quantizer 3 can be implemented as a high-speed PROM, and it is known that in general a logic circuit can be implemented as a truth table in a memory. This is discussed, for example, in "Digital Logic Techniques, Tutorial Guides in Electronic Engineering 6" T.J. Stonham, 1984, Van Nostrand Reinhold (UK) Co. Ltd, Wokingham, GB, pages 103 to 108, and in "Halbleiter-Schaltungstechnik" U. Tietze and Ch. Schenk, 5th Edition 1980, Springer-Verlag, Berlin & Heidelberg, DE, pages 486 to 493 and pages 517 to 525. Figure 6.6 of "Digital Logic Techniques" shows a schematic of a memory receiving address inputs from an external input and feedback DFFs (flip-flops), and providing outputs externally and to the DFFs. However, it is also known (and discussed in "Halbleiter - Schaltungstechnik") that a limit is reached very quickly with complex logic systems at which the required memory capacity increases excessively. US-A-4540973 (EP-A-0117525) teaches that in the case of DPCM, the use of a ROM as the quantizer requires an extremely large memory space, and proposes a strategy for reducing the memory space required. SUMMARY OF THE INVENTION According to the present invention, there is provided a high-definition television image data processing apparatus as set out in claim 1. The remaining claims set out optional features. An embodiment of the present invention provides a high-definition television image data processing apparatus having a predictive coding device which has a simplified hardware construction and which is capable of effecting high-speed coding. An embodiment of the present invention provides a high-definition television image data processing apparatus having a predictive coding device which can be adapted to use various codes and which has a simplified circuit construction. Embodiments of the present invention, given by way of non-limiting example, will now be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a block diagram showing an example of the construction of a conventional type of DPCM coding device; Fig.2 is a block diagram showing the construction of a coding device according to a first embodiment of the present invention; Fig.3 is a block diagram showing the construction of a decoding device which corresponds to the coding device of Fig.2; Fig. 4 is a block diagram showing the construction of a coding device according to a second embodiment of the present invention; and Fig. 5 is a block diagram showing the construction of a decoding device which corresponds to the coding of Fig. 4. DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described below with reference to Figs. 2 through 5. Fig. 2 is a block diagram showing the construction of a predictive coding device according to a first embodiment of the present invention. The first embodiment includes an input terminal 10 for receiving an 8-bit sampled value x i , a ROM (read-only memory) 12 that stores, in the form of a table, data representative of the arithmetic operations required for DPCM processing, an output terminal 14 through which a 4-bit DPCM code y i is output, and a D-type flip flop 16 which performs the same function as the D-type flip flop 7 of Fig. 1. The input sampled value x i from the input terminal 10 and a predicted value x and i are supplied to an address input of the ROM 12. In consequence, the 8-bit input sampled value x i and the 8-bit predicted value x and i are combined into a 16-bit address signal for the ROM 12. The ROM 12 stores in advance DPCM codes and local decoded values which are associated with combinations of the input sampled value x i and the predicted value x and i . Such input-output relationship can be determined purely mathematically, and it is not excessively difficult to obtain each value in the table. In response to an address signal consisting of the input sampled value x i and the predicted value x and i , the ROM 12 outputs the corresponding DPCM code and local decoded value to the output terminal 14 and the D-type flip flop 16, respectively. The time period required for this output is extremely short, concretely one readout cycle time. The primary difference between the circuits of Figs. 1 and 2 resides in the fact that the table in the ROM 12 performs the processing of the circuits which are arranged in a block 9 defined by a dashed line Fig. 1. If it is assumed that the input sampled value x i is 8 bits and the DPCM code y i is 4 bits (the compression ratio: 1/2), the capacity of the ROM 12 which is required to construct the table described above is 64K × 12 bits. Presently, ROMs of large capacity have been developed by utilizing MOS-LSI technology. If, for example, a ROM of 32x 8 (whose access time is 70 ns) is employed, the number of IC's required to realize the ROM 12 is 2 × 2 + 2 = 6, including two address decoding IC's. The number N of parallel processings is [(70 + 8) / 20.5 ] + 1 = 4 (where the square brackets denote that the number between is rounded to the next integer of equal or lower value); and the total number of IC's used in the overall DPCM circuit is 6 × 4 = 24. In a case where a logic IC is used, as in the conventional example, the number of parallel processings is nine and therefore the number of IC's increases at each processing section. In contrast, in the present embodiment, the number of IC's is about 1/3 that of the IC's used in the conventional example and, therefore, the number of IC's required can be greatly reduced. In the future, if a ROM with an even higher processing speed and capacity is developed with further improvements in semiconductor technology, the amount of hardware needed will be reduced further. It is to be noted that, if either the input sampled value x i or the predicted value x and i is known, the dynamic range of the differential value can be compressed to about 1/2. More specifically, if the input value x i has n levels from 0 to n - 1, the range of values which the differential value can take on corresponds to n levels with (n - 1 - x and i ) to - x and i . Accordingly, the dynamic required in this embodiment is about half the dynamic range (2n - 1) of the differential value described above in connection with the conventional example. For this reason, in the coding device of this embodiment, the individual values in the table are determined so that quantization can be effected in accordance with the dynamic range (n levels) based on the predicted value input to the ROM 12. Accordingly, the quantization of this embodiment is substantially equivalent to quantization employing twice as many levels as those used in the conventional DPCM coding device, whereby image quality can be greatly enhanced. In the above-described embodiment, if input-output characteristics associated with coding operations are known, as long as the number of input bits and output bits are identical, the contents of coding operations can be changed by replacing the ROM 12 with a ROM having a table with a corresponding input-output relationship. In other words, the coding device of this embodiment can be adapted to a variety of coding devices without any need for the circuit wiring itself to be changed. In addition, if the number of input bits or output bits needs to be changed,it is sufficient that a ROM adapted to the desired number is prepared and the design is changed so as to accommodate the bit width of a signal channel. Accordingly, it will be appreciated that, as compared with the conventional example using a logic circuit constituted by a combination of logic IC's, the coding device of the above embodiment enables changes in the contents of coding operations to be easily effected and can, therefore, be adapted to various applications. Fig. 3 is a block diagram of a decoding device (on the receiving side) which corresponds to the coding device of Fig. 2. In the illustrated decoding device, an input terminal for receiving the DPCM code y i is denoted by reference numeral 20, and a ROM 22 stores a decoding table. When the DPCM code y i and the predicted value (first-order predicted value) x and i (which will be described later) are input to the address section of the ROM 22, the ROM 22 provides a corresponding decoded value at an output terminal 24 with memory access time. Simultaneously, the decoded value output from the ROM 22 is applied to a D-type flip flop 26. The output of the D-type flip flop 26 is applied back to the ROM 22 as the predicted value x and i . The table of the ROM 22 is determined in correspondence with the table of ROM 12 at the transmitting side. Accordingly, this embodiment is arranged to allow the range of inverse quantization for decoding to be determined in accordance with the predicted value. For example, if it is assumed that the DPCM code y i is represented by 4 bits, the decoded value output from the ROM 22 by 8 bits, and the predicted value x and i output from the D-type flip flop 26 by 8 bits, the capacity of the ROM 42 is 4K × 8 and hence the decoding table can be realized by a single IC. Furthermore, since the cycle time of the ROM 42 is approximately 35 ns, the number of parallel processings is two. Accordingly, it is possible to greatly reduce the scale of the requisite hardware. The above description refers to first-order predictive DPCM for the purpose of illustration, but the range of application of the embodiment described above is not limited to first-order prediction. For example, the embodiment can be adapted to various other DPCM schemes based on second-order prediction, third-order prediction and adaptive prediction. Furthermore, the embodiment can be adapted to coding schemes of the type which allows determination of arbitrary code length. Fig. 4 is a block diagram showing the construction of the essential portion of a coding device according to a second embodiment of the present invention. The illustrated device includes an output terminal 31 for receiving the 8-bit sampled value x i , a RAM (random access memory) 39, an input terminal 38 through which a DPCM code y i is output, and a D-type flip flop 37 which has a function similar to that of the D-type flip flop 7 of Fig. 1. An input sampled value x i at the input terminal 31 and an 8-bit predicted value x and i output from the D-type flip flop 37 are supplied to corresponding address input of the RAM 39. In consequence, the 8-bit input sampled value x i and the 8-bit predicted value x and i constitute an 16-bit address signal for the RAM 39. An external storage device 40 is supplied with a load signal through a terminal 41, for example, after an electrical power source (not shown) has been switched on. In response to the load signal, the storage device 40 loads a DPCM table containing a DPCM coding code which is the result of predetermined DPCM arithmetic operations as well as a corresponding local decoded value into the RAM 39 in a sequential manner. The values can be determined purely mathematically, and it is not excessively difficult to find individual data in the table. The storage device 40 may be of a type whose access time is long, only if it has storage capacity which can accommodate a predetermined DPCM table. For example, the storage device 40 may be constituted by a semiconductor memory such as an EPROM or a magnetic recording/reproducing device such as a magnetic disk. In response to an address signal consisting of the input sample value xi and the predicted value x and i , the RAM 39 outputs a DPCM code and a local decoded value to the output terminal 38 and the D-type flip flop 37, respectively. That is to say, the RAM 39 used in the embodiment shown in Fig. 4 performs the function of the block 9 shown by the dashed line in Fig. 1. The time period required for this output is extremely short, concretely one readout cycle time. If it is assumed that the input sampled value xi is 8 bits with the DPCM code yi 4 bits (the compression ratio:1/2), the capacity of the RAM 39 which is required to construct the table described above is 64K × 4 bits. Presently, SROMs of large capacity and high speed have been developed by various manufacturers. If, for example, a ROM having a capacity of 64K × 8 bits and an access time of 35 ns is employed, the number of IC's required to construct the DPCM table is three. If the number of latch IC's and address decoding IC's required to load the DPCM table is included, the number of IC's per DPCM coder is eight (3 + 4 + 1) . The number of parallel processings is two since 35 ns/20.5 ns = 1.7, and the total number of IC's used in the overall DPCM coder is 2 × 8 = 16. If a logic IC is employed, as in the conventional example shown in Fig. 1, the number of parallel processings is nine and, therefore, the number of IC's used in the individual processing circuits increases. In contrast, since the number of IC's used in this embodiment is about 1/6 that of IC's used in the conventional example, the number of IC's required can be greatly reduced. In the above-described embodiment, if input-output characteristics associated with coding operations are known, as long as the number of input bits and output bits are identical, then no matter how complex the algorithm, the can be realized by an identical circuit arrangement simply by updating the contents of the DPCM table. Further, since the table is constituted by the SRAM, it is very easy to alter algorithms. For example, in a case where a magnetic disk device is used as the storage device 40, the algorithm can be altered by the replacement of magnetic disks. Furthermore, since the external storage device 40 may be of a type whose access time is long, it is possible to use an inexpensive and large-capacity storage such as a magnetic disk and hence to set a multiplicity of algorithms. Fig. 5 is a block diagram of the construction of the essential portion of a decoding device which corresponds to the coding device of Fig. 4. In the illustrated decoding device, an input terminal for receiving the DPCM code y i transmitted from the above-described coding device is denoted by reference numeral 43. A RAM 43 stores a decoding table, and the DPCM code y i and the predicted value x and i (which will be described later) are applied to corresponding address inputs of the RAM 43. An external storage device 46 is supplied with a load signal through a terminal 47, for example, after an electrical power source (not shown) has been switched on. In response to the load signal, the storage device 46 loads a table containing DPCM decoded values into the RAM 43 in a sequential manner. When the above-described DPCM code y i and predicted value x and i are input to the RAM 43, the RAM 43 applies a corresponding decoded value in the loaded table to an output terminal 45. Simultaneously, the decoded value output from the RAM 43 is applied to a D-type flip flop 44. The output of the D-type flip flop 44 is applied to the RAM 43 as the predicted value x i . For example, if it is assumed that the DPCM code y i is constituted by 4 bits, the decoded value output from the RAM 43 by 8 bits, and the predicted value x i output from the D-type flip flop 44 by 8 bits, the capacity of the RAM 43 is 4K × 8 bits and hence the decoding table can be realized by using a single IC. Furthermore, since the cycle time of the RAM 43 is approximately 35 ns, the number of parallel processings is two. Accordingly, it is possible to greatly reduce the scale of the requisite hardware. The table to be stored in the RAM 43 is determined in correspondence with the table stored in the RAM 39 at the transmitting side. The above description refers to first-order predictive DPCM for the purpose of illustration, but the range of application of the embodiment described above is not limited to first-order prediction. For example, the embodiment can be adapted to various other DPCM schemes based on higher-order prediction (e.g. second-order prediction, third-order prediction) and adaptive prediction. Furthermore, the embodiment can be adapted to a coding or decoding system whose code length can be arbitrarily determined. Furthermore, although, in the above embodiment, an SRAM is used as RAM, a DRAM may be employed if the conditions required for refresh and cycle time are satisfied. It will be appreciated from the foregoing that,in accordance with the present invention, it is possible to provide a coding and decoding system capable of effecting high-speed coding and decoding. Accordingly, the scale of hardware in the overall system can be reduced. In addition, since the algorithm of arithmetic operations required for coding and decoding can be altered by changing tables to be loaded into the RAM, the system of the invention can be adapted to a variety of applications by using an identical circuit arrangement. Accordingly, it is possible to construct a system which can be used for numerous purposes.

Claims: A high-definition television image data processing apparatus having at least one device for coding said image data, which device comprises: (i) predictive coding means for providing: (a) a coded value (Yi) representing the result of quantising the difference between an input value (Xi) and a predicted value (X andi); and (b) a local decoded value ( X i) corresponding to the input value (Xi), representing the result of adding the predicted value (X andi) and a decoded difference corresponding to the coded value (Yi); and (ii) predictor means (7, 16, 37) for receiving the local decoded value ( X i) and outputting the predicted value (X andi), characterised in that the predictive coding means (9) comprises memory means (12, 39) receiving the input value (Xi) and the predicted value (X andi) as address inputs and acting as a look-up table to provide the coded value (Yi) and the local decoded value ( X i) as outputs from a common memory. An apparatus according to claim 1 in which the common memory is a ROM (12). An apparatus according to claim 1 in which the common memory is a RAM (39). An apparatus according to claim 3 further comprising means (40) to change a look-up table in the RAM (39). An apparatus according to any one of the preceding claims in which the predictor means (7,16, 37) comprises delay means which delays the local decoded value ( X i) and provides the delayed local decoded value as the predicted value (X andi). An apparatus according to any one of the preceding claims having a plurality of said devices which are operable in parallel to code said image data; means for dividing input image data between said plurality of devices; and means for combining the coded values (Yi) output by said devices.

Inventors: ISHIKAWA HISASHI, ISHIKAWA, HISASHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1989
Main classification: H03M3
IPC codes: H03M3