Self-scanning light-emitting element array

Abstract: A self-scanning light-emitting element array comprises a coupled array of light-emitting elements (T(-2), T(-1), T(0), T(1), T(2)) constituted so that a light-emittng element (T(0)) which is turned on influences (L₁) a light-emitting element (T(1)) to be turned on next so that its threshold level is changed. When each element is clock-driven by a common drive pulse, the change in threshold level is shifted in the array direction, so that a turn-on operation is transferred in a clock period of the drive pulse.

Description: The present invention relates to a self-scanning type light-emitting element array in which light-emitting elements are integrated on a single substrate and a method of driving the same. As typical light-emitting elements, an LED (light-emitting diode) and an LD (laser diode) are known. In the LED, a pn or pin junction of a compound semiconductor (GaAs, GaP, GaAlAs or the like) is formed, and a forward bias voltage is applied to the junction so as to inject carriers in the junction. The LED utilizes a light-emission phenomenon occurred by carrier recombination. In the LD, a waveguide is arranged in the LED. When a current exceeding a given threshold value is supplied, injected electron-hole pairs are increased, and a population inversion state is established. Light generated by parallel reflection mirrors utilizing a cleavage surface is fed back to an active layer, thus causing laser oscillation. Then, a laser beam is emitted from an end face of the waveguide. Negative resistance elements (light-emitting thyristor, laser thyristor and the like) are known as a light-emitting element having the same light-emission mechanism as those of the LED and LD. In the light-emitting thyristor, a pnpn structure is formed by a compound semiconductor described above, and a thyristor using silicon is put into practical applications. Figs. 22 and 23 show the basic structure and current-voltage characteristics of the negative resistance element having the light-emission function (called a light-emitting thyristor herein). The structure shown in Fig. 22 is the same as that of a thyristor in which a pnpn structure is formed on an n-type GaAs substrate. Fig. 23 also represents the same S-shaped negative resistance characteristics as those of the thyristor. Not only a two-terminal thyristor shown in Fig. 22 but also a three-terminal thyristor shown in Fig. 24 are also known. The gate of the three-terminal thyristor has a function of controlling an ON voltage. The ON voltage is converted to a voltage as a sum of a gate voltage and a diffusion potential. After the thyristor is turned on, the gate electrode voltage substantially coincides with the cathode voltage. If the cathode electrode is grounded, the gate electrode voltage becomes zero volt. As is well known, a threshold voltage of the light-emitting thyristor is decreased when light is externally incident thereon. A waveguide can be formed in the light-emitting thyristor to form a laser thyristor by quite the same principle as the LD (Tashiro el al., Lecture to the Japan Society of Applied Physics, Autumn 1987, No.18p-ZG-10). The light-emitting element described above, in particular, the LED is commercially available in such a manner that a large number of elements are formed on a compound semiconductor substrate and are cut into pieces and are packaged one by one. An LED for a contact image sensor and a light source for a printer is commercially available as an LED array in which a plurality of LEDs are arrayed on a single chip. A contact image sensor, an LED printer, and the like require a scanning function of light-emitting points by these light-emitting elements in order to designate read or write points. However, in order to perform optical scanning using the above-mentioned conventional light-emitting elements, each LED formed in the LED array must be connected to a drive IC by wire bonding or the like, and must be driven by the IC. For this reason, if a large number of LEDs are arranged, the wire bonding must be performed for portions corresponding in number to the LEDs, and a large number of drive ICs are required, resulting in high cost. A space for arranging drive ICs must be assured, and it is difficult to achieve a compact array. A pitch between adjacent LEDs is determined depending on the wire bonding technique, and it is difficult to decrease the pitch. A self-scanning light-emitting array in which the light-emitting elements are optically coupled is known from the article by Z. Tani et al. : "Light spot scanner on a gallium arsenide strip", in: Solid-State Electronics, vol. 20, No.5 (1977), pages 469-472. An array in which the light-emitting elements are electrically coupled is described in JP-A-60 201 679. This invention provides a self-scanning light-emitting array comprising: an array of light-emitting elements having controllable turn-on threshold levels; at least two transfer lines alternatingly connected in sequence in an array direction to alternating ones of said light-emitting elements; polyphase clock means connected to said transfer lines and arranged to apply drive pulses repeatedly in sequence to said transfer lines; and coupling means for coupling said light-emitting elements so that a light-emitting element in at least a threshold-reduced state reduces the turn-on threshold level of the next light-emitting element in the direction of scanning whereby said next light-emitting element is capable of responding to a respective drive pulse by entering the threshold-reduced state; characterised in that means responsive to a light emission signal specifying light-emitting elements at particular positions in the array to emit light, are arranged to supply additional current to said transfer lines whereby respective light-emitting elements in a threshold-reduced state at said particular positions receive the additional current. The invention will now be described by way of non-limiting embodiments, which are not all embodiments of the invention, with reference to the accompanying drawings, in which:- Fig. 1 is a schematic circuit diagram of a light-emitting element array using light in an embodiment A-1; Fig. 2 is a schematic section view of a light-emitting element array using light in an embodiment A-2; Fig. 3 is a schematic plan view of a light-emitting element array using light in an embodiment A-3; Figs. 4 and 5 are schematic sectional views of the light-emitting element array using light in the embodiment A-3; Fig. 6 is a schematic sectional view of a light-emitting element array using light in an embodiment A-4; Fig. 7 is a schematic plan view of a light-emitting element array using light in an embodiment A-5; Fig. 8 is a schematic sectional view of the light-emitting element array using light in the embodiment A-5; Fig. 9 is a schematic circuit diagram of a light-emitting element array using a potential in an embodiment B-1; Fig. 10 is a schematic sectional view of a light-emitting element array using a potential in an embodiment B-2; Fig. 11 is a schematic plan view of a light-emitting element array using a potential in an embodiment B-3; Figs. 12 and 13 are schematic sectional views of the light-emitting element array using a potential in the embodiment B-3; Fig. 14 is a schematic plan view of a light-emitting element array using a potential in an embodiment B-4; Fig. 15 is a schematic sectional view of the light-emitting element array using a potential in the embodiment B-4; Fig. 16 is a schematic circuit diagram showing a method of driving a light-emitting element array in an embodiment C and a timing chart showing pulse waveforms; Fig. 17 is a schematic sectional view of a proximity image sensor in an application 1; Fig. 18 is a schematic sectional view of an optical printer in an application 2; Fig. 19 is a schematic sectional view of an optical printer head in the application 2; Fig. 20 is a schematic plan view of an optical display in the application 2; Fig. 21 is a schematic sectional view showing a structure of a light-emitting thyristor of a double-hetero structure; Fig. 22 is a schematic sectional view showing a structure of a light-emitting thyristor; Fig. 23 is a graph showing current-voltage characteristics of the light-emitting thyristor; Fig. 24 is a schematic sectional view showing a structure of a three-terminal thyristor; Fig. 25 is an equivalent circuit diagram of a light-emitting element array in an embodiment D-1; Fig. 26 is a graph showing characteristics of the light-emitting thyristor; Fig. 27 is a sectional view of an embodiment D-2; Fig. 28 is a plan view of the embodiment D-2; Fig. 29 is a plan view of an embodiment D-3; Fig. 30 is a sectional view of an embodiment D-3; Fig. 31 is a plan view of an embodiment D-4; Fig. 32 is a sectional view of an embodiment D-4; Fig. 33 is an equivalent circuit diagram of a light-emitting element array in an embodiment E-1; Fig. 34 is a circuit diagram showing a pn image of the equivalent circuit diagram of the embodiment E-1; Fig. 35 is a sectional view of an embodiment E-2; Fig. 36 is an equivalent circuit diagram of a light-emitting element array in an embodiment F-1; Fig. 37 is a schematic view showing a structure of a light-emitting element array in an embodiment F-2; Figs. 38 and 39 are respectively a plan view and a sectional view of a light-emitting element array in an embodiment F-3; Fig. 40 is an equivalent circuit diagram of a light-emitting element array in an embodiment F-4; Fig. 41 is an equivalent circuit diagram of a light-emitting element array in an embodiment F-5; Figs. 42 and 43 are respectively a plan view and a sectional view of a light-emitting element array in an embodiment F-6; Fig. 44 is an equivalent circuit diagram of a light-emitting element array in an embodiment F-7; Figs. 45 and 46 are respectively a plan view and a sectional view of a light-emitting element array in an embodiment F-8; Fig. 47 is an equivalent circuit diagram showing an embodiment G-1; Fig. 48 is a sectional view showing an embodiment G-2; Fig. 49 is a plan view showing an embodiment G-3; Figs. 50 and 51 are sectional views showing the embodiment G-3; Fig. 52 is a schematic view showing a basic structure of embodiments H; Fig. 53 is an equivalent circuit diagram of an embodiment H-1; Fig. 54 is a partial plan view of the embodiment H-1; Fig. 55 is a sectional view of a laser thyristor portion of the embodiment H-1; Fig. 56 is a sectional view of a light deflector portion of the embodiment H-1; Fig. 57 is a perspective view of the laser thyristor portion and the light deflector portion; Fig. 58 is a drive timing chart of the embodiment H-1; Fig. 59 is an equivalent circuit diagram of an embodiment H-2; Fig. 60 is a perspective view showing a structure of a light deflector used in the embodiment H-2; Fig. 61 is a view showing the principle of an optical scanning system by deflection; and Fig. 62 is a view showing the principle of an optical scanning system using an array. Embodiments A Embodiments A to be described hereinafter utilize light as an interaction medium between the elements. (Embodiment A-1) Fig. 1 is an equivalent circuit diagram of the principle of an embodiment A-1. This diagram illustrates a case wherein a most typical three-terminal light-emitting thyristor is used as an example of a light-emitting element whose light-emission threshold voltage and current can be externally controlled. Light-emitting thyristors T (-2) to T (+2) are arrayed in a line. Each of three transfer clock lines ( 1 ,  2 and  3 ) is connected to the corresponding anode electrodes of every three light-emitting elements. A light-emitting thyristor has characteristics that its turn-on voltage is decreased when it senses light. When light-emitting thyristors are arranged so that light emitted from an ON light-emitting element is incident on another interacting light-emitting element, the turn-on voltage of an element near the ON element or an element which is arranged to sufficiently receive light from the ON element is decreased. The operation of the equivalent circuit diagram of Fig. 1 will be described below. Assume that a high-level pulse voltage is applied to the transfer clock line  3 , and a light-emitting thyristor T (0) is kept on. Light L I emitted from the light-emitting thyristor T (0) is incident on light-emitting thyristors T (-1) and T (+1) , thus decreasing their ON voltages. Since the light-emitting thyristors T (-2) and T (+2) are located farther than the light-emitting thyristors T (-1) and T (+1) , incident light is weak, and their ON voltages are not so much decreased. In this state, a high-level pulse voltage is applied to the next clock line  1 . Since the ON voltage of the light-emitting thyristor T (+1) is decreased by the influence of light as compared to that of the light-emitting thyristor T (-2) , if the high-level voltage of the transfer clock is set to be a value between the ON voltages of the light-emitting thyristors T (+1) and T (-2) , only the light-emitting thyristor T (+1) is turned on, and the light-emitting thyristor T (-2) can be kept off. Thus, the light-emitting thyristors T (+1) and T (0) are simultaneously turned on. When a low-level voltage is applied to the clock line  3 , the light-emitting thyristor T (0) is turned off and only the light-emitting thysistor T (+1) is turned on. Thus, an ON state is transferred. Based on the above-mentioned principle, the high-level voltages of the transfer clocks  1 ,  2 and  3 are set to slightly overlap each other, the ON states of the light-emitting elements are sequentially transferred. More specifically, a light-emission point is sequentially transferred. According to this embodiment, a self-scanning type light-emitting element array which cannot be achieved by the prior art can be realized. (Embodiment A-2) In the embodiment A-1, an equivalent circuit has been presented and described. In an embodiment A-2, an IC structure of the arrangement of the embodiment A-1 will be described below. Fig. 2 is a schematic view of the structure. A p-type semiconductor layer 23, an n-type semiconductor layer 22, and a p-type semiconductor layer 21 are formed on a grounded n-type GaAs substrate 1. The multilayered structure is patterned into light-emitting elements T (-2) to T (+2) by photolithography and the like and etching. Each electrode 40 makes an ohmic contact with the corresponding p-type semiconductor layer 21, and an insulating layer 30 serves as a protection film for preventing short-circuiting between an element and a wiring and at the same time preventing deterioration of characteristics. The insulating layer 30 is formed of a material which allows light having a light-emission wavelength of a light-emitting thyristor to pass therethrough. The p-type semiconductor layer 21 serves as an anode of this thyristor, and the n-type GaAs substrate 1 serves as a cathode. Each of three transfer clock lines ( 1 ,  2 and  3 ) is sequentially connected to the anode electrodes 40 of every three light-emitting elements. It is generally known that the ON voltage of a light-emitting thyristor is changed depending on an amount of light incident on the element. Therefore, if the light-emitting thyristors are arranged so that light emitted from an ON light-emitting thyristor is incident on adjacent light-emitting thyristors, the ON voltages of the light-emitting thyristors adjacent to the ON thyristor are decreased as compared to a case wherein no light is emitted. In the structure illustrated in Fig. 2, the insulating layer 30 is formed of a transparent film with respect to a light-emission wavelength. If a light-emitting thyristor T (0) is in an ON state, light L 0 is emitted upward, and light L I is well input to adjacent elements T (-1) and T (+1) , thus decreasing their ON voltages. The operation of the light-emitting element array is the same as that in the embodiment A-1. Based on the above-mentioned principle, the high-level voltages of the transfer clocks  1 ,  2 and  3 are set to slightly overlap each other, the ON states of the light-emitting elements are sequentially transferred. More specifically, a light-emission point is sequentially transferred. According to this embodiment, an integrated self-scanning type light-emitting element array utilizing light coupling, which cannot be achieved by the prior art, can be realized. (Embodiment A-3) In this embodiment, a practical structure of the embodiment A-2 will be described. Fig. 3 is a plan view of this embodiment, and Figs. 4 and 5 are sectional views taken along lines X-X' and Y-Y' in Fig. 3, respectively. Isolation grooves 50 are formed between adjacent ones of light-emitting elements T (-2) to T (+1) . Light barriers 61 are partially formed in the isolation grooves 50 so as not to cause light from an ON light-emitting element to become incident on elements other than two adjacent elements. In this embodiment, projections of a field 60 are used as the light barriers 61. However, other materials may be used, or other shapes may be employed. A contact hole C 1 is formed in an upper electrode of each light-emitting element, and is electrically connected to an electrode 40. A contact hole C 2 is a through hole to be connected to a corresponding one of transfer clock lines  1 ,  2 and  3 . The transfer clock line  1 is connected to the light-emitting elements T (-2) and T (+1) , the transfer clock line  2 is connected to the light-emitting element T (-1) , and the transfer clock line  3 is connected to the light-emitting element T (0) . Fig. 4 is sectional view taken along a line X-X' in Fig. 3. This line is parallel to the array direction of the light-emitting element array, and Fig. 4 reveals a state of the light-emitting elements arrayed in a line. An insulating film 30 for preventing short-circuiting between each light-emitting element and the electrode 40 and an insulating film 31 as an insulating interlayer for preventing short-circuiting between the electrode 40 and the transfer clock line are formed to surround the isolation groove 50 so as to be adjacent to the isolation groove 50 of each light-emitting element. These insulating films 30 and 31 are formed of transparent insulating films so as not to interfere light coupling between adjacent elements, or may be formed of insulating films which can properly absorb light so as to be able to adjust light coupling between adjacent elements. Furthermore, an insulating film 31 which properly absorbs light and a transparent insulating film may be stacked to have an appropriate film thickness. With this structure, light coupling between adjacent elements can be established, and a transfer operation (light scanning operation) can be performed. The film structure of the light-emitting element is the same as that shown in Fig. 21 (to be described later). Fig. 5 is a sectional view taken along a line Y-Y' in Fig. 3. This line is perpendicular to the array direction of the light-emitting element array, and Fig. 5 reveals a connection state of wirings and electrodes. The contact hole C 1 led to the upper electrode of each light-emitting element is formed in the insulating film 30, and is externally led to an external portion through the electrode 40. The electrode 40 is connected to the transfer clock line  3 via the through hole C 2 . A manufacturing process for realizing this embodiment is as follows. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer are sequentially formed and stacked on an n + -type GaAs substrate 2 by epitaxial growth. The isolation grooves 50 are formed using a photoetching technique. Thereafter, the insulating film 30 is formed, and the contact holes C 1 are formed therein using the photoetching technique. A metal electrode layer is then formed by a deposition or sputtering method, and the electrodes 40 are formed using the photoetching technique. The insulating film 31 is formed, and the through holes C 2 are formed using the photoetching technique. A metal wiring layer is formed by the deposition or sputtering method, and the transfer clock lines ( 1 ,  2 and  3 ) are formed by the photoetching technique. With the above-mentioned process, the structure of this embodiment is completed. Although not described in this embodiment, a transparent protection film may be formed on the transfer clock lines. If it is not preferable that the thickness of the insulating film is too large to degrade a transmittance of light and to decrease an amount of externally output light, part or all of the upper insulating film of the light-emitting element may be removed by, e.g., photoetching. According to this embodiment, an integrated self-scanning light-emitting element array can be manufactured. (Embodiment A-4) In the embodiments A-2 and A-3, the light-emitting thyristor is adopted as the light-emitting element. However, the present invention is not limited to this, various other light-emitting elements may be adopted. In this embodiment, for example, a case will be described below wherein a laser thyristor is used. Fig. 6 is a sectional view when a laser thyristor is used as a light-emitting element. Light-emitting elements (laser thyristors) T (-1) to T (+1) are formed to have the following structure. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (non-doped) GaAs layer 123, an n-type AlGaAs layer 122, and a p-type AlGaAs layer 121 are sequentially stacked on an n-type GaAs substrate 1. The p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are patterned as shown in Fig. 6. The shape illustrated in Fig. 6 is the same as that of a conventional stripe type laser diode. The entire width of the p-type AlGaAs layer 121 and the partial width of the n-type AlGaAs layer 122 are 10 µm or less. Other portions are the same as those in Figs. 2 to 5 described above. In an operation of the laser thyristor, the same operation as in a conventional light-emitting thyristor is performed until a current component supplied to the thyristor reaches a laser oscillation current, and light emitted by a current component below the laser oscillation current is isotropically output. A laser beam is output in a direction perpendicular to the sheet surface of Fig. 6. Therefore, the laser beam does not contribute to light coupling between adjacent elements, and light emitted by a current component below the laser oscillation current contributes to light coupling. Other mechanisms of the transfer operation are the same as those in the embodiment A-2. (Embodiment A-5) Figs. 7 and 8 show an embodiment A-5 presenting a practical structure of the embodiment A-4. Fig. 7 is a plan view, and Fig. 8 is a sectional view taken along a line X-X' in Fig. 7. A manufacturing method of the structure shown in Fig. 7 will be briefly described below. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (non-doped) GaAs layer 123, an n-type AlGaAs layer 122, a p-type AlGaAs layer 121, and an upper electrode layer 20 are sequentially stacked on an n-type GaAs substrate 1 (a p-type GaAs layer for improving an ohmic contact may be formed between the p-type AlGaAs layer 121 and the upper electrode layer 20). The upper electrode layer 20 is patterned into a rectangular shape having the same width as that of the n-type AlGaAs layer 125 in Fig. 8. Using the electrode pattern 20 as a mask, the p-type AlGaAs layer 121 to the n-type AlGaAs layer 125 are etched. In this case, element isolation grooves 50 are formed. The upper electrode pattern 20 is further etched into a stripe shape having a width of 10 µm or less. Using the new electrode pattern 20 as a mask, the p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are etched. The n-type AlGaAs layer 122 is not entirely removed but is partially left. An insulating film 30 is formed on the resultant structure, and through holes C2 are formed by photoetching. Thereafter, a metal wiring layer for transfer clock lines are formed by deposition or sputtering, and the transfer clock lines ( 1 ,  2 and  3 ) are formed by photoetching. Finally, the end face of a laser beam output side is formed by cleavage or the like to have good parallelism, thus completing the structure of this embodiment. In a conventional integrated light-emitting element array, pn junction diodes are independently formed on a single substrate, are externally led one by one using a wire bonding technique, and are operated by applying a voltage by drive ICs. Thus, assembly such as a wiring bonding process is cumbersome, resulting in high cost. In contrast to this, in a light-emitting element array of this embodiment, three transfer clock terminals need only be externally lead, and assembly is considerably simplified. At the same time, a space for drive ICs can be omitted, and a compact self-scanning light-emitting element array as a whole can be produced. In a conventional array, an alignment pitch of light-emitting elements is predetermined depending on the bonding technique. However, the above-mentioned embodiments A-1 to A5 are free from such a restriction, and a light-emitting element array having a smaller pitch can be manufactured. Thus, an application to a device having a very high resolution can be achieved. In the embodiments A-1 to A-5, the transfer clock pulses are assumed to have three phases, i.e.,  1 ,  2 and  3 . The number of phases may be increased to four or five so as to attain a more stable transfer operation. A larger amount of light emitted by a light-emitting thyristor T (0) is caused to incident on a light-emitting thyristor T (+1) than to a light-emitting thyristor T (-1) , so that the elements can be driven by two-phase clocks. For example, light-emitting thyristors are arranged in an asymmetrical planar pattern, so that a larger amount of light is emitted to tlie right in the arrangement. In the above embodiment, the simplest structure of the light-emitting thyristor has been described. The scope of the present invention includes adaption of a more complex structure and a multilayer structure in order to increase light-emission efficiency. This also applies to many embodiments to be described later. For example, a double-hetero structure may be employed. Fig. 21 shows an example of the double-hetero structure (Tashiro et al., Lecture to the Japan Society of Applied Physics, Spring, 1987, No. 28p-ZE-8). In this structure, an n-type GaAs layer 24b (having a thickness of 0.5 µm) is formed on an n-type GaAs substrate 1. An n-type AlGaAs layer 24a (1 µm) having a wide band gap, a p-type GaAs layer 23a (5 nm), an n-type GaAs layer 22a (1 µm), a p-type AlGaAs layer 21b (1 µm) having a wide band gap, and a p-type GaAs layer 21a (0.15 µm) for making an ohmic contact with a lead electrode are sequentially stacked on the GaAs layer 24b. A light-emission layer is the n-type GaAs layer 22a (1 µm) sandwiched between the layers 23a and 21b. Injected electrons and holes are trapped in the GaAs layer 22a having a narrow band gap, and are recombined in this region to emit light. The light-emitting element need not always be a light-emitting thyristor, and is not particularly limited if its turn-on voltage is changed by light. For example, the above-mentioned laser thyristor may be employed. In the above embodiment, a pnpn thyristor structure has been exemplified. A structure whose threshold voltage is decreased by light and which is caused to perform a transfer operation by utilizing this function is not limited to the pnpn structure or any other specific structure if it can achieve the above function. For example, if a multilayered structure of six layers or more is employed in place of a pnpn four-layered structure, the same effect can be expected, and the same self-scanning function can be achieved. Furthermore, the same effect may be obtained if another type of thyristor, e.g., a static induction (SI) thyristor or a field control thyristor (FCT), is used. The SI thyristor or the FCT has a structure wherein a central p-type semiconductor layer serving as a current block is replaced with a depletion layer (S.M. Sze, Physics of Semiconductor Devices, 2nd Edition, pp. 238-240). In the embodiments A-1 to A-5, the light-emitting elements are arrayed in a line, but need not be arranged along a straight line. For example, the elements may be arranged in a zigzag manner depending on applications. The elements may be arranged in two lines from the halfway. According to the present invention, the light-emitting elements may be constituted by individual parts, or may be integrated by any means. Embodiments B Embodiments B described herein utilize a voltage as an interaction medium. (Embodiment B-1) The embodiments A-1 to A-5 shown in Figs. 1 to 8 utilize coupling by means of light. This embodiment utilizes coupling by means of a voltage. Fig. 9 is an equivalent circuit diagram of an embodiment B-1 of the present invention. The characteristic feature of this embodiment is that a resistor network is added to the arrangement in the embodiment A-1, i.e., Fig. 1. As light-emitting elements, light-emitting thyristors T (-2) to T (+2) are used. The light-emitting thyristors T (-2) to T (+2) have gate electrodes G -2 to G +2 , respectively. A power source voltage V GK is applied to each gate electrode through a corresponding load resistor R L . The gate electrodes G -2 to G +2 are electrically connected to each other through resistors R I to achieve an interaction. Each of three transfer clock lines  1 ,  2 and  3 is sequentially connected to the anode electrodes of every three light-emitting elements. An operation will be described below. Assume that the transfer clock  3 goes to high level, and the light-emitting element T (0) is turned on. In this case, a potential at the gate electrode G 0 is reduced to about 0 V due to the characteristics of the three-terminal thyristor (about 1 V for a silicon thyristor). Assuming that the power source voltage V GK is 5 V, the gate voltage of each light-emitting thyristor is determined by the network of the load resistors R L and the resistors R I . A gate voltage of an element nearest the light-emitting element T (0) is decreased by the largest amount, and a gate voltage is increased as an element is separated from T (0) . This can be expressed as follows: V G0 < V G-1 = V G-1 < V G2 = V G-2 A difference between these voltages can be set by appropriately selecting the values of the load resistors R L and resistors R I . As is well known, a turn-on voltage V ON at the anode side of the three-terminal thyristor is higher than a gate voltage V G by a diffusion voltage V df . V ON ≒ V G + V df Therefore, if a voltage applied to the anode is set to be higher than the turn-on voltage V ON , the corresponding light-emitting thyristor is turned on. In a state wherein the thyristor T (0) is kept on, a high-level voltage V H is applied to the next transfer clock pulse  1 . The clock pulse  1 is simultaneously applied to the light-emitting elements T (+1) and T (-2) . If the value of the high-level voltage V H is set to fall within the following range, only the light-emitting element T (+1) can be turned on. V G-2 + V df > V H > V G+1 + V df Thus, both the light-emitting elements T (0) and T (+1) are kept on. When the high-level voltage V H of the clock pulse  3 is disabled, the light-emitting element T (0) is turned off, and an ON state can be transferred. In this manner, the gate electrodes of the light-emitting thyristors are connected through the resistor network, thus providing a transfer function to the light-emitting elements. With the above-mentioned principle, the high-level voltages V H of the transfer clock lines  1 ,  2 and  3 are set to sequentially slightly overlap each other, so that the ON states of the light-emitting elements are sequentially transferred. More specifically, a light-emission point is sequentially transferred. According to this embodiment, a self-scanning type light-emitting element array which cannot be achieved by a prior art technique can be realized. (Embodiment B-2) In the embodiment B-1, the equivalent circuit has been exemplified. In the embodiment B-2, an IC structure of the arrangement of the embodiment B-1 will be described. Fig. 10 shows a structure of this embodiment. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22, and a p-type semiconductor layer 21 are sequentially formed on a grounded n-type GaAs substrate 1. Isolation grooves 50 for isolating the multilayered structure into light-emitting elements T (-1) to T (+1) are formed by, e.g., photolithography or the like and etching. Each anode electrode 40 has an ohmic contact with the p-type semiconductor layer 21, and each gate electrode 41 has an ohmic contact with the n-type semiconductor layer 22. An insulating layer 30 prevents short-circuiting between the elements and wiring layers, and also serves as a protection film for preventing deterioration of characteristics. The insulating layer 30 is preferably formed of a material which allows light having a light-emission wavelength of a light-emitting thyristor to pass therethrough well. The n-type GaAs substrate 1 serves as a cathode of each thyristor. Three transfer clock lines  1 ,  2 and  3 are connected to the anode electrodes of the light-emitting elements. The gate electrodes are connected to a resistor network through load resistors R L and interaction resistors R I . When light coupling described in the embodiment A occurs, it affects the transfer operation of this embodiment. The gate electrodes 41 are partially formed in the isolation grooves 50 between the light-emitting elements to provide a structure for preventing light coupling. The structure of this embodiment is the same as the equivalent circuit shown in the embodiment B-1 (Fig. 9), and performs the same operation. Therefore, if the high-level voltages of the transfer clock lines  1 ,  2 and  3 are set to sequentially slightly overlap each other, an ON state of light-emitting thyristors is sequentially transferred. More specifically, a light-emission point is sequentially transferred. (Embodiment B-3) Figs. 11, 12, and 13 show an embodiment B-3. This embodiment presents an actual structure of the embodiment B-2. Fig. 11 is a plan view of this embodiment, and Figs. 12 and 13 are sectional views taken along lines X-X' and Y-Y' in Fig. 11, respectively. Light-emitting elements T (-1) to T (+1) , isolation grooves of the light-emitting elements, and a field layer 60, and the like are the same as those in the embodiment A-3. A two-dimensional resistor 63 forms a resistor network connecting the gate electrodes. Light emitted from the light-emitting elements is prevented from being input to the resistor 63 by light absorbing blocks 62. In this embodiment, a portion of the field layer 60 is used as an optical barrier. However, other materials may be used or another shape may be employed. An upper electrode of each light-emitting element is led via a lead contact hole C 1 using an electrode layer 40. A clock line  1 is connected to the light-emitting elements T (-2) and T (+1) , a clock line  2 is connected to the light-emitting element T (-1) , and a clock line  3 is connected to the light-emitting element T (0) . The resistor 63 is externally led using each contact hole C 3 , and is connected to a gate electrode 41 of each element. The other end portion of the resistor 63 is connected to a voltage source line 42 for supply a voltage V GK through the contact hole C 3 . Fig. 12 is a sectional view taken along a line X-X' in Fig. 11. This line extends along an array direction of the light-emitting element array, and Fig. 12 reveals an arrayed state of the light-emitting elements. Short-circuiting preventing insulating films 30 preventing short-circuiting between the light-emitting elements and the electrodes 40 and 41, insulating films 31 as insulating interlayers for preventing short-circuiting between the electrodes 50 and the transfer clock lines, and the like which are formed in the isolation grooves 50 of the light-emitting elements are the same as those in the embodiment A-3. These insulating films 30 and 31 must be transparent insulating films so that light can be efficiently output to an external portion. In this case, as has been described above, in order to prevent a transfer operation from being influenced by light coupling, the gate electrodes 41 can be advantageously formed in the isolation grooves 50 to shield light. Fig. 13 is a sectional view taken along a line Y-Y' in Fig. 11. This line extends to be perpendicular to the array direction of the light-emitting element array, and Fig. 13 reveals a connection state of the wirings and electrodes. Lead contact holes C 1 of the light-emitting elements for the upper electrodes are formed in the insulating films 30, and are externally led using the electrode layers 40. Each electrode layer 40 is connected to the transfer clock line  3 via a through hole C 2 on the field layer 60. As the resistor 63 for the resistor network, an n-type GaAs layer 22a of an n-type semiconductor layer is used in this embodiment. This layer may be another layer, and another type of film may be formed by, e.g., sputtering without using a semiconductor layer. Each gate electrode 41 is formed to extend into the isolation groove 50 so that light emitted by the light-emitting element does not influence the resistance of the resistor 63. The following manufacturing process for realizing this embodiment can be employed. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer 21a are sequentially grown on an n + -type GaAs substrate 21 by an epitaxial growth method. Isolation grooves 50 are then formed by photoetching. Portions of the light-emitting elements and p-type GaAs layer 21a and the p-type AlGaAs layer 21b in the resistor portion are removed by photoetching using another mask. Thereafter, an insulating film 30 is formed, and contact holes C 1 are formed by photoetching. A metal electrode layer is formed by deposition or sputtering, and electrodes 40 and 41 are then formed by photoetching. Furthermore, an insulating film 31 is formed, and through holes C 2 are formed by photoetching. A metal wiring layer is then formed by deposition or sputtering, and transfer clock lines  1 ,  2 and  3 are formed by photoetching. With the above process, the structure of this embodiment is completed. Although not particularly described in this embodiment, a transparent protection film may be formed on the transfer clock lines. If it is not preferable that the thickness of the insulating film is too large to degrade the transmittance of light and to decrease an amount of externally output light, part or all of the upper insulating film of the light-emitting element may be removed by, e.g., photoetching. According to this embodiment, an integrated self-scanning light-emitting element array can be manufactured. (Embodiment B-4) In the embodiments B-2 and B-3, the light-emitting thyristor is adopted as the light-emitting element. In this embodiment, a case will be described below wherein a laser thyristor is used. Fig. 14 shows an embodiment B-4. Fig. 14 is a plan view, and Fig. 15 is a sectional view taken along a line X-X' in Fig. 14. Reference symbols such as T (-1) to T (+1) of the light-emitting elements (laser thyristors), and the like are the same as those in the above embodiment. A manufacturing method of Fig. 14 will be described below. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (non-doped) GaAs layer 123, an n-type AlGaAs layer 122, a p-type AlGaAs layer 121, and an upper electrode layer 20 are sequentially stacked on an n-type GaAs substrate 1 (a p-type GaAs layer for improving an ohmic contact may be formed between the p-type AlGaAs layer 121 and the upper electrode layer 20). The upper electrode layer 20 is patterned into a rectangular shape having the same width as that of the n-type AlGaAs layer 125 in Fig. 15. Using the electrode pattern 20 as a mask, the p-type AlGaAs layer 121 to the n-type AlGaAs layer 125 are etched to form element isolation grooves 50. The upper electrode pattern 20 is further etched into a stripe shape having a width of 10 µm or less. Using the new electrode pattern 20 as a mask, the p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are etched. The n-type AlGaAs layer 122 is not entirely removed but is partially left. Insulating films 30c, 30b and 30a are then formed on the resultant structure. Note that the three insulating films include the insulating films 30c and 30a and the light shielding film 30b, so that two functions, i.e., insulating and light shielding functions are provided. When an SiO 2 film is used as an insulating film, it allows a light component having a light-emission wavelength of 870 nm of GaAs to pass therethrough, it may induce light coupling. Thus, the light shielding film 30b formed of a light absorption material, e.g., amorphous silicon, must be formed between the insulating films. Of course, if a material having both the two insulating and light shielding functions is used, one layer need only be formed. Contact holes C 1 are formed by photoetching, and a resistor 63 is formed thereon and is photoetched. An insulating film 31 as an insulating interlayer is formed on the resultant structure, and through holes C 2 are formed by photoetching. In this case, the through holes on the resistor 63 can be formed by only the insulating film 31. However, the through holes on the upper electrode 20 must be carefully formed since the insulating films 31, 30c, 30b and 30a must be simultaneously removed. A metal wiring layer for transfer clock lines are then formed by deposition or sputtering, and transfer clock lines  1 ,  2 and  3 and a power source V GK line are formed by photoetching. Finally, the end face of a laser beam output side is formed by cleavage or tlie like to have good parallelness, thus completing the structure of this embodiment. The light-emitting element arrays in the embodiments B-1 to B-4 have a self-scanning function as in the embodiments A, which cannot be achieved by a conventional light-emitting element array and can provide effects of efficient assembly, compactness, a decrease in pitch, and the like. In the embodiments B-1 to B-4, the transfer clock pulses are assumed to have three phases, i.e.,  1 ,  2 and  3 . The number of phases may be increased to four or five so as to attain a more stable transfer operation. In the above embodiments, the light-emitting elements are arrayed in a line. However, the elements need not be arranged in a line but may be arranged in a zigzag manner depending on applications. The elements may be arranged in two lines from the halfway. The light-emitting element need not be a light-emitting thyristor. The present invention is not particularly limited to any element as long as a turn-on voltage of a light-emitting element is changed by an external potential. The light-emitting element may be a laser thyristor as described above. According to the present invention, the light-emitting elements may be constituted by individual parts, or may be integrated by any means. The structure of the light-emitting thyristor is not particularly limited. For example, a more complex structure and a multilayer structure may be adopted, and an arbitrary structure constituted by six or more layers may be adopted, as described in the embodiments A. In the series of embodiments A and B of the present invention, a semiconductor substrate is used as a substrate, and its potential is set at 0 V (ground potential). However, the present invention is not limited to this, and other materials may be used for the substrate. For example, an n-type GaAs layer corresponding to the n-type GaAs substrate 1 of this embodiment is formed on a Cr-doped semiinsulating GaAs substrate, and the structure described in the above embodiments may be formed thereon. Alternatively, a semiconductor film is formed on an insulating substrate of, e.g., glass, alumina, or the like, and the structure of this embodiment may be formed using this semiconductor. The structure of the laser is not limited to that described in the above embodiments. For example, a TJS type, a BH type, a CSP type, a VSIS type, and the like may be employed (S.M. Sze, Physics of Semiconductor Devices, 2nd Edition, pp. 724-730). As for a material, AlGaAs has been mainly described. However, other materials (e.g., AlGaInP, InGaAsP, ZnSe, GaP, and the like) may be used. In the embodiments A and B, an ON light-emitting element gives a primary influence to adjacent light-emitting elements, and the adjacent light-emitting elements become light-emitting elements to be driven next. However, the present invention is not limited to this. For example, an ON element may influence every other elements, so that an ON state can be transferred to every other elements. The above-mentioned many modifications will be applied to the following numerous embodiments. Embodiment C An embodiment C to be described below is related to a drive method of the light-emitting element arrays produced by the embodiments A and B described above. (Embodiment C-1) Drive Method of Light-Emitting Element Array Fig. 16 is a view for explaining an embodiment C-1. Fig. 16 shows an equivalent circuit diagram representing a drive principle and pulse waveforms applied to terminals. In this embodiment, current sources I 1 , I 2 and I 3 are arranged in parallel with transfer clock pulses  1 ,  2 and  3 , and a current amount I T is controlled by a light-emission signal  I . An operation will be described below. A light-emitting element T (0) is turned on in response to a start pulse  S . When the transfer pulses  1 ,  2 and  3 are sequentially applied, an ON state is transferred. This mechanism has already been described in the embodiments A and B. Assuming that a light-emitting element T (3) should be caused to emit light at a higher intensity, the light-emission signal  I is synchronously set at high level when a light-emission point has reached the position of the element T (3) . In synchronism with the signal  I , currents flow from the current sources I 1 , I 2 and I 3 . The anode of the ON element T (3) can drain the current from the current sources. Since other light-emitting elements are in an OFF state, they cannot drain the currents, and the currents flowing into these elements flow out toward a driver which generates transfer clock pulses. Therefore, the anode current of the ON light-emitting element is increased, and a light-emission intensity is also increased. Fig. 16 also illustrates a waveform of the light-emission intensity L. As can be apparent from this waveform, the light-emission intensity of the light-emitting element T (3) is increased as compared to other light-emission intensities obtained when no currents from the current sources flow. When this drive method is used, the light-emission intensity at an arbitrary position can be increased, and a locational optical write operation can be performed. When laser thyristors are used as the light-emitting elements of this embodiment, if the anode current by the transfer clock is set to be a threshold current of laser oscillation, no laser beam is emitted in a normal transfer state, and only when a light-emission signal is input, a laser beam can be emitted. Applications Applications described hereinafter related to an application of the light-emitting element arrays in the embodiments A and B and the drive method described in the embodiment C. (Application 1) Application to Contact type Image Sensor Fig. 17 shows the principle of a contact type image sensor as a first application of the present invention. In this application, a function of shifting a light-emission point can be realized by the present invention, and is applied to position scanning. In Fig. 17, a photosensor of amorphous Si is formed on a glass substrate. In a conventional sensor, the photosensor is divided into 100-µm pixels, and these pixels are scanned by read ICs to extract outputs. Illumination is uniformly made by LEDs. In a method described herein, the amorphous Si photosensor is not divided into pixels but illumination is scanned. In Fig. 17, an electrode A2 serving as a light shielding layer, an amorphous Si layer A3, a transparent electrode A4, and an electrode A5 are formed on a glass substrate A1. This structure utilizes a phenomenon that the resistances of the electrodes A2 and A5 are decreased upon incidence of light since the electrical conductivity of the amorphous Si layer A3 is increased by light. A transparent protection layer A6 is formed on this structure, and a document A7 is brought into contact with the layer A6. A light-emitting element array A10 of this embodiment is arranged at a side opposite to the document A7 with respect to the glass substrate A10. A scanning beam A11 from the array A10 passes through a rod lens array A9, then passes through a window A8, formed at the central portion of the photosensor, for introducing a beam, and is then focused on the document A7. The light-emitting element array A10 has a function of sequentially shifting a light-emission point according to the present invention. Thus, a focal point on the document is sequentially shifted accordingly. If a tone changes due to a presence of a character on the document A7, reflection beams A12 from the document are changed accordingly. Changes in beam intensity are read by the photosensor of the amorphous Si layer A3. When the light-emitting element array comprises laser thyristors, a light-emitting element array having a large amount of light can be obtained due to its high quantization efficiency, thus saving power consumption and allowing high-speed reading. In this manner, the light-emitting element array according to the present invention can be applied to reading of characters or an image of a document, or the like, and a wide application range for a facsimile system, a bar code reader, a copying machine, and the like, can be expected. (Application 2) Application to Optical Printer and Display As a second application of the present invention, an application to an optical printer will be described below. Conventionally, an application to an optical printer using a module in which a drive IC is connected to each pixel of an LED array is known. Fig. 18 shows the principle of an optical printer. A layer of a material, e.g., amorphous Si having optical conductivity (photosensitive body) is formed on the surface of a cylindrical photosensitive drum B1. The drum B1 is rotated in a direction of an arrow a at a print speed. The surface of the photosensitive body is uniformly charged by a charger B7. A light-emitting element array optical print head B8 radiates an optical dot image to be printed onto the photosensitive body so as to neutralize a charge of a portion irradiated with a light beam. A toner is attracted to the photosensitive body in accordance with a charged state on the photosensitive body by a developing unit B10. The toner image is transferred onto a paper sheet B9 fed from a cassette B11 by a transfer unit B2. The toner image on the paper sheet B9 is heated by a fixing unit B3 and is fixed thereon. The sheet B9 is then transferred to a stacker B4. The charge on the drum which completes the transfer is neutralized over the entire surface by a discharging lamp B5, and the residual toner is removed by a cleaner B6. The light-emitting element array according to the present invention is driven by the drive method described in the embodiment C-1, and is applied to the light-emitting element array optical print head B8. Fig. 19 shows the structure of the optical print head B8. The head B8 is constituted by a light-emitting element array B12 and a rod lens array B13, so that a focal point of the lens is formed on the photosensitive drum B1. When the drive method described in the embodiment C-1 is used, a light-emission intensity can be increased at a position where an optical write operation is to be performed, while transferring an ON state in the light-emitting element array of the present invention. Therefore, image data can be written on the photosensitive drum. When the light-emitting element array comprises laser thyristors, a light-emitting element array having a large amount of light can be obtained due to its high quantization efficiency, thus saving power consumption or allowing high-speed write access, i.e., printing. Thus, the present invention can be applied to the optical printer. The light-emitting element array for the optical printer has a linear arrangement. If the arrays are two-dimensionally arranged, a display can be prepared. This structure is shown in Fig. 20. If N light-emitting element arrays B14 are arranged, an image signal can be written from  I (1) to  I (N). If an integrated light-emitting element array is used, a high-density display element can be produced. If independent light-emitting elements are combined, a large-area display can be produced. Embodiments D Embodiments D described herein can simplify a structure of the light-emitting element array in the embodiments B described above. (Embodiment D-1) Fig. 25 is an equivalent circuit diagram showing the principle of an embodiment D-1. In this embodiment, a three-terminal light-emitting thyristor is used as a light-emitting element whose light-emission threshold voltage and current can be externally controlled. Light-emitting thyristors T (-2) to T (+2) are aligned in a line. Each light-emitting thyristor is represented as a combination of transistor Tr1 and Tr2. The transistor Tr1 is a pnp transistor, and the transistor Tr2 is an npn transistor. Each connecting resistor R L between adjacent light-emitting thyristors is connected between the bases of the adjacent npn transistors Tr2. Each of three transfer clock lines  1 ,  2 and  3 is sequentially repetitively connected to the anode electrodes of every third light-emitting thyristor. A resistor Re for regulating a current of the clock line is provided to each clock line. An operation will be described below. Assume that a transfer clock  3 goes to high level, and a light-emitting thyristor T (0) is turned on. In this case, the base of the npn transistor Tr2 (0) is set at a potential capable of flowing an ON current of the light-emitting thyristor T (0) This potential is transmitted to the bases of the npn transistors Tr2 (-1) and Tr2 (1) of the adjacent light-emitting thyristors T (-1) and T (1) through the corresponding connecting resistors R L , and their base currents flow. As long as the transfer clock lines  1 and  2 are set at low level, the light-emitting thyristors T (-1) and T (1) are kept off. If the resistance of the connecting resistor R L is low, the npn transistors Tr2 (-1) and Tr2 (1) have powers capable of flowing the same current as the ON current of the light-emitting thyristor T (0) However, if the resistance of the connecting resistor R L is high, the base currents of the npn transistors Tr2 (-1) and Tr2 (1) are regulated by the connecting resistors R L , and the current drive powers of the npn transistors Tr2 (-1) and Tr2 (1) are decreased. The base currents of the npn transistors Tr2 (-2) and Tr2 (2) located farther than the npn transistors Tr2 (-1) and Tr2 (1) are further decreased, and their current drive powers are decreased more. As is well known, when the base current amount of the npn transistor Tr2, i.e., the current drive power is increased, the ON voltage of the light-emitting thyristor is decreased. Fig. 26 illustrates this state. The anode voltage (emitter voltage of the pnp transistor Tr1) is plotted along the abscissa, and the anode current is plotted along the ordinate. In Fig. 26, an ON voltage V S is free from an external influence. An ON voltage V S(1) represents an ON voltage of the light-emitting thyristor T (1) and an ON voltage V S(-2) represents an ON voltage of the light-emitting thyristor T (-2) . A minimum voltage necessary for maintaining an ON state is called a hold voltage Vh. The ON voltages of the light-emitting thyristors T (-1) and T (1) closest to the ON light-emitting thyristor T are decreased for the above-mentioned reason, and reach the ON voltage V S(1) . The ON voltages of the next closest light-emitting thyristors T (-2) and T (2) become the ON voltage V S(2) since the influence of the base current is small. In Fig. 25, a clock pulse  1 next to the clock pulse  3 is applied to the light-emitting thyristors T (1) and T (-2) . Since their ON voltages respectively become ON voltages V S(1) and V S(-2) for the above-mentioned reason, if the high-level voltage of the clock pulse is set to be a value between the ON voltages V S(1) and V S(-2) , only the light-emitting thyristor T (1) can be turned on. If the clock pulses  1 ,  2 and  3 are set so that their high-level intervals appear to overlap each other, the ON light-emitting element is sequentially transferred. Thus, a light-emitting element array capable of self-scanning can be realized. As described above, according to the present invention, only one resistor connecting adjacent light-emitting elements is required, and the light-emitting element array can be formed by a simple manufacturing process. In this embodiment, three-phase transfer clock pulses are used. The light-emitting element array of this embodiment can be operated by clock pulses of four or more phases. (Embodiment D-2) In the embodiment D-1, the equivalent circuit has been described. In an embodiment D-2, an IC structure of the arrangement in the embodiment D-1 will be described. The gist of this embodiment lies in a structure wherein a connecting resistor for performing electrical connection is formed by utilizing a portion of a light-emitting element, so that a resistor element can also be formed by the same process as in the light-emitting thyristor. Fig. 27 is a sectional view of the structure of this embodiment. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22, and a p-type semiconductor layer 21 are formed on a grounded n-type GaAs substrate 1. Isolation grooves 50 for isolating the above structure into individual light-emitting elements T (-2) to T (2) are formed by photolithography or the like and etching. The n-type GaAs substrate 1 serves as the cathode of each thyristor. Each of transfer clock lines  1 ,  2 and  3 is connected to every second p-type semiconductor layer 21 serving as the anodes of the light-emitting elements. The characteristic feature of this structure is that the p-type semiconductor layer 23 constituting the thyristors is connected through the elements. The internal resistance of the p-type semiconductor layer 23 serves as the connecting resistor R L in the embodiment D-1 shown in Fig. 25. Fig. 28 is a plan view showing the structure of this embodiment. In the light-emitting elements T (-2) to T (2) when viewed from the above in Fig. 27, inner rectangles correspond to the p-type semiconductor layers 21, and a portion therearound corresponds to the p-type semiconductor layer 23. In this structure, notches 55 are formed in the p-type semiconductor layer 23. The notches 55 are used for changing the value of the connecting resistor R L described in the embodiment D-1. If a large notch 55 is formed, the resistance of the connecting resistor R L is increased. Therefore, in this embodiment, the connecting resistor R L can be desirably changed and optimized, thus achieving a more stable transfer operation. The structure of this embodiment is the same as that of the equivalent circuit in the embodiment D-1 (Fig. 25), and performs the same operation. Therefore, if the high-level voltages of the transfer clocks  1 ,  2 and  3 are set to sequentially slightly overlap each other, the ON states of the light-emitting thyristors are sequentially transferred. That is, a light-emission point can be sequentially shifted. As described above, according to this embodiment, no gate electrode is required, and one resistor for connecting adjacent light-emitting elements need only be formed. In addition, the connecting resistor R L can be formed by a semiconductor layer constituting the light-emitting elements. As can be understood from the above description, the structure of this embodiment can be formed by a simple manufacturing process. In this embodiments, the transfer clock pulses are assumed to have three phases, i.e.,  1 ,  2 and  3 . The number of phases may be increased to four or five so as to attain a more stable transfer operation. (Embodiment D-3) Figs. 29 and 30 show an embodiment D-3. This embodiment presents a practical structure of the embodiment D-2. Fig. 29 is a plan view, and Fig. 30 is a sectional view taken along a line X-X' in Fig. 29. The plan view of Fig. 29 will now be explained. Transfer clock lines  1 ,  2 and  3 are connected to underlying anode electrodes 40 via through holes C 2 . Each anode electrode 40 is connected to a p-type GaAs layer 21a as a p-type semiconductor layer of each light-emitting element. In light-emitting elements T (-2) to T (2) , a p-type GaAs layer 23a as a p-type semiconductor layer is illustrated around the rectangular p-type GaAs layers 21a. Notches 55 described in the embodiment D-2 are formed in the layer 23a so as to optimize the resistance of a connecting resistor R L . The sectional view of Fig. 30 will now be described. The light-emitting elements are formed as follows. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer 21a are sequentially formed on an n-type GaAs substrate 1. Isolation grooves 50 for isolating the resultant structure into individual light-emitting elements are formed by photolithography or the like and etching. Grooves 55 are notches for changing the value of the connecting resistor R L . Although not shown in this sectional view, the connecting resistor R L is a p-type semiconductor layer, and employs the p-type GaAs layer 23a in this embodiment. An insulating layer 30 performs electrical isolation between the anode electrodes 40 and the semiconductor layers. As a material of the insulating layer 30, a material which does not allow light from the light-emitting elements of this embodiment to pass therethrough is preferably used in view of optical isolation among the light-emitting elements. The insulating layer may comprise a multilayered structure so as to have an insulating function and an optical isolation function. When the optical isolation function is provided, a window must be additionally formed that light can be externally output. An insulating film 31 as an insulating interlayer performs insulating isolation between the anode electrodes 40 and the clock lines. The manufacturing process of the embodiment D-3 will be described below. The n-type GaAs layer 24b, the n-type AlGaAs layer 24a, the p-type GaAs layer 23a, the n-type GaAs layer 22a, the p-type AlGaAs layer 21b, and the p-type GaAs layer 21a are sequentially formed on the n-type GaAs substrate 1. The isolation grooves 50 are formed to isolate the light-emitting elements. The notches 55 are then formed to form the connecting resistor R L . The insulating film 30 is formed, and contact holes C 1 are formed therein. The electrodes 40 are formed on the resultant structure. The insulating film 31 is formed, and through holes C 2 are formed therein. Thereafter, the clock line electrodes  1 ,  2 and  3 are formed. With the above-mentioned process, the structure of this embodiment D-3 is completed. As described above, according to this embodiment, no gate electrode is required, one resistor for connecting the light-emitting elements need only be formed, and the connecting resistor R L can be formed by a semiconductor layer constituting the light-emitting elements. As can be apparent from the above description, the structure of this embodiment can be formed by a simple manufacturing process. The order of this process need not always be that described above. For example, the formation order of the isolation grooves 50 and the notches 55 may be reversed. A transparent insulating film may be formed on the structure shown in Fig. 30 to improve reliability. If it is not preferable that the thickness of the insulating film is too large to degrade the transmittance of light and to decrease an amount of externally output light, part or all of the upper insulating film of the light-emitting element may be removed by, e.g., photoetching. In this embodiment, GaAs and AlGaAs layers are used as semiconductor layers. However, the present invention is not limited to these, and other semiconductors may be used. (Embodiment D-4) Application to Laser In the embodiments D-1 to D-3 described above, the light-emitting thyristors have been described as the light-emitting elements. In the following embodiment, a case of using laser thyristors will be described. Figs. 31 and 32 show an embodiment D-4. In the embodiment D-4, the present invention is applied to a laser. Fig. 31 is a plan view of the embodiment D-4, and Fig. 32 is a sectional view thereof. A manufacturing method will be briefly described below. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (non-doped) GaAs layer 123, an n-type AlGaAs layer 122, a p-type AlGaAs layer 121, and an upper electrode layer 20 are sequentially stacked on an n-type GaAs substrate 1. The upper electrode layer 20 is patterned into a rectangular shape having the same width as that of the i-type GaAs layer 123 in Fig. 32. Using the electrode pattern 20 as a mask, the p-type AlGaAs layer 121 to the i-type GaAs layer 123 are etched. In this case, element isolation grooves 50 are formed. The upper electrode pattern 20 is further etched into a stripe pattern (current injection portion of a laser thyristor) having a width of 10 µm or less. Using the new electrode pattern 20 as a mask, the p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are etched. The n-type AlGaAs layer 122 is not entirely removed but is partially left. Notches 55 are formed by photoetching. Thereafter, an insulating film 30 is formed. The insulating film preferably has two functions, i.e., insulating and light shielding functions, and may be formed by a plurality of types of films. When an SiO 2 film is used as the insulating film, it allows light having a light-emission wavelength of 870 nm of GaAs to pass therethrough, it may induce light coupling. Thus, a light-shielding film of a light absorption material such as amorphous silicon must be formed between the SiO 2 films. Contact holes C 1 are formed by photoetching. A metal wiring layer for transfer clock lines is formed by deposition or sputtering, and the transfer clock lines  1 ,  2 and  3 are then formed by photoetching. Finally, the end face of a laser beam output side is formed by cleavage or the like to have good parallelness, thus completing the structure of this embodiment. In the structure of this embodiment, if p and n conductivity types are reversed, the structure of this embodiment can operate as described above if a bias condition and the like are inverted. Such a modification is also included in the scope of the present invention. Embodiments E Embodiments E described below present another example of simplifying the structure of light-emitting element arrays in the embodiments B described previously. (Embodiment E-1) Fig. 33 is an equivalent circuit diagram of an embodiment E-1. In this embodiment, a most typical three-terminal light-emitting thyristor is used as a light-emitting element whose light-emitting threshold voltage and current can be externally controlled. Light-emitting thyristors T (-1) , T' (-1) , T (0) , T' (0) , T (1) , and T' (1) are arranged in a line. The light-emitting thyristors T (-1) and T' (-1) , T (0) and T' (0) , and T (1) and T' (1) respectively constitute blocks. Each block is a group of light-emitting elements to which an identical clock line pulse is applied. In this embodiment, each block is constituted by two elements. Each of the light-emitting thyristors T (-1) , T (0) and T (1) is represented by a combination of transistors Tr1 and Tr2, and each of the light-emitting thyristors T' (-1) , T' (0) and T' (1) is represented by a combination of transistors Tr3 and Tr4. The transistors Tr1 and Tr3 are pnp transistors, and the transistors Tr2 and Tr4 are npn transistors. The transistors Tr1 and Tr3 are connected to the clock lines and the transistors Tr2 and Tr4 are connected to a bias voltage or a ground potential. As to connection between the light-emitting thyristors, the base electrodes (to be referred to as first gates hereinafter) of the transistors Tr1 and Tr3 are connected to each other within each block, and the base electrodes (to be referred to as second gates hereinafter) of the transistors Tr2 and Tr4 are connected to each other between different blocks. Each of three transfer clock lines  1 ,  2 and  3 is sequentially connected to the emitter electrodes of the transistors Tr1 and Tr3 of every three blocks. Each clock line has a current-limiting resistor Re. An operation will be described below. Assume that the transfer clock  1 goes to high level, and the light-emitting thyristors T(-1) and T' (-1) are turned on. In this case, the base potentials of the transistors Tr2 (-1) and Tr4 (-1) are set at a high potential (about 1 V) capable of flowing a current. Since the base of the transistor Tr4 (-1) is connected to the base of the transistor Tr2  , the light-emitting thyristor T (0) tends to be turned on. The influence of an ON state is given to only the light-emitting thyristor T (0) , and is not given to the light-emitting thyristor T' (0) . Similarly, in a block (-2), only the light-emitting thyristor T' (-2) tends to be turned on, and does not influence the light-emitting thyristor T (-2) . The ON block does not influence secondary closest blocks, e.g., blocks (-3) and (1). In this state, when the next transfer clock  2 is set at an appropriate high-level voltage, the light-emitting thyristor T (0) is immediately turned on. The bases of the transistors Tr3 (0) and Tr3 (0) are set at a substantially zero potential since the light-emitting thyristor T (0) is turned on. Thus, a current flows through the transistor Tr3 (0) . For this reason, the light-emitting thyristor T' (0) is also successively turned on. On the other hand, another block (e.g., (-3)) to which the transfer clock  2 is applied is not influenced by the block (-1), and hence is not turned on. A range of a high-level voltage capable of the transfer operation is considerably wide. The transfer operation can be performed within the range of 1.5 to 2 V for a low voltage side, and within the range up to a voltage defined by a breakdown voltage of the light emitting thyristor for a high voltage side. When the transfer block  1 goes to low level, the block (-1) is turned off, and the ON state is shifted from the block (-1) to the block (0). If the clock pulses  1 ,  2 and  3 are set so that their high-level voltages overlap each other, the ON light-emitting elements are sequentially transferred. Thus, a light-emitting element array capable of self-scanning can be realized. As described above, according to this embodiment, a self-scanning function can be realized without using a resistor for connecting light-emitting elements, and a high-level voltage of the transfer clock pulse capable of the transfer can have a considerable margin, i.e., can be in a range of 1.5 to 2V for a low voltage side and a range up to a breakdown voltage of the light-emitting thyristor for a high voltage side. In this embodiment, the operation using the three-phase clock pulses has been described. However, the structure of this embodiment can operate using clocks of four or more phases, as a matter of course. In Fig. 33, the light-emitting elements are arranged in a line. However, a linear arrangement need not be employed. For example, the light-emitting elements may be arranged in a a zigzag pattern or may be arranged in two lines from the halfway depending on applications. In this embodiment, the description has been made using only the light-emitting thyristors. However, the present invention is not limited to this as long as a device having a similar function is used. A laser thyristor may be used as the light-emitting element. The light-emitting elements may be constituted as individual parts or are integrated by any means as will be described in the next embodiment. (Embodiment E-2) The equivalent circuit has been described in the embodiment E-1. In an embodiment E-2, an IC structure of the arrangement in the embodiment E-1 will be described. Fig. 34 shows a more illustrative view of the equivalent circuit diagram of Fig. 33. Each light-emitting thyristor is basically expressed as a structure wherein a total of four p- and n-type semiconductor layers are stacked in a predetermined order. In the pnpn structure, a pnp portion corresponds to transistors Tr1 and Tr3 in Fig. 33, and an npn portion corresponds to the transistors Tr2 and Tr4. In Fig. 34, the connection relationship in Fig. 33 is replaced with the pnpn structure. Fig. 35 shows a practical structure of Fig. 34. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22, and a p-type semiconductor layer 21 are sequentially formed on a grounded n-type GaAs substrate 1. The resultant structure is patterned into individual light-emitting elements T (-1) to T (1) by photolithography or the like and etching, thus forming the structure shown in Fig. 35. The characteristic feature of this structure is that the light-emitting elements T' (0) and T (0) and the light-emitting elements T' (0) and T (1) have common lower pn portions, and upper pn portions of the light-emitting elements T (-1) and T' (-1) , the light-emitting elements T (0) and T' (0) , and the light-emitting elements T (1) and T' (1) are connected through a wiring material. The light-emitting thyristors have anode electrodes 40 and gate electrodes 41 (first gates), and are isolated by an insulating layer 30. Of the light-emitting thyristors T and T', the thyristors T are used as light-emitting elements in practice, and the thyristors T' are used for connecting adjacent elements. Light L 0 is output upward. The structure of this embodiment is the same as the equivalent circuit shown in the embodiment E-1 (Fig. 33), and performs the same operation. Therefore, if the high-level voltages of the transfer clocks  1 ,  2 and  3 are set to sequentially slightly overlap each other, the ON state of the light-emitting thyristors is sequentially transferred. That is, a light-emission point can be sequentially shifted. As described above, according to this embodiment, no resistor for connecting light-emitting elements is required, and a high-level voltage transfer range of the transfer clock pulse can have a considerable margin, i.e., can be a range of 1.5 to 2 V at a low voltage side and a range up to a breakdown voltage of the light-emitting thyristor at a high voltage side. In the structure of this embodiment, if p and n conductivity types are reversed, the structure of this embodiment can operate as described above if a bias condition and the like are inverted. Such a modification is also included in the scope of the present invention. Embodiments F Embodiments F described below can simplify drive circuits of the light-emitting element arrays in the embodiment B described previously. (Embodiment F-1) In an embodiment F-1 described herein, a diode is used as an electrical connection means. Fig. 36 is an equivalent circuit diagram showing the principle of the embodiment F-1. In this embodiment, a most typical three-terminal light-emitting thyristor is used as a light-emitting element whose light-emission threshold voltage and current can be externally controlled. Reference symbols T (-2) to T (+2) denote light-emitting thyristors, which are arranged in a line. Reference symbols G -2 to G +2 denote gate electrodes of the light-emitting thyristors T (-1) to T (+2) . Reference symbol R L denotes a load resistor of each gate electrode; D -2 to D 2 , diodes for performing an electrical interaction; and V GK , a voltage source voltage. Each of two transfer clock lines  1 and  2 is sequentially connected to the anode electrodes of every other individual light-emitting thyristors. An operation will be described below. Assume that the transfer clock  2 goes to high level, and the light-emitting element T (0) is turned on. In this condition, the potential of the gate electrode G 0 is reduced to about 0 V due to the characteristics of the three-terminal thyristor (to about 1 V in the case of a silicon thyristor). If the voltage V GK is 5 V, the gate voltages of the light-emitting thyristors are determined by the network of the diodes D -2 to D 2 . The gate voltage of an element close to the light-emitting element T (0) is most decrease , and the gate voltages are increased as the elements are apart from the element T (0) . However, an effect of decreasing a voltage occurs for only the right half from the element T (0) due to the unidirectional and asymmetrical characteristics of the diode. More specifically, the gate voltage at the gate G 1 is set to be higher than that of the gate G  by a diffusion potential V df of the diode, and the gate voltage at the gate G 2 is set to be further higher than that of the gate G 1 by the diffusion potential V df of the diode. On the other hand, no current flows through the gate G -1 corresponding to the left half since the diode D -1 is reverse-biased, and hence, has the same potential as the voltage V GK . The next transfer clock pulse  1 is applied to the closest elements T (1) , T (-1) , T (3) , T (-3) and the like. Of these elements, the element T (1) has the lowest ON voltage, i.e., about 2V df . An element having the second lowest ON voltage is T (3) , and the voltage is about 4V df . The ON voltages of the elements T (-1) and T (-3) are about V GK + V df . In this manner, if the high-level voltage of the transfer clock pulse is set to fall within the range of 2V df to 4V df , only the element T (1) can be turned on, and the transfer operation can be performed. In the equivalent circuit of this embodiment, only the diode is used as an element for connecting the gate electrodes of the light-emitting thyristors. However, a resistor may be connected in series with the diode. In this case, a potential difference between the gates G 0 and G 1 is greater than the diffusion potential V df of the diode, and the high-level clock voltage range capable of the transfer operation can be widened. In this embodiment, an operation using two-phase transfer clock pulses has been described. The structure of this embodiment can operate if clocks of three or more phases are used, as a matter of course. (Embodiment F-2) In the embodiment F-1, the equivalent circuit has been described. In an embodiment F-2 described below, an IC structure of the arrangement the embodiment F-1 will be described. The gist of this embodiment lies in a structure wherein a diode for performing electrical coupling is formed by utilizing a portion of a light-emitting element, so that a diode can be formed in the same process as that of the light-emitting thyristor. Fig. 37 shows a general structure of the embodiment F-2. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22, and a p-type semiconductor layer 21 are sequentially formed on a grounded n-type GaAs substrate 1. Isolation grooves 50 for isolating the above-mentioned structure into individual light-emitting elements are formed by photolithography or the like and etching.Reference symbols T (-2) to T (+2) denote these individual light-emitting elements. Anode electrodes 40 have an ohmic contact with the corresponding p-type semiconductor layers 21, and gate electrodes 41 have an ohmic contact with the corresponding n-type semiconductor layers 22. Insulating layers 30 are formed to prevent short-circuiting between the elements and wirings, and at the same time, serve as protection films for preventing deterioration of characteristics. The insulating layers 30 are preferably formed of a material allowing light having a light-emission wavelength of a light-emitting thyristor to pass therethrough well. The n-type GaAs substrate 1 serves as a cathode of each thyristor. Each of two transfer clock lines  1 and  2 is sequentially connected to the anode electrodes 40 of every other individual light-emitting elements. A load resistor R L is connected to each gate electrode. On the other hand, if light coupling occurs between the elements, the transfer operation of this embodiment may be influenced by the light coupling. In order to prevent this, each gate electrode partially extends into the isolation groove between the adjacent light-emitting elements so as to employ a structure capable of preventing light coupling. The structure of this embodiment is the same as the equivalent circuit shown in the embodiment F-1 (Fig. 36), and performs the same operation. Therefore, if the high-level voltages of the transfer clocks  1 and  2 are set to alternately slightly overlap each other, the ON state of the light-emitting thyristors is sequentially transferred. That is, a light-emission point is sequentially transferred. According to this embodiment, a two-phase drive self-scanning type light-emitting element array can be realized by an integrated circuit. In this embodiment, the transfer clock pulses are assumed to have two phases, i.e.,  1 and  2 . However, the number of phases can be increased to three or four in order to achieve a more stable transfer operation. (Embodiment F-3) Figs. 38 and 39 show an embodiment F-3. This embodiment presents a practical structure of the embodiment F-2. Fig. 38 is a plan view of this embodiment, and Fig. 39 is a sectional view taken along a line Y-Y' in Fig. 38. Reference symbols T (-2) to T (+1) denote light-emitting elements. A load resistor 63 connected to the gate of each light-emitting thyristor is represented by R L , and is formed by a semiconductor layer constituting the light-emitting thyristor. Diodes D -2 to D 1 are connected to the thyristors T (-2) to T (+1) , respectively. The anode of each diode is connected to the gate of the next light-emitting thyristor, and the load resistor 63. Semiconductor layers and electrodes are connected through connecting holes C 1 as contact holes. Through holes C 2 are connecting holes for connecting the anode electrodes 40 of the light-emitting thyristors and the transfer clock lines  1 and  2 . A power source line 42 is connected to a power source voltage V GK and the load resistors R L . The power source line 42 is formed simultaneously with gate electrodes 41. Note that the gate electrodes 41 also serve as light shielding layers for preventing the light-emitting elements T (-2) to T (+1) from mutual influences upon their light emission. Fig. 39 is a sectional view of this embodiment. The light-emitting elements are formed as follows. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer 21a are sequentially formed on an n-type GaAs substrate 1. Isolation grooves 50 for isolating the resultant structure into individual light-emitting elements are formed by photolithography or the like and etching. An isolation groove 51 is formed to isolate the light-emitting element T (0) and the coupling diode D 0 . Each load resistor 63 (R L ) is formed of the n-type GaAs layer 22a of the light-emitting element. The resistor may be formed of another layer. For example, the resistor may be formed of the p-type GaAs layer 23a or may be formed as another resistor region. A manufacturing process of the embodiment F-3 will be described below. The n-type GaAs layer 24b, the n-type AlGaAs layer 24a, the p-type GaAs layer 23a, the n-type GaAs layer 22a, the p-type AlGaAs layer 21b, and the p-type GaAs layer 21a are sequentially formed on the n-type GaAs substrate 1. The isolation grooves 50 are then formed to isolate the light-emitting elements and the resistors. The isolation grooves 51 are formed to isolate the light-emitting diodes and the coupling diodes. The resistors 63 are formed in the same process as that of forming the isolation grooves 51. More specifically, the p-type GaAs layer 21a and the p-type AlGaAs layer 21b are removed. The insulating films 30 are formed, and the contact holes C 1 are formed therein. Thereafter, the electrodes 40, 41 and 42 are formed. The insulating films 31 as insulating interlayers are formed, and the through holes C 2 are formed. Thereafter, the electrodes  1 and  2 are formed. With the above-mentioned process, the structure of the embodiment F-3 is completed. (Embodiment F-4) In an embodiment F-4, a transistor is used as an electrical connection means. Fig. 40 shows an equivalent circuit of the embodiment F-4. Each light-emitting thyristor described in the embodiment F-1 is expressed by a combination of a pnp transistor Tr1 and an npn transistor Tr2. The collector of the transistor Tr1 is connected to the base of the transistor Tr2, and the base of the transistor Tr1 is connected to the collector of the transistor Tr2 so as to cause these transistors to perform the same operation as the thyristor. The base of the transistor Tr1, e.g., the collector of the transistor Tr2 corresponds to the gate of a three-terminal thyristor. Combinations of the transistors Tr1 and Tr2 are expressed by T (-1) to T (1) . In the embodiment F-4, adjacent elements are coupled through a pnp transistor Tr3 without using the diodes unlike in the embodiment F-1. The base of the transistor Tr3 is connected to the base of the transistor Tr1, and the collector of the transistor Tr3 is connected to the base of the transistor Tr2. The transfer operation in this case is the same as that described in the embodiment F-1. That is, the thyristor in the embodiment F-1 can be considered as the combination of the transistors Tr1 and Tr2, and the diode in the embodiment F-1 can be considered as the transistor Tr3. A detailed device structure in the embodiment F-4 is the same as those shown in the embodiments F-2 and F-3. (Embodiment F-5) Fig. 41 is an equivalent circuit diagram of an embodiment F-5. In the embodiment F-5, the power source V GK and the load resistors R L are omitted from the equivalent circuit shown in the embodiment F-1. The equivalent circuit of the embodiment F-1 utilizes the fact that the ON voltage of the thyristor is determined with respect to the power source voltage V GK , the gate voltage of the ON element becomes almost 0 V, and this influences the adjacent elements through the diodes. In the embodiment F-5, the power source V GK is omitted. An operation of this embodiment will be described below. Assume that a clock high-level voltage is applied to a transfer clock line  2 , and a light-emitting thyristor T (0) is turned on. The potential of a gate G 0 becomes almost 0 V. In this case, the voltage at a gate G -1 of an adjacent light-emitting thyristor T (-1) is indefinite since a diode D -1 is reverse-biased when the voltage at the gate G -1 exceeds 0 V, and since no current flows. The voltage at a gate G 1 of a light-emitting thyristor T (1) cannot become higher than a diffusion potential V df of a diode D 0 . For this reason, the ON voltage of a light-emitting thyristor T (-1) becomes one determined by the device structure of the light-emitting thyristor T (-1) . Meanwhile, the ON voltage of the light-emitting thyristor T (1) becomes a voltage higher than the potential at the gate G 0 by the potential V df , i.e., about 2V df . If the ON voltage defined by the device structure is set to be higher than 2V df , two-phase drive can be achieved as has been described in the embodiment F-1. According to the embodiment F-5, neither power source nor load resistors are required, and the wiring layers for the two transfer clocks need only be formed, resulting in a simple structure. (Embodiment F-6) Figs. 42 and 43 show a structure of an embodiment F-6. The structure shown in Figs. 42 and 43 corresponds to an actual structure of the equivalent circuit shown in the embodiment F-5. Fig. 42 is a plan view, and Fig. 43 is a sectional view taken along a line X-X' in Fig. 42. This structure will be described below. Transfer clock lines  1 and  2 , light-emitting elements T (-1) to T (1) are the same as those described above. Gate electrodes 41 connect coupling diodes D -1 to D 1 and the gates of the light-emitting elements. The light-emitting element portion shown in Fig. 43 is basically the same as that shown in Fig. 39. A manufacturing process of the embodiment F-6 will be described below. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer 21a are sequentially formed on an n-type GaAs substrate 1. Isolation grooves 50 are then formed to isolate the light-emitting elements. Isolation grooves 51 are formed to isolate the light-emitting diodes and the coupling diodes. That is, the p-type GaAs layer 21a and the p-type AlGaAs layer 21b are removed. Insulating films 30 are formed, and contact holes C 1 are formed therein. Thereafter, electrodes 41 and transfer clock lines  1 and  2 are formed. With the above-mentioned process, the structure of the embodiment F-6 is completed. The characteristic feature of the structure of the embodiment F-6 is that two-phase wiring layers are not used unlike in the embodiment F-3. As can be seen from Fig. 42, wiring patterns can be formed without overlapping, and one wiring layer need only be formed. Since a resistor can be omitted, a manufacturing process can be simplified, and thus, manufacturing cost can be further decreased. (Embodiment F-7) Fig. 44 is an equivalent circuit diagram of an embodiment F-7. The embodiment F-7 corresponds to one rewriting the embodiment F-5 as an equivalent circuit using transistors. The structure of the embodiment F-7 is substantially the same as that of the embodiment F-4, except that the load resistor in the embodiment F-4 is omitted, and its operation is the same as that in the embodiment F-5. The actual structure of the embodiment F-7 is the same as that in the embodiment F-6. In this manner, the structure of this embodiment can be constituted by equivalently using transistors. (Embodiment F-8) Application to Laser In the above embodiments, the light-emitting thyristors have been described as the light-emitting elements. In the following embodiment, a case will be described wherein laser thyristors are used. Figs. 45 and 46 show a structure of an embodiment F-8. Fig. 45 is a plan view of the embodiment F-8, and Fig. 46 is a sectional view thereof. Basically, a thyristor portion is constituted as a laser thyristor, and a coupling diode is provided in its cavity portion. This structure adopts the equivalent circuits of the embodiments F-5 and F-7. A manufacturing method will be briefly described. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (non-doped) GaAs layer 123, an n-type AlGaAs layer 122, a p-type AlGaAs layer 121, and an upper electrode layer 20 are sequentially stacked on an n-type GaAs substrate 1. The upper electrode layer 20 is then photo etched into a rectangular shape having the same width as that of the n-type AlGaAs layer 125 in Fig. 46. Using the electrode pattern 20 as a mask, the p-type AlGaAs layer 121 to the n-type AlGaAs layer 125 are etched to form element isolation grooves 50. The upper electrode pattern 20 is further etched into a stripe pattern (current injection portion of a laser thyristor) having a width of 10 µm or less and a coupling laser diode pattern (D -1 D 1 portions). Using these patterns as masks, the p-type AlGaAs layer 121 and the n-type AlGaAs layer 122 are etched. The n-type AlGaAs layer 122 is not entirely removed but is partially left. Thereafter, an insulating film 30 is formed. The insulating film preferably has two functions, i.e., insulating and light shielding functions, and may be formed by a plurality of types of films. When an SiO 2 film is used as the insulating film, it allows light having a light-emission wavelength of 870 nm of GaAs to pass therethrough, it may induce light coupling. Thus, a light-shielding film of a light absorption material such as amorphous silicon must be formed between the SiO 2 films. Contact holes C 1 are formed by photoetching. A metal wiring layer for transfer clock lines is formed by deposition or sputtering, and the transfer clock lines  1 and  2 are then formed by photoetching. Finally, the end face of a laser beam output side is formed by cleavage or the like to have good parallelness, thus completing the structure of this embodiment. In this embodiment, the equivalent circuits of the embodiments F-5 and F-7 are applied to a laser. Alternatively, the equivalent circuits in the embodiments F-1 and F-4, i.e., including resistors, can form a laser, as a matter of course. In the structure of this embodiment, if p and n conductivity types are reversed, the structure of this embodiment can operate as described above if a bias condition and the like are inverted. Such a modification is also included in the scope of the present invention. In the above embodiments, control electrodes of adjacent light-emitting elements are connected through an electrical means to form a network. Every other light-emitting elements are connected to each other, so that two systems of scanning functions can be provided to a single light-emitting element array. In a two-dimensional or three-dimensional light-emitting element array, light-emitting elements are connected to four or six or more light-emitting elements through electrical means. Embodiments G Embodiments G described herein can widen a transfer clock pulse voltage range in the embodiments F described above. (Embodiment G-1) Fig. 47 is an equivalent circuit diagram showing the principle of an embodiment G-1. In this embodiment, a most typical three-terminal light-emitting thyristor is used as a light-emitting element whose light-emitting threshold voltage and current can be externally controlled. Each thyristor is constituted by a combination of a pnp transistor Tr1 and an npn transistor Tr2. The base of a transistor Tr3 is connected to the base of the npn transistor Tr2, and constitutes a current-mirror circuit in combination with the npn transistor Tr2. Light-emitting thyristors T (-1) to T (1) are aligned in a line, and are connected through the current-mirror circuits. Light-emitting thyristors T (-2) to T (2) respectively have gate electrodes G -1 G +2 . Each gate electrode has a load resistor R L . A power source voltage V GK is applied to the gate electrode. Each of two transfer clock lines  1 and  2 is connected to the anode electrodes (emitters of the transistors Tr1) of every other individual light-emitting thyristors. Each clock line has a resistor Re for restricting a current of the clock line. An operation will be described below. Assume that the transfer clock  2 goes to high level, and the light-emitting element T (0) is turned on. In this case, the potential at the gate electrode G 0 is reduced to almost 0 V due to the characteristics of the three-terminal thyristor (to about 1 V in the case of a silicon thyristor). If the power source voltage V GK is 5 V, a current limited by the resistor R L flows from the gate G 0 . A current limited by the resistor Re flows from the emitter (anode). Since the transistors Tr2 and Tr3 constitute the current-mirror circuit, the transistor Tr3 has a current drive power proportional to the transistor Tr2. With this current drive power, a current is withdrawn through the resistor R L connected to the collector of the transistor Tr3 so as to decrease the potential of the gate electrode G 1 of the adjacent light-emitting element T (1) . By appropriately adjusting the drive power of the transistor Tr3, the potential of the gate electrode G 1 can be reduced to almost zero. Since the ON voltage of the light-emitting element T (1) if becomes a voltage higher than the potential of the gate electrode G 1 by a diffusion potential V df , an ON state can be transferred to the light-emitting element T (1) the voltage of the transfer clock  1 is higher than the diffusion potential V df . In this manner, the ON voltage of the light-emitting element T 1) is decreased, while the ON voltage of the light-emitting element T (-1) located at the opposite side is not changed. Even if the potential at the gate G 0 is reduced to almost zero, the voltage of the gate G -1 for determining the ON voltage of the light-emitting element T (-1) is not influenced thereby. As described above, the light-emitting element array using the current-mirror circuits is operated by transfer clock pulses ranging from V df to V GK + V df , and can be operated with a wide voltage margin of V GK . In this embodiment, the load resistor R L need not always be used, and the light-emitting element array can operate without this resistor. In this embodiment, two-phase transfer clock pulses are used. However, the structure of this embodiment can operate using clock pulses of three or more phases. (Embodiment G-2) In the embodiment G-1, the equivalent circuit has been described. In an embodiment G-2, an IC structure of the arrangement in the embodiment G-1 will be described. The gist of this embodiment lies in a structure wherein a current-mirror circuit (Tr2 and Tr3) can be formed in the same process as that of the light-emitting thyristor. Fig. 48 shows a general structure of the embodiment G-2. An n-type semiconductor layer 24, a p-type semiconductor layer 23, an n-type semiconductor layer 22, and a p-type semiconductor layer 21 are sequentially formed on a grounded n-type GaAs substrate 1. Isolation grooves 50 are formed by photolithography or the like and etching so as to pattern the above-mentioned structure into individual light-emitting elements T (-1) to T (+1) Anode electrodes 40 have an ohmic contact with the p-type semiconductor layers 21, and gate electrodes 41 have an ohmic contact with the n-type semiconductor layers 22. Insulating layers 30 are formed to prevent short-circuiting between the elements and wirings, and at the same time, serve as protection films for preventing deterioration of characteristics. Portions surrounded by a broken line correspond to transistors Tr3, and are connected to the gate electrodes 41. Each transistor Tr3 has a collector (22), a base (23), and an emitter (24). Each transistor Tr1 has an emitter (21), a base (22), and a collector (23). Each transistor Tr2 has a collector (22), a base (23), and an emitter (24). The base of the transistor Tr2 is electrically connected to the base of the transistor Tr3. The collectors of these transistors are isolated from each other. Each gate electrode 41 is connected to a power source V GK through a load resistor R L , and the substrate 1 is grounded. The substrate 1 serves as the emitters of the transistors Tr2 and Tr3. The insulating layers 30 are preferably formed of a material allowing light having a light-emission wavelength of a light-emitting thyristor to pass therethrough well. On the other hand, if light coupling occurs between the elements, the transfer operation of this embodiment may be influenced by the light coupling. In order to prevent this, each gate electrode partially extends into the isolation groove between the adjacent light-emitting elements so as to employ a structure capable of preventing light coupling. The structure of this embodiment is the same as the equivalent circuit shown in the embodiment G-1 (Fig. 47), and performs the same operation. Therefore, if the high-level voltages of the transfer clocks  1 and  2 are set to alternately slightly overlap each other, the ON state of the light-emitting thyristors is sequentially transferred. That is, a light-emission point is sequentially transferred. (Embodiment G-3) Figs. 49, 50 and 51 show an embodiment G-3. This embodiment presents a practical structure of the embodiment G-2. Fig. 49 is a plan view of this embodiment, Fig. 50 is a sectional view taken along a line X-X' in Fig. 49, and Fig. 51 is a sectional view taken along a line Y-Y' in Fig. 49. Fig. 49 will be described below. A load resistor R L connected to the gate of each light-emitting thyristor is represented by a load resistor 63, and is formed by a semiconductor layer constituting light-emitting thyristors T (-1) to T (1) . The collectors of current-mirror transistors Tr3 (-1) to Tr3 (1) are connected to gate electrodes 41 through contact holes C 1 . The contact holes C 1 are connecting holes for connecting the semiconductor layers and the electrodes. Anode electrodes 40 of the light-emitting thyristors are connected to transfer clock lines  1 and  2 through connecting holes C 2 as through holes. A power source line 42 is connected to a power source voltage V GK , and is connected to the load resistors 63 (i.e., R L ). The power source line 42 is formed simultaneously with the gate electrodes 41. The gate electrodes 41 also serve as light shielding layers for preventing the light-emitting elements T (-2) to T (+1) from mutual influences upon their light emission. Fig. 50 is a sectional view taken along a line X-X', and Fig. 51 is a sectional view taken along a line Y-Y'. The light-emitting elements are formed as follows. An n-type GaAs layer 24b, an n-type AlGaAs layer 24a, a p-type GaAs layer 23a, an n-type GaAs layer 22a, a p-type AlGaAs layer 21b, and a p-type GaAs layer 21a are sequentially formed on an n-type GaAs substrate 1. Isolation grooves 50 for isolating the resultant structure into individual light-emitting elements are formed by photolithography or the like and etching. An isolation groove 51 is formed to isolate the light-emitting element T (0) and the current-mirror transistor Tr3. Each load resistor 63 (R L ) is formed of the n-type GaAs layer 22a of the light-emitting element. The resistor may be formed of another layer. For example, the resistor may be formed of the p-type GaAs layer 23a or may be formed as another resistor region. A manufacturing process of the embodiment G-3 will be described below. The n-type GaAs layer 24b, the n-type AlGaAs layer 24a, the p-type GaAs layer 23a, the n-type GaAs layer 22a, the p-type AlGaAs layer 21b, and the p-type GaAs layer 21a are sequentially formed on the n-type GaAs substrate 1. The isolation grooves 50 are then formed to isolate the light-emitting elements and the resistors. The p-type GaAs layer 21a and the p-type AlGaAs layer 21b corresponding to gate lead portions and prospective transistor Tr3 portions are removed, and the isolation grooves 51 are formed. In the step of removing these p-type layers 21b and 21a, a portion of the p-type GaAs layer 22a serving as the resistors 63 is simultaneously removed. The insulating films 30 are formed, and the contact holes C 1 are formed therein. Thereafter, the electrodes 40, 41 and 42 are formed. The insulating films 31 as insulating interlayers are formed, and the through holes C 2 are formed. Thereafter, the electrodes  1 and  2 are formed. With the above-mentioned process, the structure of the embodiment G-3 is completed. Embodiments H Embodiments H described herein are related to composite elements each constituted by combining the light-emitting element array described above and a light deflector. (Embodiment H-1) When a composite element of this embodiment is applied to an optical scanning apparatus used in, e.g., an optical printer, optical scanning with high resolution can be realized. There are two typical optical scanning systems applied to a conventional optical printer. One system has a means H for deflecting a laser beam La or the like emitted from a light-emitting element T, as shown in Fig. 61. The other system causes an array T of n light sources arranged in series to sequentially flash and scan or causes a shutter array to open/close and scan (Fig. 62). A typical apparatus of a light deflection system is a rotary polygonal mirror, which has advantages of a large deflection angle and a high resolution. However, such an apparatus is not easily made compact, an optical system requires a complex adjustment, and tends to be influenced by a mechanical vibration. Thus, the apparatus is not suitable for an application requiring high precision. As a light deflector capable of eliminating such drawbacks, one utilizing modulation of a refractive index using an acoustic-optical effect, electro-optical effect, or the like is known. Since such a deflector is a solid element, it can be easily rendered compact. Since the deflector includes no movable portion, it can be easily adjusted, and is not easily influenced by a mechanical vibration. Therefore, a scanning light spot has high positional accuracy. However, the deflection angle is small and resolution is low as compared to deflection by a mechanical means such as a rotary polygonal mirror, thus restricting its application range. Generally, optical scanning by deflection has an advantage that the number of light sources can be reduced. However, such an advantage leads to difficulty residing in maintaining light intensity constant on a light-receiving surface 100 for a wide optical scanning width. An optical scanning system using light source array or a shutter array originally includes no movable portion, and is also advantageous in that total scanning width can in principle be desirably increased in proportional to the number of array elements. However, a wide scanning width needs a lot of array elements such as optical shutters, so that the number of of circuits (ICs) for driving these elements is increased accordingly. As a result, a manufacturing process such as wire bonding becomes complicated. This problem can be solved by using a light-emitting element array according to the present invention, and the number of circuits for driving the light-emitting element array can be greatly reduced, thus allowing an easy increase in optical scanning width. When the above-mentioned self-scanning array employed, the scanning width can be easily increased in optical scanning system by a large number of light-emitting elements. However, light-emitting elements and light spots to be scanned have a one-to-one correspondence regardless of the scanning width. Therefore, in order to improve resolution of the light spot, a light-emission area of the light-emitting element must be reduced and an interelement pitch must be shortened. However, the light-emission area has a lower limit as long as a light-emitting element is required to provide a light output of certain intensity. Therefore, the optical scanning using the array makes it difficult to reduce the pitch of light spots below a certain limit to improve resolution. According to a composite element array of this embodiment, the conventional problem can be solved. For example, a large number of light-emitting elements described in the embodiments B are linearly, two-dimensionally or three-dimensionally arranged, and control electrodes of the light-emitting elements are connected, as shown in Fig. 9. A light deflector capable of controlling an output direction of light emitted from each light-emitting element is provided to each light-emitting element so as to constitute a composite element array. As to the light deflector, arbitrary elements such as one causing a gradient of a refractive index upon injection of a current, one for applying an electric field to control a refractive index and the like, may be used as long as they can deflect incident light. In this embodiment, as shown in Fig. 52, a large number of light deflectors H paired with light-emitting elements T are linearly arranged. A light deflector which receives a light beam La emitted by each light-emitting element T (i) is represented by H (i) . The basic operation of the composite element array with the above structure will be described below. A light beam is emitted from a light deflector H (0) and reaches a point x 0 on a light-receiving surface 100. Control is made such that the light deflector H (0) starts a deflection operation at the same time when the light-emitting element T (0) is turned on. A deflection beam from the light deflector H (0) is moved in a direction of an arrow d , and reaches an end point x 1 on the light-receiving surface 100. At the same time, the deflection beam causes the next light-emitting element T (1) to emit light, and the light deflector H (1) to start the operation. In this case, adjustment is made to cause the position of a light spot formed by the deflected light beam radiated at the end point x 1 to coincide with the spot position of the deflection start point (x 1 ) of the light deflector H (1) . Thus, if similar setting and control are made, continuous, wide-range optical scanning can be realized by this system. Of the resolution of the light deflectors H is represented by N, accuracy can be increased by N times without increasing the number of light-emitting elements. If the number of light-emitting elements is M, the total number of elements is 2M when the light deflectors are added to the light-emitting elements. Therefore, if N > 2, accuracy can be improved as compared to an array including only the 2M light-emitting elements. Thus, even though the resolution of the light deflector used in this embodiment is not so high, a remarkable effect can be obtained. An AlGaAs/GaAs-type composite element of the embodiment H-1 will be described in the detail below. A semiconductor laser with a light deflection function is disclosed in Electronic Letters, Vol. 23, p. 361 (1987). Two electrodes are arranged at two sides of a semiconductor waveguide along which light output from a semiconductor laser propagates, and currents having asymmetrical magnitudes are injected into these electrodes, so that a refractive index of a waveguide portion is caused to have a gradient, thus performing light deflection. In this embodiment, a semiconductor laser which has good beam convergence is employed as a light-emitting element T. Since threshold current control is performed, a laser thyristor is used. A light deflector H employs a device utilizing current injection as in the above-mentioned article, two electrodes are constituted by thyristors to achieve control by an external signal. The light-emitting elements T and light deflectors H are arranged in an array, as shown in Fig. 52, and are connected in the same manner as the network shown in Fig. 9, thus constituting a component element array. Fig. 53 shows interelement electrical connection. A plurality of light-emitting elements T are connected through resistors R I and R L in the same manner as in Fig. 9. A plurality of current injection elements H1 and H2 constituting a plurality of light deflectors H receive a power source voltage V' GK through load resistors R' L at their gate electrodes. The gate electrodes are electrically connected through resistors R' I so as to provide an interaction. These light-emitting elements T and the current injection elements H1 and H2 are connected so that currents I T controlled by light-emission signals  I ,  I and  I " flow in the elements through lines  1 ,  2 , 3 ,  1 ',  1 ',  3 ',  1 ",  2 " and  3 ". Fig. 54 is a partial plan view of a composite element array for realizing the above-mentioned electrical connection and light coupling. This arrangement is an example, and a different electrical wiring pattern may be employed as long as the elements are arranged so that laser output beams La from the laser thyristors T are efficiently incident on the light deflectors H. The resistors R I in this embodiment may be replaced with diodes as described in embodiments F. Thus, the number of clock lines can be decreased to two. Figs. 55 and 56 show sectional structures corresponding to an AlGaAs/GaAs-type laser thyristor array portion T (X-X' in Fig. 54) and a light deflector portion H (Y-Y' in Fig. 54). The device structure of the composite element will be briefly described. The laser thyristor T and the light deflector H have a common crystal layer structure. This is not a necessary condition. However, in order to simplify a manufacturing process, a common crystal layer is preferably used. An appropriate n-type GaAs buffer layer (although not shown in Fig. 55) is formed on an n-type GaAs substrate 1. An n-type AlGaAs layer 125, a p-type AlGaAs layer 124, an i-type (non-doped) GaAs layer 123, an n-type AlGaAs layer 122, and a p-type AlGaAs layer 121 are sequentially formed on the buffer layer. A p-type GaAs layer may be formed as an uppermost contact layer on the resultant structure. The i-type (non-doped) GaAs layer 123 serves as an active layer of the laser, and AlGaAs layers 122 and 124 formed on the two major urfaces of the layer 123 serve as cladding layers. In the laser thyristor T of this embodiment, ridges 53 are formed by partially removing the uppermost layer 121 to the halfway of the upper cladding layer 122. The laser structure is not always limited to this, and a burying structure may be used. Gate electrodes 41 are formed on the n-type AlGaAs layer 122 serving as the upper cladding layer. An end face 66 (Fig. 54) on the side of the deflector H of an optical resonator of the laser thyristor T is formed by, e.g., dry etching. The other end face 67 may be formed by a cleavage method. The light deflector H is constituted by the same multilayer structure as that of the laser thyristor T. The current injection elements H1 and H2 are arranged at symmetrical positions with respect to a light propagation direction, and have the same thyristor structures as that of the laser thyristor T. The p-type AlGaAs layers 121 immediately under upper electrodes 71 and 72 are isolated by an isolation groove 52 so as to prevent a lateral current. Gate electrodes 41 are formed on the n-type AlGaAs layer 122 by removing the upper layers in the same manner as in the laser thyristor portion. Each light deflector H is arranged at a position capable of efficiently receiving a beam La output from the laser. However, the laser and the deflector must be electrically isolated. Fig. 57 is a perspective view of a composite element described in the above-mentioned article (Electronic Letters, 1987). Crystal growth used in the above element formation can be achieved by LP-CVD, MO-CVD, or MBE. In this embodiment, since the laser employs a GaAs active layer, a light-emission wavelength is about 900 nm. However, the material is not limited to GaAs. If AlGaAs is used, the wavelength can be shortened to about 780 nm, while if InGaP or AlGaInP is used, it can be shortened to the order of 600 nm. These materials may be selected depending on applications. A drive method of the optical scanning composite element will be described below. Under the connection relationship shown in Fig. 53, clock pulses are sequentially applied to the laser thyristors T (-1) , T (0) and T (1) through the lines  2 ,  3 and  1 at timings shown in Fig. 58 so as to be turned on. A laser drive current is supplied from the line  I to turn on and scan each laser. Pulses which rise earlier by Δt than the clock pulses are sequentially applied to pairs of thyristors H1 (-1) , H2 (-1) , H1 (0) , H2 (0) , H1 (1) and H2 (1) of the light deflectors H (-1) , H (0) and H (1) through lines  1 ',  1 ",  2 ',  2 ",  3 ' and  3 ". For example, the clock pulse is applied to the line  3 , and pulses are applied to the two thyristors H1 (0) and H2 (0) of the light deflector H (0) from the lines  3 ' and  3 " immediately before the laser T (0) is turned on, so that these thyristors are turned on. When the laser T (0) is turned on, symmetrical ramp signals I T1 and I T2 are applied from the lines  1 ' and  2 " to the thyristors H1 (0 ) and H 02(0) . The clock pulse becomes zero when the next clock pulse is sent to the line  1 , and the ramp currents are returned to the initial values. Thus, the thyristors H1 (0) and H2 (0) are turned off. At this time, the thyristors H1 (1) and H2 (1) of the adjacent light deflector H (1) have already been turned on, and start a deflection operation when the adjacent laser T (1) is turned on. Thereafter, the elements are operated at the similar timings. (Embodiment H-2) In an embodiment H-2, a light deflector of a type of controlling a refractive index by an electrical field is employed as the light deflector H to constitute a composite element. As is well known, the light deflector utilizing such an effect can be realized by using a dielectric crystal prism having an electro-optical effect. In the case of a semiconductor, not only the electro-optical effect but also Franz-Keldysh effect or a quantum trapping Stark effect using a quantum well can be utilized by applying a reverse bias to a junction. If such a composite effect is applied to a semiconductor waveguide, a semiconductor deflector can be easily anologized from the above dielectric element. Fig. 60 shows its structure. In this structure, an n-type AlGaAs layer 125, an i-type (non-doped) GaAs layer 123, and a p-type AlGaAs layer 121 are formed on an n-type GaAs substrate 1, and electrodes 73 and 74 are formed on two major surfaces of the resultant structure. A negative voltage is applied to the electrode 74 relative to the electrode 73, the i-type (non-doped) GaAs layer 123 is depleted, and an electric field is applied thereto. Depending on this electric field intensity, the refractive index of the i-type (non-doped) GaAs layer 123 is changed. Therefore, the refractive index under the electrode 74 is different from that of other regions, and this difference can be externally controlled. Thus, the direction of an output beam Lh can be controlled. The light deflector H and the laser thyristor T are combined to realize a composite element. The same laser thyristor and arrangement as in the embodiment H-1 may be employed. However, since the light deflector of this embodiment is used in a reverse bias state, power consumption is small, and no problem is posed even if all the elements are always operated. In this case, the clock line need only be formed for the light-emitting element T, as shown in Fig. 59, and no gate electrodes are required for the light deflector H. Only a line for supplying a common ramp voltage V' GK is formed. Of course, the start and end points of this ramp voltage must be caused to coincide with turn-on and turn-off timings of each laser. Note that the light deflector H in Fig. 60 has a simplest structure, and may employ another structure. For example, a light waveguide layer may comprise a quantum well layer. In this case, a quantum well laser thyristor is preferably employed to facilitate a manufacturing process. The electrode shape is not limited to that shown in Fig. 60 as long as it can effectively form asymmetrical refractive index distribution. Furthermore, constituting materials need only be those having the above-mentioned effect, and at least materials described in the embodiment H-1 can be utilized. As described above, when light deflectors are added to light-emitting elements, resolution of scanning light spots can be improved as compared to a composite element including only a light-emitting element array without increasing the number of light-emitting elements. Since the threshold current or voltage of the light-emitting elements can be controlled and their control electrodes are connected through electrical means, a simple scan system can be established only by applying drive clocks. Drive circuits are not complicated for an arrangement including the light deflectors. The above embodiments solve the conventional problems, e.g., the number of wire bondings, drive ICs, miniaturization, and a decrease in pitch, by providing a self-scanning function to a light-emitting element array itself. When the light-emitting element array itself scans, no drive ICs are required, and, hence, wire bonding can be omitted. The above embodiments also provide a light-emitting array which can stably and reliably perform turn-on self-scanning. The above embodiments provide a light-emitting array which can facilitate external self-scanning control, and can widen a control margin so as not to cause an erroneous operation. The above embodiments provide a self-scanning light-emitting element array which has a simple integrated circuit structure to facilitate its manufacture. The above embodiments provide a self-scanning light-emitting element array which has a simple integrated circuit structure to facilitate its manufacture. The above embodiments provide a self-scanning light-emitting element array which has directivity in a self-scanning function in an element array direction so that turn-on transfer can be performed by two-phase clocks. The above embodiments provide a self-scanning light-emitting element array which can allow control for increasing a luminance of at least one element at an arbitrary position in the light-emitting element array, so as to obtain an image display function. The above embodiments provide a self-scanning light-emitting element array which can obtain light-point scanning performance sufficiently finer than an array pitch of light-emitting elements. The above embodiments provide a method of driving a light-emitting element array, suitable for stably and reliably performing self-scanning of the light-emitting element array, and simplifying an integrated circuit structure of the array. The above embodiments incorporate a method of driving a light emitting array, in which turn-on transfer is driven in response to clocks, and transfer control and sync control of an image display are realized.

Claims: A self-scanning light-emitting array comprising: an array of light-emitting elements (T) having controllable turn-on threshold levels; at least two transfer lines ( 1 , 2 ) alternatingly connected in sequence in an array direction to alternating ones of said light-emitting elements (T); polyphase clock means connected to said transfer lines ( 1 , 2 ) and arranged to apply drive pulses repeatedly in sequence to said transfer lines; and coupling means (R; D) for coupling said light-emitting elements (T) so that a light-emitting element in at least a threshold-reduced state reduces the turn-on threshold level of the next light-emitting element in the direction of scanning whereby said next light-emitting element is capable of responding to a respective drive pulse by entering the threshold-reduced state; characterised in that means (I 1 , I 2 ), responsive to a light emission signal ( l ) specifying light-emitting elements at particular positions in the array to emit light, are arranged to supply additional current (I T ) to said transfer lines ( 1 , 2 ) whereby respective light-emitting elements in a threshold-reduced state at said particular positions receive the additional current (I T ). An array according to claim 1, wherein said light-emitting elements (T) are arranged in either a linear array or a two-dimensional arrangement. An array according to claim 1 or claim 2, wherein said polyphase clock means is operable to generate drive pulses such that a trailing period of a drive pulse on a given transfer line overlaps a leading period of the next drive pulse on the adjacent transfer line. An array according to claim 1, claim 2 or claim 3, wherein said polyphase clock means has two phases and is connected to said light-emitting elements (T) in alternating manner through two transfer lines ( 1 , 2 ), said coupling means being undirectional means (D). An array according to claim 1, claim 2 or claim 3, wherein said polyphase clock means has three phases and is connected to said light-emitting elements (T) in sequential manner through three transfer lines ( 1 , 2 , 3 ). An array according to any one of the preceding claims, comprising means for shielding light between adjacent light-emitting elements (T). An array according to any one of the preceding claims, wherein said coupling means comprises diodes (D). An array according to any one of claims 1 to 6, wherein said coupling means comprises transistors (Tr). An array according to claim 1, wherein each said light-emitting element (T) has a cell consisting of main and subsidiary light-emitting elements each having an anode and an upper gate, said anode and upper gate of said main light-emitting elements in one cell being connected to those of said subsidiary light-emitting elements in the next cell. An array according to any one of the preceding claims, wherein said means for supplying additional current comprises luminance control means operable to supply a corresponding current in response to an image signal to cause said threshold-reduced state light-emitting element (T) to increase its light intensity. An array according to any one of the preceding claims, wherein a first said light-emitting element (T 0 ) is disposed at a leading end portion of said array and is responsive to a one-shot pulse ( s ) thereby to turn on at the beginning of self-scanning. An array according to any one of the preceding claims, wherein each light-emitting element (T) is a laser thyristor having a laser beam output emitted perpendicularly to its longitudinal direction, and further comprising an array of beam deflectors (H) each arranged in front of said laser thyristor to deflect said laser beam output. An array according to claim 12, wherein each beam deflector (H) has first and second anodes arranged at respective sides of the laser beam output path, and including a beam deflector current source means operable to supply currents having symmetrical magnitude to said first and second anodes of the beam deflector associated with the threshold-reduced state laser thyristor to form a gradient refractive index distribution across the laser beam output path. An array according to claim 13, wherein said beam deflector current source means is operable to supply currents having waveforms which are ramp-shaped with opposite gradient slopes, so that, in operation, output light from the associated laser thyristor is deflected to the left and right about the centre of the output path. An array according to claim 14, wherein said anode of said beam deflector has a thyristor structure, each of two thyristor arrays constituted by the elements comprises a structure equivalent to said coupling means and said clock means provided to said light-emitting array to shift a minimal conducting state in the longitudinal direction, and said clock means of the beam deflector is operable to supply clock pulses synchronously with the clock pulses from the clock means of the laser thyristors to said thyristor array, and to supply the ramp waveform currents superposed on the clock pulses to said thyristor arrays. An array according to claim 12, wherein each beam deflector comprises a dielectric crystal prism for controlling a refractive index with an electric field. An array according to claim 16, including means for supplying a ramp voltage synchronous with a turn-on shift of said light-emitting array to said dielectric crystal prism. An array according to any one of the preceding claims, in which said coupling means comprises a resistor network (R I ) for coupling gates (G) of the light-emitting elements (T) for controlling the threshold levels of the light-emitting elements in the array direction. An array according to claim 18, wherein said resistor network comprises one resistor layer bonded to said gates (G) and a conductor extending in the array direction, the conductor being arranged to receive a constant voltage. An array according to claim 19, wherein said resistor layer comprises a p-type or n-type semiconductor layer. An array according to claim 18, claim 19 or claim 20, wherein said light-emitting elements (T) include a gate layer integral with said coupling resistors and having a plurality of notches to provide said coupling resistors. An array according to claim 21, wherein said gate layer extends in the array direction, and its internal resistance provides the coupling resistors. An array according to claim 22, wherein the width of said gate layer perpendicular to the array direction is decreased to adjust the resistance of said resistor network. An array according to any one of the preceding claims, comprising load resistors (R L ) for coupling gates (G) of the light-emitting elements (T) to a voltage line. An array according to any one of claims 1 to 17, in which said coupling means includes a transistor having its base connected to a lower gate of a light-emitting element (T), and its collector connected to an upper gate of the next light-emitting element. An array according to claim 25, further comprising a load resistor (R L ) between the collector of each transistor and a bias line. An array according to claim 25 or claim 26, wherein said light-emitting element (T) comprises a cell consisting of a light-emitting thyristor having upper and lower gates and connected to said transfer line, and a transistor having a base integral to said lower gate so that the output of said transistor in said cell is coupled to said upper gate in the next light-emitting thyristor. An array according to claim 18 or claim 25, wherein gate metallization extends to a groove between adjacent light-emitting elements (T) to shield the light coupling therebetween. An array according to claim 18 or claim 25, wherein said light-emitting element (T) comprises a light-emitting thyristor. An array according to claim 18 or claim 25, wherein said light-emitting element (T) comprises a laser thyristor.

Inventors: KUSUDA YUKIHISA, TANAKA SHUHEI, TONE KIYOSHI, YAMASHITA KEN, KUSUDA, YUKIHISA, TANAKA, SHUHEI, TONE, KIYOSHI, YAMASHITA, KEN, KUSUDA, YUKIHISA C/O NIPPON SHEET GLASS CO., LTD., TANAKA, SHUHEI C/O NIPPON SHEET GLASS CO., LTD., TONE, KIYOSHI C/O NIPPON SHEET GLASS CO., LTD., YAMASHITA, KEN C/O NIPPON SHEET GLASS CO., LTD.
Applicants: NIPPON SHEET GLASS CO LTD, NIPPON SHEET GLASS CO., LTD.
Application year: 1989
Main classification: H01L33
IPC codes: H01S5, G06K15, B41J2, H01L27, H01L33