TABLECLOTH MEMORY MATRIX WITH STAGGERED EPROM CELLS

Abstract: The memory matrix comprises parallel and alternating source (S) and drain (D) lines, floating gate areas (F) placed between the source and drain lines (S, D) and control gate lines (G) parallel to each other and perpendicular to the source and drain lines (S, D) superimposed on the floating gate areas (F). The floating gate areas (F) are arranged in rows parallel to the source and drain lines (S, D) in positions longitudinally staggered in relation to those of the adjacent row in such a manner that the floating gate areas (F) of one row (A′) underlie a first plurality (G′) of control gate lines (G) and the floating gate areas (F) of the adjacent row (A″) underlie a second plurality (G″) alternating with the first (G′) of the control gate lines (G). The floating gate areas together with the adjacent source and drain lines (S, D) and with the superimposed control gate lines (G) define respective EPROM cells (C) arranged in a staggered manner in the memory matrix.

Description: The present invention relates to a tablecloth memory matrix with staggered EPROM cells. In the manufacture of a memory matrix, in particular with EPROM cells, it is important to increase to the maximum the density of the individual cells in order to improve the performance of and utilize better the available area. This requires the search for and use of ever more advanced technologies, especially in photolithography, where the definition of ever smaller structures is required down to submicron dimensions such as 0.8 micrometres. Despite such technologies, it is ever more difficult to reduce cell size so that research is directed toward new structures capable of overcoming these problems. In the field of EPROM cells, from the conventional configuration calling for pairs of control gate lines superimposed on and self-aligned with floating gate areas alternating with parallel source lines while drain contacts are placed between one gate line and the next of each pair the step was made a few years ago to a so-called 'tablecloth' configuration calling for parallel and alternating source and drain lines, floating gate areas placed between said source and drain lines, and parallel control gate lines perpendicular to said source and drain lines, superimposed on and self-aligned with said floating gate areas. The new configuration is described better in Italian patent application 23479 A/84 filed 7 November 1984 by the same applicant which is the priority document of FR-A-2 572 836, and has proven beneficial compared with the conventional one as regards size problems, achieving levels of miniaturization, cell density and compactness worthy of interest. The complexity of the decoder required to accede to the individual cells has however discouraged practical application. To overcome this shortcoming the original tablecloth configuration was subsequently modified into a configuration called 'semitablecloth', which is structurally equivalent to the tablecloth configuration but which, thanks to appropriate electrical connections, has each cell made up of two semicells which are written and read simultaneously. With the semitablecloth configuration, better described in Italian patent application 19656 A/87 filed 12 March 1987 by the same applicant it proved possible to use a conventional decoder. To this was added the important advantage of offering 100% redundancy, it being practically impossible that both the semicells of a given cell prove defective. On the other hand this configuration has the defect of occupying much space. In view of this state of the art the object of the present invention is to accomplish a memory matrix with EPROM cells which would provide the dimensional and compactness virtues of the presently known tablecloth matrix while simplifying the access procedure in such a manner as to permit the use of a conventional decoder. In accordance with the invention said object is achieved by a memory matrix with EPROM cells comprising parallel and alternate source and drain lines, floating gate areas placed between said source and drain lines, and parallel control gate lines perpendicular to said source and drain lines superimposed on said floating gate areas characterized in that said floating gate areas are arranged in rows parallel with said source and drain lines in longitudinally staggered positions in relation to those of the adjacent row in such a manner that the floating gate areas of one row underlie a first plurality of said control gate lines and the floating gate areas of the adjacent row underlie a second plurality of said control gate lines alternating with the first. It is clear that the staggered arrangement of the floating gate areas determines a corresponding staggered arrangement of the various cells of the matrix and allows a quite compact structure with minimal dimensions even though there is no longer the reduncancy of the semitablecloth matrix. At the same time it is possible to access the individual cells of the matrix by using a conventional decoder. The characteristics of the present invention will be made clearer in the following detailed description of one of its possible practical forms of embodiment illustrated as a nonlimiting example in the annexed drawings wherein: FIG. 1 shows a schematic plan view of a portion of a memory matrix with EPROM cells staggered in accordance with the present invention, FIG. 2 shows an enlarged cross section along line II-II of FIG. 1 of a detail of said memory matrix, and FIG. 3 shows an enlarged cross section along line III-III of FIG. 1 of another detail. The so-called 'tablecloth' structure of FIG. 1 comprises a single-crystal silicon substrate SS on which are made by the diffusion of appropriate dopant two pluralities of parallel alternating source S and drain D lines separated by field oxide areas OC. The whole is covered by a thin oxide layer OS (FIGS. 2 and 3). Between each source line S and the adjacent drain line D there are parallel to said lines a row of floating gate areas F each of which is made up (FIGS. 2 and 3) of a rectangular strip of polysilicon which extends over the thin oxide OS from one field oxide area OC to the other. On each strip there is a similar layer of dielectric oxide OD replaceable by a composite layer of oxide-nitride-oxide (the so-called ONO) and over that another similar strip of polysilicon P which forms a single body with a respective one of a plurality of control gate lines or bit lines G of silicide or polysilicide arranged parallel to each other and perpendicular to the source S and drain D lines. Each group F, OD, P together with the adjacent source S and drain D lines and with the superimposed control gate line G constitutes a respective elementary EPROM cell C isolated from the others through a thick oxide layer OSS. As may be seen in FIG. 1 the cells C are arranged along parallel rows placed between the source S and drain D lines and those of one row are staggered longitudinally in relation to those of the adjacent row in the sense that the cells of a row A' have their own floating gate areas F overlaid by a first plurality of control gate lines G' while those of the adjacent row A'' are overlaid by a second plurality of control gate lines G'' alternating with the first. From the described structure there derives the following manner of operation of the memory matrix. Desiring to write any cell C it is necessary to bring to writing voltage, e.g. 12V, the control gate line (or 'bit line') G which passes through the selected cell while all the others must be held at low voltage or grounded. In addition writing voltage must be given to the drain line D of the selected cell while all the other drain D and source S lines are kept grounded. Reading must be performed in a similar manner, modifying the voltages applied but again making the selection through a control gate line G and a drain line D. It is thus possible to access a single cell at a time with no need for using decoders different from conventional ones.

Claims: Memory matrix with EPROM cells comprising parallel and alternating source (S) and drain (D) lines, floating gate areas (F) placed between said source (S) and drain (D) lines and control gate lines (G) parallel with each other and perpendicular to said source (S) and drain (D) lines superimposed on said floating gate areas (F) characterized in that said floating gate areas (F) are arranged in rows parallel to said source (S) and drain (D) lines in positions longitudinally staggered in relation to those of the adjacent row in such a manner that the floating gate areas (F) of a row (A′) underlie a first plurality (G′) of said control gate lines (G) and the floating gate areas (F) of the adjacent row (A'') are subjected to a second plurality (G'') alternating with the first (G') of said control gate lines (G). Memory matrix in accordance with claim 1 characterized in that each floating gate area (F) consists of a polysilicon strip (F) which extends parallel to said source (S) and drain (D) lines between opposing field oxide areas (OC) and between said source (S) and drain (D) lines, there being superimposed on said polysilicon strip (F) a similar layer of dielectric oxide (OD) and over that a similar polysilicon strip (P) forming a single body with a respective control gate line (G).

Inventors: MAZZALI, STEFANO
Applicants: SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1989
Main classification: H01L27
IPC codes: H01L21, H01L29, H01L27