A decoding method and apparatus for decoding code words that are wordwise protected by a non-binary BCH code against at least one symbol error

Abstract: There is described a decoding method and decoder apparatus for non-binary BCH-codes. Upon reception for an input word, first a syndrome information is generated. From this, the key equation is set up and solved to yield an error locator polynomial sig(z) and an error evaluator polynomial w(z). Next, on the basis of polynomial sig(z), its formal derivative polynomial sig′(z), Euclid's algorithm is used for calculating two accessory polynomials b(z), c(z), such that b(z)sig(z) + c(z)sig′(z) = 1. From these, a Lagrangian polynomial L(z) is calculated which for any inversed error location value has the associated error symbol value. The error data thereupon can be calculated by evaluating the error locator polynomial and the Lagrangian polynomial.

Description: FIELD OF THE INVENTION The invention relates to a decoding method for decoding code words that are wordwise protected by a non-binary BCH code against at least one symbol error. In most partical codes, each symbol contains a string of at least two bits. More generally, however, the cardinality of the symbol set is at least three. The invention is applicable to non-primitive BCH-codes as well as to primitive BCH-codes. In a primitive code the code length is exactly (2 n-1 ). In a non-primitive code the length can be any odd integer, the code being nevertheless still a cyclic code. The invention is applicable to narrow-sense BCH-codes as well as to non-narrow-sense BCH-codes. The invention is applicable to full-length codes as well as to shortened or punctured BCH-codes. All these exemplary sub-categories are well-known in the art and will not be explained in detail. The derivation hereinafter will only be given for one particular sub-category, to wit, a primitive, narrow-sense BCH-code. Extension to more general BCH-codes is straightforward. A further sub-category of BCH-codes are Reed-Solomon codes, wherein the finite field associated with the code symbols and the finite field for the decoding calculations are identical. In contradistinction thereto, the code symbols may also be defined on a sub-field of the field that is used for the calculations. Also here, the present invention applies to both categories. As far as the invention concerns, the symbols have more than two possible values, which means that localizing an error also necessitates finding an error value. The invention particularly suits codes that have a high distance, and thus could, in principle, correct many symbol errors for each code word. BACKGROUND ART CITATION A particular method according to the above has been disclosed in US patent 4,642,808 (PHN 10.710) assigned to the same assignee. The known code is a distance 21 code over 8-bit symbols, and is a Reed-Solomon code. The known method, improving on classical correction methods by in particular accelerating the decoding for a low number of symbol errors, still requires a long processing time and/or the use of complicated or special purpose hardware, when e.g. more than three errors occur. SUMMARY OF THE INVENTION Among other things, it is an object of the present invention to provide a decoding method which particularly, but not exclusively in the case of relatively large numbers of symbol errors, provides acceleration and/or simplification of the decoding. According to a first aspect, the invention thereto provides a decoding method for a non-binary BCH-code which provides wordwise protection against at least one symbol error, said method comprising the steps of: a. receiving a protected word and therefrom under control of code defining information generating a syndrome information; b. as based on said syndrome information setting up and solving a key equation for thereby generating an error locator polynomial sig(z) and an error evaluator polynomial w(z); c. by means of Euclid's algorithm and on the basis of the error locator polynomial sig(z) and its formal derivative sig′(z) calculating first and second accessory polynomials b(z), c(z) such that b(z).sig(z)+c(z).sig′(z) = 1; d. generating an intermediate polynomial L*(z) as based on the error locator polynomial, its formal derivative, the error evaluator polynomial, and the second accessory polynomial c(z) according to: L*(z) = -w(z).c(z) = -w(z) {1-b(z).sig(z)} sig′(z) e. generating a Lagrange polynomial L(z) as the minimal degree polynomial through any error occurred according to: L(z) = L*(z) mod sig(z). said Lagrange polynomial for any inversed error location value having the associated error value; f. evaluating the error locator polynomial sig(z) for producing a set of error locations in the received word for by substitution in the Lagrange polynomial generating an associated set of error values; g. outputting a set of error data, each error data represented by a location quantity and an associated error value quantity. The invention also relates to a decoder apparatus for executing the decoding method. Further advantageous aspects are recited in dependent Claims. BRIEF DESCRIPTION OF THE DRAWINGS A preferred embodiment of the invention is further explained, with respect to the appended drawings. First, the code is explained briefly; next a prior art decoding is shown, followed by a detailed description of the above preferred embodiment. In the Figures Figure 1 shows schematically a format of a code word; Figure 2 shows the decoding according to prior art; Figure 3 shows the decoding according to the present invention; and Figure 4 shows an apparatus for practising the decoding. DESCRIPTION OF PRIOR ART DECODING Figure 1 schematically shows a format of a code word which consists, by way of example, of 32 symbols of eight bits each c o ..c n-1 that have been numbered from right to left. The word has 22 data symbols D and ten parity symbols P all symbols being shown as blocks. The code word can be expressed as a vector c =(c o ..c n-1 ) or, according to formula A in polynomial notation. Each code word is a multiple of the generator polynomial g(z), as shown in formula B, m(z) also being a polynomial. The zeroes of the generator polynomial define the distance properties, and thus the amount of error protection, of the code. Decoding boils down to assigning to each word received a best-fitting code word. Figure 2 is a diagrammatic representation of so-called time-domain decoding according to prior art. The input (block 20) receives the actual, possibly erroneous word, as represented by either vector (r i ) or polynomial (r(z)) notation. Syndrome generator 20 may comprise elementary hardware to evaluate r(z) in the zeroes of the generator polynomial g(z) thereby generating what is commonly called the weighted power sum symmetric functions denoted S j , or syndrome polynomial S(z). The syndrome can be found by standard polynomial evaluation or residue calculations by means of hardware that is relatively simple in comparison to the so-called "random" division hardware to be discussed hereinafter. As an alternative, syndrome determination may be effected with hardware which to an appreciable extent corresponds to hardware used for encoding, in which case the device calculates r(z) mod g(z)=rem(z). This remainder polynomial rem(z) has degree d-1, where d is the distance of the code. Both representations rem(z), S(z) contain the same information; from rem(z), the power sum symmetric functions S j can easily be obtained by polynomial evaluation. Block 22 represents the setting up and solving fo the key equation, for example, according to the Berlekamp-Massey algorithm which computes the error locator polynomial sig(z) and the error evaluator polynomial w(z), as described in Berlekamp's Book "Algebraic Coding Theory", Algorithm 7.4. An alternative has been described in Mc. Eliece, "Theory of information and Coding", p. 175. In general, operations necessary thereto require multiplications and divisions of factors that each can have arbitrary values in the Galois field GF(q m ), wherein the decoding calculations are executed. Usually, such a device has a processor-like structure with all associated features, such as ALU, register set, control store, and I/O organization. Another possible realization could be as a systolic array. In both realizations, block 22 would be of an appreciable complexity. Block 24 receives the error locator polynomial sig(z) and is a so-called Chien search device. In elementary operations which, although representing a completely different function, on a level of technical implementation resemble the syndrome formation, therein the values of sig(z) are calculated in a prespecified set of points in the Galois field GF(q m ). Any zero of sig(z) so found would correspond to an associated error location. Thus, at output 28 any error location information Xi may be output for further use. The referenced patent US 4,642,808 discloses various shortcuts to the calculation of these error locations by obviating or streamlining the Chien search, based on algebraic analysis and statistical considerations. Block 26 receives from block 22 the error evaluator polynomial w(z), from block 24 the various error locations so found and also, either directly as a sub-quantity of sig(z), or after a separate calculation in block 22, the formal derivative polynomial sig′(z). For the case wherein all symbols are bit strings, this formal derivative in fact consists of the even-numbered components of sig(z), which is to be evaluated at the various error locations. Block 26 executes the standard Forney algorithm. For narrow-sense BCH codes this boils down to for each error location so found executing the division of -w(z) evaluated at the error location found by the formal derivative polynomial sig′(z) also evaluated at the same error location. For a treatise with a broader scope than the present disclosure, but on the readily accessible knowledge level of an engineer or student, reference is had to R.E. Blahut, the Theory and Practice of error control codes, Addison Wesley 1983, pp. 183-191. It should be noted that the algorithm embodiment of the present disclosure is applicable to narrow-sense BCH-codes, but amendments to allow for other categories of code would be straightforward. In particular, they would not change the decoding method described hereinafter in any material way. Now, the above dividing requires dividing two random-valued symbols, and could, in principle, require a similar processor structure as in block 22. The output of block 26 yields the respective error values Yi. Thus, the second division in block 26 is a complicating factor. If block 24 is also realized as a (third) processor, and blocks 22, 24, 26 are mapped on a single hardware structure in a time-multiplex organization, the resulting operating speed is low. If the Chien search is done in specific hardware, many I/O operations between the three sub-systems would be necessary, which would just as well be time-consuming. On the other hand, a speed-up may be effected by executing block 26 as a fast hardware divider. Then, however, a very large device would result (e.g. table look-up for eight-bit symbols would require a 64kx8 = 1/2 Mb ROM). The underlying problem is the essential pipelining organization among blocks 24 and 26. The latter cannot operate before the error locations have been found. The basic calculation in block 26 is represented by expression C in Figure 2. The quotient of these two evaluated polynomials cannot be written as the evaluation of a quotient polynomial, because in general the latter is not of finite degree in z. DESCRIPTION OF A PREFERRED EMBODIMENT Now, one of the measures taken by the present invention is based on the realization that the numerator of the above expression may, before the evaluations, be changed by adding (or subtracting) any other polynomial in z, provided that this other polynomial have zero value at the zeroes of the error locator polynomial. This would be valid, regardless of the contribution of this other polynomial at other locations than those zeroes. Figure 3 schematically shows the decoding according to the present invention. Various elements correspond to Figure 2 and carry identical labels. As shown, blocks 20, 24 and also the data communicated r i /r(z); S j /S(z); sig (z); Xi correspond both as to their hardware content and as to their formulation. Block 30 however uses the so-called Euclid's algorithm, which for two polynomial S(z), t(z) calculates two other accessory polynomials a(z), b(z) to yield the following expression for their greatest common divisor GCD: GCD[S(z), t(z)] = a(z)S(z) + b(z)t(z). The use thereof is described by Blahut, op cit., p. 193 ff. However, the present invention in first instance uses Euclid's algorithm for another purpose than Blahut does, to wit, in a replacement box 30 instead of box 22. Now, block 30 generates a new polynomial L(z), the Lagrange polynomial, which for each discrete i in the interval [1,t], t being the maximum error correcting capability, satisfies L(X -1 / i) = Y i , each Y i representing an error value associated to a respective error position given by X i . Now, the quantity L(z) = -w(z).c(z)mod sig(z), where b(z)sig(z)+c(z).sig′(z)=1. It should be noted that for any correctable error pattern, i.e., one that has no repeated roots, the greatest common divisor of sig(z) and sig′(z) is exactly 1, which allowed us to apply Euclid's algorithm in the first place. Reiterating, by means of Euclid's algorithm, first and second accessory polynomials b(z), c(z) are calculated; next, by means of the second accessory polynomial c(z) an intermediate polynomial L*(z) is generated as also based on the error locator polynomial sig(z), its formal derivative sig′(z), and the error locator polynomial w(z) according to L*(z) = -w(z).c(z) = -w(z) {1-b(z).sig(z)} sig′(z) Finally a Lagrange polynomial L(z) is found as the minimal degree polynomial through any error, in that for any inversed error location it has the associated error value: L(z) = L*(z)mod sig(z). Now, evaluation of the error locator polynomial sig(z) produces a set of error locations in the received word, which error locations by substitution in the above Lagrange polynomial L(z) yield an associated set of error values. The execution of all of the above operation is realized as respective straightforward implementations of the associated equations and expressions. As explained supra, a first aspect of the invention is to use Euclid's algorithm, by itself well-known, for calculating the polynomial c(z). Next, the invention may go a step further in that Euclid's algorithm also be used for solving the key equation in block 30, in lieu of using the Berlekamp/Massey algorithm of block 22. Alternately, block 30 contains both Euclid's algorithm implemented and also Berlekamp/Massey's. In neither instance retrocoupling or sequence-wise I/O between blocks 24, 30, 32 is necessary, making the set-up ideal for pipelining. The above refers to errors-only decoding, wherein the error locator polynomial would dictate the positions where the system should calculate the errors (if any). In combined error plus erasure decoding, or in erasure-only decoding, the locations are wholly or partly specified by external information, such as demodulation error flags, or other pointer-like information. This produces a modified key equation, as taught by Blahut op. cit. Block 30 should receive the relevant indicators or erasure locator polynomial. The modified key equation requires a modified algorithm, which, however, leaves the principles of the remaining operation unchanged. For brevity, the extra input to block 30 has been omitted. HARDWARE EMBODIMENT Figure 4 shows an exemplary apparatus for practicing the decoding; it should be noted that especially on the hardware level the invention allows a wide variation as to special/general purpose, embedding/non-embedding and various other realizations. The input word symbols are received on input 100; deinterleaving, demodulation are ignored for brevity. Block 104 contains the code defining information, such as, for example, the elements of the parity check matrix. Sequencer 106 controls a selection from the information in block 104 to combine this with any input symbol to calculate its contribution to the syndrome symbol string. Provisional syndrome symbols are stored in element 110. A gain under control of sequencer 106, the provisional syndrome is combined in combination element 108 with the updating contribution thereto. When the syndrome symbol string has been completed, they are transferred to storage element 112 which is signalled to a further sequencer 116. Thereupon, the next input word may be processed. The user symbols of the code word, and, if required, the parity symbols are fed to output 102 for further storage or otherwise. The above completes description of block 20 in Figure 2. Sequencer 116 now controls processor element 114 to set up and solve the key equation as based on the syndrome symbol string or its polynomial equivalent representation in storage element 112. This produces the error locator polynomial sig(z). Local RAM and, possibly, ROM storage block 118 allows for containing intermediate data and program information. The same sub-systems also allow for applying Euclid's algorithm as explained supra, either with respect to solving the key equation, or to calculate the polynomial c(z) with respect to both sig(z) and its formal derivative polynomial sig′(z). Thereupon the Lagrange polynomial L(z) is produced. Upon finalization of those polynomials sig(z), L(z), sequencer 116 signals so to blocks 24, 32, and in conjunction therewith, the two polynomials are transmitted via network 124 to the latter blocks. Of course, such transmission may be effected by means of respective point-to-point lines. The operations in blocks 24, 32 are straightforward evaluations, so no further details have been given. Further no details have been given on handshaking for synchronization purposes between the respective sub-systems. On output 120 the error location information is produced, on output 122 the error value information. If applicable a separate output may be provided for signalling an incorrectable codeword, for example, under control of an error location pointing to a non-existent code symbol of a shortened code. Further, a separate input could be provided to control the decoding, for example, in that two or more different decoding strategies are selectable. Finally, signalling information as to the reliability on a symbol level could be in/output. All of the latter refinements are standard knowledge, see for example US-A-4 683 572 (PHN 10.931) to the same assignee, and no further details have been given here. In the above solution, the error data are specifically output as symbols. Any other output system would be feasible as well, such directly using the error data for effecting a correction, outputting the error data in polynomial form, and other.

Claims: A decoding method for a non-binary BCH-code which provides wordwise protection against at least one symbol error, said method comprising the steps of: a. receiving a protected word and therefrom under control of code defining information generating a syndrome information; b. as based on said syndrome information setting up and solving a key equation for thereby generating an error locator polynomial sig(z) and an error evaluator polynomial w(z); c. by means of Euclid's algorithm and on the basis of the error locator polynomial sig(z) and its formal derivative sig′(z) calculating first and second accessory polynomials b(z), c(z) such that b(z).sig(z)+c(z).sig′(z) = 1; d. generating an intermediate polynomial L*(z) as based on the error locator polynomial, its formal derivative, the error evaluator polynomial, and the second accessory polynomial c(z) according to: L*(z) = -w(z).c(z) = -w(z) {1-b(z).sig(z)} sig′(z) e. generating a Lagrange polynomial L(z) as the minimal degree polynomial through any error occurred according to: L(z) = L*(z) mod sig(z). said Lagrange polynomial for any inversed error location value having the associated error value; f. evaluating the error locator polynomial sig(z) for producing a set of error locations in the received word for by substitution in the Lagrange polynomial generating an associated set of error values; g. outputting a set of error data, each error data represented by a location quantity and an associated error value quantity. A method as claimed in Claim 1, wherein the solving of said key equation is also executed by applying Euclid's polynomial for determining the error locator polynomial sig(z) and error evaluator polynomial w(z). A decoder apparatus for decoding a non-binary BCH code that provides wordwise protection against at least one symbol error, said apparatus comprising: a. a syndrome generator for receiving a protected word and therefrom generating under control of fixed code defining information a syndrome information equivalent to a string of at least two syndrome symbols; b. processing means fed by said syndrome generator for on the basis of said syndrome information setting up and solving a key equation for the protected word and therefrom generating an error locator polynomial sig(z) and an error evaluator polynomial w(z); c. said processing means furthermore having Euclid's algorithm means for receiving said error locator polynomial sig(z) and its formal derivative polynomial sig′(z) and therefrom calculating first and second accessory polynomials b(z), c(z) such that: b(z).sig(z)+c(z).sig′(z) = 1 as based on the fact that polynomials sig(z) and sig(z) have no commen divisor other than 1: d. said processing means furthermore having Lagrangian algorithm means for receiving said error locator polynomial sig(z) and its formal derivative polynomial sig′(z), said error evaluator polynomial w(z), and said first accessory polynomial b(z) for on the basis thereof calculating an intermediate polynomial L*(z) given by L*(z) = -w(z).c(z) = -w(z) {1-b(z).sig(z)} sig′(z) and a Lagrangian polynomial L(z) given by L(z) = L*(z) mod sig(z), said Lagrangian polynomial L(z) for any inversed error location having the associated error value; e. first evaluation means fed by said processing means for receiving and evaluating the error locator polynomial sig(z) for generating an error location set for the word in question; f. second evaluation means fed in functional paralellism with the first evaluation means by said processing means for receiving the Lagrangian polynomial L(z) for generating for each error location in such error location set an associated error value; g. output means fed by said first and second evaluation means for outputting said error location set and any associated error value for further use. A decoder apparatus as claimed in Claim 3, wherein said Euclid's algorithm means is also effective for solving the key equation for therefrom determining the error locator polynomial sig(z) and error evaluator polynomial w(z).

Inventors: BAGGEN CONSTANT PAUL MARIE JOZ, VRIES LODEWIJK BAREND, BAGGEN, CONSTANT PAUL MARIE JOZEF, VRIES, LODEWIJK BAREND
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1989
Main classification: H03M13
IPC codes: H03M13