Balanced integrator-filter arrangement

Abstract: The invention relates to an active RC filter arrangement comprising a balanced amplifier (A₁) which can be extended to obtain an n th -order filter arrangement. Once a general n th -order filter arrangement has been created it can be modified to obtain, inter alia , a low-pass, a high-pass or an all-pass n th -order active RC filter by merely changing the values of the resistors and capacitors.

Description: The invention relates to a filter arrangement comprising a first balanced amplifier having a non-inverting and an inverting input and having a non-inverting and an inverting output, a first and a second input terminal, a first and a second output terminal, a first and a second feedback circuit, each comprising a first capacitor, the first feedback circuit being arranged between the inverting output and the non-inverting input of the first amplifier, and the second feedback circuit being arranged between the non-inverting output and the inverting input of the first amplifier, a first and a second input circuit, each comprising the parallel arrangement of a first resistor and a second capacitor, the first input circuit being arranged between the first input terminal and the non-inverting input of the first amplifier and the second input circuit being arranged between the second input terminal and the inverting input of the first amplifier, a connection between the inverting output of the first amplifier and the second output terminal and a connection between the non-inverting output of the first amplifier and the first output terminal. Such a filter arrangement is very suitable for realising active RC filters comprising balanced amplifiers. Active RC filters comprising balanced amplifier are known from United States Patent Specification US 4,509,019. Said specification describes the basic principle of an active RC filter comprising a balanced amplifier. Moreover, said specification reveals some filter types based on said principle including a first-order low-pass filter (Fig. 3). There are several known methods of designing a filter having specific desired characteristics. A frequently employed method is that in which lower-order filter sections are cascaded. It is common practice to employ first-order and second-order sections for this purpose. Sections orders higher than four are hardly ever used because such sections are difficult to realise. A filter arrangement of a type as defined in the opening paragraph is known from the article "New Structures for MOSFET-C Filters", Proceedings of the IEEE, Vol. 75, No. 7, July 1987, page 957. This article describes how difficult it may be to translate known filter designs into versions comprising balanced amplifiers. Said article proposes three different second-order filter sections comprising balanced amplifiers. A disadvantage of these known filter circuits is that only second-order filters are mentioned and that neither of the filters is suitable for realising all the filter operations which are customary and possible for said order without throughly modifying the circuit configuration, i.e. without changing the interconnections between the filter elements and, sometimes, the positions of the inputs and outputs of the network. For this reason the systematic design of active RC filters comprising balanced amplifiers is a difficult task. Therefore, it is the object of the invention to provide filter circuits by means of which first-order and higher-order active RC filters can be realised simply. According to the invention a filter arrangement of a type defined in the opening paragraph is characterized in that the filter arrangement also comprises a third and a fourth input circuit, each comprising a third capacitor, the third input circuit being arranged between the first input terminal and the inverting input of the first amplifier, and the fourth input circuit being arranged between the second input terminal and the non-inverting input of the first amplifier. This filter arrangement constitutes the elementary configuration which serves as a basis for realising first-order and higher-order filter arrangements, enabling active RC filters of a specific order for substantially every possible filter function to be realised by merely changing the values of resistors and capacitors. A first embodiment of a filter arrangement in accordance with the invention is characterized in that the filter arrangement further comprises a first and a second coupling circuit, each comprising a second resistor, the first coupling circuit being arranged between the non-inverting input of the first amplifier and the inverting output of the first amplifier, and the second coupling circuit being arranged between the inverting input of the first amplifier and the non-inverting output of the first amplifier. The addition of two network elements yielding a general first-order filter arrangement. Filter arrangements having special characteristics are obtained by an appropriate choice of the values of the filter elements. A further embodiment is characterized in that the capacitance values of the third capacitors in the third and the fourth input circuit and the first capacitors in the first and the second feedback circuit are substantially equal, and in that the conductance values of the first resistors in the first and second input circuit and the second resistors in the first and second coupling circuit are substantially equal. This yields a first-order all-pass network. IEEE Transactions on Circuits and Systems, CAS-34, No. 8, August 1987, "Analysis and compensation of high-frequency effects in integrated MOSFET-C continuous-time filters", pp. 862-875 discloses in its Figs. 1 and 4 a filter arrangement as set out in Claim 1 in which the second capacitor is not included. 1985 International Symposium on Circuits and Systems Proceedings, 5-17 June 1985 Kyoto, Vol. 3, "Considerations in the design of high frequency fully integrated continuous time filters", pp. 1439-1442, also shows in its Fig. 1 a filter arrangement as set out in Claim 1 without the second capacitor. By extending the elementary configuration a second embodiment of a filter arrangement in accordance with the invention is obtained, which is characterized in that the filter arrangement further comprises a second balanced amplifier having a non-inverting and an inverting input and having a non-inverting and an inverting output, a fifth and a sixth input circuit, each comprising a fourth capacitor, the fifth input circuit being arranged between the first input terminal and the non-inverting input of the second amplifier, and the sixth input circuit being arranged between the second input terminal and the inverting input of the second amplifier, a seventh and an eighth input circuit, each comprising a third resistor, the seventh input circuit being arranged between the non-inverting output of the first amplifier and the non-inverting input of the second amplifier, and the eighth input circuit being arranged between the inverting output of the first amplifier and the inverting input of the second amplifier, a third and a fourth feedback circuit, each comprising a fifth capacitor, the third feedback circuit being arranged between the inverting output and the non-inverting input of the second amplifier, and the fourth feedback circuit being arranged between the non-inverting output and the inverting input of the second amplifier, a first and a second coupling circuit, each comprising a second resistor, the first coupling circuit being arranged between the non-inverting input of the first amplifier and a first node, and the second coupling circuit being arranged between the inverting input of the first amplifier and a second node, a third and a fourth coupling circuit, each comprising a fourth resistor, the third coupling circuit being arranged between the first node and the non-inverting input of the second amplifier, and the fourth coupling circuit being arranged between the second node and the inverting input of the second amplifier. A modification thereof constitutes a general second-order filter arrangement which, in accordance with the invention is characterized in that the first node and the inverting output of the second amplifier and a fourth output terminal are interconnected, and in that the second node and the non-inverting output of the second amplifier and a third output terminal are interconnected. Special embodiments of the second-order filter arrangement are obtained by varying the values of the resistors and the capacitors. An embodiment having the characteristics of an all-pass network is characterized in that the capacitance values of the second capacitors in the first and second input circuit are substantially equal zero, in that the conductance values of the first resistors in the first and the second input circuit and of the second resistor in the first and the second coupling circuit are substantially equal, in that the conductance values of the third resistors in the seventh and the eighth input circuit and of the fourth resistors in the third and the fourth coupling circuit are substantially equal, in that the capacitance values of the third capacitors in the third and the fourth input circuit and of the first capacitors in the first and the second feedback circuit are substantially equal, and in that the capacitance values of the fourth capacitors in the fifth and the sixth input circuit and of the fifth capacitors in the third and the fourth feedback circuit are substantially equal. A further extension of the elementary configuration yields a third embodiment of a filter arrangement in accordance with the invention which is characterized in that the filter arrangement further comprises a third balanced amplifier having a non-inverting and an inverting input and having a non-inverting and an inverting output, a fifth and a sixth output terminal, a ninth and a tenth input circuit, each comprising a sixth capacitor, the ninth input circuit being arranged between the first input terminal and the non-inverting input of the third amplifier, and the tenth input circuit being arranged between the second input terminal and the inverting input of the third amplifier, an eleventh and a twelfth input circuit, each comprising a seventh capacitor, the eleventh input circuit being arranged between the first input terminal and the inverting input of the third amplifier, and the twelfth input circuit being arranged between the second input terminal and the non-inverting input of the third amplifier, a thirteenth and a fourteenth input circuit, each comprising a fifth resistor, the thirteenth input circuit being arranged between the inverting output of the second amplifier and the inverting input of the third amplifier, and the fourteenth input circuit being arranged between the non-inverting output of the second amplifier and the non-inverting input of the third amplifier, a fifth and a sixth coupling circuit, each comprising a sixth resistor, the fifth coupling circuit being arranged between the first node and the non-inverting input of the third amplifier, and the sixth coupling circuit being arranged between the second node and the inverting input of the third amplifier, a fifth and a sixth feedback circuit, each comprising an eighth capacitor, the fifth feedback circuit being arranged between the non-inverting input and the inverting output of the third amplifier, and the sixth feedback circuit being arranged between the inverting input and the non-inverting output of the third amplifier, and in that the inverting output of the third amplifier is connected to the sixth output terminal and the non-inverting output of the third amplifier is connected to the fifth output terminal. A further embodiment constitutes a general third-order filter arrangement, characterized in that the first node is connected to the inverting output of the third amplifier and the second node is connected to the non-inverting output of the third amplifier. Special filter arrangements can be obtained by varying the values of the resistors and capacitors. An all-pass network is obtained if the conductance values of the first resistors in the first and the second input circuit and of the second resistors in the first and the second coupling circuit are substantially equal, in that the conductance values of the third resistors in the seventh and the eighth input circuit and of the fourth resistors in the third and the fourth coupling circuit are substantially equal, in that the conductance values of the fifth resistors in the thirteenth and the fourteenth input circuit and the sixth resistors in the fifth and of the sixth coupling circuit are substantially equal, in that the capacitance balues of the second capacitors in the first and the second input circuit and of the sixth capacitors in the ninth and the tenth input circuit are substantially zero, in that the capacitance values of the third capacitors in the third and the fourth input circuit and of the first capacitors in the first and the second feedback circuit are substantially equal, in that the capacitance values of the fourth capacitors in the fifth and the sixth input circuit and of the fifth capacitors in the third and the fourth feedback circuit are substantially equal, and in that the capacitance values of the seventh capacitors in the eleventh and the twelfth input circuit and of the eighth capacitors in the fifth and in the sixth feedback circuit are substantially equal. Yet another extension of the elementary configuration results in a fourth embodiment of a filter arrangement in accordance with the invention, which is characterized in that the filter arrangement further comprises a fourth balanced amplifier having a non-inverting input and an inverting input and having a non-inverting output and an inverting output, a seventh and an eighth output terminal, a fifteenth and a sixteenth input circuit, each comprising a ninth capacitor, the fifteenth input circuit being arranged between the first input terminal and the non-inverting input of the fourth amplifier and the sixteenth input circuit being arranged between the second input terminal and the inverting input of the fourth amplifier, a seventeenth and an eighteenth input circuit, each comprising a seventh resistor, the seventeenth input circuit being arranged between the non-inverting output of the third amplifier and the non-inverting input of the fourth amplifier, and the eighteenth input circuit being arranged between the inverting output of the third amplifier and the inverting input of the fourth amplifier, a seventh and an eighth feedback circuit, each comprising a tenth capacitor, the seventh feedback circuit being arranged between the non-inverting input and the inverting output of the fourth amplifier, and the eighth feedback circuit being arranged between the inverting input and the non-inverting output of the fourth amplifier, a ninth and a tenth feedback circuit, each comprising an eighth resistor, the ninth feedback circuit being arranged between the non-inverting input and the inverting output of the fourth amplifier, and the tenth feedback circuit being arranged between the inverting input and the non-inverting output of the fourth amplifier, and in that the inverting output of the fourth amplifier is connected to the eighth output terminal and the non-inverting output of the fourth amplifier is connected to the seventh output terminal. This is a general fourth-order filter arrangement which enables filters having special characteristics to be obtained by varying the values of the resistors and the capacitors. An all-pass network is obtained in that the conductance values of the first resistors in the first and the second input circuit and of the second resistors in the first and the second coupling circuit are substantially equal, in that the conductance values of the third resistors in the seventh and the eighth input circuit and of the fourth resistors in the third and the fourth coupling circuit are substantially equal, in that the conductance values of the fifth resistors in the thirteenth and the fourteenth input circuit and of the sixth resistors in the fifth and the sixth coupling circuit are substantially equal, in that the conductance values of the seventh resistors in the seventeenth and the eighteenth input circuit and of the eighth resistors in the ninth and the tenth feedback circuit are substantially equal, in that the capacitance values of the third capacitors in the third and the fourth input circuit and the of first capacitors in the first and the second feedback circuit are substantially equal, in that the capacitance values of the fourth capacitors in the fifth and the sixth input circuit and of the fifth capacitors in the third and the fourth feedback circuit are substantially equal, in that the capacitance values of the seventh capacitors in the eleventh and the twelfth input circuit and of the eighth capacitors in the fifth and the sixth feedback circuit are substantially equal, in that the capacitance values of the ninth capacitors in the fifteenth and the sixteenth input circuit and the of tenth capacitors in the seventh and the eighth feedback circuit are substantially equal, and in that the capacitance values of the second capacitors in the first and the second input circuit and the of sixth capacitors in the ninth and the tenth input circuit are substantially zero. The invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which: Fig. 1 shows a diagram of a first-order elementary configuration in accordance with the invention, Fig. 2 shows a diagram of a general first-order filter arrangement in accordance with the invention, Fig. 3 shows a diagram of a first-order all-pass filter arrangement in accordance with the invention, Fig. 4 shows a diagram of a first-order high-pass filter arrangement, Fig. 5 shows a diagram of a second-order elementary configuration in accordance with the invention, Fig. 6 shows a diagram of a general second-order filter arrangement in accordance with the invention, Fig. 7 shows a diagram of a second-order low-pass filter arrangement, Fig. 8 shows a diagram of a second-order high-pass filter arrangement in, Fig. 9 shows a diagram of a second-order filter arrangement having a transmission zero point, Fig. 10 shows a diagram of a second-order all-pass filter arrangement in accordance with the invention, Fig. 11 shows a diagram of a second-order band-pass filter arrangement, Fig. 12 shows a diagram of a third-order elementary configuration in accordance with the invention, Fig. 13 shows a diagram of a general third-order filter arrangement in accordance with the invention, Fig. 14 shows a diagram of a third-order low-pass filter arrangement, Fig. 15 shows a diagram of a third-order high-pass filter arrangement, Fig. 16 shows a diagram of a third-order filter arrangement having a transmission zero point, Fig. 17 shows a diagram of a third-order all-pass filter arrangement in accordance with the invention, Fig. 18 shows a diagram of a general fourth-order filter arrangement in accordance with the invention, Fig. 19 shows a diagram of a fourth-order low-pass filter arrangement, Fig. 20 shows a diagram of a fourth-order high-pass filter arrangement Fig. 21 shows a diagram of a fourth-order all-pass filter arrangement in accordance with the invention. Hereinafter some examples of filter arrangements in accordance with the invention are described. Examples of first-order to fourth-order filter arrangements are given, in which an appropriate selection of the component values results in useful filters. Fig. 1 shows diagrammatically the elementary configuration around which all the filter arrangements are built. It comprises a balanced amplifier A₁ having a non-inverting input 3 and an inverting input 4, an inverting output 5 and an non-inverting output 6. The filter arrangement has two input terminals 1 and 2 and two output terminals 7 and 8. The amplifier A₁ comprises a feedback capacitor C₁ between the inverting output 5 and the non-inverting input 6 and between the non-inverting output 6 and the inverting input 4. A parallel arrangement of a resistor R₁ and a capacitor C₂ is arranged between the input terminal 1 and the non-inverting input 3 and between the input terminal 2 and the inverting input 4. A capacitor C₃ is arranged between the input terminal 1 and the inverting input 4 and the between the input terminal 2 and the non-inverting input 3. The inverting output 5 is connected to the output 8 and the non-inverting output 6 is connected to the output 7. This crosswise connection ensures that the output signals have the same polarities as the input signals applied to the filter arrangement. The circuit is fully symmetrical and is driven by two balanced input signals of opposite polarity. Fig. 2 shows the general first-order filter arrangement. It is obtained in that in the arrangement shown in Fig. 1 two resistors R₂ are added between the inverting output 5 and the non-inverting input 3 and between the non-inverting output 6 and the inverting input 4. The filter arrangement operates as follows. An input voltage +V₁ is applied to the input terminal 1 and an equal but opposite input voltage -V₁ is applied to the input terminal 2. An output voltage +V₂ is obtained on the output terminal 7 and an equal but opposite output voltage -V₂ is obtained on the output terminal 8. The voltage transfer function can be computed by solving the nodal equation for the currents in the node N₁. N₁ corresponds to the non-inverting input 3 of the amplifier A₁, which amplifier is assumed not to draw any input current. In that case the following equation is valid: G₁*V₁+p*(C₂-C₃)*V₁ = G₂*V₂+p*C₁*V₂ V₂ V₁ = G₁+p*(C₂-C₃) G₂+p*C₁ where G i is the conductance value of the resistor R i in conformity with 1 R i = G i and where p is the complex frequency p=jω. Formula (2) is the complex transfer function of the filter arrangement expressed as a polynomial of p. The highest power of p dictates the order of the filter network. The network shown in Fig. 2 is consequently of the first-order. Varying the values of the filter components yields filter arrangements having special characteristics. Some examples of such arrangements will be given hereinafter. Fig. 3 shows a first-order all-pass filter arrangement. It is obtained by selecting C₂=0, G₁=G₂=G and C₃=C₁=C in the general first-order filter arrangement shown in Fig. 2. The voltage transfer function then becomes V₂ V₁ = G-pC G+pC Such a transfer function is characterized by a frequency-independent amplitude response. Fig. 4 shows a second example. It is a first-order high-pass filter arrangement obtained by making G₁=0 and C₃=0 in the general first-order filter arrangement shown in Fig. 2. The transfer function is then V₂ V₁ = p*C₂ G₂+pC₁ Further it is to be noted that a first-order low-pass filter arrangement can be obtained by making C₂=0 and C₃=0 in the general filter arrangement shown in Fig. 2. Extending the elementary configurations hown in Fig. 1 yields a filter arrangement which may be regarded as the elementary configuration for for second-order filter arrangements shown diagrammatically in Fig. 5. It is obtained by adding the following components to the arrangement shown in Fig. 1: a second balanced amplifier A₂ having a non-inverting input 11, an inverting input 12, an inverting output 13 and a non-inverting output 14; a resistor R₂ between the node 9 and the non-inverting input 3 of the first amplifier A₁ and between the node 10 and the inverting input of the amplifier A₁; a resistor R₄ between the non-inverting input 11 of the amplifier A₂ and the node 9, and between the inverting input 12 of the amplifier A₂ and the node 10; a resistor R₃ between the non-inverting output 6 of the amplifier A₁ and the non-inverting input 11 of the amplifier A₂ and between the inverting output 5 of A₁ and the inverting input 12 of the amplifier A₂; a capacitor C₄ between the input terminal 1 and the non-inverting input 11 of the amplifier A₂ and between the input terminal 2 and the inverting input 12 of the amplifier A₂; a capacitor C₅ between the non-inverting input 11 and the inverting output 13 of the amplifier A₂ and between the inverting input 12 and the non-inverting output 14 of the amplifier A₂. A general second-order filter arrangement is shown in Fig. 6 and is obtained by providing in the arrangement shown in Fig. 5 a connection between the node 9 and the inverting output 13 of the amplifier A₂ and between the node 10 and the non-inverting output 14 of the amplifier A₂. In addition, the inverting output 13 of the amplifier A₂ is connected to the output terminal 16 and the non-inverting output 14 of the amplifier A₂ is connected to the output terminal 15. This cross connection at the output of the arrangement ensures that the output signals have the same polarities as the input signals. An input voltage +V₁ is applied to the input terminal 1 and an input voltage -V₁ is applied to the input terminal 2. A voltage -V₂ is obtained on the inverting output 5 of the amplifier A₁ and a voltage +V₂ is obtained on the non-inverting output 6 of the amplifier A₂. A voltage +V₃ is obtained on the output terminal 15 of the filter arrangement and a voltage -V₃ appears on the output terminal 15. The plus and minus signs preceding the signal voltages indicate that the signal voltages are of equal amplitude but opposite polarity. In order to calculate the voltage transfer function it is assumed that the balanced amplifiers A₁ and A₂ draw no input current. Moreover, a second node N₂ is introduced, which corresponds to the non-inverting input 11 of the amplifier A₂. The node N₁ complies with: G₁*V₁+p*(C₂-C₃)*V₁ = G₂*V₃+p*C₁*V₂ and the node N₂ complies with: G₃*V₂+p*C₄*V₁ = G₄*V₃+p*C₅*V₃ V₂ can be eliminated from the set of equations by multiplying the terms of equation (5) by G₃ and those of equation(6) by p*C₁ and subsequently adding (5) and (6) to one another, which operations may be represented by the following diagrammatic notation From the result the voltage transfer function can be computed: V₃ V₁ = G₁*G₃+p*(C₂-C₃)*G₃+p*p*C₁*C₄ G₂*G₃+p*C₁*G₄ +p*p*C₁*C₅ This is a second-order transfer function. By an appropriate choice of the values of the filter components special second-order filter arrangements are obtained, of which a number of examples will be described hereinafter. A second-order low-pass filter arrangement is obtained by selecting C₂=C₃=C₄=0 in (8). The voltage transfer function then becomes: V₃ V₁ = G₁*G₃ G₂*G₃+p*C₁*G₄ +p*p*C₁*C₅ The diagram of the low-pass filter is shown in Fig. 7. A second-order high-pass filter arrangement is obtained by selecting G₁ = 0 and C₃ = 0 in (8). The voltage transfer function then becomes: V₃ V₁ = p*C₂*G₃ +p*p*C₁*C₄ G₂*G₃+p*C₁*G₄ +p*p*C₁*C₅ and the diagram of the high-pass filter is shown in Fig. 8. A second-order filter arrangement with which the frequency can be rejected, also referred to as a band-rejection filter or notch filter, is obtained by selecting C₂=C₃=0 in (8). The voltage transfer function is then: V₃ V₁ = G₁*G₃ +p*p*C₁*C₄ G₂*G₃+p*C₁*G₄ +p*p*C₁*C₅ and the diagram is given in Fig. 9. A further example relates to a filter arrangement which behaves as a second-order all-pass filter. By selecting G₂=G₁, G₄=G₃, C₂=0, C₁=C₃ and C₅=C₄ in (8), the voltage transfer function becomes: V₃ V₁ = G₁*G₃ - p*C₃*G₃ + p*p*C₃*C₄ G₂*G₃ + p*C₃*G₃ + p*p*C₃*C₄ The diagram of the all-pass filter is shown in Fig. 10. The last example of a special second-order filter arrangement is a second-order band-pass arrangement shown in Fig. 11. It is obtained by selecting by G₁=0 and C₃=C₄=0 in (8). The voltage transfer function then becomes: V₃ V₁ = p*C₂*G₃ G₂*G₃+p*C₁*G₄+p*p*C₁*C₅ The elementary configuration for second-order filter arrangement of Fig. 5 can be extended to obtain a third-order elementary configuration whose diagram is shown in Fig. 12. It is obtained by adding the following components to the arrangement of Fig. 5: a balanced amplifier A₃ having a non-inverting input 17 and an inverting input 18 and having an inverting output 19 and a non-inverting output 20; a capacitor C₆ between the input terminal 1 and the non-inverting input 17 and between the input terminal 2 and the inverting input 18; a capacitor C₇ between the input terminal 1 and the inverting input 18 and between the input terminal 2 and the non-inverting input 17; a resistor R₅ between the inverting output 13 and the inverting input 18 and between the non-inverting output 14 and the non-inverting input 17; a capacitor C₈ between the non-inverting input 17 and the inverting output 19 and between the inverting input 18 and the non-inverting output 20; a resistor R₆ between the node 9 and the non-inverting input 17 and between the node 10 and the inverting input 18. Further, the inverting output 19 is connected to the output terminal 22 and the non-inverting output 22 is connected to the output terminal 21. A general third-order filter arrangement is shown in Fig. 13 and is formed by arranging a connection between the node 9 and the inverting output 19 and between the node 10 and the non-inverting input 20 in the arrangement shown in Fig. 12. An input voltage +V₁ is applied to the input terminal 2 and an input voltage -V₁ is applied to the input terminal 2. The output voltage on the inverting output 5 of the amplifier A₁ is -V₂, that on the non-inverting output 6 of the amplifier A₁ is +V₂, that on the inverting output 13 of the amplifier A₂ is -V₃, that on the non-inverting output 14 of the amplifier A₂ is +V₃, that on the output terminal 21 is +V₄, and that on the output terminal 22 is -V₄. Moreover, a third node N₃ is shown which node corresponds to the non-inverting input 17 of the amplifier A₃. The node N₁ complies with: G₁*V₁+p*(C₂-C₃)*V₁=G₂*V₄+p*C₁*V₂ The node N₂ complies with: G₃*V₂+p*C₄*V₁=G₄*V₄+p*C₅*V₃ and the node N₃ complies with: G₅*V₃+p*(C₆-C₇)*V₁=G₆*V₄+p*C₈*V₄ In these three equations V₂ and V₃ can be eliminated as follows: which yields the following voltage transfer function: V4 V1 = G1*G3*G5+p*(C2-C3)*G3*G5+p*p*C1*C4*G5+p*p*p*C1*C5*(C6-C7) G2*G3*G5+p*C1*G4*G5 +p*p*C1*C5*G6+p*p*p*C1*C5*C8 Filters having special characteristics can be obtained by an appropriate choice of the values of the filter elements in the general third-order filter arrangement of Fig. 13. A first example is a third-order low-pass filter, of which the diagram is shown in Fig. 14. This is achieved by selecting C₂=C₃=C₅=C₆=C₇=0 in (18). The transfer function then becomes: V4 V1 = G1*G3*G5 G2*G3*G5+p*C1*G4*G5+p*p*C1*C5*G6+p*p*p*C1*C5*C8 A second example is a third-order high-pass filter arrangement, shown in Fig. 15, which is obtained by selecting G₁=0 and C₃=C₇=0 in (18). The transfer function is then: V4 V1 = p*C2*G3*G5+p*p*C1*C4*G5+p*p*p*C1*C5*C6 G2*G3*G5+p*C1*G4*G5+p*p*C1*C5*G6+p*p*p*C1*C5*C8 A third example is a third-order band-rejection filter, whose diagram is shown in Fig.16. By selecting G₅=G₁, C₃=C₇=0 and C₂*C₄=C₅*C₆ in (18) the voltage transfer function becomes: (G1*G3+p*p*C1*C4) * (G1+p*C2/G1) G2*G3*G1+p*C1*G4*G1+p*p*C1*C5*G6+p*p*p*C1*C5*C8 The numerator of (21) now includes a term equal to the numerator of the voltage transfer function (11) of a second-order band-rejection filter. Fig. 17 shows a fourth example. It is a third-order all-pass filter arrangement obtained by selecting G₂=G₁, G₄=G₃, G₆=G₅, C₂=C₆=0, C₃=C₁, C₅=C₄ and C₈=C₇ in formula (18). The voltage transfer function is then: V4 V1 = G1*G3*G5 - p*C1*G3*G5+p*p*C1*C4*G5 - p*p*p*C1*C4*C7 G1*G3*G5 + p*C1*G3*G5+p*p*C1*C4*G5 + p*p*p*C1*C4*C7 The third-order elementary configuration of Fig. 12 can be extended to obtain a general fourth-order arrangement, whose diagram is shown in Fig. 18, by adding the following components to the arrangement shown in Fig. 12: a balanced amplifier A₄ having a non-inverting input 23 and an inverting input 24 and having an inverting output 25 and a non-inverting output 26; a capacitor C₉ between the first input terminal 1 and the non-inverting input 23 and between the input terminal 2 and the inverting input 24, a resistor R₇ between the inverting output 19 and the inverting input 24 and between the non-inverting output 20 and the non-inverting input 23; the parallel arrangement of a resistor R₈ and a capacitor C₁₀ between the non-inverting input 23 and the inverting output 25 and between the inverting input 24 and the non-inverting output 26. Moreover, a connection is arranged between a first output terminal 27 and the non-inverting output 26 and between the second output terminal 28 and the inverting output 25. It is to be noted that the arrangement shown in Fig. 18 is not identical to a fourth-order elementary configuration corresponding to the third-order elemenatary configuration of Fig. 12, the second-order elementary configuration of Fig. 5 and the first-order elementary configuration of Fig. 1, but is a general fourth-order filter arrangement corresponding to the general third-order filter arrangement shown in Fig. 13, the general second-order filter arrangement of Fig. 16, and the general first-order filter arrangement of Fig. 2. Extension to fifth-order and higher-order elementary configurations and fifth-order and higher-order general filter arrangement derived therefrom is readily possible by proceeding with the extensions in a manner as specified in the foregoing. An input voltage +V₁ is applied to the input terminal 1 and an input voltage -V₁ is applied to an input terminal 2. The output voltage on the inverting output 5 of the amplifier A₁ is -V₂, that on the non-inverting output 6 of the amplifier A₁ is +V₂, that on the inverting output 13 of the amplifier A₂ is -V₃, that on the non-inverting output 14 of the amplifier A₂ is +V₃, that on the inverting output 19 of the amplifier A₃ is -V₄, that on the non-inverting output 20 of the amplifier A₃ is +V₄, that on the output terminal 27 is +V₅, and that on the output terminal 28 is -V₅. Moreover, a fourth node N₄ is shown, which node corresponds to the non-inverting input 23 of the amplifier A₄. The voltage transfer function is computed by calculating the currents in the four nodes N₁ ...N₄. It is assumed that the amplifiers A₁ ... A₄ draw no input current. The node N₁ complies with: G₁*V₁+p*(C₂-C₃)*V₁=G₂*V₅+p*C₁*V₂ N₂ complies with: G₃*V₂+p*C₄*V₁=G₄*V₅+p*C₅*V₃ N₃ complies with: G₅*V₃+p*(C₆-C₇)*V₁=G₆*V₅+p*C₈*V₄ and N₄ complies with: G₇*V₄+p*C₉*V₁ = G₈*V₅+p*C₁₀*V₅ In this set of equations V₂, V₃ and V₄ can be eliminated by: This yields the following voltage transfer function: By selecting suitable values for the filter components in (28) special arrangements can be derived from the general fourth-order filter arrangement of Fig. 18, of which a number of examples will be given hereinafter. A fourth-order low-pass filter arrangement is obtained by selecting C₂=C₃=C₄=C₆=C₇=C₉=0 in (28). The voltage transfer function is then: The diagram is shown in Fig. 19. Fig. 20 shows a fourth-order high-pass filter arrangement obtained by selecting G₁=0 and C₃=C₇=0 in (28). The voltage transfer function is then: Fig. 21 shows a fourth-order all-pass filter arrangement. It is obtained by the following selection of components in formula (28): G₂=G₁, G₄=G₃, G₆=G₅ and G₈=G₇; C₂=C₆=0; C₃=C₁, C₅=C₄, C₈=C₇ and C₁₀=C₉. The voltage transfer function may then be written as follows: The invention is not limited to the embodiments shown herein. The general and special first-order and higher-order filter arrangements shown herein may be arranged in series, as required, in order to create other filter arrangements having different characteristics. For this reason some filter arrangements are provided with cross connections at their output sides in order to preclude changes in polarity when these filter arrangements are connected in series. As will be apparent from the description, the invention is by no means limited to a specific integration process technology, such as for example MOS technology. As already stated in the foregoing, the invention is not limited to fourth-order filter arrangements. Proceeding from the method as proposed by the invention those skilled in the art will be able to design any desired higher-order filter arrangement.

Claims: A filter arrangement comprising a first balanced amplifier (A₁) having a non-inverting (3) and an inverting input (4) and having a non-inverting (6) and an inverting output (5), a first (1) and a second (2) input terminal, a first (7) and a second (8) output terminal, a first and a second feedback circuit, each comprising a first capacitor (C₁), the first feedback circuit being arranged between the inverting output (5) and the non-inverting input (3) of the first amplifier (A₁), and the second feedback circuit being arranged between the non-inverting output (6) and the inverting input (4) of the first amplifier (A₁), a first and a second input circuit, each comprising the parallel arrangement of a first resistor (R₁) and a second capacitor (C₂), the first input circuit being arranged between the first input terminal (1) and the non-inverting input (3) of the first amplifier (A₁) and the second input circuit being arranged between the second input terminal (2) and the inverting input (4) of the first amplifier (A₁), a connection between the inverting output (5) of the first amplifier (A₁) and the second output terminal (8) and a connection between the non-inverting output (6) of the first amplifier (A₁) and the first output terminal (7), characterized in that the filter arrangement also comprises a third and a fourth input circuit, each comprising a third capacitor (C₃), the third input circuit being arranged between the first input terminal (1) and the inverting input (4) of the first amplifier (A₁), and the fourth input circuit being arranged between the second input terminal (2) and the non-inverting input (3) of the first amplifier (A₁). A filter arrangement as claimed in Claim 1, characterized in that the filter arrangement further comprises a first and a second coupling circuit, each comprising a second resistor (R₂), the first coupling circuit being arranged between the non-inverting input (3) of the first amplifier (A₁) and the inverting output (5) of the first amplifier (A₁), and the second coupling circuit being arranged between the inverting input (4) of the first amplifier (A₁) and the non-inverting output (6) of the first amplifier (A₁). A filter arrangement as claimed in Claim 2, characterized in that the capacitance values of the second capacitors (C₂) in the first and the second input circuit are substantially zero, in that the capacitance values of the third capacitors (C₃) in the third and the fourth input circuit and the first capacitors (C₁) in the first and the second feedback circuit are substantially equal, and in that the conductance values of the first resistors (R₁) in the first and second input circuit and the second resistors (R₂) in the first and the second coupling circuits are substantially equal. A filter arrangement as claimed in Claim 1, characterized in that the filter arrangement further comprises a second balanced amplifier (A₂) having a non-inverting (11) and an inverting input (12) and having a non-inverting (14) and an inverting output (13), a fifth and a sixth input circuit, each comprising a fourth capacitor (C₄), the fifth input circuit being arranged between the first input terminal (1) and the non-inverting input (11) of the second amplifier (A₂) and the sixth input circuit being arranged between the second input terminal (2) and the inverting input (12) of the second amplifier (A₂), a seventh and an eighth input circuit, each comprising a third resistor (R₃), the seventh input circuit being arranged between the non-inverting output (6) of the first amplifier (A₁) and the non-inverting input (11) of the second amplifier (A₂), and the eighth input circuit being arranged between the inverting output (5) of the first amplifier (A₁) and the inverting input (12) of the second amplifier (A₂), a third and a fourth feedback circuit, each comprising a fifth capacitor (C₅), the third feedback circuit being arranged between the inverting output (13) and the non-inverting input (11) of the second amplifier (A₂) and the fourth feedback circuit being arranged between the non-inverting output (14) and the inverting input (12) of the second amplifier (A₂), a first and second coupling circuit, each comprising a second resistor (R₂), the first coupling circuit being arranged between the non-inverting input (3) of the first amplifier (A₁) and a first node (9), and the second coupling circuit being arranged between the inverting input (4) of the first amplifier (A₁) and a second node (10), a third and a fourth coupling circuit, each comprising a fourth resistor (R₄), the third coupling circuit being arranged between the first node (9) and the non-inverting input (11) of the second amplifier (A₂), and the fourth coupling circuit being arranged between the second node (10) and the inverting input (12) of the second amplifier (A₂). A filter arrangement as claimed in Claim 4, characterized in that the first node (9) and the inverting output (13) of the second amplifier and a fourth output terminal (16) are interconnected, and in that the second node (10) and the non-inverting output (14) of the second amplifier (A₂) and a third output terminal (15) are interconnected. A filter arrangement as claimed in Claim 5, characterized in that the capacitance values of the second capacitors (C₂) in the first and the second input circuit are substantially zero, in that the conductance values of the first resistors (R₁) in the first and second input circuit and of the second resistors (R₂) in the first and the second coupling circuit are substantially equal, in that the conductance values of the third resistors (R₃) in the seventh and the eighth input circuit and of the fourth resistors (R₄) in the third and the fourth coupling circuit are substantially equal, in that the capacitance value of the third capacitors (C₃) in the third and the fourth input circuit and of the first capacitors (C₁) in the first and the second feedback circuit are substantially equal, and in that the capacitance values of the fourth capacitors (C₄) in the fifth and the sixth input circuit and of the fifth capacitors (C₅) in the third and the fourth feedback circuit are substantially equal. A filter arrangement as claimed in Claim 4, characterized in that the filter arrangement further comprises a third balanced amplifier (A₃) having a non-inverting (17) and an inverting (18) input and having a non-inverting (20) and an inverting (19) output, a fifth (21) and a sixth (22) output terminal, a ninth and a tenth input circuit, each comprising a sixth capacitor (C₆), the ninth input circuit being arranged between the first input terminal (1) and the non-inverting input (17) of the third amplifier (A₃), and the tenth input circuit being arranged between the second input terminal (2) and the inverting input (18) of the third amplifier (A₃), an eleventh and a twelfth input circuit, each comprising a seventh capacitor (C₇), the eleventh input circuit being arranged between the first input terminal (1) and the inverting input (18) of the third amplifier (A₃), and the twelfth input circuit being arranged between the second input terminal (2) and the non-inverting input (17) of the third amplifier (A₃), a thirteenth and a fourteenth input circuit, each comprising a fifth resistor (R₅), the thirteenth input circuit being arranged between the inverting output (13) of the second amplifier (A₂) and the inverting input (18) of the third amplifier (A₃), and the fourteenth input circuit being arranged between the non-inverting output (14) of the second amplifier (A₂) and the non-inverting input (17) of the third amplifier (A₃), a fifth and a sixth coupling circuit, each comprising a sixth resistor (R₆), the fifth coupling circuit being arranged between the first node (9) and the non-inverting input (17) of the third amplifier (A₃), and the sixth coupling circuit being arranged between the second node (10) and the inverting input (18) of the third amplifier (A₃), a fifth and a sixth feedback circuit, each comprising an eighth capacitor (C₈), the fifth feedback circuit being arranged between the non-inverting input (17) and the inverting output (19) of the third amplifier (A₃), and the sixth feedback circuit being arranged between the inverting input (18) and the non-inverting output (20) of the third amplifier (A₃), and in that the inverting output (19) of the third amplifier (A₃) is connected to the sixth output terminal (22) and the non-inverting output (19) of the third amplifier (A₃) is connected to the fifth output terminal (21). A filter arrangement as claimed in Claim 7, characterized in that the first node (9) is connected to the inverting output (19) of the third amplifier (A₃) and the second node (10) is connected to the non-inverting output (20) of the third amplifier (A₃). A filter arrangement as claimed in Claim 8, characterized in that the conductance values of the first resistors (R₁) in the first and the second input circuit and of the second resistors (R₂) in the first and the second coupling circuit are substantially equal, in that the conductance values of the third resistors (R₃) in the seventh and the eighth input circuit and of the fourth resistors (R₄) in the third and the fourth coupling circuit are substantially equal, in that the conductance values of the fifth resistors (R₅) in the thirteenth and the fourteenth input circuit and the sixth resistors (R₆) in the fifth and of the sixth coupling circuit are substantially equal, in that the capacitance values of the second capacitors (C₂) in the first and the second input circuit and of the sixth capacitors (C₆) in the ninth and the tenth input circuit are substantially zero, in that the capacitance values of the third capacitors (C₃) in the third and the fourth input circuit and of the first capacitors (C₁) in the first and the second feedback circuit are substantially equal, in that the capacitance values of the fourth capacitors (C₄) in the fifth and the sixth input circuit and of the fifth capacitors (C₅) in the third and the fourth feedback circuit are substantially equal, and in that the capacitance values of the seventh capacitors (C₇) in the eleventh and the twelfth input circuit and of the eighth capacitors (C₈) in the fifth and in the sixth feedback circuit are substantially equal. A filter arrangement as claimed in Claim 7, characterized in that the filter arrangement further comprises a fourth balanced amplifier (A₄) having a non-inverting input (23) and an inverting input (24) and having a non-inverting output (26) and an inverting output (25), a seventh (27) and an eighth (28) output terminal, a fifteenth and a sixteenth input circuit, each comprising a ninth capacitor (C₉), the fifteenth input circuit being arranged between the first input terminal (1) and the non-inverting input (23) of the fourth amplifier (A₄) and the sixteenth input circuit being arranged between the second input terminal (2) and the inverting input (24) of the fourth amplifier (A₄), a seventeenth and an eighteenth input circuit, each comprising a seventh resistor (R₇), the seventeenth input circuit being arranged between the non-inverting output (20) of the third amplifier (A₃) and the non-inverting input (23) of the fourth amplifier (A₄), and the eighteenth input circuit being arranged between the inverting output (19) of the third amplifier (A₃) and the inverting input (24) of the fourth amplifier (A₄), a seventh and an eighth feedback circuit, each comprising a tenth capacitor (C₁₀), the seventh feedback circuit being arranged between the non-inverting input (23) and the inverting output (25) of the fourth amplifier (A₄), and the eighth feedback circuit being arranged between the inverting input (24) and the non-inverting output (26) of the fourth amplifier (A₄), a ninth and a tenth feedback circuit, each comprising an eighth resistor (R₈), the ninth feedback circuit being arranged between the non-inverting input (23) and the inverting output (25) of the fourth amplifier (A₄), and the tenth feedback circuit being arranged between the inverting input (24) and the non-inverting output (26) of the fourth amplifier (A₄), and in that the inverting output (25) of the fourth amplifier (A₄) is connected to the eighth output terminal (28) and the non-inverting output (26) of the fourth amplifier (A₄) is connected to the seventh output terminal (27). A filter arrangement as claimed in Claim 10, characterized in that the conductance values of the first resistors (R₁) in the first and the second input circuit and of the second resistors (R₂) in the first and the second coupling circuit are substantially equal, in that the conductance values of the third resistors (R₃) in the seventh and the eighth input circuit and the fourth resistors (R₄) in the third and the fourth coupling circuit are substantially equal, in that the conductance values of the fifth resistors (R₅) in the thirteenth and the fourteenth input circuit and of the sixth resistors (R₆) in the fifth and the sixth coupling circuit are substantially equal, in that the conductance values of the seventh resistors (R₇) in the seventeenth and the eighteenth input circuit and of the eighth resistors (R₈) in the ninth and the tenth feedback circuit are substantially equal, in that the capacitance values of the third capacitors (C₃) in the third and the fourth input circuit and of the first capacitors (C₁) in the first and the second feedback circuit are substantially equal, in that the capacitance values of the fourth capacitors (C₄) in the fifth and the sixth input circuit and of the fifth capacitors (C₅) in the third and the fourth feedback circuit are substantially equal, in that the capacitance values of the seventh capacitors (C₇) in the eleventh and the twelfth input circuit and of the eighth capacitors (C₈) in the fifth and the sixth feedback circuit are substantially equal, in that the capacitance values of the ninth capacitors (C₉) in the fifteenth and the sixteenth input circuit and of the tenth capacitors (C₁₀) in the seventh and the eighth feedback circuit are substantially equal, and in that the capacitance values of the second capacitors (C₂) in the first and the second input circuit and of the sixth capacitors (C₆) in the ninth and the tenth input circuit are substantially zero.

Inventors: VOORMAN JOHANNES OTTO, VOORMAN, JOHANNES OTTO
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1989
Main classification: H03H11
IPC codes: H03H11