An active-matrix display device

Abstract: An active-matrix display device comprising a plurality of picture elements (4) that are arranged into a matrix and thin-film transistors (6) that switch the picture elements, an MIS-structured diode (5) and each of the picture elements (4) being connected with the thin-film transistors in parallel.

Description: This invention relates to an active-matrix display device, such as a liquid crystal display device or the like, particularly to an active-matrix display device using thin-film transistors as switching devices. A conventional active-matrix liquid crystal display device using thin-film transistors (hereinafter abbreviated as TFTs, as necessary) reduces crosstalk between the picture elements by the incorporation of TFTs thereinto, and removes limitations of the number of scanning lines. This device, therefore, gives display a greater capacity and higher quality as compared with a display device of a simple matrix type. Even such an active-matrix liquid crystal display device using TFTs, however, may incur deterioration of its image quality such as a decrease of the image contrast caused by crosstalk, in the case where the off-characteristics of the TFTs are inadequate or the off-resistance of the liquid crystal is insufficient. Moreover, occurrences of internal offset voltage within the liquid crystal cells or the application of an asymmetric voltage to the liquid crystal may cause deterioration of its image quality such as flickering, low contrast, deviation of a potential between electrodes, or the like. To eliminate these problems, as shown in Figure 6 of the accompanying drawings, a conventional active-matrix display device is connected with a parallel circuit of the corresponding picture element 1 and the corresponding capacitance 2. The capacitance 2 alleviates deterioration of the image quality caused by inadequate off-characteristics of TFTs 3 and insufficient off-resistance of the liquid crystal. However, the conventional display device mentioned above cannot fully resolve the deterioration problem of the image quality caused by an internal offset voltage within the liquid crystal cells and an asymmetric voltage applied to the liquid crystal. Reference is also directed to US-A- 4704002 which discloses a dot matrix display panel, comprising a plurality of picture elements arranged in a matrix and a corresponding number of thin-film transistors, each picture element being switched by a respective one of the thin film transistors. The device also comprises a plurality of capacitors associated with the thin-film transistors or MIS diodes. The panel has a structure comprising a gate insulating layer and an amorphous silicon semi-conductor layer provided as one laminated film on, and substantially equal in shape and size to, an insulating substrate of the panel. In this structure, both the amorphous silicon semi-conductor layer and the gate insulating layer are common to all of the plurality of thin-film transistors and all of the capacitors/MIS-diodes. It is an object of the present invention to provide an active-matrix display device which overcomes the above-discussed and other disadvantages and deficiencies of the prior art. An active-matrix display device in accordance with the present invention comprises a plurality of picture elements that are arranged in a matrix and a corresponding number of thin-film transistors, each said picture element being switched by a respective one of said thin-film transistors, the device further comprising the same number of MIS-structured diodes as there are picture elements, each MIS-structured diode being connected in parallel with a respective one of said picture elements and comprising an insulating layer which is common to all other of the MIS-structured diodes and at least one respective doped silicon semi-conductor layer that is patterned into islands, a respective island constituting a part of said MIS-structured diode. In a preferred embodiment, the thin-film transistors are amorphous silicon thin-film transistors. In a preferred embodiment, gate insulating films of each of said thin-film transistors are formed by a two-layered film of tantalum oxide and silicon nitride or a two-layered film of tantalum oxide and silicon oxide. In a preferred embodiment, insulating films are formed by a two-layered film of tantalum oxide and silicon nitride or a two-layered film of tantalum oxide and silicon oxide. Thus, the invention described herein makes possible the provision of an active-matrix display device that prevents deterioration of the image quality caused by an internal offset voltage of the liquid crystal or an asymmetrical voltage applied to the liquid crystal. The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is an equivalent circuit of an active-matrix display device in accordance with this invention; Figure 2 is a plane view showing a part of a display device of this invention; Figure 3 is a sectional view showing the display device taken along line III-III of Figure 2; Figure 4 is a sectional view showing the display device taken along line IV-IV of Figure 2; Figure 5 is of a graph showing the capacitance-voltage characteristics of the MIS diode of the illustrated display device; and Figure 6 is an equivalent circuit of a conventional active-matrix display device. This invention provides an active-matrix display device in which each picture element and an MIS diode with a lamination of a metal layer, an insulating film, and semiconductor layers is connected with each TFT in parallel. In the case where a positive or negative voltage is applied to a display means (e.g., liquid crystal) or an MIS diode through the picture element electrode, the applied voltage begins to decay while being divided capacitively between the parasitic capacitance within the TFT, and a parallel circuit composed of the liquid crystal and the MIS diode, at the moment when the TFT is switched over from the On state to the Off state. In this case, since the capacitance value of the MIS diode changes depending upon the polarity of the bias voltage, the applied voltage capacitively divided changes, as well. The capacitance of the MIS diode varies so as to alleviate the asymmetry of the applied voltage that is caused by the parasitic capacitance of the TFT and the off-resistance of the liquid crystal. Thus, it is possible to effectively prevent the image quality from being deteriorated by the internal offset voltage and asymmetrically applied voltage. Examples Figure 1 shows an equivalent circuit of a liquid crystal display device of this invention, in which X₁ to X m show gate bus lines, and Y₁ to Y n show source bus lines. A number of picture elements 4 are arranged into a matrix, each of which is connected with a TFT 6 of amorphous silicon (a-Si) to drive the said picture element 4 . An MIS diode 5 is connected to each picture element 4 in parallel; that is, instead of capacitance 2 (Figure 6) of the above-mentioned conventional display device, the MIS-structured diode 5 is connected to each picture element 4 . The display device with the above-mentioned circuit structure is produced as follows: Tantalum is applied to a thickness of about 3000 Å on a glass substrate 20 by sputtering, and patternized by photolithography to form gate wirings 7 and diode wirings 8 (as shown in Figure 4). Then, the surface of the tantalum film is oxidized by anodic oxidation to form an insulating layer 14 of tantalum oxide (Ta₂O₅). Then, by plasma chemical vapor deposition, an insulating layer 15 with a thickness of 3000 Å of silicon nitride (SiNx), intrinsic amorphous silicon (a-Si(i)) layers 16 and 24 with a thickness of 300 Å each, and n-type amorphous silicon (a-Si(n⁺)) layers 17 and 23 with a thickness of 500 Å each are formed in this order. Then, by photolithography, the a-Si(i) layers 16 and 24 , and a-Si(n⁺) layers 17 and 23 are patternized into islands, forming patterns 10 and 12 . Thereafter, titanium (Ti) is applied to a thickness of 3000 Å by sputtering on those patterns, and patternized by photolithography to form source wirings 9 , drain electrodes 29 , and diode electrodes 22 . ITO is then applied to a thickness of 1000 Å by sputtering, and patternized by photolithography to form picture element electrodes 11 and source wirings 9 and 19 . In this way, TFTs 6 are formed in which MIS-structured diodes 5 are formed by a lamination of the tantalum oxide layer 14 , the silicon nitride layer 15 , the a-Si(n⁺) layer 23, and a-Si(i) layer 24 that are formed on the wirings 8 . Then, silicon nitride (SiNx) is applied to a thickness of 4000 Å by plasma chemical vapor deposition to form a protective film 33 , on which an orientation film 34 is formed, resulting in a substrate for use in a liquid crystal display device. Then, the said substrate is stuck with a glass substrate 30 on which a transparent electrode 31 of ITO and an orientation film 32 has been disposed. A liquid crystal 38 is put into a space between these substrates. The wirings 8 for the MIS diodes are electrically connected with the transparent electrode 31 , resulting in an active-matrix display device in which the MIS-structured diode 5 and the corresponding picture element 4 are connected with the corresponding TFT 6 in parallel. Next, operation for compensating the asymmetric voltage applied to the liquid crystal is described below: In the case where a positive or negative voltage is applied to the picture element 4 and the MIS diode 5 through the picture element electrode, the applied voltage begins to decay while being divided capacitively between the parasitic capacitance between the drain and the source within the TFT 6 , and a parallel circuit composed of the picture element 4 and diode 5 , at the moment when the TFT 6 is switched over from the On state to the Off state. In this case, since the capacitance of the MIS diode 5 changes depending upon the polarity of the bias voltage, the voltage to be applied to the picture element 4 and the MIS diode 5 by the above-mentioned capacitive division changes, as well. Since the above-mentioned display device uses the amorphous silicon of a lightly n-doped semiconductor as a semiconductor layer of the MIS diode, the capacitance of the MIS diode becomes large when a positive bias voltage (from the viewpoint of the counter-electrode) is applied (i.e., when a negative bias voltage from the viewpoint of the drain electrode is applied) (Fig. 5). Accordingly, decay of the voltage applied to the liquid crystal is decelerated. On the other hand, when negative bias voltage from the viewpoint of the counter-electrode (i.e., a positive bias voltage from the viewpoint of the drain electrode) is applied, the capacitance of the MIS diode becomes small. Accordingly, decay of the voltage applied to the liquid crystal is accelerated. The above-mentioned phenomenon of the deceleration and the acceleration of decay of the applied voltage acts so as to alleviate asymmetry of the positive and negative voltage applied to the liquid crystal, caused by the parasitic capacitance between the drain and the source of TFT or by the off-resistance of the liquid crystal. Accordingly, even though voltage is asymmetrically applied to the liquid crystal, since the asymmetry of the applied voltage is alleviated, it is possible to effectively suppress deterioration of the image contrast, flickering, etc. caused by the said asymmetry. Furthermore, it is possible to prevent occurrence of such defects as reduction of the time constant of the liquid crystal, deviation of the potential between electrodes, etc. The above-mentioned example uses two-layered films of tantalum oxide and silicon nitride as a gate insulting film of the TFT and an insulating film of the MIS diode, but one or both of those insulating films can be a two-layered film of tantalum oxide and silicon oxide, or a single-layered film of silicon nitride or silicon oxide only. As mentioned above, since each of the MIS-structured diodes and the corresponding picture element are connected with the TFT in parallel, this invention makes it possible for the diode to compensate for asymmetry of the voltage applied to each picture element so as to alleviate it. Thus, it is possible to effectively prevent deterioration of the image quality caused by internal offset voltage or asymmetrical voltage applied to a display means such as a liquid crystal, thereby attaining a great improvement of the image quality of the display device. It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope of this invention as defined by the appended claims.

Claims: An active-matrix display device comprising a plurality of picture elements (4) arranged in a matrix and a corresponding number of thin-film transistors (6), each said picture element (4) being switched by a respective one of said thin-film transistors (6), the device further comprising the same number of MIS-structured diodes (5) as there are picture elements (4), each MIS-structured diode (5) being connected in parallel with a respective one of said picture elements (4) and comprising an insulating layer (15) which is common to all other of the MIS-structured diodes (5) and at least one respective doped silicon semi-conductor layer (23,24), characterised in that the doped silicon semi-conductor layer (23,24) is patterned into islands, a respective island constituting a part of said MIS-structured diode (5). An active-matrix display device according to claim 1, wherein said thin-film transistors (6) are amorphous silicon thin-film transistors. An active-matrix display device according to claim 1, wherein gate insulating films of each of said thin-film transistors (6) are formed by a two-layered film of tantalum oxide and silicon nitride or a two-layered film of tantalum oxide and silicon oxide. An active-matrix display device according to claim 1, wherein insulating films are formed by a two-layered film of tantalum oxide and silicon nitride or a two-layered film of tantalum oxide and silicon oxide.

Inventors: ADACHI MASAHIRO, KATAYAMA MIKIO, MORIMOTO HIROSHI, TANAKA HIROHISA, ADACHI, MASAHIRO, KATAYAMA, MIKIO, MORIMOTO, HIROSHI, TANAKA, HIROHISA
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1989
Main classification: G02F1
IPC codes: G02F1