Amplifiers

Abstract: A high current drive integrated circuit amplifier in which the quiescent currents in the output transistors (1, 2) are controlled by control current signals which are applied to respective input signal amplifiers (6, 7) and which are of values determined by currents flowing in respective current sensing transistors (8, 9) associated with the output transistors (1, 2). The control arrangement (12) ensures that the output transistors (1, 2) can not be driven to a non-conducting condition.

Description: The present invention relates to amplifiers. In particular, although not exclusively the invention relates to high current drive integrated circuit amplifiers. Amplifiers capable of delivering output currents much higher than their quiescent currents tend to have complicated circuits, including additional amplifier stages within the main amplifier loops to control the quiescent currents. These additional amplifier stages introduce their own speed and stability problems, since they have to be separately stabilised, and any offsets within these additional amplifier stages can lead to ill-defined quiescent currents in the main amplifier. An arrangement for establishing quiescent currents in amplifier output stages is disclosed for example in published European Patent Application No. 0155717, in which voltage feedback from a pair of transistors having their inputs connected in common respectively with those of a pair of output transistors is utilised to establish the quiescent currents in those output transistors. Other arrangements having similar objects are disclosed in United States Patent Specification No. 4,480,230 and published European Patent Application No. 0217431. According to the present invention a complementary symmetry metal oxide semiconductor (CMOS) integrated circuit push-pull amplifier comprising an ouput stage including a first pair of field effect transistors of opposite conductivity type the source-drain current paths of which are connected in series across an energising supply, a second pair of field effect transistors having their inputs connected respectively in common with those of the first pair of transistors and first and second input circuit means for applying input signal voltages to the inputs of the transistors of said first and second pairs is characterised in that there are provided a control current path connec between the first and second input circuit means, the input signal voltages applied to the inputs of the transistors of said first and second pairs being dependent at least in part on the value of current flow through said control current path, and feedback means which is coupled to said control current path and which is responsive to the values of current flow in the source-drain current paths of said second pair of transistors to maintain substantially constant the value of current flow through said control current path and to effect substantially a predetermined minimum value of current flow in common through the source-drain paths of said first pair of transistors. Preferably the control current path comprises a third pair of field effect transistors of opposite conductivity type having their source-drain current paths connected in series in said control current path between the first and second input circuit means. The means to effect substantially a predetermined value of current flow in common through the source-drain paths of said first pair of transistors may comprise a fourth pair of field effect transistors of opposite conductivity type having their respective gate and drain electrodes connected together and having their source-drain current paths connected in series between the gate electrodes of the third pair of transistors. An amplifier in accordance with the present invention will now be described by way of example with reference to the accompanying drawings, of which:- Figure 1 shows the circuit of the amplifier schematically, Figure 2 shows part of the circuit of Figure 1 diagrammatically, and Figure 3 shows substantially the whole circuit of the amplifier diagrammatically. Referring first to Figure 1, the amplifier is shown as a CMOS integrated circuit amplifier, although the invention could equally be applied to bipolar transistor amplifier circuits. The amplifier comprises a complementary pair of output transistor devices 1 and 2 which are arranged to source or sink output currents to or from a load (not shown) connected to an output path 3 in dependence upon input signal voltages applied differentially between input terminals 4 and 5. Voltage amplifiers 6 and 7 are arranged to apply drive voltages dependent upon these input signal voltages to respective output devices 1 and 2, the drive voltage provided by the amplifier 6 being applied in common to the gate electrode of the output device 1 and that of a current sensing transistor 8, and the drive voltage provided by the amplifier 7 being applied in common to the gate electrode of the output device 2 and that of a current sensing transistor 9. Individual compensation capacitors 10 and 11 are provided between the output path 3 and the output circuits of the amplifiers 6 an 7. A quiescent current control circuit 12, shown diagrammatically in Figure 2, is arranged to draw a current of a predetermined value between a point in the output circuit of the amplifier 6 and a corresponding point in the output circuit of the amplifier 7, which predetermined current value serves to set the quiescent current levels in the output devices 1 and 2 and the respective current sensing transistors 8 and 9. The circuit 12 comprises a p-channel transistor 13 the source to drain path of which connected between the drain electrode of the p-channel sensing transistor 8 and a negative supply line 14, and an n-channel transistor 15 the source to drain path of which is connected between the drain electrode of the n-channel sensing transistor 9 and a positive supply line 16, the gate electrodes of the transistors 13 and 15 being connected to earth. The source electrode of the transistor 13 is connected to the gate electrode of an n-channel transistor 17 and the source electrode of the transistor 15 is connected to the gate electrode of a p-channel transistor 18, the drain to source and source to drain paths respectively of these transistors 17 and 18 providing the path for the current of predetermined value referred to above. An n-channel transistor 19 and a p-channel transistor 20 have their source electrodes connected together, the gate and drain electrodes of transistor 19 being connected together and to the source electrode of the transistor 13, and the gate and drain electrodes of transistor 20 being connected together and to the source electrode of the transistor 15. Referring now to Figure 3 the amplifiers 6 and 7 are of similar form but with the polarity of all transistors reversed. Thus the amplifier 6 comprises a long-tail pair of p-channel transistors 21 and 22 whose source electrodes are connected to a constant current source comprising transistor 23 and whose drain electrodes are connected to an active load in the form of a current mirror circuit 24. An output from the drain electrode of the transistor 22 is applied to the gate electrodes of the transistors 8 and 1 by way of cascoded transistors 25 and 26, which are connected between the negative and positive supply lines 14 and 16 by way of constant current sink and source transistors 27 and 28 respectively. The current path through the transistors 17 and 18 is connected between the drain electrode of the transistor 22 and the corresponding point in the amplifier 7, while the compensating capacitor 10 is connected to the source electrode of the transistor 26. A similar current path is provided between the drain electrode of the transistor 21 and the corresponding point in the amplifier 7 by way of a complementary pair of transistors 29 and 30. The current sensing transistors 8 and 9 are much smaller than the respective output transistors 1 and 2, and draw correspondingly smaller currents. However since all four transistors in general operate in the region of saturation the drain currents of the sensing transistors 8 and 9 in operation are proportional to their gate drive voltages, as are the drain currents of the respective output transistors 1 and 2. The currents flowing through the sensing transistors 8 and 9 in general flow partly in common through the transistors 19 and 20 and partly through respective transistors 13 and 15. The sum of gate/source voltages concomitant with the current flow in these transistors 13 and 15, 19 and 20, provides a forward bias between the gate electrodes of the transistors 17 and 18. If the drive voltage to either output transistor 1 or 2 rises, so that the current in that transistor and in the corresponding sensing transistor 8 or 9 rises, the forward bias between the gate electrodes of the transistors 17 and 18 tends to rise, as does the current flow through these transistors. Any such increase in current flow in transistors 17 and 18 will leave a smaller proportion of the constant current flow through, say, the transistor 27 to be drawn through the cascode transistors 25 and 26, thus reducing the drive voltage to the transistors 8 and 1. The sense of the feedback around this loop will therefore tend to maintain substantially constant the voltage across the transistors 19 and 20 and the current through the transistors 17 and 18. In the absence of input signal voltages between the terminals 4 and 5 the current feedback loop determines substantially equal quiescent current flow values in the output transistors 1 and 2, and in the associated current sensing transistors 8 and 9. If the transistors 13 and 15, 17 and 18 and 19 and 20 are of similar size, the quiescent current flow through the sensing transistors 8 and 9 will tend to split equally to flow half through the transistors 13 and 15 respectively and half in common through the transistors 19 and 20. In the presence of an increasing input signal voltage between the terminals 4 and 5 the decreasing value of drive voltage to, say, the transistors 9 and 2 will tend to decrease the value of current flowing in the sensing transistor 9, and increase that in the sensing transistor 8, to the point where current flow in the transistor 15 tends to cut off. However, a current of half the quiescent value will continue to flow through the transistors 19 and 20, maintained in value by the current feedback loop, so that the drive voltage actually delivered to the gate electrodes of the transistors 9 and 2, by virtue of the current feedback loop and the nature of the output circuits of the amplifiers 6 and 7, can never reduce the current flow through the sensing transistor 9, say, to less than half the quiescent value. Since the quiescent current control circuit 12 has currents as input and output, with no internal voltage gain or high impedance nodes, no compensation is required within it. Large output currents are possible because of the large drive voltages which may be set up in the output stages of the amplifiers 6 and 7. Any offsets between the amplifiers are corrected by the quiescent current control circuit 12. In order for the amplifier as a whole to be stable when driving large output currents the voltages across the compensation capacitors 10 and 11 should not vary with output current. This is achieved by connecting each of these capacitors to a low impedance node in the cascode output circuit of the respective amplifier 6 or 7. The cascode transistor 26 having its gate electrode connected to earth improves power supply rejection, by making the voltage across the compensation capacitor 10 less dependent upon power supply voltage. The transistors 29 and 30 are arranged to draw a current between the drain electrode of the transistor 21 in the amplifier 6 and the corresponding point in the amplifier 7 substantially to balance the current drawn through the transistors 17 and 18. Additional transistors 31 to 34 are provided to "power down" the amplifier, that is, to turn the output transistors 1 and 2 off by biasing the cascode output stages of the amplifiers 6 and 7 off.

Claims: A complementary symmetry metal oxide semiconductor (CMOS) integrated circuit push-pull amplifier comprising an output stage including a first pair of field effect transistors (1, 2) of opposite conductivity type the source-drain current paths of which are connected in series across an energising supply, a second pair of field effect transistors (8, 9) having their inputs connected respectively in common with those of the first pair of transistors (1, 2), and first and second input circuit means (6, 7) for applying input signal voltages to the inputs of the transistors of said first and second pairs (1, 2 and 8, 9) characterised in that there are provided a control current path (17, 18) connected between the first and second input circuit means (6, 7), the input signal voltages applied to the inputs of the transistors of said first and second pairs ( 1, 2 and 8, 9) being dependent at least in part on the value of current flow through said control current path (17, 18), and feedback means (13, 15, 19 and 20) which is coupled to said control current path and which is responsive to the values of current flow in the source-drain current paths of said second pair of transistors (8, 9) to maintain substantially constant the value of current flow through said control current path (17, 18) and to effect substantially a predetermined minimum value of current flow in common through the source-drain paths of said first pair of transistors (1, 2). An integrated circuit push-pull amplifier in accordance with Claim 1 wherein the control current path comprises a third pair of field effect transistors (17, 18) of opposite conductivity type having their source-drain current paths connected in series in said control current path between the first and second input circuit means (6, 7). An integrated circuit push-pull amplifier in accordance with Claim 2 wherein the means to effect substantially a predetermined value of current flow in common through the source-drain paths of said first pair of transistors comprises a fourth pair of field effect transistors (19, 20) of opposite conductivity type having their respective gate and drain electrodes connected together and having their source-drain current paths connected in series between the gate electrodes of the third pair of transistors (17, 18).

Inventors: DEDIC IAN JUSO, DEDIC, IAN JUSO
Applicants: PLESSEY SEMICONDUCTORS LTD, PLESSEY SEMICONDUCTORS LIMITED
Application year: 1989
Main classification: H03F1
IPC codes: H03F1