DISTRIBUTED ROUTER OF CONNECTIONLESS PACKETS OVER CONNECTION ORIENTED NETWORKS

Abstract: A network for routing datagrams which include at least one segment, the network comprising at least one segment switching means (101 ... 104) and a plurality of routers (111 ... 130) connected between the switching means (101 ... 104) and a plurality of terminals (91 ... 98) and adapted to process data in a datagram transferred from a first terminal (91) so as to pass the datagram from a first router (111) to a second router (118) via the switching means (101 ... 104) and pass the datagram from the second router (118) to a second terminal (96). A method of routing datagrams is also provided with the datagrams being routed through a hierarchical arrangement of switching means on the basis of their final destination addresses. A router for connecting the switching means and processing the final destination address to enable transfer of datagrams across the network is also provided.

Description: DISTRIBUTED ROUTER OF CONNECTIONLESS PACKETS OVER CONNECTION ORIENTED NETWORKS FIELD OF THE INVENTION This invention relates to the field of packet routers, in particular, to routers of datagram packets over a connection-oriented network, with plurality of hierarchical levels and plurality of routers at any hierarchical level distributable over the network. BACKGROUND OF THE INVENTION Computer communications over Local Area Networks (LANs) are typically carried on by datagrams without prior set-up of connection between the communicating equipments. This is advantageous because of simplicity in protocol, requiring no set-up procedure, and because of speed of communication, obviating the time delay that would be incurred by the connection set-up. It is desirable to have the possibility of such connectionless datagram communications also over wide area, without limitations brought about by distance. For economic reasons wide area communications are most advantageously provided in a shared or common carrier manner. Therefore the desire for wide area datagram communication must realistically be linked with the evolution of public networks and the means for bringing it about must be made part of such networks. There are two developments already in the realm of public networking that are centrally relevant to the quest for wide area datagrams communication. They are the development of Metropolitan Area Networks (MANs) being ' standardised by the Institution of Electrical and Electronic Engineers Project 802.6 and the development of Broadband 1 Integrated Services Digital Network (B_ISDN) being 2 standardised by the International Consultative Committee on 3 Telegraphy and Telephony (CCITT) Study Group XVIII. Among 4 recent published overview references to the two developments 5 are respectively an article by R.M. Newman, Z.L. Budrikis 6 and J.L. Hullett entitled "The QPSX MAN", IEEE 7 Communications Magazine, Vol. 26, No. 4, pp 20-28, April 8 1988 and an article by T.M. Chen and D.G. Messerschmidt 9 entitled "Integrated Voice/Data Switching", IEEE 0 Communications Magazine, Vol. 26, No. 6, pp 16-26, June 1 1988. 2 3 A MAN will provide integrated digital communications, 4 including datagram communication, typically over the area of 5 a city. B_ISDN is intended to be universal and may 6 eventually subsume MANs, provided it will also offer 7 datagram communications. However the gamut of services by 8 the B_ISDN as presently conceived contains only connection- 9 oriented communications, with datagram communication only ' as 0 a specialist limited service rendered by a centralized 1 server on a subscription basis. 2 3 SUMMARY OF THE INVENTION 4 5 The invention disclosed here is of a router for 6 datagrams that is applicable to MANs and B_ISDN, though not 7 restricted in scope to those particular network 8 developments. The present invention provides a network for 9 routing datagrams which include at least one segment, the 0 network comprising at least one segment switching means, and 31 a plurality of routers connected between the switching means 32 and a plurality of terminals and- adapted to process data in 33 a datagram transmitted from a first terminal so as to pass 34 said datagram from a first router to a second router via 35 said switching means and pass said datagram from said second 36 router to a second terminal. 37 . 38 The invention also provides a method of routing datagrams in a network having at least one segment switching means, and a plurality of routers connected between the switching means and a plurality of terminals, said method comprising processing data in a datagram transmitted from a first terminal so as to pass said datagram from a first router to a second router via said switching means and pass said datagram from said second router to a second terminal. In known arrangements a central datagram server is generally envisaged for the purpose but this cannot perform satisfactorily and, in accordance with the invention a distributed routing scheme is provided. In the system of the invention the routing task of a datagram router can be reduced to directing the datagram to the appropriate other router when there is no diversity (i.e. only one possible path from source to destination), or to an appropriate other router when there is diversity. It has also been recognised that the datagram can be sent from the one router to the other over the connection-oriented network without requiring circuit set-up, provided a set-up circuit exists permanently between the two routers. These, principles apply equally when the connection-oriented network has actual physical circuits and when it has virtual circuits. It has been further recognized that routers can be grouped into domains and that domains can be interconnected hierarchically. It has been further recognized that advantageously the routers should be logically at the edge of a domain and thus be edge devices having two distinct directions. A router directed from domain j into domain i may be designated Rji. It is an edge device of both domains, j and i. It has its input socket from domain j and its output socket into domain i. Similar observations with reversed direction apply to router Rij . For universal connectionless datagram transfer, all routers entering a domain must be permanently connected to routers that leave the domain. The exception is that the output of Rji is not• connected to the input of Ri . A further requirement for universal connectivity is that in all domains except the domain at the highest hierarchical level, there is at least one router whose output goes directly or indirectly to a domain at higher hierarchical level. Yet further requirements are that there be only one domain at the highest hierarchical level and that every domain be reachable from that highest level domain. A domain may comprise a fast packet switch or Asynchronous Transfer Mode Switch (ATM switch) having a plurality of input and output ports, all ports being interconnected. An example of a fast packet switch is described in the article by "Starlite, A Wideband Digital Switch", A. Huang and S. Knauer, 1984 Proceedings of IEEE Conference on Global Telecommunications pp 5.3.1-5.3.5. It has been recognized, that given the above structure and properties, routing can be done everywhere on the basis of a global final destination address. Also, the process of routing can be done expeditiously provided that the address itself is subdivided into hierarchical subfields, as for instance, a fifteen digit number divided into three or four subfields approximating the existing practice in telephones numbering. It has been recognized that the task at any router is that of translating the final destination address to a route label that indicates the circuit on which the datagram has to be sent so as to reach the appropriate next router. It has been further recognized that the translation can be done by look-up of candidate labels and of values of particular logical variables, associated with the candidate labels, minimally one label candidate associated with each subfield of the final destination address. The actually applicable label can be determined by simple deduction based on the values of the logical variables. This procedure of determining the applicable label amounts to a novel algorithm. The translation carried out in accordance with this algorithm can be done at great speed so that the routing can be implemented on the fly even when datagrams are transmitted at 100 Mbit/s or even higher. The present invention is applicable both when the datagrams are transmitted as variable length packets where all bits of the packet are transmitted contiguously and when the datagrams are segmented into parts. The IEEE 802.6 and the B_ISDN schemes have segmentation into segments of fixed length and the detailed description of the invention which follows is for that case. The reassembly of datagrams from segments that are transferred in an interleaved manner over a connection- oriented network' poses a problem bf similar magnitude in memory or speed requirement as does route selection. In accordance with the invention it has been recognized that it is also a problem of label translation from a large to a smaller space. The invention also provides a router for a network for routing datagrams having at least one segment, said router comprising: first means for receiving said datagram and accessing said destination address from said datagram; second means responsive to said first means for determining output connection data (VCI_0UT) on the basis of said destination address; and third means for including said output connection data (VCI_0UT) in said datagram; said datagram being routed in said network on the basis of said output connection data (VCI_0UT) after being outputted from said router. BRIEF DESCRIPTION OF THE DRAWINGS The invention together with the operation and practice of it will be more fully described, by way of example only, with reference to the accompanying drawings, in which: FIGURE 1 is a block diagram of a hierarchical network embodying the routing scheme of the invention; FIGURE 2 shows the format of an IEEE 802.6 standard segment; FIGURE 3 shows the format of an IEEE 802.6 MAC (Media Access Control) level packet header; FIGURE 4 shows the format of the CCITT E.164 service number; FIGURE 5A is an overview block diagram of a router circuit; FIGURE 5B is a block diagram the address-to-VCI translator embodying the principle of label translation of the invention; FIGURE 6 shows a block diagram of a reassembly message identifier determining circuit; FIGURE 7 shows a block diagram of a tag server which is part of the system of Figure 6; FIGURE 8 shows a logic circuit that may be used for the priority encoding called for in the scheme of Figure 5; FIGURE 9 shows a block schematic of the multiplexor of the scheme of Figure 5; and FIGURE 10 is a flow diagram of the program executed by the Controller of Figure 7. DETAILED DESCRIPTION in the prior art it seems to be taken for granted that the routing of datagrams should be given to one or more centralised servers. These would be computers to which subscribers would have prearranged circuits. A subscriber would send a datagram to that computer including in the datagram an indication of the intended destination(s) and, in turn, the computer would send the datagram to that destination or those destinations, again using prearranged circuits. Since the circuits over which the datagrams are sent are permanently set up, there is no delay due to circuit set-up and in that sense the scheme of the prior art is high speed. But the fact that all datagrams have to be channelled through the one processor robs the scheme of any chance of having truly high speed or real time performance. Moreover the scheme is limited in interconnectivity to a finite number of subscribers. This problem is avoided, in accordance with the invention by distributing the service function and making it such that the scheme can grow without limit, even to covering a substantial portion of the communicating equipment on earth, and achieve connectionless or datagram connectivity for all. The system of the invention superimposes on a connection-oriented switched network which may be established especially for that purpose or which could exist to carry other communication traffic. With reference to Figure 1, the overall connectionless routing system is divided into domains. By way of illustration domains at Level zero are shown as circles and labelled 81 through to 85. A Level zero domain may comprise a QPSX MAN referred to earlier. The domains at Level one, two and three are shown as square boxes, Level one domains being labelled as 101 and 102, a Level two domain as 103 and a Level three domain as 104. The system includes three Type I routers 111, 113 and 129 which take input from a Level zero domain and output into a Level one domain. Type II routers ' , examples of which are 112, 114 and' 130 take input from a Level one domain and output into Level zero domain. Type III routers, examples of which are 119, 120, 121, 122, 126 and 128, have inputs and outputs in Level one and higher domains. Inherent in the system of Figure 1 is the assumption that Level zero domains require no routing. Customers or end equipments are attached exclusively to Level zero domains. End equipments are illustrated by small circles, such as 91 and 92 attached to Level zero domain 81. There is no need for routing over these domains either because they have only one piece of end equipment or because it is a connectionless subnetwork, like that standardized as the IEEE 802.6 MAN, which supports connectionless datagram transfers. The latter alternative reduces the number of routers required for the overall scheme and is the more advantageous of the two. The Level one domain, labelled 101 is illustrated with fixed circuits connecting the output socket of Router 113 to the input sockets of all Type II and Type III routers on the domain, except 114-, namely 112, 116, 118, 119 and 121. Similarly the input to Router 114 is shown connected to all outputs of Type I and III. Routers 113 and 114 have, been singled out for brevity;* similar lines go from each router to every other router in the domain, and similarly for the routers on domains 102, 103 and 104 but these are not shown in Figure 1 for clarity of illustration. Assuming that there are N incoming routers and N outgoing routers around the edge of a domain and two domains are connected by a single oppositely directed pair of routers, then the number of one-way, or simplex, circuits emanating from each output socket is (N-l), and that is also the number of simplex circuits terminating on each input socket. The total number of fixed simplex circuits in the domain is 2N(N-1). Still referring to Router 113 on domain 101 of Figure 1 , consider the instance of a datagram that has originated in domain 82 , that is intended to go beyond domain 82. It has to be routed by Router 113 to another router with input socket in domain 101. The routing is made on basis of the final destination address which is carried in the header of the datagram. This task and its implementation embodying the principles of the invention will be described for the case of the format of the datagram and its transmission being in conformance with the IEEE 802.6 Draft Standard (Draft D9, August 1989). The datagram is carried in a succession of fixed length segments. The format of a segment is shown in Figure 2. With reference to Figure 2 the rows represent groups of eight binary digits, or octets, with the sequence of transmission left to right and top to bottom. The first seven octets, labelled 01-07, are segment header and of the remaining 46 octets, 44 are payloaded with data for transmission and 2 are a segment trailer. A datagram may have any length up to 8000 octets and by the above is carried in segments 44 octet long. The IEEE 802.6 Standard provides for two other classes of service besides connectionless datagram namely isochronous and connection-oriented non-isochronous. The segments of all three classes share the segment header octets 01 through to 05. Whether a segment is part of a connectionless datagram is indicated by a particular value of the final four bits of the VCI (Virtual Circuit Identifier) field 71, i.e. the first four bits of row 04. When these are all zeros, the segment is connectionless. In the description which follows the expressions "VCI" and "Label" are used synonomously. Given that the segment is connectionless, the information of whether it is carrying the beginning of a message (BOM), continuation of a message (COM), end of a message (EOM) or a single segment message (SSM) is disclosed by the two-bit S_Type field, or subfield 75 in Figure 2. All segments of a message must carry the same message identifier, (M_ID) field 76.. A datagram begins with octet 08 of an SSM or BOM segment and is started by an ISO (International Standards Organisation) Level 2 header followed by an ISO Level 3 header. By a principle of the present invention routing is on the basis of the final destination address. That address will in all cases be present in the Level 3 header. It is possible by the IEEE 802.6 Standard that the CCITT E.164 final destination address is also present in the Level 2 header, and the routing can then be done on the basis of that header. In the following description it is assumed that the latter applies. Should in a given circumstance the Level 2 header not have a final destination address then what is described here would be done with little change on the basis of the destination given in the Level 3 header. Figure 3 shows the Level 2 header format conforming to the IEEE 802.6 Standard. There are seven fields altogether with only the destination address (DA) field 142 of immediate interest. It consists of two subfields, the first of four bits indicating the address type and the second a 60 bit subfield of address. When the address is according to CCITT E.164 then all 60 bit positions are taken up by the 15 binary-coded decimal numbers of that address. Its format is shown in Figure 4. The connectionless routing task and the principles of the invention for implementing it can be understood with reference to Figure 5A which is a block diagram of a router. The router takes in segments serially having the format of Figure 2 on an uninterrupted time basis on input line 520, modifies them in the appropriate manner and puts them out serially on output line 538. Input and output, in use, are continuous and regular, at the rate of the network transmission. For instance, if the rate is 44.210 Mbit/s, one of the standard net rates in public network digital transports and currently planned to be used in DQDB networks in North America, then the rate of segment input and output is 104, 269 segments/second. A router with the architecture of Figure 5A and with components of the invention is feasible at that and higher rates, for instance 140 and 155 Mbit/s which are also currently contemplated in DQDB networks. The input and output can be serial in individual bits or in groups of bits, for instance 8 bit groups or octets, and that will not alter the principles of the invention. The router is comprised of identifiable standard components: latches 503 and 504, demultiplexers 506, 507 and 508, multiplexors 509, 510, 511, 512 and 513, and delays 541, 542, 543 and 544. It incorporates two systems of the invention: the address-to-VCI translator 501 and the packet re-assembler/label server 502. The timing of events in all components and the systems is under the control of Timing Control 505, which itself is synchronized to the bits or groups of bits and segment starts in the input. Latch 503 captures S_Type, which is field 75 in the format of Figure 2 and indicates the segment type. The contents of latch 503 provides an indication to Demultiplexer 506 and also to the systems 501, 502 and Multiplexor 513. If the segment is a single segment message (SSM) or a beginning of message (BOM), the Demultiplexer 506 puts the segment on line 521. If it is a continuation of message (COM) or end of message (EOM) then it is put on line 522. Delay 541 delays the segment sufficiently to allow a decision ' to be made, having regard to the contents of latch 503 as to which output to switch to in time for the arrival of the first bit of the " segment. The segments leaving the router must have the same bit fields as they came in with, except for the VCI and M_ID which are fields 71 and 76 in Figure 2. Further exceptions are two .cyclic redundancy fields that are recalculated and changed. We assume that these are not done in the router but in a further unit that follows it. But of course that function could also be incorporated in the router system without altering the invention. The segments leaving the router must have VCIs and M_ID's appropriate for their passage to their next immediate destination. The VCIs are the labels by which the ATM switch, for instance 101 or 103 of Figure 1, transfers the segments from a given input port to intended output ports. The M_ID's are the labels that logically link the separate segments of a message, and must be different for different messages that are concurrent or interleaved in their segments for a given source and destination. The appropriate VCI is determined from the final destination address or subscriber number, such as that of 91 or 97 in Figure 1, which is carried at the head end of the message, i-e. at the start of field 77 of SSMs and BOMs. The final destination is latched from the incoming SSM and BOM by Latch 504 and presented on line 527 to the Address-to-VCI Translator 501 which determines the appropriate VCI and puts it on line 528. The SSM or BOM is demultiplexed in Demultiplexor 508 which places the VCI and M_ID that it has on entry on line 525 and the remaining fields on line 526. In the case of a BOM the VCI_IN and M_ID_IN on line 325 and VCI_OUT on line 528 are read into the Message Reassembler/Label Server 502, so that this unit is able to recognize the subsequent COMs and EOM of that same message and give to these the same VCI_OUT and M_ID_0UT as are given to the BOM. The remaining fields on line 526 are applied via Delay 543 to Multiplexor 512 which multiplexes them with 1 VCI_0UT and M_ID_OUT to make up B0M_0UT. The M_ID_OUT is 2 given out by the Message Reassembler/Label Server 502. 33 . 4 5 In the case of an SSM, the M_ID is in all cases a null 6 field and there is no linking of any subsequent segments 7 with the first. Therefore there is no need to place the 8 VCI_IN, M_ID_IN and VCI_OUT into store in the 9 Reassembler/Label Server 502, which supplies the appropriate 0 (null) M_ID_0UT for the SSM. Therefore SSM_0UT is formed by 1 the same multiplexing as is B0M_0UT and appears on the same 2 line 536. COM and EOM segments are similarly demultiplexed, by 5 Demultiplexer 507, which places the incoming VCI and M_ID on 6 line 524, and the remaining fields on line 523. The VCI_IN, M_ID_IN are input to the Reassembler/Label Server 502 which recalls the VCI_0UT and M_ID_0UT that had been given to the BOM segment of that message. The VCI_0UT and M_ID_OUT are multiplexed in Multiplexor 510 and* the output of this multiplexor is multiplexed with the remaining fields of the segment, C0M_R_IN or E0M_R_IN in Multiplexor 511 which places the resulting segment, C0M_0UT or E0M_0UT on line 535. Finally, Multiplexor 513 selects for output as SEG_0UT on line 538 the input either on line 536 or 535, whichever is appropriate by the S_Type indication on line 540. Demultiplexing and multiplexing are shown in Figure 5A ' as being performed in progressive stages. This is for the sake of description only. In actual implementation all of the demultiplexing, shown in units 506, 507 and 508, would be more effectively done in a single demultiplexer, and of all the multiplexing, shown in units 509-513, in a single multiplexor. Also for the sake of description only, B0M_R_IN and SSM_R_IN are shown as distinct from COM_R_IN and E0M_R_IN. In implementation they would not be distinguished and would be on common line. Hence the two 1 delays 542 and 543 would also be a single delay. 2 3 The delays, shown in Delay units 542, 543 and 544 are 4 important for ensuring proper time alignment of the 5 different components of the outputted segment. The delays 6 542 and 543, if not common, must be equal to each other, and 7 equal to the larger of the delays in unit 501 or 502 in 8 producing the VCIJDUT and M_ID_0UT. 9 10 If the larger delay is in Unit 502, Unit 544 is 11 inserted as a trimming delay in line 528 to make the delay 12 with which VCIJDUT from Unit 501 is available for 13 multiplexing equal to the delay from Unit 502. If 501 had 14 the longer delay, then the trimming delay would instead be 15 applied to VCI_0UT and M_ID_OUT from 502. 16 17 Since segments may come into the router one after the 18 other without any time gap between them, and succeeding 19 segments may quite arbitrarily be any of the four types, 20 BOM, * SSM, COM or ' EOM, the tasks performed with respect to a 21 segment by the Units 501 and 502 with the architecturing of 22 Figure 5A should be completed in a single segment period. 23 This incidentally means that the delay of Delay Units 542 24 and 543 is limited to a maximum of one segment period and 25 more significantly that the systems 501 and 502 in fact 26 perform their tasks in the limited time. 27 28 The task of the Address_to_VCI translator can be 29 accomplished in the short time that is available if the 30 translation can be done by simple memory look-up. For each 31 possible destination address there would be in memory an -32 appropriate VCI. But at present that is not practical, 33 given the size of the address space. Since the destination 34 address has 60 bits, the number of possible different 35 addresses is 2 60 or 10 18 . 36 37 An approach has been developed that makes it practical 38 to accomplish the address_to_VCI translation by memory look αp and has been termed simultaneous partitioned memory look-up. The total address is divided into subfields, each of which is small enough to access a corresponding memory that is of practicable size. With reference to Figure 5B, which illustrates a block schematic of system 501 of Figure 5A, the destination address D_ADDR on line(s) 522 is demultiplexed into the (n+1) fields, FieldJ), Field_l...Field i on lines 211,214, ...216. These fields are presented as addresses to the random access memories 221,222, ...225,226. From each memory a read-out is made of a candidate VCI, VCI_0 on line 244, VCI_1 on line 234,...VCI-n on line 236. Also read out from each memory is a logical variable, I Q on line 243, I on line 244,...,I n on line 246. The candidate VCIs are input to the multiplexor MUX 270 and the logical variables to the logical unit 250. The logical unit produces control signals on lines 260 which collectively select the appropriate VCI and this becomes VCIJDUT on the multiplexor output lines 528. The VCI and logical variables stored and retrieved from the memories are dependent on the particular partitioning of the address _ and the particular interconnections of hierarchical domains that are made. The task of writing to the memories would be done by a network management system. In the description which follows the selection of the VCI is for the case where the partitioning of the address is strictly hierarchical and where furthermore this partitioning corresponds exactly to the hierarchical division into domains. The logical variable is then simply a single binary bit indicating whether a routing to at least that level is indicated and the selection is then effected by a priority encoding by the logical unit or priority encoder 250. The task of priority encoding is known and can be - understood from the following mathematical description of the function of a priority encoder. Let I j , k = 0,1, ..n be the binary valued inputs to the priority encoder and let ^, j = 0, ...m be the binary-valued outputs from the encoder. Collectively the outputs can be taken as a binary coded decimal positive integer y whose value is m j-0 The largest possible value of y must at least equal n. This is assured if m > log 2 .(n+1) (2) • * The output of the encoder has the value y = z if and only if I z = 1 and Ij = 0 for j = * z+l,...,n (3) The truth table of a priority encoder for the case of n=7, and therefore m=3, is given in Table I. 6 TABLE I A realization of the encoder is given in Figure 8. The logical variables I l t to I 7 are put on lines 285 through 291. These or their negations or inverses, as for instance the negation of I<2 by the "negator or inverter 292, are put in the different combinations shown to the OR gates 300 to 304. The outputs of the OR gates along with certain combinations of 1- j 's or negation I- j 's are input to the AND gates 305, 306 and 307 that produce as their outputs and put on lines 308, 309 and 310 respectively XQ, X and 2 . IQ is not an input to the circuit because the output XQ = 0, x*^ 0, 2 = 0, that corresponds to lg = 1 is produced by the encoder as a default when I ^ through I are all zero. The label selection is implemented by the multiplexor 270 of Figure 5B. A realization of a multiplexer for the simplified case of selecting one from four sixteen bit labels is illustrated in Figure 9. In this case there are only two x components, XQ and x j *_. These are presented to the decoder 410. Depending on the values of XQ, X-**_, one particular output line 421, 422, 423 or 424 is asserted. The truth table for the decoder 410 is given in Table II. 1 These lines are applied to the ENABLE inputs of tri-state 2 buffers 440, 441, 442 and 443. The input to the buffers are " 3 respectively VCI_0, VCI_1, VCI_2 and VCI_3 and depending on 4 which buffer is asserted, that Label appears on the buffer 5 output and is placed on the output bus 528. 6 7 TABLE II 8 18 19 The tasks of the Message Reassembler/Label Server 502 20 of Figure 5A " , should also be completed in less than a 21 segment period, and to accomplish this, memory look-up is 22 again required. The address space for this is the union of 23 VCI and M_ID which is 34 bits, and hence the number of 24 address locations required would be of the order of 2 x 25 10 * *" . Again this is far too large to be practical. 26 27 A two sep memory look-up to enable this has been 28 developed and an embodiment is described with reference to 29 . Figure 6. The VCI_IN and M_ID_IN of the incoming segment on 30 line 524 are presented to and are demultiplexed by 310 and 31 respectively passed to the VCI TAG server 317 and M_ID TAG 32 server 318 which produce a VCI TAG of k bits on bus 322 and 33 an M_ID TAG of 1 bits on bus 323. The two buses are 34 combined into the common bus 324 of (k+1) bits and presented 35 to the M_ID_0UT Server 326 which in turn produces the 36 M_ID_0UT 328 and to the VCIJDUT Server 325 which produces 37 the VCI_0UT 327. 38 The required memory sizes in the four servers are related exponentially to the number of input bits and linearly to the number of output bits. The total number of bits stored over the four memories is : N-L = k2 m +12 n + n2^ k+1 ) + m2( k+1 ) (4) If a single memory look-up was used then the number of stored bits would be N 2 = (m+n) 2< m+n > (5) When (k+1) is an appreciably smaller number than (m+n), then N^ is very much smaller than N 2 . For instance, with m equal to 20 and n equal to 14 and if k and 1 are both equal to 8, N**L is approximately eleven million, while N 2 is in excess of 5 x 10 11 or five hundred thousand million. The four servers 317, 318, 325 and 326 in the block schematic ' of Figure 6 are all similar circuits differing only in numerical sizes of memories and lines and can be understood with the help of Figure 7. The Key 350 in Figure 7 represents any one of the inputs VCI_IN 311 or M_ID_IN 312 or combined VCI TAG and M_ID_IN TAG 324 of Figure 6. The TAG 396 in Figure 7 represents respectively the VCI TAG 322 or M_ID_IN TAG 323 or VCIJDUT 327 or M_ID_0UT 328 of Figure 6. With reference to Figure 7, the key 350 is applied on bus 356 as address selection to Count RAM 340 and on bus 355 as address selection to Label RAM 365. This enables the read-out and write-in of data stored at the selected memory locations. A count value 347 from the RAM 340 is read out into a counter 346, and a label value 389 from the RAM 365 is read into Tag_latch 395. Writing into the RAMs and operation of the counter 346, latch 395 and TAG_FIF0 380 are under the control of a controller 385. The controller 385 receives segment type indication on bus 397. It also receives on bus -390 the Tag value as read out from the Label RAM 365, and on bus 348 the updated count value produced by the counter 346. It also has the possibility of input of externally generated labels on bus 399. When appropriate, the controller issues: (i) to the Count RAM 340 a Write command on line 341; (ii) to the counter 346 a Load command on line 342, an Increment command on line 343, a Decrement command on line 344, and a Clear command on line 345; (ϋi) to the TAG_FIF0380 a Read command on line 370, a Write command on line 391, and Tag out on bus 372; (iv) to the LabelJAM 365 a Write command on line 360, a data word of all-zeros on bus 366; and (v) to the Tag_latch 395 a clear command on line 371 and Load command on line 394. Also, when appropriate, the controller 385 outputs the error code on bus 386 and the New_output indication on line 387. The controller can be a micro-programed processor with a wide choice of specific embodiments. The processor may comprise an EPS 448 or a number of these cascaded in parallel. Its functions can be achieved by executing a program described by the following pseudo-code (which is somewhat similar to the languages Pascal and C): repeat {CONTROL LOOP} repeat {do nothing} until new_input; {SYNCHRONIZATION ON} clear (new_input); {LINE 398} load (counter); case segment type of BOM: begin if( (counter=0) and (tag=0)) then begin error_code:=0; read(tag_fifo,data); write(label_ram,data); increment(counter); write(counter_ram,counter); load(tag_latch) end else if( (counteroO) and (tagoO)) then begin error_code:=0; increment(counter); ' * write(coύnter_ram,counter); load(tag_latch); end else begin err r_code:=1; clear(tag_latch); end; end; COM: begin if( (counteroO) and (tagoO)) then begin ' error_code:=0; load(tag_latch); end else begin error_code:=2; . clear(tag_latch); end; end; EOM: begin if( (counteroO) and (tagoO)) then begin load( tag_latch ) ; decremen ( counter ) ; wr i te ( coun ter_r am , counter ) ; if(counter=0) then begin write(tag_fifo,tag); write(label_ram,0); error sode:=0; end; end * * else begin " error_code:=3; - clear(tag_latch); end; end; {END OF CASE} pulse(newjDutput); until forever; A flow diagram of the program is illustrated in Figures 10A to 10D. The operation of the tag server and actions of its controller 385 may be explained more fully by reference to Figure 7 for the case of a VCI TAG server i.e. the server 317 of Figure 6. In this case the Key 350 appearing on buses 355 and 356 is then the VCI as it has come in the header of the current segment. If the segment is a COM (continuation of message), the Label read out from the Label RAM 365 is non-zero, and previously stored for that VCI. The Count read-out of the Count RAM 340 is also non-zero. The .controller checks if the read out Label and Count are non-zero. If either or both were zero that would signify an error condition and the controller would signal it by producing an error code on bus 386. If the VCIJTAG is valid, the controller issues a Load command on the line 394 and the VCIJTAG is latched into the Tag_latch 395. . When the segment is a BOM (beginning of message) there may or may not be a VCIJTAG for it. If there is, then the Count and Label, as read out, are non-zero. In that case the Controller will latch the VCIJTAG into the Tag_Latch 395 as before. It will also put an Increment command on the line 343 which increase the Count of the counter 346 by one. Following this the controller will put a Write command on the line 341 to write the updated Count into the Count RAM 340. If there is no VCIJTAG for the given VCI, then the Count and Label, as read out are zero, and a VCIJTAG has to be assigned. Assigning of the VCIJTAG occurs from the TAG_FIF0 380 on command from the controller. Assuming the TAG_FIF0 380 is not empty, the next in line unused VCIJTAG is read out by command on line 370 onto bus 366, and by command on line 360, it is written into the Label RAM 365 which also makes the VCIJTAG appear on the bus 389. The valid VCIJTAG is now latched into the Tag_Latch 395. Also the Count is incremented making it one, and written into the Count RAM 340 as before. Should the TAG_FIF0380 be empty when a BOM arrives and assigning of a tag is necessary, then no assignment can be made. It will be an error condition that will result in the loss of that message. The numerical size of the TAG space can be selected so as to ensure that the possiblity of ' running into depletion is of negligible probability. Finally, when the segment is an EOM (end of message), the conditions and actions in reading the Label RAM 365 are the same as for a COM. But there is the possibility that the tag becomes free and is returned to the pool. The controller 385 puts a Decrement command on the line 344 to the counter 346. This reduces the Count by one and the updated Count is written into the Count RAM 340. If the resulting Count equals zero then the Tag has become free. The tag is latched into the Tag_Latch 395 and also by Write command on the line 391 written into the TAG_FIFO 380. Following this, an all-zeros tag is put by the controller on the bus 366 and by Write command on line 360 written into Label RAM 365. The operation of the other two servers in Figure 6, the M_ID_IN TAG server 318 and the M_ID_0UT server 326, are similar and can be understood by analogy. The M_ID_0UT server 326 differs from the other two only in that M_ID_0UT labels are limited in, their total number by the number allocated to the server * by an external manager (not shown) and not the size of space. Labels can be brought in from an outside source via label in bus 399 and into the TAG_FIF0 380 via bus 372. Also the Key, comprised of VCIJTAG and M_ID_TAG, is unique for a particular datagram and the Count will be one for a particular Key following BOM and go back to zero, following EOM. Thus the function of the Count RAM 340 is nil and may be dispensed with in this case. The VCIJDUT server differs from the M_ID_0UT server only that it does not have a pool of labels and therefore does not require the service of a TAG_FIF0. Also, in common with the M_ID_0UT server, it does not require a COUNT RAM. A VCIJDUT is determined by the system of Figure 5 on entry of BOM. It is passed to the Controller of the VCIJDUT server via bus 399 as shown in Figure 7. The Controller writes it via bus 366 into label RAM 365. On arrival of EOM, that address location is zeroed, again via bus 366. Although three types of router, Types I, II and III have been described, it will be appreciated that a generic embodiment is possible. By appropriate change of executable programs in the controllers a generic router can be changed from one type to another. It will also be appreciated that the overall system of Figure 1 can be altered materially and still achieve the same functions. It has already been noted that the connectionless zero level domains can be dispensed with by connecting the end equipment directly to the routers, one pair of routers for each separate end equipment but this is less favourable in that it requires a substantially larger number of routers. The zero level domains act as concentrators, allowing one router to serve a large number of equipments while at the same time providing a connectionless switched service for intradomain communication. It will also be appreciated that the concentration function can also be achieved by a connection-oriented domain with a simplified routing function from the separate end equipments, if all connectionless messages are sent to a single router. The router then approximates the central connectionless server. The connection-oriented concentrator does not itself provide any connectionless intradomain communication, and the router functionality has to be accordingly enlarged to provide it. Although a specific context of network standards and specific embodiment of the invention within that context are shown and described herein, this is merely for the purpose of illustration. Those skilled in the art will be able to devise other arrangements which, although not specifically shown or described herein, embody those principles and which do not depart from their spirit and scope. For example, the system described above is in the context of segmented transfer of datagrams, but it is applicable with some deletions to the less demanding context of unsegmented transfer. Also, for example, particular types of hardware such as random access memories, multiplexers, priority encoders, FIFO memories etc. are described but these could be replaced by more elementary or specially constructed components to perform similar functions.

Claims: CLAIMS : 1. A network for routing datagrams which include at least one segment, the network comprising at least one segment switching means (101...104), and a plurality of routers (111...130) connected between the switching means (101 104) and a plurality of terminals (91 98) and adapted to process data in a datagram transmitted from a first terminal (91) so as to pass said datagram from a first router (111) to a second router (118) via said switching means (101...104) and pass said datagram from said second router (118) to a second terminal (96). 2. A network as claimed in claim 1, comprising a plurality of segment switching means (101...104) connected by said routers (111...130) so as to correspond to respective hierarchical segment transfer levels, switching means (101,102) of a first level being coupled to said terminals and switching means (103) of a second level, which is coupled to at least two switching means (101,102) of said first level. 3. A network as claimed in claim 2, wherein one switching means (101) of said first level is connected to another switching means of said first level. 4. A network as claimed in claim 3, wherein said switching means (101...103) are all coupled to a switching means (103,104) of a higher segment transfer level, except the switching means (104) of the highest segment transfer level. 5. A network as claimed in any one of the preceding claims, wherein a datagram is transferred through said network on the basis of a final destination address of said datagram. " 6. A network as claimed in any one of the preceding claims, wherein said terminals are connected in at least one group by at least one area network means (81...85) connected to said switching means (101...104) by said routers (111...130). 7. A network as claimed in claim 5, wherein said routers (111...130) comprise: first means (503,504,505,506,507,541) for receiving said datagrams and accessing said destination address from said datagram; second means (501) responsive to said first means for determining output connection data (VCIJDUT) on the basis of said destination address; and third means (502,505,508,509,511,512,513,540,542,544, 543) for including said output connection data (VCIJDUT) in said datagram; said datagram being routed in said network on the basis of said output connection data (VCIJDUT) after,, being outputted from ' said * router. 8. A network as claimed in claim 7, wherein said second means (501) includes: memory circuits (221...226) having connection data (VCIJDUT) and selection data stored therein; fourth means (201) for dividing said destination address into fields and applying said fields to respective ones of said memory circuits (221...226) to access a plurality of corresponding connection data and selection data; and fifth means (250) for selecting said output connection data (VCIJDUT) from said plurality of connection data on the basis of said selection data. 9. A network as claimed in claim 8, wherein said selection data correspond to a priority code such that said connection data is selected on a priority basis corresponding to said hierarchical segment transfer levels. 10. A network as claimed in claim 7, 8 or 9, wherein said third means (502,505,508,509,511,512,513,540,542,544,543) includes message means (502) for determining output message data (M_ID_0UT) for said at least one segment of said datagram on the basis of input connection data (VCI_IN) and input message data (M_ID_IN) accessed from said at least one segment by said first means (503,504,505,506,507,541); said third means (502,505,508,509,511,512,513,540,542, 544,543) including said output message data (M_ID_0UT) in said at least one segment; said output message data (M_ID_0UT) indicating said at least one segment belongs to said datagram on output from said router. 11. A network as claimed in claim 10, wherein said message means (502) further determines said output connection data (VCIJDUT) for subsequent segments o'f a datagram after a first segment thereof has been processed by said router, said output connection data (VCIJDUT) being determined on the basis of said input connection data (VCI_IN) and said input message data (M_ID_IN); said third means (502,505,508,509,511,512,513,540,542, 544,543) including said output connection data (VCIJDUT) in said subsequent segments. 12. A network as claimed in claim 11, wherein said message means (502) includes at least two tag serving means (317 and 323) which are adapted for access by said input connection data (VCI_IN) and said - input message data (M_ID_IN), respectively, to output a connection tag and a message tag, respectively, said output message data (M_IDJDUT) and said output connection data (VCIJDUT) being determined on the basis of said tags. 13. A network as claimed in claim 12, including further tag serving means (325,326) responsive to said tags for outputting said output connection data -(VCIJDUT) and said output message data (M_ID_0UT), wherein said tag serving means (317,318,325,326) comprise: an available tag store (380) for storing available tags, a memory (365) for storing a current tag for a datagram, and means (340,346,385) for determining when the current tag is no longer required and returning said current tag to said tag store (380). 14. A network as claimed in any one of the preceding claims, wherein said routers process said datagrams in real time. 15. A router for a network for routing datagrams having at least one segment, said router comprising: first means (503,504,505,506,507,541) for receiving said datagram and accessing said destination address from " said datagram; second means (501) responsive to said first means for determining output connection data (VCIJDUT) on the basis of said destination address; and third means (502,505,508,509,511,512,513,540,542,544, 543) for including said output connection data (VCIJDUT) in said datagram; said datagram being routed in said network on the basis of said output connection data (VCIJDUT) after being outputted from said router. 16. A router as claimed in claim 15, wherein said second means (501) includes: memory circuits (221...226) having connection data (VCIJDUT) and selection data stored therein; fourth means (201) for dividing said destination address into fields and applying said fields to respective ones of said memory circuits (221...226) to access a plurality of corresponding connection data and selection data; and fifth means (250) for selecting said output connection data (VCIJDUT) from said plurality of connection data on the basis of said selection data. 17. A router as claimed in claim 16, wherein said selection data correspond to a priority code such that said connection data is selected on a priority basis corresponding to said hierarchical segment transfer levels. 18. A router as claimed in claim 15, 16 or 17, wherein said third means (502,505,508,509,511,512,513,540,542,544,543) further includes message means (502) for determining output message data (M_ID_0UT) for said at least one segment of said datagram on the basis of input connection data (VCI_IN) and input message data (M_ID_IN) accessed from said at least one segment by said first means (530,504,404,506,507,541); said third means (502,505,508,509,511,512,513,540,542, 544,543) including said output message data (M_ID_CDUT) indicating said at least one segment belongs to said datagram on output from said router. 19. A router as claimed in claim 18, wherein said message means (502) further determines said output connection data (VCIJDUT) for subsequent segments of a datagram after a first segment thereof has been processed by said router, said output connection data (VCIJDUT) being determined on the basis of said input connection data (VCI_IN) and said input message data (M_ID_IN); said third means (502,505,508,509,511,512,513,540,542, 544,543) including said output connection data (VCIJDUT) in said subsequent segments. 20. A router as claimed in claim 19, wherein said message means (502) includes at least two tag serving means (317 and 318) which are adapted for access by said input connection data (VCI_IN) and said input message data (M_ID_IN), respectively, to output a connection tag and a message tag, respectively, said output message data (M_ID_0UT) and said output connection data (VCIJDUT) being determined on the basis of said tags. 21. A router as claimed in claim 20, including further tag serving means (325,326) responsive to said tags for outputting said output connection data (VCIJDUT) and said output message data (M_ID_0UT), wherein said tag serving means (317,318,325,326) comprise: an available tag store (380) for storing available tags, a memory (365) for storing a current tag for a datagram, and means (340,346,385) for determining when the current tag is no longer required and returning said current tag to said tag store (380). 22. A router as claimed in any one of claims 15 to 21, wherein said datagrams are processed in real time. 23. A method of routing datagrams in a network having at least one segment switching means (101...104), and a plurality of routers (111...130) connected between the switching means (101...104) and a plurality of terminals (91...98), said method comprising processing data in a datagram transmitted from a first terminal (91) so as to pass said datagram from a first router (111) to a second router (118) via said switching means (101...104) and pass said datagram from said second router (118) to a second terminal (96). 24. A. method of routing datagrams as claimed in claim 23, comprising transferring a datagram through said network on the basis of a final destination address of said datagram. 25. A method of routing datagrams as claimed in claim 24, further comprising: accessing said destination address from said datagram, determining output connection data (VCIJDUT) on the basis of said destination address, including said output connection data (VCIJDUT) in said datagram, and routing said datagram in said network on the basis of said output connection data (VCIJDUT) after said datagram is outputted from said router. 26. A method of routing datagrams as claimed in claim 25, further comprising dividing said destination address into fields, applying said fields to respective memory circuits having connection data and selection data stored therein to access a plurality of corresponding connection data and selection data, and selecting output connection data (VCIJDUT) from said plurality of connection data on the basis of said selection data. 27. A method of routing datagrams as claimed in claim 25 or 26, wherein said selection data correspond to a priority code such that said connection data is . selected on a •* * * * priority basis corresponding to hierarchical segement transfer levels, which comprise respective segment switching means (101 104) connected by said routers (111...130). 28. A method of routing datagrams as claimed in claims 25, 26 or 27, further comprising accessing input connection data (VCI_IN) and input message data (M_ID_IN) from said at least one segment, determining output message data (M_ID_0UT) on the basis of said input connection data (VCI_IN) and said input message data (M_ID_IN), and including said output message data (M_ID_0UT) in said at least one segment, said output message data (M_ID_0UT) indicating said at least one segment belongs to said datagram on output from said router. 29. A method of routing datagrams as claimed in claim 28, further including determining said output connection data (VCIJDUT) for subsequent segments of a datagram, after processing of a first segment thereof, on the basis of said 1 input connection data (VCI_IN) and said input message data 2 (M_ID_IN), and including said output connection data in said 3 subsequent segments. 4 5 30. A method of routing datagrams as claimed in claim 29, 6 further including accessing a connection tag and a message 7 tag from tag serving means (317,318) on the basis of said 8 input connection data (VCI_IN) and said input message data 9 (M_ID_IN), respectively, and determining said output message 10 data (M_ID_0UT) and said output connection data (VCIJDUT) on 11 the basis of said tags. 12 13 31. A method of routing datagrams as claimed in claim 30, 14 further including obtaining said output message data 15 (M_ID_0UT) and said output connection data (VCIJDUT) from 16 further tag serving means (325,326) on the basis of said 17 tags, wherein in said tag serving means (317,318,325,326) 18 available tags are stored in a tag store, a current tag for 19 a datagram is stored in a memory and- the current tag is • 20 returned * to the tag store when said datagram has passed 21 through said router. 22 23 32. A method of routing datagrams as claimed in any one of 24 claims 23 to 32, wherein the steps of the method are 25 performed in real time. 26 27 28 29 30 31 32 33 34 35 36 37 38

Inventors: BUDRIKIS ZIGMANTAS LEONAS, CANTONI ANTONIO, BUDRIKIS, ZIGMANTAS, LEONAS, CANTONI, ANTONIO
Applicants: BUDRIKIS ZIGMANTAS LEONAS, CANTONI ANTONIO, BUDRIKIS, ZIGMANTAS, LEONAS, CANTONI, ANTONIO
Application year: 1989
Main classification: H04L11
IPC codes: H04L12