Semiconductor chip and method of manufacturing it

Abstract: A power supply wiring arrangement of a semiconductor integrated circuit formed on a semiconductor chip (40), characterized by a) a plurality of pairs of metal bumps (44) formed on the semiconductor chip (40), b) a plurality of conductor strips (50) each extending between the bumps forming each of said pairs of metal bumps (44), and c) a plurality of thick-layer wiring strips (48) directly connected to selected ones of said metal bumps (44) and said conductor strips (50), said thick-layer wiring strips being substantially identical in material and in thickness to said metal bumps (44).

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor chip and, more particularly, to a power supply wiring arrangement of a semiconductor integrated circuit typically implemented by an emitter-coupled logic gate array fabricated on a semiconductor chip forming a large-scale integrated circuit, as well as to a method of manufacturing such a chip. SUMMARY OF THE INVENTION The present invention contemplates provision of an improved semiconductor chip eliminating the problems which would result from an increased integration density on a semiconductor large-scale integrated circuit chip. The present invention further contemplates provision of an improved semiconductor chip minimizing the irregularities in the levels of the supply voltages to the individual elementary cells of a semiconductor large-scale integrated circuit chip. The present invention further contemplates provision of an improved semiconductor chip in the form of an emitter-coupled logic gate array minimizing the irregularities in the levels of the supply voltages to the individual elementary cells of the gate array and eliminating the problems which would result from an increased integration density on a semiconductor large-scale integrated circuit chip. GB-A-2089121 discloses a power supply wiring arrangement of a semiconductor integrated circuit formed on a semiconductor chip, comprising a plurality of pairs of metal bumps formed on the semiconductor chip; a power supplying network for distributing electric power to components of said integrated circuit; said power supplying network comprising a plurality of conductor strips each extending between the bumps forming each of said pairs of metal bumps. According to the invention there is provided a semiconductor chip comprising, a substrate, a logic gate array comprising logic building blocks consisting of elementary cells arranged in parallel rows on the substrate between a pair of bonding pad areas at opposite edges of the chip; the rows of logic building blocks being spaced apart from each other to form parallel wiring channels between them; interconnections between the cells extending along the wiring channels, an insulator layer covering said interconnections; each of said pair of bonding pad areas comprising bonding pads with metal bumps spaced so as to form with pads of the other area a plurality of pairs of opposing metal bumps; main power supply conductor strips extending between and interconnecting each pair of metal bumps, the building blocks and main power supply conductor strips being arranged in such a manner that no cells are located below said strips; the main power supply conductor strips being connected to power distribution lines, characterised in that the power distribution lines are thick-layer wiring strips forming a layer underlying the power supply conductor strips; the thick-layer wiring strips are identical in material and thickness to the metal bumps; the thick-layer wiring strips are branched from the main power supply conductor strips and extend on and along the logic building blocks but not the wiring channels; and the thick layer wiring strips are formed on said insulator layer, the power supply conductor strips bridging the thick layer wiring strips so that there is a layer of air between each of the conductor strips and the insulator layer. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS The drawbacks of a prior art semiconductor integrated circuit chip of the nature to which the present invention appertains and the features and advantages of a semiconductor integrated circuit chip according to the present invention over such a prior art semiconductor chip will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals and characters designate similar or corresponding structures, elements and portions and in which: Fig. 1 is a plan view showing the general cell configuration and power supply wiring arrangement of a prior art emitter coupled logic gate array; Fig. 2 is a fragmentary plan view showing, to an enlarged scale, a portion of the prior art gate array shown enclosed by circle II in Fig. 1; Fig. 3 is a sectional view taken along line III-III in Fig. 2; Fig. 4 is a plan view showing the general cell configuration and power supply wiring arrangement of a preferred embodiment of a semiconductor chip according to the present invention; Fig. 5 is a fragmentary plan view showing, to an enlarged scale, a portion of the gate array shown enclosed by circle VIII in Fig. 4; and Fig. 6 is a sectional view taken along line XI - XI in Fig. 5. DETAILED DESCRIPTION OF THE PRIOR ART Drawbacks of a prior art semiconductor integrated circuit will be hereinafter described in more detail with reference to Fig. 1 which shows the general cell configuration and power supply wiring arrangement of a known emitter coupled logic gate array formed on a semiconductor large scale integrated circuit chip 10. The semiconductor integrated circuit thus formed on the large-scale integrated circuit chip 10 has peripheral bonding-pad areas 12 each having a series of wire bonding pads 14 arranged alongside the edge of the chip 10. On the circuit chip 10 are further provided a plurality of logic building blocks 16 arranged in parallel with each other to form wiring channels 18 therebetween and each composed of a series of elementary cells 20. On the logic building blocks 16 and wiring channels 18 are formed high-level and low-level power supply conductor strips 22 and 24 each of which extends at right angles to the logic building blocks 16 and wiring channels 18. The high-level power supply conductor strips 22 extend in parallel with each other between a pair of common high-level power supply leads 26 extending along one pair of parallel bonding-pad areas and each leading from particular one or two of the wire bonding pads 12 arranged along the pair of bonding pad areas. The low-level power supply conductor strips 24 extend in parallel with these high-level power supply conductor strips 22 and are arranged alternately to the high-level power supply conductor strips 22 so that each of the elementary cells 20 has its center portion crossed by a portion of a high-level power supply conductor strip 22 as will be better seen in Fig. 2. Fig. 2 is a fragmentary plan view showing, to an enlarged scale, a portion of the prior-art gate array shown enclosed by circle II in Fig. 1. Each of the low-level power supply conductor strips 24 is thus located adjacent end portions of adjacent two of the elementary cells 20 of each logic building block 16 so that each elementary cell 20 has its opposite end portions respectively crossed by portions of adjacent two of the low-level power supply conductor strips 24 as will be also better seen in Fig. 2. The elementary cells 20 forming the individual logic building blocks 16 are selectively connected together through interconnection lines extending underneath the elementary cells 20 and in the wiring channels 18, though not shown in the drawings. Interconnection lines selectively connecting the elementary cells 20 may also be formed in the toplevel layer including the high-level power supply conductor strips 22. In the prior-art emitter-coupled logic gate array thus formed on the large-scale integrated circuit chip 10, the logical swings between the high-level and low-level voltages used for the individual elementary cells 30 are significantly smaller than those used in logic gate arrays of other types. The absolute values of the logic levels used in the emitter-coupled logic array are thus determined on the basis of the high-level power supply voltage and, for this reason, the high-level power supply conductor strips 22 in particular must be fabricated with strict preciseness. The high-level power supply conductor strips 22 are thus laid out with a view to reducing the voltage drops through the conductor strips and are, for this purpose, formed to extend over the individual elementary cells 20. The high-level power supply conductor strips 22 included in the toplevel layer of the chip 10 can be formed with desired thicknesses and can be connected directly from the power-supply bonding pad or pads 12 to the individual elementary cells 20. On the other hand, the low-level power supply conductor strips 24 need not be fabricated with the preciseness required for the fabrication of the high-level power supply conductor strips 22 and are laid out to extend in part over the elementary cells 20 and in part below the high-level power supply conductor strips 22. The conductor strips 24 are formed by an inter-level layer underlying the toplevel layer including the high-level power supply conductor strips 22 where the low-level power supply conductor strips 24 cross the high-level power supply conductor strips 22. Where the low-level power supply conductor strips 24 cross the elementary cells 20, the conductor strips 24 are formed to extend over the elementary cells 20 to minimize the irregularities in the levels of the supply voltages to the individual elementary cells 20. It is now assumed that the design rules of the chip 10 are such that each of the elementary cells 20 has a length (X) of 300 microns and a pitch (Y) of 200 microns and that each of the high-level and low-level power supply conductor strips 22 and 24 has a width (W) of 50 microns. It is further assumed that the toplevel layer forming the high-level power supply conductor strips 22 is 3 microns thick and has a resistivity of 0.01 ohm/square and that a current of 10 mA is to be applied to each of the elementary cells 20. It is further assumed that there are ten elementary cells 20 located between the end point (indicated by sign "*" in Fig. 1) and the center point (indicated by sign "+" in Fig. 1) of the cell area of the chip 10. (Note that only six elementary cells 20 are shown for simplicity of illustration.) In this instance, the voltage drop in the length of high-level power supply conductor strip 22 extending over these ten elementary cells 20 is approximately 22 mV. To achieve a reasonable noise margin and an acceptable high-speed performance efficiency in an emitter-coupled logic gate array, it is imperative that the voltage drop through a single high-level power supply line be limited within a range of this order, that is, approximately 22 mV. Fig. 3 shows a cross sectional configuration of a portion of the large-scale integrated circuit chip 10 as taken along line III-III in Fig. 2. The prior-art large-scale integrated circuit chip 10 is shown including a semiconductor substrate 30, an inter-level conductor layer 32 forming interconnections for the elementary cells 20, and an insulator layer 34 of, typically, silicon dioxide underlying the toplevel layer including the high-level power supply conductor strips 22. The semiconductor substrate 30 is formed typically by a laminar structure consisting of a base layer of silicon and layers of insulator and diffusion selectively deposited thereon. The inter-level conductor layer 32 is formed by interconnection lines each having a width of, typically, 3 microns and is covered with the insulator layer 34. The insulator layer 34 underlies the toplevel layer forming the high-level power supply conductor strips 22 which extend transversely to the interconnection lines formed by the inter-level conductor layer 32. It is now assumed that the insulator layer 34 of silicon dioxide has a relative permittivity of 4 and is 2 microns thick. Each of the high-level power supply conductor strips 22 measuring 50 microns in width as above noted, the parasitic capacitance C p between one of the interconnection lines forming the inter-level conductor layer 32 and one of the high-level power supply conductor strips 22 included in the toplevel layer crossing the interconnection line is given, when the layers 22 and 32 are regarded as the parallel plates of a capacitor, as: C p = (50µm x 3µm)/2µm x 4 x ε o = 2.66 x 10 -3 pF where ε o stands for the permittivity of free space and is given as ε o = 8.854 x 10 -6 pF/µm. Considering that a single elementary cell 20 is crossed by a single high-level power supply conductor strip 22 and a single low-level power supply conductor strip 24 (which consists of two half-width strip portions) each having a width W of 50 microns, the total parasitic capacitance C T between the inter-level conductor layer 32 formed by a unit length 1mm (= 1000µm) of the interconnection line under consideration and the high-level power supply conductor strips 22 crossing the interconnection line is given as: C T = 1000µm/300µm x 2 x (2.66 x 10 -3 pF) ≈ 0.018 pF The capacitance value of this order is of paramount importance in an emitter-coupled logic gate array and it is thus strongly desired that the value be reduced as much as possible. In the meantime, there is a growing trend of the elementary cells of a logic gate array being scaled down and of the pitch distances of the elementary cells being reduced with a view to further improving the integration density of the array. In this connection, an imaginary large-scale integrated circuit chip may be taken into consideration in which the elementary cells in a logic gate array of the design described with reference to Fig. 1 is miniaturized by reducing the length X of each elementary cell to 150 microns and the pitch Y of each elementary cell to 100 microns. It may be herein assumed that, as a result of such improvement in the design rules of the logic array, the elementary cells which can be formed on a single chip is nine times larger in number than the elementary cells 22 provided in the logic gate array shown in Fig. 1. It may thus be considered that the numbers of the rows and columns of the elementary cells are each three times larger than those of the elementary cells 20 in the shown prior-art array and accordingly that there are thirty elementary cells located between the end and the center points of the cell area of the chip. In this instance, the voltage drop V in the length of high-level power supply conductor strip extending over these thirty elementary cells is approximately 93 mV. It is herein also assumed that the insulator layer 34 of silicon dioxide in such a circuit chip has a relative permittivity of 4 and is 2 microns thick and that each of the interconnection lines forming the inter-level conductor layer 32 is 3 microns wide. If each of the high-level power supply conductor strips 22 is 50 microns wide, the parasitic capacitance between one of the interconnection lines forming the inter-level conductor layer 32 and one of the high-level power supply conductor strips 22 forming the toplevel layer crossing the interconnection line equal the capacitance C p given by Equation 1, hence 2.66 x 10 -3 pF. Assuming further that a single elementary cell 20 is crossed by a single high-level power supply conductor strip 22 and a single low-level power supply conductor strip 24 each having a width W of 50 microns, the total parasitic capacitance C T between the inter-level conductor layer 32 formed by a unit length 1mm (= 1000µm) of the interconnection line under consideration and the high-level power supply conductor strips 22 crossing the interconnection line is given as: C T = 1000µm/150µm x 2 x (2.66 x 10 -3 pF) ≈ 0.035 pF From the above description it will be understood that notably increased ranges of voltage drops and inability of achieving desired noise margins result from the scaling down of emitter-coupled logic gate arrays of the prior-art design. The noise margin of an emitter-coupled logic gate array could be improved by the use of an increased logical swing between the high-level and low-level voltages for the individual elementary cells. This expedient will however prove unacceptable because of the fact that the use of the increased logical swing in a large-scale integrated circuit may result in irregularities in the levels of the supply voltages to the individual elementary cells and may give rise to an increase in the delay time in the operation of each of the elementary cells provided in the integrated circuit. An increase in the delay time in the operation of an elementary cell may also be caused by the increase in the parasitic capacitance per unit length of an interconnection line. This problem implements another important factor to be taken into account in increasing the integration density of a large-scale integrated circuit chip while maintaining the potential performance characteristics of the circuit. In the description regarding the imaginary large-scale integrated circuit chip, it has been assumed that the elementary cells in a prior-art logic gate array of the design described with reference to Fig. 1 is miniaturized by reducing the length X and pitch Y of each elementary cell with the width W of each of the high-level and low-level power supply conductor strips and maintained (at 50 microns). In the case of this arrangement of a large-scale integrated circuit, there is another problem that the toplevel layer including the high-level power supply conductor strips has lesser areas allowing interconnection lines to extend between the high-level power supply conductor strips 22. This is objectionable from the view point of providing an increased number of interconnection lines in a large-scale integrated circuit with an increased integration density. The parasitic capacitance between the inter-level conductor layer forming interconnections and the insulator layer underlying the high-level power supply conductor strips could be reduced by otherwise increasing the thickness of the latter. Where each of the length and pitch of each of the elementary cells is reduced to one half as in the described imaginary large-scale integrated circuit chip, the increase in the voltage drop due to such measurement of each elementary cell could be offset by doubling the thickness of the insulator layer underlying the high-level power supply conductor strips. Various difficulties will however be encountered in forming such a thick insulator layer by the semiconductor process techniques presently available. Accordingly, it is an important object of the preferred embodiment of the present invention to provide an improved semiconductor chip eliminating the problems which would result from an increased integration density on a semiconductor large-scale integrated circuit chip. It is another import object of that embodiment to provide an improved semiconductor chip minimizing the irregularities in the levels of the supply voltages to the individual elementary cells of a semiconductor large scale integrated circuit chip. It is still another import object of that embodiment to provide an improved semiconductor chip in the form of an emitter coupled logic gate array minimizing the irregularities in the levels of the supply voltages to the individual elementary cells of the gate array and eliminating the problems which would result from an increased integration density on a semiconductor large scale integrated circuit chip and to devise an advantageous method of manufacturing such a chip. PREFERRED EMBODIMENTS OF THE INVENTION Fig. 4 shows the general cell configuration and power supply wiring arrangement of the preferred embodiment of a semiconductor chip according to the present invention. The semiconductor chip herein shown is provided in the form of an emitter coupled logic gate array fabricated on a semiconductor large scale integrated circuit chip which is represented by reference numeral 60. The large-scale integrated circuit chip 60 implementing the preferred embodiment of the present invention is assumed to be electrically connected to external circuit components by a wire bonding process. Thus, the semiconductor integrated circuit formed on the large-scale integrated circuit chip 60 has peripheral bonding-pad areas 12 each having a series of wire bonding pads 14 arranged alongside each edge of the chip 60. On selected ones of these wire bonding pads 14 are mounted a set of metal bumps 44 a to 44 e located alongside one edge of the chip 60 and a set of metal bumps 44 a ' to 44 e ' located the alongside the opposite parallel edge of the chip 60. Thus, the emitter-coupled logic gate array formed on the chip 60 herein shown has a plurality of pairs of metal bumps 44 a and 44 a '; 44 b and 44 b '; 44 c and 44 c '; 44 d and 44 d ' and 44 e and 44 e ' as shown. The alternative pairs of bumps 44 a and 44 a '; 44 c and 44 c ' and 44 e and 44 e ' are used as high-level power supply terminals for the emitter-coupled logic gate array and the alternative pairs of bumps 44 b and 44 b ' and 44 d and 44 d ' are used as low-level power supply terminals for the gate array. The metal bumps 44 a to 44 e and 44 a ' to 44 e ', shown hatched in Fig. 4, are typically of gold, copper or solder and are formed on the chip 60 preferably during the semiconductor wafer processing operation to fabricate the emitter-coupled logic gate array on the chip 60. The metal bumps 44 a to 44 e and 44 a ' to 44 e ' are formed on the selected ones of the bonding pads 14 typically by a thermocompression bonding process. On the semiconductor large-scale integrated circuit chip 60 shown in Fig. 4 are further provided a plurality of logic building blocks 16 arranged in parallel rows between one pair of parallel bonding-pad areas 12 of the chip 60 and spaced apart from each other to form parallel wiring channels 18 between the individual blocks 16. Each row of logic building blocks 16 consists of elementary cells 20 arranged in series between the other pair of parallel bonding-pad areas 12 as partly shown to an enlarged scale in Fig. 5. The elementary cells 20 are connected together through interconnection lines extending underneath the elementary cells 20 and in the wiring channels 18, though not shown in the drawings. In the semiconductor large-scale integrated circuit chip 60, there are further provided main power supply lines implemented by conductor strips 62 extending between the metal bumps 44 a and 44 a '; 44 b and 44 b '; 44 c and 44 c '; 44d and 44 d '; and 44 e and 44 e '. The main power supply conductor strips 62 extending between the metal bumps 44 a and 44 a '; 44 c and 44 c '; and 44 e and 44 e ' provide main high-level power supply lines in the large-scale integrated circuit chip 60 and the main power supply conductor strips 62 extending between the metal bumps 44 b and 44 b '; and 44 d and 44 d ' provide main low-level power supply lines in the chip 60. The main power supply conductor strips 62 thus connecting the pairs of metal bumps 44 a to 44 e and 44 a ' to 44 e ' extend perpendicularly to the logic building blocks 16 and are bonded to local power distribution lines 64 implemented by thick-layer wiring strips forming a layer underlying the layer of the main power supply conductor strips 62. These local power distribution lines 64 are preferably formed concurrently with the formation of the metal bumps 44 a to 44 e and 44 a ' to 44 e ' on the semiconductor chip 60. The main power supply conductor strips 62 are thermocompression bonded to these local power distribution lines 64 and to the metal bumps 44 a to 44 e and 44 a ' to 44 e ' during the semiconductor wafer processing operation to fabricate the emitter-coupled logic gate array on the chip 60. Each of the logic building blocks 16 is composed of a row of three elementary cells 20 located between adjacent two of the main power supply conductor strips 64. It may be herein noted that there are no elementary cells 20 located below the main power supply conductor strips 62 so that the elementary cells 20 provided on the chip 60 are free from the mechanical stresses that will be created when the main power supply conductor strips 62 are bonded to the local power distribution lines 64 during wire bonding processing. Each of the local power distribution lines 64 thus branched perpendicularly from the main power supply conductor strips 62 extends on and along one of the logic building blocks 16 and is electrically connected to selected ones of the elementary cells 20 of the logic building block 16 along which the local power distribution line 64 extends. The local power distribution lines 64 are thus electrically connected through the main power supply conductor strips 62 to the pairs of metal bumps 44 a to 44 e and 44 a ' to 44 e '. In this instance, the local power distribution lines 64 connected through the main power supply conductor strips 62 to the alternate pairs of metal bumps 44 a and 44 a '; 44 c and 44 c ' and 44 e and 44 e ' are used as high-level power distribution lines and the local power distribution lines 64 connected through the conductor strips 62 to the alternative pairs of leads 44 b and 44 b ' and 44 d and 44 d ' are used as low-level power distribution lines. The local power distribution line 64 which extends on each of the logic building blocks 16 is thus used either as the high-level power distribution line or as the low-level power distribution line. Between adjacent two of the main power supply conductor strips is provided a column of high-level and low-level power distribution lines 64 which extend alternately from the high-level and low-level power supply main power supply conductor strips 62. Thus, the high-level and low-level power distribution lines 64 appear alternately on the logic building blocks 16 extending between the high-level power supply main conductor strip 62 intervening between the pair of high-level power supply metal bumps 44 a and 44 a ', 44 c and 44 c ' or 44 e and 44 e ' and the low-level power supply conductor strip 62 intervening between the pair of low-level power supply leads 44 b and 44 b ' or 44 d and 44 d '. It may be noted that the low-level power distribution lines for the logic building blocks 16 having the overlying high-level power distribution lines 64 and the high-level power distribution lines for the logic building blocks 16 having the overlying low-level power distribution lines 64 lines are formed by another inter-level layer (not shown) underlying the inter-level layer forming the local power distribution lines 64 herein shown. It may be further noted that the conductor strips forming the local power distribution lines 64 herein shown extend along and overlies the respectively associated ones of the logic building blocks 16 and are not located on the parallel wiring channels 18 between the individual logic building blocks 16. In the absence of the local power distribution lines 64 on the wiring channels 18, there are no parasitic capacitances added to the interconnection lines extending in the wiring channels 18. The main power supply conductor strips 62 may be bonded to the metal bumps 44 a to 44 e and 44 a ' to 44 e ' and the local power distribution lines 64 with use of a lead carrier similar to that used in the tape automated bonding process. In this instance, the lead carrier may be removed from the chip 60 on completion of the thermocompression bonding of the main power supply conductor strips 62 but this is not an essential requirement in fabricating a conductor strip according to the second preferred embodiment of the present invention. It may be noted that the lead carrier to be used in this thermocpmpression bonding process is fabricated separately of the semiconductor wafer processing steps and has apertures where the conductor strips 62 are to be bonded to the bumps and local power distribution lines. Fig. 6 shows a cross sectional configuration of a portion of the large-scale integrated circuit chip 60 taken along line XI-XI in Fig. 5. The large-scale integrated circuit chip 60 is shown comprising a semiconductor substrate 30, an inter-level conductor layer 32 forming interconnections for the elementary cells 20, and an insulator layer 34 of, typically, silicon dioxide. The main power supply conductor strips 62 bridge the local power distribution lines 64 which are herein shown by phantom lines and thus extend over the insulator layer 34 so that there is formed a layer of air 66 between each of the conductor strips 62 and the insulator layer 34. The metal bumps 44 are herein assumed to be formed to a thickness of 20 microns and, accordingly, the layer of air 66 formed between the insulator layer 34 and the main power supply conductor strips 62 has a thickness (T) of 20 microns which is assumed to be the thickness of the local power distribution lines 64 which are formed concurrently with the formation of the metal bumps 44 a to 44 e and 44 a ' to 44 e '. The semiconductor substrate 30 is formed typically by a laminar structure comprising a base layer of silicon and layers of insulator and diffusion selectively deposited thereon. The interconnection lines formed by the inter-level conductor layer 32 are directed in crossing relationship to the main power supply conductor strips 62 and are assumed to measure 3 microns in width. The insulator layer 34 of silicon dioxide overlying this inter-level conductor layer 32 is formed to a thickness of 2 microns and is assumed to have a relative permittivity of 4. Each of the main power supply conductor strips 62 is assumed to have a width of 60 microns, a thickness of 60 microns and a resistivity of 0.005 ohm/square. It is further assumed that the design rules of the large-scale integrated circuit chip 60 herein shown are also such that each of the elementary cells 20 has a length X of 150 microns and a pitch Y of 100 microns. It is further assumed that there are a total of 60 rows of logic building blocks 16 on the semiconductor chip 60 although only 13 rows of logic building blocks are shown in Fig. 7 for simplicity of illustration and that a current of 10 mA is to be applied to each of the elementary cells 20. Thus, each of the main power supply conductor strips 62 such as for example, the high-level main power supply conductor strip 62 extending between the metal bumps 44 c and 44 c ' is required to supply current to a total of ninety (= 3 x 2 x 60/4) elementary cells 20 located between the end point (indicated by sign "*" in Fig. 4) and the center point (indicated by sign "+" in Fig. 4) of the cell area of the chip 60. In this instance, the voltage drop _V in the length of main power supply conductor strip 62 extending over these ninety elementary cells 20 is approximately 12 mV. This value of the voltage drop _V is higher than that of the voltage drop _V caused in the first preferred embodiment of the present invention, the increase in the voltage drop having resulted from the absence of the thick-layer wiring strips between the insulator layer 34 and the main power supply conductor strips 62. In view, however, of the fact that the local power distribution lines 64 are formed by thick-layer wiring strips, the voltage drop _V of 12 mV through the main power supply conductor strip 62 is acceptable for practical purposes. In the arrangement shown in Fig. 4, the parasitic capacitance C p between one of the interconnection lines forming the inter-level conductor layer 32 and the high-level main power supply conductor strip 62 crossing the interconnection line is given as: C p = 1/(1/C s + 1/C a ) where C s is the capacitance resulting from the insulator layer 34 and C a is the capacitance resulting from the layer of air 66. Each of the main power supply conductor strips 62 measuring 60 microns in width as above noted, the parasitic capacitance C s resulting from the insulator layer 34 is calculated, when the layer 32 and the layer forming the conductor strip 62 are regarded as the parallel plates of a capacitor, as: C s = (60µm x 3µm)/2µm x 4 x ε o = 3.187 x 10 -3 pF The capacitance C a resulting from the layer of air 66 is calculated as C a = (60µm x 3µm)/20µm x 1 x ε o = 7.969 x 10 -5 pF The parasitic capacitance C p is thus given as C p = 1/{1/(3.187 x 10 -3 ) + 1/(7.969 x 10 -5 )} = 7.77 x 10 -5 pF Considering that the main power supply conductor strip 62 under consideration is associated with three elementary cells 20 each having the length (X) of 150 microns and per se has a width of 60 microns, the total parasitic capacitance C T between the inter-level conductor layer 32 formed by a unit length lmm (= 1000µm) of the interconnection line under consideration and the main power supply conductor strip 62 crossing the interconnection line is given as: C T = 1000µm/(150µm x 3 + 60µm) x (7.77 x 10 -5 pF) = 0.00015 pF It will be understood that the capacitance value of the order given by this Eq. 8 approximately equals 0.4 per cent of the value of 0.035 pF given by Eq. 3, offering 99.6 per cent of improvement over the described prior-art semiconductor integrated circuit. Actually associated with an interconnection line included in the interlevel conductor layer 32 are not only the parasitic capacitance formed between the interconnection line and the main power supply conductor strip 62 crossing the line but the capacitance formed between the particular interconnection line and each of the overlying and underlying interconnection lines extending in crossing relationship to the former. In the wiring arrangement of a prior-art large-scale integrated circuit chip, the former parasitic capacitance is far larger than the latter and, in addition, increasing the integration density of a large-scale integrated circuit chip may make it difficult to provide the wiring channels between the logic building blocks on the large-scale integrated circuit chip. In this preferred embodiment of the present invention, the parasitic capacitance formed between the interconnection line and the main power supply conductor strip 62 is reduced to approximately 4 per cent of that in the prior-art semiconductor integrated circuit as has been noted and practically can be disregarded at least in respect of the inter-level conductor layer closest to the layer of the power supply lines. As will have been understood from the foregoing description, a semiconductor chip according to the present invention is characterized inter alia by the power supply wiring arrangement in which conductor strips fabricated by a process independent of the wafer processing operation to fabricate a large-scale integrated circuit on a semiconductor chip are bonded to the metal bumps and thick-layer wiring strips formed on the chip during the wafer processing operation. By virtue of this power supply wiring arrangement, the resistances in the power supply lines to the individual elementary cells on the large-scale integrated circuit chip can be reduced significantly with consequent reduction in the voltage drops in a high-density, large-current integrated circuit and accordingly in the parasitic capacitances associated with the interconnection lines in the inter-level conductor layer. A semiconductor chip according to the present invention is further advantageous in that the number of the main power supply lines can also be reduced significantly so that there can be provided ample spaces for the wiring channels to accommodate an increased number of interconnection lines in a large-scale integrated circuit chip having an increased integration density. It may also be added that, because of the significant reduction in the voltage drops in the supply power and in the parasitic capacitance associated with the interconnection lines in an inter-level conductor layer, a large-scale integrated circuit chip carrying a semiconductor integrated circuit according to the present invention provides a sufficient range of noise margin and permits formation of an internal circuits having an increased ability to activate loads on the chip with a current of the order used in a high-speed large-scale integrated circuit chip typically forming an emitter-coupled logic gate circuit.

Claims: A semiconductor chip comprising a substrate, a logic gate array comprising logic building blocks (16) consisting of elementary cells (20) arranged in parallel rows on the substrate between a pair of bonding pad areas (12) at opposite edges of the chip (60); the rows of logic building blocks being spaced apart from each other to form parallel wiring channels (18) between them; interconnections (32) between the cells (16) extending along the wiring channels, an insulator layer (34) covering said interconnections; each of said pair of bonding pad areas comprising bonding pads (14) with metal bumps (44i) spaced so as to form with pads of the other area a plurality of pairs of opposing metal bumps; main power supply conductor strips (62) extending between and interconnecting each pair of metal bumps, the building blocks and main power supply conductor strips being arranged in such a manner that no cells (20) are located below said strips; the main power supply conductor strips being connected to power distribution lines (64), characterised in that the power distribution lines (64) are thick-layer wiring strips forming a layer underlying the power supply conductor strips; the thick-layer wiring strips are identical in material and thickness to the metal bumps; the thick-layer wiring strips are branched from the main power supply conductor strips and extend on and along the logic building blocks but not the wiring channels (18); and the thick layer wiring strips are formed on said insulator layer, the power supply conductor strips bridging the thick layer wiring strips so that there is a layer of air between each of the conductor strips and the insulator layer. A method of manufacturing a semiconductor chip as claimed in Claim 1, characterised by including the step of forming the thick layer wiring strips concurrently with and from the same material as the metal bumps.

Inventors: MISAWA HIROYUKO, MISAWA, HIROYUKO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: H01L23
IPC codes: H01L23, H01L21, H01L27