FREQUENCY SYNTHESISERS

Abstract: A frequency synthesiser for synthesising a prescribed frequency comprising a digital detector and analogue sample-and-hold detector arranged wherein the digital detector is disabled when the synthesiser has been tracked in a feedback loop to be at or near the prescribed frequency.

Description: FREOUENCY SYNTHESISERS The present invention relates to Frequency Synthesisers and more particularly to Synthesisers including phase locking. A signal having a particular frequency may be synthesised digitally. Synthesisers have a local oscillator (L.O.) and may include a programmable or other divider, and the output of the local oscillator is locked in-phase to a reference source (typically a crystal type device the output of which may be divided by a reference divider). The local oscillator typically operates at several Megahertz or even Gigahertz whilst the frequency of the reference source is usually of the order of a few Kilohertz. Divided signals can then be phase compared in a phase detector which gives an output indicative of the phase imbalance of the divided signals. This allows frequency comparison by a digital function and so provides phase up or phase down error signal for use in controlling the local oscillator via an alteration of the applied voltage to a varactor diode. A particular end product of such a frequency synthesiser is in the tuning circuit of a radio or television receiver. Conventionally, the phase detector is part of a phase and frequency comparator including a digital phase detector and an analogue phase detector. The digital detector has advantages in high frequency applications in which output pulses produced thereby are used to drive a .charge pump circuit feeding or draining .an integrating capacitor whose voltage is used to control a voltage dependant resonance element, such as a varactor diode, of a voltage controlled oscillator (VCO). Digital phase detectors are inherently noisy and such method of VCO control can lead to considerable jitter on the output of the synthesiser. It is an object of such frequency synthesisers to achieve a very pure L.O. signal, that is one with a low sideband spectrum whereby accurate frequency locking can be achieved. Sidebands generated are of either a periodic nature caused by comparison frequency etc. leaking onto the varactor line, or fundamental system noise. It is an object of the present invention to reduce the problems of sideband generation associated with the phase detectors in the synthesis loop. According to the present invention there is provided a frequency synthesiser having a phase locked loop circuit including phase detector means, a digital phase detector and an analogue sample-and-hold detector where to first and second signals are applied for phase comparison, and control means for operating the detectors in tandem while a relatively large phase difference exists between the first and second signals, and for disabling the digital phase detector when a leasser phase difference is detected, the lesser phase difference being indicative of the loop approaching lock. The analogue sample-and-hold phase detector may comprise a capacitor, current sources for charging and draining the capacitor in accordance with phase errors fed thereto, an amplifier to a first input of which the voltage on the capacitor is applied, a feedback path between the output of the amplifier and a second input thereto, and a second capacitor between the output of the amplifier and ground, the first capacitor serving to integrate the error signals fed thereto and the second capacitor serving to integrate the output from the amplifier, whereby the detector has a linear output when the phase errors are within a predetermined range. An embodiment of the present invention will now be described with reference to the accompanying drawings in which:- Figure 1 is a schematic representation of a frequency synthesiser, Figure 2a, 2b and 2c illustrate respectively, in graphical form, an ideal and a practical response and a response using a known solution to the distortion problem shown in Figure 2b; Figure 3 illustrates, in part-graphical and part-schematic view, an analogue phase detector arrangement for achieving frequency lock; Figure 5 illustrates in schematic form a phase detector for achieving frequency lock according to an embodiment of the present invention; and, Figure 6 is a graphical representation of output voltage against phase error of a phase detector according to a preferred embodiment of the present invention; Figure 7 is a block diagram of a combined phase detector incorporating the preferred analogue phase detector; and Figure 8 is a block diagram of the analogue phase detector of Fig. 7. Figure 1 shows, in schematic form, a frequency synthesiser arrangement. It can be seen that the arrangement comprises a local oscillator divider chain 1 and a reference divider chain 3 each feeding into a phase detector 5. The detector 5 outputs through an amplifier 7 and a filter " 9. The detector 5 output is used to control the local oscillator through a varactor diode 11 therein. The reference divider chain 3 comprises a reference frequency generator 15 providing a reference frequency which is divided in divider element 16. The divider element 16 divides the reference frequency by the operator K. The local oscillator chain comprises a local oscillator 17 which outputs a local oscillator frequency which is divided by a further divider element 19. The divider element 19 divides the oscillator frequency using a divisor N stored in a data latch 21. The output of phase detector 5, loop amplifier 7 and filter 9 is arranged to steer the LO 17 such that the phase and frequency of the two signals input to detector 5 are balanced with one another. Figure 2(a) illustrates an ideal frequency lock profile wherein the lock frequency FLO is accurately positioned along the curve with no "band ripple" due to the phase detector arrangement of the detector 5. Figure 2(b) illustrates a practical frequency response curve for a digital phase detector showing 'noise' associated with reset signals and differential delays causing ripple on the varactor control line. A solution Figure 2(c) has been proposed to overcome this by further processing which introduces a step in the response over the region of imprecise resolution. However, this provides a 'dead zone' around lock which is disadvantageous. In the detector arrangement of the present invention, shown in figures 3 and 5, the capacitor 50 samples the voltage in the reference cycle. If the capacitor 50 is as near ideal as possible then there will be little leakage especially if buffers (53, 55) are added. Thus, if the frequency lock condition corresponds to Vcc 2 (where Vcc is a rail voltage) and this " value is stored in capacitor 50 there will be little sag in the stored voltage value. In practise, the capacitor will be discharged and charged repeatedly over a set time span with a constant consequential finite phase error. The s/h detector is frequency locked but not phase locked. The analogue sample and hold phase detector is most useful when the synthesiser is near to the frequency lock situation as in-band ripple due to the digital detector may be eliminated. There is no ripple or dead band with the analogue s h detector as the voltage on the capacitor 50 varies smoothly and continuously and, if the detector is in a stable state, this value is preferably Vcc/2. In a practical embodiment of the present invention, the digital detector is switched off when the synthesiser approaches frequency lock to avoid the generation of digital noise in the loop. A symbolic diagram of a typical prior arrangement is shown in figure 4. As can be seen, the analogue sample-and-hold detector and digital detector are operated in tandem. The digital detector 71 receives the reference frequency and oscillator frequency. The up or down phase of these frequencies trigger a sample and hold detector 73. The digital and the analogue detector voltage outputs are then summed externally into an external amplifier 75. Once frequency lock has been achieved it is usual for the output of the digital detector to be disabled. In the embodiment of the present invention shown in figure 5, it will be appreciated that, although the digital and analogue detectors are still operated in tandem, the output from each detector can be processed separately. Summing of respective outputs is also continued but, once the summation enters the linear section 61 (see Fig. 3) of the stored voltage-with-frequency curve of the capacitor 50, the digital phase detector is disabled. Consequently, noise problems associated with this digital phase detector are removed as is the dead zone. It will be appreciated that the present invention couples the speed of digital detectors in approaching frequency lock with the inherently less noisy analogue type detectors such as sample-and- hold. Signals, from the reference source fref and the local oscillator fpd are initially directed as stated above, in tandem to a digital detector 81 and an analogue sample-and-hold detector 83. Output signals from respective detectors 81 and 83 are directed to signal processing means (not shown) whereby the voltage of the local oscillator can be adapted as stated previously. The sample and hold detector 83 additionally includes means to disable the digital detector 81 when the value of the S/H detector 83 approximates the preferred pre-determined value of Vcc/2. Switches 85, 87 and 89 may be added such that the digital detector may be disabled as follows :- (i) By opening switch 86; or (ii) By closing switches 87 and 89 and opening switch 85; Operation of switches 85, 87 and 89 may be controlled by a control element which detects approach of the Vcc/2 condition. Ref erring now to Figs. 6 to 8 of the drawings, there is shown in Figure 7 a combined phase detector incorporating, an analogue phase detector (Figure 8) in accordance with a preferred embodiment of the present invention. The combined phase detector comprises a digital phase detector 110 arranged to receive signals at frequencies Fi and F2. One of these frequencies is derived from the output of a voltage controlled oscillator (VCO) 17 (Fig. 1) and the other frequency is derived from a stable source such as a crystal oscillator 15 (Fig. 1 also). The digital detector 110 may be of conventional form and serves to provide phase up or phase down output signals when signals of a first of the frequencies lead or lag the signals from the other frequency source. The output phase error signals are fed to a charge pump 112 and to an analogue phase detector 114 in accordance with the preferred embodiment of the present invention. The charge pump 112 pumps current into or drains current from an integrating capacitor (not shown but forming part of the charge pump circuit). The output of the charge pump circuit is fed to a buffer amplifier 116 having variable feedback H s and hence to the VCO 11 (Fig. 1). A reference voltage (equal to Vcc/2) is differentially fed to the buffer amplifier 116 so that the output signal thereupon is dependant upon the difference between the voltage on the integrating capacitor and the reference voltage Vcc/2. The output (the phase error signal) from the digital phase detector 110 is also fed to the analogue phase detector 114. Referring particularly to Figure 8, it will be seen that the phase error signal is input to a controller A which sets current levels of and is arranged to switch on and off current sources I s (up) and I s (down). A capacitor C is charged or drained in dependance upon which of the current sources is switched on. The voltage V\ on the capacitor C is fed to an amplifier 120 having a feedback loop paralleled by a second capacitor C2. The output of the amplifier 110 is buffered by buffer amplifier 124 (which may be the same amplifier as the amplifier 116 of Figure 7 or which may feed the amplifier 116 of Figure 7). It can be shown that, if ø is the phase error then over one reference cycle, the voltage on the capacitor Cl is: where ti = ø and f re f is the freq'uency of the reference source 2π f re f (or its quotient) After integration: V i = J _ • ø (11 ) Ci 2π f re f and the gain, in volts/radian, = Kø = Vi ø -is 2π f re f Ci It can be also shown that the output voltage V 0 = _gm_ Vi SC 2 + gm where gm is the mutual conductance of the amplifier 120 and SC2 is the Laplace transform for the capacitance C2. The overall gain for the amplifier Kø in volts/radian then equal Referring to Figure 6, it will be seen that the slope of the graph (Kø) is variable. The response is linear for small errors but limits when the phase error becomes too large. By appropriately adjusting the gain e.g. by adjusting the values of Ci and C2, an optimism value of slope may be selected. Over the chosen range, the output V 0 will vary linearly with phase error. Such an analogue phase detector has great use in the combined detector circuit of Figures 3 and 5 or 7. A lock detect 126 is provided. The lock detect is sensitive to the output voltage of the analogue detector 114. At values of Vo within the chosen linear range of the detector 114, the lock detect is enabled and serves to disable the charge pump 112. The output of the detector 114 is then used to control the VCO. Any jitter or noise originating in the digital phase detector 110 is smoothed out, to a great extent, by the capacitors of the analogue detector 114. The invention is not confined to the precise details of the foregoing example and variations may be made thereto. For example, the analogue phase detector 114 of Figure 8 may be used in other circuits than that shown in Figure 27 (For example, Fig. 5). It will be appreciated that other feedback arrangements may be applied to the amplifier 120 of Figure 8 or to the amplifier 116 of Figure 7. Other variations are possible within the scope of the present invention, as defined by the. appended claims.

Claims: CLAIMS 1. A frequency synthesiser having a phase locked loop circuit including a phase detector means, comprising a digital phase detector and an analogue sample-and-hold detector whereto first and second signals are applied for comparison, and control means for operating the detectors in tandem while a relatively large phase difference exists between the first and second signals and for disabling the digital phase detector when a lesser phase difference is detected, the lesser phase difference being indicative of the loop approaching lock. 2. A synthesiser as claimed in claim 1 wherein the sample-and- hold detector includes an internal capacitor which is arranged to be charged and sampled in order to determine signal phase differences. 3. A synthesiser as claimed in claim 1 or 2 adapted to detect phase differences between signals from a reference source and a local oscillator source. 4. A synthesiser as claimed in Claim 1, 2 or 3 wherein the digital detector is disabled by a control element when the control element detects that the loop is in the linear region. 5. A synthesiser as claimed in claim 1 wherein the analogue phase detector comprises a capacitor, current sources for charging and draining the capacitor in accordance with phase errors fed thereto, an amplifier to a first input of which the voltage on the capacitor is applied, a feedback path between the output of the amplifier and a second input thereto, and a second capacitor between the output of " the amplifier and ground, the first capacitor serving to integrate the error signals fed thereto and the second capacitor serving to integrate the output from the amplifier, whereby the detector has a linear output when the phase errors are within a predetermined range. 6. A synthesiser as claimed in claim 5 wherein control means are provided, the control means serving to regulate the current sources and to switch on a first of the current sources, in response to a phase-up error signal, to charge the first capacitor and to switch off the current sources, in response to a phase-down error signal, to drain the first capacitor. 7. A synthesiser as claimed in claim 5 or 6 further including a buffer amplifier for buffering the integrated output of the first amplifier. 8. A synthesiser as claimed in claim 5 comprising a digital phase detector whereto signals whose phase and/or frequency are to be compared are fed, the digital phase detector providing phase error signals for feeding to the analogue phase detector, a charge pump whereto the phase error signals are also fed, lock detect means driven by the output of the analogue phase detector, the lock detector being enabled when the analogue phase detector's output is within its linear range, the lock detector serving, when enabled, to disable the charge pump, and output means whereto the outputs of the analogue detector and the charge pump, are fed. 9. A synthesiser as claimed in claim 8 wherein the charge pump comprises current sources, a capacitor, and control means, the control means serving to enable the current sources to charge or discharge the capacitor in dependance upon phase-up or phase-down signals received from the digital phase detector. 10. A synthesiser as claimed in claim 8 wherein the output means is arranged to control a voltage controlled oscillator having an output signal from which is derived one of the signals fed to the digital phase detector for comparison, whereby to form a phase locked loop.

Inventors: COWLEY NICHOLAS PAUL, MCCLELLAND THOMAS DAVID STEPHE, COWLEY, NICHOLAS, PAUL, MCCLELLAND, THOMAS, DAVID, STEPHEN
Applicants: PLESSEY OVERSEAS, PLESSEY OVERSEAS LIMITED
Application year: 1989
Main classification: H03L7
IPC codes: H03L7