High accuracy comparator circuit

Abstract: A latching comparator (10) circuit of high accuracy is featured. A latching stage comprising a first and second switch (14, 16) feeds comparative signals to an output (13). Any capacitive or noise mismatch which can possibly occur in the opening of the first latching switch is resolved by introducing a delay in the clocking of the second switch (16), thus allowing the signal of the first switch (14) to stabilize.

Description: The invention relates to comparator circuit for comparing different voltage signals and providing a digital output, and more particularly to a method and new circuit for providing greater accuracy in comparing the differential voltage signals. It sometimes becomes a problem to compare differential voltage signals of small differential value when utilizing latching comparator circuits. The problem arises when high impedance nodes are latched to provide a comparison signal. The opening of the latching switch introduces noise from the switch together with mismatched capacitance, and parasitics due to process variations. This noise can be sufficiently large to distort the differential signals. This distortion can result in an output with an opposite value. JP-A-59148425 discloses a known level comparator of the above-mentioned type which suffers from the problems of parasitic noise. The present invention seeks to eliminate the aforementioned problem. The present invention provides a latching comparator comprising: an amplifying stage having a positive input and a negative input (12) for introducing differential voltage signals for comparison, and having inverted and non-inverted outputs constituting a first pair of nodes for receiving amplified differential voltage input signals; an output (13) for providing a comparison signal representative of a one or a zero value; an amplifying and latching stage having inputs connected to the first pair of nodes and outputs connected to a second pair of nodes, which second pair of nodes are operatively connected to said positive and negative inputs of said amplifying stage, said second pair of nodes receiving amplified differential voltage signals at a higher gain than said first pair of nodes which amplified differential voltage signals are fed back to the amplifying stage, the amplifying and latching stage having a first switch operatively connected to said first pair of nodes and said output, and a second switch operatively connected to said second pair of nodes and said output; characterised by clocking means operatively connected to said first and second switches for providing a pair of clocking signals to successively open said switches, said second switch being opened after said first switch, whereby an impedance mismatch at said first pair of nodes due to noise introduced by said first switch will have stabilized by the time said second switch is opened. Preferably, a delay of between 15 and 25 nanoseconds is provided between the first and second latching switches. The delay allows for the stabilization of any impedance mismatched parasitics due to noise at the first pair of nodes introduced by opening the first latching switch. Preferably, the output connected to the latching stage provides a 5 volt (Vcc) signal representing a digital one, or a zero volt signal. There is therefore provided an improved latching comparator circuit of greater accuracy. In the accompanying drawings, by way of example only: FIGURE 1 illustrates a latching comparator circuit containing the invention which provides a second clock signal that stabilizes the impressed differential voltage signal. FIGURE 2 shows typical timing and cycle diagrams for the latching comparator circuit of FIGURE 1, overcoming an error that can be introduced during switching. Generally speaking, the invention pertains to a latching comparator circuit and method wherein accuracy is improved by assuring that differential voltage signals of even small value will be precisely latched. Now referring to FIGURE 1, a latching comparator circuit 10 is shown. Differential voltage signals are introduced to circuit 10 at positive input 11 and negative input 12. The voltage signals are amplified by a number of amplification stages to provide a set of differential signals at nodes A; A and B; B , respectively. The nodes B; B are at high impedance. Should a low voltage differential signal be impressed thereon, say on the order of 0.0001 volt, a problem is introduced in obtaining an accurate digital signal at output 13, as will be explained hereinafter. Nodes B; B are shorted by a switch 14 which forms part of a latching stage 15 which passes the comparison signal to output 13. Likewise nodes A; A are shorted by a switch 16 which forms part of the latching stage 15. When switches 14 and 16 are opened, the latching stage 15 will pass a comparison signal to the output 13 via final latching stage 70 and invertor 71. Switches 14 and 16 comprise p-channel and n-channel, pass-gates, respectively, that require opposite voltages for them to open or close. They form a bridge network. They are controlled by a clock 17, which opens switch 14 by feeding a positive "1" on line 18 and a negative "0" signal on line 19. Likewise switch 16 is opened when clock 17 feeds a positive "1" signal on line 20 and a negative "0" signal on line 21. If both switch 14 and switch 16 were opened simultaneously, as has been done in the past, a false comparison signal could be obtained at output 13. This is so because the low voltage differential signal at high impedance nodes B; B could be distorted by the mismatched capacitive effect provided by switch 14, when it opens. In other words, a signal error, as shown in FIGURE 2, could occur due to the "noise" introduced by switch 14. A small positive differential signal of 0.0001 volt may be seen as a negative voltage at this instant in time, due to the capacitive effect of opening switch 14. In order to provide a solution to this potential problem, and assure a greater accuracy for circuit 10, the invention introduces a delay of approximately 15 to 25 nanoseconds in the opening of switch 16. The added delay 'C", as illustrated in FIGURE 2, is provided in lines 20 and 21 controlling switch 16 by inverters 23. By delaying the opening of switch 16, and consequently the operation of latching stage 15, the instability evident at nodes B; B (error regions "D") after the opening of switch 14 is allowed to settle, causing the signals to be sampled at a higher differential value. By opening switch 16 subsequent to switch 14, any potential capacitive effects have stabilized at nodes B; B . Nodes A; A see a larger, stable difference due a 500 to 1,000 times gain from the input, by the introduction of delay "C". The output 13 provides a digital "one" signal of 5 volts and a zero voltage signal. The final latching stage 70 provides positive feed-back at transistors 31 and 32. The invertor 71 provides additional gain to restore the output. Transistors 31 and 32 act like capacitors together with inverters 35, 36, 37 and 38 to delay the clock signal for switch 16.

Claims: A latching comparator (10) comprising: an amplifying stage (11,12, 60, 61) having a positive input (11) and a negative input (12) for introducing differential voltage signals for comparison, and having inverted and non-inverted outputs (B, B ) constituting a first pair of nodes for receiving amplified differential voltage input signals; an output (13) for providing a comparison signal representative of a one or a zero value; an amplifying and latching stage (15) having inputs connected to the first pair of nodes (B, B ) and outputs connected to a second pair of nodes (A, A ), which second pair of nodes are operatively connected to said positive and negative inputs (11,12) of said amplifying stage, said second pair of nodes (A, A ) receiving amplified differential voltage signals at a higher gain than said first pair of nodes (B, B ) which amplified differential voltage signals are fed back to the first amplifying stage, the amplifying and latching stage (15) having a first switch (14) operatively connected to said first pair of nodes (B, B ) and said output (13), and a second switch (16) operatively connected to said second pair of nodes (A, A ) and said output (13); characterised by clocking means (17) operatively connected to said first and second switches (14,16) for providing a pair of clocking signals to successively open said switches (14,16), said second switch (16) being opened after said first switch (14), whereby an impedance mismatch at said first pair of nodes (B, B ) due to noise introduced by said first switch (14) will have stabilized by the time said second switch (16) is opened. A latching comparator as claimed in claim 1, wherein said clocking means (17) further includes delay means (31,32,35,36,37,38) for providing a clocking signal to said second switch (16), 15 to 25 nanoseconds after said first switch (14). A latching comparator circuit as claimed in claim 1 or claim 2, wherein said first and second switches (14,16) form a bridge network. A latching comparator as claimed in claim 1, 2 or 3, wherein said second switch signal is delayed by a number of inverters (39,36,37,38) from the first switch signal. The latching comparator circuit as claimed in any preceding claim, wherein said output (13) provides a comparison signal of approximately 5 volts representing a one value. A method of comparing differential voltage signals, comprising the steps of: (a) introducing said differential voltage signals to respective positive and negative inputs (11,12) of an amplifying stage (11,12,60,61), said amplifying stage having inverted and non-inverted outputs (B, B ) constituting a first pair of nodes which receive the amplified differential voltage signals; (b) introducing said amplified differential voltage signals to a second pair of nodes (A, A ) at the output of an amplifying and latching stage, which second pair of nodes are operatively connected to said positive and negative inputs (11,12) of said first amplifying stage, said second pair of nodes (A, A ) receiving amplified differential voltage signals at a higher gain than said first pair of nodes (B, B ); (c) feeding back the voltage signals at the second pair of nodes (A, A ) to the first amplifying stage; (d) opening a first latching switch disposed between said first pair of nodes (B, B ) to provide a latching signal; and characterised by (e) opening a second latching switch (16) disposed between said second pair of nodes (A, A ) to provide a latching signal, said second switch (16) being opened subsequent to said first switch (14) whereby an impedance mismatch at the first pair of nodes (B, B ) due to noise introduced by opening said first switch (14) will have stabilized by the time said second switch (16) is opened. A method as claimed in claim 6, wherein said second switch (16) is opened 15 to 25 nanoseconds after said first switch (14).

Inventors: FEEMSTER RYAN ERVIN, MOYAL MIKI ZVI, FEEMSTER, RYAN ERVIN, MOYAL, MIKI ZVI
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1989
Main classification: H03K3
IPC codes: H03K3, H03K5