Boost clock signal generator

Abstract: A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors (46) which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor (58, 59) is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit (78, 79) are connected to the series pass FET transistors for enabling one or the other of the differentially-connected FET transistors into conduction. The pair of capacitive coupling elements (51, 52) coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.

Description: High density dynamic memories are routinely implemented with redundant word lines. The redundant word lines are used when a tested memory has a failure of one or more word lines. When the memory has a defective word line, it is possible by activating programmable fuses to activate one or more redundant word lines. In a common dynamic memory organization, rows of memory cells are arranged in blocks of four. Addressing of rows occurs on alternate clock phases. When a defective row line is replaced by a redundant row line, it is necessary to clock the row driver on either clock phase. Additionally, the dynamic memory is provided with a sample word line for each section of memory rows which must be activated on either phase of the phase clocks. The reference line will provide a logic reference which is used to distinguish logic states of data produced by an actual row of the memory having data. This is described in the following prior art: U.S. Patent No. 4,599,528, U.S. Patent No. 4,490,626, U.S. Patent No. 4,969,638, U.S. Patent No. 3,654,394, U.S. Patent No. 2,867,723, U.S. Patent No. 4,639,614, U.S. Patent No. 4,494,018. WO-A-86/05934 (NCR) discloses a clock signal circuit receiving two clock signals, the pulses of which are non-overlapping with respect to each other. The circuits comprise a set of transistors connected with a set of NOR gates. In operation, selected, boosted clock signals are supplied to an output line. The coupling of either clock phase signal to the redundant word line driver or sample word line driver must be done with a circuit having a speed which will not significantly increase the access time for the dynamic memory. Further, to adequately reset the row driver clock lines and sample word line driver clock lines, the coupling must provide a voltage boost below ground to a negative voltage which is more negative than the threshold voltage of the array device. Thus, the need for a boost clock which can provide clocking signals for the redundant word lines and sample word lines on each phase of the two phases of the phase clock at a speed which does not substantially increase access time is evident. The object of this invention is to provide CMOS boost clock signals for redundant and sample word line drivers of a dynamic RAM which do not significantly increase access time of a dynamic RAM. The invention is set forth in claim 1. The object is provided by a CMOS circuit which is capable of providing each of two clock phases to a redundant word line driver or sample word line driver. Two phase clock signals, only one of which is active during a memory RAS cycle, are individually coupled to the drain connection of two differentially connected FET transistors. The differentially connected FET transistors have source connections which form an output terminal for either clock phase signal. The gate connections of the differential transistors are biased to float at a level of approximately 0 volts. The gates are connected to an output logic circuit which indicates that one or the other clock signal is active, and that the RAS strobe cycle is in progress. To increase the speed of switching for the differential transistor pair, capacitive elements couple the drains of each transistor to the gates of the other transistor. Thus, the negative going clock signal level appearing on a drain of one transistor will force the other transistor towards a non-conducting state. Fig. 1 illustrates the organization of a dynamic RAM including redundant word lines and sample word lines. Fig. 2 illustrates a boost circuit which is capable of providing both redundant word line clock signals and sample word line clock signals. The memory is shown in Fig. 1 as being subdivided into four sections 20a, 20b, 20c and 20d. Each pair of the RAM sections is shown to include a pair of redundant word lines 21, 22, 23 and 24. Each RAM half includes a sample word line 26 and 33. If it is necessary during the manufacture of a DRAM to activate one of the redundant word lines, certain fusible links may be activated to connect the redundant word lines which are activated in place of a defective word line. The sample word lines will additionally provide a sample logic level in which to compare the contents of each activated word line, i.e., regular or redundant, which may be addressed by the address decoder 14. The redundant word lines are connected to a word line driver 18. These word lines may be suitably addressed by an address enable circuit 16. When a redundant word line is to be accessed, the driver circuit 18 will be enabled to receive a driving signal in synchronization with one or the other clock phases for that word line. Shown in Fig. 1 is a boost clock 15 which will supply the signal for the word line driver 18 which is ultimately coupled to drive the word line 21, 22, 23 and 24 into a read or write mode. These driving signals from the boost clock 15 are also used to drive the sample line 26. A conventional address buffer 11 and RAS buffer 12 will cooperate in receiving address information for the DRAM 20. The decoder 14 will decode a particular address and apply the clocking signals needed to access the addressed memory location. The RAS buffer 12 will provide a strobe signal PRASBII to the boost clock 15. The boost clock 15 receives two clock signals, PX1 and PX2 which are exclusive signals. One or the other of these signals is used to provide a clock time for the word driver circuits used to address the DRAM 20. The address enable circuit 16 receives one of the clock signals PX1, which is associated with clocking of the regular word lines in the RAM half 20a and 20b. A similar address enable circuit 16 is shown for addressing that half of RAM 20 identified as 20c and 20d. Similarly, a boost clock circuit 15 is shown for providing the three drive signals for the redundant word lines and sample word lines. When a redundant word line is being selected by the decoder 14, it is necessary to drive the word line on the occurrence of either a clock phase PX1 or clock phase PX2 which is normally used for the second half of the RAM 20c and 20d. The boost clock circuit 15 will provide the required drive signals, synchronized with the decoder 14 output signals. A particular boost clock, which is a preferred embodiment of the present invention, useful for supplying a boost clock signal during either PX1 or PX2, is shown in Fig. 2. In this circuit, three different driver signals are generated, PXS12, PXRU12 and PXRD12. These drive signals will activate two redundant lines and a sample line. Additional boost clock circuits can be provided for as many additional redundant word lines or sample word lines as may be required for a particular DRAM architecture. Shown in Fig. 2 are three pairs of differentially connected FET transistors 46, 47 and 48. These differentially connected transistors receive the clock signals PX1 and PX2 on the drain connections. These clock signals are connected to the drains of each pair of differentially connected transistors 46, 47 and 48. The gates of each of these pairs of differentially connected transistors are maintained at a floating potential of approximately 0 volts. Series PMOS FET transistors 58, 59, 61, 62 and 64, 65 have a gate connection return to ground potential. This maintains the gates of the differential transistor pairs 46, 47 and 48 at approximately 0 volts. Each of the connected source connections of differential transistor pairs 46, 47 and 48 form one of the output terminals PXS12, PXRU12 and PXRD12 for providing a drive signal for either a redundant word line or a sample word line of a DRAM. The source connections for the differential transistor pairs 46, 47 and 48 is connected through a series FET gate 70, 71 and 72 to VDD, a source of positive potential. Normally, a gate signal PRASII is applied to the gates of each of transistors 70, 71 and 72. In a logic low state, PRASII will maintain the outputs PXS12, PXRU12, PXRD12 at a high level. Just prior to the appearance of a clock pulse PX1 or PX2, the decoder circuitry 14 of Fig. 1 will apply the PRASII signal as a high logic level, permitting the differential transistor pairs 46, 47 and 48 to follow the clock signal PX1 or PX2. The decoder circuit 14 of Fig. 1 will provide an ENABLE signal to permit one or the other of clock signals PX1 or PX2 to propagate through to one of the driver signal terminals PXS12, PXRU12 and PXRD12. These logic circuits are shown as conventional NOR circuits 76 and 78, connected to the decoder 14 of Fig. 1. In operation, one or the other of logic circuit 76 or 78 provides an enabling signal to the gate of one transistor of transistor pairs 46, 47 and 48 in response to signals PB1, PBII and PRASBII. The action of the transistor of a differential pair receiving the gate signal is to turn that particular transistor into a conducting mode. Additionally, one of a connected cross-coupling element, shown as an FET transistor with source and gate connected together, 51, 52, 53, 54, 55 and 56, couples the clock signal to the gate. The coupling elements 51, 52, 53, 54, 55 and 56 will, during the negative transition of a clock pulse applied to one of the drain connections, couple the negative transition to the opposite transistor in the transistor pair. Thus, a logic signal produced by logic circuit 78 will tend to turn the connected transistor of transistor pairs 46, 47 and 48 into a conducting state. The negative-going edge of the clock pulse connected to this transistor will tend to force the opposite transistor of the differential pair into a non-conducting state, thus turning off the opposite transistor. The source connection will therefore follow the phase clock from a positive VDD level to a negative -2 volts. The coupling provided by the connected coupling element will avoid the condition where the non-conducting transistor is inadvertently gated on by the lowering of the source voltage below the threshold voltage VTN of transistor pairs 46, 47 and 48. Since, in the first transistor pair 46, FET transistors 58 and 59 maintain the gate potentials floating in the absence of a logic signal, the cross-coupled clock signal will maintain this gate signal negatively biased, avoiding incidental turn-on of the transistor. Thus, it is seen where each of the transistor pairs 46, 47 and 48 can provide one or the other clock signals, PX1, PX2, boosted below ground, to a connected driver circuit. It has been found that the capacitive coupling elements comprising transistors 51, 52, 53, 54, 55 and 56 are preferable over a direct coupling method. The capacitive coupling effectively isolates the unactivated clock PX1 or PX2 during the period the remaining clock is active. Direct coupling of each clock to the gate of an oppositely connected transistor of each transistor pair would provide feedback of a disadvantageous voltage pulse or glitch into the unactivated clock. It is therefore seen how a boost clock for redundant word lines or sample word lines may be effected using cross-couples CMOS differential transistor pairs.

Claims: Boost clock signal generator which provides a boost clock signal from a pair of phase clock signals which synchronize reading of memory locations comprising: a pair of differentially connected FET transistors (46) for generating said boost clock signal, each of said transistors having a drain connection connected to one of said clock signals, and commonly connected sources forming an output terminal; a series pass FET transistor (58, 59) in series with each gate of said differentially connected transistors for maintaining each gate at a floating voltage potential; a pair (51, 52) of capacitive coupling elements coupling the drain of each transistor of said pair of differentially connected FET transistors to the gate of an opposite transistor of said pair; a first logic circuit (76) connected to one of said series pass FET transistors; and, a second logic circuit (78) connected to the remaining one of said series pass FET transistors, whereby one or the other of said differentially connected transistors is gated on by one of said logic circuits in response to an enable signal, and it is driven into non-conduction by a signal coupled by one of said capacitive coupling elements. Boost clock signal generator of claim 1, further comprising a control FET transistor (70) connecting said differential transistor source connections to a source of DC potential, said control FET operatively supplying a control voltage to said output terminal in response to a logic signal applied to the gate of said control FET transistor. Boost clock signal generator of claims 1 or 2, further comprising second and third identical boost clock generators (47, 48), connected in parallel with said first boost clock signal generator (46). Boost clock signal generator of claim 3 wherein the second and third identical boost clock generators (47, 48) comprise: second and third pairs of differential FET transistors (47 - 48) each pair having source connections connected together to form first, second and third output terminals, and drain connections connected to said phase clocks; second and third pairs of FET gate transistors (61, 62, 64, 65), each transistor serially connected to a gate connection of said differential transistor pairs and connected to a first and second logic circuit, said transistors maintaining said differential transistor gates at a floating potential, said first and second logic circuits enabling one transistor of each differential pair of transistors to connect one of said clock signals to said first, second and third output terminals; and, second and third pairs (53 - 56) of capacitive coupling elements, each pair connecting the drains of one of said differential transistor pairs to the gate of the remaining transistor, said capacitive coupling elements increasing the speed at which said differential transistors switch from a non-conducting to a conducting state. Boost clock signal generator of claim 4, wherein said capacitive coupling elements comprise FET transistors having their source connected to their drain connection and to one transistor of said differential pair, and a gate connected to a remaining differential transistor of said pair. The boost clock signal generator of claims 4 or 5, further comprising first, second and third series FET transistors (70-72) connected to said first, second and third output terminals for coupling a logic signal common to each gate of said series FET transistors to said first, second and third output terminals.

Inventors: DHONG SANG HOO, HWANG WEI NMI, LU NICKY CHUA-CHUN, DHONG, SANG HOO, HWANG, WEI NMI, LU, NICKY CHUA-CHUN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: G11C8
IPC codes: G11C8, G11C29, G11C11