Microprocessor equipped with parity control unit on same chip

Abstract: A microprocessor having a on-chip redundant control unit is disclosed. This processor includes a set of data terminals, an execution unit and a data bus buffer coupled between the set of data terminals and the execution unit, and the data bus buffer fetches data on the set of data terminals in response to a first timing signal and transfers the fetched data to the execution unit in response to a second timing signal. The on-chip redundant control unit receives the fetched data and redundant information and checks the validity of the fetched data in response to the redundant information before the generation of the second timing signal, so that an effective memory access time is not prolonged.

Description: BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to a microprocessor and, more particularly, to a microprocessor for structuring a high reliability data processing system. Description of Related Art: As one of techniques for structuring a high reliability data processing system, it is known in the art to add redundant information to data. In a system employing a parity bit as redundant information, data read out of a memory is checked to be valid or not from that data and the parity bit information added thereto, whereas data processed by the microprocessor is written into the memory together with the parity bit information produced from the data to be written. Referring to Fig. 1, there is shown such a data processing system according to prior art. A microprocessor 701 is interconnected through a system control bus 704, a system address bus 705 and a system data bus 706 to a program/data memory 702 storing a program and operand data to be executed and processed. The program and data stored in the memory 702 are called hereinafter "data". There are further provided a parity bit memory 703 and a parity control circuit 708. The memory 703 is connected to the system control and address buses 704 and 705, and the control circuit 708 is connected to the system control and data buses 704 and 706. The memory 703 and the control circuit 708 are interconnected through a parity bit line 707. The control circuit 708 supplies a data valid/invalid indication signal 709 and a ready signal 710. In a data read operation, the microprocessor 701 accesses to desired addresses of the memories 702 and 703 by means of the control and address buses 704 and 705. The data read out of the accessed address is transferred. via the data bus 706 to the microprocessor 701 and further to the parity control circuit 708. Moreover, parity bit information added to the data read out of the memory 702 is read out from the parity bit memory 703 and transferred to the control circuit 708 via the line 707. The parity control circuit 708 calculates a syndrome of the data supplied thereto and compares the calculation resultant with the parity bit information. During the calculation, the control circuit 708 changes the ready signal 710 to an inactive level to inform the microprocessor 701 of the circuit 708 being calculating. When the calculation is completed, the'control circuit 708 changes the ready signal 710 to an active level and informs, by the signal 709, the microprocessor 701 whether or not the data read out of the memory 702 is valid. In a data write operation, the microprocessor 701 accesses desired addresses of the memories 702 and 703 by means of the control and address buses 704 and 705 and transferred data to be written onto the data bus 706. This data is written into the accessed address of the memory 702 and further supplied to the parity control circuit 708. The circuit 708 calculates a syndrome of the data and produces parity bit information which is in turn written into the accessed address of the memory 703 through the line 707. During the syndrome calculation, the circuit 708 supplied the inactive level ready signal 710 to the microprocessor 701. Thus, a high reliability system can be structured. As apparent from the above description, however, an effective memory access time is determined by the summation of an access time required by the memory 702 and a syndrome calculation time required by the parity control circuit 708. For this reason, the microprocessor cannot perform a data processing operation at a high speed, and this reduces the performance of the system. Attention is drawn to the following prior art. Patent Abstracts of Japan, Vol. 006, No. 002, discloses providing a unit which executes an error processing operation, a parity error operation for example, on a memory independently of and separately from an execution unit. US-A-4.528.666 discloses incorporating a parity/check generation unit into a memory system. US-A-4.648.034 discloses a protocol for synchronizing the operation of a CPU with that of a co-processor. US-A-4.205.301 discloses a method for detecting malfunction of a semiconductor device. Patent Abstracts of Japan, Vol. 010, No. 241, discloses means for processing an output from a parity check circuit, the parity check being inhibited during memory read-out. SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor having a shortened effective memory access time. Another object of some embodiments of the present invention is to provide a microprocessor in which a redundant information control unit is fabricated as an on-chip unit together with a control circuit for controlling activation/inactivation of the redundant information control unit. A microprocessor according to one aspect of the present invention comprises, on a single semiconductor chip, an execution unit for executing an instruction, a set of data terminals supplied with data, and characterised in that said execution unit includes means for generating a first timing signal and thereafter a second timing signal and that said microprocessor further comprises, on said single semiconductor chip, first means responsive to said first timing signal for fetching the data supplied to said set of data terminals, second means responsive to said second timing signal for transferring the data fetched in said first means to said execution unit, means for checking the validity of the data fetched in said first means and producing before said second timing signal is generated a resultant signal representing whether or not the said data fetched in said first means is valid, and means for supplying said resultant signal to said execution unit, said checking means including a redundant information terminal supplied with redundant information accompanying said data supplied to said set of data terminals, storing means responsive to said first timing signal for temporarily storing said redundant information, and means responsive to the data fetched in said first means and the redundant information stored in said storing means for producing said resultant signal. There may be a clock generator on said chip, said execution unit including means for generating the first timing signal (RDL) and thereafter the second timing signal (RDO) from successive clock signal cycles. Said supplying means may receive a control signal and supply said resultant signal to said execution unit when said control signal takes an active level and supply a valid signal representing that said data fetched in said first means is valid to said execution unit irrespective of said resultant signal when said control signal takes an inactive level. The redundant information control unit can check the validity of the data fetched in the microprocessor before the data appears on the internal data bus, so that the data checking time of the control unit does not influence an effective memory access time. In an embodiment of this micro-processor to a system employing no redundant information, it is sufficient to supply the redundant enable signal of the inactive level, so that no external control circuit for the redundant information terminal is required. BRIEF DESCRIPTION OF THE INVENTION The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram representative of a data processing system according to prior art; Fig. 2 is a block diagram representative of a data processing system employing a microprocessor according to an embodiment of the present invention; Fig. 3 is a detailed block diagram representative of a data bus buffer, a parity control unit and a parity enable control circuit of the microprocessor shown in Fig. 1; Fig. 4 is a timing chart representative of a data read operation of the microprocessor shown in Fig. 1; Fig. 5 is a timing chart representative of a data write operation of the microprocessor shown in Fig. 1; Fig. 6 is a block diagram representative of another embodiment of the present invention; and Fig. 7 is a timing chart representative of an address output of the microprocessor shown in Fig. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 2, a microprocessor 1 according to an embodiment of the present invention is fabricated as a monolithic semiconductor integrated circuit device and is interconnected through a system control bus 4, a system address bus 5 and a system data but 6 to a program/data memory 2 storing a program and operand data to be executed and processed which are called simply "data" hereinafter. The microprocessor 1 is further interconnected through the system control and address buses 4 and 5 and a parity bit line 7 to a parity bit memory 3 storing parity bit information as redundant information. The parity bit line 7 is connected to a parity terminal 51 of the processor 1. The microprocessor 1 includes an instruction execution unit 10 for executing instructions for the program and performing read/write operations of operand data. The unit 10 outputs a set of control signals onto the system control bus 4 vaa an internal control bus 70 and a control bus buffer 20 and a set of address signals onto the system address bus 5 via an internal address bus 80 and an address bus buffer 30. A data bus buffer 40 and an internal data bus 90 are of a bidirectional type and interconnect the execution unit 10 and the system data bus 6. The data bus buffer 40 is supplied with control signals R/W, RDL, RDO, WDL1 and WDL2 for data read/write operation via the internal control bus 70 and/or directly from the execution unit. The signal R/W is a data read/write signal for designating a data read operation or a data write operation. The signal RDL is a read data latch signal used as a first timing signal for fetching read-data on the system data bus 6 into the microprocessor 1, and the signal RDO is a read data output signal used as a second timing signal for transferring the fetched read-data onto the internal data bus 90. The signal WLD1 is a first write data latch signal used for fetching write-data on the internal data bus 90 into the data bus buffer 40, and the signal WDL2 is a second write data latch signal used for transferring the fetched wrste-data onto the system data bus 6. The read-data fetched into the buffer 40 by the timing signal RDL is transferred via a set of read-data lines 41 to an on-chip parity control unit 50. This unit 50 calculates a syndrome of the fetched read-data and produces a data validity indication signal 52 in response to a parity bit information supplied from the terminal 51, the signal 52 being in turn supplied to a parity enable control circuit 60. The unit 50 is further supplied with the control signals R/W, RDL and WDL2. The control circuit 60 is also supplied with a parity enable signal REC from a terminal 61. When a redundant control function is employed, the signal REC is fixed to logic "0" as an active level. On the other hand, in case where the redundant control function is not employed, the signal REC is fixed to logic "1" as an inactive level. A signal 62 derived from the enable control circuit 60 is supplied to the execution unit 10. The write-data fetched into the buffer 40 by the control signal WDL1 is transferred to the control unit 50 via a set of write-data lines 42. The unit 50 calculates a syndrome of the write-data to produce parity bit information which is in turn transferred onto the line 7 via the terminal 51. Referring to Fig. 3, the data bus buffer 40 includes N pieces of buffer units 40-1 to 40-N for implementing the interface between the system data bus 5 consisting of N bus lines 6-1 to 6-N and the internal data bus 90 consisting of N bus lines 90-1 to 90-N. Since each of the buffer units 40-1 to 40-N has the same construction as one other, only the first unit 40-1 is shown in Fig. 2. A latch circuit 413 latches write-data on the internal bus line 90-1 in response to the signal WDL1 and a latch circuit 412 latches the output of the latch circuit 413 in response to the signal WDL2. An output buffer circuit 411 is controlled by the signal R/W and transfers the output of the latch circuit 412 onto the system data bus line 6-1 in the data write operation mode. The output of the circuit 411 is brought into a high impedance state in the data read operation mode. An input buffer circuit 414 is activated in the data read mode and'deactivated in the data write mode under the control of the signal R/W. A latch circuit 415 latches the output of the input buffer circuit 411, i.e. read-data on the system data bus line 6-1, in response to the signal RDL. An output buffer circuit 416 transfers the output of the latch circuit 415 onto the internal data bus line 90-1 in response to the signal RDO. The output of the latch circuit 415 is derived as one bit read-data RD1 and the output of the latch circuit 413 is derived as one bit write-data WD1. The read-data of N bits RD1 to RDN and the write-data of N bits WD1 to WDN are supplied to a multiplexer 501 in the parity control unit 50 via the data lines 41 and 42, respectively. The multiplexer 501 is controlled by the signal R/W and selects the read-data RD1 to RDN in the data read mode and the write-data WD1 to WDN in the data write mode. The selected data from the multiplexer 501 is supplied to a syndrome calculator 503 to calculate syndrome thereof. Since the construction and operation of the calculator 502 are well known in the art and the present invention does not relate directly to the calculator 502, detailed description thereof is omitted in order to avoid the complexity of the drawing. The calculation resultant signal 53 of the calculator 52 is supplied to one input of an exclusive NOR gate (EX-NOR gate) 503 and is latched into a latch circuit 504 in response to the signal WDL2. The output of the latch circuit 504 is transferred onto the line 7 in the data write mode by an output buffer circuit 505 controlled by the signal R/W. An input buffer circuit 506 is activated by the R/W signal in the data read mode to transfer the parity bit information to an latch circuit 507. This circuit 507 latches the parity bit information in response to the signal RDL and supplied the same to the other input of the EX-OR gate 503. The output of the EX-OR gate 503 is derived as the data validity indication signal 52 representing whether or not the read-data is valid. The parity enable control circuit 60 consists of an OR gate 601. As mentioned hereinbefore, the enable signal REC is fixed to logic "0" in the case of employing the redundant control function, and therefore the OR gate 601 transfers the data validity indication signal 52 to the execution unit 10 as the signal 62. In the case of employing no redundant control function, the enable signal REC is fixed to logic "1", so that the output signal 62 of the OR gate 601 is held at logic "1" irrespective of the signal 52. Accordingly, the execution unit 10 regards all the read-data as being valid. No control circuit for controlling the parity bit terminal 51 is therefore required. The data read operation and data write operation of the processor 1 will be described below with reference to Figs. 2 and 3 and further to Figs. 4 and 5 representing the data read and write timing charts, respectively. In the present microprocessor 1, each bus cycle for the data read/write operation is composed basically'of two clocks (T1 and T2 states) of a system clock signal . Based upon this clock signal , two timing clock signals 1 and 2 different in phase from each other are produced to generate the above timing signals RDL, RDO, WDL1 and WDL2. In the data read operation (Fig. 4), the microprocessor 1 outputs a set of address signals on the system address bus 5 and a set of data read control signal on the system control bus 4 to access desired addresses of the memories 2 and 3 at the beginning of the data read bus cycle. The data read out of the accessed address of the memory is transferred to the system data bus 6 and the parity bit information read of the accessed address of the memory 3 is transferred to the line 7. The execution unit 10 generates the read data latch signal RDL in synchronism with the timing clock 2 occurring in the T2 state, so that the read-data on the system data bus 6 is fetched in the latch circuit 415 and transferred to the syndrome calculator 502. The parity bit information on the line 7 is fetched in the latch circuit 507. By the falling of the signal RDL to logic "0", the latch circuit 415 closes the input gate thereof to hold the read-data therein. In synchronism with the timing clock 2 occurring in the T1 state after the T2 state, the execution unit 10 produces the read data output signal RDO, so that the data output buffer 416 transfers the read-data from the latch circuit 415 onto the internal data bus 90. On the other hand, the syndrome calculator 502 receives the read-data at the timing of the generation of the signal RDL and calculates the syndrome thereof. The calculated resultant in compared by the EX-OR gate 503 with the parity bit information from the latch circuit 507 and the comparison resultant 52 is supplies to the execution unit 10 via the OR gate 601. There is a time period corresponding to one clock of the clock signal  from a time point at which the data bus buffer 40 fetches the read-data on the system data bus 6 to a time point at which the data bus buffer 40 transfers the fetched read-data onto the internal data bus 90. During this time period, the parity control unit 50 can check the validity of the read-data. Accordingly, the checking time required by the unit 50 does not appear in the read data bus cycle. If the signal 52 from the unit indicates the invalidity of the read-data, the execution unit 10 restarts the read-data bus cycle or suspends the data processing operation. In the data write operation (Fig. 5), the execution unit 10 transfers data to be written, i.e. write-data, onto the internal data bus 90 in synchronism with the timing clock 2 occurring in the T2 state just before the data write bus cycle to be executed, and further generates the data latch signal WDL1. In response to the signal WDL1, the latch circuit 413 fetches the write-data on the internal data bus 90 and supplies the same to the syndrome calculator 502. The calculator 502 starts to calculates the syndrome thereof. At the beginning of the data write bus cycle, a set of write-address data is transferred onto the system address bus 5. The execution unit 10 generates the signal WDL2 in synchronism with the timing clock ₂ occurring in the T1 state. In response to the signal WDL2, the latch circuit 412 fetches the write-data from the latch circuit 413 and transfers the same onto the system data bus 5 via the output buffer circuit 411. Since a time period from the generation of the signal WDL1 to that of the signal WDL2 corresponds to one clock time of the clock signal , the calculator 502 completes the calculation of the syndrome of the write-data during that time period. The calculated resultant 53 is fetched in the latch circuit 504 in response to the signal WDL2 and transferred onto the parity bit line 7 via the output buffer circuit 505 and the terminal 51. The write-data on the system data bus 6 and the parity bit information on the line 7 are written into the accessed addressed of the memories 2 and 3, respectively. Thus, the syndrome calculation time also does not appear in the data write bus cycle. As described above, the microprocessor 1 has the on-chip parity control unit 50 without prolonging each of the data read and write bus cycles. Moreover, the microprocessor 1 can be easily applied to a system employing no parity bit control function. In order to further enhance the reliability of a system, an address for accessing an external memory or peripheral unit may be added with parity bit information. A microprocessor applicable to such a system is shown in Fig. 6 as another embodiment of the present invention. The present microprocessor 1 further includes an address parity control unit 110 for adding parity bit information to an address to be transferred onto the system address bus 5. This unit 110 includes a calculator 112 for calculating the syndrome of the address to produce address parity bit information 115, a latch circuit 113 for fetching the information 115 in response to a second address latch timing signal AL2 and an output buffer circuit 114 for transferring the output of the latch circuit 113 onto an address parity bit line 120 via an address parity bit terminal 111. The buffer 114 is brought into a high impedance state by a signal HQ generated when the microprocessor 1 is in a hold or halt state. The address data buffer 30 includes buffer units 30-1 to 30-M coupled respectively between each of the internal address bit-lines 80-1 to 80-M and each of the system address bit lines 5-1 to 5-M. Each of the units 30-1 to 30-M includes a latch circuit 301 for fetching an internal address in response to a first address latch timing signal AL1, a latch circuit 302 for fetching the output of the latch circuit 301 in response to the signal AL2 and an output buffer circuit 303 controlled by the signal HQ. As an address output timing chart is shown in Fig. 7, the execution unit 10 transfers an address onto the internal address bus 80 and generates the signal AL1 in synchronism with the timing clock 1 occurring in the T2 state ust before the bus cycle to be executed. In response to the signal AL1, the latch circuit 301 fetches the address on the bus 80 and transfers the same to the syndrome calculator 112. The execution unit 10 thereafter generates the signal AL2 in synchronism with the timing clock 1 occurring in the T1 state. As a result, the address is fetched in the latch circuit 302 and transferred onto the system address bus 5 via the output buffer 303. Since a time period from the generation time of the signal AL1 to that of the signal AL2 corresponding to one clock time period of the clock signal , the calculator 112 completes the calculation of the address syndrome during that time period. The address parity bit information 115 is thus fetched in the latch circuit 113 in response to the signal AL2 and transferred onto the line 112 via the buffer 114 and the terminal 111. The microprocessor 1 shown in Fig. 6 is further different from that shown in Fig. 2 in that a parity enable control flag 11 is provided in the execution unit 10 and the set/reset signal thereof is utilized as the parity enable control signal REC in place of the externally supplied signal shown in Fig. 2. The set state of the flag 11 disables the data parity control function, whereas the reset state thereof enables this function. The parity enable control signal REC can be supplied to the microprocessor 1 from the outside thereof, similarly to Fig. 1. Inversely, the parity enable control flag 11 can be provided in the microprocessor shown in Fig. 1. In the above embodiments, the parity bit is employed as the redundant information, but other type redundant information may be employed. Moreover, two or more redundant information control units of different types from each other may be provided in a microprocessor and one of them may be selectively activated in accordance to a system to be structured. The present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope of the invention as defined by the claims.

Claims: A microprocessor comprising, on a single semiconductor chip, an execution unit (10) for executing an instruction, a set of data terminals (6) supplied with data, and characterised in that said execution unit includes means for generating a first timing signal (RDL) and thereafter a second timing signal (RDO) and that said microprocessor further comprises, on said single semiconductor chip, first means (415) responsive to said first timing signal for fetching the data supplied to said set of data terminals, second means (416) responsive to said second timing signal for transferring the data fetched in said first means to said execution unit, means (50,51) for checking the validity of the data fetched in said first means and producing before said second timing signal is generated a resultant signal (52) representing whether or not the said data fetched in said first means is valid, and means (60) for supplying said resultant signal to said execution unit, said checking means including a redundant information terminal (51) supplied with redundant information accompanying said data supplied to said set of data terminals, storing means (507) responsive to said first timing signal for temporarily storing said redundant information, and means (502,503) responsive to the data fetched in said first means and the redundant information stored in said storing means for producing said resultant signal. The microprocessor as claimed in Claim 1, comprising a clock signal generator on said chip, said execution unit including means for generating the first timing signal (RDL) and thereafter the second timing signal (RDO) from successive clock signal cycles. The microprocessor as claimed in Claim 1 or Claim 2, characterised in that said supplying means receives a control signal (REC) and supplies said resultant signal to said execution unit when said control signal takes an active level and supplies a valid signal representing that said data fetched in said first means is valid to said execution unit irrespective of said resultant signal when said control signal takes an inactive level.

Inventors: SATO YOSHIKUNI, SATO, YOSHIKUNI, SATO, YOSHIKUNI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: G06F11
IPC codes: G06F11, G06F15