Semiconductor memory device

Abstract: Memory cells (12,22...N2) disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by first gate means. One memory cell column in the n memory cell columns in a selected block is selected by second gate means. One memory cell (12,22...N2) in a selected memory cell column is selected by a row address. The data in a selected memory cell (12,22...N2) are stored in a register and output therefrom.

Description: The present invention relates to a semiconductor memory device comprising a memory cell array composed of a plurality of memory cells arranged into a matrix pattern, c.f. IEE International Solid-State Circuit Conference Volume 27, pages 100-101, San Francisco, 22-24 February 1984, Taguchi et al.: "A Capacitance-Coupled Bit-Line Cell for Mb level DRAM's". The memory described in this prior art document contains a matrix of memory cells selected by row and column decoders, the row decoder controlling the rows, and the cells are divided into blocks. A block is selected by a signal from the column decoder, i.e. selected by a column address. The columns inside a block in the circuit of this document are selected by activating transfer gates connected to the ends of the columns. Two pairs of folded bit lines, i.e. two columns, form a block and share a common sense amplifier. During operation of this prior art memory device, one of two columns is selectively connected to a single sense amplifier, and the output of the sense amplifier is connected to a common data bus via a transfer gate. Therefore, data is transmitted to the data bus from only one of the two columns. Since one sense amplifier is provided for two columns, the selected one of the two columns must first be connected to the sense amplifier before the sense amplifier may be activated. In order to facilitate understanding the basic concept of the present invention the background art is briefly described hereinafter. BACKGROUND OF THE INVENTION Fig. 3 shows a part of a semiconductor memory device-circuit as the background art of this invention, i.e. shows one column of a CMOS DRAM having a serial access function. In Fig. 3, a bit line equalizer circuit, pre-charger circuit and the like are omitted, and only those circuit portions associated with data sensing and transfer are shown. Each bit line of a pair of bit lines BLN and BLN is connected with the same number of cells. A V PL line is a fixed electrode of a cell capacitor. The bit line pair BLN, BLN is pre-charged to 1/2 V cc . When a word line WL1 or WL₂ is activated, the contents (data) of a cell which appear on one of the bit line pairs are compared with a reference voltage 1/2 V cc on the other of the bit line pair, and amplified by a sense amplifier. In sensing the data, a line SAN is first disabled and then a line SAP is activated. After a sufficient potential difference is obtained between the bit line pair BLN, BLN , a line CSL of a selected column is activated to transfer the data to data lines DQ and DQ . The data is read in this manner. If the data is to be transferred to and stored in serial data registers, a transfer gate TRG common to all columns is activated to thereby transfer the data to the data register. At a cycle other than the transfer cycle, the transfer gate TRG takes a low level and is closed. In response to an external serial mode signal, serial gates SSL are sequentially activated to sequentially transfer and output the data in the data registers connected to respective columns, to serially input/output lines SI/O, SI/O . As described above, according to the background art, a serial register is provided for each column to conduct serial access in the column direction. The larger the memory capacity becomes, the smaller the pitch between columns becomes. It is therefore difficult to provide for each column a serial circuit portion such as serial registers. There is a tendency that a cell capacitance is made smaller, whereas the capacitance of the bit line pair BLN, BLN becomes large, mainly due to the addition of the serial circuit portion. Namely, the pitch between columns becomes large because it depends upon the serial circuit portion such as serial registers. It is therefore impossible to have a cell array with a highly efficient pattern. In addition, the read-out quantity of cell data becomes small and considerably deteriorates a sense margin. SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems and seeks to provide a semiconductor memory device allowing a cell array of a small pitch between columns without any pattern restriction at the serial circuit portion, and having a small ratio of bit line capacitance to a cell capacitance, and an improved sense margin. The present invention provides a semiconductor memory device having the features recited in claim 1. Preferred embodiments of the invention are recited in dependent claims 2 to 6. BRIEF DESCPIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention; Figs. 2A and 2B are schematic diagrams showing examples of a cell array of the memory device shown in Fig. 1; Fig. 3 is a circuit diagram showing one column of a semiconductor memory device according to the background art; Fig. 4 is a schematic diagram showing an example of a cell array according to the background art; Fig. 5 is a schematic diagram showing an example of a cell array with four divided columns according to the background art; Fig. 6 is a circuit diagram showing another embodiment of a semiconductor memory device according to this invention; and Fig. 7 is a schematic diagram showing a cell array of the memory device shown in Fig. 6. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 is a circuit diagram showing an embodiment of a part (bundled columns) of a semiconductor memory device according to the present invention. Bit lines BLN₁ and BLN ₁ constitute a bit line pair 10, and bit lines BLN₂ and BLN ₂ constitute a bit line pair 20. Each of the bit lines BLN₁, BLN₁ , BLN₂ and BLN₂ is connected with the same number of memory cells via transistors. A V PL line is a fixed electrode of a cell capacitor. The bit lines BLN1, BLN₁ , BLN2 and BLN₂ are precharged to 1/2 V cc . For example, when a word line WL₁ is activated to turn on transistors 11 and 21, the contents (data) of cells 12 and 22 appear on the bit lines BLN₁ and BLN₂ to change their potentials. The potentials on the bit lines BLN₁ and BLN₂ are respectively compared with a reference voltage 1/2 V cc on the other bit lines BLN₁ and BLN₂ and amplified by sense amplifiers (SENSE AMPLIFIER). In sensing the data, a line SAN is first disabled and then a line SAP is activated. After a sufficient potential difference is obtained between the bit line pair BLN₁ and BLN₁ , and between the bit line pair BLN₂ and BLN₂ , a line (CSL₁ or CLS₂) of a selected column is activated to transfer the data to data lines DQ and DQ . The data is read in this manner. The above operations are substantially the same as the case when a word line WL₂ is activated. The bit line pairs 10 and 20 have one different row address bit A n . The lines CSL₁ and CSL₂ are therefore accessed through decoding the column address A m and the row address bit A n . Upon such decoding, one of the partial columns 100 and 200 is selected and connected to data lines DQ and DQ to read out the data. If the data are transferred to a serial circuit portion, a transfer gate line TRG₁ or TRG₂ of a transfer gate (TRANSFER GATE) is activated in accordance with the one row address bit A m to turn on a transistor 15 or 25, to thereby transfer the sensed data of the partial column 100 or 200 to a data register (DATA REGISTER) and stored therein. The stored data are output in response to an external serial mode signal. Specifically, as shown in Fig. 1, serial select lines SSL₁ to SSL n provided for each of the blocks (bundled columns) are sequentially activated to turn on transistors 6, 6 of serial gates (SERIAL GATE). The contents of data registers for respective bundled columns are sequentially transferred and output to serial input/output lines SI/O and SI/O . Next, the cell array circuit arrangement of this embodiment will be described while comparing it with the background art. Fig. 4 is a schematic diagram showing an example of a cell array according to the background art. Word lines are divided into two groups at the center of cell array indicated by a one-dot-chain line, the groups each being accessed by a similar address except one row address bit A n . That is, 2n word lines are divided into a group of word lines WL₁ ... WL i ... WL n and a group of word lines WL n+1 ... WL n+i ... WL 2n , each group being accessed by similar address except for one row address bit A n . Fig. 2A shows an example of a cell array of the semiconductor memory of this invention. The ratio of the vertical side to the horizontal side of the array shown in Fig. 2A is about four times as large as that of the array shown in Fig. 4. The cell array shown in Fig. 2B has a ratio similar to that of the background art. This array is realized by dividing the cell array into upper and lower parts relative to the middle of the array indicated at a one-dot-chain line in Fig. 2A, and disposing them side by side as shown in Fig. 2B. With this cell array, it is not necessary to change the layout of the background art memory chip to a large extent. A part of a circuit diagram of a second embodiment of a semiconductor memory device according to this invention is shown in Fig. 6. The cell array of the memory device is schematically shown in Fig. 7. In this embodiment, four partial columns are connected to one serial circuit portion. With this arrangement, the capacitance of each bit line becomes one fourth that of the background art, and the pattern at the serial circuit portion can be designed with a pitch four times as large as that of the background art. Fig. 5 shows an example of a cell array divided into four groups according to the background art. In Fig. 5, word lines are divided into four groups each being distinguished by two row address bits A m and A n . Lines CSL₁ to CLS₄ shown in Fig. 6 are accessed by decoding one column address and the row address bits A m and A n . Transfer gate lines TRG₁ to TRG₄ are actuated in correspondence with the row address bits A n and column address bits A m . Fig. 7 illustrates a cell array, similar to Fig. 2B, wherein four columns are disposed side by side. A general cell array divided into 2 n may be realized in a similar manner. As described so far, bit cells provided for one column of the background art are divided into 2 n cell groups, and each group is connected to a different bit line pair and connected to a each sense amplifier. The capacitance of each bit line is therefore reduced by 1/2 n when compared with the background art, to thereby improve the sense margin. In addition, by bundling a number of bit line pairs, the serial circuit portion such as data registers can be patterned with a pitch 2 n times as large as that of the background art. The pitch between columns is not determined on the basis of the serial circuit portion, so that an optimum cell size can be selected. In addition, it is possible to obtain a cell layout as desired, without changing the chip layout of the background art, i.e., without changing the chip vertical/horizontal side ratio.

Claims: A dynamic address multiplexed semiconductor memory device, comprising: a memory cell array composed of a plurality of memory cells (12,22,...,N2) arranged into a matrix pattern; any specific memory cell being selectable on the basis of a row address (A n ) and a column address (A m ); and a block (30) being formed by the memory cells arranged in n, n being a positive integer larger than 2, memory cell columns (100,200), respectively so as to be selected on the basis of a column address (A m ); a plurality of sense amplifiers (SENSE AMPLIFIER) each provided for each memory cell column (100,200), for sensing and amplifying data read from the selected memory cell to a bit line (BLN, BLN ); a first data bus ( DQ , DQ ) connected to an output of each of said sense amplifiers via each of first gate means (I/O GATE), for transferring data between said sense amplifiers and said first data bus; data being transferred from any of said sense amplifiers to said first data bus, when any of the first gate means is turned on after the sense amplifier having been activated; a plurality of data registers (DATA REGISTER) each provided for each block; a second data bus (SI/O, SI/O ) connected to an output of each of said data registers via each of serial gates (SERIAL GATE) respectively; data in said data registers being transferred in series to said second data bus, when the serial gates (SERIAL GATE) are turned on in sequence; characterised by the outputs of said sense amplifiers belonging to each of the blocks being connected to an input of each of said data registers via each of second gate means (TRANSFER GATE); data of any one of said sense amplifiers belonging to each of the blocks being transferred to each of said data registers, when the second gate means is turned on; the first (I/O GATE) and second gate means (TRANSFER GATE) being activated independently. The semiconductor memory device according to claim 1, wherein all of said blocks (30) are arranged in the row direction. The semiconductor memory device according to claim 1, wherein units of one n-th of the total number of a plurality of said blocks are disposed in the row direction to form one block group, and said n units of blocks groups are disposed in sequence in the column direction. The semiconductor memory device according to claim 1, wherein the first and second gate means are activated in accordance with the row address. The semiconductor memory device according to claim 4. wherein all of said blocks are arranged in the row direction. The semiconductor memory device according to claim 4, wherein units of one n-th of the total number of a plurality of said blocks are disposed in the row direction to form one block group, and said n units of block groups are disposed in sequence in the column direction.

Inventors: IKAWA TATSUO, OHSHIMA SHIGEO, TODA HARUKI, IKAWA, TATSUO, OHSHIMA, SHIGEO, TODA, HARUKI
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1989
Main classification: G11C11
IPC codes: G11C11, H01L27