High speed differential sense amplifier for use with single transistor memory cells

Abstract: A novel circuit is provided which allows a differential sense amplifier to be utilized in conjunction with a memory array comprised of a plurality of memory cells each containing a single transistor. A differential input signal is applied to the sense amplifier based upon the binary data stored in an addressed memory cell at a rate equal to or greater than the differential input signal available in prior art differential memory cells having two transistors per cell. This is accomplished by precharging the selected bit line and a reference bit line, and then selecting the word line of the memory cell to be read, while causing the reference memory cell to conduct. The differential voltage between the selected bit line and the reference bit line is then sensed to determine the state of the data stored in the selected memory cell. The ratio of currents through the selected bit line and the reference bit line is selected to be other than one, in order to achieve a rapid differential voltage swing, and that rapid reading of the data stored within the selected memory cell.

Description: This invention pertains to memory devices, and more particularly, to sense amplifiers for use in determining the data stored in single transistor memory cells, such as EPROM memory cells. EEPROM devices are well known in the prior art and may be categorized broadly into two groups: those memory arrays which employ memory cells utilizing a single transistor and those memory arrays which employ memory cells which utilize two transistors. The advantage in utilizing two transistors per memory cell is that a differential output signal may be obtained which can be sensed by a differential sense amplifier, providing greater speed of operation and less susceptibility to errors caused by noise. However, utilizing two transistors per memory cell consumes a greater amount of surface area in an integrated circuit than memory devices utilizing a single transistor per memory cell. FIGURE 1 depicts a schematic diagram of a memory device utilizing an array of two transistor memory cells and a differential sense amplifier. For convenience, only a single memory cell formed of transistors 11 and 12 is shown, although it is well known in the art how such memory arrays comprising a plurality of memory cells, each containing two transistors, are formed and selectively addressed. Referring to Figure 1, floating gate transistors 11 and 12 each include a floating gate which is selectively charged to increase the control gate threshold voltage of the transistor to correspond to a logical zero, as compared with the control gate threshold voltage of a transistor having substantially no charge placed on its floating gate and corresponding to a logical one. In circuit 10 of Figure 1, transistors 11 and 12 are erased to be in the low threshold voltage state, i.e., each having a threshold voltage corresponding to a logical one. Then, during programming, either transistor 11 or 12 is programmed by placing a charge on its floating gate in order to increase its threshold voltage to correspond to a logical zero, thereby providing a differential data signal on BIT and BIT lines 18 and 19, which is in turn applied to the differential input leads of differential sense amplifier 20. Differential sense amplifier in turn provides a single ended output signal on output terminal 21 which is capable of being provided more quickly and with less susceptibility to noise and variations of voltage levels on leads 18 and 19 than is possible if a single ended sense amplifier were used, as depicted in the prior art structure of Figure 2. Table 1 depicts the operation of memory cell 10 during the erase and programming modes. Programmed State V T Transistor 11 BIT V T Transistor 12 BIT erased low 1 low 1 0 low 1 high 0 1 high 0 low 1 As shown in Figure 2, another type of memory array is constructed of a plurality of memory cells, each containing a single floating gate transistor, such as transistor 31. Again, for simplicity, the entire array of memory cells is not shown, such construction being well known to those of ordinary skill in the art. During a reading of a selected memory cell, BIT line 35 is connected to the input lead of single ended sense amplifier 37, which is inherently slower (due to its responding to a single ended input signal which changes voltage in one direction with respect to a reference voltage) and more susceptible to noise and variations in voltage levels on BIT line 35 (due to its lack of common mode noise rejection) than is the differential sense amplifier 20 of Figure 1 having its input leads connected to both BIT and BIT lines. The prior art circuit of Figure 3 has combined the use of a memory array having a plurality of memory cells, each containing a single floating gate transistor, with the higher speed and lower susceptibility to noise of a differential sense amplifier. For simplicity, Figure 3 shows only a single memory cell formed of transistor 101-N-1 associated with row line 102-N and BIT line 103-1. It is readily understood by those of ordinary skill in the art that the memory array actually includes a plurality of N row lines and M BIT lines, and a plurality of NxM uniquely addressable single transistor memory cells. When transistor 101-N-1 is selected for reading, row line 102-N is enabled by placing a read voltage having a voltage greater than the control gate threshold voltage of a memory array transistor which is programmed to the logical one state (no charge on its floating gate), and less than the control gate threshold voltage of a memory array transistor which is programmed to a logical zero state (a charge placed on its floating gate). BIT line 103-1 is selected by turning on column select transistors 104-1 and 105-1 and applying reference voltage VREF to the gate of transistor 106-1. As shown in Figure 3, transistors 104-1 and 105-1 serve as column select transistors connected in an AND configuration. Other addressing techniques or the use of other than two select transistors 104-1, 105-1, are well known in the art. The reference voltage applied to the gate of transistor 106-1 is approximately 2.5 to 3 volts and causes transistor 106-1 to precharge the selected column 103-1. When memory array transistor 101-N-1 stores a logical one, it turns on when selected for reading, causing differential sense amplifier input lead 107 to be connected to ground. Conversely, when memory array transistor 101-N-1 stores a logical zero it does not turn on when selected for reading due to its higher control gate threshold voltage. In this case, input lead 107 of differential sense amplifier 111 is not connected to ground, and the current I/2 supplied by array load current source 109 is not discharged to ground but is made available on high impedance input lead 107 of differential sense amplifier 111. Although not shown in Figure 3, it is well known in art that various multiplexing techniques can be used to multiplex a plurality of columns to a single differential sense amplifier, or to multiplex a plurality of output leads from a plurality of differential sense amplifiers to a single output lead of an integrated circuit. In order to provide a differential input signal to differential sense amplifier 111, a set 117 of reference transistors is provided between differential input lead 108 and ground in the same configuration as those elements located between differential input lead 107 and ground. Thus, reference set 117 includes a reference unprogrammed memory cell 101-N-REF (storing a logical one) and having its control gate connected to row line 102-N. Similarly, reference set 117 includes reference transistors 104-REF and 105-REF corresponding to column select transistors 104-1 and 105-1, respectively, with their control gates connected to VCC (typically 5 volts). Reference set 117 also includes transistor 106-REF having its control gate connected to reference voltage VREF, serving as an analog to transistor 106 1. Reference load current source 110 provides a current I equal to twice the current provided by array load current source 109. Balancing transistor 118 serves to connect the inverting and noninverting input leads of differential sense amplifier 111 prior to sensing the data stored in the selected memory cell. As shown in Figure 3, balancing transistor 118 is a P channel transistor controlled by a signal BAL applied to its gate electrode which goes high when sensing is to be performed following selection of a desired row and column defining the single memory cell to be sensed by differential sense amplifier 111. When memory array transistor 101-N-1 stores a logical zero and is selected for reading, differential input lead 107 is not connected to ground and thus when balancing is terminated (i.e., when transistor 118 turns off): Thus where ΔV₁₀₇ = the rate of change of the voltage on differential input lead 107; V₁₀₈ = the constant reference voltage to be compared to the voltage of sense node 107; I = The reference current through reference Bit line 103-REF C₁₀₇ = the capacitance on input lead 107; and dv / dt = the time rate of change of the differential input voltage between differential input leads 107 and 108. Conversely, when memory array transistor 101-N-1 stores a logical one and is selected for reading from equation (2) from equation (3) Unfortunately, the rate of change of differential input voltage in the prior art circuit of Figure 3 is only one half that developed by a prior art circuit, such as shown in Figure 1, which utilizes two transistors per memory cell. Thus, the prior art circuit of Figure 3 is slower than a prior art circuit which utilizes two transistors per memory cell. A memory circuit as defined in the preamble of patent claim 1 and a method as defined in the preamble of patent claim 9 are known from NEW ELECTRONICS, vol. 18, no. 22, Nov. 1985, p.70,73,74. The precharge sub-circuit as defined in claims 4 through 8 is known per se from EP-A-0 154 547. The teaching of the present invention may briefly summarized as follows: In accordance with the teachings of this invention, a novel circuit is provided as indicated in claim 1. It allows a differential sense amplifier to be utilized in conjunction with a memory array comprised of a plurality of memory cells each containing a single transistor, as well as a reference bit line including a reference memory cell. In accordance with the teachings of this invention, a differential input signal is applied to the sense amplifier based upon the binary data stored in an addressed memory cell at a rate equal to or greater than the differential input signal available in prior art differential memory cells having two transistors per cell. This is accomplished by precharging the selected bit line and the reference bit line, and then selecting the word line of the memory cell to be read, while causing the reference memory cell to conduct. The differential voltage between the selected bit line and the reference bit line is then sensed to determine the state of the data stored in the selected memory cell. The ratio of currents through the selected bit line and the reference bit line is selected to be other than one, in order to achieve a rapid differential voltage swing, and rapid reading of the data stored within the selected memory cell. The features and advantages of the invention will be more readily apparent upon reading the following description of a preferred exemplified embodiment of the invention and upon reference to the accompanying drawings wherein: BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 is a schematic diagram of a typical prior art memory device including a differential memory cell consisting of two transistors; FIGURE 2 is a schematic diagram of a typical prior art memory device including a single transistor memory cell and a single ended sense amplifier; FIGURE 3 is a schematic diagram of a prior art memory device utilizing single transistor memory cells and a differential sense amplifier; and FIGURE 4 is a schematic diagram of one embodiment of a memory device constructed in accordance with the teachings of this invention which utilizes single transistor memory cells and a differential sense amplifier. DETAILED DESCRIPTION One embodiment of a memory array circuit constructed in accordance with the teachings of this invention is shown in the schematic diagram of Figure 4. Once again, only a single memory array transistor 201-N-1 is shown, although it is to be understood that the memory array comprises a plurality of such memory cells having their sources connected in common, their drains connected in common, and their control gates connected to individual row lines such as row line 202-N. Connected between BIT line 203-1 and differential input lead 207 are column select transistors 205-1 and 204-1 and transistor 206-1 having its gate connected to reference voltage VREF, as in the prior art embodiment of Figure 3. Similarly, reference set 217 includes transistors 204-REF, 205-REF and 206-REF corresponding to transistors 204-1, 205-1, and 206-1, respectively, as in the case of a prior art circuit of Figure 3. The gates of transistors 204-REF and 205-REF are connected to VCC (typically 5 volts)and the gate of transistor 206-REF is connected to reference voltage VREF. However, unlike the prior art, reference memory array transistor cell 202-REF has its control gate connected to a balancing signal BAL . In addition, transistors 251 through 254 are used to precharge BIT line 203-1 and reference line 203-REF. When suitable circuitry (not shown), for example of a well-known design, detects that the address signal applied to the memory array has changed, thereby indicating that a different memory array transistor has been selected for reading, precharge signal P and balancing signal BAL go low, thereby turning off reference cell 202-REF and turning on P channel transistors 251 and 252. The source of P channel transistor 252 is connected to VCC. Since memory cell transistor 201-N-1 has been selected for reading, column select transistors 204-1 and 205-1 are turned on, as is transistor 206-1, and thus BIT line 203-1 is precharged via conducting P channel transistors 252 and 254. Since P channel transistors 253 and 254 have their sources connected in common and their gates connected in common, the ratio of currents I₂ and I₃ through transistors 253 and 254, respectively, is equal to the ratio between the sizes of transistors 253 and 254, so that In one embodiment, transistor 254 is chosen to be 2.5 times the size of transistor 253 and thus α = 2.5 (9) At this time, differential input leads 207 and 208 are precharged to a voltage level of VCC-VTP, where: VCC = the power supply voltage (typically about 5 volts); and VTP = the threshold voltage of P channel transistors (typically about 1 volt). After a time sufficient to allow BIT line 203-1 and reference line 203-REF to precharge (typically approximately 20-30 nanoseconds), balance signal BAL goes high, thus turning on reference cell transistor 202-REF and turning off balancing transistor 251. At this time, the differential signal developed between differential input leads 207 and 208 when selected memory cell 201-N-1 stores a logical one (low control gate threshold voltage) is defined as follows: I₅ = I₆ = I cell (10) and, since the selected memory transistor turns on, I₂ = I₅ = I cell and (11) I₃ = α I ₂ = α I cell ; (12) where I₂ = the current through P channel transistor 253; I₃ = the current through P channel transistor 254; I₅ = the current through BIT line 203-1; I₆ = the current through reference cell 202-REF and thus through reference bit line 203-REF; and I cell = the current through a memory cell transistor storing a logical one when selected for reading. Thus, but since V₂₀₇ = constant from equations (12) and (10) where ΔV₂₀₈ = the change in voltage on differential input lead 208; ΔV₂₀₇ = the change in voltage on differential input lead 207; and C₂₀₈ = the capacitance on differential input lead 208. For the embodiment where α = 2.5, In a typical memory device constructed in accordance with the teachings of this invention, when α = 2.5, this three fold increase in as compared to the prior art circuit of Fig. 3 results in a three fold improvement in the sense amplifier reading time of a logical one, since the bit line capacitance C₂₀₈ of this invention is equal to the bit line capacitance C₁₀₇ of the prior art circuit of Fig. 3. Naturally, α can be made to any value desired, by adjusting the size ratio of transistors 253 and 254, thus altering the improvement in reading speed of a logical one with respect to the prior art circuit of Fig. 3. Conversely, after BIT line 203-1 and reference line 203-REF are precharged, the differential input signal across leads 207 and 208 when the selected memory array transistor 207-N-1 stores a logical zero (high control gate threshold voltage) is determined as follows: but since V₂₀₇ = constant, from equation (14) Since I₃ = 0 (since precharging has ceased), and I₆ = I cell (from equation 10), In a typical memory device constructed in accordance with the teachings of this invention, this two fold increase in as compared to the prior art circuit of Fig. 3 results in a two fold inprovement in the sense amplifier reading time of a logical one, since the bit line capacitance C₂₀₈ of this invention is equal to the bit line capacitance C₁₀₇ of the prior art circuit of Fig. 3. It has been discovered that transistors 253 and 254 need not be made very large, but only sufficiently large to conduct currents I₂ and I₃, respectively. However, should transistor 253 be made rather large, a slight transient voltage will appear on differential input lead 207 when the BAL goes high and balancing transistor 251 turns off. If this occurs, it is preferable to wait a short period of time to allow the transient voltage on lead 207 to settle prior to sensing the stored data being addressed. Typically, when a relatively large transistor 253 is used, one need only wait 5 to 10 nanoseconds or so after balancing transistor 251 turns off prior to sensing the state of the stored data. Thus, in accordance with the teachings of this invention, a novel memory circuit is provided which provides a differential signal which develops at a rate equal to or greater than that of a true differential signal developed utilizing a two transistor memory cell. Although the foregoing invention has been described in some detail by way of illustration and example for purposes of clarity of understanding, it will be readily apparent to those of ordinary skill in the art in light of the teachings of this application that certain changes and modifications may be practiced within the scope of the appended claims.

Claims: A memory circuit comprising a plurality of bit lines (203-1), a plurality of word lines (202-N), a plurality of memory cells (201-N-1), each memory cell being uniquely associated with a bit line-word line pair, means (204-1, 205-1) for addressing a selected bit line, means for addressing a selected word line, a reference bit line (203-ref) including a reference memory cell (202-ref), a sense amplifier (211) having a first input lead (207) for connection to a selected bit line, a second input lead (208) for connection to said reference bit line, and an output lead (212) for providing an output signal indicative of the logical state of the data stored in a selected memory cell defined by said selected bit line and said selected word line, balancing means (251) for selectively causing said first and said second input leads to be at the same voltage level, a precharge source means (252) for providing a precharge signal, first means (253) for connecting said precharge signal to said selected bit line, thereby providing a selected bit line charging current (I2), and second means (254) for connecting said precharge signal to said reference bit line, thereby providing a reference bit line charging current (I3), said memory circuit characterized in that: said first and second means (253, 254) for connecting are sized to provide between said reference bit line charging current (I3) and said bit line charging current (I2) a predetermined ratio of current (I3/I2) greater than one. A memory device as in claim 1 further characterized in that said reference memory cell comprises a memory transistor (202 ref) programmed to a first logical state having a source connected to said reference bit line, (203 ref) a drain connected to a selected voltage level, and a control gate connected to a control signal ( BAL ). A memory device as in claim 2 further characterized in that said control signal serves to selectively cause said reference transistor to conduct, and also serves to selectively cause said balancing means (251) to cause said first and said second input leads to be at the same voltage level. A memory device as in claim 1 further characterized in that said precharge source comprises a transistor (252) having an input current handling terminal connected to a voltage source, an output current handling terminal for providing said precharge signal, and a control gate connected to a precharge control signal ( P ). A memory device as in claim 4 further characterized in that said first means for connecting comprises a first current handling terminal connected to said output current handling terminal of said precharge source, and a second current handling terminal connected to said selected bit line. A memory device as in claim 4 further characterized in that said first means for connecting comprises a transistor (253) having a first current handling terminal connected to said output current handling terminal of said precharge source, a second current handling terminal connected to said selected bit line, and a control gate connected to said selected bit line. A memory device as in claim 5 further characterized in that said second means for connecting comprises a first current handling terminal connected to said output current handling terminal of said precharge source, and a second current handling terminal connected to said reference bit line. A memory device as in claim 6 further characterized in that said second means for connecting comprises a transistor (254) having a first current handling terminal connected to said output current handling terminal of said precharge source, a second current handling terminal connected to said reference bit line, and a control gate connected to said selected bit line. A method of operating a memory device comprising a plurality of bit lines (203-1), a plurality of word lines (202-N), a plurality of memory cells (201-N-1), each memory cell being uniquely associated with a bit line-word line pair, means for (204-1, 205-1) addressing a selected bit line , means for addressing a selected word line, a reference bit line (203-ref) including a reference memory cell (202-ref), a sense amplifier (211) having a first input lead (207) for connection to a selected bit line, a second input lead (208) for connection to said reference bit line, and an output lead (212) for providing an output signal indicative of the logical state of the data stored in a selected memory cell defined by said selected bit line and said selected word line, balancing means (251) for selectively causing said first and said second input leads to be at the same voltage level, a precharge source means (252) for providing a precharge signal, first means (253) for connecting said precharge signal to said selected bit line, thereby providing a selected bit line charging current (I2), and second means (254) for connecting said precharge signal to said reference bit line, thereby providing a reference bit line charging current (I3), said method comprising the steps of: selecting a desired memory cell by selecting its associated bit line and word line; precharging said selected bit line and said reference bit line; causing said first and second input leads of said sense amplifier to have the same voltage potential; ceasing to cause said first and second input leads of said sense amplifier to have the same voltage potential, thereby allowing the voltages on said first and second input leads to change based on the current provided by said first and second means for connecting through said selected bit line and said reference bit line, respectively; and sensing the voltages on said first and second input leads to provide said output signal, characterized in that said first and second means (253, 254) for connecting are caused to provide between said reference bit line charging current (I3) and said bit line charging current (I2) a predetermined ratio of current (I3/I2) greater than one.

Inventors: AMIN ALAAELDIN A M COMPUTER EN, EMOTO BERNARD, AMIN, ALAAELDIN A. M. COMPUTER ENGINEERING DEPT., EMOTO, BERNARD
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1989
Main classification: G11C16
IPC codes: G11C16, G11C17