Unity-gain current-limiting circuit

Abstract: A highly accurate current-limiting circuit pre­ vents an output current (I OUT ) flowing through an output line (L OUT ) from exceeding a specified value (I LIM ) of an input current (I IN ) flowing through an input line (L IN ). The circuit contains a first channel device (10) controlled by a first reference voltage (V REF1 ), a current source (12) that supplies a reference current (I REF ), a second channel device (14) controlled by a second reference voltage (V REF2 ), a current bypass device (16), and a bypass control system (18). The current gain below the specified value of the input current is close to one. By suitably choosing certain of the circuit parameters, the circuit operates in a substantially temperature-independent manner.

Description: The invention relates to an electronic circuit for preventing an output current flowing through an output line from exceeding a specified value of an input current flowing through an input line. Such an electronic circuit is suitable for use in semiconductor devices and,more particularly,in circuits that limit the maximum value of a current and is known from Soclof, Applications of Analog Integrated Circuits (Prentice-Hall: 1985),pp.35-42,Fig.2-3. Current-limiting circuitry is employed in many semiconductor devices to conserve power or to achieve a predetermined maximum output current for a variable input current.For example, Soclof describes how voltage regulators use current-limiting circuits to avoid excessive power dissipation that could lead to overheating and permanent damage.The current limiters in Soclof provide a current gain that is much greater than unity at values of the input current below which significant current limiting occurs. A current-limiting circuit that achieves a current gain largely equal to one is desirable in certain applications.In such a device,the output current ideally equals the input current up to a specified value of the input current above which the output current is fixed at the specified value of the input current. Designing a simple unity-gain circuit that comes close to the ideal current transfer characteristic presents a significant challenge. It is often desirable that the circuit operate in a largely temperature-independent manner. This increases the challenge considerably. It is an object of the invention to provide a current-limiting circuit wherein the output current substantially equals the input current up to a specified value of the input current above which the output current is fixed at the specified value of the input current.An electronic circuit as specified in the opening paragraph is according to the invention characterized by a main channel, including the output line and an intermediate line coupled to the input line by way of a first node at which a first nodal voltage is present, for providing a current path between the intermediate and output lines, the intermediate line carrying a current substantially equal to the output current; a current source, coupled between a first voltage supply and a second node at which a second nodal voltage is present, for supplying a reference current; a reference channel for providing a current path between the second node and a second voltage supply; bypass means coupled to the first node for providing a current shunt away from the main channel; and control means coupled to the nodes for supplying the bypass means with a control signal that causes a portion of the input current to be diverted away from the intermediate line and through the bypass means when the input current achieves a prescribed relationship to the reference current, the diverted current portion progressively increasing as the input current increases such that the output current does not pass the specified value of the input current. This electronic circuit is a highly accurate current-limiting circuit that prevents the output current flowing through the output line from exceeding a specified value of the input current flowing through the input line. The current gain below the specified value of the input current is very close to unity. The circuit is formed with a main channel, a current source, a reference channel, a bypass means, and a control means. The main channel provides a current path between the output line and the intermediate line coupled to the input line by way of the first node at which the first nodal voltage is present. The intermediate line carries an intermediate current largely equal to the output current. The main channel preferably contains a first channel device that causes the output current to vary in a prescribed way as a function of the first nodal voltage and a first reference voltage. The output current usually increases as the magnitude of the difference between the two voltages increases. The current source, which is coupled between a first voltage supply and a second node at which a second nodal voltage is present, supplies a reference current. The reference channel provides a current path between the second node and a second voltage supply. The reference channel preferably contains a second channel device that largely sets the second nodal voltage at a value dependent on the reference current and a second reference voltage. The bypass means is coupled to the first node to provide a current shunt away from the main channel. The control means, which is coupled to the two nodes, supplies the bypass means with a control signal that causes a portion of the input current to be diverted away from the intermediate line and through the bypass device when the input current achieves a prescribed relationship to the reference current. As the input current increases, the diverted current portion progressively increases in such a way that the output current does not pass the specified value of the input current. More specifically, the control signal switches between a pair of opposite states depending on the amount of difference between the nodal voltages. Generation of the control signal at one of the states disables the bypass means so that none of the input current flows through it. The output current largely equals the input current. Generation of the control signal at the other state enables the bypass means so as to permit the requisite portion of the input current to flow through it. The control means is usually implemented with a differential amplifier and a positive feedback means in order to produce a sharp transition between the unity-gain and current-limited conditions. The first channel device is preferably formed with a first bipolar transistor having a base responsive to the first reference voltage, an emitter coupled through a first resistor to the intermediate line, and a collector coupled to the output line. The second channel device is then likewise formed with a like-polarity second bipolar transistor having a base responsive to the second reference voltage, an emitter coupled through a second resistor to the second node, and a collector coupled to the second voltage supply. The two reference voltages are typically the same. In this case, the circuit can be made to operate in a substantially temperature-independent manner by setting the ratio of the value of the second resistor to the value of the first resistor equal to the ratio of the emitter area of the first transistor to the emitter area of the second transistor. The invention will now be described with reference to the accompanying drawings in which: Fig. 1 is a block diagram of a unity-gain current-limiting circuit in accordance with the invention. Fig. 2 is a graph for output current as a function of input current for the circuit in Fig. 1. Fig. 3 is a circuit diagram for a general implementation of the circuit in Fig. 1. Fig. 4 is a circuit diagram for a preferred embodiment of the circuit in Fig. 3. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. The arrows in Figs. 1, 3, and 4 indicate the directions of positive current flow. Referring to the drawings, Fig. 1 illustrates the basic features of a current-limiting circuit configured according to the teachings of the invention. The circuit prevents an output current L OUT from exceeding a specified value I LIM of an input current I IN . Output current I OUT flows through an output line L OUT connected to a circuit output terminal T OUT . Input current I IN similarly flows through an input line L IN connected to a circuit input terminal T IN . The circuit in Fig. 1 is connected between a source of a first supply voltage V S1 and a source of a second supply voltage V S2 . The V S1 and V S2 supplies provide operating power to the circuit. The principal components of the circuit are a first channel device 10 controlled by a fixed first reference voltage V REF1 , a current source 12 that supplies a reference current I REF , a second channel device 14 controlled by a fixed second reference voltage V REF2 , a current bypass device 16, and a bypass control system 18. Channel device 10 provides a current path between output line L OUT and an intermediate line L ITM connected through a first node N1 to input line L IN . An intermediate current I ITM flows on intermediate line L ITM . The current path through device 10 is of such a nature that current I ITM is largely equal to current I OUT . I ITM is preferably within 5% of I OUT and typically differs from I OUT by 1% or less. The combination of line L ITM , device 10, and line L OUT thereby forms a main channel for current I OUT . A first nodal voltage V N1 is present at node N1. Current I OUT depends strongly on voltage V N1 . More precisely, channel device 10 causes current I OUT to vary in a prescribed manner as a function of voltages V N1 and V REF1. The relationship among these parameters usually has the characteristic that I OUT increases as the magnitude of the voltage difference between V N1 and V REF1 increases. Current source 12 is connected between the V S1 supply and a second node N2. A second nodal voltage V N2 is present at node N2. Source 12 is typically implemented in such a manner that current I REF is substantially independent of temperature and the overall power supply voltage |V S2 - V S1 |. However, I REF can be made to vary with either or both of these parameters. Channel device 14 is part of a reference channel that provides a current path between node N2 and the V S2 supply. The remainder of the reference channel consists of interconnecting lines L REF ' and L REF " which carry respectively largely equal currents I REF ' and I REF ", The difference between I REF ' and I REF " is preferably no more than 5% and is typically 1% or less. For the reason given below, current I REF ' is substantially equal to reference current I REF supplied by current source 12. This enables device 14 to set voltage V N2 at a value dependent on current I REF and voltage V REF2 . Bypass device 16 provides a shunt for selectively diverting a portion of current I IN away from the main channel and through a circuit bypass terminal T BP . Lines L BP and L Bp ' connect device 16 respectively to node N1 and terminal T BP . When device 16 is enabled (or activated), largely equal bypass currents I BP and I Bp ' flow respectively on lines L BP and L BP' . Currents I BP and I BP ' represent the diverted portion of current I IN . I BP ' is preferably within 5% of I BP and typically differs from I BP by 1% or less. Device 16 performs the current shunting when current I IN achieves a prescribed relationship to current I REF . For example, if channel devices 10 and 14 are substantially identical, shunting occurs when I IN is greater than I REF . Control system 18 supplies device 16 with a control signal V CTL that regulates the shunting. Control signal V CTL switches between a pair of opposite voltage states, referred to here as the high and low states, depending on the amount (i.e., the magnitude and sign) of the difference between voltages V N1 and V N2 . The shunting is initiated when signal V CTL goes to the high state and is terminated when signal V CTL returns to the low state. The high state may represent either a high voltage condition or a low voltage condition depending on whether V S2 is greater than or less than V S1 . Similar comments apply to the low state. Voltages V N1 and V N2 are supplied to control system 18 from nodes N1 and N2 by way of lines L₁ and L₂ that carry bias currents much smaller than currents I REF and I LIM . It is for this reason that I REF ' is substantially equal to L REF . During the time that signal V CTL is at the high state (so as to enable bypass device 16), control system 18 receives negative feedback from device 16 by way of lines L BP and L₁. System 18 operates in such a way that the negative feedback prevents the magnitude of the difference between voltages V N1 and V N2 from becoming very large. With the foregoing in mind, the circuit components interact as follows to accomplish the current-limiting function. Let "I T " represent the value of current I IN at which shunting begins. Assume (for example) that V S2 is greater than V S1 . The various currents then flow in the directions indicated in Fig. 1. Fig. 2 shows how I OUT varies with I IN . If I IN is below I T , V N1 is greater than V N2 . In response, control system 18 supplies signal V CTL at a value that falls into a voltage range representing the low state. This disables (or deactivates) bypass device 16. Substantially none of I IN flows through device 16. Neglecting the small bias current on line L₁, I ITM is substantially equal to I IN . Current I OUT thus largely equals I IN . See the left half of Fig. 2. The current gain --i.e., I OUT /I IN -- is very close to one. Increasing I IN causes I OUT to increase. Channel device 10 reduces V N1 in response to the increase in I OUT . V N1 drops to a value close to V N2 when I IN reaches transition value I T . V N1 may be slightly greater than or slightly less than V N2 at this point depending on the internal construction of control system 18. The magnitude of the voltage difference between V N1 and V N2 is usually no more than 60 millivolts when I IN equals I T . A slight further increase in I IN and a consequent slight further decrease in V N1 causes control system 18 to produce signal V CTL at a value falling into a voltage range representing the high state. Bypass device 16 becomes active. This allows (non-zero) portion I BP of current I IN to be diverted away from line L ITM and along line L BP through device 16. As I IN continues to increase beyond I T , I BP progressively increases in such a way that I OUT does not pass limiting value I LIM . More particularly, the manner in which components 16 and 18 are arranged allows I BP to change by a relatively large amount in response to a small change in the difference between V N1 and V N2 . The negative feedback through device 16 controls the difference between V N1 and V N2 . (Interaction between control system 18 and channel device 14 typically causes V N2 to rise slightly). In turn, device 10 prevents current I OUT from passing I LIM . The resulting current profile is shown in the right half of Fig. 2. The sharpness of the transition between the unity-gain and fully-limited conditions is essentially represented by the difference between I T and I LIM . This difference is, in turn, determined principally by the gain of the transfer function through components 18 and 16. using relatively simple configurations for components 16 and 18, the difference between I T and I LIM can be 5% or less to give a sharp transfer curve. Turning to Fig. 3, it shows internal details for a general embodiment to the current-limiting circuit in Fig. 1. The embodiment in Fig. 3 uses several three-electrode amplifiers identified by reference symbols beginning with the letter "A". Each such Ai amplifier has a first flow electrode (1E), a second flow electrode (2E), and a control electrode (CE) for controlling current flow between the flow electrodes (1E and 2E). Charge carriers, either electrons or holes, that move between the flow electrodes of each Ai amplifier originate at its first flow electrode and terminate at its second flow electrode. The current (if any) flowing in the control electrode is much smaller than that otherwise moving between the flow electrodes. Each Ai amplifier is typically a single transistor. In the case of a bipolar transistor, its emitter, collector, and base are respectively the first, second, and control electrodes. These are the source, drain, and gate, respectively, for a field-effect transistor of either the insulated-gate or junction type. Each Ai amplifier could, however, be formed with more electronic elements than just a single transistor. One example is a bipolar Darlington circuit in which the emitter of an input transistor drives the base of a trailing transistor. In this example, the control electrode of the Ai amplifier is (connected to) the base of the input transistor, while the first and second electrodes are (connected to) the emitter and collector of the trailing transistor. Certain of the Ai amplifiers are "like-configured". This means that they have corresponding elements interconnected in the same way and that each set of corresponding elements is of the same semiconductor polarity. For example, two of the Ai amplifiers are like-configured if both are NPN transistors (even though the emitter areas are different), but not if they are complementary transistors. Likewise two Darlington circuits are like-configured as long as the input transistors are of the same polarity and the trailing transistors are of the same polarity even if it is different from that of the input transistors. Channel devices 10 and 14 in Fig. 3 respectively center around like-configured three-electrode (always-on) amplifiers A1 and A2 whose control electrodes are respectively responsive to voltages V REF1 and V REF2 . The first and second electrodes of amplifier A1 are respectively coupled to lines L ITM and L OUT . The first and second electrodes of amplifier A2 are respectively coupled to node N2 and the V S2 supply. Device 10 may have a first resistor R1 connected between node N1 and the first electrode of amplifier A1. If so, device 14 has a second resistor R2 connected between node N2 and the first electrode of amplifier A2. Bypass device 16 is formed with a three-electrode switching amplifier A3 whose control electrode is responsive to signal V CTL . Amplifier A3 has its first and second electrodes respectively connected to node N1 and terminal T BP . Amplifier A3 turns on when signal V CTL goes to the high state, and vice versa. Control system 18 consists of a differential amplifier 20 and a feedback device 22. Differential amplifier 20 supplies signal V CTL from a node N3 at its output by amplifying the difference between voltages V N1 and V N2 respectively supplied to its inverting and non-inverting inputs. Device 22 provides positive feedback from the output of amplifier 20 to its non-inverting input. The positive feedback increases the gain of system 18. In turn, this reduces the magnitude of the difference between voltages V N1 and V N2 at the fully limited condition. Fig. 4 illustrates a preferred bipolar implementation for the circuit of Fig. 3. Voltages V S1 and V S2 are low and high supply voltages V EE and V CC in Fig. 4. Terminal V BP is connected to the V CC supply. The current-limiting circuit is typically part of a monolithic semiconductor integrated circuit. Amplifiers A1 and A2 and devices 10 and 14 of Fig. 4 are respectively formed with NPN transistors Q1 and Q2. Devices 10 and 14 also include resistors R1 and R2 in Fig. 4. Device 16 is implemented with an NPN transistor Q3. Differential amplifier 20 centers around largely identical NPN transistors Q4 L and Q4 R whose bases receive voltages V N1 and V N2 . A current source 24 is connected between the V EE supply and the interconnected emitters of transistors Q4 L and Q4 R . Their collectors are respectively connected to node N3 and the V CC supply. Another current source 26 is connected between node N3 and the V CC supply. Amplifier 20 operates in a conventional manner. Feedback device 22 consists of a PN-junction diode whose anode and cathode are respectively connected to nodes N3 and N2. The diode is preferably an NPN transistor Q5 having its collector tied back to its base. When signal V CTL goes to the high state, transistor Q5 turns on largely in synchronism with transistor Q3. The positive feedback through transistor Q5 causes V N2 to rise slightly due to interaction with transistor Q2. The following relationships respectively define the operation of devices 10 and 14: V REF1 - V BE1 - R 1 I ITM = V N1 V REF2 - V BE2 - R 2 I REF ' = V N2 V BE1 and V BE2 are the respective base-to-emitter voltages of transistors Q1 and Q2. R₁ and R₂ are the respective resistances of resistors R1 and R2. The base-to-emitter voltage of an NPN transistor approximately equals kT/q multiplied by the natural logarithm of the collector current divided by the transistor saturation current, where k is Boltzmann's constant, T is the absolute temperature, and q is the electronic charge. Taking note of this along with the approximate current equalities discussed above for Fig. 1, Eqs.(1) and (2) can be converted into: R 1 I OUT + (kT/q)1n(I OUT /I S1 ) ≈ V REF1 - V N1 V N2 ≈ V REF2 - R 2 I REF - (kT/q)1n(I REF /I S2 ) I S1 and I S2 are the respective saturation currents for transistors Q1 and Q2. Eq. (3) shows that I OUT increases as the magnitude of the difference between V REF1 and V N1 increases. Eq. (4) demonstrates how V N2 can be calculated as a function of V REF2 and I REF . As mentioned above, I IN equals I T when V N1 is nearly equal to V N2 . Since I OUT largely equals I IN at that point, Eqs. (3) and (4) can be combined to give the following relationship for the transition point: I T + (kT/qR 1 )In(I S2 I T /I S1 I REF ) ≈(R 2 /R 1 )I REF + (V REF1 - V REF2 )/R 1 V REF2 preferably equals V REF1 . In addition, the saturation current ratio I S2 /I S1 substantially equals the emitter area ratio A E2 /A E1 , where A E1 and A E2 are the respective emitter areas of transistors Q1 and Q2. Eq. (5) reduces to: I T + (kT/qR 1 )1n(A E2 I T /A E1 I REF ) ≈(R 2 /R 1 )I REF It is usually desirable that the invention be substantially insensitive to changes in temperature. This is achieved in Fig. 4 by choosing the values of circuit parameters in such a way that the parenthetical portion of the logarithmic term in Eq. (6) equals one so that the logarithmic term equals zero. As a result: I T /I REF = A E1 /A E2 ≈ R 2 /R 1 Resistances R₁ and R₂ vary with temperature. However, the temperature dependencies largely "cancel out" in the ratio R₂/R₁. Eq. (7) thereby establishes the conditions that enable the circuit in Fig. 4 to operate in a substantially temperature independent manner. In the preferred embodiment, V EE and V CC are nominally 0 and 5 volts. V REF1 and V REF2 are both 2.5 volts. R₁ and R₂ are both 1,000 ohms. A E2 equals A E1 . I REF is 200 microamperes. I T and I LIM are about 210 and 220 microamperes. Differential amplifier 20 has a gain of approximately 1,000. While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed before. For example, semiconductor elements of opposite polarity to those described above may be used to achieve the same results. Temperature compensation similar to that described above can be achieved when the invention is implemented with field-effect transistors. Various modifications and applications may be thus made by those skilled in the art without departing from the true scope and spirit of the invention as defined in the appended claims.

Claims: An electronic circuit for preventing an output current (I OUT ) flowing through an output line (L OUT ) from exceeding a specified value of an input current (I IN ) flowing through an input line (L IN ), characterized by: a main channel (10), including the output line (L OUT ) and an intermediate line(L ITM ) coupled to the input line (L IN ) by way of a first node (N1) at which a first nodal voltage (V N1 ) is present, for providing a current path between the intermediate (L ITM ) and output (L OUT ) lines, the intermediate line (L ITM ) carrying a current substantially equal to the output current; a current source (12) coupled between a first voltage supply (V S1 ) and a second node (N2) at which a second nodal voltage (V N2 ) is present, for supplying a reference current (I REF ); a reference channel (14) for providing a current path between the second node (N2) and a second voltage supply (V S2 ) ; bypass means (16) coupled to the first node (N1) for providing a current shunt away from the main channel (10); and control means (18) coupled to the nodes (N1,N2) for supplying the bypass means (16) with a control signal (V CTL ) that causes a portion of the input current (I IN ) to be diverted away from the intermediate line (L ITM ) and through the bypass means (16) when the input current (I IN ) achieves a prescribed relationship to the reference current (I REF ), the diverted current portion progressively increasing as the input current (I IN ) increases such that the output current (I OUT ) does not pass the specified value of the input current (I IN ). A circuit as in Claim 1 characterized in that: the main channel (10) comprises a first channel device (10) that causes the output current (I OUT ) to vary in a prescribed way as a function of the first nodal voltage (V NI ) and a first reference voltage (V REF1 ); the reference channel (14) comprises a second channel device (14) that substantially sets the second nodal voltages (V N2 ) at a value dependent on the reference current (I REF ) and a second reference voltage (V REF2 ); and the control signal (V CTL ) switches between a pair of opposite states depending on the amount of difference between the nodal voltages (V N1 , V N2 ). A circuit as in Claim 2 characterized in that the output current (I OUT ) increases as the magnitude of the difference between the first nodal voltage (V N1 ) and the first reference voltage (V REF1 ) increases. A circuit as in Claim 2 characterized in that generation of the control signal (V CTL ) at a selected one of the states causes the bypass means (16) to be disabled, substantially none of the input current (I IN ) flowing through the bypass means when it is disabled. A circuit as in Claim 2 characterized in that: the first channel device (10) comprises a first amplifier (A1) having a first flow electrode coupled to the intermediate line (L ITM ), a second flow electrode coupled to the output line (L OUT ), and a control electrode responsive to the first reference voltage (V REF1 ) for controlling current flow between the flow electrodes of the first amplifier (A1); and the second channel device (14) comprises a second amplifier (A2) having a first flow electrode coupled to the second node (N2), a second flow electrode coupled to the second voltage supply (V S2 ), and a control electrode responsive to the second reference voltage (V REF2 ) for controlling current flow between the flow electrodes of the second amplifier (A2). A circuit as in Claim 5 characterized in that: the first channel device (10) includes a first resistor (R1) coupled between the intermediate line (L ITM ) and the first electrode of the first amplifier (A1); and the second channel device (14) includes a second resistor (R2) coupled between the second node (N2) and the first electrode of the second amplifier (A2). A circuit as in Claim 6 characterized in that the first (A1) and second (A2) amplifiers respectively comprise first (Q1) and second (Q2) like-polarity bipolar transistors, each having an emitter, a collector, and a base respectively coupled to the first, second, and control electrodes of its amplifier. A circuit as in Claim 7 characterized in that: the reference voltages are substantially the same; and R₂/R₁ is substantially equal to A E1 /A E2 , where R₁ and R₂ are the respective resistances of the first (R1) and second (R2) resistors, and A E1 and A E2 are the respective areas of the emitters of the first (Q1) and second (Q2) transistors. A circuit as in Claim 5, 6, 7 or 8 characterized in that the control means (18) comprises a differential amplifier (20) having an inverting input for receiving the first nodal voltage (V N1 ), a non-inverting input for receiving the second nodal voltage (V N2 ), and an output for supplying the control signal (V CTL ) as an amplification of the difference between the nodal voltages (V N1 ,V N2 ). A circuit as in Claim 9 characterized in that the control means (18) includes feedback means (22) for providing positive feedback from the output of the differential amplifier to its non-inverting input. A circuit as in Claim 9 characterized in that the bypass means (16) comprises a further amplifier (A3) having a first flow electrode coupled to the first node (N1), a second flow electrode coupled to the second voltage supply (V S2 ), and a control electrode responsive to the control signal (V CTL ) for controlling current flow between the flow electrodes of the further amplifier (A3).

Inventors: BLAUSCHILD ROBERT ALAN, BLAUSCHILD, ROBERT ALAN
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1989
Main classification: G05F1
IPC codes: H02H9, H03G11, G05F1