Digital signal processor

Abstract: The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reduceing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.

Description: The present invention relates to a digital signal processor capable of performing an arithmetic processing of mainly a signal series and in particular to a DMA transfer between an external memory and an internal register in a digital signal processor. In "A DSP architecture for 64 KBPS motion video codec" by Tokumichi Murakami et al in: Proceedings of the International Symposium on Circuits and Systems, ESPOO, Finland, June 7-9, 1988, IEEE New York (US), Vol. 1, pages 227-230, an architecture for a digital signal processor according to the precharacterizing clause of claim 1 is described. This digital signal processor - a VLSI processor based on a 24-bit fixed point architecture - is dedicated for a video codec performing several coding sequences in real time. The architecture contains busses, data memories, an execution unit, adjecent generators, sequencer and DMAC. Fig. 1 is a schematic block diagram of the digital signal processing processor disclosed in "A 50nS FLOATING-POINT SIGNAL PROCESSOR VLSI", P.401, Proceedings of ICASSP 86, 1986. It should be noted that for the sake of simplicity, only necessary blocks are shown in Fig. 1. In the block diagram of Fig. 1, reference numeral 1 denotes an instruction memory for storing an instruction word; 3 indicates an instruction execution control unit for controlling various operations of decoding the instruction word and calculations; 5 is a data bus for mutually connecting the following sections with each other and for mainly performing a data transmission; 4 is an internal data memory for storing the calculation data; 6 represents a calculating unit for performing various calculations with respect to two pieces of data which have been transferred from the data bus 5; 8 denotes an address generating unit capable of generating at most 3 addresses at the same time; 10 represents an external data memory connecting unit for controlling the read/write operations to an external data memory (not shown); 78 is an external address bus; 79 denotes an external data bus; 80 indicates an external device control signal bus; 81 is a serial port (referred to as an "SIO" hereinafter) for performing a serial data transmission between external devices (not shown in detail); and, reference numeral 82 denotes a direct memory access control unit (referred to as a "DMAC" hereinafter) for controlling a direct memory access data transfer (referred to as a "DMA" hereinafter) between SIO 81 and external data memory connecting unit 10. Fig. 2 illustrates a timing chart of external data memory accessing operations of the digital signal processor shown in Fig. 1. Fig. 2a is a read timing chart and Fig. 2b is a write timing chart. In Figs. 2a and 2b, reference numeral 291 is an external address terminal; 292 represents a strobe signal for controlling the read timing supplied from the external data memory; 293 is an external data terminal; and, 294 represents a strobe signal for controlling write timing to the external data memory. An operation of the digital signal processor will now be described. In Fig. 1, the instruction word of the designated address is read out from the instruction memory 1, and input via an input/output path 201 to the instruction execution control unit 3. The control signal and data which have been decoded by the instruction execution control unit 3 are transferred via an output path 202 to the data bus 5. In response to this control signal, calculation data from the internal data memory 4 to the data bus 5 is read via an output path 203, the data from the data bus 5 is input via an output path 204 to the calculation unit 6, the calculating process and calculation result at the calculation unit 6 is output via an output path 205 to the data bus 5, the data sent from the data bus 5 to the internal data memory 4 is written via an output path 206, and various operations such as the external data memory access are controlled. Both the address of the input data from the internal data memory 4 to the calculation unit 6 and the writing address of the output data from the calculation unit 6 to the internal data memory 4 are controlled by the address generating unit 8 having three systems of address generators. This address generating unit 8 generates the address with the readable/writable data input from the data bus 5 via an input/output path 210, controls the internal data memory 4 and the external data memory connection unit 10 in response to the data which has been output via output paths 208 and 209, and determines the input data and output data write destination to the calculation unit 6. When, on the other hand, data is set to a specific register of DMAC 82 via the data bus 5 and a path (not shown), DMA is initialized. Once DMA is initialized, all of operations other than the DMA transfer are interrupted, and the data transfer is carried out from SIO 81 to the external data memory connection unit 10 via the output path 208 and data bus 5. The transfer word number is set into the specific register of DMAC 82 in response to the instruction which has been previously output via the output path 201. As the settable transfer word numbers, a selection is made to only 64, 128, 256 and 512 words. A description will now be made to Fig. 2. When the readout operation of the external data memory is carried out as shown in Fig. 2a, an RE terminal of the external device control signal bus 80 becomes active for 1 machine cycle, the strobe signal 292 informs the external device of the data readout, and the address data is output from the external address bus 78 for 1 machine cycle. Furthermore, the data read from the external device is fetched at the trailing edge of the same cycle. When the writing operation of the external data memory as shown in Fig. 2b is carried out, a WE terminal of the external device control signal bus 80 becomes active for 1 machine cycle, the data writing operation is announced to the external device, the address data is output from the external address bus 78 and the write data is output from the external data bus 79 for one machine cycle. Since the second conventional digital signal processor is arranged as described above, the following problems exist: a). Since no direct data transfer is carried out between the internal data memory and external data memory, the processing efficiency of the internal calculation is lowered. b). When the external data memory is accessed by way of the direct data transfer, the address of the external data memory is simple increasing sequence and the transfer word number cannot be arbitarily designated, so that it is difficult to directly transfer the two-dimensional block data. c). Since the internal calculation of the processor is interrupted when the direct data transfer is carried out, the processing efficiency of the internal calculation is extremely lowered. d). Since the external address output is fixed at 12 bits, the accessing region of the external data memory is narrow. It is an object of the present invention to provide a high-speed digital signal processor having a simpler circuit arrangement and being more flexible in accessing different types of external memories. To achieve this object, a digital signal processor according to the present invention comprises: an instruction memory for storing instruction words defining internal operations; an instruction execution control unit for decoding said instruction words read from said instruction memory in a predetermined order; a calculation unit for performing various calculations on two input data transferred from a data bus and from an internal data memory storing calculation data; a data output bus for transferring a calculation result derived from said calculation unit to said internal data memory; an adress generating unit for generating addresses to identify the write destinations of data; an external data memory connecting unit for reading and writing the data between an external data memory and said data bus in response to values output from said address generating unit; characterized by a mode register for setting an access method of said external data memory; a direct memory transfer bus for connecting one of the ports of said internal data memory to said external data memory connecting unit; and, a direct memory access control unit for inputting and outputting the data in units of block between said external data memory connecting unit and said internal data memory via said direct memory transfer bus; said direct memory access control unit including an address output mode unit for holding information to select between a high speed memory access mode and a low speed memory access mode, in said low speed memory access mode, both an upper part of an address and a lower part of an address is outputted in subsequent machine cycles to said external data memory, in said high speed memory access mode only the lower part of an address is output thereto; and a memory connecting unit for holding selection information, said selection information being either indicative of whether or not a read/write completion signal from said external data memory is detected during the use of the low speed mode, or being indicative of the use of the high speed mode wherein after the lower part of the address is output, the read and write operations are accomplished in one machine cycle. In accordance with the digital signal processor of the invention, from an address terminal in the external data memory connecting unit, both an upper address and lower address can be output in two machine cycles, and the two-dimensional block transfer can be performed without decreasing the efficiency of the internal calculation by employing the DMA bus in the direct data memory transfer control unit. With an employment of the mode register and direct data memory control register, the external address output format and connecting memory in program and direct data memory transmission can be independently set, so that, for instance, the small region at the high-speed memory can be accessed in the program, and the large region at the low-speed memory can be accessed in DMA. The present invention will now be described by way of example in explaining a preferred embodyment with reference to the accompaning drawings : Fig. 1 is a schematic block diagram of a conventional digital signal processor; Fig. 2 is an access timing chart of an external data memory employed in the conventional digital signal processor according to Fig. 1; Fig. 3 is a schematic block diagram showing a digital signal processor according to a preferred embodiment of the invention; Fig. 4 is a block diagram showing an arrangement of the direct memory access control unit shown in Fig. 3; Fig. 5 is a diagram for showing DMA transfer regions in an internal data memory and an external data memory; Fig. 6 is a diagram for representing a register arrangement example for setting external data memory access methods of a programmed transfer and a DMA transfer; Fig. 7 is a timing chart in case that the external data memory is accessed by the programmed and DMA transfer; Fig. 8 is a timing chart of the external data memory access in an external data memory connecting unit shown in Fig. 3. A description of a preferred embodiment of the invention will now be made. Fig. 3 is a schematic block diagram of a digital signal processor according to the present invention. It should be noted that the same reference numerals will be employed for denoting the same or similar circuit elements shown in Fig. 1 and no further explanation thereof will be made. In the processor shown in Fig. 3, reference numeral 83 indicates a mode register for setting the access method of the external data memory; 84 indicates an output bus for outputting the calculation result; and 85 is a direct data transfer bus. Furthermore, reference numeral 211 is an input/output path of the data from the data bus 5 to the mode register 83; 212 is an output path of the control signal from the mode register 83 to the external data memory connecting unit 10; 263 indicates an input/output path of the data from the direct data memory transfer bus 85 to the data memory 4; 264 indicates an input/output path of the data between the direct data memory transfer bus 85 and external data memory connecting unit 10; and reference numeral 265 indicates an output path of the data from the data output bus 84 to the external data memory connecting unit 10. Fig. 4 is a schematic block diagram of an arrangement of DMAC 82 employed in Fig. 3. In Fig. 4, reference numeral 231 indicates a frame horizontal size register (dmfhr) for representing a horizontal size of a two-dimensional address space (domain); 232 denotes a block horizontal size register (dmbhr) for representing a horizontl size of a rectangular portion within the two-dimensional address space; 233 denotes a block start address register (dmbsr) for indicating a head address of the external data memory to execute a DMA transfer; 234 represents an internal memory start address register (dmssr) for indicating a head address of the internal data memory to execute the DMA transfer; 235 represents a word register (dmwcr) to indicate the number of words of the DMA transfer; 236 indicates a DMAC register (dmcr) for selecting an external address output mode at the DMA transfer, and the external memory; 237 is a DMA address calculation unit; and reference numeral 238 is a DMA transfer control unit to control the DMA transfer. Furthermore, reference numeral 271 is an input/output path of the frame horizontal size register 231; 272 is an input/output path of the block horizontal size reigster 232; 273 indicates an input/output path of the block start address register 233; 274 is an input/output path of the internal memory start address register 234; 275 is an input/output path of the word register 235; and reference numeral 276 is an input/output path of the DMAC register 236. In addition, reference numeral 277 indicates an output path for the internal data memory address of the DMA transfer from the DMA address calculation unit 237; 278 is an output path for the external data memory address of the DMA transfer from the DMA address calculation unit 237; and 279 denotes an output path for outputting the control signal such as a DMA transfer word number from the DMA transfer controlling unit 238 to the DMA address calculating unit 237. Fig. 5 illustrates an example of a transfer region of the DMA transfer performed between the internal data memory 4 and external data memory 241 by DMAC 82 shown in Fig. 4. Fig. 6 is a diagram for illustrating bit arrangements of the DMCA register 236 shown in Fig. 4 and the mode register 83 shown in Fig. 3. In Fig. 6, symbol "A" denotes preliminary bits, symbol "B" indicates a first bit of an address output mode, and symbol "C" indicates a zeroth bit of a memory connection mode. Fig. 7 illustrates a timing example where the external data memory is accessed by the programs and DMA's. An operation of the digital signal processor will now be described. The instruction word read from the instruction memory 1 is input to the instruction execution controlling unit 3 via the input/output path 201. In response to the control signal decoded by this instruction execution controlling unit 3, the calculation data from the internal data memory 4 to the data bus 5 is read via the output path 203, whereas the data from the data bus 5 is input to the calculation unit 6 via the output path 204. The calculation processing result at the calculating unit 6 is output to the data output bus 84 via the output path 205, the data from the data output path 206 is written to the internal data memory 4, and also the data from the data output bus 84 is written into the external data memory connecting unit 10 via the output path 265. Both the address of the input data which has been input from the internal data memory 4 via the output path 204 and a write destination address of the internal data memory 4 of the output data which has been output from the calculation unit 6 via the output path 205 to the data output bus 84, are controlled by the address generating unit 8 having three-line address generators. The address generating unit 8 generates addresses by using readable/writable data which has been supplied from the data bus 5 via the input/output path 210, and controls of the internal data memory 4 and external data memory connecting unit 10 are performed by using the data output via the output path 208 and 209, respectively, so as to determine the write destinations of the input data and output data to the calculating unit 6. The access mode of the external data memory 241 by means of the external data memory connecting unit 10 is determined by a value which has been set via the data bus 5 into the mode register 83 in accordance with the instruction word read from the instruction memory 1. When, on the other hand, the data is set into the specific register of DMAC 82 via the data bus 5 based upon the above-described instruction word, the DMA transfer is initialized. The external data memory connecting unit 10 is controlled by DMAC 82 independently to carry out the data transfer between the internal data memory 4 and external data memory 241 via the input/output paths 263 and 264, and direct data transfer bus 85. The DMA transfer controlling unit 238 performs an initialization of the DMA transfer by means of the data which has been set in the DMA address calculating unit 237 via the data bus 5. The DMA address calculating unit 237 generates a two-dimensional block address 278 with respect to the address of the external data memory 241, and also an ascending one-dimensional address 277 with respect to the internal data memory 4 based upon the values of the frame horizontal size register 231, block horizontal size register 232, block start address register 233 and internal memory start address register 234. In the DMA transfer controlling unit 238, when the DMA transfer word number which has been set in the word register 235 is ended, a termination signal is sent to the DMA address calculating unit 237. As shown in Fig. 5, the above-described DMA transfer can be performed between arbitrarily rectangular regions (k-line x 1-column in Fig. 5) of the external data memory 241 from the arbitrary address (address "t" in Fig. 5) and of the internal data memory 4 from the arbitrary address (address "S" in Fig. 5). As shown in Fig. 6, when both the zeroth bits of the mode register 83 and DMAC register 236, which indicate the memory connecting mode, are "0", it is a waiting mode waiting until the read/write completion signal from the external device is detected during the use of the low-speed memory. To the contrary, when the zeroth bit indicating the memory connecting mode is "1", it is such a mode that after the lower bits of the address are output, the read and write operations are accomplished in one machine cycle. When the first bit, which indicates the address output mode, is "0", both the upper and lower bits of the address are output in two machine cycles, whereas when this bit is "1", only the lower bits of the address are output in one machine cycle. By independently setting the mode register 83 and DMAC register 236, the external memory access from the program and DMA can be independently carried out. In Fig. 7, there is shown an access timing example of the external data memory 241 in case that "1" are set as the address output mode and as the memory connecting mode in the mode register 83 shown in Fig. 6, and "0" are set as the address output mode and as the memory connecting mode in DMAC register 236. The access to the external data memory 241 from DMAC 82 is accomplished by detecting the read/write completion signal from the external device in case of the low speed memory (n' machine cycles in Fig. 7), whereas the external data memory access from the program is completed in 1 machine cycle in case of the high speed memory. The external data memory access by DMA is continuously performed unless the external data memory access is effected by the program. Then, when the external data memory access is executed by the program, the access operation by DMAC 82 is interrupted and after the access operation by the program is accomplished, the process is restarted. Fig. 8 is a timing chart of the external data memory access (read out) in the external data memory connecting unit 10 shown in Fig. 3. It should be noted that same reference numerals will be employed for denoting the same or similar circuit elements shown Fig. 2, and no further explanation thereof is made. In Fig. 8, reference numeral 251 is a signal for controlling upper address timings when the address is output (referred to as an "AHE"); 252 is a signal for controlling lower address timings when the address is output (referred to as an "ALE"); 253 indicates a signal for announcing to the external device whether or not the external data memory access is executed by the processor or DMA (referred to as a "P/D"); and reference numeral 254 is a read/write completion signal from the external device (referred to as a "DTACK"). When the high speed memory shown in Fig. 8(a) is used, AHE 251 is asserted in the first machine cycle and also the upper address is output from an external address terminal 291 of the address bus 78, both ALE 252 and RE 292 are asserted in the second machine cycle, and the data from an external data terminal 293 of an external data memory 241 is fetched at the trailing edge of the second machine cycle. When the low speed memory as shown in Fig. 8(b) is used, AHE 251 is asserted in the first machine cycle and also the upper address is output from the external address terminal 291 of the address bus 78, both ALE 252 and RE 292 are asserted in the second machine cycle, RE 292 is negated and the data from the external data terminal 292 of the external data memory 241 is fetched at the trailing edge of a cycle where the external device asserts DTACK 254. Furthermore, ALE 252 is negated at the trailing edge of the cycle where DTACK 254 negated. As above-described, the external data memory connecting unit 10 has the following features. (a). The connecting unit 10 includes two address output modes to the external data memory. In one address output mode, both the upper and lower addresses are output in two machine cycles, so that all of external data memory regions can be accessed. In the other address output mode, the lower address is output only in one machine cycle, so that the specific region of the external data memory 241 can be accessed at a high speed. These two modes are changed by the value of the mode register set by an instruction. (b). It is possible to connect two types of external data memory 241. One is the high speed memory where after the lower address is output, the read/write operation is accomplished in one machine cycle. The other is the low speed memory where it is waited until the read/write completion signal from the external device is detected. These two types are changed by the value of the above-described mode register. The direct data memory transfer unit has the following features. (c). In accordance with the direct memory control register set by an instruction, the above-described two address output modes and two types of external data memory connections are available independent from the external data memory access by an internal instruction based upon the value of the mode register. (d). The address designation with respect to the external data memory connecting unit is so arranged in a manner that the rectangular portion of k-lines by l-columns (k, l are integers) in the two-dimensional address space of m-lines by n-columns (m, n are positive integers) are sequentially designated. The address with respect to the internal data memory is designated from an arbitrary starting address in an ascending order, and the two-dimensional data transfer is performed between the external data memory and internal data memory. Further, when the data transfer is commenced, the transfer direction and transfer data number are designated by an instruction, so that the data input/output and internal calculation process with the external data memory are executed in parallel in units of rectangular block of k-lines by l-columns. It should be noted that in the above-described preferred embodiment, a description was made that the number of the external address terminals was 16 bits, however other terminal numbers may be utilized.

Claims: A digital signal processor comprising: an instruction memory (1) for storing instruction words defining internal operations; an instruction execution control unit (3) for decoding said instruction words read from said instruction memory (1) in a predetermined order; a calculation unit (6) for performing various calculations on two input data transferred from a data bus (5) and from an internal data memory (4) storing calculation data; a data output bus (84) for transferring a calculation result derived from said calculation unit (6) to said internal data memory (4); an address generating unit (8) for generating addresses to identify the write destinations of data; an external data memory connecting unit (10) for reading and writing the data between an external data memory (241) and said data bus (5) in response to values output from said address generating unit (8); characterized by a mode register (83) for setting an access method of said external data memory (241); a direct memory transfer bus (85) for connecting one of the ports of said internal data memory (4) to said external data memory connecting unit (10); and, a direct memory access control unit (82) for inputting and outputting the data in units of block between said external data memory connecting unit (10) and said internal data memory (4) via said direct memory transfer bus (85); said direct memory access control unit (82) including an address output mode unit (236) for holding information to select between a high speed memory access mode and a low speed memory access mode, in said low speed memory access mode both, an upper part of an address and a lower part of an address is outputted in subsequent machine cycles to said external data memory (241), in said high speed memory access mode only the lower part of an address is outputted thereto; and a memory connecting unit for holding selection information, said selection information being either indicative of whether or not a read/write completion signal from said external data memory (241) is detected during the use of the low speed mode, or being indicative of the use of the high speed mode wherein after the lower part of the address is output, the read and write operations are accomplished in one machine cycle. A digital signal processor as claimed in claim 1, characterized in that said direct memory access control unit (82) includes: a frame horizontal size register (231) connected to said data bus (5) for representing a horizontal size of a two-dimensional address space; a block horizontal size register (232) for representing a horizontal size of a rectangular portion in the two-dimensional address space; a block start address register (233) for indicating a head address of said external data memory (241); an internal memory start address register (234) for representing a head address of said internal data memory (4); a word register (235) for indicating a transfer word number; a DMAC register (236) for selecting an external address output mode and an external memory connection mode; a DMA address calculation unit (237) for performing an address calculation of said external data memory; and a DMA transfer control unit (238) for performing a direct memory access transfer. A digital signal processor as claimed in claim 2, characterized in that said DMA address calculation unit (237) includes: means for generating a two-dimensional block address supplying to said external data memory (241) and a one-dimensional address supplying to said internal data memory (4), based upon the respective values which have been set in said frame horizontal size register (231), block horizontal size register (232), block start address register (233), and internal memory start address register (234). A digital signal processor as claimed in claim 3, characterized in that said external data memory connecting unit (10) includes: changing means for inputting/outputting data between said direct memory transfer bus (85) and said external data memory (241) in case that the address of said external data memory (241) is designated by said direct memory access transfer control unit (238), and for inputting/outputting data between said external data memory (241) and either the data bus (5) or the data output bus (84) when the address of said external data memory (241) is designated by said address generating unit (8). A digital signal processor as claimed in claim 4, characterized in that said external data memory connecting unit (10) further includes: mode setting means for changing an address mode output to said external data memory (241) in accordance with a set value of said mode register (83) or said address output mode unit of the DMAC register (236), and for changing such a condition that the read/write completion signal is input or not in response to said set value of said mode register (83) or said memory connecting unit of the DMAC register (236). A digital signal processor as claimed in claim 5, characterized in that said digital signal processor including means for interrupting data input/output operations between said direct memory transfer bus (85) and said external data memory connecting unit (10) in case that an access request to said external data memory (241) is generated by said calculation unit (6) during inputting/outputting data between said external data memory (241) and said direct memory transfer bus (85), and for inputting/outputting data between said external data memory (241) and either of said data bus (5) and said data output bus (84).

Inventors: KAMIZAWA KOH, KINJO NAOTO, MURAKAMI TOKUMICHI, OHIRA HIDEO, WAKABAYASHI TAKAO, KAMIZAWA, KOH, KINJO, NAOTO, MURAKAMI, TOKUMICHI, OHIRA, HIDEO, WAKABAYASHI, TAKAO, KAMIZAWA, KOH C/O MITSUBISHI DENKI, KINJO, NAOTO C/O MITSUBISHI DENKI, MURAKAMI, TOKUMICHI C/O MITSUBISHI DENKI, OHIRA, HIDEO C/O MITSUBISHI DENKI, WAKABAYASHI, TAKAO C/O MITSUBISHI DENKI
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1989
Main classification: G06T1
IPC codes: H04N7, G06T7