MONOLITHIC PRESSURE SENSITIVE INTEGRATED CIRCUIT AND A PROCESS FOR MANUFACTURE THEREOF

Abstract: A monolithic pressure sensitive silicon integrated circuit is formed by first providing a localized etch-stop layer (12) on one surface of the silicon chip (10), then growing successive epitaxial layers (14,16) of opposite conductivity types over this surface. In the upper of the two layers, there is formed a bridge of four piezoresistors (41-44) overlying the periphery of the etch-stop layer and the conditioning circuitry for amplifying the output of the bridge including both lateral (48) and vertical (50) junction transistors. The back surface of the chip is etched anisotropically to form a cavity (54) that leaves a thin diaphragm underlying the bridge of the four piezoresistors.

Description: This invention relates to a monolithic pressure sensitive integrated circuit and to a process for its manufacture. A monolithic pressure sensitive integrated circuit is a semiconductor chip in which there are combined a pressure sensitive diaphragm, its piezoresistors, and the circuitry used to process or condition the signal developed by the piezoresistors to make it useful for its designed purpose. Pressure sensors are of particular use for automotive applications. An article entitled "A Pressure Sensor for Automotive Applications" by J. A. Oakes, Proceedings of the Third International Conference on Automotive Electronics , PPS. 143-149, 20-23 October, 1981, London, England, sponsored by the Institute for Mechanical Engineers, describes a pressure sensor for automotive applications that uses two separate chips and a hybrid substrate. One chip includes the sensitive pressure diaphragm and its associated piezoresistors; the second chip includes electronics for amplifying the signal received from the piezoresistors; and the hybrid substrate includes additional conditioning circuits. A monolithic chip to replace such two chips and hybrid substrate has a number of obvious advantages. A process for preparing a monolithic pressure sensor which combines both the pressure sensitive elements and conditioning electronics is described in US Patent No. 4,618,397. However, the present invention in one aspect is a process for making a monolithic pressure sensor by a different process believed to be more reliable, manufacturable and to yield an improved pressure sensor. A process for manufacturing a monolithic pressure sensitive integrated circuit, and a monolithic pressure sensitive integrated circuit in accordance with the present invention are characterised by the features specified in the characterising portions of claims 1 and 4 respectively. In particular, in the process of the present invention, greater use is made of multifunction steps whereby there can be reduced the total number of steps in the process. For example, the diffusion step used to form base zones of vertical (junction) transistors and emitter and collector zones of lateral transistors included in the conditioning circuitry is also used to form diffused piezoresistors used for sensing. In the manufacture of a monolithic pressure sensitive integrated circuit in accordance with an example of the invention, there is first prepared as the starting material a monocrystalline semiconductive wafer that is lightly doped n-type. The wafer is cut so that both its major top and bottom surfaces lie along 〈100〉 crystal planes and are appropriately separated to provide a thickness to the wafer sufficient to facilitate handling of the wafer. Typically, the wafer is large enough in lateral area to accommodate many pressure sensors and ultimately the wafer will be diced to form many chips each including one or more pressure sensors. The description will focus on the preparation of an individual pressure sensor for reasons of simplicity. There is then formed in the top surface of the wafer for each pressure sensor a heavily doped p-type etch-stop layer that will be used to control the degree of localized thinning of the wafer to form the diaphragm of each pressure sensor. Then a first p-type epitaxial layer is grown over the top surface of the wafer, advantageously in two stages, the first with little intentional doping and the second with added p-type doping. This first epitaxial layer serves to isolate the heavily-doped etch-stop layer from a subsequently grown n-type second epitaxial layer in which the integrated circuit is to be formed. At the top of the first epitaxial layer, selected regions are treated to be heavily n-type for use as buried layers in the circuitry to be formed and other selected regions are treated to be more heavily p-type for use in forming pairs of vertical p-n junctions which are used for isolating the various elements of the circuitry to be formed. Typically, the circuitry includes at least a hundred transistors. In an illustrative embodiment these transistors include both lateral p-n-p junction transistors and vertical n-p-n junction transistors. Thereafter a second epitaxial layer of n-type conductivity, opposite that of the first epitaxial layer, is grown thereover. This second epitaxial layer is then treated to include four piezoresistors appropriately positioned over the periphery of the etch-stop layer, both vertical and lateral junction transistors in the surrounding regions, diffused resistors, and pairs of vertical p-n junctions for isolating, where necessary, the elements (components) of the circuitry in the second epitaxial layer. As previously mentioned, in the preferred embodiment, the piezoresistors, the diffused resistors, the pairs of isolation junctions, the base zones of the vertical junction transistors, and the emitter and collector zones of the lateral junction transistors are formed by a common masked p-type diffusion step. A common n-type diffusion step is then used to form the emitter zones of the vertical junction transistors and the base contact areas of the lateral transistors. The circuit elements are then interconnected on the top surface by appropriate metallization. Finally, the back surface of the original substrate is appropriately etched to form a cavity that extends to the p-type etch-stop layer, leaving the chip thinned there to form a diaphragm across which there is developed in operation the pressure differential being sensed. This pressure differential strains the four piezoresistors, positioned opposite the periphery of the diaphragm and typically connected in a Wheatstone bridge, and the change in their resistances gives rise to a voltage that is amplified by the conditioning circuitry on the chip. Additionally, the conditioning circuitry typically is adapted to provide compensation for the temperature coefficient of the piezoresistors so that temperature effects are minimized. The present invention will now be described, by way of example, with reference to the following detailed description taken in conjunction with the accompanying drawings, in which:- Figures 1 through 5 show cross-sectional views of a silicon wafer at various stages in its processing into a monolithic pressure sensitive integrated circuit (IC) in accordance with the invention; and Figure 6 is a top view of a portion of the silicon wafer to illustrate the disposition of the piezoresistors of the device relative to the diaphragm included to create the pressure sensitive region of the IC. It is to be noted that the drawings are not to scale since the vertical dimensions generally are much smaller than the horizontal dimensions. To increase clarity the scale used for Figure 6 is different than used for Figures 1-5. Referring now to Figure 1, there is shown a cross-sectional view of a portion of a wafer 10 of monocrystalline silicon, illustratively of n-type, whose resistivity is not especially critical but is typically of fairly high resistivity, for example, between one and ten ohm-centimeters, so as to be easily etched. Its thickness should be no greater than that necessary for good mechanical support, since it will eventually need to be thinned and the thicker it is initially the more the thinning that will need to be done. Typically, it's thickness will be several hundred micrometers, for example, 400 micrometers. Typically the lateral surface area of the wafer 10 is selected to be sufficiently large to accommodate at least several hundred sensors. The wafer 10 eventually will be diced up to form individual chips including usually only a single pressure sensor. The drawing shows only enough of the wafer 10 to accommodate a single pressure sensor for purposes of simplicity. The wafer 10 advantageously is prepared so that its top and bottom (major) surfaces 11 and 13, respectively, are oriented parallel to the 〈100〉 plane of the silicon crystal so that the subsequent diaphragm thinning can be done in the usual fashion by anisotropic etching of the bottom surface 13 to form uniform well defined cavities with good control of the diaphragm thickness. Typically, the bottom surface 13 is provided with a coating (not shown) to protect it during the processing of the top surface 11. Moreover, to serve as an etch-stop for the anisotropic etching, there is formed in the top surface 11 of the wafer 10 for each pressure sensor a (heavily doped) p-type layer (etch-stop region) 12, localized at the region where the diaphragm of the sensor is to be located. Typically it will be a square of about 1.78 mm (70 mils) on each side and initially about a micrometer thick. The p-type doping, which may be done either by ion implantation or diffusion, advantageously is of a concentration of at least 10¹⁹ atoms per cubic centimeter and is typically 6 x 10¹⁹ atoms per cubic centimeter. Conventional photolithographic techniques can be used to localize p-type layer 12. Referring now to Figure 2, there is shown wafer 10 after further processing with a (grown p-type) first epitaxial layer 14 over the top surface 11 of the wafer 10 which serves as a substrate. Because the first portion of the first epitaxial layer 14 tends to be p-type because of autodoping, (the outdiffusion of the p-type dopant in layer 12 into the epitaxial layer), it is feasible to begin the growth of this first epitaxial layer 14 without intentional doping but then to continue the growth in a p-type ambient in the usual fashion to insure that the growth will continue to be p-type. The broken line 15 in Figure 2 is used to denote that the first epitaxial layer 14 was grown with two portions, but this line is not included in subsequent figures to minimize unnecessary complexity in the drawing. This first epitaxial layer 14 is typically about fifteen micrometers thick and largely of a resistivity between 5 and 11 ohms-centimeter although the initially grown material may become more heavily doped because of the autodoping. As mentioned earlier, first epitaxial layer 14 serves primarily as an isolation layer to protect a (n-type) second epitaxial layer 16 (see Figure 3) which will be subsequently grown thereover and in which will be formed the elements (circuit components, i.e., piezoresistors, resistors, transistors, capacitors) of the integrated circuit being fabricated. However, before growing this second epitaxial layer 16 by conventional integrated circuit silicon technology, there are formed at the top surface of the first epitaxial layer 14 various (heavily doped) p-type regions 18 which are typically circular or square in shape. The outdiffusion (updiffusion) from these p-type regions 18 into the (n-type) second epitaxial layer 16 to be subsequently grown over first epitaxial layer 14 will help form pairs of vertical p-n junctions in such second epitaxial layer to serve as isolation junctions for dividing the second epitaxial layer into separate pockets 30 and 32 (see Figure 3) in a fashion known in integrated circuit technology. Also formed at the top surface of first epitaxial layer 14 are (heavily doped) n-type regions 20 that similarly will be useful to form low-resistivity n-type buried layers in this second epitaxial layer 16 to improve the lateral conductance in such layer for various purposes, such as insuring a low collector resistance in a vertical junction transistor formed in such second epitaxial layer. Referring now to Figure 3, there is shown wafer 10 after still further processing with a second epitaxial layer 16 whose bulk is lightly doped n-type grown over first epitaxial layer 14, typically to a thickness of about 8.5 micrometers. During the growth of the second epitaxial layer 16, outdiffusion of acceptors from p-type regions 18 will begin the formation of annular-like p-type pockets or wells 28 that eventually enclose circular n-type pockets, all of which are denoted as 30 except for a central pocket 32 opposite p-type layer 12, and isolate each such individual pocket 30,32 from the rest of the second epitaxial layer 16 by the pair of vertical p-n junctions formed by the inner and outer walls of the (annular) p-type pockets 28 and (n-type) pockets 30, 32. This permits a junction transistor to be formed in each such pocket 30. Each of the thus formed junction transistors (which are shown in Figure 4) is isolated from the others in the manner well known in silicon integrated circuit technology. Piezoresistors (which are shown in Figure 4) that will serve as the sensing elements of the sensor being fabricated are to be formed in pocket 32. Referring now to Figure 4, there is shown wafer 10 after still further processing in which piezoresistors 41, 42, 43 and 44 (only 42 and 44 are shown in this view; Figure 6 which shows a top view of all four piezoresistors) are formed in pocket 32, lateral transistors 48 are formed in some of pockets 30, and vertical transistors 50 are formed in others of pockets 30. Advantageously four separate piezoresistors are formed in pocket 32, suitable for connection together as the four arms of a Wheatstone bridge. Each of the piezoresistors 41-44 typically is a diffused p-type region that is provided with the necessary contact areas for its interconnection. A typical layout for the piezoresistors is described in the first-mentioned paper by J. A. Oakes. As mentioned earlier, there may be as many as a hundred or more elements in the conditioning circuitry depending on the sensitivity desired and the degree of compensation desired for various temperature and aging effects. Typically, one such transistor is formed in each of the enclosed pockets 30 defined by the (annular) p-type regions 28 formed by extending the earlier p-type regions 18 through the full thickness of second epitaxial layer 16. Advantageously, although not necessarily, most or all of the transistors are of the bipolar junction type. It is usually desirable to have complementary transistors (both n-p-n and p-n-p types) for circuitry that will operate with low current drain. This is achieved by forming the p-n-p types as lateral transistors 48 and the n-p-n types as vertical transistors 50 since this permits the multiple use of some of the diffusion steps of the processing. In particular, in the illustrative embodiment of the invention, there are first introduced acceptor atoms, selectively either by a common step of ion implantation or vapour-solid diffusion, to form p-type base zones 50b of the vertical transistors 50, p-type emitter 48a and collector 48c zones of the lateral transistors 48, (p-type) piezoresistors 41, 42, 43 and 44 (only 42 and 44 are shown in Figure 4; 41, 42, 43, and 44 are shown in a top view in Figure 6) in the central region 32, any other resistors (not shown) that may be needed and also the topmost portions of the p-type pockets 28. This can be followed by a common step for the selective introduction of donor atoms to form the n-type emitter zones 50a of the vertical transistors 50, and to form (heavily doped) n-type surface regions 50c to define the collector contact regions in the vertical transistors 50 and the base contact regions (not shown) in the lateral transistor 48. N-type pockets 30 serve as the base regions of each of lateral transistors 48. The introductions of the donor and acceptor atoms are localized to selected regions in the usual fashion, for example, by appropriate masks on the surface that have been patterned by photolithographic techniques familiar in integrated circuit technology. Thereafter, the various elements formed are interconnected into the desired circuit configurations by patterned metal layers (not shown) on the top surface of second epitaxial layer 16 appropriately insulated from one another, as required, by insulating layers (not shown). Finally passivating layers (not shown) are provided over the top surface of second epitaxial layer 16 to insure the desired environmental protection. Such processing will not be described in detail because it is well known in the art. Referring now to Figure 5, there is shown wafer 10 after still further processing. The bottom surface 13 of wafer 10 is thinned to form the diaphragm properly positioned with respect to the piezoresistors 41, 42, 43 and 44. This is done in conventional fashion, for example as described in the J. A. Oakes paper. Basically, there is employed anisotropic etching, using an etchant which etches different crystallographic planes at different rates. In particular, the bottom surface 13 is covered with an etch-resistant mask which is patterned to leave a square opening opposite the p-type layer 12, and this surface is then exposed to an etchant, such as potassium hydroxide or ethylene diamine, which is known to etch the 〈100〉 plane about 100 times faster than it etches the 〈111〉 plane. This etching is permitted to continue until the p-type layer 12 is reached. P-type layer 12 is heavily doped and therefore highly resistant to etching. Accordingly, it serves as an etch-stop. As a result, as is shown in Figure 5, there is formed a cavity 54 with smooth side walls that are tapered and form the side walls of a frustum of a pyramid of square cross-section whose top surface 56 corresponds essentially to a portion of the bottom surface of the p-type layer 12. Thereafter any additional layers believed useful, such as environment-protective coatings, may be provided. At this point, the preparation of the wafer 10 is essentially complete and it is then diced in the usual manner into individual chips, each of which incorporates one or more sensors, as the particular design calls for. Before use, the individual chips are usually packaged in a structure that provides a pressure difference on opposite sides of the diaphragm portion of the chip. Usually this involves providing a vacuum on one side and the pressure to be measured on the opposite side. It can also involve providing atmospheric pressure on one side and the pressure to be measured on the opposite side. Additionally, the package typically includes pins or terminals to the enclosed integrated circuit for the application of power supply voltage and the derivation of output signals for utilization. Referring now to Figure 6, there is shown an exploded top view of pocket 32 and the surrounding p-type pocket 28 which are shown in cross-sectional view in Figures 4 and 5. The broken line 36 is the outline of the diaphragm (that is, the exposed portion of a lower surface of p-type layer 12 which is denoted as, typically a square, to be formed by thinning wafer 10, and the four piezoresistors 41, 42, 43 and 44 are seen to be positioned around the outline. Each is shown provided at each of its ends with a contact region for connection into a Wheatstone bridge. When the piezoresistors 41-44 are properly located and the diaphragm is stressed, any two adjacent piezoresistors will change their resistance in opposite senses, while any two opposed piezoresistors will change in the same direction. As is known for a Wheatstone bridge, if a voltage difference is maintained between one pair of opposite corners of the Wheatstone bridge, a signal voltage will be developed across the other pair of opposite corners of the Wheatstone bridge. This voltage typically is supplied to the terminals of an operational amplifier for providing an output voltage for use in an appropriate load. For a more detailed discussion of the optimum location of the piezoresistors 41-44, particularly in sensors for use in automotive applications, reference is made to the previously mentioned J.A. Oakes paper. It is to be understood that the specific embodiment described is merely illustrative of the general principles of the invention and various modifications can be made therein without departing from the spirit and scope of the invention. It is to be appreciated that other techniques are available for forming the various elements required in the second epitaxial layer 16. Moreover, the various dimensions and doping levels mentioned are merely exemplary and other parameters are feasible and are typically dictated by the intended application. In addition other forms of circuit elements, for example, thin film or MOS transistors, diodes, resistors and capacitors, as needed, can be formed in the (top) second epitaxial layer 16 or on an overlying layer for the conditioning circuitry for use with the piezoresistors 41-44. In addition, other configurations of piezoresistors 41-44 can be formed opposite the diaphragm. Also semiconductors other than silicon can be used so long as they are sufficiently piezoresistive and are amenable to the fabrication of monolithic integrated circuits. Additionally, the particular sequence of steps described in the illustrative embodiment may be modified. In particular, the etching of the cavity 54 to form the diaphragm need not be postponed till near the end of the processing.

Claims: A process for making a monolithic pressure sensitive integrated circuit comprising: forming on one surface (11) of a monocrystalline semiconductor wafer (10) a localized etch stop region (12); growing over said one surface a first epitaxial layer (14); forming in the region overlying the etch stop region (12) a plurality of piezoresistors (41-44) and in the surrounding region the remainder of the integrated circuit and interconnecting said remainder and the piezoresistors into the desired integrated circuit; and etching anisotropically the back surface (13) of the wafer (10) in the region underlying the etch stop region (12) to thin the wafer (10) in the region underlying the piezoresistors (41-44); characterised in that a second epitaxial layer (16) of opposite conductivity to the first epitaxial layer (14) is grown over the first epitaxial layer; and in that the piezoresistors (41-44) and the remainder of the integrated circuit are formed in the second epitaxial layer (16). A process as claimed in claim 1, comprising forming in the first epitaxial layer (14) a surface region (20) having the conductivity type opposite the conductivity type of the first epitaxial layer and substantially overlying the etch-stop region (12) and a plurality of surface regions (18,20) of both conductivity types in surrounding regions; forming in the second epitaxial layer (16) by a first doping step localized regions of the opposite conductivity type for serving as the piezoresistors (41-44) in regions substantially overlying the periphery of the etch-stop region (12), base zones (50b) of vertical transistors (50), emitter (48a) and collector (48c) zones of lateral transistors (48) and p-n junction isolation barriers; forming in the second epitaxial layer (16) by a second doping step, localized regions of the conductivity type of the first epitaxial layer (14) for serving as the emitter zones (50a) of the vertical transistors (50), base contact regions in the lateral transistors, and doped collector contact regions (50c) in the vertical transistors; interconnecting with metallization the piezoresistors (41-44) and the vertical and lateral transistors (50,48) in the second epitaxial layer (16) into an integrated circuit; and forming in the back surface of the wafer (10) a cavity (54) aligned with the etch-stop region (12) for forming a diaphragm whose periphery underlies the piezoresistors (41-44). A process as claimed in claim 1 or 2, in which the first epitaxial layer (14) is first partially grown without added doping and then grown with added doping. A monolithic pressure sensitive integrated circuit comprising a monocrystalline silicon chip including: a bulk portion (10) of relatively high resistivity and including at its back surface (13) a cavity (54) for forming a thinned region in the chip; an etch stop region (12) of low resistivity at the bottom of the cavity (54) for defining the depth of the cavity; and first epitaxial layer (14) overlying the front surface (11) of the chip; characterised by a second epitaxial layer (16) of conductivity opposite that of, and overlying, the first epitaxial layer (14), the second epitaxial layer including a central region which includes a plurality of piezoresistors (41-44) disposed symmetrically to overlie the periphery of the etch stop region (12), and also surrounding regions in which are formed transistors (48,50) and p-n junction isolation regions that are interconnected with the piezoresistors to form an integrated circuit. A monolithic pressure sensitive integrated circuit as claimed in claim 4, in which the second epitaxial layer (16) includes a plurality of lateral junction transistors (48) and a plurality of vertical junction transistors (50) for interconnection with the piezoresistors (41-44) into the integrated circuit. A monolithic pressure sensitive integrated circuit as claimed in claim 4 or 5, in which the bulk portion (10) is n-type, the etch-stop region (12) is p-type, the first epitaxial layer (14) is p-type and the second epitaxial layer (16) is n-type. A monolithic pressure sensitive integrated circuit as claimed in any one of claims 4 to 6, in which the etch stop region (12) is square and there are four piezoresistors (41-44) disposed over the four sides of the square connected to form a Wheatstone bridge. A monolithic pressure sensitive integrated circuit as claimed in claim 7, in which the cavity (54) is square. A monolithic pressure sensitive integrated circuit as claimed in any one of claims 4 to 8, in which the front and back surfaes (11,13) of the chip lie along 〈100〉 crystal planes.

Inventors: BROWN, RONALD E., HORNBACK, DONALD L., LEISURE, RONALD K., STEVENSON, PAUL E., YODER, DOUGLAS J.
Applicants: DELCO ELECTRONICS CORPORATION (A DELAWARE CORP.)
Application year: 1989
Main classification: G01L9
IPC codes: G01L9, H01L29