Improved current mirror circuit

Abstract: The present invention relates to a switched current mode drive circuit comprising an MOS reference transistor (22; 32) and control element (24; 34) connected between a reference voltage source and a current source; an MOS mirroring transistor (26; 36) connected between the reference voltage source and load means in mirrored configuration to the reference transistor; and signal means connected between the control element and the mirroring transistor for controlling drain potential of the reference transistor whereby it follows the drain potential of the mirroring transistor.

Description: The present invention relates to an improved current mirror electronic circuit. More particularly the invention is useful for a switched current mode driver designed for use in input-output channel selection functions associated with an IBM (Registered Trade Mark) 360/370 channel, capable of interconnection with a plurality of peripheral devices for receiving selection signals from the channel and redriving the signals to the next control unit. In the use of IBM 360/370 channel systems where a plurality of peripheral devices must be connected to one or more central processing units (CPU's) it is common to use a control unit associated with each peripheral device being attached to the 360/370 channel. Such control units use a module that performs power supply, logic and switching functions with respect to the connection lines that are required to initiate and terminate operations between the 360/370 channel interface and the respective control units. In such systems it is usual to provide an integrated select-out bypass chip that performs select-out and select-in control for a single IBM system 360 and system 370 I/O interface. The control unit attached to the 360/370 channel interface uses a select-out signal to detect the start of a selection sequence from the channel. Unlike the other interface lines, the select-out signal not only is received by each control unit, but also passes through logic and is redriven to the next control unit attached to the channel. The integrated select-out bypass function provides an electrical bypass for the select-out/select-in signal when the control unit is powered off. Besides the select out bypass function, the internal select-out bypass design contains the driver and receiver used when the control unit is powered up to receive and redrive the select-out signal to the next control unit. Driver requirements for use in IBM 360/370 channels to drive the select-in and select-out lines require capability to drive 3.9 volts into a 95-ohm cable and be short circuit protected. Modern systems also require short circuit detection (RAS) and a high impedance mode for testing purposes. Bipolar driver circuits have been used in the past in typical line driver implementations. However the usual 6-volt power supply requirement for bipolar circuits is undesirable. Moreover, the large current limiting resistors associated with such circuits result in excessive power dissipation. Consequently, a need exists to utilise MOS (metal oxide silicon) circuitry for such line driver implementations in order to operate at the lower power supply voltages, typically 5 volts, available with more recently designed systems, and to reduce power dissipation. PCT patent application WO89/07792 discloses an improved current mirror where the gate voltages of the reference and mirror elements are varied together to control the load current. The voltage at the input current terminal varies as the loading at the output varies. WO89/07792 takes the place of the corresponding European application EP-A-402 383 according to Article 158(1), EPC, and thus represents state of the art in accordance with Article 54(3), EPC, for the designated contracting states DE, FR, GB. Japanese unexamined patent JP-A-54 136,261 discloses a current inversion circuit that uses a feedback control element in series with the mirror element and the load to control the load current. The use of the feedback control element in series with the load necessitates a higher power supply voltage. European Patent application EP-A-0 189,894 includes in Fig 55(B) a disclosure of a switched current mirror comprising P-MOS FETs. An embodiment of the disclosure using N-MOS FETs is described later and illustrated in Figure 2b of the present application. This embodiment does not allow in any way for the output conductance, G DS, of the mirror element. The object of the present invention is to provide an improved current mirror circuit for electronic circuitry. The invention provides a current mirror comprising an MOS reference transistor and a feedback control element serially connected between a reference voltage source and a current source , the gate of the reference transistor being connected to said current source; an MOS mirroring transistor connected between the reference voltage source and load means in mirrored configuration to said reference transistor ; and signal means for controlling the drain potential of said reference transistor by means of the feedback control element whereby it follows the drain potential of said mirroring transistor. In order that the invention may be more readily understood, an embodiment will now be described with reference to the accompanying drawings in which: Figure 1 represents a typical known type of non-current mode line driver designed in bipolar technology. Figure 2a represents a known type of switched current mode driver Figure 2b represents an MOS technology realisation of a known type of switched current mode driver such as illustrated in Figure 2a, Figure 3a represents an improved output resistance current mirror circuit in accordance with the invention, Figure 3b is a graph of the electrical output characteristics of the circuit of Figure 3a, Figure 4a is a schematic of another improved current mirror circuit, and Figure 4b is yet another improved mirror circuit similar to that illustrated in Figure 4a. Figure 1 shows a typical known type of line driver implementation. This basic circuit has been used extensively in bipolar versions of I/O drivers of the type generally described herein. In the driver circuit illustrated in Figure 1, a +6 volt supply voltage is provided through a current limiting resistor 11 to the collector of an NPN transistor 12 having its emitter connected to a 95 ohm load resistor at the output. The driver input is connected to the base of the transistor and a 750 ohm resistor 14 is provided between the input and supply voltage terminals. The configuration may be implemented in MOS technology simply by replacing the NPN device with a MOSFET (MOS Field Effect Transistor). However the large current limiting resistor and the 6 volt power supply requirements are very undesirable. Many newer technologies do not allow operation of drivers at 6 volts, and systems are less expensive if all circuits use a single power supply, typically 5 volts with a 10% tolerance. The 35 ohm current limiting resistor dissipates a significant amount of power, especially when the driver is short circuited. It is often added as an external resistor, increasing both the module pin count and the production costs. A basic Switched Current Mode Driver (SCMD) configuration, shown in Figure 2a, would partially overcome these problems. When switched ON, a current I ON from a current source is forced through the load. The voltage developed at the output is then V OUT = I ON X R LOAD . For I ON > 42.2 ma and R LOAD > 92.6 ohms, the voltage developed exceeds the required 3.9 volts. When the SCMD is switched OFF, the load pulls the line to a logic zero level, as does the classic driver of Figure 1. The power dissipated by a SCMD under short circuit conditions is only Power = I ON X V DD . For I ON = 42 ma and V DD = 5.0 volts, the power dissipated is 0.21 watts. Under similar conditions, the circuit of Figure 1, dissipates Power = V DD ²/35 = 1.02 Watts Thus, the SCMD dissipates about one-fifth the power of a conventional bipolar driver under short circuit conditions. The SCMD requires no complicated protection circuit to shut it down during short circuits. Unlike many other drivers, the SCMD returns to normal operation as soon as a short circuit is removed, without requiring a reactivation sequence such as cycling its input. A SCMD may be provided by a current mirroring device and a switch. Figure 2b shows such a known type of driver configuration implemented in MOS technology. In Figure 2b, the Switched Current Mode Driver utilises a supply voltage V DD connected to the source of a P channel reference device 22, having its gate and drain connected to a current reference 23 and a switch 24 respectively. A current mirroring device, typically another P channel device 26, is provided, again having its source connected to the supply voltage V DD , its gate connected to the drain of device 22, and its drain connected to an output or load impedance 27. When the switch 24 is open, the reference current flows through device 22 and is mirrored in device 26 forcing the output high. When the switch 24 is closed, it bypasses device 22 so no current is reflected in device 26. With no current in device 26, the load resistor 27 pulls the output low. Choice of appropriate sizes for device 22 and device 26 allows them to remain saturated while the source-to-drain voltage of device 26 is made arbitrarily small. Theoretically, any supply voltage greater than the required output voltage across resistor 27 is sufficient to power the circuit. This allows the switched current mode driver to operate from a typical 5 volt, 10% supply and meet the 3.9 volt logic one level. The precision of current mirroring devices in any integrated circuit technology can be high, due to good tracking of parameters across carefully designed devices. It depends primarily on parameter matching rather than on the absolute values. MOS technology is especially well suited for current mirroring device designs because of extremely low gate current. The only parameter of concern not cancelled by tracking is the output conductance, G DS , which may, however, be reduced to an arbitrarily small value by device design. Therefore, the theoretical accuracy of a SCMD implemented in MOS technology is limited only by the accuracy of the reference current and the degree of matching of the devices. In MOS technology, the output impedance of a SCMD is increased as device lengths are increased. Unfortunately, area and capacitance considerations limit the length that may be used in practice. Current errors may be eliminated, even in short devices, by forcing all nodes of the mirroring devices to the same potential. This is commonly done by "stacking" mirroring devices. Stacked mirroring devices, however, require higher power supply voltages to bias the additional devices. Thus, prior art stacked mirroring devices only improve the output impedance when the output potential is significantly lower than V DD and it has been found that the 3.9 volt requirement of the typical SCMD cannot be met with this type of current mirroring device. A solution to the problem is to add a feedback circuit that controls the drain of the reference device, as illustrated in Figure 3a. In Figure 3a a current mirroring circuit is illustrated wherein device 32 serves as a reference, device 34 is a feedback control element and device 36 is the mirroring device. As shown, all devices 32, 34, 36 are P channel MOSFETS. V DD is connected to the source of device 32, and its drain is connected to the source of device 34. The drain of device 34 is connected to a current reference 33, and to the gate of device 32. The gate of device 32 is also connected to the gate of device 36, with the source of device 36 being connected to V DD and its drain being connected to load impedance 37, as illustrated. The circuit otherwise includes a conventional operational amplifier 38 having its output connected to the gate of device 34. An inverting input of the OP AMP 38 is connected to the drain of device 32 and the non-inverting input is connected to the drain of mirroring device 36. The gates as well as the sources of the two mirroring devices (32 and 36) are tied together, forcing their V GS potentials to track each other. The OP AMP 38 and the device 34 force the drain of device 32 to follow the potential at V OUT which is also the drain voltage of device 36. Therefore, the gates, sources, and drains of the two mirroring devices 32 and 36 are at the same potential. V GATE must adjust itself so that the reference current flows through device 32. Since device 36 sees the same terminal voltages as device 32 does, it mirrors the reference current "perfectly", whether or not the devices are operating in saturation. As V OUT approaches V DD , the source-to-drain voltage of the mirroring devices becomes very small, forcing the devices out of saturation and into the linear region. The mirroring devices continue to operate with the devices in the linear region by lowering the potential at the gates of devices 32 and 36. This, in turn, increases the gate drive of the mirroring devices, thereby maintaining constant current. This range of ideal operation is shown in Figure 3b as region "B". If device 33 were an ideal current source, V GATE would continue dropping as V OUT were brought arbitrarily close to V DD . There is, of course, a limit to how low V GATE can drop and still sustain current through the non-ideal device 33 current source. When this limit, typically 1 volt, is reached, a further increase in V OUT will not produce a corresponding drop in V GATE . Instead, the reference current begins to decrease, which in turn decreases the mirrored output current, I OUT . This is shown as region "A" in Figure 3b and can be made arbitrarily small by making device 33 a more perfect current source (e.g. connect it to a negative power supply instead of ground). Even without a perfect I REF source, this improved mirroring device allows operation much closer to the V DD rail than the other circuits. Device 34 cannot force the drain of device 32 to drop below the potential of V GATE . If V OUT falls below V GATE the feed back circuit effectively short circuits the gates of the mirroring devices to the drain of device 32 through device 34. This mode of operation is shown as region "C" in Figure 3b. The characteristics of the mirroring device in this region are nearly identical to those of a simple mirroring device built with equivalent device sizes. The normal mode of operation for this improved current mirroring device, when implementing a SCMD is in region "B". Because the near ideal characteristics of region "B" extend very close to V DD and allow devices forming the SCMD to operate in the linear region. Lower power supply voltages and much smaller devices may be used in this configuration than in previous configurations. A "battery" that drops the same voltage as the gate-to-source voltage, V GS , of device 34 may replace the operational amplifier of Figure 3a as shown in Figure 4a where like elements are represented by like primed numerals. This "battery" is easily implemented as a scaled device biased by a small constant current source as shown in Figure 4b. As long as the V GS voltage of device 42 is equal to that of device 34″, the mirror devices 32″ and 36″ will see the same potential at all nodes and the circuit will behave just like the one in Figure 3a. The advantages of this circuit are its smaller area, reduced complexity and wider bandwidth due to the removal of the operational amplifier.

Claims: A current mirror circuit comprising an MOS reference transistor (32) and a feedback control element (34) serially connected between a reference voltage source (VDD) and a current source (33), the gate of the reference transistor (32) being connected to said current source; an MOS mirroring transistor (36) connected between the reference voltage source (VDD) and load means (37) in mirrored configuration to said reference transistor (32); and signal means (38; 40; 42) for controlling the drain potential of said reference transistor (32) by means of the feedback control element (34) whereby it follows the drain potential of said mirroring transistor (36). The current mirror circuit as claimed in claim 1 wherein said signal means (38) comprises operation amplifier means connected in feedback configuration from the drain of said mirroring transistor and the drain of said reference transistor to the gate of said feedback control element. The current mirror circuit as claimed in claim 1 wherein the signal means comprises a battery (40) connected between the drain of said mirroring transistor and the gate of said feedback control element. The current mirror circuit as claimed in claim 1 wherein the signal means comprises another MOS transistor (42) having its source connected to the drain of said mirroring transistor and its gate and drain connected to the gate of said feedback control element and to the bias means respectively.

Inventors: LARSON TONY RAY, TRETTER LARRY LEEROY, LARSON, TONY RAY, TRETTER, LARRY LEEROY
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: H03K17
IPC codes: H03K17, G05F3, G06F3