Focus detecting apparatus for camera and self-scanning image sensor therefor

Abstract: A focus detecting apparatus including a first object distance measuring zone located above a center portion of the finder field of view, second and third object distance measuring zones located on the opposite sides of the center portion of the finder field of view, first, second and third automatic foousing optical systems for converging the luminous fluxes of objects to be photographed in the first, second and third object distance measuring zones, and, first, second and third object distance measuring sensors on which the luminous fluxes of the objects in the first, second and third object distance measuring zones are converged by the associated first, second and third automatic focusing optical systems.

Description: Background of the Invention 1. Field of the Invention The present invention relates to a focus detecting apparatus of a camera which has a plurality of object distance measuring zones according to the preamble of claim 1 and to a self scanning image sensor therefor according to the preamble of claim 2. 2. Description of Related Art A recent single-lens reflex camera usually has an automatic focusing device. A known automatic focusing device in a conventional single-lens reflex camera has a focus detecting apparatus which detectes whether beams of light are focused on an object to be photographed and a lens driving device which moves a photographing lens (focusing lens) to a focused position in accordance with the result of the detection of the focus detecting apparatus. Fig. 25 is a schematic sectional view of a known single-lens reflex camera having a focus detecting apparatus, taken along an optical axis. In Fig. 25, a camera body 1 has an interchangeable lens 2 incorporated therein having a group of photographing lenses which will be referred to as a photographing lens group L hereinafter. An object distance measuring unit 160 which constitutes a focus detecting apparatus is provided below a main mirror 3 provided in the camera body 1, at a position optically equivalent to a film plane 4. The main mirror 3 has a half mirror portion at its center, so that the beams of light which are transmitted through the photographing lens group L and which are incident on the main mirror 3 are partly transmitted through the half mirror portion thereof. The beams of light transmitted through the half mirror portion are reflected by an auxiliary mirror 6 and are incident upon the object distance measuring unit 160. Above the object distance measuring unit 160 are provided a light intercepting plate 211 which intercepts beams of light which are not used to detect the object distance and an opening 212 through which the beams of light to be used for the detection of the object distance are transmitted. The beams of light which are reflected by the main mirror 3 are transmitted through a focusing glass 7 and are then reflected by a pentagonal prism 9, so that the beams of light are introduced into a finder 8. The finder 8 has an object distance measuring zone 177 at a center portion of a finder field of view 176, as shown in Fig. 30. The object in the object distance measuring zone 177 is detected to adjust the focus. The object distance measuring unit 160 has a field mask 163, a condenser lens 164, an aperture mask 165, separator lenses 166 and 167 which constitute an image separating optical system to split an aerial image of an object into two images, and a CCD image sensor 168 which constitutes an object distance measuring sensor, as shown in Fig. 26. The field mask 163, the condensor lens 164, the aperture mask 165 and the separator lenses 166 and 167 constitute an automatic focusing optical system 169 which, in turn, constitutes a focus detecting optical system together with the CCD image sensor 168. The field mask 163 of the automatic focusing optical system 169 is provided in the vicinity of a film equivalent plane 170. The film equivalent plane 170 is optically conjugate with the object 162 with respect to the photographing lens group L, so that when the photographing lens group L is located in the focused position, an aerial image 171 of the object 162 in focus is formed on the film equivalent plane 170. The condenser lens 164 and the aperture mask 165 split the beams of light passing the right and left sides of the photographing lens group L into two luminous fluxes. The separator lenses 166 and 167 are located in a conjugation relationship to the photographing lens group L through the condenser lens 164. The separator lenses 166 and 167 are usually located side by side in parallel with the length of the film plane, as shown in Fig. 27, so that imaginary opening areas 174 and 175 of an exit pupil of the photographing lens group L mounted to the camera body 1 can be viewed through the measuring zone 172 which is optically conjugate with the center measuring zone 177 (Fig. 30) in the finder field of view 176. The beams of light which are transmitted through the opening areas 174 and 175 are incident upon the separotor lenses 166 and 167, so that two images 171a, 171a of the aerial image 171 formed on the film equivalent plane 170 are reformed on the CCD image sensor 168 by the separator lenses 166 and 167. Supposing that the distance between the reformed images 171a and 171a in focus (Fig. 28(a)), namely the distance between peak values of the image signal S is ℓ o as shown in Fig. 29(a), when the focal point of the photographing lens group L is located before the in-focus position shown in Fig. 29(a), as shown in Fig. 28(b), the distance is decreased, so that the distance ℓ₁ between the peak values of the image signal S is smaller than ℓ o . On the contrary, when the focal point of the photographing lens group L is located behind the in-focus position shown in Fig. 28(a), the distance is increased, so that the distance ℓ₂ between the peak values of the image signal S is larger than ℓ o , as shown in Fig. 28(c). The change of the image distance is substantially proportional to the amount of defocus of the photographing lens group L, and accordingly, in a conventional single-lens reflex camera, the distance of the images formed on the CCD image sensor 168 is detected to arithmetically process the same in order to determine the direction and the amount of defocus of the photographing lens group L, thereby to move the photographing lens group L to the focused position (in-focus position). As can be seen in Fig. 30, for example, when a photographer determined a composition so that the desired object 162 is located in the center measuring (focusing) zone 177 of the finder field of view 176, a focusing lens of the photographing lens group L is moved to the focused position by a focusing lens driving motor (not shown) and a focusing lens driving mechanism (not shown), where a picture in focus can be taken. In the focus detecting device as mentioned above, since the measuring zone 177 is located in the center area of the finder field of view 176, the photographing lens is focused on the object 162. However, there is a case where a desired object should be located in the circumferential area rather than the center area of the finder field of view. Furthermore, there is also a case where two human figures can not be placed in the center area of the finder field of view 176, namely in the measuring zone 177. To this end, a conventional camera has a so-called focus lock device in which the focusing is effected while the object is placed in the center measuring zone 177 of the finder field of view 176, and then the focus is locked. In this state, when a desired framing is effected, a picture in which the desired object is placed in the circumferential area and the camera is focused on the object 162, as shown in Fig. 31 can be taken. However, in the conventional focus detecting device, the focusing is effected (by moving the photographing lens) once the object is placed in the center of the finder field of view 176, and the focus is then locked to fix the photographing lens group L. After that, the composition is redetermined and then the releasing is effected. Due to these troublesome operations, it takes much time to take a picture. To this end, there is also known a multi-focus detecting apparatus in which two circumferential measuring zones 177a and l77b are provided to surround the measuring zone 177 of the finder field of view 176, so that whether or not the camera is focusd on the object placed on the circumferential zones 177a and 177b is also detected, as can be seen in Fig. 30. Such a multi-focus detecting apparatus usually has a first center automatic focusing optical system 169, a pair of second and third automatic focusing optical systems 211 ans 212, and first, second and third CCD image sensors 168, 241 and 242, as shown in Fig. 32. The first automatic focusing optical system 169 has a condenser lens portion 222 and a separator lens portion 232. The second automatic focusing optical system 211 has a condenser lens portion 221 and a separator lens portion 231. The third automatic focusing optical system 212 has a condenser lens portion 223 and a separator lens portion 233. Numerals 177′, 177a′, 177b′ designate fields of view of the center measuring area and the circumferential measuring areas of the first, second, and third automatic focusing optical systems 169, 211 and 212 and are substantially conjugate with the measuring zones 177, 177a and 177b of the finder field of view 176, respectively. The CCD image sensors 168, 241 and 242 are formed on the same integrated circuit board 251. Upon taking a picture of a human figure, a photographer usually unconsciously looks at her or his face through the finder. This is because the face reflects a state of mind of human being. Usually, the face of a human figure in a portrait is located slightly above the center of the finder field of view rather than the center. However, in the conventional focus detecting apparatuses, the center measuring zone 177 is provided at the center of the finder field of view 176. As a result, upon taking a picture of a human figure, the center measuring zone 177 does not often correspond to the face of the human figure, as shown in Fig. 30. Therefore, after the center of the finder field of view 176 is located to correspond to the face, the focusing is effected and is then locked. After that, the framing is effected (Fig. 30). Therefore, a photographer tends to concentrate his or her attention to agreement of the face of the human figure with the measuring zone 177 and miss a shutter chance without noticing a possible change of the expression. Furthermore, in the conventional multi-focus detecting apparatus, since three CCD image sensors 168, 241 and 242 are arranged in the form of a generally H-shape, as shown in Fig. 33, it is necessary to bend a single transfer register 252 which reads data of the three image sensors 168, 241 and 242, as shown in Fig. 33, resulting in an increased transfer distance. The quantity of charge accumulated by the CCD sensors 168, 241 and 242 depends on the intensity (brightness) of the luminous flux of the object. It is also known to provide a monitor sensor 168m in the vicinity of the center CCD image sensor 168 to detect the amount of light incident thereon, thereby to control the integration time (time of accumulation of the charges), see US-A-4 701 626. In this known detecting mechanisms as mentioned above, in which the integration time is controlled by a mean value of the brightnesses detected by the measuring zones 177, 177a and l77b, or by the brightness of the center measuring zone 177, if there is a large difference in brightness between the measuring zones 177, 177a and l77b, the quantity of charge accumulated in the CCD image sensor corresponding to the measuring zone having a high brightness exceeds a saturation value, so that the detection can not be effected, or a sufficient charge can not be accumulated in the CCD image sensor corresponding to the measuring zone having a low brightness, so that the detection can not be effected. The CCD image sensor used in a conventional focus detecting apparatus, as mentioned above has a light receiver having an array of photoelectric converting elements, an integrating portion which integrates the signal charge converted by the light receiver, and a charge transfer portion which reads the integrated signal charge. The signal charge integrated by the integral portion is transferred to the charge tranfer portion, and is then successively tranferred from the charge tranfer portion by two-phase or more than two-phase of tranfer pulses which are generated at a constant interval. These tranfer pulses are usually periodically output, so that the signal charge is tranferred during the period of outputting. No accumulated control pulse is output during the period of outputting of the tranfer pulses to prevent the signal charge from being transferred from the integral portion to the charge transfer portion. This is because if the accumulated control pulse is output when the charge transfer portion has an electric charge therein, the signal charge is mixed with the accumulated control pulse in the chrage transfer portion, so that the signal no longer functions as a data signal. To avoid this, even if the brightness of an object is high, so that the integrating portion is saturated, the integrating operation cannot be completed until the output time of the transfer pulse ends. As a result, when the brightness of an object is high, no precise focus detection can be effected. To solve the problem mentioned above, it is known to make the prohibition period of outputting the accumulated control pulse variable (e.g. Japanese Unexamined Patent Publication No. 60-121409). However, such a varying means makes the circuit construction and the control operation thereof complex. Summary of the Invention The primary object of the present invention is to eliminate the above-mentioned drawbacks by providing a focus detecting apparatus in which a point of view of a photographer coincides with the measuring zones acc. to claim 1. Another object of the present invention is to provide a focus detecting apparatus in which a distance of transfer of signal charges can be decreased. Still another object of the present invention is to provide a focus detecting apparatus in which accurate object distance signals can be obtained for every measuring zone. To achieve the objects mentioned above, according to the present invention, a focus detection apparatus is provided having the features of claim 1. With this arrangement, the face of a human figure is placed in the measuring zones in a normal composition of a portrait. According to another feature of the present invention, three measuring zones are arranged in the form of generally inverted U-shape with the lower side left open, so that three object distance measuring zones corresponding to the measuring zones are located in the corresponding arrangement. With this arrangement, if CCD image sensors are used as measuring sensors, it is possible to arrange the transfer registers in generally inverted U-shape with an open lower side, thus resulting in a decreased distance of transfer of signal charge. In addition, it is possible to provide the measuring zone corresponding to the center measuring sensors above the center of the finder field of view. According to an aspect of the present invention, there is provided a focus detecting apparatus having the features of claim 1. With this arrangement, since the integration time varies in accordance with the brightness of an object, so that when the object has a high brightness, the integration time is reduced accordingly, no saturation of the integral value occurs even for an object of high brightness, thus resulting in a precise object distance signal. In addition to the foregoing, since the integration time can be controlled while monitoring the quantitiy of light of each object distance measuring sensor, even if there is a large difference in brightness between the object distance measuring zones, a precise object distance signal can be obtained for each object distance measuring zone. According to another aspect of the present invention, the signal charge which is integrated by the integrating portion is temporarily held by the charge holding portion before the signal charge is transferred to the charge transfer portion according to claim 2. With this feature of the invention, the signal charge integrated by the integrating portion can be tranferred to the charge holding portion, regardless of the state of the transfer portion, for example, regardless of the transfer of the signal charge. Namely, since the time of integration can be controlled, no saturation of integral values takes place even for an object of high brightness. Brief Description of the Drawings The invention will be described below in detail with reference to the accompanying drawings, in which: Figure 1 is a schematic front elevational view of a finder field of view with three measuring zones, in a single-lens reflex camera having a focus detecting apparatus according to the present invention; Fig. 2 is a front elevational view of a CCD image sensor shown in Fig. 1; Fig. 3 is a schematic perspective view of an automatic focusing optical system shown in Fig. 1; Fig. 4 is a plan view of an automatic focusing optical system shown in Fig. 3; Fig. 5 is a side elevational view of an automatic focusing optical system shown in Fig. 4; Fig. 6 is a front elevational view of a view mask used in the present invention; Fig. 7 is a front elevational view of a condenser lens used in the present invention; Fig. 8 is a schematic view showing a separator lens according to the present invention; Fig. 9 is an explanatory view of an exit pupil and an aperture area when a photographing lens of a camera is viewed through a measuring zone of an automatic focusing optical system which is substantially and optically conjugate with the center measuring zone of the finde; Fig. 10 is an explanatory view of an exit pupil and an aperture area when the exit pupil shown in Fig. 3 is influenced by a so-called vignetting; Fig. 11A is a front elevational view of a CCD image sensor of an AF device according to an embodiment of the present invention; Fig. 11B is a front elevational view of a CCD image sensor for an object distance measuring zone according to an embodiment of the present invention; Fig. 12 is a sectional view taken along the line XII-XII in Fig. 11A, for explaining the transfer operation of electric charges; Fig. 13 is a view similar to Fig. 12, for showing the vicinity of the portion of Fig. 11A along which Fig. 12 is sectioned: Fig. 14A is a sectional view of a CCD image sensor, similar to Fig. 12, but according to another embodiment of the present invention; Fig. 14B is a sectional view of a monitor light receiving portion; Fig. 15A is a diagram showing a driving control circuit of a CCD image sensor shown in Fig. 11A; Fig. 15B is a diagram showing a driving control circuit of a CCD image sensor shown in Fig.11B; Fig. 16 is a diagram showing a time chart of a CCD image sensor; Fig. 17 is a diagram of a video signal processing circuit; Fig. 18 is a diagram showing a circuit for generating a monitor reference voltage Vref; Fig. 19 is a system block diagram of an AF single-lens reflex camera to which the present invention is applied; Figs. 20 through 24 are flow charts showing operations of an AF device according to the present invention, of which Fig. 20 is a main flow chart, Fig. 21 is a flow chart of processing of a photometer switch and a release switch; Fig. 22A and 22B are flow charts of the AF processing; Fig. 23A and 23B are flow charts of fetching process of data of the CCD image sensor; Fig. 24 is a flow chart of the AF motor stopping operation; Fig. 25 is a longitudinal sectional view of an AF single-lens reflex camera having a focus detecting apparatus according to the present invention, taken along the optical axis; Fig. 26 is a perspective view of a conventional automatic focusing optical system; Fig. 27 is a schematic view showing the focusing operation of the focus detecting device shown in Fig. 26; Fig. 28 is a schematic view of outputs of a conventional CCD image sensor; Fig. 29 is a schematic view showing how to take a picture of a desired main object which is deviated left or right from the center of the field of view, in a conventional camera having a focus detecting device; Fig. 30 is an explanatory view of a conventional finder filed of view in which a face of a human figure is not located at the center of the field of view; Fig. 31 is an explanatory view showing how to lock the focus in a conventional finder field of view; Fig. 32 is an explanatory view of a conventional automatic focusing optical system; and, Fig. 33 is a front elevational view of a light receiving portion of a conventional CCD image sensor and a signal transferring portion. Description of Preferred Embodiments The following discussion will be directed to preferred embodiments of a single-lens reflex camera which has an automatic focusing unit (which will be referred to as an AF unit) 5 to which the present invention is applied. Focus Detecting Unit The AF unit 5 of the present invention can be incorporated in a conventional single-lens reflex camera, as shown in Fig. 25. In Fig. 25, a first measuring zone 12 is provided in the finder field of view 11 of the finder 8, above the center thereof, as shown in Fig. 1. A pair of second and third measuring zones 13 and 14 are provided on the opposite sides of the center measuring zone 12. The measuring zones 12, 13 and 14 are made visible for example by frame lines formed on a focusing glass 7. In the AF unit 5 is provided a CCD image sensor unit 15 which includes a single integrated circuit board 15a which is provided thereon with three CCD image sensors (first, second and third sensors) 16, 17 and 18 which are arranged in a generally inverted U-shape to receive the luminuous fluxes of the object in the measuring zones 12, 13 and 14 (Fig. 2). Numeral 19 designates a transfer register which serves as a charge transferring portion to read the signal charges accumulated by the CCD image sensors 16, 17 and 18. As can be seen from the foregoing, since the first measuring zone 12 is located above the center portion of the finder field of view and since the first CCD image sensor 16 is located at the light receiving position at which it receives the luminuous flux of the object in the first measuring zone 12, upon taking a picture of a human figure, the face of the human figure substantially coincides with the first measuring zone 12. Namely, the point of view of a photographer who looks at the finder field of view 11 coincides with the first measuring zone 12, resulting in no miss of a shutter chance. Figs. 3 and 4 show a focus detecting optical system provided in the AF unit 5. The focus detecting optical system has a first automatic focusing optical system 169 (which will be referred to as a first AF optical system hereinafter) and a pair of second automatic focusing optical system (second AF optical system) 178 and third automatic focusing optical system (third AF optical system) 179 for converging the luminuous fluxes of the objects in the measuring zones 12, 13 and 14 onto the CCD image sensors 16, 17 and 18, respectively. The field of view 12a of the center measuring zone and the fields of view of the circumferential measuring zones 13a and 14a conjugate with the measuring zones 12, 13 and 14 are formed on the film equivalent plane 170 in the AF optical systems 169, 178 and 179. Aerial images of the objects in the measuring zones 12, 13 and 14 are formed on the fields of view 12a, 13a and 14a. In Fig. 3, an exit pupil of the photographing lens group L is shown at 173 by a solid line, as viewed through the fist measuring field of view 12a of the first AF optical system 169. The exit pupil 173 is substantially circular, as shown in Fig. 9. The opening areas 174 and 175 as viewed through the separator lenses 166 and 167 are substantially eliptical, as shown in Fig. 9. The exit pupil 173 of the photographing lens group L as viwed through the circumferential fields of view 13a and 14a is shown by a dotted line in Fig. 3. The exit pupil 173 shown at the dotted line is substantially eliptical. The opening areas 190 and 191 in which the luminous flux is passed through the separator lenses 180, 181 and 183, 184 is circular as shown in Fig. 10. The AF unit 5 has a view mask 203, a condenser lens 201, a mask M located in front of the condenser lens 201, a prism plate 202 located in rear of the condenser lens 201, an auxiliary lens 214, a separator lens I, a diaphragm mask 204 provided between the auxiliary lens 214 and the separator lens I, a cover glass 215, and an integrated circuit board 15a which has the CCD image sensors 16, 17 and 18 (measuring sensors) formed thereon. The view mask 203 has openings 203a, 203b and 203c for forming the center field of view 12a and the circumferential fields of view 12b and 12c (Fig. 6). These openings are located in the form of generally inverted U-shape. The mask M has openings Ma, Mb and Mc corresponding to the measuring zones 12,13 and 14, in the shape of U corresponding to the shape formed by the openings 203a, 203b and 203c. The condenser lens 201 has three condenser lens portions 201a, 201b, and 201c, so that the optical axis of the condenser lens 201a is located above the line ℓx which connects the optical axes 201b0 and 201c0 of the condenser lens portions 201b and 201c at a predetermined distance therefrom in Fig. 7. In Fig. 7, both the condenser lens 201 and the view mask 203 are shown to show the positional relationship between the condenser lens portions 201a, 201b, 201c and the openings 203a, 203b, 203c of the view nask 203. The prism plate 202 has a center parallel plane portion 202a and prisms 202b and 202c on the opposite sides of the center parallel plane portion 202a. The separator lens I has separator lens portions 166, 167, 180, 181, 183 and 184. The auxiliary lens 214 has auxiliary lens portions 214a, 214b and 214c. The diaphragm aperture 204 has eliptical openings 204a, 204a′, 204b, 204b′, 204c and 204c′ corresponding to the separator lens portions 166, 167, 180, 181, 183 and 184, as shown in Fig. 8. In the illustrated embodiment, the distance between the view mask 203 and the condenser lens 201 is 3.55 mm, the distance between the mask M and the condenser lens 201 is 0.20 mm, and the openings 203a, 203b and 203c form a rectangle of 3.75 mm × 1.4 mm. The radii of curvature of the surface (upper surface in Fig. 4) of the condenser lens portions 201a, 201b and 201c adjacent to the mask M and the opposite surface thereof are 18. 504 mm and 7. 496 mm, respectively, so that the thickness of the center portion thereof is 2.0 mm. The radii of curvature of the surface (upper surface in Fig. 4) of the separator lens portions 166, 167, 180, 181, 183 and 184 adjacent to the diaphragm mask 204 and the opposite surface thereof are ∞ and 1.750 mm, respectively, so that the thickness of the center portion thereof is 1.25 mm. The radii of curvature of the surfaces of the auxiliary lens portions 214a, 214b and 214c on the light incident side and the light emitting side are 10.416 mm and ∞, respectively, so that the thickness of the center portion thereof is 1.20 mm. The diaphragm mask 204 has a thickness of 0.04 mm, and the major and minor diameters of the openings 204a, 204a′ ∼204c, 204c′ are 0. 96 mm and 0. 48 mm, respectively. The thickness of the cover glass 215 is 0.50 mm and the distance between the cover glass 215 and the separator lens I is 1.64 mm. The distance between the condenser lens 201 and the auxiliary lens 214 is 10.5 mm. On the opposite sides of the first AF optical system 169 are provided the second and third Af optical system 178 and 179 for measuring the circumferential zone. The first AF optical system 169 is composed of the view mask 203, the mask M, the condenser lens portion 201b, the separator lens portions 166 and 167, and the auxiliary lens portion 214a. The second AF optical system 178 is composed of the view mask 203, the mask M, the condenser lens 201a, the prism 202a, the auxiliary lens portion 214b and the separator lens portions 180 and 181. The third AF optical system 179 is composed of the view mask 203, the mask M, the condenser lens portion 201c, the prism 202a, the auxiliary lens portion 214b and the separator lens portions 183 and 184. The focus detecting apparatus is constituted by the first, second, and third AF optical systems 169, 178, 179, and the first, second, third image sensors 16, 17 and 18. The first CCD image sensor 16 of the sensor unit 15 shown in Fig. 2 is located on the center optical axis X of the first AF optical system 169 (Fig. 3). The second CCD image sensor 17 is located on the center optical axis X1 of the second AF optical system 178, and the third CCD image sensor 18 is located on the center optical axis X2 of the third AF optical system 179. The signal charges accumulated in the CCD image sensors 16, 17 and 18 are successively output as video signals through the transfer register 19 in the U-shape to be transferred to the control circuit. As mentioned above, since the CCD image sensors 16, 17 and 18 are arranged in the shape of general U on a single substrate, the transfer register 19 can be arranged in the shape of generally U. As a result, it is not necessary for the transfer register 19 to be bent as in the prior art, so that the transfer distance of the received signals can be decreased. The luminous fluxes Q1 and Q2 (Fig. 4) which are incident upon the second and third CCD image sensors 17 and 18 from the condenser lens portions 201a and 201c to be converged thereon are bent toward the center first CCD image sensor 16 by the prisms 202b and 202c of the prism plate 202, so that the distances between the CCD image sensors 16, 17 and 18 can be decreased, resulting in a realization of a small integrated circuit board 15a. In the illustrated embodiment, the integrated circuit board 15a could be about 6mm × 6mm. The conventional integrated circuit board is usually 12 ∼14 mm × 12 ∼14 mm. In Fig. 4, the luminous flux which is incident through the opening 204a′ of the diaphragm mask 204 to form an image on the first CCD image sensor 16 is similar to the luminous flux which is incident through the opening 204a of the diaphragm mask 204 to form an image on the first CCD image sensor 16, and accordingly is omitted. Similarly, in Fig. 5, the luminous flux which is incident through the opening 204c of the diaphragm mask 204 to form an image on the second CCD image sensor 17 is similar to the luminous flux which is incident through the opening 204c′ of the diaphragm mask 204 to form an image on the third CCD image sensor 18, and accordingly is omitted. In Fig. 3, the separator lenses 180, 181, 183 and 184 are located one on another, so that they are substantially optically conjugate with the exit pupil 173 of the photographing lens group L through the condenser lens 201 and the prism plate 202 (Fig. 4), whereby the upper and lower opening areas 190 and 191 of the exit pupil 173 are viewed through the circumferential measuring fields of view 13a and 14a. The reason that the separator lenses 180 and 181, the separators 183 and 184 are put one on another is that the luminous flux which is incident upon the circumferential measuring fields of views 13a and 14a through the photographing lens group L is an oblique luminous flux, so that the exit pupil 173 of the photographing lens group L as viewed from the circumferential measuring fields of views 13a and 14a is a slightly flatly deformed shape, due to a vignetting, as shown in Fig. 10. Therefore, if the opening areas 190 and 191 are arranged side by side in the horizontal direction, the substantial lens distance between the separator lenses 180 and 181 (separator lenses 183 and 184) is decreased, resulting in an insufficient base length and a decreased accuracy of the detection of the image distance. In Fig. 3, the optical axes X1 and X2 of the second and third AF optical systems 178 and 179 intersect the center O1 of the exit pupil 173. X11, X12 and X22 designate the optical axes of the separator lens 181, the separator lens 180 and the separator lens 183, respectively. The optical axes X11 and X21 intersect each other at the center O2 of the opening area 191 and the optical axes X12 and X22 intersect each other at the center 03 of the opening area 190. Construction of Object Distance Measuring Sensor Fig. 11A shows an object distance measuring sensor unit in which a self-scanning image sensors are used according to the present invention. In the illustrated embodiment, although the self-scanning image sensors are used as the CCD image sensors, the present invention is not limited thereto. For instance, BBD, CID or MOS image sensors can be used in place of the self-scanning image sensors. The focus detecting apparatus has an AF optical system similar to the first AF optical system 169 as shown in Figs. 3 and 4 and three light receiving portions S1, S2 and S3 as an object distance measuring sensor. The light receiving portions S1, S2 and S3 have the second CCD image sensor 20, the first CCD image sensor 30 and the third CCD image sensor 40 which receive the luminous fluxes of the objects in the second measuring zone 13, the first measuring zone 12 and the third measuring zone 14, respectively. The CCD image sensors 20, 30 and 40 are provided on the same integrated circuit board 50 and each has an array of a large number of photoelectric converting elements (e.g. 100 photodiodes). The third CCD image sensor 40 is provided on its one end with an intercepted photoelectric converting elements 41a. The CCD image sensors 20, 30 and 40 are arranged so that the center first CCD image sensor 30 lies in the horizontal plane, and the second and third CCD image sensors 20 and 40 are located on the lower left and right sides of the center CCD image sensor 30 to lie in the vertical planes, so that the CCD image sensors 20, 30 and 40 form a generally inverted U-shaped shape. The corresponding generally U-shaped single transfer register 51 is provided inside the CCD image sensors 20, 30 and 40 to transfer the electrical charges. The transfer register 51 is provided on its one end with a CCD output portion 52, so that the signal charges accumulated by the CCD image sensors 20, 30 and 40 are successively read out as video signals from the CCD output portion 52. The second and third light receiving portions S1 and S3 have monitor light receiving portions 22 and 42 which are located outside the second and third CCD image sensors 20 and 40 and which have lengths approximately half the lengths of the CCD image sensors 20 and 40, respectively. Similarly, the first light receiving portion S1 has a monitor light receiving portion which is located above the first CCD image sensor 30 and which has a length approximately half the length of the CCD image sensor 30. The monitor output portions 23, 33 and 43 are provided outside the monitor light receiving portions 22, 32 and 42. The aerial image of the objects in the measuring zones 12, 13 and 14 are divided and formed on the CCD image sensors 20, 30 and 40 and the monitor light receiving portions 22, 32 and 42. The transfer register 51 has a reset terminal Φ R connected thereto, so that every time one video signal is output from the CCD output portion 52, the a reset signal is input thereto to reset the video signal. Each of the CCD image sensors 20, 30 and 40 has a large number of photoelectric converting elements (photodiodes) which are aligned in the longitudinal direction. Adjacent to the CCD image sensors 20, 30 and 40 are provided respective integral gates ST, so that the signal charges connverted by the photoelectric converting elements are integrated (accumulated) at the portion of the integrated circuit board located below the integral gates ST (Figs. 12 and 13). The gates Φ INT1 , Φ INT2 and Φ INT3 which are integral control gates provided between the transfer register 51 and the associated CCD image sensors 20, 30 and 40 independently control the start and stop of the accumulation (integration) of the charges in the CCD image sensors 20, 30 and 40. The integral starts and stops when the integral control gates Φ INT1 , Φ INT2 and Φ INT3 are "L" and "H", respectively. The gates Φ T1 , Φ T2 and Φ T3 provided between the transfer register 51 and the associated CCD image sensors 20, 30 and 40 are charge holding gates which form the charge holding portion for temporarily holding the integrated signal charges. The gates Φ T are shift gates which transfer the signal charges temporarily accumulated by the gates Φ T1 , Φ T2 and Φ T3 at one time. The charge holding portion is constituted by the charge holding gates Φ T1 , Φ T2 and Φ T3 , and the portions of the integrated circuit board located below those gates. The transfer gates Φ₁ and Φ₂ are provided on the surface of the transfer register 51 along the length thereof. The two-phase clock pulses are input to the transfer gates Φ₁ and Φ₂, so that the signal charges transferred to the transfer registor 51 is successively transferred to the CCD output portion 52. The monitor light receiving portions 22, 32 and 42 are composed of photoelectric converting elements. The charges converted by the monitor light receiving portions 22, 32 and 42 are accumulated in the portions of the integrated circuit board under the integral gate ST. The integral values are detected by the monitor output portions 23, 33 and 43 and are fed to a control circuit (which will be explained hereinafter) through the monitor output terminals M1, M2 and M3. The signals are then supplied to a micro computer through the control circuit to monitor the same. The integral (accumulation) of the charges in the monitor light receiving portions 22, 32 and 42 starts and stops when the integral control gates Φ INT1 , Φ INT2 and Φ INT3 are "L" and "H", respectively, as mentioned above. Each of the monitor light receiving portions 22, 32 and 42 and the monitor output portions 23, 33 and 43 is comprised of four pieces. Only four monitor light receiving pieces 32a, 32b, 32c and 32d of the center monitor light receiving portion 32 and only four monitor output pieces 33a, 33b, 33c and 33d of the center monitor output portion 33 are shown in Fig. 11 for simplification. The charges produced by the monitor light receiving pieces 32a, 32b, 32c and 32d are accumulated in the portions of the integrated circuit board under the respective integral gates ST and are discharged at the completion of the integral operation. The integral values are detected by the monitor output pieces 33a, 33b, 33c and 33d, respectively. Monitor output terminals M2D, M21, M22 and M23 are connected to the monitor output pieces 33a, 33b, 33c and 33d. The monitor output terminal M2D is connected to an operation amplifier 119 (Fig. 18), and the monitor output terminals M21, M22 and M23 are connected to operation amplifiers 79, 80 and 81, respectively (Fig. 15). The monitor light receiving piece 32a which is connected to the monitor output terminal M2D intercepts the light incident thereupon. The dark current produced by the monitor light receiving piece 32a is removed from the reference voltage to obtain a precise monitor reference voltage Vref (Figs. 16 and 18). In the illustrated embodiment mentioned above, although the monitor light receiving portions 22, 32 and 42 are provided separately from the CCD image sensors 20, 30 and 40, it is possible to use parts of the photoelectric converting elements of the CCD image sensors 20, 30 and 40 to form the monitor light receiving portions 22, 32 and 42. Operation of Measuring Sensor The operation of the transfer of charges of the light receiving portions will be explained below with reference to Figs. 12, 13 and 16. Fig. 12 (A) is a sectional view taken along the line XII-XII in Fig. 11 and Figs.12(B)∼12(F) are schematic view showing the transfer operation of the charges. An integral gate ST is located on the right side of the photoelectric converting element 21 of the second CCD image sensor 20 in the vicinity thereof. The gates Φ T1 , Φ T and Φ CCD are located in this order on the right side of the integral gate ST. The photoelectric converting element 21, the integral gate ST, and the gates Φ T1 , Φ T are provided on the integrated circuit board 50 at a predetermined distance along a direction perpendicular to the length thereof. The gate Φ CCD is comprised of gates Φ₁ and Φ₂ which are alternately provided on the transfer registor 51 in a direction of the length thereof. The integral operation and the transfer operation of the charges of the CCD image sensors 20, 30 and 40 will be explained below. The following explanation will be directed to the second CCD image sensor 20 by way of an example. A constant voltage is applied to the integral gate ST. When the integral is commenced at t1, the signal charges converted by the photoelectric converting element 21 is accumulated, i.e. integrated by the integral gate ST (Fig. 12(A)). During integral, the gates Φ T2 and Φ T are all "L" (Fig. 16). When the integral value of the monitor light receiving portion 22 reaches the monitor reference voltage Vref at t2, the gate Φ T1 turns to "H". As a result, since the potential of the gate Φ T1 is below the potential of the gate ST, the accumulated charges under the gate ST move to the portion under the gate Φ T1 (Fig. 12(C)). At t3, the gate Φ T1 is "L", so that the charges moved under the gate Φ T1 are confined and temporarily held in the potential well thereof (Fig. 12(D)). When the gate Φ T is "H" at t4, the potential of the gate Φ T is below the potential of the gate Φ T1 . The voltage "H" is applied to the gate Φ CCD . The potential of the gate Φ CCD is below that of the gate Φ T , and accordingly the electric charge of the gate Φ T1 moves to the gate Φ CCD and accordingly the transfer registor 51 (Fig. 12(E)). When the gate Φ T turns to "L" at t5, the charge moved to the transfer registor 51 is maintained therein (Fig. 12(F)). Thus, the integral operation and the temporarily hold of the signal charges which are converted by the photoelectric converting element 21 and the tranfer of the signal charges to the tranfer registor 51 are completed. The charges transferred to the transfer registor 51 are successively transferred to the CCD output portion 52 in accordance with the known two-phase clock pulses by the gates Φ₁ and Φ₂ to be output as video signals from the CCD output portion 52. As can be seen from the above explanation, according to the illustrated embodiment of the present invention, since the electric charges which are converted and integrated by the photoelectric converting elements 21 are temporarily held by the charge holding gates Φ T1 (exactly speaking, the portions of the integrated circuit board under the charge holding gates Φ T1 ), the integral operation can be finished at an optional time, regardless of the level of the gates Φ CCD of the transfer registor 51. The signal charges accumulated (integrated) by the CCD image sensors 30 and 40 are similarly transferred to the transfer registor 51. When all the electric charges of the CCD image sensors 20, 30 and are transferred to the transfer registor 51, the latter outputs the video signals in the order of the CCD image sensors 40, 30 and 20 in 40 accordance with the two-phase clock pulses through the CCD output portion 52. Since the aerial object images divided by the separator lens 14 are input to the CCD image sensors 20, 30 and 40, front halves of the video signals of the CCD image sensors 20, 30 and 40 form one image signal and the rear halves of the video signals forms another image signal. The micro computer (object distance arithmetic means) which receives the video signals performs) the necessary processes (predictor arithmetic) to detect the phase difference of the images thereby to detect a defocus value and the number of revolution and the direction of rotation of the AF motor. Fig. 13(A) shows a starting portion of the accumulation (integration) of the electric charges of the second light receiving portion S1, and Figs. 13(B) and (C) schematically show the accumulating operation of the charge accumulating portion thereof. Next to the gate S1 is provided the integral control gate Φ INT1 and the gate Φ T1 which are alternatively located in the longitudinal direction. (N⁺) is formed under the integral control gate Φ INT1 and on the downstream side (right side in Fig. 13) of (P⁺), so that the signal charges can be discharged into the bottom of the integrated circuit board. With this arrangement, when the integral control gate Φ INT1 is "L" in comparison with the potential of the gate ST (exactly speaking, the portion under the gate), the potential of the portion of (N⁺) is high. On the contrary, when the integral control gate Φ INT1 is "H", the potential of the portion of (P⁺) is low and the potential of (N⁺) is lower than the potential of (P⁺). Accordingly, the integral control gate Φ INT1 is "L" at the time t1 of the commencement of the integration, so that the charges produced by the photoelectric converting element 21 are accumulated in the gate ST (exactly speaking, the portion under the gate), as shown in Fig. 13(B). The integral control gate Φ INT1 is "H" at the time t2 of the end of the integration, so that the charges produced by the photoelectric converting element 21 are moved from the gate ST (exactly speaking, the portion under the gate) to the portion of (N⁺) of the integral control gate Φ INT1 to be discharged, as shown in Fig. 13(C). Fig. 14A shows another embodiment equivalent to the above-mentioned embodiment. In this alternative embodiment, the photoelectric converting element 21 is spaced from the array of the gates and is aligned with respect to the gate ST in the vertical direction. The integral control gate Φ INT1 and the gate Φ T1 are located on the opposite sides of the gate ST. The sequential control and the operation of the start and stop of the integration and the transfer of the signal charges are similar to those of the embodiment mentioned above. Fig. 14B shows an embodiment of the monitor light receiving element, in which the monitor light receiving portion 22 is connected to the floating diffusion portion 55 through the gate ST. The floating diffusion portion 55 is connectd to the source of a nch depletion FET 56 and a buffer 57. The gate and drain of the nch depletion FET 56 are connected to the integral control gate Φ INT1 and the power source VAA, respectively. When the gate Φ INT1 is "H", the floating diffusion portion 55 is reset to be connected to the power source VAA, so that the voltage is output as a monitor output from the monitor terminal M1 through the buffer. When the gate Φ INT1 is "L", the nch depletion FET 56 is made OFF, so that the electric charge produced by the monitor light receiving portion 22 is moved into the floating diffusion portion 55 through the gate ST. since the output of the monitor terminal M1 decreases in accordance with the quantity of integration of the charge, the quantity of integration of the charge can be detected by monitoring the output of the monitor terminal M1 into the control circuit. The above dicussion has been directed to an image sensor for a focus detecting device having three measuring zones. However, the image sensor according to the present invention can be applied to an focus detecting apparatus having a single measureing zone. In this alternative, as shown in Fig. 11B which shows an image sensor corresponding to the first object distance measuring sensor shown in Fig. 11A, monitor sensor light receiving portions 132a, 132b, 132c and 132d are provided adjacent to the CCD image sensor 130. The transfer gate 151 is provided on the side opposite to the monitor light receiving portions. Between the CCD image sensor 130 and the transfer gate 151 are provided integral control gate Φ INT1 , integral gate ST, charge holding gate Φ T2 and shift gate Φ T . The transfer gates Φ₁ and Φ₂ are provided above the transfer gate 151. The tranfer gate 150 has at its terminal end an output portion 152, so that the signal charges produced by the CCD image sensor 130 are successively output as video signals. The operations of the above mentioned various components are similar to those of the object distance measuring sensor shown in Fig. 11A. Drive Control Circuit of Object Distance Measuring Sensor The drive control circuit of the object distance measuring sensor will be explained below with reference to Fig. 15A. The oscillator 60 generates a clock pulse of XHz for operating the CCD image sensors 20, 30 and 40. It is possible to use a clock of the micro computer in place of the oscillator 60. The oscillator 60 generates a clock pulse of (1/4)XHz which is input to the 4-bit counter 61. The clock terminals Φ₈, Φ₁₆, Φ₃₂ and Φ₆₄ of the 4-bit counter 61 output clock pulses of (1/8)XHz, (1/16)XHz, (1/32)XHz and (1/64)XHz, respectively (Fig. 16). The clock terminal Φ₈ is connected to one of input terminals of the AND gate 66, C terminal of the D flip-flop 73 and third input terminals of three flip-flop circuits A1, A2 and A3. The clock terminal Φ₁₆ is connected to ones of input terminals of the respective AND gates 66 and 68. Each of the AND gates 66 and 68 has four input terminals. The clock terminal Φ₃₂ is connected to one of input terminals of the AND gate 66 and one of the AND gate 68 through an inverter 62. The clock terminal Φ₆₄ is connected to ones of input terminals of the respective AND gates 66 and 68, and is also connected to the gates Φ₁ and Φ₂ through a buffer 62 and through an inverter 63 and a buffer 64, respectively. Therefore, the level of the gate Φ₁ is identical to the level of the clock terminal Φ₆₄, and the level of the gate Φ₂ is opposite to the level of the gate Φ₁. Namely, when the gate Φ₂ is "L", the gate Φ₁ is "H" and vice versa (Fig. 16). The output terminal of the AND gate 66 is connected to the gate Φ R , so that the level of the gate Φ R becomes "H" when the clock terminal Φ₈ is "L" and the other clock terminals Φ₁₆, Φ₃₂ and Φ₆₄ are "H" and vice versa. The output level of the AND gate 68 becomes "H" when the clock terminals Φ₁₆ and Φ₆₄ are "H" and the other clock terminal Φ₃₂ is "H" and vice versa. The output terminal of the AND gate 68 is connected to a terminal C of a front stage D flip-flop 69 and to a terminal C of a rear stage D flip-flop 70 through an inverter 72. The power source voltage VAA is applied to the terminals D of the D flip-flop's 69 and 70. The terminals R of the D flip-flop's 69 and 70 are connected to the output terminal Φ TP of the micro computer. The terminal Q of the front stage D flip-flop 69 is connected to one of the input terminals of the AND gate 71. The terminal Q of the rear stage D flip-flop 70 is connected to the other input terminal of the AND gate 71. The output terminal of the AND gate 71 is connected to the gate Φ T . The level of the output terminal Φ TP is controlled by the micro computer. The operation of the D flip-flop's 69 and 70 and the level change of the gate Φ T will be explained below. The terminals Q, Q of the D flip-flop's 69 and 70 are "L" and "H" when the output terminal Φ TP is "H", namely when the level of the terminal R is "H", respectively. Accordingly, the gate Φ T is "L". When the output terminal Φ TP is "L", namely when the level of the terminal R is "L", the level of the terminal Q of the front stage D flip-flop 69 becomes "H", in accordance with a raise of the output of the terminal C, i.e. as the output of the AND gate 68 changes from "L" to "H". On the other hand, the level of the terminal Q of the rear stage D flip-flop 70 becomes"L" , in accordance with a descent of the output of the terminal C, i.e. as the output of the AND gate 68 changes from "H" to "L". Consequently, since the both terminals Q, Q are "H" before the output of the AND gate 68 begins descending, the output of the AND gate 71 and accordingly the gate Φ T is "H". After that, when the terminal Q of the flip-flop 70 becomes "L", the gate Φ T becomes "L". The power source voltage VAA is applied to the terminal D of the D flip-flop 73. The terminals C, R and Q of the D flip-flop 73 are connected to the clock terminal Φ₈, an output terminal Φ START of the micro computer and input terminals of NAND gates 74, 75 and 76, respectively. The terminal Q is always "L" when the output terminal Φ START is "H" . The terminal Q becomes "H" when the output terminal Φ START is "L". The level of the output terminal Φ START is controlled by the micro computer. The over input terminals of the NAND gates 74, 75 and 76 are connected to one of the input terminals of an OR gate 91, and ones of the output terminals of the flip-flop circuits A1, A2 and A3, respectively. The output terminals of the NAND gates 74, 75 and 76 are connected to the gates Φ INT1 , Φ INT2 and Φ INT3 , respectively. The OR gate 91 is connected at its output terminal to the input terminal Φ TM of the micro computer. The flip-flop circuit A1 has three-stage D flip-flops 87, 88 and 89 and and an AND gate 90 to form a delay circuit having three inputs and two outputs. The first input forms a first clock input which is connected to a terminal C of the front stage D flip-flop 87, and the intermediate input forms a reset input which is connected to the terminals R of the D flip-flop's 87, 88 and 89. The third input of the delay circuit forms a center clock input which is connected to the terminals C of the intermediate stage flip-flop 88 and the rear stage flip-flop 89. One of the output terminals of the delay circuit is connected to the terminal Q of the rear stage flip-flop 89 and the other output terminal is connected to the output of the AND gate 90. The first clock input is connected to the output of the NAND gate 84. The reset input is connected to the output terminal Φ START , and the center clock input is connected to the clock terminal Φ₈. The power source voltage VAA is applied to the terminal D of the front stage D flip-flop 87. The terminal Q of the front stage flip-flop 87 is connected to the terminal D of the intermediate stage D flip-flop 88. The terminal Q of the intermediate stage D flip-flop 88 is connected to the terminal D of the rear stage D flip-flop 89 and one of the input terminals of the AND gate 90. The terminal Q of the rear stage D flip-flop 89 is connected to the other input terminal of the AND gate 90, an input terminal Φ T1M of the micro computer which is one of the outputs of the flip-flop circuit A1 and one of the inputs of the OR gate 91, and the other input of the NAND gate 74. The output of the AND gate 90 forms the other output of the flip-flop circuit A1, connected to the gate Φ T1 . The internal constructions of the flip-flop circuits A2 and A3 are similar to that of the flip-flop circuit A1. The connection of the reset terminals and the center clock inputs of the flip-flop circuits A2 and A3 are similar to that of the flip-flop circuit A1. Note that the first clock inputs of the flip-flop circuits A2 and A3 are connected to the outputs of the OR gates 85 and 86, respectively. One of the outputs of the flip-flop A2 is connected to an input terminal Φ T2M of the micro computer, one of the input terminals of the OR gate 91 and the other input terminal of the NAND gate 75. The other output of the flip-flop A2 is connected to the gate Φ T2 . One of the outputs of the flip-flop A3 is connected to an input terminal Φ T3M of the micro computer, one of the input terminals of the OR gate 91 and the other input terminal of the NAND gate 76. The other output of the flip-flop A3 is connected to the gate Φ T3 . The OR gates 84, 85 and 86 are connected at their one output terminal to the output terminal Φ STOP of the micro computer. Accordingly, the outputs of the OR gates 84, 85 and 86 are "H" when the output terminal Φ STOP is "H". The output terminal Φ STOP forms a terminal which forcedly stops the integration of the CCD image sensors 20, 30 and 40 and which becomes "H" after a lapse of a predetermined time of integration. The other input terminals of the OR gates 84 and 86 are connected to the output terminals of the comparators 78 and 82. The other input terminal of the OR gate 85 is connected to the output terminal of the OR gate 83. Inverter input terminals of the comparators 78 and 82 are connected to the monitor output terminals M1 and M3, and a non-inverter input terminal is connected to the monitor reference voltage Vref. The comparators 78 and 82 outputs "H" when the level of the monitor output terminals M1 and M3 is identical to the monitor reference voltage Vref. When the output of the comparators 78 and 82 is "H", the output of the OR gates 84 and 88 is "H". The monitor output terminals M1 and M3 output the integral value of the monitor input portions 22 and 42. The monitor reference voltage Vref is a reference value at which the integration is stopped and can be controlled by the micro computer to be selectively a standard, about half the standard, and about one fourth the standard. The OR gate 83 has three input terminals connected to the output terminals of the comparators 79, 80 and 81, respectively. The inverter input terminals of the comparators 79, 80 and 81 are connected to the monitor output terminals M21, M22 and M23. The monitor reference voltage Vref is applied to the non-inverter input terminals of the comparators. Therefore, when the level of one of the monitor output terminals M21, M22 and M23 is identical to the monitor reference voltage Vref, the comparator 79, 80 or 81 which is connected to the associated monitor output terminal becomes "H", and the outputs of the OR gates 83 and 85 become "H". Note that if the monitor light receiving portions 32 and 34 are formed by four pieces similarly to the monitor light receiving portion 22, the circuits bewteen the monitor output terminal M1 and the OR gate 84 and between the monitor output terminal M3 and the OR gate 86 are similar to that between the monitor output terminal M2 and the OR gate 85. Fig. 15B shows a drive control circuit of a single object distance measuring sensor shown in Fig. 11B. Any one of the monitor terminals M21, M22 and M23 exceeds a reference voltage Vref, the integral gate Φ T2 turned from "H" to "L" to complete the integral operation. The basic operation of the arrangement shown in Fig. 15B is similar to that shown in Fig. 15A. Integral Circuit The integral operation of the CCD image sensors will be explained below with reference to Figs. 12, 15 and 16. At the stop of integration, the output terminal Φ START is "H". In this state, since the terminal Q of the D flip-flop 73 is "L", the outputs of the NAND gates 74∼ 76, i.e. the integral control gates Φ INT1 , Φ INT2 and Φ INT3 are "H", so that no integration is performed, as shown in Fig. 13(C). The reset input of the flip-flop circuit A1 is "H". Therefore, since the output of the terminal Q of the rear stage flip-flop 89 is "H" and the output of the intermediate stage flip-flop 88 is "L", the output of the AND gate 90 is "L" . Namely, one of the outputs of the flip-flop circuit A1 is "H" and the other output is "L". Consequently, the input terminal Φ T1M is "H" and the gate Φ T1 is "L". The operation of the flip-flop circuits A2 and A3 is similar to the flip-flop circuit A1, so that the gates Φ T2 and Φ T3 are "L" and the input terminals Φ T2M and Φ T3M are "H". At the commencement of integration, the output terminal Φ START turns to "L". As a result, the terminal R of the D flip-flop 73 is "L", and accordingly the terminal Q of the D flip-flop 73 becomes "H" in accordance with a raise of the output of the terminal C and the signal "H" is latched. Conxequently, one of the inputs of the NAND gates 74∼76 becomes "H". Since the reset input of the flip-flop circuit A1 becomes "L", when the OR gate 84 becomes "H", the terminal Q of the front stage D flip-flop circuit 87 becomes "H" in accordance therewith. However, the output of the OR gate 84 is maintained "L", until the output of the monitor light receiving portion 22 reaches the monitor reference voltage Vref or the output terminal Φ STOP becomes "H" . Accordingly, the terminals Q of the front stage D flip-flop 87 and the intermediate D flip-flop are maintained "L" without change, and the terminal Q of the rear stage D flip-flop 89 is maintained "H" without change. Namely, the outputs of the flip-flop circuit A1 are maintained to be same as the value before the integration, that is, the, input terminal Φ T1M is "H" and the gate Φ T1 is "L", and accordingly the other inputs of the NAND gates 74 ∼76 are maintained "H". Consequently, the inputs of the NAND gate 74 become "H", so that the integral control gate Φ INT1 connected to the output terminal of the NAND gate 74 becomes "L". As a result, the integration of the CCD image sensor 20 and the integration of the monitor light receiving portion 22 are commenced (Fig. 12 and Fig. 13(C)). Since the flip-flop circuits A2 and A3 operate similarly to the flip-flop circuit A1, the gates Φ INT2 and Φ INT3 become "L", so that the intagration of the CCD image sensors 30 and 40 and the integration of the monitor input portions 32 and 42 are commenced. When the integration level of the monitor terminal M1 becomes the monitor reference voltage Vref, the output of the comparator 78 becomes "H", and the output of the OR gate 84 turns to "H". Namely, since the first clock input of the flip-flop circuit A1 is turned to "H", the terminal Q of the front stage D flip-flop 87 becomes "H" in accordance with a raise of the first clock input, and the terminal D of the intermediate flip-flop 88 becomes "H". Accordingly, the terminal Q of the intermediate flip-flop 88 is turned to "H" in accordance with a raise of the intermediate clock input (the clock terminal Φ₈), so that one of the inputs of the AND gate 90 becomes "H". The terminal D of the rear stage D flip-flop 89 is turned "H" at the same time when one of the inputs of the AND gate 90 becomes "H". After that, when the terminal C is turned from "L" to "H", the terminal Q of the rear stage D flip-flop becomes "L" in accordance therewith. Namely, the inputs of the AND gate 90 become "H", during a period of one cycle of the clock signal Φ₈, and the other input is then turned to "L". As a result, the other output of the flip-flop circuit A1, i.e. the gate Φ T1 is turned to "H" during a period of one cycle of the clock terminal Φ₈, and is then returned to "L" .Thus, the signal charges integrated at the gate ST are transferred to the gate Φ T1 to complete the integral operation, when the gate Φ T1 is "H" between the times t2 and t3, as shown in Fig. 12(C). When the gate Φ T1 is returned to "L" (at t3), the electric charge is confined and temprarily held in the gate Φ T1 (exactly speaking, the portion under the gate), as shown in Fig. 12(D). The terminal Q of the rear stage D flip-flop 89, i.e. one of the outputs of the flip-flop circuit A1 becomes "L". As a result, the other input of the NAND gate 74 is "L" , so that the output thereof, i.e., the integral control gate Φ INT1 is "H", and accordingly no integration is performed, as shown in Fig. 13(C). In summary, when the monitor terminal M1 is identical to the monitor reference voltage Vref, the gate Φ T1 is turned to "H" to transfer the integrated electric charge and is then returned to "L" to hold the charge. The integral control gate Φ INT1 is turned to "H" to stop the integration in a hard ware. By the operations mentioned above, in case of an object having high brightness, since the integral operation is stopped at any time when one of the monitor terminals reaches the monitor reference voltage, before a predetermined period of time lapses, no saturation of the integral values ( accumulated charges ) occurs. The flip-flop circuits A2 and A3 operates similar to the flip-flop circuit A1. The integral control gates Φ INT2 and Φ INT3 and the gates Φ T2 and Φ T3 change similar to the integral control gate Φ INT1 and the gate Φ T1 mentioned above. The center flip-flop circuit A2 stops the integration as soon as one of the three monitor terminals M21, M22 and M23 reaches the monitor reference voltage Vref, since the outputs of the OR gates 83 and 85 are "H". The micro computer detects the completion of the integration when the levels of the input terminals Φ T1M , Φ T2M and Φ T3M are turned from "H" to "L". When the micro computer detects that the integration processes of all of the CCD image sensors 20, 30 and 40 are completed (i.e. that all the electric charges of the store gate ST are transferred to the gates Φ T1 , Φ T2 and Φ T3 ) in accordance with the change in level of the terminals Φ T1M , Φ T2M and Φ T3M , the micro computer turns the terminal Φ TP and accordingly the terminals R of the D flip-flops 69 and 70 to "L". Consequently, the terminal Q of the front stage D flip-flop 69 (one of the input terminals of the AND gate 71) becomes "H" when the output of the AND gate 68 changes from "L" to "H". The terminal Q of the rear stage D flip-flop (the other terminal of the AND gate 71) is turned to "L" when the output of the AND gate 68 is changed from "L" to "H" . Since the inputs of the AND gate 71 are "H" between the time t4 at which the output of the AND gate 68 is raised and the time t5 at which the output descends, the output of the AND gate 71, i.e. the gate Φ T becomes "H", so that the charges temporarily held by the charge holding gates Φ T1 , Φ T2 and Φ T3 are moved to the portion of the integrated circuit board under the gate Φ CCD (tranfer registor 51). After that, when the output of the AND gate 68 is turned to "L", the gate Φ T is returned to "L", and accordingly, the charges moved to the gate Φ CCD are confined in the tranfer registor 51. The charges in the transfer register 51 are then transferred to the CCD output portion 52 by the two-phase clock supplied to the transfer gates Φ₁ and Φ₂. After that, the signal charges are output therefrom as video signals. Since the signal charges thus integrated are temporarily held in the portions of the integrated circuit board under the charge holding gates Φ T1 , Φ T2 and Φ T3 , the signal charges can be transferred to the tranfer registor 51 at an optional timing. Namely, the pulses can be periodically supplied to the tranfer gate Φ₁ and Φ₂ and the gate Φ CCD independently of the integration time, resulting in a compact and simple circuit construction. Video Signal Processing Circuit The processing circuit of the video signal which is output from the transfer register 51 will be explained below with reference to Fig. 17. The signal charges transferred from the CCD image sensors 20, 30 and 40 to the transfer register 51 are successively transferred to the CCD output portion 52 by the two-phase clock applied to the transfer gates Φ₁ and Φ₂. The transfer operation perse is well known and accordingly no detailed explanation therefor is given herein. The signal charges accumulated by the CCD image sensors 40, 30 and 20 are successively output in this order from the CCD output portion 52 to the Video terminal as video signals. The video signal which is first output to the Video terminal is a signal of the intercepted photoelectric converting element 41a of the CCD image sensor 40, i.e. a dark current component of the photoelectric converting element 41a. The video terminal is connected to a MOS switching element 100 and a non-inverter input terminal of an operation amplifier 101. The output is fed back to the non-inverter input terminal of the operation amplifier 101. The output terminal of the operation amplifier 101 is connected to an inverter input terminal of a differential amplifier 118 through a resistor R1. The output of the differential amplifier 118 is connected to an A/D converter through a terminal A/DIN. The intermediate portion between the resistor R1 and the inverter input terminal of the differential amplifier 118 is connected to MOS switching elements 112, 114 and 116 through resistors R2, R3 and R4. The input terminals of the MOS switching elements 112, 114 and 116 are connected to the output terminal of the differential amplifier 118. A control terminal of the MOS switching element 100 is connected to an S/H terminal. The output of the MOS switching element 100 is connected to a non-inverter input terminal of the operation amplifier 102. A condenser 103 is provided between a line connecting the output of the MOS switching element 100 and the non-inverter input of the operation amplifier 102 and the ground. The condenser 103 stores the output voltage corresponding to the electric charges of the photoelectric converting element 41a. The output of the operation amplifier 102 is fed back to the inverter input thereof. The output of the operation amplifier 102 is connected to the non-inverter input terminal of the differential amplifier 118 through a resistor R5. Between the resistor R5 and the non-inverter input of the differential amplifier 118 are connected the MOS switching element 113 through a resistor R6, the MOS switching element 115 through a resistor R7, and the MOS switching element 117 through a resistor R8, respectively. The input terminals of the MOS switching elements 113, 115 and 117 are grounded at GND and the output terminals thereof are connected to the control terminals of the MOS switching elements 112, 114 and 116 and the terminals G1, G2 and G3, respectively. The terminals G1, G2 and G3 are connected to the micro computer and can be selectively used to control three stages of the gain of the differential amplifier 118. The resistance ratio of the resistors R2, R3 and R4 is 1:2:4, and the resistance ratio of the resistors R6, R7 and R8 is 1:2:4. Namely, supposing that the gain when the terminal G1 is selected is 1, the gains when the terminals G2 and G3 are selected are 2 and 4, respectively. The video processing circuit operates as follows. A reference video signal is issued from the intercepted photoelectric converting element 41a of the third image sensor 40 to be input into the Video terminal. Synchronously with the inputting of the reference video signal due to the dark current, the micro computer outputs a sample hold pulse "H" to the S/H terminal, and accordingly, the reference video signal is stored (accumulated) in the condenser 103 through the MOS switching element 100 and is input into the non-inverter input terminal of the operation amplifier 102. The operation amplifier 102 forms a buffer, so that the stored voltage of the condenser 103 is buffer-output. The output of the operation amplifier 102 is supplied to the non-inverter input terminal of the differential amplifier 118 through the resistor R6. After the reference video signal is input, since the sample hold pulse "L" is output to the S/H terminal, the storage of the reference video signal in the condenser 103 is maintained. Supposing that the resistance value of the resistors R1 and R5 is Ra and the resistance value of the resistors R2 and R6 is Rb when the gate G1 is selected, respectively, the output voltage of the differential amplifier 118 is given by the following equation: [(Rb/Ra) × (reference video signal - video signal)] Similarly, supposing that the resistance value of the resistors R3 and R7 is 2Rb and the resistance value of the resistors R4 and R8 is 4Rb, a gain twice or three times the gain at the selection of the terminal G1 mentioned above can be obtained by selecting the terminal G2 or G3. As a result, the amplified signal in which the reference video signal component is sabtracted from the video input signal, i.e. the dark current and the level fluctuation is removed is obtained by the differential amplifier 118 and is supplied to the A/DIn terminal. Fig. 18 shows a circuit which generates the monitor reference voltage Vref. The voltage of the light interception input portion 33a of the monitor input portion 33 is input to a terminal M2D which is connected to a non-inverter input terminal of an operation amplifier 119. The output of the operation amplifier 119 is fed back to an inverter input terminal thereof. The output terminal of the operation amplifier 119 is connected to an output of a 6-bit A/D converter 121 through a resistor R9, so that the monitor reference voltage Vref is taken out from the connection of the resistor R9 and the output mentioned above. The 6-bit A/D converter 121 is of a type in which the current is output. The monitor reference voltage Vref is given by the following equation: M2D -Vref =e × n (mV) wherein e=50 (mV), n=0∼63 A predetermined 6-bit signal (n) is supplied to the input bits d1 ∼ d6 of the 6-bit A/D converter 121 from the micro computer. For instance, when "110000" is input, e × 110000 ≒ 2.4 V is obtained. By comparing the monitor reference voltage Vref with the monitor outputs M1, M21, M22, M23 and M3, the dark current component and the direct current component are removed, so that accurate charges can be detected from the monitor light receiving portions 22, 32 and 42. Camera System Fig. 19 shows a block diagram of a whole system of a camera. The CPU 130 having a function as an object distance arithmetic means controls the whole system. A power source voltage VDD1 is supplied to the CPU 130 through the battery 151 and a regulator 142. The power source voltage VDD1 is backed-up by a super capacitor condenser 143 to prevent a fluctuation due to a quick decrease of voltage of the battery 151. A port P1 of the CPU 130 is connected to a DC/DC converter 131. A plus terminal of the battery 151 is connected to the DC/DC converter 131. The DC/DC converter 131 outputs the reference voltage VAA of the control circuit of the light receiving portions and the power source voltage VDD1 of the photometer circuit. The CPU 130 is connected to a photometer A/D converter 133, an exposure control circuit 134, a winding control circuit 135, a CCD processing circuit 138, an AF motor control circuit 139, an AF motor pulser 141, a finder inside LCD 144, and a finder oudside LCD 145. A photometer switch 146, a release switch 147, a lock switch 148 and an information switch 149 are input to the CPU 130. The photometer A/D converter circuit 133 logarithmically compresses the output of the photometer light receiving element 132 and converts the analogue signal to a digital signal to input the same to the CPU 130. The exposure control circuit 134 controls the exposure by a sequential control of a mirror and a shutter blade. The winding control circuit 135 drives a film winding motor 136 to wind a film when the film is loaded and when the exposure is finished and to rewind the film when the film is finished to be taken. The CCD processing circuit 138 includes the light receiving portion control circuit, the video processing circuit and the generating circuit of the monitor reference voltage Vref to cause the light receiving portion 137 to commence the integration in order to make a video signal thereby to input the video signal into the CPU 130. The CPU 130 performs the arithmetic process, based on the video signal from the CCD processing circuit 138 to detect the defocus value and to detect the number of revolution (the number of pulses of the pulser 141 of the AF motor) and the direction of rotation, of the AF motor 140. The AF motor control circuit 139 drives the AF motor 140 in accordance with the above-mentioned information of the number of revolution and the direction of rotation from the CPU 130 to drive the focusing lens in order to effect the focusing operation. The pulser 141 of the AF motor generates the pulses in accordance with the number of revolution of the AF motor 140 to input the same into the CPU 130. The CPU 130 counts the number of the pulses produced by the pulser 141 of the AF motor to detect the number of revolution of the AF motor 140. When the number of pulses is a predetermined value, the CPU 130 supplies a stop signal to the AF motor control circuit 139 to stop the AF motor 140. The finder inside LCD 144 indicates information on focus state, shutter speed and strobe. The finder outside LCD 145 indicates photographing information on shutter speed, strobe, photograpghing modes, automatic-focus mode, and the number of taken frames of a film, etc. The photometer switch 146 and the release switch 147 are associated with a release button, so that when the release button is pushed down by a half step, the photometer switch 146 is made ON and when the release button is pushed down by a full step, the release switch 147 is made ON. When the photometer switch 146 is made ON, the integration of the CCD 137, the necessary AF arithmetic process, the drive of the AF motor 140 and the photometering process, etc. are performed. When the release button 147 is made ON, the exposure control circuit 134 operates under predetermined conditions to perform the release operation and the exposure control, so that when the exposure is finished, the film winding motor 136 is driven to wind the film. When the lock switch 148 is made OFF, even if the photometer switch 146 and the release switch 147 are made ON, the ON signals are not received by the CPU 130 which intermittently operates to detect whether or not the lock switch 148 is made ON. When the lock switch 148 is made ON, if the photometer switch 146 and the release switch 147 are made ON, the CPU 130 makes the P1 "L" and actuates the DC/DC converter 131 to supply the electric power to the circumferential circuits. The information switch 149 switches the exposure modes, the AF modes, the release modes, and the ISO sensitivity etc. The exposure modes include program modes, diaphragm manual modes, shutter manual-auto modes, etc. The AF modes include a single AF mode in which the shutter can be actuated only when the lens is correctly focused, a servo AF mode in which the shutter can be actuated regardless of focusing, and a manual focus mode, etc. The release modes include a single release mode in which the shutter can be actuated only once under the condition that the release switch 147 is turned from OFF to ON, and a successive release mode in which the shutter can be continuously actuated so long as the release switch 147 is made ON. The CPU 130 has serial communication ports P3, SCK and SI for reading data of the lens inside ROM 150 provided on the lens. The port P3 forms a reset terminal, so that it is reset at "H" and the reset is released at "L". The port SCK is a serial clock port and the port SI is a serial data input port, respectively. The communication between the CPU 130 and the lens inside ROM 150 is effected in such a way that when the port P3 is "L", the serial clock is transferred to the lens inside ROM 150 from the port SCK to activate the lens inside ROM 150 in order to output the ROM data to the port S1. The above discussion has been directed to an AF single-lens reflex camera to which the present invention is applied, by way of an example. Operation Flow The operation of the CPU 130 will be explained below with reference to Figs. 20 ∼24. Fig. 20 shows a main flow chart of an AF single-lens reflex camera. When the battery 151 is loaded, the CPU 130 inputs and checks the lock switch 148 at steps S301 and S302. If the lock switch 148 is made ON, the CPU 130 makes it possible to interrupt the control by the photometer switch 146 and the release switch 147 when made ON (step S303) and inputs information of the information switch 149 (step S304). After that, the control proceeds to step S305 at which setting processes of the exposure mode, the AF mode and the release mode, etc. are performed in accordance with information input by the information switch 149 and memorizing processes of the set modes are also performed. After that, the set information are indicated in the finder inside LCD 144 and the finder outside LCD 145 (step S306). If the lock switch 148 is OFF at step S302, the control proceeds to step S307 at which no interruption of the photometer switch 146 and the release switch 147 can be permitted. The indication of the finder inside LCD 144 and the finder outside LCD 145 disappears (step S308). After the indication process is performed at steps S306 or S308, the interval timer (125 mS) starts at step S309, so that the interruption by the timer is made possible (step S310). After that, the control is stopped at step S311. The processes mentioned above are performed once every 125 mS. If the switch, such as the photometer switch 146 is made ON, the following flow chart is interrupted. When the photometer switch 146 is made ON, the control proceeds to the routine shown in Fig. 21. In this routine, the conditions are initialized (step S321). For instance, a bit which shows whether or not the integration is performed is represented by "0", and a bit which shows whether or not the Af motor is driven is represented by "0", etc. After that, at step S322, the port P1 is made "L" to actuate the DC/DC converter 131 in order to supply the power source voltage VAA and VDD to the various devices, so that the devices can be activated. Then, the control proceeds to step S323. At step S323, the brightness signal of the object issued from the light receiving element 132 is converted to a digital signal by the photometer A/D converter circuit 133, so that the digital brightness value is input (step S323). After that, at step S324, the lens information is input by the serial communication with the lens inside ROM 150. After that, the input processes of the the photometer switch 146 and the release switch 147 are performed (step S325), the input process of the various information set by the information switch 149 and the setting process are performed (step S326), so that the control proceeds to step S326. In the illustrated embodiment, it is supposed that the AF mode is selected to be the servo AF mode. The servo AF mode is a release priority mode in which the release can be effected when the release switch 147 is made ON, regardless of focusing. At step S328, the AE arithmetic process is performed, based on the brightness value (BV value), the ISO sensitivity and the exposure mode to obtain proper TV value and AV value necessary for the exposure control, so that the values are displayed in the finder inside LCD 144 and the finder outside LCD 145 (step S329). When the arithmetic operation is finished, whether or not the release switch is made ON is checked at step S330. If the release switch is made ON, the control proceeds to step S331 at which a release operation is effected. Namely, a release magnet is activated to disengage the mirror and the shutter blades and front and rear blade magnets are activated to magnetically engage the shutter blades. After that, a diaphragm magnet is activated to fix the aperture at a predetermined value in accordance with the AV value, and the power supply to the front blade magnet is released to give a priority to the TE front blade. After the lapse of a predetermined period of time based on the TV value, the supply of the power to the rear blade magnet is released to give a priority to the rear blade to expose the film (step S323). After the exposure process is completed, the winding motor 136 is driven to effect the winding operation in which the film is wound and a mechanical charge of the mirror and the shutter is effected (step S333). After that, the control is returned to step S323. If the release switch 147 is OFF at step S330, the control proceeds to step S 334 at which whether the photometer switch 146 is made ON is checked. If the the photometer switch 146 is OFF, the control jumps to the main routine. On the contrary, if the photometer switch 146 is ON, the the control proceeds to the AF sub-routine at step S335 to perform the AF process. After that, the control is returned to step S323. The following discussion will be directed to the AF sub-routine at step S335 (Figs. 22A and 22B). At step S341, whether the Af motor 140 is driven is checked, that is, whether or not the AF motor driving bit is "1" is checked. If the Af motor 140 is being driven (bit is "1"), since the AF arithmetic process is finished, so that the AF motor 140 is being driven, based on the defocus value, the control is returned to step S323. If the Af motor driving bit is "0" at step S341, since the AF motor 140 is inoperative, the control proceeds to step S342. At step S342, whether the integration is being performed is checked, that is, whether the integral bit is "1" is checked. If the integral bit is "0", (no integration is performed), the control proceeds to step S343 to perform the processes of steps S343∼S349. If the integral bit is "1", the control proceeds to step S350. At step S343, the bits d6 ∼d1 are set to be "110000" to set a standard value of the monitor reference voltage Vref. At step S344, the integral amplifier gain of the CCD image sensors 20, 30 and 40 is set to be 1. At step S345, the integral timer which detects an excess integration time is set to be 200 mS and starts at step S346. At step S347, the interruption by the output terminal Φ TM is made possible. At step 348, the integral bit is set "1". At step S349, the output terminal Φ START is set "0" ("L") to start the integration, so that the control is returned to the interruption loop. If it is checked that the integration is being performed at step S342, the control proceeds to step S350 to check whether the integral timer is over time. If no over time is checked, the control is returned to step S341, so that the processes mentioned above are repeated until the integration is completed. If the integral timer is over time, the control proceeds to step S351 at which the interruption by the output terminal Φ TM is made possible. At step S352, the integration completion flags F3, F2 and F1 which represent that the integration of the CCD image sensors 40, 30 and 20 is finished, namely, that the integral values of the monitor output terminals M1, M2 and M3 become the monitor reference voltage Vref are set "0". At step S353, the amplifier gain of the CCD image sensors 20, 30 and 40 is set to be a standard value "1" . After that, the control proceeds to step S354. At steps S354 ∼S369, the stages (three stages) of the monitor reference voltage Vref to which the integral values of the monitor output terminals M1, M2 and M3 amount are successively judged, so that the gain of the differential amplifier 118 is set for each of the CCD image sensors 20, 30 and 40. In summary, the gains of the amplification of the integral values of the CCD image sensors 20, 30 and 40 (measuring zones) are set to make it possible to perform the necessary brightness measuring arithmetic process when the integral values of the monitor outputs M1, M2 and M3 do not reach the monitor reference voltage Vref. The gain setting process will be explained below. At step S354, whether or not the integration completion flag F1 of the second image sensor 20 is "1" . If the flag F1 is "0", the control proceeds to step S355 and if the flag F1 is "1" the control jumps to step S358. Since the first detection shows "0", the control proceeds to step S355 to judge whether or not the terminal Φ T1M is "L", that is, whether the integral value of the second monitor input portion 22 reaches the monitor reference voltage Vref. If the terminal Φ T1M is "L", the control jumps to step S358. On the contrary, if the terminal Φ T1M is "H", the control proceeds to S356. At step S356, the gain of the second CCD image sensor 20 is set "1". After that, the integration completion flag F1 is set at step S357, and then the control proceeds to step S358. At step S358, whether or not the integration completion flag F2 of the first CCD image sensor 30 is "1" is judged. If the flag F2 is "0", the control proceeds to step S359. If the flag F2 is "1", the control jumps to step S362. Since the first detection detects "0", the control proceeds to step S359 to check whether the terminal Φ T2M is "L", that is, whether the integral value of the first monitor input portion 32 reaches the monitor reference voltage Vref. If the terminal Φ T2M is "L", the control jumps to step S362. On the contrary, if the terminal Φ T2M is "H",the control proceeds to S360. At step S360, the amplification gain of the first circumferential CCD image sensor 30 is set "1" . After that, the integration completion flag F2 is set at step S361, and then the control proceeds to step S362. At step 360, the gain the first CCD image sensor 30 is set "1". After that, the integration completion flag F2 is set, and then the control proceeds to step S362. At step S362, whether or not the integration completion flag F3 of the third CCD image sensor 40 is "1" is judged. If the flag F3 is "0", the control proceeds to step S363. If the flag F3 is "1", the control jumps to step S366. Since the first detection detects "0", the control proceeds to step S363 to check whether the terminal Φ T3M is "L", that is, whether the integral value of the third monitor input portion 42 reaches the monitor reference voltage Vref. If the terminal Φ T3M is "L", the control jumps to step S366. On the contrary, if the terminal Φ T3M is "H" ,the control proceeds to S364. At step S364, the amplification gain of the second circumferential CCD image sensor 40 is set "1". After that, the integration completion flag F3 is set at step S365, and then the control proceeds to step S366. At step S366, whether G is 3, that is, whether the processes of steps S354∼S366 are repeated three times is checked. If the processes of steps S354 ∼S366 are not repeated three times, the control proceeds to step S367 to shift the bits d6 ∼d1 rightward by one bit, so that the output voltage of the 6-bit D/A converter 121 becomes half, i.e. about 1.2 V, whereby the monitor reference voltage Vref becomes half. After that, at step S368, 1 is added to G to return the control to step S354. Namely, in the first process of steps S354∼S366, the monitor reference voltage Vref makes about 2.4 V of the output voltage of the 6-bit D/A converter 121. However, in the second and third processes of steps S354∼S366, the monitor reference voltage Vref is made about 1/2 and 1/4, respectively. Consequently, three stages (steps) of gains of amplification depending on the quantity of light incident upon the CCD image sensors 20, 30 and 40 can be obtained. At step S366, if G is 3 (G=3), the control proceeds to step S369, since three processes of steps S354 ∼S366 have been already performed, so that the output terminal Φ STOP is turned to "H" to forcedly stop the integration of the CCD image sensors 20, 30 and 40. The operation is returned. According to the monitor sub-routine mentioned above, when a predetermined time of integration (200 mS in the illustrated embodiment) of the monitor light receiving portions 22, 32 and 42 and the CCD image sensors 20, 30 and 40 are performed and when the integral values of the monitor light receiving portions 22, 32 and 42 are the monitor reference voltage Vref within a predetermined period of time, the integration is stopped in a hard ware. Even if the integral values of the monitor light receiving portions 22, 32 and 42 do not reach the monitor reference voltage Vref within a predetermined period of time, the integration is stopped in a soft ware after the lapse of a predetermined time, at step S369. After the lapse of a predetermined time and before the stop of the integration, the integral values of the monitor light receiving portions 22, 32 and 42 are checked in three steps (stages) of levels. Depending on the levels, the integral value amplification levels can be determined. Namely, if the integral value is small, the integral value is amplified with a gain twice or four times the standard gain. Accordingly, even if all or parts of the objects in the measuring zone are dark, the data for sufficient measuring arithmetic inputs can be obtained. The integration of the CCD image sensors and the transfer of the electric charges will be explained below with reference to Figs. 23A and 23B. The flow chart shown in Figs. 23A and 23B is interrupted under the condition that the input terminal Φ TM is "L". The input terminal Φ TM is "H" at the commencement of the integration and during integration, and becomes "L"at the stop of the integration. When the input terminal Φ TM is "L", the gates Φ T1 ∼Φ T3 change like "L"→"H"→"L", so thatthe electric charges accumulated in the vicinity of the gate ST are transferred to the vicinity of the gate Φ T (Fig. 12 (C) and (D)). At step S371, the output terminal Φ TP is turned to "L", so that the control proceeds to step S372. When the output terminal Φ TP is "L", the gate Φ T is turned to "H" as soon as the clock terminals Φ₁₆ and Φ₆₄ are "H" and the clock gate Φ32 is "L", so that the electric charges accumulated in the vicinity of the gates Φ T1 , Φ T2 and Φ T3 are transferred to the CCD transfer portion 51 (Fig. 12(E) and (F)). The electric charges accumulated in the CCD transfer portion 51 are transferred to the CCD output portion 52 by the gates Φ₁ and Φ₂ to which the two-phase clock pulses are applied. At steps S372 ∼S386, the number of pulses of the gate Φ₁ at the CCD output portion 52 is counted to detect the light receivng element of the light receivng portion having the integral value corresponding to the video signal issued from the CCD output portion 52. In the illustrated embodiment, the output of the intercepted photoelectric converting element 41a corres ponds to the fifth pulse, and the outputs of the light receiving portions 40, 30 and 20 correspond to any one of the 10 ∼109th pulses, any one of the 120∼219th pulses and any one of the 230 ∼329th pulses, respectively. At step S327, the number of pulses of the gate Φ₁ is counted. After that, at step S373, whether five pulses are produced at the gate Φ₁ is checked. The check is repeated until five pulses are produced. When five pulses are detected, the control proceeds to step S375 at which an S/H pulse is output to store (memorize) the video signal in the condenser 82. When the video signal is stored, the control proceeds to step 375 at which the gain of the differential amplifier 118 is set to be the gain which has been set at step S364. After that, the control proceeds to step S376. At step S376, the control does not proceed until the video signal is produced from the third image sensor 40, that is, until the number of pulses of the gate Φ₁ is 10. When 10 pulses are counted, the control proceeds to step S 377 at which the video signal amplified by the differential amplifier 118 and converted into a digital signal by the A/D converter is stored in the RAM. This process is repeated until 119 pulses are counted, so that the video signals from the photoelectric elements of the third CCD image sensor 40 are successively stored in the RAM. Namely, 100 video signals (10th ∼109th) are stored in the RAM. When the 110th pulse is detected, the control proceeds to step 379 at which the gain of the differential amplifier 118 is set to be the gain which has been set at step S360. After that, at step S380, the number of pulses is counted until the 130th pulse is issued. When the 120th pulse is detected, the control proceeds to step S381 at which the video signal amplified by the differential amplifier 118 and converted into a digital signal by the A/D converter is stored in the RAM. This process is repeated until 219 pulses are counted, so that the video signals from the photoelectric elements of the first CCD image sensor 30 are successively stored in the RAM. Namely, 100 video signals (130th∼229th) are stored in the RAM. When the 230th pulse is detected, the control proceeds to step 383 at which the gain of the differential amplifier 118 is set to be the gain which has been set at step S356. After that, at step S384, the number of pulses is counted until the 230th pulse is issued. When the 230th pulse is detected, the control proceeds to step S385 at which the video signal amplified by the differential amplifier 118 and converted into a digital signal by the A/D converter is stored in the RAM. This process is repeated until 329 pulses are counted, so that the video signals from the photoelectric elements of the second circumferential CCD image sensor 20 are successively stored in the RAM. Namely, 100 video signals (220th ∼329th) are stored in the RAM. Thus, the video signals issued from the photoelectric elements of the CCD image sensors 40, 30 and 20 are successively stored in the RAM. When the storing operation is completed, the control proceeds to step S387 at which the integral bit is reset "0". After that, at step S388, the output terminal Φ START is set "1" , and at step S389, an interruption by the input terminal Φ TM is made impossible. At steps S390, S391 and S392, the predictor arithmetic processes (of a known correlation method) are performed for every video signals of the CCD image sensors 20, 30 and 40 stored in the RAM to detect the object distance and the defocus value for every CCD image sensors 20, 30 and 40. After that, at step S393, the measuring zones 12, 13 and 14 of the shortest object distance are detected, so that the focusing operation is performed for the objects of the measuring zones 12, 13 and 14. At step S395, the focusing state is checked. If the lens (camera) is correctly focused, the control proceeds to step S395 to indicate the in-focus state in the finder inside LCD 144. If the lens (camera) is not focused, the control jumps to step S396. At step S396, the pulses which define the number of revolution of the AF motor 140, based on the result of the predictor arithmetic process are set. After that, the interruption by the AF motor pulse counter is made possible at step S397. At step S398, the AF motor drive bit is "1" to drive the AF motor 140. After that, the control is returned. When the AF motor 140 rotates, the AF motor pulser 121 produces the pulses, so that the number of pulses is counted by the counter provided in the CPU 130. When the number of pulses becomes the value set at step S396, the AF motor stop routine is interrupted (step S401) to stop the AF motor 140. After that, at step S302, the AF motor drive bit is set "0". The control is then returned. In the illustrated embodiment, the brightnesses of the objects in the three measuring zones are detected by the monitor light receiving portions to adjust the time of integration or the gain, and accordingly even if there is a large difference in brightness between the measuring zones, a precise object distance can be detected for every measuring zone. As mentioned above, according to the present invention, the object distances of the objects in all the measuring zones are detected, so that the focusing is effected for the object of the shortest object distance. Therefore, if the object to be taken is not located in the center of the finder filed of view, namely, for example, if spaced human figures are located in the right and left measuring zones, so that the background appears in the center filed of view, the focusing is effected for the human figure having the shortest object distance in the right or left measuring zone. As a result, complicated and troublesome operations of the prior art in which after the human figure is first positioned in the center measuring zone, a so-called focus lock is effected, and the camera is then moved to have a desired composition are unnecessary in the present invention. Namely, according to the present invention, a desired composition can be easily and simply realized. It is also possible to effect the focusing for an object of the longest object distance or an optional object distance (optional measuring zone) which is selected by a photographer. As can be seen from the foregoing, according to the present invention, since the measuring zone is provided above the center of the finder field of view, upon taking a picture of a human figure, a face of the human figure is located in the measuring zone, so that the photographer's eyes substantially coincide with the face of the human figure, resulting in no miss of a shutter chance. Also, according to the present invention, photoelectric (converting) elements are arranged in the shape of inverted U, no snake-like bend of the signal transfer memebrs as in the prior art is necessary. This results in a decreased transfer distance of the signal charge, in the present invention. Furthermore, according to the present invention, since the quantities of light incident upon the object distance measuring sensors for each of the measuring zones are detected, so that when the quantities of light of the monitor light receiving portions reach a predetermined value, the integrationn of the associated object distance measuring sensor is stopped, the time of integration can be properly controlled for every measuring zone. In addition, if the amplification gain of the signal charge of each measuring zone can be independently controlled, even if there is a measuring sensor in which the monitor value does not reach a predetermined value, a proper signal charge can be obtained for each of the measuring sensors by increasing the signal charge of that measuring sensor in which the monitor value does not reach a predetermined value to be larger than the output gain or gains of the other measuring sensor or sensors, thus resulting in a precise detection of the object distance for each measuring zone. As can be understood from the above discussion, according to the present invention, since the object distance can be porecisely detected for each of the measuring sensors, regardless of the brightness of the objects in the measuring zones, the apparatus of the present invention can be advantageously applied to an AF device in which the object distance of each of the measuring zones is detected to focus the lens at an optimum depth of field. Furthermore, in the self-scanning image sensor according to the present invention, since the electric charges are temporarily held by the charge holding portion provided between the integral portion and the charge tranfer portion, the integral operation can be stopped regardless of the state of the charge transfer portion, and accordingly, for example, precise object distance data particularly for an high brightness object can be obtained. Furthermore, the stop of the integral operation can be controlled by a simple control circuit.

Claims: A focus detecting apparatus for a camera having a finder (8) comprising an object distance measuring sensor array (S1, S2, S3) on which the luminous flux originating from objects to be photographed in an object distance measuring zone (12) corresponding to a field in a finder field of view (11) is converged by an optical system, and an object distance measuring arithmetic means (138) for integrating the output of the object distance measuring sensor array (S1,S2,S3) to detect the object distance in said object distance measuring zone (12) in accordance with the integrated value, wherein said sensor array (S1, S2, S3) comprises a photoelectric converter array (20, 30, 40) having a number of photoelectric converting elements, a monitor light receiving portion (22, 32, 42) in the vicinity of the photoelectric converter array (20, 30, 40) to receive the quantity of light incident upon said sensor array (S1, S2, S3) in order to control its charge integrating time, an integrating portion (ST) which integrates the signal charges obtained by said photoelectric converting elements, a signal charge transferring register (51) which outputs the signal charges to said arithmetic means (138), and control means for transferring the integrated signal charges from the integrating portion (ST) when the quantity of light received by the monitor light receiving portion (32) first amounts to a predetermined value prior to the lapse of a predetermined integration time or when a predetermined integration time lapses before the quantity of light received amounts to a predetermined value, characterized in that said sensor array (S1, S2, S3) has a charge holding portion (Φ T1 , Φ T2 , Φ T3 ) which temporarily holds the integrated signal charges before their transfer to said transferring register (51), that said control means transfers all the signal charges held by the charge holding portion (Φ T1 , Φ T2 , Φ T3 ) into the charge transferring register (51) after completion of said transferring of signal charges from the charge integrating portion (ST) to the charge holding portion (Φ T1 , Φ T2 , Φ T3 ), that said object distance measuring zone (12) is a first measuring zone located above the centre of the finder field of view (11), that second and third measuring zones (13, 14) are located on opposite sides of the centre of the finder field of view (11), that one object distance measuring sensor (S2) of the sensor array and two additional sensors (S1, S3) of said sensor array of equal design corresponding to said first, second and third measuring zones (12, 13, 14) are arranged as an array of generally inverted U-shape, that the gains of the outputs of the object distance measuring sensors (S1, S2, S3) are independently variable, that each of said object distance measuring sensors (S1, S2, S3) has a separate monitor light receiving portion (22, 32, 42) and a separate integration time controlling portion (Φ INT1 , Φ INT2 , Φ INT3 ) for starting and stopping its integration, and that said photoelectric converter arrays (20, 30, 40), said monitor light receiving portions (22, 32, 42), said charge holding portions (Φ T1 , Φ T2 , Φ T3 ), said integration time control portions (Φ INT1 , Φ INT2 , Φ INT3 ) and a common transferring register (51) are formed on a single integrated circuit board. A self-scanning image sensor comprising a light receiving portion (130) having a number of photoelectric converting elements, an integrating portion (ST) which integrates the signal charges obtained by the photoelectric converting elements, a charge transferring register (151) which outputs said signal charges transferred thereto by means of a transferring portion (Φ T ), a monitor sensor portion (132) for receiving the light incident upon said photoelectric converting elements in order to control the charge integrating time of the sensor to avoid saturation thereof, and control means for transferring the integrated signal charges from said integrating portion (ST) when the quantity of light received by the monitor sensor portion (132) first amounts to a predetermined value prior to the lapse of a predetermined integration time or when a predetermined integration time lapses before the quantity of light received amounts to a predetermined value, wherein said light receiving portion (130), said monitor sensor portion (132), said integrating portion (ST), said transferring portion (Φ T ) and said charge transferring register (151) are formed on a single integrated circuit board, characterized by a charge holding portion (Φ T2 ) which temporarily holds the signal charges transferred thereto by said control means from said integrating portion (ST) before their transfer to said charge transferring portion (Φ T ), and an integration control portion (Φ INT2 ) adapted to control the start and stop of the integration of charges in said light receiving portion (130) independent from the state of said charge transferring register (151). The image sensor according to claim 2, characterized in that the integration control portion (Φ INT2 ), the integrating portion (ST), the charge holding portion (Φ T2 ) and the transferring portion (Φ T ) are provided between the light receiving portion (130) and the transferring register (151). The image sensor according to claim 2 or 3, characterized in that transferring gates (Φ₁, Φ₂) are provided on the surface of said transferring register (151) along the length thereof. The image sensor according to any one of claims 2 to 4, characterized in that said transferring portion (Φ T ) is a shift gate. The image sensor according to any one of claims 2 to 5, characterized in that said charge holding portion (Φ T1 ) is provided between said integrating portion (ST) and said transferring portion (Φ T ). The image sensor according to claim 6, characterized in that said integration control portion (Φ INT1 ) is provided next to said integrating portion (ST). The image sensor according to any one of claims 2 to 7, characterized in that said light receiving portion (130) is spaced from and vertically aligned with the integrating portion (ST), the integration control portion (Φ INT1 ) and the charge holding portion (Φ T1 ), being provided on opposite sides of said integrating portion (ST). The image sensor according to any one of claims 2 to 8, characterized in that said monitor sensor portion (132) is connected with a floating diffusion portion (55) via said integrating portion (ST), said diffusion portion (55) being connected to a buffer (57) and to the source electrode of an n-channel depletion FET (56) the gate electrode of which is connected with said integration control portion (Φ INT1 ) whereas the drain electrode is connected with a voltage source.

Inventors: KAWASAKI MASAHIRO C O ASAHI KO, SHINDO OSAMU C O ASAHI KOGAKU, KAWASAKI, MASAHIRO C/O ASAHI KOGAKU KOGYO K.K., SHINDO, OSAMU C/O ASAHI KOGAKU KOGYO K.K.
Applicants: ASAHI OPTICAL CO LTD, ASAHI KOGAKU KOGYO KABUSHIKI KAISHA
Application year: 1989
Main classification: G03B3
IPC codes: G03B13, G02B7