AUDIO SIGNAL DEMODULATION CIRCUIT

Abstract: An external clock signal is subjected to frequency division to supply circuits with low frequency clock pulses. Furthermore, provision is made of a logic circuit (1) which fixes the clock or the input data to the high level or to the low level during a period of other than the voice signals, the clock or the input data being input to the circuit that processes the signals of before the time axis is being extended in response to timing pulses generated in synchronism with the video signals.

Description: TECHNICAL FIELD The present invention relates to an audio signal demodulating circuit for demodulating an audio signal from a high definition television signal (MUSE signal). BACKGROUND ART In recent years, high definition television ("high vision"), which provides more impression and deeper presence feeling and higher audio quality than convention television, has been developed. The MUSE system proposed by NIHON HOSO KYOKAI (NHK) is an example of the associated transmission system. The MUSE system is described in more detail in the NHK Technical Research Report (SHO-62), Vol. 39, No. 2, Consecutive Volume Number 172, Development of MUSE system, Pages 18-53. In the MUSE system, an audio signal is time-division multiplexed during a video V-blanking period. Referring now to the drawings, an explanation will be given of a circuit for demodulating an audio signal in the MUSE system. Fig. 5 is a block diagram of a conventional audio signal demodulating circuit, Fig. 6 is a timing chart of an audio signal in the circuit, and Fig. 7 is a MUSE transmission signal format. In Fig. 5, numeral 2 is an input changing circuit for changing the gain of an input data signal depending on whether the input data signal is in an AM mode or an FM mode. Numeral 3 is an audio low pass filter (LPF) circuit for producing an audio data signal upon receipt of an output signal of the input changing circuit 2. Numeral 4 is a ternary-to-binary converting circuit for converting an audio data signal output from the LPF circuit, which is a ternary two symbol audio data signal, into a binary three symbol audio data signal. Numeral 5 is a time-base extension circuit for receiving an audio data signal multiplexed during vertical blanking periods of a video signal and extending the time base of the received audio data signal to restore it to a continuous audio signal. Numeral 6 is an inter-frame de-interleave circuit for canceling the inter-frame de-interleave applied to an audio data signal at the transmission side. Numeral 7 is a timing signal generating circuit for producing several kinds of timing signals on the basis of a frame pulse (FP) and a horizontal pulse (HD) supplied from an image synchronization circuit (not shown). Numerals 8, 9 and 10 are frequency division circuits for frequency-dividing an input clock. The operation of the audio signal demodulating circuit as constructed above will be explained below. First, an n-bit input audio data signal supplied to a data input terminal is changed in its gain corresponding to its mode by the input changing circuit 2, since the multiplexing level of an audio data signal differs between the AM mode and the FM mode, and the data signal, which has thus been changed to have an audio multiplexing level common to the AM mode and the FM mode, is supplied to the LPF circuit 3. The LPF circuit 3 constitutes a digital LPF circuit having a 6 MHz root cosine roll-off characteristic which serves as an audio low pass filter. The ternary-to-binary converting circuit 4 converts the audio data signal from a ternary two symbol signal into a binary three symbol signal. In this case, an audio signal has been time-multiplexed during the vertical blanking periods of a video signal, as illustrated in the MUSE transmission signal format shown in Fig. 7, to have a time-base arrangement shown at (E) of Fig. 6. The time-base extension circuit 5 extracts this time-multiplexed audio signal and extends its time base to provide a continuous audio signal as shown at (D) of Fig. 6. Then, since the input audio signal has been previously inter-frame interleaved at the transmission side in order to disperse a possible burst error occurring in the transmission system, the inter-frame de-interleave circuit 6 operates to cancel the inter-frame interleave at the receiving side. Thus, a continuous audio signal is outputted from a data output terminal as an output data. Additionally, the timing signal generating circuit 7 generates and supplies several kinds of timing signals synchronized with frames of a video signal, such as used for extracting an audio signal in the time-base extension circuit 5, on the basis of a frame pulse (FP) and a horizontal pulse (HD) supplied from the video synchronization circuit (not shown). Further, the frequency division circuits 8, 9 and 10, frequency-divide a basic clock (=16.2 MHz) supplied to a clock input terminal from the outside and produces several kinds of clocks having the frequencies of 2.025 MHz, 1.35 MHz, etc. However, a conventional audio signal demodulating circuit of the above construction comprises many components operating at a higher clock frequency (16.2 MHz), so that it consumes undesired excessive electrical power. DISCLOSURE OF INVENTION An object of the present invention is to provide an audio signal demodulating circuit which can reduce electrical power consumption. The audio signal demodulating circuit according to the present invention, and as defined by Claim 1, attains this object. BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a block diagram showing the audio signal demodulating circuit according to an embodiment of the present invention; Fig. 2 is a timing chart for signals appearing in the audio signal demodulating circuit shown in Fig. 1; Fig. 3 is a block diagram showing the audio signal demodulating circuit according to another embodiment of the present invention; Fig. 4 is a timing chart for signals appearing in the audio signal demodulating circuit shown in Fig. 3; Fig. 5 is a block diagram showing a conventional audio signal demodulating circuit; Fig. 6 is a timing chart for an audio signal appearing in the audio signal demodulating circuit shown i Fig. 5; and Fig. 7 is a drawing showing a MUSE transmission signal format. BEST MODE FOR CARRYING OUT THE INVENTION Now referring to the drawings, an explanation will be given of an audio signal demodulating circuit according to one embodiment of the present invention. Fig. 1 is a block diagram showing the audio signal demodulating circuit according to an embodiment of the present invention. Fig. 2 is a timing chart for signals appearing in the audio signal demodulating circuit. In Fig. 1, numeral 2 is an input changing circuit; numeral 3 is an LPF circuit; numeral 4 is a ternary-to-binary converting circuit; numeral 5 is a time-base extension circuit; numeral 6 is an inter-frame de-interleave circuit; and numeral 7 is a timing generating circuit. These constituent circuits are identical to those of the conventional audio signal demodulating circuit. The audio signal demodulating circuit according to the present invention is characterized by the provision of a logic circuit 1 for fixing a clock signal to a low level during a time period for processing a signal other than an audio signal by using an output signal from the timing generating circuit. In the above arrangement, an input data signal shown at (A) of Fig. 2 is applied to the input changing circuit 2, whose gain is changed in accordance with the AM mode and the FM mode having different audio signal multiplexing levels, so that the audio signal multiplexing levels may be made equal to each other. Then, in the LPF circuit 3, the audio signal thus changed passes through a low-pass filter for audio signals having a 6 MHz root cosine roll-off characteristic. Then, the audio signal is converted from a ternary two symbol signal into a binary three symbol signal through the ternary-to-binary converting circuit 4. On the other hand, several kinds of timing signals synchronized with a video signal are generated through the timing generating circuit 7 on the basis of a frame pulse (FP) and a horizontal pulse (HD) supplied from a video synchronization circuit (not shown). One of the timing signals is a pulse such as shown at Fig. 2(B) which is synchronized with the period of the audio signal. By using this timing signal such as shown at Fig. 2(E), the logic circuit 1 fixes the clocks to a low (or high) level as shown in Fig. 2(E) during a time period for processing signals other than an audio signal. The resultant clocks are used as a clock signal for the input changing circuit 2, the LPF circuit 3 and the ternary-to-binary converting circuit 4. Therefore, the output from the ternary-to-binary converting circuit 4 is substantially fixed to the low (or high) level during the period other than the audio signal period, as shown at Fig. 2(C). The time-base extension circuit 5 extracts the audio signal, which has been time-multiplexed during a video vertical blanking period, and extends its time-base to -form a continuous audio signal as shown at Fig. 2(D). Further, the inter-frame de-interleave circuit 6 cancels the inter-frame interleave applied to the audio signal at the transmission side to produce an output data. Additionally, the frequency division circuits 8, 9 and 10 frequency-divide a basic clock (= 16.2 MHz) supplied from the outside to supply (resultant) clocks having the frequencies of 2.025 MHz and 1.35 MHz to the time-base extension circuit 5 and the inter-frame de-interleave circuit 6. In accordance with the present invention, the logic circuit 1 is provided to fix the clock signal to a low (or high) level during the period other than the audio signal period, so that the clock signal and the input data signal are fixed during the period other than the audio signal period, thereby greatly reducing electric power consumption. Figs. 3 and 4 show the second embodiment of the present invention. In this embodiment, the timing generating circuit 7 generates a timing signal such as shown at Fig. 4(B) which is synchronized with the period of the audio signal. By using this timing pulse signal, a logic circuit 1′ operates to fix only MSB of the n-bits signal during the period other than the audio signal period to a high level and the remaining (n-l)-bits to a low level as shown at Fig. 4(C). Thus, in this embodiment, the level of the signal during the period other than the audio signal period is fixed, so that electric power consumption can be reduced. INDUSTRIAL APPLICABILITY In accordance with the present invention, a logic circuit is provided which uses a timing signal generated in the timing generating circuit in synchronism with a video signal so as to fix the clock signal or input data signal to be supplied to the circuits, which process a signal before it is subjected to time-base extension, to a high level or a low level. Thus, the clock signal or input data signal during the period other than the audio signal period can be fixed to a high level or a low level, so that electric power consumption of the entire audio signal demodulating circuit can be remarkably reduced.

Claims: A demodulating circuit for a MUSE television signal, the circuit including: a gain changing circuit (2) having a signal input for receiving the MUSE signal, and a gain which depends on whether an audio signal, in the MUSE signal, is in an AM or FM mode; an audio low pass filter (3) for receiving the output of the gain changing circuit (2); a ternary-to-binary converting circuit (4) for converting the output of the audio low pass filter (3) from a ternary two symbol signal to a binary three symbol signal, the output of said converting circuit (4) being in the form of time multiplexed audio signals; a time-base extension circuit (5) for extending the time base of the time multiplexed audio signals so as to provide a continuous audio signal; an inter-frame de-interleave circuit (6) for cancelling an inter-frame interleave in the continuous audio signal; a clock pulse input for external clock pulses; a timing signal generating circuit (7) for generating a plurality of timing signals in response to frame and horizontal pulses in the MUSE signal; and frequency division circuits (8,9,10) for frequency dividing the external clock pulse input, the components of the demodulating circuit, which includes said gain changing circuit (2), said audio low pass filter (3), said ternary-to-binary converting circuit (4), said time-base extension circuit (5) and said inter-frame de-interleave circuit (6), being controlled by said clock pulse input, said timing signals and said frequency divided clock pulse input, characterised in that the demodulator circuit further includes a logic circuit (1), which receives one of said timing signals, and which generates a high or low level signal which inhibits high frequency operation of said components, during periods other than when the time-multiplexed audio signals are output from said ternary-to-binary converting circuit (4) so as to reduce power consumption of said components in said periods. A circuit according to Claim 1, wherein the logic circuit (1) and the frequency division circuits (8,9,10) receive said clock input, and wherein an output of the logic circuit (1) is supplied to said gain changing circuit (2), said low pass filter (3) and said ternary-to-binary converting circuit (4). A circuit according to Claim 1 wherein the logic circuit is connected to the input of said gain changing circuit (2).

Inventors: ARITA HISASHI - WAKABA -CHOME, IWAMOTO TAKUSHI, KAWASHIMA TADASHI, NINOMIYA YUICHI - TAKAISHI -CH, OHTSUKA YOSHIMICHI - IKUTA -CH, OKUMURA NAOJI, ARITA, HISASHI 3-7, WAKABA 2-CHOME, IWAMOTO, TAKUSHI, KAWASHIMA, TADASHI, NINOMIYA, YUICHI 17-4, TAKAISHI 2-CHOME, OHTSUKA, YOSHIMICHI 10-10, IKUTA 6-CHOME, OKUMURA, NAOJI
Applicants: JAPAN BROADCASTING CORP, MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., NIPPON HOSO KYOKAI
Application year: 1989
Main classification: H04N5
IPC codes: H04N5, H04N7, H04B1