Floating point arithmetic units

Abstract: In a floating point arithmetic unit an iterative binary arithmetic operation is performed upon two operands (D₁, D₂) applied to the unit in floating point form. The unit includes respective operating portions for deriving mantissa, exponent and sign components of the desired result (D₃) respectively, the mantissa operating portion including fixed point multiplication means (10) for multiplying together the respective mantissa components of the two operands concerned, and subtraction means (41, 42, 15) operative, in each cycle of the iterative operation, to form the inverse of the fractional part of a binary number derived from the output of the said multiplication means (10) and to increment that inverse by adding one to the least significant bit thereof. The use of such a floating point arithmetic unit can enable division and square root operations, for example, to be performed at high speed and with desirably high accuracy.

Description: The present invention relates to floating point arithmetic units for use, for example, in carrying out division or square root operations on numerical values expressed in floating point notation. Arithmetic operations using operands supplied in floating point form can provide wide dynamic range and high accuracy, and accordingly such floating point operations are advantageously used in various high-level computing operations, in which, for example, high speed processing of division and square root operations is required. Division operations may be carried out by using a number of methods, for example, substraction and shift, and converging methods such as the Newton-Raphson method. In the substraction and shift method, the shifted divisor is repeatedly subtracted from a dividend; one form of this method, known as the non-restoring method, can calculate the required quotient at high speed. In a converging method, the reciprocal of the divisor is calculated by an iterative process and this reciprocal is then multiplied by the dividend to obtain the quotient. In this method, the number of operation cycles needed to produce the required result is reduced as compared with other methods, provided that an initial assumed value of the reciprocal is sufficiently close to the true value finally obtained by the iterative process. A converging method (e.g. Newton-Raphson method) may also be used in square root operations. In this method the square root of a number B is produced by first calculating 1/ B and then multiplying the obtained value by B to give B . When a calculation of 1/ B is executed by the Newton-Raphson method, the number of operational cycles needed may be kept desirably small provided that the initial assumed reciprocal value for the square root ( 1/ B ) is close to the final desired value. Many of the known floating point arithmetic units utilize the Newton-Raphson method because, in other methods, the quotient obtained by one cycle is only accurate to at most 3 to 4 bits, so that to obtain the final quotient, the calculations must be repeated for eight cycles in order to achieve a result in conformity with the IEEE single-precision standard. In contrast, in the Newton-Raphson method, if the assumed initial value of the reciprocal is sufficiently close to the true value required, the quotient may be obtained by an iterative converging calculation requiring only about 3 to 4 cycles, and accordingly, in such a dividing operation using the Newton-Raphson method, the quotient can be obtained at a higher speed than with the other methods. Many units also utilize the Newton-Raphson method for the square root operation, since here too, provided that the initial assumed reciprocal root value is sufficiently accurate, a converging calculation of about 3 to 4 cycles is sufficient, and accordingly, such a square root operation by the Newton-Raphson method can be processed at a high speed. A division operation using the Newton-Raphson method is explained below. In a first step of the division operation, a reciprocal function is calculated. For example, the division expression C = A/B may be expressed, using a reciprocal form, as C = A(1/B). The reciprocal function (1/B) is calculated by the Newton-Raphson method using iteration of the formula: X i+1 = X i (2 - BX i ) where, i = 0, 1, 2, ...; X 0 is the initial assumed value of the reciprocal of the divisor B; and X i is the ith approximation of (1/B). If the initial value X 0 satisfies the inequality (2/B) > |X 0 | > 0, convergence of the iterative calculation is assured. In a typical method of obtaining the initial value, the upper 10 bits (small variations in this number being possible) of the divisor are used as a pointer to a memory (ROM) holding a look-up table of initial values. The ROM outputs the appropriate initial value X 0 in response to an address indicated by the pointer bits of the divisor. The output initial value (X 0 ) typically has substantially the same number of bits as the applied pointer (in this example, 10 bits). In the case of a floating point division operation, the reciprocals of both an exponent portion and a mantissa portion are obtained in this way from respective look-up tables (ROM). The looked-up initial value X 0 is used in an iterative process to determine 1/B, whereafter two binary operands D 1 (=A) and D 2 (=1/B) are expressed in floating point form, as follows, D 1 = (-1) Sa 2 Ea-BS D 2 = (-1) Sb 2 Eb-BS where Sa is the sign of the operand D 1 Sb is the sign of the operand D 2 Ea is the exponent of the operand D 1 Eb is the exponent of the operand D 1 BS is a predetermined negative exponent bias (1.Fa) denotes the mantissa of the operand D 1 which is of fixed point format having one significant digit before the binary point, and (1.Fb) denotes the mantissa of the operand D 2 which is of fixed point format having one significant digit before the binary point, and the following operations are executed. The respective mantissas (1.Fa) and (1.Fb) of the input data D 1 and D 2 are multiplied together, by means of a fixed point multiplication circuit, to obtain the result (1.Fa) x (1.Fb). This result is necessarily either of the form 1.xxxx... or 1x.xxxx.... Although 1.xxxx... is already normalized, 1x.xxxx... still remains to be normalized. This normalization is executed in response to an overflow signal by shifting the data to the right by one bit and by increasing the exponent portion by one. Then, the normalized value may be rounded off to place the output data in the required format. If the bits are all "1", an overflow occurs, and in this case the data is shifted by one bit to the right. The above processes provide a final output which is a normalized number constituting the mantissa of A/B. To determine the required exponent, the operation (Ea + Eb) is executed and the result is added to a negative bias (-BS); i.e. (Ea + Eb - BS) is obtained. Then, if the above-mentioned overflow is generated during normalization, the exponent value is incremented by one as mentioned above. A similar exponent increment operation is performed in the case of an overflow arising from the rounding off process. A sign operation is performed by an exclusive OR circuit, to give the sign of the quotient A/B. When the above-described division process is carried out, using a floating point binary arithmetic unit, calculation of the reciprocal (1/B) of the divisor by the iterative process based on the formula X i+1 = X i (2 - BX i ) requires the multiplication BX i , the subtraction (2 - BX i ), and the multiplication X i (2 - BX i ). In particular, an addition or subtraction circuit has conventionally been included, to execute the subtraction (2 - BX i ) , and each step in the above iterative process conventionally requires three separate arithmetic operations. For example, US 4594680 describes a floating point arithmetic unit, for executing an iterative binary arithmetic operation upon two operands applied to the unit in floating point form, which unit includes respective operating portions for deriving mantissa, exponent and sign components of the desired result respectively, the mantissa operating portion including fixed point multiplication means for multiplying together the respective mantissa components of the two operands concerned. In this floating point arithmetic unit the subtraction means include an adder which is used to perform a two's-complement decrement operation, and a complementer which performs a one's-complement operation on the output of the adder. Another floating point arithmetic unit (divider), described in "High-speed divider using multiplication", K J Burkhardt and S Leung, Microprocessors and Microsystems, vol 5, no. 6, August 1981, simply employs a one's complementer as the subtraction means, but in this case the exact formula 2-BX i cannot be used and is replaced by the approximation 2-2 -16 -BX i . This approximation provides high-speed operation, but a large error occurs. In a square root operation using a Newton-Raphson method, a reciprocal function is calculated, so that, for example, C = B is expressed as C = B(1/ B ) . The appropriate iterative process in such a Newton-Raphson method can be based on the formula: X i+1 = (1/2)*X i (3 - BX i 2 ) where X 0 (corresponding to i = 0) is an assumed first approximation to the reciprocal of B ; X i is an ith approximation value; and the asterisk denotes multiplication. If the initial value X 0 satisfies the inequality 0 < X 0 < 3/B , the iterative calculation will converge, and the operation can be completed. In a typical method of obtaining the initial value, as described above, the upper 10 bits (small variation in this number being possible) of B are applied to a look up table (ROM) as a pointer, and the ROM supplies the appropriate initial value X 0 from the memory location in accordance with the value of B. Typically, the number of bits in the initial value X 0 is substantially the same as that of the pointer. Generally, in floating point operations, the reciprocals of the exponent and the mantissa are derived in this way from respective look up tables. In the square root operation, to find 1/ B an iterative process based on the formula X i+1 = (1/2)*X i (3 - BX i 2 ) must be performed, so that each iterative cycle comprises the following five arithmetic operations: MLT: B*X i (hereinafter B*X i = Y i ) MLT: Y i *X i SUB: 3 - (Y i *X i ) MLT: X i *(3 - (Y i *X i )) MLT: (1/2)*(X i *(3 - (Y i *X i ))) where MLT denotes multiplication, and SUB denotes subtraction. According to the present invention there is provided a floating point arithmetic unit, for executing an iterative binary arithmetic operation upon two operands applied to the unit in floating point form, which unit includes respective operating portions for deriving mantissa, exponent and sign components of the desired result respectively, the mantissa operating portion including fixed point multiplication means for multiplying together the respective mantissa components of the two operands concerned; characterised in that the mantissa operating portion further includes subtraction means operative, in each cycle of the iterative operation, to form the inverse of the fractional part of a binary number derived from the output of the said multiplication means, which derived binary number is greater than 0 and less than or equal to 1, and to increment that inverse by adding one to the least significant bit thereof, thereby to produce a binary output value representative of the difference between a first predetermined positive integer and the said derived binary number without adding that integer to the derived binary number, the said first predetermined positive integer being 2 or 3. Such a floating point arithmetic unit can perform one or each of the above-mentioned iterative processes required in division and square root operations, for example, in a manner that is more efficient than hitherto conventional means for performing such processes. Reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is a block diagram of one example of a floating point arithmetic unit; Fig. 2 is a schematic block diagram of a part of a floating point arithmetic unit embodying the present invention; Fig. 3 is a more detailed block diagram of a floating point arithmetic unit embodying the present invention; and Fig. 4 is a block diagram of a modified form of the floating point arithmetic unit of Fig. 3. The floating point operation unit of Fig. 1 receives binary input operands D 1 and D 2 , in floating point form, and comprises an exponent operation circuit, a sign operation circuit, and a mantissa operation circuit. The exponent operation circuit comprises adders 20 and 21, incrementers 22 and 23, and a multiplexer 24; the sign operation circuit comprises an exclusive OR circuit 30; and the mantissa operation circuit comprises a fixed point operation circuit (or multiplication circuit) 10, right shifters 13 and 16, a rounding off controller 14, and an incrementer 15. Assuming that exponents of the inputs are Ea and Eb, the operation (Ea + Eb) is executed in the first adder 20 and the result is added in the second adder 21 to a negative bias (-BS) to give (Ea + Eb - BS). Then, in the incrementer 22 an increment by one operation (+1) is executed (in dependence upon a signal F 1 ) when a correction of an overflow is necessary for normalization, and in the incrementer 23 an increment by one operation (+1) is executed so that any overflow arising from a rounding off process (described below) and indicated by an overflow signal F 2 can be corrected by selecting in the multiplexer 24 the incremented output of the incrementer 23. In the sign operation circuit, an exclusive OR operation is carried out, using the exclusive OR circuit 30, for the signs Sa and Sb of the input operands D 1 and D 2 . In the mantissa operation circuit, the respective mantissa portions of the operands D 1 and D 2 , namely (1.Fa) and (1.Fb), are multiplied together by the fixed point multiplication circuit 10, and if a carry signal F 1 is output from the circuit 10, normalization of the resulting product is carried out by a one bit right shift effected in the right shifter 13. The carry signal F 1 is supplied simultaneously to the incrementer 22 so that "1" is added to the exponent as mentioned above. The rounding off of the normalized result is controlled by the rounding off controller 14, and the rounding off process is performed in the incrementer 15 by adding "+1" to the LSB (least significant bit) when necessary. When an overflow arises in the incrementer 15, the carry signal F 2 is output and the right shifter 16 shifts the output of the incrementer 15 by one bit to the right, and thus the normalized mantissa is obtained. The floating point operation unit of Fig. 2 comprises a multiplying circuit 1 for multiplying mantissa portions by each other (which mantissa portions form respective parts of the two binary input operands applied to the unit), and for normalizing the output; a bit inversion circuit 2 for inverting the output data from the multiplying circuit; a selection circuit 3 for selecting either the output of the bit inversion circuit or the output of the multiplying circuit in response to a 'division' or 'square root' control signal which becomes active during one of the operations in the division or square root process concerned; and an increment circuit 4 for selectively executing a rounding off process on the output of the multiplying circuit in response to a predetermined rounding off control signal when the multiplying circuit output is selected in the selection circuit, and for selectively adding "1" to the LSB of the output of the inversion circuit in response to the above-mentioned division or square root control signal when the output of the bit inversion circuit is selected in the selection circuit, and for normalizing the above-obtained respective output values. The division operation processes are as follows. When the floating point division operation A/B is carried out using the above-described iterative method, in each iterative cycle the necessary operation (2 - BX i ) is first executed using the multiplying circuit, the bit inversion circuit, and the incrementer. Here, X 0 is an initial value of the reciprocal of the divisor B, and X i is an ith approximation value of the reciprocal, and X i is such that 0 <BX i ≦ 1, (i = 0, 1,...). Then, the multiplication operation X i+1 = X i (2 - BX i ), which gives an approximation value of the reciprocal of the divisor B, is executed by the multiplying circuit, and the iterative cycle comprising these respective calculations is repeated a predetermined number of times, whereafter the desired result A/B is determined by multiplying together the resulting final reciprocal value X i+1 and the dividend A. A square root operation is based on the equivalence C = N = (N/ N ) . If the binary number N is expressed in normalized floating point form according to the IEEE standard, the mantissa part of this number is a number B such that 1 ≦ B < 2. The approximate value X i+1 of 1/√B may be obtained by iteration using the formula: X i+1 = (1/2)*X i (3 - BX i 2 ); where 0 < X 0 ≦ 3/B , B > 0, and X 0 is an initial value. If the initial value X 0 read from a look up table (ROM) satisfies the inequality 0 < X 0 ≦ 1/B , it follows that 0 < Y 0 X 0 ≦ 1, where Y 0 = BX 0 and therefore, 2 ≦ (3 - Y 0 X 0 ) < 3, 1 ≦ (1/2)*(3 - Y 0 X 0 ) < 3/2, and (1/2)*(3 - Y 0 X 0 ) is a normalized number. Accordingly, (1/2)*(3 - Y i X i ) will generally be a normalized number. The calculation of (1/2)*(3 - Y i X i ) is effected on the following basis. Since 0 < Y i X i ≦ 1, if Y i X i is the inverted value of the bits to the right of the binary point of Y i X i , (3 - Y i X i )d = (10. Y i X i + LSB(1))b, where LSB(1) denotes an addition of "1" to the LSB, ( )d indicates that the bracketed expression is in decimal notation, and ( )b indicates that the bracketed expression is in binary notation. The thus obtained binary number constituting (10. Y i X i + LSB(1))b is then shifted to the right by one bit, to give (1/2)*(3 - Y i X i ), this being a necessary step in the Newton-Raphson method square root operation, assuming that 0 < Y i X i ≦ 1. By using the above binary manipulations, the calculation of X i+1 , which is repeated five times during the iterative process, is reduced to the steps shown below:- MLT: B*X i (hereinafter B*X i = Y i ) Manipulations (above): (1/2)*(3 - Y i *X i ) MLT: X i *(1/2)*(3 - Y i *X i ) Thus, the calculation of X i+1 may be executed by just two arithmetic operations in addition to the above-described binary manipulations. Figure 3 shows a block diagram of a floating point arithmetic unit, having two inputs for receiving normalized operands conforming to the relevant IEEE standard. The unit comprises an exponent operation circuit, a sign operation circuit, and a mantissa operation circuit. The exponent operation circuit comprises adders 20 and 21, incrementers 22 and 23, and a multiplexer 24; the sign operation circuit comprises an exclusive OR circuit 30; and the mantissa operation circuit comprises a fixed point multiplier 10, a one bit shifter 13 as a first right shift means, a rounding off controller 14, a 53 bit incrementer 15, a one bit shifter 16 as a second right shifter, a bit inverter 41 as an inversion means, a multiplexer (MUXF) 42, and OR circuits 45, 46 and 47. The inverter 41 is located between the shifter 13 and the incrementer 15 in the mantissa operation circuit and performs an inversion operation on the output from the shifter, and the multiplexer 42 selects either the output of the inverter 41 or the output of the shifter in response to a control signal specifying either a division or square root process. In the case of a division process, a division control signal DIV is at a high (H) level when the operation (2-BX i ) is executed and the output of the inverter 41 is selected, and in the case of a square root process, a square root control signal SQRT is at H level when the operation (1/2)*(3-Y i *X i ) is executed and the output of the inverter 41 is selected in the multiplexer 42. In the case of a simple multiplication process to form the product of the two applied operands, the control signals DIV and SQRT are both at a low (L) level and the output of the shifter 13 is selected. It is assumed that the two inputs of the unit receive binary data D 1 and D 2 expressed in floating point form as follows: D 1 = (-1) Sa 2 Ea-BS D 2 = (-1) Sb 2 Eb-BS First, in the mantissa operation circuit, the fixed point multiplier multiplies the respective mantissa portions (1.Fa) and (1.Fb) of the operands D 1 and D 2 together. The fixed point multiplier comprises a partial products generation and addition circuit 11 and an adder 12. The shifter 13 shifts the output of the adder 12 by one bit to the right (to the LSB side), and selectively outputs either the shifted data or the unshifted output data from the adder 12 in response to an overflow signal F 1 generated by the adder 12. In this embodiment, when the signal F 1 is output, the shifted data is selected. The rounding off controller 14 operates during the above-mentioned simple multiplication process. The rounding off controller 14 receives the sign data and a predetermined round mode signal, rejects the figures below the LSB (rounding off process), determines where or not "1" should be added to the LSB, and outputs a rounding off control signal to initiate such addition. The incrementer 15, in the case of the above-mentioned simple multiplication operation, adds "1" to the LSB of the output data of the multiplexer 42 (i.e. output of shifter 13) in response to the rounding off control signal from the rounding off controller 14. The incrementer 15, in the case of the appropriate multiplication/subtraction operation during each cycle of the iterative process in either the division or square root operation, adds "1" to the LSB of the output data of the multiplexer 42 (i.e. output of inverter 41) in response to the control signal DIV or SQRT. In this case, if the added result data is not normalized, the overflow signal F 2 is output. The shifter 16, as in the shifter 13, shifts the output data of the incrementer 15 by one bit to the right (to the LSB side) when either the overflow signal F 2 or the signal SQRT is active, but otherwise outputs the data from the incrementer 15 unshifted. The output data from the shifter 16 constitutes the result D 3 of the operation performed on the input operands D 1 and D 2 . In the exponent operation circuit, the adder 20 adds the data Ea and Eb, which are the exponent portions corresponding to the exponents of the data D 1 and D 2 , and the adder 21 adds the intermediate exponent sum (Ea + Eb),, which is an output of the adder 20, to a predetermined negative bias (-BS). In dependence upon the overflow signal F 1 , the incrementer 22 adds "1" to the resulting exponent (Ea + Eb - BS) supplied from the adder 21; the incrementer 23 always adds "1" to the output data of the incrementer 22 to enable correction of any overflow arising from the rounding off process; and the multiplexer 24 effects such correction by selecting either the output of the incrementer 22 or the output of the incrementer 23 in response to overflow signal F 2 . The multiplexer 24 selects the output of the incrementer 23 when the signal F 2 is output, and selects the output of the incrementer 22 when the signal F 2 is not output. The selected data provides the exponent portion of the result D 3 . In the sign operation circuit, the exclusive OR circuit 30 receives sign data Sa and Sb corresponding to the input data D 1 and D 2 and outputs the sign data. The sign data becomes "0" (positive) when the respective signs of the input data D 1 and D 2 are the same, and becomes "1" (negative) when the signs are different. The sign data is supplied to the rounding off controller 14 and is also output to give the sign of the result D 3 . A division process performed by the unit of Figure 3 in accordance with the IEEE standard is explained in detail below. The division is C = A/B = A(1/B), and the operands A and B, and the result C are provided in normalized form. Firstly, an (i + 1)th approximation is obtained of the reciprocal function 1/B using the iterative process based on the formula X i+1 = X i (2 - BX i ); where 0 < X 0 < 2/B when B > 0, and 0 > X 0 > 2/B when B < 0. The initial value X 0 is found, such that 0 < X 0 ≦ 1/B, using a look up table (not shown). It follows that 0 < BX 0 ≦ 1, and therefore that 1 ≦ 2 - BX 0 < 2. Here (2 - BX 0 ) is a normalized number, and thus, generally, (2 - BX i ) is a normalized number. Each iterative cycle comprises two steps. In a first step the operation (2 - BX i ), where 0 < BX i ≦ 1, is executed as follows. Where BX i is the inverted value of BX i , 2 - BX i = BX i + LSB(1). As before, LSB(1) denotes the addition "+1" to LSB. First the exponent operation circuit and the sign operation circuit are disabled, then the appropriate data of the divisor B and the initial value X 0 of the reciprocal of the divisor are supplied to the multiplier 10 as respective input data D 1 and D 2 , and the control signal DIV is set to H level. The output BX 0 of the multiplier 10 is supplied through shifter 13 to the inverter 41, which inverts each bit as required to form BX 0 , which result is selected by the multiplexer 42 and supplied to the incrementer 15. The incrementer 15 adds "1" to the LSB of the input data ( BX 0 ) in response to the H level signal DIV and the added data ( BX 0 + LSB(1)), i.e. (2 - BX 0 ), is normalized through the shifter 16 and output as normalized data D 3 (step 1). In a second step the output data (2-BX 0 ), from the first step, and the initial value X 0 are used to provide the multiplier 10 with input data D 1 and D 2 , and the control signal DIV is made L level, and the output of the multiplier 10, X 0 (2 - BX 0 ), is supplied to the incrementer 15 through the shifter 13, having been selected by the multiplexer 42. The incrementer 15 executes the rounding off process, if required, in accordance with the appropriate control signal from the rounding off controller 14. Similarly, the output data of the incrementer 15 is normalized through the shifter 16, and output as data D 3 representing X 1 (step 2). Thereafter, the above steps 1 and 2 are repeated three or four times, as successive cycles of the iterative process, and thus the obtained data X i+1 , i.e. an (i+1)th approximation for the value of 1/B, is supplied to the multiplier 10 with the dividend data A, as input data D 1 and D 2 . At this time, the signal DIV is made L level and the exponent operation circuit and the sign operation circuit are enabled, so that the result of the floating point division A/B is output as data D 3 . As mentioned above, provided that 0 < BX i ≦ 1, the operation (2-BX i ) which is necessary in the Newton-Raphson division method can be carried out in one step, simply by adding "1" to the LSB of BX i , which is an inverted form of BX i . Accordingly, each cycle in the iterative process, based on X i+1 = X i (2-BX i ), used to calculate the reciprocal of the divisor (1/B) requires just two steps, one step being the operation (2-BX i ) and the other step the operation X i (2-BX i ), whereby the separate subtraction operation that would be required to accomplish the said one step in the unit of Fig. 1, for example, is avoided. Three to four iterations are typically carried out, so the total operation time for the floating point division is considerably shorted, as compared with the unit of Fig. 1. The operation of (1/2)*(3-Y i *X i ), which is used in the square root process, is carried out as follows. Since the output Y i X i from the multiplier 10 is such that 0 < Y i X i ≦ 1, the fixed-point-form data output from the shifter 13 is 1.0000... or 0.xxxx.... On passing through the inverter 41, the data 1.0000... becomes 1.1111.... and 0.xxxx... becomes 0. xxxx ...., where x denotes the inverted value of x. When the operation (1/2)*(3-Y i *X i ) in the square root process is executed, the activated control signal SQRT selects the output of the inverter 41 through the multiplexer 42. If the signal SQRT is not supplied, the output of the shifter 13 is supplied to the incrementer 15; when the signal SQRT is supplied, "1" is added to the content of the incrementer 15 at the LSB thereof. The output of the incrementer 15 is passed through the shifter 16 to provide the mantissa output. The bit to the left of the binary point is set to 1 in the shifter 16. The rounding off process (if selected) is the same as in the division operation. In the incrementer 15, when the carry signal F 2 is "1", the signal F 2 is supplied to the multiplexer (MUXE) 24 in the exponent operation circuit, so that the output from the incrementer 23 is selected instead of the output from the incrementer 22, and the output of the incrementer 15 is shifted by one bit to the right in the shifter 16. When the signal SQRT is supplied, the output of the incrementer 15 is also shifted. Accordingly, at the output of the incrementer 15, the result of the operation (3-Y i *X i ) is provided and this result is divided by two in the shifter 16. Thus, provided that 0 < Y i X i ≦ 1, the operation (1/2)*(3-Y i X i ) can be executed in one step by the unit of Fig. 3, so that separate subtraction and divide-by-two operations are not required. Figure 4 is a block diagram of a further floating point arithmetic unit, including a modified mantissa operation circuit. The exponent operation circuit and the sign operation circuit are the same as those of the unit of Figure 3. The unit of Fig. 4 is optimised to execute a square root operation based on an iterative process, each cycle of which comprises the steps B*X i = Y i , (1/2)*(3-Y i *X i ), and X i *(1/2)*(3-Y i *X i ). The modified mantissa operation circuit comprises an inverter 43 instead of inverter 41, and the application of the control signal SQRT is different from that in the unit of Fig. 3. The remaining parts are similar to the corresponding portions in the unit of Fig. 3. The output of the shifter 13 is supplied to the inverter 43 and the multiplexer 42. In the inverter 43, the input data to the right of the binary point are inverted. When the input data to the left of the binary point is 0 the bits to the left of the binary point are set to "10"; thus the data "10. xxxx ..." is output. When the input data is 1.0000...., the bits to the left of the binary point are set to "01"; thus the data "01.1111...." is output. The step (1/2)*(3-Y i *X i ) is performed as follows. Since the output YiXi of the multiplier 10 satisfies the inequality 0 < Y i X i ≦ 1, the multiplier overflow bit V is "0", so that the fixed-point-form data output from the shifter 13 is 1.0000... or 0.xxxx.... The data 1.0000... is modified to 01.1111... and the data 0.xxxx... is modified to 10. xxxx ... by the inverter 43, where x is the inverted value of the bit x. The multiplexer 42 selects the output of the inverter in response to the control signal SQRT given during this step of the square root operation, namely the step (1/2)*(3-Y i *X i ). If the signal SQRT is not supplied, the output of the shifter 13 is supplied to the incrementer 15. If the signal SQRT is given, a further "1" is added to the LSB in the incrementer 15. The output of the incrementer 15 is passed through another shifter 16 so as to output the required mantissa portion. When the rounding off mode is selected, the rounding off controller receives the sign data and the data (G,R) from the shifter 13 and outputs the round control signal. When the rounding off control signal is given, the incrementer 15 operates in the same way as when the signal SQRT is given. An explanation of the data (G, R) is omitted, since it does not relate specifically to the invention. When the carry of the incrementer 15 is output and the signal SQRT is not given, the multiplexer 24 selects the output of the incrementer 23. The carry of the incrementer 15 shifts the data in the shifter 16 by one bit to the right. In the square root operation, since the overflow bit (i.e. the bit corresponding to 2 1 ) is "1" (the output of the incrementer 15 being in the form 10.xxxx...), the shifter 16 always shifts the data, and therefore the signal SQRT need not be supplied to the shifter 16 as in the unit of Fig. 3. As mentioned above, at the output of the incrementer 15 the result of the operation (3-Y i *X i ) is obtained, and this output is multiplied by 1/2 by a one bit right shift in the shifter 16, so that the complete operation (1/2)*(3-Y i X i ) is executed in just one step, provided that 0 < Y i X i ≦ 1.

Claims: A floating point arithmetic unit, for executing an iterative binary arithmetic operation upon two operands (D 1 , D 2 ) applied to the unit in floating point form, which unit includes respective operating portions for deriving mantissa, exponent and sign components of the desired result (D 3 ) respectively, the mantissa operating portion including fixed point multiplication means (10) for multiplying together the respective mantissa components of the two operands concerned; characterised in that the mantissa operating portion further includes subtraction means (41, 42, 15; 43, 42, 15) operative, in each cycle of the iterative operation, to form the inverse (BX i ; Y i X i ) of the fractional part of a binary number (BX i ; Y i X i ) derived from the output of the said multiplication means (10), which derived binary number (BX i ; Y i X i ) is greater than 0 and less than or equal to 1, and to increment that inverse by adding one to the least significant bit thereof, thereby to produce a binary output value representative of the difference (2-BX i ; 3-Y i X i ) between a first predetermined positive integer (2;3) and the said derived binary number (BX i ; Y i X i ) without adding that integer to the derived binary number, the said first predetermined positive integer being 2 or 3. A floating point arithmetic unit as claimed in claim 1, wherein the said iterative binary arithmetic operation is a division operation in which, in each said cycle, the calculation X i+1 = X i (2-BX i ) is performed, where i is the cycle number, B is the divisor, and X i and X i+1 are the current and next approximations respectively of the reciprocal of B, and the said subtraction means are activated when, during a predetermined step (2-BX i ) of each said cycle, the multiplication means form the product BX i of the divisor B and the said current approximation X i of the reciprocal of B, to perform such inverse formation and increment operations on the said derived binary number, thereby to produce the said binary output value representative of 2-BX i . A floating point arithmetic unit as claimed in claim 1, wherein the said iterative binary arithmetic operation is a square root operation in which, in each said cycle, the calculation X i+1 = ½ X i (3-BX i 2 ) is performed, where i is the cycle number, B is the number whose square root is to be found, and X i and X i+1 are the current and next approximations respectively of the square root of B, and the subtraction means are activated when, during a predetermined step (3-Y i X i ) of each said cycle, the multiplication means (10) form the product Y i X i of the said current approximation X i and an intermediate product Y i of B and X i produced during a preceding step of the cycle concerned, to perform such inverse formation and increment operations on the said derived binary number, thereby to produce the said binary output value representative of 3-Y i X i . A floating point arithmetic unit as claimed in claim 1, wherein the said subtraction means are also operable selectively to produce, by such inverse formation and increment operations performed on the said derived binary number (Y i X i ), a binary output value representative of the difference (3-Y i X i ) between a second predetermined positive integer (3), different from the said first predetermined positive integer (2), and the said derived binary number (Y i X i ), one of the said first and second predetermined positive integers being 2 and the other being 3. A floating point arithmetic unit as claimed in claim 4, operable selectively to carry out respective first and second different such iterative binary arithmetic operations, wherein the operation of the said subtraction means is modified, according to which of the two iterative binary arithmetic binary operations is being performed by the unit, such that the binary output value produced by the subtraction means when the unit is performing the said first iterative binary arithmetic operation is representative of the difference (2-BX i ) between the said first predetermined positive integer (2) and the said derived binary number (BX i ), and is representative of the difference (3-Y i X i ) between the said second predetermined positive integer (3) and the said derived binary number (Y i X i ) when the unit is performing the said second iterative binary arithmetic operation. A floating point arithmetic unit as claimed in claim 5, wherein: the said first iterative binary arithmetic operation is a division operation in which, in each said cycle, the calculation X i+1 = X i (2-BX i ) is performed, where i is the cycle number, B is the divisor, and X i and X i+1 are the current and next approximations respectively of the reciprocal of B, and the said subtraction means are activated when, during a predetermined step (2-BX i ) of each said cycle of the said division operation, the multiplication means form the product BX i of the divisor B and the said current approximation X i of the reciprocal of B, to perform such inverse formation and increment operations on the said derived binary number, thereby to produce the said binary output value representative of 2-BX i ; and the said second iterative binary arithmetic operation is a square root operation in which, in each said cycle, the calculation X i+1 = ½ X i (3-BX i 2 ) is performed, where i is the cycle number, B is the number whose square root is to be found, and X i and X i+1 are the current and next approximations respectively of the square root of B, and the subtraction means are activated when, during a predetermined step (3-Y i X i ) in each said cycle of the said square root operation, the multiplication means (10) form the product Y i X i of the said current approximation X i and an intermediate product Y i of B and X i produced during a preceding step of the cycle concerned, to perform such inverse formation and increment operations on the said derived binary number, thereby to produce the said binary output value representative of 3-Y i X i . A floating point arithmetic unit as claimed in claim 6, wherein the mantissa operating portion further includes: a first right shift means (13) connected to an output of the fixed point multiplication means (10) and operable to deliver at a data output thereof the said derived binary number, representing the product BX i or Y i X i as the case may be, in the form 1.0000.... or 0.xxxx....; incrementer means (15) having a data input for receiving a binary input value, and operable in response to an increment signal to increment the received binary input value by one; inversion means (41) connected to the said data output of the said first right shift means (13) for forming the said inverse of the fractional part of the said derived binary number, the inversion means being operable selectively to apply that inverse to the said data input of the incrementer means (15) when the said predetermined step (2-BX i ; 3-Y i X i ) of the said division or square root operation is being performed by the unit, the said increment signal also being applied to the said incrementer means during that step (2-BX i ; 3-Y i X i ) so that the incrementer means add one to the said inverse, and being operable, at other times during the said cycle, to connect the said data output of the first right shift means to the said data input of the said incrementer means (15); rounding off control means (14) connected to the said data output of the first right shift means (13) and operable to produce a round-off control signal for use by the said incrementer means (15); and second right shift means (16) connected for receiving an output value of the said incrementer means (15) and also connected for receiving a carry signal produced by the said incrementer means, and operable in response to that carry signal, and during the said predetermined step (3-Y i X i ) of the square root operation, to shift the received output value to the right. A floating point arithmetic unit as claimed in claim 7, wherein the said fixed point multiplication means (10) comprise: a partial product multiplier and addition circuit; and an adder; a carry signal produced by the adder being applied to the said first right shift means (13) for causing the binary value produced at the said output of the fixed point multiplication means (10) to be shifted by one bit to the right. A floating point arithmetic unit as claimed in claim 7 or 8, wherein the said inversion means (41, 42, 45) comprise: an inverter (41); and a multiplexer (42) connected between the said inverter (41) and the said incrementer means (15) and also connected for receiving a control signal (DIV, SQRT) which is activated when, in each said cycle of the said division and square root operations, the said predetermined step (2-BX i ; 3-Y i X i ) is performed; the multiplexer (42) being operable to select the binary value at the said output of the said first right shift means (13) when the said control signal (DIV, SQRT) is inactive, and to select the said inverse produced by the said inverter (41) when the control signal (DIV, SQRT) is active. A floating point arithmetic unit as claimed in claim 3, wherein the mantissa operating portion further includes: a first right shift means (13) connected to an output of the fixed point multiplication means (10) and operable to deliver at a data output thereof the said derived binary number, representing the product Y i X i , in the form 1.0000.... or 0.xxxx....; incrementer means (15) having a data input for receiving a binary input value, and operable in response to an increment signal to increment the received binary input value by one; inversion means (42, 43) connected to the said data output of the said first right shift means (13) for forming the said inverse by inverting each bit to the right of the binary point of the said derived binary number and by presetting the bits to the left of the binary point to "10" when the said derived binary number is 0.xxxx.... and to "01" when the said derived binary number is 1.0000...., the inversion means being operable selectively to apply that inverse to the said data input of the incrementer means (15) when the said predetermined step (3-Y i X i ) of the said square root operation is being performed by the unit, the said increment signal also being applied to the said incrementer means during that step (3-Y i X i ) so that the incrementer means add one to the said inverse, and being operable, at other times during the said cycle, to connect the said data output of the first right shift means (13) to the said data input of the said incrementer means (15); rounding off control means (14) connected to the said data output of the first right shift means (13) and operable to produce a round-off control signal for use by the said incrementer means (15); and second right shift means (16) connected for receiving an output value of the said incrementer means (15) and also connected for receiving a carry signal produced by the said incrementer means, and operable in response to that carry signal, and during the said predetermined step (3-Y i X i ) of the square root operation, to shift the received output value to the right.

Inventors: KATSUNO AKIRA, KATSUNO, AKIRA
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: G06F7
IPC codes: G06F7