Liquid crystal display panel with reduced pixel defects

Abstract: A liquid crystal display panel has a glass substrate (51), a plurality of rows of gate electrodes (52) provided on the glass substrate, a plurality of columns of drain electrodes (56), a plurality of pixel electrodes (60) corresponding to each of the intersections of a matrix formed by the gate electrodes and the drain electrodes, and first and second insulating films (53,58) between the gate electrodes, the drain electrodes, and the pixel electrodes in order to isolate them from each other. The pixel electrodes (60) communicate with the source electrodes (57) through openings (59) in the second insulating films (58).

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly to a liquid crystal display panel with reduced pixel defects. Description of the Related Art In recent years, research and development has been pursued actively on liquid crystal displays which make it possible to reduce the thickness of the display panel. In particular, the active matrix addressing method using thin film transistors has been the object of research in view of its potential as a method which is capable of preventing the occurrence of the contrast deterioration problem in liquid crystal displays and enables the creation of a display with a large number of scanning lines (namely, a large capacity). In applying thin film transistors to a liquid crystal display, it becomes necessary to form a thin film transistor array with satisfactory yield at low cost. In so doing, it is desirable to give the simplest possible structure to the thin film transistor. As the thin film semiconductor material for the thin film transistor, use is usually made of amorphous silicon, polycrystalline silicon, cadmium sulfide or the like. In FIG. 1 is shown a sectional view of a thin film display as disclosed in Applied Physics, Vol. 24, pp. 357-362, 1981 for the case of using amorphous silicon as the thin film semiconductor material. In this structure, both a gate electrode 21 and a pixel electrode 23 are formed into an island pattern on the same glass substrate 20. This thin film transistor (TFT) element has a gate insulating film 30 formed so as to cover both the gate electrode 21 and the pixel electrode 23, an islandlike semiconductor film 25, a source electrode 29 electrically connected to the pixel electrode 23, and a drain electrode 28 which serves as a signal line. Further, another structure used for the liquid crystal display which is disclosed in Society of Information Display (SID), p. 310, 1988 is shown in FIG. 2. The present transistor is constituted of a first and a second insulating films 22 and 24 formed so as to cover a gate electrode 21 provided on a glass substrate 20, a semiconductor film 25 formed into an island pattern on the second insulating film 24, and source and drain electrodes 29 and 28 that are electrically connected respectively to source and drain regions 27 formed on the semiconductor film 25. A pixel electrode 23 is formed on the second insulating film 24 to be connected with the source electrode 29. Reference numeral 26 is a protective film. In the transistor structures shown above, the structure shown in FIG. 1, for example, is designed so as to avoid bringing the gate electrode 21 and the pixel electrode 23 into electrical contact on the glass substrate 20. Further, the structure shown in FIG. 2 is designed so as to avoid the electrical contact between the drain electrode 28 and the pixel electrode 23 in the same plane, as is indicated in the explanatory diagram shown in FIG. 3. However, in the manufacturing process of the transistor array, electrical contact tends to be formed between the gate electrode 21 and the pixel electrode 23 or between the drain electrode 28 and the pixel electrode 23, because of dust that strays into the device during the photoresist process or the like. When such a contact takes place, it is represented as a point defect in the picture display, which becomes a cause for the deterioration in the yield. SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a liquid crystal display panel which is capable of reducing the defects in the picture display and producing a high yield with a simple construction. The liquid crystal display panel according to the present invention comprises a substrate; a plurality of gate electrodes provided on said substrate forming rows; a plurality of electrodes, being one of either source or drain electrodes, provided above said substrate forming columns; and, a pixel display unit provided at each intersection of said rows and columns, each pixel display unit comprising; one of the gate electrodes provided on the substrate; an insulating film provided above the gate electrode; a semiconductor layer provided on the insulating film directly above the gate electrode, the semiconductor layer having source and drain regions and being insulated from the gate electrode by the insulating film; one of the electrodes, being a source or a drain electrode, provided on the insulating film and connected appropriately to the source or drain region of the semiconductor layer; and a pixel electrode laterally spaced from an area of overlap between the gate electrode and the semiconductor layer and insulated from the semiconductor layer by the insulating film except for a connection between the pixel electrode and the source or drain region, as appropriate, via a hole defined in the insulating film; characterised by; a further insulating film provided over the gate electrode and insulating the pixel electrode from the gate electrode. The first electrode that is connected to one of the source and drain regions, the gate electrode, and the pixel electrode are mutually insulated by means of the two insulating layers or films. Therefore, even when the gate electrode or the first electrode protrudes over the pixel electrode due to dust or the like, which entered into the device during the photoresist process, it will not lead to a picture defect because these electrodes are isolated by the insulating layers or films. In addition, the structure of the device according to the present invention is such that the increase in the number of fabrication steps over that of the conventional structure is only slight. Therefore, it becomes possible to obtain a thin film transistor array with low cost and high yield. BRIEF DESCRIPTION OF THE DRAWINGS The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein: FIGS. 1 and 2 are sectional views of thin film transistors of the prior art; FIG. 3 is a plan view for explaining the liquid crystal display panels of the prior art and the present invention; FIG. 4 is a sectional view for explaining an embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 3 again, a plurality of rows of gate electrodes 21 and a plurality of columns of drain electrodes 29 are formed. A plurality of pixel electrodes 23 are formed corresponding to each intersection of a matrix formed by the gate electrodes 21 and the drain electrodes 29. Referring to FIG. 4, first, chromium is deposited to a thickness of 100 nm on a glass substrate 10, and a gate electrode 11 is formed by patterning the film into island form. Subsequently, after forming a 150 nm thick SiO x film as a first insulating film 12, indium tin oxide is formed to a thickness of 100 nm which is patterned into island form to create a pixel electrode 13. Then, 300 nm of SiN x as a second insulating film 14, 100 nm of amorphous silicon as a semiconductor layer 15, and 100 nm of SiN x as a protective film 16 are formed sequentially by a plasma CVD method at a temperature of about 250°C. Further, after patterning the protective film 16 into island form, an n⁺-type amorphous silicon layer doped with an impurity such as phosphorus which serves as a source and drain region 17 is formed to a thickness of 40 nm, and the layer is patterned to avoid electrical contact between the source region and the drain region. Then, after patterning the amorphous silicon layer into island form, a contact hole is opened at a part in the second insulating film 14 over the pixel electrode 13. The contact hole is created by a dry etching using CF₄. Thereafter, chromium is formed to a thickness of 200 nm as the metal for source and drain electrodes, and patterned so as to establish an electrical contact between the pixel electrode 13 and a source electrode 19 via the contact hole and to ensure the electrical isolation between the source electrode 19 and a drain electrode 18, completing the fabrication of the thin film transistor. Then, an upper glass substrate 40 having a transparent electrode 41 thereon is formed above the glass substrate 10. A liquid crystal 42 is inserted between the pixel electrode 13 and the transparent electrode 41. It should be pointed out that although the first insulating film 12 was formed covering the entire surface in the present embodiment, the film may be formed limited only to the vicinity of the gate electrode as shown in FIG. 2. In that event, the pixel electrode will be formed on the glass substrate. In the thin film transistor of the present embodiment, a structure is employed in which the protective film 16 is formed directly above the channel section that is formed in the amorphous silicon layer 15 directly above the gate electrode 11. However, the present invention also operates effectively in a structure where the protective film 16 is missing. In that case, the fabrication process differs slightly from that of the present embodiment, requiring the etching of the n⁺-type amorphous silicon layer. Moreover, although amorphous silicon is used as the thin film semiconductor in the thin film transistor of the present embodiment, the present invention will also remain effective even when other semiconductors such as polycrystalline silicon and cadmium sulfide are employed. In the present embodiment, the pixel electrode 13, the drain electrode 18 and the gate electrode 11 are isolated from one another by the insulating films 12 and 14, so that the number of pixel defects due to short-circuiting between these electrodes are reduced, yet the structure is simple. The number of occurrences of point defects was evaluated by actually forming a liquid crystal display having a thin film transistor array of the present embodiment and carrying out a picture display. The result of the evaluation showed that in contrast to an average number of defect occurrences of 5 per 100 cm² in the prior structure, it was improved to an average value of 0.2 in the liquid crystal display using the transistor array of the present structure, confirming that the effect of the present invention is conspicuous. It should be noted that although the description has been given above is based on the connection formed between the pixel electrode and the source electrode as an example, similar effect can be realized for the case of connecting the pixel electrode and the drain electrode. It should also be noted that materials other than those specified above may be employed in fabricating the components of the liquid crystal display. As examples, polyimide, as well as silicon nitride or silicon oxide, may be used for forming insulating films, and the semiconductor layer may be made of i-a-Si with ohmic contact layers of n⁺-a-Si. Other conventional materials may, of course, also be used.

Claims: A liquid crystal display panel comprising: a substrate; a plurality of gate electrodes (11) provided on said substrate (20) forming rows; a plurality of electrodes (18), being one of either source or drain electrodes, provided above said substrate forming columns; and, a pixel display unit provided at each intersection of said rows and columns, each pixel display unit comprising; one of the gate electrodes (11) provided on the substrate; an insulating film (14) provided above the gate electrode; a semiconductor layer (15) provided on the insulating film directly above the gate electrode, the semiconductor layer having source and drain regions (17) and being insulated from the gate electrode by the insulating film; one of the electrodes (18), being a source or a drain electrode, provided on the insulating film and connected appropriately to the source or drain region of the semiconductor layer; and a pixel electrode (13) laterally spaced from an area of overlap between the gate electrode and the semiconductor layer and insulated from the semiconductor layer by the insulating film except for a connection between the pixel electrode and the source or drain region, as appropriate, via a hole defined in the insulating film; characterised by; a further insulating film (12) provided over the gate electrode and insulating the pixel electrode from the gate electrode. A liquid crystal display panel according to claim 1, in which at least a portion of said pixel electrode is provided on a portion of said further insulating film. A liquid crystal display panel according to claim 1, in which said pixel electrode is provided on said substrate. A liquid crystal display panel according to any preceding claim, in which said further insulating film is of silicon nitride or silicon oxide. A liquid crystal display panel according to any of claims 1 to 3, in which said insulating film is of silicon nitride or polyimide. A liquid crystal display panel according to any preceding claim, in which said semiconductor layer is of amorphous silicon. A liquid crystal display panel according to any of claims 1 to 3, in which said substrate is a glass substrate, said insulating film is a silicon nitride, said further insulating film is a silicon oxide, and said semiconductor layer is an amorphous silicon layer.

Inventors: KANEKO SETSUO, SUKEGAWA OSAMU, KANEKO, SETSUO, SUKEGAWA, OSAMU
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: G02F1
IPC codes: G02F1