Brushless motor driver

Abstract: In the brushless motor driver according to the invention, saturation voltage generating means (22) are provided for generating a saturation voltage corresponding to a torque command, while current correcting means (25) are provided for comparing the saturation voltage with operating voltages of driving transistors (Q21, Q25, Q29; Q22, Q26, Q30) to correct the amount of current in transistor drive control signals so that the operating voltages drop below the saturation voltage. Thus, it is possible to drive a brushless motor with a high efficiency and a low noise while preventing saturation of the driving transistors with respect to any torque command.

Description: The present invention relates to a brushless motor driver applicable to an acoustic apparatus and an image apparatus and the like. Fig. 4 is a circuit diagram showing a conventional brushless motor driver. As shown in Fig. 4, a brushless motor 1 has three phase driving coils 2a, 2b and 2c and a rotor (not shown), and driving transistors Q21, Q22, Q25, Q26, Q29 and Q30 are provided for controlling current supply to the driving coils 2a, 2b and 2c. The driving transistors Q21, Q25 and Q29 arranged at an upper side are NPN transistors respectively, whose collectors are connected with a positive feed terminal 3 of a power source V CC . On the other hand, the driving transistors Q22, Q26 and Q30 arranged at a lower side are NPN transistors respectively, whose emitters are connected to an inverting input terminal of a control amplifier A1 and to ground (negative feed terminal) through a resistance R11. An emitter of the driving transistor Q21 is connected with a collector of the driving transistor Q22, and the node between the both transistors Q21 and Q22 is connected with the driving coil 2a. An emitter of the driving transistor Q25 is connected with a collector of the driving transistor Q26, and the node between the both transistors Q25 and Q26 is connected with the driving coil 2b. An emitter of the driving transistor Q29 is connected with a collector of the driving transistor Q30, and the node between the both transistors Q29 and Q30 is connected with the driving coil 2c. Terminals 4 to 9 are provided for inputting sensor signals H U ⁺, H U ⁻, H V ⁺, H V ⁻, H W ⁺ and H W ⁻ as shown in Fig. 5 respectively, the sensor signals H U ⁺, H U ⁻, H V ⁺, H V ⁻, H W ⁺ and H W ⁻ being produced by well known technique on the basis of rotating angle of the rotor. The sensor signals H U ⁺, H V ⁺, H W ⁺ are 120 degrees out of phase to each other, while the sensor signals H U ⁻, H V ⁻ and H W ⁻ are 180 degrees out of phase with the sensor signals H U ⁺, H V ⁺ and H W ⁺ respectively. The terminals 4 and 5 are respectively connected with bases of NPN transistors Q1 and Q2 forming a differential transistor pair, and emitters of the transistors Q1 and Q2 are coupled and connected with ground through a constant current source 10. The terminals 6 and 7 are respectively connected with bases of NPN transistors Q4 and Q5 forming a differential transistor pair, and emitters of the transistors Q4 and Q5 are coupled and connected with ground through a constant current source 11. The terminals 8 and 9 are respectively connected with bases of NPN transistors Q7 and Q8 forming a differential transistor pair, and emitters of the transistors Q7 and Q8 are coupled and connected with ground through a constant current source 12. A collector of the transistor Q1 is connected with a collector and a base of a PNP transistor Q3 and a base of a PNP transistor Q12, and emitters of the transistors Q3 and Q12 are connected with the positive feed terminal 3 respectively. Thus the transistors Q3 and Q12 form a current mirror circuit. A collector of the transistor Q4 is connected with a collector and a base of a PNP transistor Q6 and a base of a PNP transistor Q11, and emitters of the transistors Q6 and Q11 are connected with the positive feed terminal 3 respectively. Thus the transistors Q6 and Q11 form a current mirror circuit. A collector of the transistor Q7 is connected with a collector and a base of a PNP transistor Q9 and a base of a PNP transistor Q10, and emitters of the transistors Q9 and Q10 are connected with the positive feed terminal 3 respectively. Thus the transistors Q9 and Q10 form a current mirror circuit. Collectors of the transistors Q2 and Q9 are connected and collectors of the transistors Q5 and Q3 are connected while collectors of the transistors Q8 and Q6 are connected. A collector of the transistor Q10 is connected with ground through a resistance R1, and a collector of the transistor Q11 is connected with ground through a resistance R2 while a collector of the transistor Q12 is connected with ground through a resistance R3. In the above circuit, a current corresponding to the current obtained by adding a current flowing through transistor Q1 and a current flowing through transistor Q5 flows through the resistance R3 via the transistors Q3 and Q12 forming-the current mirror circuit, and a voltage corresponding to a voltage drop across the resistance R3 can be output from a node N1 as an output voltage for U phase. Similarly, a current corresponding to the one obtained by adding a current flowing through the transistor Q4 and a current flowing through the transistor Q8 flows through the resistance R2 via the transistors Q6 and Q11 forming the current mirror circuit, and a voltage corresponding to a voltage drop across the resistance R2 can be output from a node N2 as an output voltage for V phase. Further, a current corresponding to the one obtained by adding a current flowing through the transistor Q7 and a current flowing through . transistor Q2 flows through the resistance R1 via the transistors Q9 and Q10 forming the current mirror circuit, and a voltage corresponding to a voltage drop across the resistance R1 can be output from a node N3 as an output voltage for W phase. Incidentally, a waveform synthetic circuit 13 consists of the terminals 4 to 9, the transistors Q1 to Q12, the resistances R1 to R3 and the constant current sources 10 to 12. The node N1 of the output voltage for U phase is connected with both bases of a PNP transistor Q13 and an NPN transistor Q14, and the node N2 of the output voltage for V phase is connected with both bases of a PNP transistor Q15 and an NPN transistor Q16, while the node N3 of the output voltage for W phase is connected with both bases of a PNP transistor Q17 and an NPN transistor Q18. Emitters of the transistors Q13, Q15 and Q17 are commonly to the positive feed terminal 3 through a constant current source 14, and collectors of the transistors Q13, Q15 and Q17 are respectively connected with bases of the driving transistors Q22, Q26 and Q30 arranged on the lower side. Resistances R7, R8 and R9 are connected between bases and emitters of the driving transistors Q22, Q26 and Q30 respectively. Thus, operation of the transistors Q13, Q15 and Q17 is controlled on the basis of the output voltage of the nodes N1, N2 and N3 respectively to selectively supply a current of the constant current source 14 to the bases of the driving transistors Q22, Q26 and Q30 and the resistancesR7, R8 and R9, so that the operation of the driving transistors Q22, Q26 and Q30 can be controlled. On the other hand, emitters of the transistors Q14, Q16 and Q18 are commonly connected with ground through a constant current source 15. A collector of the transistor Q14 is connected with a base and a collector of a PNP transistor Q19 and a base of a PNP transistor Q20, and emitters of the transistors Q19 and Q20 are connected with the positive feed terminal 3, respectively. Thus the transistors Q19 and Q20 provide a current mirror circuit. A collector of the transistor Q20 is connected with a base of the driving transistor Q21 while being connected with an emitter of the driving transistor Q21 through a resistance R4. A collector of the transistor Q16 is connected with a base and a collector of a PNP transistor Q23 and a base of a PNP transistor Q24, and emitters of the transistors Q23 and Q24 are connected with the positive feed terminal 3, respectively. Thus the transistors Q23 and Q24 provide a current mirror circuit. A collector of the transistor Q24 is connected with a base of the driving transistor Q25 while being connected with an emitter of the driving transistor Q25 through a resistance R5. A collector of the transistor Q18 is connected with a base and a collector of a PNP transistor Q27 and a base of a PNP transistor Q28, and emitters of the transistors Q27 and Q28 are connected with the positive feed terminal 3. Thus the transistors Q27 and Q28 consist of a current mirror circuit. A collector of the transistor Q28 is connected with a base of the driving transistor Q29 while being connected with an emitter of the driving transistor Q29 through a resistance R6. Thus the transistors Q14, Q16 and Q18 are controlled on the basis of the output voltage of the nodes N1, N2 and N3, respectively, to selectively supply a current absorbed by the constant current source 15 to the transistors Q19, Q23 and Q27, to thereby selectively supply a current corresponding to the current flowing in the transistors Q19, Q23 and Q27 to the bases of the driving transistors Q21, Q25 and Q29 and the resistancesR4, R5 and R6 through the transistors Q20, Q24 and Q28, so that the driving transistors Q21, Q25 and Q29 can be controlled. In the control amplifier A1, a torque command V T is applied to a non-inverting input terminal thereof from a terminal 16. The control amplifier A1 adjusts the amount of current I CTL flowing in each of the constant current sources 14 and 15 so that a voltage R F across the resistance R11 is the same as the voltage of the torque command V T . The resistance 10 is provided for setting a DC-gain of the control amplifier A1 in cooperation with the resistance R11. The operation of the conventional brushless motor driver having the above structure will be explained below. The sensor signals H U ⁺, H U ⁻, H V ⁺, H V ⁻, H W ⁺ and H W ⁻ as shown in Fig. 5 are applied to the terminals 4 to 9 of the waveform synthetic circuit 13 in relation to the rotating angle ϑ E of the rotor. As a result, a current I O of the constant current source 10 is fed to the transistors Q3 and Q9 in proportion to the base-to-emitter voltages of the transistors Q1 and Q2 forming the differential transistor pair. Further, a current I O of the constant current source 11 is fed to the transistors Q6 and Q3 in proportion to the base-to-emitter voltages of the transistors Q4 and Q5 forming the differential transistor pair. Moreover, a current I O of the constant current source 12 is fed to the transistors Q9 and Q6 in proportion to the base-to-emitter voltages of the transistors Q7 and Q8 forming the differential transistor pair. Thus, the current corresponding to the one obtained by adding the current flowing through the transistor Q1 and the current flowing through the transistor Q5 flows through the resistance R3 via the transistors Q3 and Q12 forming the current mirror circuit, to thereby set the potential of the node N1. Further, the current corresponding to the one obtained by adding the current flowing through the transistor Q4 and the current flowing through the transistor Q8 flows through the resistance R2 via the transistors Q6 and Q11 forming the current mirror circuit, to thereby set the potential of the node N2. Moreover, the current corresponding to the one obtained by adding the current flowing through the transistor Q7 and the current flowing through the transistor Q2 flows through the resistance R1 via the transistors Q9 and Q10 forming the current mirror circuit, to thereby set the potential of the node N3. Consequently, the potential of the node N1 is "H" when the voltages of the sensor signals H U ⁺, H U ⁻, H V ⁺ and H V ⁻ have the relation of H U ⁺ > H U ⁻, H V ⁻ > H V ⁺ (namely, the rotating angle ϑ E is within the range from O° to 120°), while the potential is "L" when the voltages of the sensor signals H U ⁺, H U ⁻, H V ⁻ and H V ⁺ have the relation of H U ⁺ < H U ⁻, H V ⁻ < H V ⁺ (namely, the rotating angle ϑ E is within the range from 180° to 300°). When the level of the node N1 is "H", the transistor Q14 conducts to supply the current corresponding to the current flowing through the transistor Q14 to the base of the driving transistor Q21 and the resistance R4 through transistors Q19 and Q20 forming the current mirror circuit, so that the driving transistor Q21 is turned on. On the other hand, when the level of the node N2 is "L", the transistor Q13 conducts to supply a current to the base of the driving transistor Q22 and the resistance R7, so that the driving transistor Q22 is turned on. Similarly, the potential of the node N2 is "H" when the voltages of the sensor signals H V ⁺, H V ⁻, H W ⁺ and H W ⁻ have the relation of H V ⁺ > H V ⁻, H W ⁻ > H W ⁺ (namely, the rotating angle ϑ E is within the range from 120° to 240°), so that the driving transistor Q25 is turned on by the transistors Q16, Q23 and Q24. On the other hand, the potential of the node N2 is "L" when the voltages of the sensor signals H V ⁺, H V ⁻, H W ⁺ and H W ⁻ have the relation of H V ⁺ < H V ⁻, H W ⁻ < H W ⁺ (namely, the rotating angle ϑ E is within the range from O° to 60° and 300° to 360°), so that the driving transistor Q26 is turned on by the transistor Q15. Similarly, the potential of the node N3 is "H" when the voltages of the sensor signals H W ⁺, H W ⁻, H U ⁺ and H U ⁻ have the relation of H W ⁺ > H W ⁻, H U ⁻ > H U ⁺ (namely, the rotating angle ϑ E is within the range from 240° to 360°), so that the driving transistor Q29 is turned on by the transistor Q18, Q27 and Q28. On the other hand, the potential of the node N3 is "L" when the voltages of the sensor signals H W ⁺, H W ⁻, H U ⁺ and H U ⁻ have the relation of H W ⁺ < H W ⁻, H U ⁻ < H U ⁺ (namely, the rotating angle ϑ E is within the range from 60° to 180°), so that the driving transistor Q30 is turned on by the transistor Q17. Thus, the driving transistors Q21, Q25 and Q29 arranged on the upper side and the driving transistors Q22, Q26 and Q30 arranged on the lower side are sequentially turned on by switching every rotating angle 120° on the basis of the sensor signals H U ⁺, H U ⁻, H V ⁺, H V ⁻, H W ⁺ and H W ⁻, whereby the current sequentially flows to driving coils 2a, 2b and 2c so as to obtain a rotating magnetic field for producing a moment of rotation. A table of energized state will be shown below. The motor is driven by repeating the above energized state 1 to 6. Fig. 6 shows the current inflow-outflow state of the brushless motor 1 in U phase, V phase and W phase. In the above brushless motor driver, the currents I CTL of the constant current sources 14 and 15 are adjusted by the control amplifier A1 so that a driving current corresponding to the torque command V T flows to the driving coils 2a, 2b and 2c. Namely, when the voltage of the torque command V T rises, the currents I CTL of the constant current sources 14 and 15 are increased by the operation of the control amplifier A1, whereby the base currents of the driving transistors Q21, Q22, Q25, Q26, Q29 and Q30 are increased to increase the driving current flowing in the driving coils 2a, 2b and 2c. The driving current causes the voltage R F to rise by flowing in the resistance R11. When the voltage R F becomes equal to the voltage of the torque command the increase of the current I CTL by the control amplifier A1 is ceased for supplying the driving current corresponding to the torque command V T to the driving coils 2a, 2b and 2c. Similarly, when the voltage of to torque command V T decreases the currents I CTL of the constant current sources 14 and 15 are decreased by the operation of the control amplifier A1, whereby the base currents of the driving transistors Q21, Q22, Q25, Q26, Q29 and Q30 are decreased to decrease the driving current flowing in the driving coils 2a, 2b and 2c. The driving current causes the voltage R F to reduce by flowing in the resistance R11. When the voltage R F becomes equal to the voltage of the torque command V T , the decrease of the current I CTL by the control amplifier A1 is ceased for supplying the driving current corresponding to the torque command V T to the driving coils 2a, 2b and 2c. However, such a conventional brushless motor driver has the following disadvantages. Since the driving current flowing in the motor 1 depends only on the voltage of the torque command V T and the voltage R F across the resistance R11, the driving transistors Q21, Q22, Q25, Q26, Q29 and Q30 always enter into a saturation area irrespective of the value of the torque command V T , thereby deteriorating the running efficiency and making noise. Another brushless motor driver is disclosed in the patent publication JP-A 58-33988. The motor is controlled by applying signals of the rotor position to differential amplifiers. The voltage of a reference voltage generator is compared with the outputs of transistors, which detect the operating voltages of coil drive transistors, thereby controlling the currents of the transistors through a current mirror circuit, a transistor and a condenser of a low pass filter. The arrangement is provided to prevent oversaturation of the coil drive transistors. A principal object of the present invention is to provide an improved brushless motor driver which can drive the motor with a high efficiency and a low noise while preventing saturation of driving transistors with respect to any torque command. According to the present invention, a brushless motor driver is provided as defined in claim 1. The brushless motor driver comprises a brushless motor having a rotor and driving coils for polyphase; control signal producing means for producing transistor drive control signals per each phase on the basis of the rotating angle of the rotor; means for applying a torque command; current adjusting means for adjusting an amount of current in the transistor drive control signals on the basis of the torque command; a group of driving transistors, each of the driving transistors having a control electrode, for driving the rotor by controlling current with respect to the driving coils on the basis of the transistor drive control signals applied to each of the control electrodes; saturation voltage generating means for generating a saturation voltage corresponding to the torque command; and current correcting means for comparing the saturation voltage generated by the saturation voltage generating means with an operating voltage of each the driving transistors to correct the amount of current in the transistor drive control signals so that the operating voltage drops below the saturation voltage generator by the saturation voltage generating means. With the brushless motor driver according to the present invention, the saturation voltage corresponding to the torque command is generated and compared with the operating voltage of each of the driving transistors to correct the value of current in the transistor drive control signals so that the operating voltage drops below the generated saturation voltage, for driving the motor with high efficiency and low noise while preventing saturation of the driving transistors at any torque command. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which Fig. 1 is a circuit diagram showing a brushless motor driver according to an embodiment of the present invention; Fig. 2 is a characteristic diagram showing a relation between current I CTL and base potential of a transistor Q35; Fig. 3 is a diagram showing a motor driving waveform; Fig. 4 is a circuit diagram showing a conventional brushless motor driver; Fig. 5 is a waveform diagram of sensor signals; and Fig. 6 is a diagram showing a relation between a rotating angle ϑ E and an inflow-outflow state of currents flowing in U phase, V phase and W phase. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a circuit diagram showing a brushless motor driver according to an embodiment of the present invention. In Fig. 1, the same reference numerals as in Fig. 4 designate identical or equivalent parts. In the brushless motor driver, a PNP transistor Q49 in lieu of the constant current source 14 in Fig. 4 is connected to emitters of the transistors Q13, Q15 and Q17, while an NPN transistor Q50 in lieu of the constant current source 15 in Fig. 4 is connected to emitters of the transistors Q14, Q16 and Q18. A constant current source 17 is further provided in which an amount or value of a current I CTL is controlled by the control amplifier A1. A current distributing circuit which consists of transistors Q39 to Q48 is also provided between the constant current source 17 and the transistors Q49 and Q50. Namely, one end of the constant current source 17 is connected with the positive feed terminal 3 while another end thereof is connected with a collector and a base of an NPN transistor Q39 and a base of an NPN transistor Q40. Emitters of the transistors Q39 and Q40 are connected with ground respectively, thus the transistors Q39 and Q40 form a current mirror circuit. A collector of the transistor Q40 is connected with a collector and a base of a PNP transistor Q41 and a base of a PNP transistor Q42, while emitters of the transistors Q41 and Q42 are connected with the positive feed terminal 3 respectively, thus the transistors Q41 and Q42 form a current mirror circuit. A collector of the transistor Q42 is connected with emitters of PNP transistors Q43 and Q44 forming a differential transistor pair. A reference voltage V REF is applied to a base of the transistor Q43 from a voltage source 18, while an output voltage V O of an error amplifier A2 is applied to a base of the transistor Q44, so that a current flowing in the transistor Q42 may be distributed to the transistors Q43 and Q44 according to the voltages V REF at the basis of Q43 and V O at the basis of Q44. A collector of the transistor Q43 is connected with a collector and a base of an NPN transistor Q45 and a base of the NPN transistor Q50, while emitters of the transistors Q45 and Q50 are connected with ground respectively, thus the transistors Q45 and Q50 form a current mirror circuit. A collector of the transistor Q44 is connected with a collector and a base of an NPN transistor Q46 and a base of an NPN transistor Q47, while emitters of the transistors Q46 and Q47 are connected with ground respecetively, thus the transistors Q46 and Q47 form a current mirror circuit. A collector of the transistor Q47 is connected with a collector and a base of a PNP transistor Q48 and a base of the PNP transistor Q49, while emitters of the transistors Q48 and Q49 are connected with the positive feed terminal 3 respectively, thus the transistors Q48 and Q49 form a current mirror circuit. In the above circuit structure, a current corresponding to a current supplied to the transistor Q39 from the constant current source 17 flows to the transistor Q42 through the transistors Q40 and Q41. A current flowing in the transistor Q42 is distributed to the transistors Q43 and Q44 according to the voltages V REF and V O . Thus a current corresponding to a current flowing in the transistor Q43 flows in the transistor Q50 through the transistor Q45, while a current corresponding to the current flowing in the transistor Q44 flows in the transistor Q49 through the transistors Q46, Q47 and Q48. An amplification circuit 19 consists of an error amplifier A2, a voltage source 18 for generating a reference voltage V REF , and resistances R15 and R16. The reference voltage V REF from the voltage source 18 is in addition to Q43 also fed to a non-inverting input terminal of the error amplifier A2. In a inverting input terminal of the error amplifier A2, a potential (a motor driving output voltage for U phase) of a node between the driving transistors Q21 and Q22 is inputted through resistances R12 and R15, and a potential (a motor driving output voltage for V phase) of a node between the driving transistors Q25 and Q26 is inputted through resistances R13 and R15, while a potential (a motor driving output voltage for W phase) of a node between the driving transistors Q29 and Q30 is inputted through resistances R14 and R15, respectively. The error amplifier A2 produces the voltage V O by amplifying the difference between the reference voltage V REF and the motor driving output voltage with a gain corresponding to the ratio of the resistance R16 to the resistance R15, and supplies the voltage V O to the base of the transistor Q44 so that the sum of the motor driving output voltages becomes equal to the reference voltage V REF . A saturation voltage generating circuit 22 consists of constant current sources 20 and 21, a diode Q34, and a resistance R17. One end of the constant current source 20 for supplying the current I CTL and one end of the constant current source 21 for supplying a current I₁ are connected to the positive feed terminal 3 respectively, while the other ends of the constant current sources 20 and 21 are connected with an anode of the diode 34 respectively. A cathode of the diode 34 is connected with the emitters of the driving transistors Q22, Q26 and Q30 through the resistance R17. On the other hand, a constant current source 23 and diodes Q31, Q32 and Q33 are provided for detecting operating voltages (collector-to-emitter voltages) of the driving transistors Q22, Q26 and Q30 arranged at the lower side. Namely, one end of the constant current source 23 for supplying a current I₁ is connected with the positive feed terminal 3, while the other end of the constant current source 23 is connected with anodes of the diodes Q31, Q32 and Q33, and cathodes of the diodes Q31, Q32 and Q33 are connected with the collectors of the driving transistors Q22, Q26 and Q30 respectively. Further, a current correcting circuit 25 consists of transistors Q35 to Q38, and a constant current source 24 for correcting the base currents of the driving transistors Q21, Q22, Q25, Q26, Q29 and Q30. Namely, one end of the constant current source 24 for supplying a current I CTL is connected with the positive feed terminal 3, while the other end of the constant current source 24 is connected with emitters of PNP transistors Q35 and Q36 forming a differential transistor pair. A base of the transistor Q35 is connected with a node between the constant current source 20 and the diode Q34, while a base of the transistor Q36 is connected with a node between the constant current source 23 and the diodes Q31, Q32 and Q33. A collector of the transistor Q35 is connected with ground while a collector of the transistor Q36 is connected with a collector and a base of an NPN transistor Q37 and a base of an NPN transistor Q38. Emitters of transistors Q37 and Q38 are connected with ground respectively, while the collector of the transistor Q38 is connected with a collector of the transistor Q39, thus the transistors Q37 and Q38 form a current mirror circuit. Now let us consider a base potential of the transistor Q35. The base potential of the transistor Q35 is the sum of the voltage R F across the resistance R11, the voltage across the resistance R17, and the voltage across the diode Q34. As shown in Fig. 2, the base potential has a characteristic shown by a solid line S with respect to the current I CTL . In Fig. 2, reference numeral α designates a rising component of the base potential on the basis of the current I₁ supplied from the constant current source 21. The rising component is given by the following equation: α = KT q ℓn I₁ I S + R17 x I₁ where K indicates the Boltzmann constant, T the absolute temperature, q the electric charge, and I S the reverse saturation current of the diode Q34. The rising component α is set for generating the saturation voltage which is slightly higher than the actual saturation voltage of the driving transistors. On the other hand, the base potential of the transistor Q36 is the sum of the voltage R F across the resistance R11, the operating voltage of the driving transistor Q22, Q26 or Q30, and the voltage across the diode Q31, Q32 or Q33. In comparison between the base potentials of the transistor Q35 and Q36, since the voltages R F are cancelled out each other and the voltage across the diode Q31, Q32 or Q33 is also cancelled out with the voltage across the diode Q34, the saturation of the driving transistor is practically detected by the voltage across the resistance R17. Namely, when the operating voltage of the driving transistor drops below the voltage across the resistance R17 by the saturation of the driving transistor, the base potential of the transistor Q36 becomes less than the base potential of the transistor Q35, whereby the current I CTL of the constant current source 24 is divided into the transistor Q36 on the basis of the differential characteristic of the transistors Q35 and Q36. Thus, with the operation of the transistors Q37 and Q38 forming the current mirror circuit, a current corresponding to a current flowing in the transistor Q36 is absorbed from the constant current source 17 into ground through the transistor Q38. The operation of the brushless motor driver having the above structure will be explained below. First, the operation will be explained in a case where voltage of middle points in motor driving waveforms specified by the motor driving output voltages for U∼W phase are equal to the reference voltage V REF , and the driving transistors Q21, Q22, Q25, Q26, Q29 and Q30 are not in the saturation state. In this case, the same voltage as the reference voltage V REF is applied to the base of the transistor Q44 as the output voltage V O of the error amplifier A2, while the reference voltage V REF is applied to the base of the transistor Q43 from the voltage source 18. Therefore, the current flowing in the transistor Q42 is divided in a ratio 1:1 for supplying to the transistors Q43 and Q44. Further, in the non-saturation state of the driving transistors Q22, Q26 and Q30, the base potential of the transistor Q36 is higher than the base potential of the transistor Q35, and hence all the current I CTL of the constant current source 24 flows to the transistor Q35, to thereby prevent the current I CTL of the constant current source 17 from being absorbed by the transistor Q38. Accordingly, the current corresponding to the current I CTL flowing in the transistor Q39 flows to the transistor Q42 through the transistors Q40 and Q41, and the current flowing in the transistor Q42 is divided in the ratio 1:1 for supplying to the transistors Q43 and Q44, whereby the current corresponding to the current flowing in the transistor Q43 flows to the transistor Q50 through the transistor Q45, while the current corresponding to the current flowing in the transistor Q44 flows to the transistor Q49 through the transistors Q46, Q47 and Q48. Thus, the base currents corresponding to the torque command V T are supplied to the driving transistors Q21, Q22, Q25, Q26, Q29 and Q30, whereby the driving currents corresponding to the torque command V T are supplied to the driving coils 2a, 2b and 2c. In the afore mentioned state, when the driving transistors are saturated, the operating voltages of the driving transistors Q22, Q26 and Q30 arranged at the lower side drop, whereby the base potential of the transistor Q36 drops below the base potential of the transistor Q35 corresponding to the generated saturation voltage. Consequently, a part of the current I CTL of the constant current source 24 flows to the transistor Q36, whereby the current corresponding to the current flowing in the transistor Q36 is absorbed through the transistor Q37 by the transistor Q38 from the constant current source 17. As a result, the current supplied to the transistor Q39 from the constant current source 17 decreases to cause the currents of the transistors Q49 and Q50 to decrease, whereby the base currents of the driving transistors Q21, Q22, Q25, Q26, Q29 and Q30 decrease to prevent the driving transistors from saturating. Further, in the afore mentioned motor driving state, the sum of the motor driving output voltages for U∼W phase is adjusted so as to correspond with the reference voltage V REF by the amplification circuit 19 and the transistors Q43 and Q44 forming the differential circuit. Namely, if the sum of the motor driving output voltages becomes higher than the reference voltage V REF , the increased voltage is amplified by the amplification circuit 19 to cause the base potential V O of the transistor Q44 to drop, whereby the current flowing in the transistor Q50 decreases while the current flowing in the transistor Q49 increases on the basis of the differential characteristic of the transistors Q43 and Q44. Consequently, the base currents of the driving transistors Q21, Q25 and Q29 arranged at the upper side decrease to cause the operating voltages (collector-to-emitter voltages) of the driving transistors Q21, Q25 and Q29 to rise, while the base currents of the driving transistors Q22, Q26 and Q30 arranged at the lower side increase to cause the operating voltages (collector-to-emitter voltages) of the driving transistors Q22, Q26 and Q30 to drop, whereby the motor driving output voltages of U∼W phases drop. Conversely, if the sum of the motor driving output voltages becomes lower than the reference voltage V REF , the decreased voltage is amplified by the amplification circuit 19 to cause the base potential V O of the transistor Q44 to rise, whereby the current flowing in the transistor Q50 increases while the current flowing in the transistor Q49 decreases on the basis of the differential characteristic of the transistors Q43 and Q44. Consequently, the base currents of the driving transistors Q21, Q25 and Q29 arranged at the upper side increase to cause the operating voltages of the driving transistors Q21, Q25 and Q29 to drop, while the base currents of the driving transistors Q22, Q26 and Q30 arranged at the lower side decrease to cause the operating voltages of the driving transistors Q22, Q26 and Q30 to rise, whereby the motor driving output voltages of U∼W phases rise. Thus, the sum of the motor driving output voltages for U∼W phases is adjusted so as to correspond with the reference voltage V REF . Fig. 3 shows a motor driving waveform N in which the middle point thereof is set at the reference voltage V REF . As shown in Fig. 3, the motor driving waveform N oscillates around the reference voltage V REF . Therefore, if the reference voltage V REF is given by the following equation: V REF = VCC - (V BE1 + V CE1 + V CE2 ) 2 where V BE1 : the base-to-emitter voltages of the transistors Q21, Q25 and Q29 V CE1 : the collector-to-emitter voltages of the PNP transistors Q20, Q24 and Q28 V CE2 : the collector-to-emitter voltages of the transistors Q22, Q26 and Q30 By detecting the saturation voltage of the driving transistors Q22, Q26 and Q30 arranged at the lower side, it is possible to drive the driving transistors Q21, Q25 and Q29 arranged at the upper side without saturation. In the present embodiment, the reference voltage V REF is given on the basis of the above equation, thus the driving transistors Q21, Q22, Q25, Q26, Q29 and Q30 are prevented from saturating. Further, in the above embodiment, the driving transistors Q21, Q25 and Q29 arranged at the upper side from PNP-NPN complementary output circuits in cooperation with the PNP transistors Q20, Q24 and Q28. Though, if the reference voltage V REF is given by the following equation: V REF = V CC - (V CE3 + V CE2 ) 2 where V CE3 : the collector-to-emitter voltages of the PNP transistors arranged at the upper side V CE2 : the collector-to-emitter voltages of the driving transistors arranged at the lower side The driving transistors arranged at the upper side can be formed as a PNP output circuit. In the above embodiment, the saturation of the driving transistors Q22, Q26 and Q30 arranged at the lower side for adjust the motor driving output voltages of U ∼ W phases, is detected by means of the amplification circuit 19 and transistors Q43 and Q44 so that the driving transistors Q21, Q25 and Q29 arranged at the upper side can be prevented from saturation. The saturation of the driving transistors Q21, Q25 and Q29 arranged at the upper side for adjusting the motor driving output voltages of U ∼ W phases may be detected by means the amplification circuit 19 and transistors Q43 and Q44 so that the driving transistors Q22, Q26 and Q30 arranged at the lower side can also be prevented from saturation.

Claims: A brushless motor driver comprising: a brushless motor having a rotor and driving coils (2a, 2b, 2c) for polyphase; control signal producing means (13) for producing transistor drive control signals per each phase on the basis of the rotating angle of said rotor; driving transistors (Q21, Q22, Q25, Q26, Q29, Q30) for controlling the current fed to said driving coils (2a, 2b, 2c) on the basis of said transistor drive control signals; means (16) for applying a torque command; current adjusting means (A1, R10, R11, Q39 - Q50, 17) for adjusting an amount of current flowing in said driving transistors on the basis of said torque command (V T ); saturation voltage generating means (22) for generating a saturation voltage corresponding to said torque command (V T ); and current correcting means (25) for comparing said saturation voltage with an operating voltage of said driving transistors (Q21, Q22, Q25, Q26, Q29, Q30) to correct the amount of current flowing in said driving transistors which is adjusted by said current adjusting means so that said operating voltage drops below said saturation voltage, characterized in that said brushless motor driver further comprises a positive feed terminal (3) and a negative feed terminal (R F ), said driving transistors including a group of first driving transistors (Q21, Q25, Q29) connected between said positive feed terminal (3) and each of said driving coils (2a, 2b, 2c) respectively and a group of second driving transistors (Q22, Q26, Q30) connected between said negative feed terminal (R F ) and each of said driving coils (2a, 2b, 2c) respectively, said current correcting means (25) compares said operating voltage of at least one of said groups of first driving transistors (Q21, Q25, Q29) and second driving transistors (Q22, Q26, Q30) with said saturation voltage, said brushless motor driver further comprises amplification circuit means (19) for adjusting the ratio of currents flowing in said group of first driving transistors (Q21, Q25, Q29) and said group of second driving transistors (Q22, Q26, Q30) so that the potential of the nodes between said first driving transistors and said second driving transistors is substantially equal to a reference voltage (V REF ), said circuit means (19) being arranged to compare said potential of the nodes between said first driving transistors and said second driving transistors with said reference voltage (V REF ). A brushless motor driver in accordance with claim 1, characterized in that said saturation voltage generating means (22) comprises: constant current sources (20, 21) for generating an amount of current corresponding to said torque command (V T ); and a resistance (R17) connected in series with said constant current sources (20, 21) for generating a saturation voltage as a function of a current supplied from said constant current sources (20, 21). A brushless motor driver in accordance with claim 1, characterized in that said current correcting means (25) comprises: a constant current source (24) for generating an amount of current corresponding to said torque command (V T ); a differential transistor pair (Q35, Q36), which consists of two transistors (Q35, Q36) connected to said constant current source (24) respectively, for distributing the current supplied from said constant current source (24) to each of said two transistors (Q35, Q36) as a function of said saturation voltage generated by said saturation voltage generating means (22) and said operating voltage of said group of driving transistors; and a current mirror circuit (Q37, Q38) connected to one transistor (36) of said differential transistor pair (Q35, Q36) for correcting an amount of current flowing in said group of driving transistors as a function of the current flowing in said one transistor (Q36) when said operating voltage of said group of driving transistors drops below the saturation voltage generated by said saturation voltage generating means (22).

Inventors: ISHII TOSHIHIKO C O MITSUBISHI, ISHII, TOSHIHIKO C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1989
Main classification: H02P6
IPC codes: H02P6