Complementary bipolar semiconductor device

Abstract: A complementary semiconductor device is disclosed which comprises a substrate (1) and four layer structure (2 ... 6) of pnpn provided on the substrate wherein the first three layers (2, 3, 5) constitute a pnp-type bipolar transistor and the second to fourth layers (3, 5, 6) constitute an npn-type bipolar transistor. According to the present invention, the pnp- and npn-type transistors can be produced by crystal growth of one time and thus production steps are simple and yield is remarkably improved.

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device and more particularly it relates to a complementary bipolar integrated semiconductor device which has a high operation speed and has a low power consumption and is easily made in large scale integration and a method for making it. Hitherto an Si complementary bipolar integrated circuit has been discussed in the I.E.D.M 84, Technical Digest (1984), pages 753-756. According to conventional techniques, pnp and npn type transistors have been produced through separate processing steps, and the steps have been complicated and yield has been low. Furthermore, conventional techniques have had problems that since more high-temperature processing steps are required than for production of either one of pnp or npn type transistors, it is difficult to obtain elements exactly as designed owing to the effect of diffusion of impurities. Moreover, with reference to compound semiconductors, although the "Applied Physics Letter" vol. 46 (3), (1985) pages 302-304 makes mention of npn type transistors, there have been severe limitations in processing and complementary circuits have not yet been realized. Besides, as in the case of Si, when pnp and npn are produced through separate processing steps, the same problems as above occur. A semiconductor device with the features included in the first part of claim 1 is disclosed in JP-A-62 298 150. SUMMARY OF THE INVENTION The object of the present invention is to provide a structure for a transistor from which a large scale integrated circuit of high speed and low power consumption. The object is met by a semiconductor device according to claim 1. Preferred embodiments are disclosed in the subclaims. The semiconductor crystal is composed of five layers of pnipn and the pnip portion and nipn portions are operating as ordinary pnp and npn type transistors, respectively. Furthermore, when a compound semiconductor is used as a constituting material, at least a part of a p layer or an n layer which is the outermost layer of the laminate structure can have a wider forbidden bandwidth than in other layers. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(a) is a schematic view of a sectional structure of the semiconductor device of Example 1 which is not covered by the present invention. Fig. 1(b) is a schematic view of a modified sectional structure of the semiconductor of Fig. 1. Fig. 2 schematically shows the steps of production according to Example 2. Fig. 3 is a diagram of the band structure of a modification of Example 1. Fig. 4 is a diagram of the modified band structure of a modification of Example 2. Fig. 5 is a diagram of the band structure of Example 2. Fig. 6 is a diagram of the band structure of Example 4. Fig. 7 is a diagram of the band structure of the first case in Example 6. Fig. 8 is a diagram of the band structure of the second case in Example 6. Fig. 9 is a diagram of the modified band structure of a modification of Example 4. Fig. 10 is a diagram of the modified band structure of a modification ofExample 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention the transistor structure can be produced by one crystal growth for pnp and npn transistors. Thus, a complementary integrated circuit can be produced through a simple step and yield can be remarkably improved. Especially for compound semiconductors, it has become possible for the first time to produce a complementary integrated circuit on the same substrate. Example 1 Fig. 1a is a cross-sectional view of structure of the transistor produced in example 1 which is not covered by the invention. In Fig. 1a, 2' indicates p type GaAs layer (impurity density p=1 x 10 19 /cm 3 , film thickness d=0.5 µm), 3 indicates n type GaAs layer (n=5 x 10 17 /cm 3 , d=200 nm), 5 indicates p type GaAs layer (p=5 x 10 17 /cm 3 , d=200 nm) and 6' indicates n type GaAs layer (n=5 x 10 18 /cm 3 , d=100 nm) and the low impurity density layer indicated by 4 in Fig. 1(b) was not formed in this example. The present method of production was as follows. First, the layers were sequently stacked on a GaAs substrate by molecular beam epitaxy method. In this case, Si was used as n-type impurity and Be was used as p-type impurity. The crystal growth can be made by other methods, for example, an organometallic CVD method. Further, other impurities such as Sn as n-type and C as p-type may be used if doping thereof can be made to the above-mentioned extent without considerable diffusion during the crystal growth. Next, the crystal was processed to the shape as shown in Fig. 2 by repeatedly carrying out ordinary photolithography and etching. On the right side of figure 2(c) between 15 and 16 is first region where npnp layers remain and npn transistor is formed using top three layers, whereas between 17 and 18 in figure 2(c) is second region where pnp layers remain and pnp transistor is formed. Furthermore, electrodes indicated by 7-12 in Fig. 1 were deposited by repeatedly carrying out photolithography, vacuum evaporation and lifting-off. This was further subjected to a heat treatment (for 2 minutes at 400°C in N 2 ) to afford ohmic contact between electrode and semiconductor. As electrode materials which can provide good ohmic contact by such heat treatment, AuGe alloy and AuZn alloy were used for n-type GaAs and p-type GaAs, respectively. However, the similar results can also be obtained by using other materials such as AuSn alloy for n-type and AuBe alloy for the p-type. Furthermore, although not shown, a smooth surface converted with SiO 2 can be obtained by coating SOG at 500 nm on the transistor and heat treating it at 300°C for 10 minutes under ordinary atmospheric conditions. Holes were made through SiO 2 by ordinary photolithography and etching with aqueous HF solution to expose electrode portion. Therein was deposited a wiring metal such as Ti/Al two-layer film and wiring was formed by carrying out further lithography and etching. According to this procedure, it becomes possible to prevent disconnection of wiring at portion of different levels, and further, since SiO 2 acts as a protective film, it is possible to prevent change with time of transistor characteristics caused by deterioration of semiconductor surface due to water or the like. In order to further improve moisture resistance, on said SiO 2 film can be deposited a film of phospho-silicate glass (PSG) by hot CVD method or a film of silicon nitride by plasma CVD method. By wiring on this smoothened film, sufficient reliability can be realized when a large scale integration is effected. In the above example, the upper n-layer of npn type bipolar transistor was the emitter and the lower player of pnp type bipolar transistor was the emitter, but it can also be operated as a bipolar transistor where these layers are collectors. Example 2 As shown in Fig. 2, on a semi-insulating GaAs substrate were sequently grown a p-type GaAs layer 2' (impurity density p=1 x 10 19 /cm 3 , film thickness 0.5 µm), a p-type Al x Ga 1-x As layer 2 (x=0.3, impurity density p=5 x 10 17 /cm 3 , film thickness 0.1 µm), an n-type GaAs layer 3 (impurity density n=5 x 10 18 /cm 3 , film thickness 0.05 µm), a low impurity density GaAs layer 4 (impurity density: 1 x 10 16 /cm 3 or less, film thickness 0.3 µm), a p-type GaAs layer 5 (impurity density p=2 x 10 19 /cm 3 , film thickness 0.08 µm), an n-type Al x Ga 1-x As layer 6 (x=0.3, impurity density n=5 x 10 17 /cm 3 , film thickness 0.1 µm), and an n-type GaAs layer 6' (impurity density n=5 x 10 18 /cm 3 , film thickness 0.1 µm). Be was used as p-type impurity here, but a similar effect can be obtained with Mg, Mn, C and the like. Si was used as n-type impurity here, but a similar effect can be obtained with Sn, S, Se, Te and the like. The band structure of this crystal in depth direction is as shown in Fig. 5. This crystal was subjected to the same processing as in Example 1 to obtain a transistor of the shape as shown in Fig. 1b. Furthermore, the surface of this transistor was smoothened with SiO 2 in the same manner as in Example 1 and wiring was made. With reference to electrode material, AuGe alloy was used for n-type GaAs layers 6' and 3 and AuZn alloy was used for p-type GaAs layers 5 and 2'. However, similar results can be obtained by using other materials such as AuSn alloy for the n-type and AuBe ally for the p-type. High frequency characteristics of the resulting transistor were as follows. The npn type transistor: f T =35 GHz, f max =32 GHz and the pnp type transistor: f T =24 GHz, f max =41 GHz. Power consumption per 1 gate and delay time examined by forming a ring oscillator were 0.3 mW and 41 picoseconds. Moreover, in this example, the effect of improving breakdown voltage was obtained by introducing the low impurity density layer 4 and at least 15 V was obtained as collector to emitter voltage. Moreover, there is obtained the effect to improve doping rate by using AlGaAs as layer 2 and 6 which function as emitter layer and a current gain of at least 200 for a transistor was obtained. Layers 2' and 6' were provided for easily attaining ohmic contact and operation per se is not damaged even if these are removed. Fig. 4 is a diagram of band structure of crystal when layers 2' and 6' were not provided. The value of f T of a transistor using this crystal was about 80% of that of the transistor of this example due to increase of resistance. However, the complementary circuit operated without hindrance. Power consumption was increased by 10% and gate delay increased by 20%. Example 3 Before deposition of electrodes in Example 2, H + ion was implanted into area 15 of Fig. 2 (c) and O + ion into area 17 at an accelerating voltage of 180 kV and at a dose of 5 x 10 12 /cm 2 . Thereafter, a transistor was produced by the same steps as in Example 2. Since the portions into which ions were implanted became high-resistive resulting in decrease of junction capacitance, f T and f max increased, namely, f T =35 GHz and f max =51 GHz in npn type transistor and f T =35 GHz and f max =47 GHz in pnp-type transistor. H + and O + were used as ions to be implanted above, but the similar effect can be obtained using other ions such as B + and F + if collector base·emitter base junction capacitance is decreased by selecting appropriate acceleration voltage. Example 4 A composition graded layer 20 (film thickness 30 nm) gradually changing in Al compositional ratio from 0.3 to 0 was introduced at Al 0.3 Ga 0.7 As-GaAs interface, namely, at interface of layers 2-3 and 5-6 present in the growing crystal in Examples 2 and 3. Diagram of band structure in depth direction of the crystal in this case is shown in Fig. 6. As a result, there were obtained effects of reduction in series resistance (40%) and reduction in threshold voltage (1.3 V → 1.0 V). With the reduction, f T value increased by 20% and power consumption decreased by 20%. Example 5 Thickness of low impurity density GaAs layer 4 in Examples 2-4 was decreased from 0.3 µm to 0.15 µm. As a result, f T was improved by about 15% for npn-type transistor and about 10% for pnp-type transistor. Example 6 The low impurity density GaAs layer 4 in Examples 2-5 was substituted by a low impurity density Al 0.3 Ga 0.7 As layer. Diagram of band structure in depth direction of crystal in this case is shown in Fig. 7. In this case, accumulation of carrier occurred at interface of layers 3-4 and 4-5 and current gain decreased. Therefore, the same Al composition graded layer of 30 nm as in Example 4 was provided at the interfaces of layers 3-4, 4-5. The diagram of band structure when the Al composition graded layer was provided is shown in Fig. 8. Breakdown voltage of transistor became twice and current to afford maximum f T became twice. Thus, f T was improved by about 25%. Example 7 Transistors were produced by exchanging layers 2' and 6', 2 and 6 and 3 and 5, respectively in Examples 2-6. In this case, n and p were exchanged with each other and hence npn type transistor and pnp type transistor were exchanged with each other. As a result, f T and f max changed, namely, f T decreased by 30% and f max decreased by 50% for npn type transistor and f T increased by 25% and f max increased by 5% for pnp type transistor. Explanation has been made on specific materials in the above Examples. Other applicable materials will be explained below. First, with reference to the forbidden band-width of a semiconductor, all of layers 2'-6' may have the same forbidden band-width. In this case, the materials may be element or compound semiconductors such as Si, Ge, GaAs, InP, InAs, GaSb and Gap and their alloys such as Si x Ge 1-x (x: 0-1) alloy, Al x Ga 1-x As, In x Ga 1-x As, GaAs x P 1-x , Al x Ga 1-x Sb and GaAs x Sb 1-x . It is also possible to increase current gain by changing the forbidden band-width in the multi-layer structure. In this case, it is necessary to form a hetero junction by increasing the forbidden band-width of layers 2 and 6 about more than 0.1 eV than those of layers 2', 3, 4, 5 and 6'. In this case, further direct current and high frequency characteristics are improved if a series resistance is decreased by providing a composition graded layer of 30 nm - 100 nm in thickness so that conduction band edge and valence band edge are smoothly connected at interfaces of layers 2'-2 and 6'-6. When such composition graded layer was provided in Examples 4 and 7, the band structure diagrams are as shown in Fig. 9 and Fig. 10, respectively. As combinations of material wide in forbidden band-width and material narrow in forbidden band-width usable in such structure, mention may be made of, for example, Al x Ga 1-x As (x ≧ 0.1) - GaAs, Si - Ge x Si 1-x (x ≧ 0.1), InP - In x Ga 1-x As (x ≧ 0.1), GaP-Si, GaAs - Ge, InAlAs - InGaAs, InP - InGaAs, GaP-GaAsP, GaAsP - GaAs, and Al x Ga 1-x Sb - GaSb (x ≧ 0.1). Further, when the transistor is operated at a high current density of more than 10 4 A/cm 2 or when breakdown voltage of collector must be especially high (≧ 20V), deterioration of characteristics under high current density and high voltage can be prevented by increasing the forbidden band-width of intrinsic collector layer 4 to the extent similar to that of layers 2 and 6 in the above case. Combinations of materials usable in this case are the same as mentioned-above. Similar improvements to those mentioned above can be attained by providing a forbidden band-width graded layer at the interface between layers 4 and 3 and layers 5 and 4 in the same manner as mentioned above. Film thickness and impurity density: Ranges of thickness and impurity density of respective layers which may be selected are shown below in the sequence of (1) layer No., (2) impurity density n or p and (3) thickness d. Layer 2': n ≧ 1 x 10 18 /cm 3 , d ≧ 200 nm Layer 2: n ≧ 1 x 10 17 /cm 3 , d ≧ 50 nm Layer 3: n ≧ 1 x 10 17 /cm 3 , 200 nm ≧ d ≧ 30 nm Layer 4: p,n ≦ 1 x 10 16 /cm 3 , 1 µm ≧ d ≧ 100 nm Layer 5: n ≧ 1 x 10 17 /cm 3 , 200 nm ≧ d ≧ 30 nm Layer 6: p ≧ 1 x 10 17 /cm 3 , d ≧ 50 nm Layer 6': p ≧ 1 x 10 18 /cm 3 , d ≧ 100 nm The impurity density is subjected to further limitation by the forbidden band-width of the respective layers. If forbidden band-width of all layers are identical, the impurity density of layer 2 and that of layer 3 (referred to as n 2 ' and p 3 , respectively) must have the relation of n 2 ≧ 10 p 3 . Furthermore, impurity density of layer 5 and that of layer 6 must also have the relation of p 6 ≧ 10 x n 5 (the symbols have the similar meanings to those in the above formula). When the forbidden band-width of layer 2 and that of layer 6 are wider than those of other layers by 0.1 eV or more, good transistor operation in all of the above-mentioned regions is obtained. Example 8 In Fig. 2 (a), 1 indicates an Si substrate (n-type impurity density 1 x 10 16 /cm 3 ). On this substrate were sequently grown B doped p-type Si layers 2' and 2 (impurity density p=1 x 10 20 /cm 3 , thickness 0.5 µm), As doped n-type Si layer 3 (impurity density n=1 x 10 18 /cm 3 , thickness 0.2 µm), low impurity density layer 4 (impurity density 5 x 10 15 /cm 3 , thickness 0.4 µm), B doped p-type Si layer 5 (impurity density p=2 x 10 18 /cm 3 , thickness 0.1 µm), and As doped n-type Si layers 6 and 6' (n=1 x 10 20 /cm 3 , thickness 0.5 µm). Then, as shown in Fig. 2 (b), the portion other than region 13 which is to be npn-type transistor was subjected to etching by ordinary photolithography and ordinary etching until layer 5 was exposed. Further, as shown in Fig. 2 (c), isolation region 14, pnp-type transistor emitter region 18, pnp-type transistor base region 17, npn-type transistor collector region 16, and npn-type transistor base region 15 were formed by processing according to ordinary photolithography and etching. To the thus processed crystal were applied electrodes using a metal such as Al and polycrystal silicon doped with impurity which can afford ohmic contact to obtain a transistor as shown in Fig. 1b. Then, smoothening and wiring were effected in the same manner as in Example 2, although these procedures are not shown in the drawings. High frequency characteristics of this transistor were measured to obtain a maximum cut-off frequency f T of 20 GHz and maximum oscillatable frequency f max of 22 GHz for npn-type transistor and f T of 15 GHz and f max of 20 GHz for pnp-type transistor. A ring oscillator was prepared by complementary circuit using these npn and pnp transistors and delay per 1 gate was measured to obtain a power consumption of 0.1 mW and a delay time of 61 picoseconds per 1 gate. Yield of integrated circuit was 60% of complete operation for circuit of 200 in element number. Example 9 When thickness of layer 4 in Example 8 was changed to 0.2 µm, f T of npn and pnp transistors were 30 GHz and 20 GHz, respectively. Yield increased to 70% under the above-mentioned conditions. Example 10 In Example 8, layers of up to layer 4 were prepared by crystal growth and layers 5, 6 and 6' were formed by introduction of impurity from the surface by diffusion. In this case, thickness of layer 4 upon crystal growth was 0.6 µm and thickness after diffusion was 0.35 µm by deduction of thicknesses of layers 5 and 6 which were 0.1 µm and 0.5 µm, respectively. Performance of the elements was the same as in Example 8. Example 11 A transistor was prepared in the same manner as in Example 8 except that layer 2 and layers 6 and 6' were exchanged and layer 3 and layer 5 were exchanged. In this case, however, since pnp-type transistor and npn-type transistor were replaced with each other, it is necessary to use electrode materials which can afford ohmic contacts, respectively. Characteristics of respective elements were as follows: f T and f max of npn-type transistor were 16 GHz and 26 GHz, respectively and f T and f max of pnp-type transistor were 18 GHz and 20 GHz, respectively. In Examples 8-11, n-type Si substrate (impurity density n=1 x 10 16 /cm 3 ) was used, but nearly the same values of characteristics for both the n-type and p-type transistors are obtained by using other substrates as far as impurity density thereof is 5 x 10 18 /cm 3 or less. Furthermore, similar characteristics can be obtained by using an insulator substrate such as sapphire and this is advantageous in preparation of circuits of high integration because parasitic capacitance such as wiring capacitance is reduced. According to the present invention, transistors of both the pnp-type and npn-type can be produced by one crystal growth. Therefore, complementary integrated circuit can be produced by simple step and yield can be markedly improved. Especially, complementary integrated circuits can be produced with compound semiconductors.

Claims: A semiconductor device comprising a substrate (1) and a multi-layer structure provided thereon, wherein said multi-layer structure contains at least a first semiconductor layer (2, 2') of a first conductivity type, a second semiconductor layer (3) having a conductivity type opposite to that of the first semiconductor layer (2, 2'), a third semiconductor layer (5) having a conductivity type identical with that of the first semiconductor layer (2, 2'), and a fourth semiconductor layer (6, 6') having a conductivity type identical with that of the second semiconductor layer (3), said semiconductor layers being stacked in this order on the substrate, characterised in that an intrinsic semiconductor layer (4) is provided between the second and the third semiconductor layers (3, 5) and a groove (14) extends into said substrate (1) to divide the multi-layer structure into first and second regions, wherein said first region (2', 2, 3, 4, 5) is a first bipolar transistor composed of the first semiconductor layer (2, 2') of the first region being an emitter, the second semiconductor layer (3) of the first region being a base and the intrinsic semiconductor layer (4) of the first region and the third semiconductor layer (5) of the first region being a collector, and said second region (2', 2, 3, 4, 5, 6, 6') is a second bipolar transistor composed of the fourth semiconductor layer (6, 6') of the second region being an emitter, the third semiconductor layer (5) of the second region being a base and the intrinsic semiconductor layer (4) of the second region and the second semiconductor layer (3) of the second region being a collector. The semiconductor device according to claim 1, wherein the thickness of the intrinsic semiconductor layer (4) ranges within 0.1 µm to 1 µm. The semiconductor device according to claim 1 or 2, wherein the intrinsic semiconductor layer (4) has a wider forbidden band-width than the second and the third semiconductor layers (3, 5). The semiconductor device according to any of claims 1 to 3, wherein at least a part of the first semiconductor layer (2, 2') has a wider forbidden band-width than the second, third and fourth semiconductor layers (3, 5, 6, 6'). The semiconductor device according to any of claims 1 to 4, wherein a part of the fourth semiconductor layer (6, 6') has a wider forbidden band-width than the first, second and third semiconductor layers (2', 2 , 3, 5). The semiconductor device according to any of claims 1 to 5, wherein said semiconductor layers (2', 2 , ... 6, 6') are made of compound semiconductors.

Inventors: KUSANO CHUSHIROU SANKOPO HIGAS, TAKAHASHI SUSUMU, TANOUE TOMONORI, KUSANO, CHUSHIROU, TAKAHASHI, SUSUMU, TANOUE, TOMONORI, KUSANO, CHUSHIROU SANKOPO HIGASHITOKOROZAWA 304
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1989
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L29