Lateral insulated gate bipolar transistor

Abstract: A lateral insulated gate bipolar transistor comprises a p layer (50) and a p⁺ layer (70) provided apart from each other and extending from a surface of an n⁻ layer (20) into the n⁻ layer, an n⁺ layer (60) provided extending from a surface of the p layer (50) into the p layer, a first main electrode (2) provided in ohmic contact with the n⁺ layer (60) and the p layer (50) , a second main electrode (3) provided in ohmic contact with the p⁺ layer (70) , and a control electrode (1) provided through an insulating film (10) on the n⁺ layer (60) , the p layer (50) and the n⁻ layer (20) on the side of the first main electrode (2) away from the second main electrode (3).

Description: BACKGROUND OF THE INVENTION The present invention relates to a lateral insulated gate bipolar transistor, and more particularly to improvement on a latch-up prevention ability of the lateral insulated gate bipolar transistor. In the recent years, an insulated gate bipolar transistor (hereinafter referred to as IGBT) is highlighted as a semiconductor device capable of controlling a relatively large current at a high speed. In order to integrate the IGBT together with another device, it is desirable that an emitter (cathode), a gate (ccncrc[ electrode) and a collector (anode) are placed in the same plane. An example of an IGBT structure satisfying this requirement is a lateral IGBT disclosed by JP-A-59-132667 (& EP-A-0 111 803). The disclosed structure is shown in Fig. 9. In an n - layer 20 are independently provided a p layer 50 having an impurity concentration higher than that of the n - layer 20 and a p + layer 70 having an impurity higher than that of the p layer 50. In the layer 50 is provided an n + layer 60 having an impurity concentration higher than the p layer 50. The p layer 50 and the n + layer 60 are electrically short-circuited by an emitter electrode 2. A collector electrode 3 is provided on a surface of the p + layer 70 in ohmic contact with the p + layer 70. An insulating film 10 is provided stretching over the surfaces of the n + layer 60, the p layer 50 and the n - layer 20 and a gate electrode 1 is provided on the insulating film 10. The n + layer 60 and the insulating film 10 are provided opposite to the p + layer 70 and the n + layer 60 exists between the p + layer 70 and a region where the p layer 50 and the emitter electrode 2 are in ohmic contact with each other. In this transistor, when a positive potential is applied to the gate electrode 1, the conductivity of a surface portion of the p layer 50 under the insulating film 10 is inverted into an n type so that a channel is formed. Electrons ⊖ flowing out of the n + layer 60 pass through the channel and the n - layer 20 and reach the p + layer 70 from which positive holes ⊕ are injected. Thereby, the n - layer 20 having a high resistance is conductivity-modulated to exhibit a low resistance, thereby providing a merit that an on-resistance lower than that of a MOSFET having the same forward blocking characteristic can be realized. In the above-mentioned conventional lateral IGBT, the n + layer 60 exists between the p + layer 70 and the region where the p layer 50 and the emitter electrode 2 are in ohmic contact with each other. In this case, the positive holes ⊕ injected from the p + layer 70 concentrically flow through the p layer 50 under the n + layer 60 and reach the emitter electrode. Therefore, a potential drop is produced due to a resistance component R of the p layer 50 in a lateral direction. As a result, there is a problem that a pn junction formed by the n + layer 60 and the p layer 50 is forward-biased by the potential drop to cause the injection of electrons from the n + layer 60 into the p layer 50 so that there occurs a so-called latch-up phenomenon in which a parasitic thyristor formed by the n + layer 60, the p layer 50, the n - layer 20 and the p + layer 70 is turned on, thereby making it impossible to control a current by the gate. Figs. 1A and 1B are a longitudinal cross section and a plan view showing a lateral IGBT such as that known from EP-A-0 047 392. On the side of one surface of an n - layer 20, a p layer 50 and a p + layer 70 extending from the surface of the n - layer 20 thereinto are provided apart from each other. In the p layer 50 is provided an n + layer 60 which extends from a surface of the p layer 50 thereinto. An insulating film 10 is provided stretching over the surfaces of the n + layer 60, the p layer 50 and the n - layer 20 and a gate electrode 1 is provided on the insulating film 10. The p layer 50 and the n + layer 60 are provided in ohmic contact with an emitter electrode 2 at a position nearer to the p + layer 70 than the gate electrode 1. A region where the p layer 50 and the emitter electrode 2 are in ohmic contact with each other is positioned nearer to the p + layer 70 than the n + layer 60. A collector electrode 3 is provided in ohmic contact with a surface of the p + layer 70. The p layer 50, the n + layer 60 and the p + layer 70 are juxtaposed, in the one surface of the n - layer 20, with their stripe shapes the longitudinal directions of which are parallel to each other. Necessarily, the emitter electrode 2, the gate electrode 1 and the collector electrode 3 are provided along the p layer 50, the n + layer 60 and the p + layer 70, respectively. Next, explanation will be made of the operation of the lateral IGBT having the above-mentioned construction. When a positive potential is applied to the gate electrode 1 in a state in which a voltage bringing the collector electrode 3 into a positive potential and the emitter electrode 2 into a negative potential is applied between the collector electrode 3 and the emitter electrode 2, a channel is produced in a surface of the p layer 50 under the insulating film 10 so that electrons ⊖ are flown out of the n + layer 60 through the channel and reach the p + layer 70 through the n - layer 20. In Fig. 1A, the flow of electrons ⊖ is indicated by dotted line. A pn junction between the p + layer 70 and the n - layer 20 is forward-biased by the electrons ⊖ reaching the p + layer 70 so that positive holes ⊕ are injected from the p + layer 70 into the n - layer 20. The positive holes ⊕ pass through the n - layer 20 and the p layer 50 and reach the emitter electrode 2. In Fig. 1A, the flow of positive holes ⊕ is indicated by one-dotted chain line. Since the region where the emitter electrode 2 and the p layer 50 are in ohmic contact with each other is positioned nearer to the p + layer 70 than the n + layer 60, the positive holes ⊕ can arrive at the emitter electrode 2 without passing under the n + layer 60, thereby providing a merit that the latch-up prevention ability is improved and hence it is possible to control a large current. In the present lateral IGBT, it is preferable that the impurity concentrations of the p + layer 70, the n - layer 20, the p layer 50 and the n + layer 60 are equal to 1 x 10 18 to 1 x 10 20 atoms/cm 3 , 1 x 10 13 to 5 x 10 15 atoms/cm 3 , 1 x 10 15 to 5 x 10 18 atoms/cm 3 and equal to or higher than 1 x 10 19 atoms/cm 3 , respectively. Fig. 1A shows the minimum unit of the lateral IGBT for explaining the basic concept thereof. An actual product has a structure which a multiplicity of such minimum units are provided in parallel. Fig. 2 is a longitudinal cross section showing another lateral IGBT. In Fig. 2, the same reference numerals as those in Fig. 1A designate the same portions as those in Fig. 1A. An n + buried layer 61 is provided in an n - layer 20 below a p layer 50 and apart from the p layer 50. In the present embodiment, since electrons ⊖ flow through the n + buried layer 61 having a low resistance, the resistance of a region through which the electrons ⊖ flow is reduced, thereby providing a merit that an ON resistance is lowered as compared with that in the first embodiment. The present lateral IGBT has such a plane structure as shown in Fig. 1B. SUMMARY OF THE INVENTION An object of the present invention is to provide an improved lateral IGBT which has an improved latch-up prevention ability and a lower on-resistance. The above object is realized in lateral insulated gate bipolar transistors as disclosed in anyone of independent claims 1 or 5. Particular embodiments are disclosed in the dependent claims. In the present invention, carriers injected from the semiconductor region serving as the collector can arrive at the emitter electrode without passing below the semiconductor region serving as the emitter. Therefore, the latch-up prevention ability can be improved, thereby making it possible to control a large current. Furthermore, the electron and hole flow paths coincide, thereby lowering the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A and 1B are a longitudinal cross section and a plan view showing a lateral IGBT; Fig. 2 is a longitudinal cross section showing another lateral IGBT; Fig. 3 is a perspective view showing a first embodiment of the present invention; Figs. 4A and 4B are a longitudinal cross section and a plan view showing a second embodiment of the present invention; Figs. 5 and 6 are longitudinal cross sections showing lateral IGBTs; Figs. 7A and 7B are a schematic plan view and a circuit diagram of a power converting device in which the present invention is used; Fig. 8 shows current waveforms for explaining the operation of the device shown in Figs. 7A and 7B; and Fig. 9 is a longitudinal cross section of a conventional lateral IGBT. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be explained by virtue of the accompanying drawings which show embodiments thereof. Fig. 3 is a perspective view showing a first embodiment of the present invention. In Fig. 3, the same reference numerals as those in Fig. 1A designate the same portions as those in Fig. 1A. An insulating film 10 is provided stretching over a p layer 50 and an n - layer 20 at a side near to a collector electrode 3 and stretching over the n - layer 20, the p layer 50 and a n + layer 60 at a side away from the collector electrode 3. Each of the p layer 50 and a p + layer 70 is formed in a surface of the n - layer 20 and with a shape elongated in one direction and the n + layer 60 is constructed by a plurality of regions which are provided in parallel along a longitudinal direction of the p + layer 70. Therefore, the collector electrode 3 is formed along a longitudinal direction of the p + layer 70, an emitter electrode 2 is divided into a plurality of portions and a gate electrode 1 is formed so as to enclose each emitter electrode 2. In the present embodiment, electrons ⊖ flowing out of the n + layer 60 pass through a channel produced in the vicinity of the p layer under the insulating film 10 and flow into the n - layer 20 from a portion under the insulating film 10 opposing the p + layer 70. Therefore, the electrons and positive holes take the same path in the n - layer 20 and hence the conductivity is sufficiently modulated, thereby providing a merit that an on resistance lower than that in the lateral IGBT of Fig.1A is exhibited. Figs. 4A and 4B are a longitudinal cross section and a plan view showing a second embodiment of the present invention. A p + layer 70 and a p layer 50 elongated in one direction are independently provided in an n - layer 20. An n + layer 63, an n + layer 60 and an n + layer 62 are provided in the p layer 50 and along a longitudinal direction of the p layer 50. The n + layer 60 is positioned between the n + layers 62 and 63 and are divided into a plurality of regions along the longitudinal direction of the p layer 50. An emitter electrode 2 includes a plurality of portions which are in ohmic contact with the n + layer 60 and the p layer 50 positioned on the side near to the p + layer 70 than n + layer 60. A collector electrode 3 is provided on a surface of the p + layer 70 along a longitudinal direction and in ohmic contact with the p + layer 70. A gate electrode 1,101,102 is formed on the n + layer 63, the p layer 50 and the n - layer 20 through an insulating film 10 on a side near the collector electrode 3 so as to stretch over the layers 63, 50 and 20 and is formed on the n + layer 60, the p layer 50 and the n layer 62 through the insulating film 10 on a side away from the collector electrode 3 as to stretch over the layers 60, 50 and 62. Portions 102, 101 of the gate electrode 1 near to and away from the collector electrode 3 are integral with each other. The n + layer 62 and the n + layer 63 are connected by an n + layer 4 but may be connected by a conductor in place of the n + layer 4. Each of opposite ends of the p layer 50 in the longitudinal direction thereof has a predetermined curvature for the purpose of mitigating the concentration of an electric field and the gate electrode 1 is provided through the insulating film 10 on the periphery of the p layer 50 and the n - layer 20 adjacent thereto. The p layer 50, the n + layer 60, the n + layer 62 and the n + layer 63 have a symmetrical structure with respect to line A-A (see Fig. 4B). In this case, two rows for each of the n + layer 60 and the emitter electrode 2 are provided in a longitudinal direction. Preferably, the two rows are positionally shifted from each other in the longitudinal direction. An actual device has a structure in which the p + layers 70 and the p layer 50 are alternately arranged so that the p + layers 70 are positioned at opposite outsides. The operation of the present embodiment is as follows. When a positive potential is applied to the gate electrode 1 in a state in which a voltage bringing the collector electrode 3 into a positive potential is applied between the collector electrode 3 and the emitter electrode 2, a channel is formed in a surface of the p layer 50 lying below the insulating film 10. With the formation of this channel, electrons ⊖ from the n + layer 60 flow into the n + layer 62 through the channel. The electrons ⊖ arriving at the n + layer 62 reach the n + layer 63 through the n + layer 4 and pass through the channel formed in the p layer 50 below a portion of the gate electrode 1 near to the collector electrode 3 to flow into the n - layer 20, thereby arriving at the p + layer 70. The flow of electrons ⊖ is indicated by dotted line in Fig. 4A. On the other hand, positive holes ⊕ from the p + layer 70 take a route in which they pass through the n - layer 20 to enter into the p layer 50 and reach the emitter electrode 3, as indicated by one-dotted chain line in Fig. 4A. Thus, in the present embodiment, since the flow paths of the electrons ⊖ and the positive holes ⊕ coincide with each other, a sufficient conductivity modulation is made, thereby realizing a lateral IGBT which has an on-resistance lower than that in the lateral iGBT of Fig.1A. Also, a distance along which the electrons flow through the channel is shortened as compared with the third embodiment. Namely, the sum of the length of the channel between the n + layer 60 and the n + layer 62 and the length of the channel between the n layer 63 and the n - layer 20 in the present embodiment is shorter than the length of the channel in the third embodiment extending from the n + layer 60 to the n - layer 20 and hence the flow distance of electrons ⊖ is short, thereby providing an advantage of low on-resistance. Fig. 5 is a longitudinal cross section showing a structure in which an n - layer 20 is formed on a p - layer 30 and is surrounded by a p + layer 71. An electrode 5 is provided on a surface of the p + layer 71 in ohmic contact with the p + layer 71. The lowest potential is applied to the electrode 5 so that the p + layer 71 and the p - layer 30 are reverse-biased relative to the n - layer 20. Therefore, the lateral IGBT formed on the same p - layer 30 is electrically isolated from the other elements or devices. A lateral iGBT having a n - drift layer formed on a p - substrate is known from IEDM 1987, Technical Digest, pages 774-777. Such formation of a lateral IGBT in the pn-isolated substrate is applicable to all the embodiments of the invention excepting an embodiment which will be explained in conjunction with Fig. 6. Fig. 6 is a longitudinal cross section showing a structure in which an n - layer 20 is a monocrystalline region which is island-wise formed through an insulating film (or dielectric film) 11 in a supporting substrate 80. A lateral MOS-bipolar device formed in a single-crystalline region of a substrate with dielectric isolation is known from IEDM 1985, Technical Digest, pages 724-727. In the structure of Fig. 5, positive holes injected from the p + layer 70 may flow as a leakage current into the electrode 5 applied with the lowest potential, thereby resulting in a loss. In the present structure, on the other hand, all of positive holes flow into an emitter electrode 2, thereby providing a merit that any leakage current can be prevented. In the present structure, an n region 21 having an impurity concentration higher than the n - layer 20 is formed in a portion of the n - layer 20 adjacent to the p + layer 70 and an n + layer 22 is formed in a portion of the n - layer 20 adjacent to the insulating film 11. Also, a p layer 50 has a p + region 51 adjacent to an n + layer 60. Such formation of a lateral IGBT in the monocrystalline island of the dielectric-isolated substrate is applicable to all the embodiments of the invention excepting the embodiment explained in conjunction with Fig. 5. Figs. 7A and 7B are a schematic plan view and a circuit diagram of an example of a power converting device to which lateral IGBT's according to the present invention are applied, more particularly, an inverter in which a current is controlled by turning on/off four lateral IGBT's. In the figures, reference numerals 80a, 80b, 80c and 80d designate lateral IGBT's formed in an island-like area of a dielectric-isolated substrate 300, numerals 90a, 90b, 90c and 90d diodes formed in another island-like area of the dielectric-isolated substrate 300, symbol T AC an AC terminal, symbol T DC DC terminals, symbols G a , G b , G c and G d gate terminals, numeral 100 a load, and numeral 200 a DC power source. Such a device may involve an operation in which the IGBT 30a is turned on when a current is flowing through the diode 90b. Namely, when the IGBT 80a is turned off in order to control a current in a state in which the IGBT's 80a and 80d are in ON state so that a current I 1 is flown, a current I 2 flows through the IGBT 80d and the diode 90b. At this time, if the IGBT 80a is turned on again, a power source voltage is applied across the diode 90b so that excess carriers having been stored in the diode 90d are swept out, thereby causing a current I 3 to flow transiently. This transient state is schematically shown in Fig. 8. When the IGBT 80a is turned on at instant of time t = t 1 , the current I 2 having flown through the diode 90b is decreased and at instant of time t = t 2 the current I 3 having a direction reverse to that of the current I 2 start to flow through the diode 90b. At this time, a current of I 1 + I 3 flows through the IGBT 80a until instant of time t = t 3 when the current I 3 becomes zero. Thus, an excessive current flows through the IGBT 80a during a period of time from t 2 to t 3 . Therefore, in the conventional lateral IGBT of Fig. 9, latch-up occurs, thereby making it impossible to control a current. However, in the power converting device in which the lateral IGBT's according to the present invention are used, no impossibility of control is encountered since the latch-up prevention ability is improved. In the foregoing, typical examples of the present invention have been disclosed. However, it should be noted that the present invention is not limited to the disclosed embodiments and various changes or modifications are possible within the scope of the appended claims. In a lateral insulated gate bipolar transistor according to the present invention, since a region where a semiconductor layer having the same conductivity type as a collector layer contacts an emitter electrode is provided nearer to the collector layer than an emitter layer, the latch-up prevention ability is improved, thereby making it possible to control a large current. Moreover, on-resistance is reduced since the electron and hole flow paths coincide.

Claims: A lateral insulated gate bipolar transistor comprising a first semiconductor region (20) of one conductivity type having a major surface, second and third semiconductor regions (50, 70) of the other conductivity type located apart from each other in said first semiconductor region (20) with their shapes elongated in one direction, and extending from said major surface of said first semiconductor region (20) into said first semiconductor region (20), a plurality of fourth semiconductor regions (60) of the one conductivity type located in said second semiconductor region (50), disposed in a row along said one direction and extending from said major surface into said second semiconductor region (50), a plurality of first main electrodes (2), each of which being in ohmic contact with one of said fourth semiconductor regions (60) and said second semiconductor region (50) at said major surface, a second main electrode (3) provided in ohmic contact with said third semiconductor region (70) at said major surface along said one direction, and a control electrode (1) disposed apart from said first main electrodes (2) on an insulating film (10), a first portion of said control electrode (1) being located on said first, second and fourth semiconductor regions (20, 50, 60) at said major surface on the side opposite to that of said second main electrode (3) with respect to said first main electrodes (2), a second portion of said control electrode (1) being located on said first and second semiconductor regions (20, 50) at said major surface on the same side as that of said second main electrode (3) with respect to said first main electrode (2), and a plurality of third portions of said control electrode (1), each of which being located on said second semiconductor region (50) and on two regions of said plurality of fourth semiconductor regions (60) which are adjacent to each other, said third portions extending on said second semiconductor region (50) between said two adjacent fourth semiconductor regions (60) from said first portion of said control electrode (1) to said second portion of said control electrode (1). A lateral insulated gate bipolar transistor according to claim 1, wherein said first semiconductor region (20) is a region formed on the side of one surface of a semiconductor substrate (30) of the other conductivity type and extends from said one surface into said substrate (30). A lateral insulated gate bipolar transistor according to claim 1, wherein said first semiconductor region (20) is a monocrystalline semiconductor island formed in a substrate (80) and electrically isolated therefrom by a dielectric film (11). A lateral insulated gate bipolar transistor according to claim 1, wherein said control electrode (1) surrounds said first main electrodes (2). A lateral insulated gate bipolar transistor comprising a first semiconductor region (20) of one conductivity type having a major surface, second and third semiconductor regions (50, 70) of the other conductivity type located apart from each other in said first semiconductor region (20) with their shapes elongated in one direction, and extending from said major surface of said first semiconductor region (20) into said first semiconductor region (20), a plurality of fourth semiconductor regions (60) of the one conductivity type located in said second semiconductor region (50), disposed in a row along said one direction and extending from said major surface into said second semiconductor region (50), fifth and sixth semiconductor regions (62, 63) of the one conductivity type located in said second semiconductor region, extending from said major surface into said second semiconductor region (50), and extending along said one direction apart from said fourth semiconductor regions (60) on opposite sides thereof, a plurality of first main electrodes (2), each of which being in ohmic contact with one of said fourth semiconductor regions (60) and said second semiconductor region (50) at said major surface, a second main electrode (3) provided in ohmic contact with said third semiconductor region (70) at said major surface along said one direction, a first control electrode (101) disposed apart from said first main electrodes (2) on an insulating film (10) on said second, fourth and fifth semiconductor regions (50, 60, 62) at said major surface on the side opposite to that of said second main electrode (3) with respect to said first main electrodes (2), a second control electrode (102) disposed apart from said first main electrodes (2) on an insulating film (10) on said first, second and sixth semiconductor regions (20, 50, 63) at said major surface on the same side at that of said second main electrode (3) with respect to said first main electrode (2) and electrically connected to said first control electrode (101), and means (4) electrically connecting said fifth semiconductor region (62) and said sixth semiconductor region (63).

Inventors: MORI MUTSUHIRO, SAKURAI NAOKI, TANAKA TOMOYUKI, MORI, MUTSUHIRO, SAKURAI, NAOKI, TANAKA, TOMOYUKI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1989
Main classification: H01L29
IPC codes: H01L29