Liquid crystal apparatus

Abstract: Disclosed is a driving apparatus comprising: a. means for driving matrix electrodes having scanning and information electrodes; b. means for counting the number of scanning electrodes to which a scanning selection signal is applied; and c. means for designating a width of a scanning selection period for every predetermined count value.

Description: BACKGROUND OF THE INVENTION : Field of the Invention The present invention relates to a liquid crystal apparatus using a ferroelectric liquid crystal material and, more particularly, to a liquid crystal apparatus which can suppress a flicker generated in a display drive operation at a low temperature. Related Background Art In a known liquid crystal display element, scanning electrodes and signal electrodes are arranged in a matrix, and a liquid crystal compound is filled between these electrodes to form a large number of pixels so as to display an image or information. As a method of driving the display element, a time-divisional driving method is adopted. In this method, address signals are sequentially, periodically, and selectively applied to the scanning electrodes, and a predetermined information signal is parallelly and selectively applied to the signal electrodes in synchronism with the address signals. Most of commercially available liquid crystal display elements are TN (Twisted Nematic) liquid crystal described in, e.g., M. Schadt and W. Helfrich, "Voltage Dependent Optical Activity of a Twisted Nematic Liquid Crystal", Applied Physics Letters, 1971, Vol. 18(4), pp. 127 to 128. In recent years, as an improved conventional liquid crystal element, a liquid crystal element having bistability is proposed in, e.g., Japanese Patent Laid-Open (Kokai) JP-A-56107216 and U.S. Patent US-A-4,367,924 by Clark and Lagerwall. As a bistable liquid crystal, a ferroelectric liquid crystal having a chiral smectic C phase (SmC*) or H phase (SmH*) is used. In the C or H phase state, the ferroelectric liquid crystal takes a first or second optically stable state in response to an applied electric field, and maintains the state when no electric field is applied. That is, the ferroelectric liquid crystal has bistability, and is expected to be widely used in the field of high-speed storage type display apparatuses having a quick response property with respect to a change in electric field. The ferroelectric liquid crystal element is driven by driving apparatuses disclosed in, e.g., U.S. Patent US-A-4,548,476, US-A-4,665,561, US-A-4,697,887, US-A-4,709,995, US-A-4,712,872. However, threshold characteristics of a ferroelectric liquid crystal largely depend on an external temperature, as shown in Fig. 10. More specifically, as a temperature becomes lower, an applied voltage necessary for inversion is increased and a voltage application time is prolonged. Therefore, a ferroelectric liquid crystal must increase a drive pulse width (scanning selection period) in a driving operation at a low temperature as compared to a scanning driving operation at a frame frequency of 15 Hz at a high temperature. The ferroelectric liquid crystal requires a scanning driving operation at a low frame frequency of, e.g., 5 to 10 Hz. For this reason, in a driving operation at a low temperature, a flicker caused by the scanning driving operation at a low frame frequency occurs. Document EP-A-0 149 899 discloses a liquid crystal apparatus comprising a liquid crystal element having a matrix of electrodes including scanning electrodes and information electrodes. Driving means include means for applying a scanning selection signal to the scanning signal electrodes and means for applying an information signal to the information signal electrodes in synchronism with the scanning selection signal. For controlling the driving frequency of the driving means the control means operates in a time sharing mode. In order to achieve a temperature compensation this conventional liquid crystal apparatus suggests to control the frequency and the voltage of the driving means in case of a low temperature. However, a detailed realization for such a temperature compensation is not disclosed. SUMMARY OF THE INVENTION: It is, therefore, an object of the present invention to provide a liquid crystal apparatus with high-quality display wherein the generation of a flicker is suppressed over a wide temperature range. According to the present invention this object is achieved by a liquid crystal apparatus comprising a liquid crystal display having a matrix of electrodes including scanning electrodes and information electrodes; driving means including means for applying a scanning selection signal to said scanning electrodes and means for applying an information signal to said information electrodes in synchronism with said scanning selection signal; and control means for controlling a driving frequency of said driving means, said control means using a time sharing, said apparatus being characterized in that said control means comprises means for setting the number of lines to be scanned per field, the number of fields to be scanned per frame and the number of frames to be scanned between temperature compensation operations, and means for changing in dependence on the external temperature the number of line selection periods constituting a field period and the number of field periods constituting a frame period. The advantages of the invention will become apparent and obvious to those skilled in the pertinent art upon referring to the following description provided in connection with the accompanying drawings, of which: BRIEF DESCRIPTION OF THE DRAWINGS : Fig. 1 is a block diagram of an apparatus according to the present invention; Fig. 2 is a block diagram of a controller used in the present invention; Fig. 3 is a chart of a look-up table used in the present invention; Fig. 4 is a block diagram of a data output unit; Fig. 5 is a flow chart showing an information processing procedure used in the present invention; Fig. 6 is a waveform chart of clock signals used in the present invention; Fig. 7 is a graph showing the relationship between thermistor characteristics and an A/D conversion output; Figs. 8A to 8E are driving waveform charts used in the present invention; Fig. 9 is a block diagram showing a frame driver used in the present invention; and Fig. 10 is a graph showing temperature dependency of a DOBAMBC as a ferroelectric liquid crystal compound with respect to threshold characteristics. DESCRIPTION OF THE PREFERRED EMBODIMENT: Fig. 1 shows an embodiment of the present invention. A word processor body 1 is a host apparatus serving as a supply source of image data to be displayed on a display according the present invention. A display control apparatus 50 controls a driving operation of the display on the basis of display data supplied from the word processor body 1 in accordance with various conditions (to be described later). A display 100 employs an FLC (ferroelectric liquid crystal). A segment side driver 200 and a common side driver 300 respectively drive information electrodes and scanning electrodes provided to the display 100 in accordance with drive data supplied from the display control apparatus 50, and the like. A thermo sensor 400 is arranged at an appropriate position of the display 100, e.g., a portion at an average temperature. The display 100 includes a display screen 102, an effective display region 104 on the display screen 102, and a frame 106 provided outside the effective display region on the display screen 102. In this embodiment, electrodes corresponding to the frame 106 are arranged on the display 100, and are driven to form the frame on the screen 102. The display control apparatus 50 includes a controller 500 (to be described later with reference to Fig. 2) for controlling transmission/reception of various data with the display 100 and the word processor body 1, a data output unit 600 (to be described later with reference to Fig. 4) for driving the display drivers 200 and 300 based on display data supplied from the word processor body 1 in accordance with setting data from the controller 500, and driving the drivers to set data for the controller 500, and a frame driver 700 for forming the frame 106 on the display screen 102 on the basis of output data from the data output unit 600. The display control apparatus 50 also includes a power controller 800 for appropriately changing a voltage signal from the word processor body 1 under the control of the controller 500 to generate a voltage to be applied from the display drivers 200 and 300 to power sources, a D/A converter 900, arranged between the controller 500 and the power controller 800, for converting digital setting data of the controller 500 into analog data and supplying the analog data to the power controller 800, and an A/D converter 950, arranged between the thermo sensor 400 and the controller 500, for converting analog temperature data detected at the display 100 into digital data and supplying the digital data to the controller 500. The word processor body 1 has a function of a host apparatus serving as a display data supply source to the display 100 and the display control apparatus 50, and may be replaced with another host apparatus, e.g., a computer, an image reader, or the like. In any case, according to this embodiment, the word processor body 1 is assumed to be able to exchange the following data. That is, data to be supplied to the display control apparatus 50 are: D: Signal including address data for designating a display position of data and a horizontal sync signal. If a host apparatus has a VRAM corresponding to the effective display region 104, it can directly output address data capable of designating a display address (corresponding to a display on the effective display region 104) of image data. In this embodiment, the word processor body 1 superposes this signal on the horizontal sync signal or a blanking signal, and supplies the superposed signal to the data output unit 600. CLK: Transfer clock of image data PD0 to PD3. The word processor body 1 supplies the clock CLK to the data output unit 600. PDOWN: Signal for informing that a system power supply is turned off. The word processor body 1 supplies the signal PDOWN to the controller 500 as a non-maskable interrupt (NMI). Data to be supplied from the display control apparatus to the word processor body 1 are: P ON/OFF: Status for informing that the display control apparatus 50 completes rise and fall operations respectively when the system power supply is turned on and off. This status is output from the controller 500. Light: Signal for indicating an ON/OFF operation of a light source FL combined with the display 100. This signal is output by the controller 500. Busy: Sync signal for causing the word processor body 1 to stand by for a transfer operation of the signal D so that the display control apparatus 50 performs various setting operations during initialization or a display operation. In this embodiment, the word processor body 1 can accept the Busy signal. The Busy signal is supplied from the controller 500 to the word processor body 1 through the data output unit 600. Signals and data exchanged among respective units are summarized below. Fig. 2 shows an arrangement of the controller 500. The controller 500 comprises a CPU (microprocessor) 501 for controlling respective units in accordance with a control procedure shown in Fig. 5, a ROM 503 in which various tables shown in Fig. 3 are developed in addition to a program corresponding to the control procedure shown in Fig. 5 to be executed by the CPU 501, and a RAM 505 serving as a work area when the CPU 501 executes the control procedure. Port units PORT1 to PORT6 can set I/O directions, and respectively have ports P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, and P60 to P67. A port unit PORT7 serves as an output port, and has ports P70 to P74. I/O setting registers (data direction registers) DDR1 to DDR6 switch I/O directions of the port units PORT1 to PORT6. In this embodiment, the ports P13 to P17 (corresponding to signals A3 to A7) of the port unit PORT1, the ports P21 to P25 and P27 of the port unit PORT2, the ports P40 and P41 (corresponding to signals A8 and A9) of the port unit PORT4, the ports P53 to P57 of the port unit PORT5, the port P62 of the port unit PORT6, the ports P72 to P74 of the port unit PORT7, and terminals MP0, MP1, and STBY of the CPU 501 are unused. The controller 500 also comprises a reset unit 507 for resetting the CPU 501, and a clock generator 509 for supplying an operation reference clock (4 MHz) to the CPU 501. Timers TMR1, TMR2, and SC1 respectively have reference clock generation sources and registers, and can frequency-divide the reference clock in accordance with setting to the registers. The timer TMR2 frequency-divides the reference clock in accordance with setting to the register, and generates the signal Tout serving as a system clock of the data output unit 600. The data output unit 600 generates a clock signal for defining one horizontal scanning period (1H) of the display 100 on the basis of the signal Tout. The timer TMR1 is used for adjusting an operation time on the program and 1H of the display screen 102, and realizes such adjustment in accordance with a setting value to its register. These timers TMR1 and TMR2 supply the signal IRQ3 as an internal interrupt signal to the CPU 501 upon time-up of a setting time based on the setting value or at the beginning of the next count operation after time-up, and the CPU 501 accepts this signal as needed. Note that the timer SCI is not used in this embodiment. In Fig. 2, the controller 500 also includes an internal address bus AB and an internal data bus DB for connecting the CPU 501 and the respective units, and a hand-shake controller 511 connected between the port units PORT5 and PORT6, and the CPU 501. Fig. 3 shows memory areas allocated in the ROM 503. Data shown in Table 1 below are developed (stored) in the memory areas. Lower 2 bytes of each address in a temperature compensation look-up table shown in Table 1 coincide with A/D-converted temperature data in consideration of processing efficiency. More specifically, the look-up table shown in Fig. 3 is realized by reading an address obtained by adding a start address of each parameter area to temperature data. In order to perform temperature compensation, data of a drive voltage according to an external temperature and 1H (horizontal scanning period = scanning selection period) are developed. Fig. 4 shows an arrangement of the data output unit 600. A data input unit 601 is linked to the word processor body 1 to receive the signal D and the transfer clock CLK. The signal D is a sum signal of the image signal and the horizontal sync signal, and is transmitted from the word processor body 1. In this embodiment, real address data is superposed on the horizontal sync signal or the horizontal blanking period, and the superposed signal is supplied. The data input unit 601 switches a data output path in accordance with the presence/absence of detection of the horizontal sync signal or the horizontal blanking period. Upon detection of the horizontal sync signal or the horizontal blanking period, the data input unit 601 recognizes the superposed signal component as the real address data, and outputs it as the real address data RA/D. When the horizontal sync signal or the horizontal blanking period is not detected, the unit 601 recognizes a signal component during this interval as image data, and outputs it as 4-bit parallel image data D0 to D3. When the data input unit 601 recognizes input of the real address data, it enables the address/data identification signal A/ D . The signal A/ D is supplied to an IRQ generator 603 and a DACT generator 605. The IRQ generator 603 outputs the interrupt signal IRQ upon reception of the signal A/ D The signal IRQ is supplied to the controller 500 as the interrupt instruction IRQ1 in accordance with setting at a switch 520 to perform operation in a line access mode or a block access mode. The DACT generator 605 outputs the DACT signal for identifying the presence/absence of access of the display 100 upon reception of the signal A/ D , and supplies it to the controller 500, an FEN generator 611, and a gate array 680. The FEN generator 611 generates the signal FEN which starts the gate array 680 in accordance with a trigger signal input from an FEN trigger generator 613 when the DACT signal is enabled. The FEN trigger generator 613 generates a trigger signal in response to a write signal ADWR which is output from the controller 500 to cause the A/D converter 950 to fetch temperature information from the thermo sensor 400. In this case, the FEN trigger generator 613 is selected by the chip select signal DS0 generated by a device selector 621. More specifically, when the controller 500 performs chip selection of the A/D converter 950 to fetch temperature data, the FEN trigger generator 613 is also selected, and frame drive is started in response to the write signal ADWR . A busy gate 619 supplies, to the word processor body 1, a signal BUSY for acknowledging a busy state of the display control apparatus 50 in accordance with the busy signal IBUSY from the controller 500. The device selector 621 receives the signals A10 to A15 from the controller 500, and outputs the signals DS0 to DS2 for performing chip selection of the A/D converter 950, the D/A converter 900, and the data output unit 600 in accordance with the values of the input signals. A register selector 623 is started in response to the signal DS2 , and sets a latch pulse gate array 625 on the basis of the signals A0 to A4 from the controller 500 at that time. The latch pulse gate array 625 selects registers in a register unit 630, and consists of bits corresponding in number to the number of registers in the register unit 630. In this embodiment, the register unit 630 has 22 1-byte areas, and the latch pulse gate array 625 has a 22-bit configuration, each bit of which corresponds to the 1-byte area. More specifically, when the register selector 623 sets bits of the latch pulse gate array 625, the areas corresponding to the set bits are selected, and data read or write access from or to the selected registers is performed through the system data bus in accordance with the read signal RD or the write signal WR supplied from the controller 500 to the latch pulse gate array 625. The register unit 630 includes real address data registers RA/DL and RA/DU for respectively storing lower and upper 1-byte data of the real address data RA/D under the control of a real address store controller 641. Horizontal dot count data registers DCL and DCU respectively store lower and upper 1-byte data of data corresponding to the number of dots (800 dots in this embodiment) in the horizontal scanning direction of the display. A counter 643 for horizontal dot number is started at the beginning of transfer of the image data D0 to D3 to counts clocks. When the counter 643 counts the clocks corresponding to the numerical values stored in the registers DCL and DCU, it causes an LATH generator 645 to generate the latch signal LATH . A drive mode register DM stores mode data corresponding to the line or block access mode. Registers DLL and DLU store common line selection address data. Data stored in the register DLL is output as address data CA6 and CA5 for designating a block, and address data CA4 to CA0 for designating a line. Data stored in the register DLU is supplied to a decoder 650 to be output as the chip select signals CS0 to CS7 for selecting a common driving element 310. One-byte areas CL1 and CL2 store drive data to be supplied to the common side driver 300 when common side lines are driven (line write access) in the block access mode. 1-byte areas SL1 and SL2 similarly store drive data to be supplied to the segment side driver 200. One-byte areas CB1 and CB2 store drive data to be supplied to the common side driver 300 when common side lines are driven upon block erasure in the block access mode. 1-byte areas SB1 and SB2 similarly store drive data to be supplied to the segment side driver 200. One-byte areas CC1 and CC2 store data to be supplied to the common side driver 300 when common side lines are driven upon line write access in the line access mode. 1-byte areas SC1 and SC2 similarly store drive data to be supplied to the segment side driver 200. The following three 1-byte areas are areas for storing data for switching the frame driver 700, and are divided in units of 4 bits, so that registers FV1, FCVc, FV2, FV3, FSVc, and FV4 are allocated. A multiplier 661 multiplies, e.g., doubles, the pulse signal Tout from the controller 500. Ring counters 663A, 663B, 663C, and 663D respectively count 3-, 4-, 6-, and 12-phase outputs of the multiplier 661, and are respectively used for dividing one horizontal scanning period (1H) by 4, 3, 2, and 1. The divided period will be referred to as ΔT hereinafter. For example, when the 1H is divided by 3, 3ΔT defines the 1H. A multiplexer 665 selects one of the outputs from the ring counters 663A to 663D, and is set in accordance with the content of the drive mode register DM, i.e., data indicating the number of divisions of the 1H. For example, if the number of divisions is 3, the multiplexer 665 selects the output from the 4-phase ring counter 663B. A 4-phase ring counter 667 counts the outputs from the ring counters 663A to 663D. A multiplexer 669 is set in the same manner as the multiplexer 665. Fig. 6 shows the clock Tout, the output waveform of the multiplexer 661, and the output waveforms of the ring counters 663A to 663D and 667. More specifically, when the multiplexer 665 selects one of the outputs from the ring counters 663A to 663D, one of 4ΔT/1H, 3ΔT/1H, 2ΔT/1H, and ΔT/1H is selected, and its output waveform is supplied to a shift register unit 673 as a shift clock, thus outputting ON/OFF data for every ΔT. One of the outputs from the 4-phase ring counter 667 is selected by the multiplexer 669, and its output waveform is supplied to the shift register unit 673 as a shift/load signal, thus setting an operation based on the selected number of divisions. Referring again to Fig. 4, the areas CL1, CB1, and CC1 of the register unit 630 store ON/OFF data for every ΔT of the clear signal CCLR and the enable signal CEN to be supplied to the common side driver 300. The areas CL2, CB2, and CC2 similarly store ON/OFF data for every ΔT of the drive waveform defining signals CM1 and CM2. The areas SL1, SB1, and SC1 store ON/OFF state for every ΔT of the clear signal SCLR and the enable signal SEN to be supplied to the segment side driver 200. The areas SL2, SB2, and SC2 similarly store ON/OFF data for every ΔT of the waveform defining signals SM1 and SM2. In this embodiment, a storage area for each signal data has a 4-bit configuration, and 1 bit corresponds to ON/OFF data of 1ΔT. More specifically, in this embodiment, the maximum number of divisions of 1H is 4. A multiplexer unit 671 is linked to the areas CL1 to SC2. The multiplexer unit 671 selects one of signal data in line write access and block erasure access in the block access mode and the line write access in the line access mode in accordance with the content of the drive mode register DM. The multiplexer unit 671 includes a multiplexer MPX1 for selecting 4-bit data for the signal CCLR from the areas CL1, CB1, and CC1, a multiplexer MPX2 for similarly selecting 4-bit data for the signal CEN, a multiplexer MPX3 for selecting 4-bit data for the signal CM1 from the areas CL2, CB2, and CC2, and a multiplexer MPX4 for similarly selecting 4-bit data for the signal CM2. The multiplexer unit 671 also includes a multiplexer MPX5 for selecting 4-bit data for the signal SCLR from the areas SL1, SB1, and SC1, a multiplexer MPX6 for similarly selecting 4-bit data for the signal SEN, a multiplexer MPX7 for selecting 4-bit data for the signal SM1 from the areas SL2, SB2 and SC2, and a multiplexer MPX8 for similarly selecting 4-bit data for the signal SM2. The shift register unit 673 includes shift registers P/S1 to P/S8 for parallel/serial (P/S) conversion linked to the multiplexers MPX1 to MPX8 of the multiplexer unit 671, respectively. The shift register unit 673 receives the output from the multiplexer 665 as a shift clock signal, and defines an output period ΔT of the 1-bit ON/OFF data. The unit 673 also receives the output from the multiplexer 669 as a preset signal for performing an operation with the preset number of divisions. A multiplexer unit 675 includes multiplexers MPX11 to MPX18 linked to the shift registers P/S1 to P/S8, respectively. The unit 675 outputs P/S-converted ON/OFF data on the basis of bit selection data (stored in the register DM) of the 4-bit ON/OFF data of the signals stored in the registers CL1 to SC2. An output unit 677 performs the same processing as in the shift register unit 673 and the multiplexer unit 675 for the registers FV1, FCVc, FV2, FV3, FSVc, and FV4. A gate array 680 is enabled in accordance with the signals DACT and FEN to supply the switch signals V1 to V4 , CVc , and SVc to the frame driver 700. An MR generator 690 supplies the signal MR to the controller 500 when the chip select signal DS1 of the D/A converter 900 is enabled, i.e., when the D/A converter 900 is accessed, thereby changing a pulse width of the clock E generated by the CPU 501. Fig. 5 shows a program flow of a display control mode. Display control of this embodiment will be briefly described below with reference to Fig. 5. In Fig. 5, when the power switch of the word processor body 1 is set "ON", an INIT routine is automatically started (step S101). In this step, the Busy signal is set to "ON" to perform temperature compensation upon power-on. Finally, the Busy signal is set to "OFF", and the control waits until the interrupt request IRQ1 is input (step S102). The interrupt request IRQ1 is generated when address data is transferred from the word processor body 1. If no address data is input, the program is not executed, and the display screen 102 is left unchanged. When the address data is transferred and the interrupt request IRQ1 is generated, the control advances to an LSTART routine in accordance with the procedure in step S102. When the request IRQ1 is generated by the line access mode, the LSTART routine is started, and the corresponding program is executed. In this routine, the transferred address data is loaded from the data output unit 600, and it is checked if this address corresponds to the final line of the effective display region 104 (step S104). If it is determined that the address does not correspond to the final line, program execution branches to an LLINE routine (step S106). In this routine, the Busy signal is set to "ON", and line write access for one scanning line is performed on the basis of the image data following the address data. Then, the Busy signal is set to "OFF", and the control waits for the interrupt request IRQ1 (step S105). When the request signal IRQ1 is supplied, the LSTART routine is started again. If it is determined in step S105 that the address data corresponds to the final line, program execution branches to an FLLINE routine. In this routine, line write access of the final line is performed on the basis of the transferred image data. Frame driving and temperature compensation data are then updated, and the Busy signal is set to "OFF" to wait for the interrupt request IRQ1 (step S105). If the interrupt request IRQ1 is input, the LSTART routine is started again. With the above-mentioned procedure, display control in the line access mode is performed. According to the present invention, when a period in units of several tens of seconds is determined using a line counter, several ten thousands of lines must be counted to obtain one scanning selection period. In this embodiment, display control is performed using three associated counters. The three counters are respectively used to determine a frame driving period, an inter-unit correction period, and a temperature compensation period in display control. A first counter C1 is a down counter for determining a field driving timing. The counter C1 is initialized to a predetermined value in accordance with a temperature, and is decremented by one for each line scanning. A field driving operation is performed when the counter value becomes zero, and at that time, the counter is reset. The initial value of the counter according to a temperature is set in temperature compensation. A second counter C2 is a down counter for determining a timing of inter-unit temperature compensation table correction. The counter C2 is initialized to a predetermined value in accordance with a temperature, and is decremented every time the first counter C1 becomes zero, thereby counting the number of field scannings. When the second counter C2 becomes zero, a dip switch for inter-unit correction is read to calculate an offset value for performing temperature compensation table correction. Then, a driving condition reflecting the offset value is set. The counter is then reset. A third counter C3 is a down counter for determining a temperature compensation timing. The counter C3 is initialized to a predetermined value in accordance with a temperature, and is decremented every time the second counter C2 becomes zero, thus counting the number of frame scannings. When the third counter C3 becomes zero, the output from the temperature sensor is A/D-converted, and the driving condition is set on the basis of this temperature data. The counter is then reset. The first and second counters C1 and C2 are set as follows. That is, if the first counter C1 is represented by m and the second counter C2 is represented by n , a product of m and n coincides with the number of scanning lines forming one frame. The third counter C3 is read from the look-up table shown in Fig. 3 so that even if one scanning selection period changes due to a change in temperature, waveform setting by temperature compensation is performed at almost a constant cycle over the entire operation temperature range of the display. For example, if the following liquid crystal display apparatus is assumed, the number of lines is set as shown in Table 2 below at respective temperatures. In this embodiment, as shown in Table 2, at 40°C, every time 50 lines are counted, the control advances to a field driving routine; 8 fields, an inter-unit correction routine; and 625 frames, a temperature compensation routine. However, at a temperature of 5°C, every time 25 lines are counted, the control advances to the field driving routine; 16 fields, the inter-unit correction routine; and 107 frames, the temperature compensation routine. Fig. 9 shows an arrangement of the frame driver 700. The frame driver 700 includes switches 710, 715, 720, 730, 735, and 740 for respectively turning on/off supply paths of the voltage signals V1, VC, V2, V3, VC, and V4. These switches are controlled by the switch signals V1 , CVc , V2 , V3 , SVc , and V4 supplied from the gate array 680 of the data output unit 600 respectively through inverters 711, 716, 721, 731, 736, and 741. Upon frame driving, the switches 710, 715, and 720 are switched in accordance with the contents of the registers FV1, FCVc, and FV2 allocated in the register unit 630 of the data output unit 600, i.e., the states of the signals V1 , CVc , and V2 , so that a waveform signal selectively having a value of V1, VC, or V2 can be applied to a frame transparent electrode 151 parallel to the common line. The switches 730, 735, and 740 are switched in accordance with the contents of the registers FV3, FSVc, and FV4, i.e., the states of the signals V3 , SVc , and V4 , so that a waveform signal selectively having a value of V3, VC, or V4 can be applied to a frame transparent electrode 150 parallel to the segment line. Inter-unit correction is performed to set a driving condition to a predetermined correction value since a driving condition varies in units of display units due to a variation in a manufacturing process. Figs. 8A to 8E show drive waveforms used in the present invention. Fig. 8A shows a scanning selection signal, a scanning nonselection signal, a white information signal, and a black information signal. When the white information signal is applied from an information electrode to a pixel on a scanning electrode to which the scanning selection signal is applied, the pixel is erased to a black state in a phase T₁ (erased to the black state upon application of a voltage V₂ in a phase t₁ and a voltage of V₃ + V₂ in a phase t₂). In the next phase t₃, a voltage of V₁ + V₃ is applied, and the pixel is written in a white state. On the other hand, when the black information signal is applied from the information electrode to a pixel on the same scanning electrode, the pixel is erased to the black state in the phase T₁ (erased to the black state upon application of a voltage V₂ in a phase t₁ and a voltage of -V₃ + V₂ in a phase t₂), and is applied with a voltage of V₃ - V₁ in the next phase t₃, so that the immediately preceding black state is maintained and the pixel is written in the black state. In this embodiment, the above-mentioned scanning selection signal is applied to every third or more scanning electrodes. Fig. 8B exemplifies a case wherein the scanning selection signal is applied to every third scanning electrodes. Fig. 8C shows a voltage waveform to be applied to a ferroelectric liquid crystal pixel. In the above embodiment, every third scanning electrodes are selected. However, the present invention is not limited to such an interlace selection method of selecting every third scanning electrodes. For example, interlace selection methods of selecting every fourth, fifth, or (N+1)th scanning electrodes may be employed (the number of field scannings at that time is N + 1). Especially, in the present invention, an interlace selection method of selecting every ninth scanning electrodes is effective to suppress a flicker. Figs. 8D and 8E show more preferable examples. In a drive example shown in Fig. 8D, the scanning selection signal is applied to every seventh scanning electrode. More specifically, the scanning selection signal is applied to 1st (F+1)th, 5th (F+5)th, 3rd (F+3)th, 7th (F+7)th, 2nd (F+2)th, 6th (F+6)th, and 4th (F+4)th scanning electrodes in the order of 1st, 2nd,..., 7th fields (the number of field scannings is represented by F). That is, the application order of scanning signals does not coincide with the order of lines in correspondence with the field order. According to the drive example shown in Fig. 8D, the scanning selection signal is applied to non-adjacent scanning electrodes in continuous seven fields constituting one frame scanning. Fig. 8E shows another example (interlace selection method of selecting every fourth electrodes). The drive examples shown in Figs. 8D and 8E are more effective in terms of flicker suppression than in a case of the scanning signal application method shown in Fig. 8B. In the present invention, various types of ferroelectric liquid crystal elements can be employed. More specifically, an SSFLC disclosed in U.S. Patent US-A-4,367,924 (Clark et al.), a ferroelectric liquid crystal element in an orientation state having a helical residue disclosed in U.S. Patent No. 4,586,791 (Isogai et al.), or a ferroelectric liquid crystal element disclosed in UK Patent Application No. 2,159,635 may be used.

Claims: A liquid crystal apparatus comprising: a liquid crystal display (100) having a matrix of electrodes including scanning electrodes (S i ) and information electrodes (I i ); driving means (200, 300) including means (300) for applying a scanning selection signal to said scanning electrodes (S i ) and means (200) for applying an information signal to said information electrodes (I i ) in synchronism with said scanning selection signal; and control means (50) for controlling a driving frequency of said driving means (200, 300), said apparatus being characterized in that said control means (50) comprises means (C1, C2, C3) for setting the number of lines (m) to be scanned per field, the number of fields (n) to be scanned per frame and the number of frames (k) to be scanned between temperature compensation operations, and means (600) for changing in dependence on the external temperature the number of line selection periods constituting a field period and the number of field periods constituting a frame period. An apparatus according to claim 1, characterized in that said scanning selection signal is applied to every third or more scanning electrodes (S₁, S₄, S₇) during one field period so as to perform an interlace of at least 3:1. An apparatus according to claim 2, characterized in that said scanning selection signal is applied to said scanning electrodes (S i ) such that a group of adjacent scanning electrodes (S i ) are scanned during at least three consecutive field periods in such an order that adjacent scanning electrodes (S i ) are not scanned in successive field periods (Figs. 8D and 8E). An apparatus according to any of the preceding claims 1 to 3, characterized in that said scanning selection signal is a signal having voltage levels in positive (V₁) and negative (-V₂) directions with reference to an application voltage of a scanning nonselection signal (0).

Inventors: INOUE HIROSHI, OOKI AKIKO, TSUBOYAMA AKIRA, INOUE, HIROSHI, OOKI, AKIKO, TSUBOYAMA, AKIRA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1989
Main classification: G09G3
IPC codes: G02F1, G09G3