CHARGED PARTICLE MULTIDETECTOR

Abstract: A charged particle multidetector comprising a plurality of electrodes supported on a monolithic substrate. An amplifier is provided in respect of each electrode and circuits are provided for detecting the arrival of a charged particle at any one electrode. Counters are provided in respect of each electrode and the contents of the counters are incremented in response to each detection of the arrival of a charged particle at the respective electrode. The counters and associated circuitry providing inputs to the counters are all mounted on the same monolithic substrate as the electrodes. The accumulated content of each counter is read out periodically to appropriate signal processing devices.

Description: CHARGED PARTICLE MULTIDETECTOR The present invention relates to a charged particle multidetector and methods which may be used to form such a multidetector. Scientific analytical instruments such as electron spectrometers typically employ some means of dispersing a beam of charged particles so that a spectrum may be built up by scanning the resultant image across a slit in front of a detector. This procedure is inefficient because at any given time it utilises only a small fraction of the total available signal in the dispersed image. In order to make full use of this signal it is necessary to simultaneously detect as many as possible of the electrons in the dispersed electron image while preserving an adequate degree of spatial resolution. This is possible if a multiple-element detector (referred to herein as a "multidetector") is used in place of the single detector and scanned slit arrangement. In such a spectrometer, a monochromatic beam of electrons is incident on a target and scattered or emitted electrons are dispersed in energy using hemispherical electrostatic deflectors. Instead of using a conventional slit and single detector arrangement at the exit of the electron energy analyser the multidetector allows electrons with a range of energies to be detected simultaneously. A multidetector of this type is described in J. Phys. E., 13, 713-715 (1980) by Hicks, P.J.; Daviel, S; allbank B; and Comer, J. In the known multidetector, three stages are required in order to detect the electron image and transform it into a suitable electrical signal. Stage one amplifies the electron signal by a factor of around 10 6 using a microchannel plate electron multiplier. Electrons emerging from the microchannel plate are accelerated towards the second stage which translates the electron image into ' a photon image by means of a phosphor screen. This photon image is subsequently picked up and converted into an electrical signal in the third and final stage using a solid state imaging device such as a CCD (charge- coupled device) or photodiode array. An optical system comprising either a lens or a coherent fibre optic bundle is needed to transport the photon image from the phosphor to the photo-sensitive elements of the imaging device. A wide variety of multidetectors (or position- sensitive detectors) have been devised to suit particular experimental applications: even the photographic plate can be regarded as a parallel detection system. However for the detection of single- particle events the use of the microchannel plate electron multiplier (MCP) has become more or less mandatory in order to provide amplification of the image signal. The methods used for detecting the amplified electron image can then be grouped into two broad categories: i) Systems that convert the electron output of the MCP into photons by the use of phosphor screen and then detect the focussed light image. This can be accomplished either by means of a vidicon TV camera (see J. Electron Spectrosc. Relat. Pheno . , 2 , 405, (1973) by Gelius, U.; Basilier, E; Svensson, S.; Bergmark, T.; and Siegbahn, K. ) or self-scanned, solid state imaging devices such as charge-coupled devices (CCDs) or photodiode arrays of the type mentioned above, ii) Systems that directly detect the amplified electron image output from the MCP. This has been achieved using either: (a) charge division in the form of a continous resistive anode (see J. Electron Spectrosc, Relat. Phenom., 6_, 151-156 (1975) by Moak, C. D.; Date, S; Gracia Santibanez, F; and Carlston, T.A.) or a capacitively-coupled array of multiple anodes (see Rev. Sci. Inεtrum. , 47, 289-290 (1976) by Kellogg, E; Henry, P; Murray, S; Van Speybroeck, L; and Bjorkholm, P). The principal disadvantage of this technique is that events can only be detected by the detector one at a time (i.e. unable to register events which arrive simultaneously) . (b) an electrically independent multiple anode array that is capable of detecting simultaneous events. Each anode in the array needs its own amplifier, discriminator and counting electronics. This clearly presents a major obstacle to constructing a multidetector with a large number of electrodes (e.g. 256) if discrete units have to be used for the electronics associated with each anode. Nevertheless, a system has been described (see Applied Optics 14, 1632-1644, (1975), Timothy, J.G. and Bybee, R.L.) which uses 64 discrete electrodes on 50 urn centres for detecting X-rays and UV photons. More recently it has become possible to purchase microchannel plates coupled to multiple anode arrays. However, the large amount of external electronics needed to process the signals from these arrays remains their most serious drawback. It has been proposed to produce a monolithic integration of an array of electrodes and amplifiers on a single chip integrated circuit (see Nuc. Instrum. Metho. Phys. Res. .226 / 20 (1984) by Asplund, L; Gelius, U; Tove, P. .; Erikson, S.A.; and Bingerforε, N) . This proposal suggests a scheme for detecting electron events and shifting them a single bit at a time off chip by means of a serial shift register. This proposal does not seem to have been commercially exploited however. One problem with adopting an integrated circuit approach as described above is that electrons emerge from the exit plane of a microchannel plate which is at a high potential, typically around 2kV relative to ground. The electrons emerge with low kinetic energy (e.g. lOOeV) and thus,if they are to be collected on the detector electrodes, the electrodes themselves cannot afford to have a lower potential than 2kV or they would repel the emergent electrons. This means that the detector chip has to "float" at 2kV by means of an isolated power supply. Signal or data lines from the chip would normally be processed at real ground. Typically the signal or data lines leave the vacuum system within which the multidetector is supported by way of multi-way, high voltage, feedthroughs and then undergo opto-isolation to reference them to real ground. This is clearly inconvenient as the multi-way, high voltage, feedthroughs are not "off-the shelf" components. Alternatively the opto-isolators could be within the vacuum system. In either event the opto-isolation adds complications to a system which claims simplicity as one of its key features. It is an object of the present invention to provide a multidetector which is capable of obviating or mitigating the problems ouutlined above. According to the present invention there is provided a charged particle multidetector comprising a plurality of electrodes supported on a monolithic substrate, an amplifier in respect of each electrode, the amplifier being supported on the substrate, and means for transferring output signals derived from the amplifier to output terminals adapted for connection to circuitry not supported by the substrate, wherein each amplifier is associated with a respective counter supported on the substrate, means are provided on the substrate for monitoring the outputs of the amplifiers to detect the arrival of charged particles at the respective electrodes, means are provided on the substrate to increment the content of each counter in response to detection of the arrival of a charged particle at the respective electrode, and the transferring means comprise means for periodically reading out the accumulated contents of each counter to the output terminals. The term "counter" is used herein to mean any : data storage device which can be incremented to store an accumulated count of a series of events. Preferably, the monitoring means comprises means for detecting when the output of any amplifier exceeds a predetermined threshold, and the incrementing means comprises means for incrementing the respective counter each time an amplifier output exceeding the predetermined threshold is detected. Preferably the amplifier and comparator circuits comprise an inverter connected to receive the output of one electrode, a transmission gate connected in parallel with the inverter, a capacitor connected between the output of the inverter and a stable voltage source, a reference capacitor one terminal of which is connected to a stable voltage source, a sense amplifier connected between the output of the inverter and a second terminal of the reference capacitor, and switches for alternately connecting inputs to the sense amplifier to respective ones of the capacitors and to a common voltage source, means being provided to close the transmission gate when the sense amplifier is connected to the capacitors. Each electrode may be connected to a respective amplifier located beneath the electrode on the substrate. Each amplifier may be connected to a respective counter located adjacent the respective electrode on the substrate. Alternatively a plurality of ' electrodes may be connected to a respective adder located remote from the said plurality of electrodes, means being provided to sequentially sample the outputs of the amplifiers associated with the plurality of electrodes, and the adder being arranged to sequentially increment counters loca ed on the substrate remote from the electrodes each of which counters is associated with a respective one of the plurality of electrodes. Preferably, the electrodes are in the form of metal pads supported on a layer of polyimide formed over the amplifiers supported on the substrate, connections being made between the electrodes and the amplifiers through via holes formed in the polyimide layer. The polyimide layer and via holes may be formed by depositing a first layer of polyimide on the substrate, heating the layer to effect precuring, applying a layer of photoresist to the first layer of polyimide, exposing and etching the photoresist to remove areas of the first polyimide layer corresponding to the intended positions of the via holes, the removed areas being larger than the intended areas of the via holes, heating the first layer of polyimide to effect partial curing, depositing a second layer of polyimide over the first layer and the etched areas, applying a second layer of photoresist to the said layer of polyimide, exposing and etching the photoresist to remove areas of the second polyimide layer corresponding to the intended positions of the via hole, the etched areas corresponding to the intended areas of the via holes, and heating the resultant structure to cure the remaining polyimide. Preferably the electrodes are located adjacent an output plane of a microchannel plate, a spacing layer of polyimide provided with openings registering with the electrodes being located over the substrate so as to be sandwiched between the microchannel plate and the substrate supporting the electrodes, and the surface of the spacing layer supporting an electrically conductive layer in direct contact with the microchannel plate and connected to a terminal held at ground potential. Each electrode may comprise a pair of first and second electrodes separated by an insulating layer, the first electrodes being exposed to charged particles to be detected and connected to a source of bias potential, and the second electrodes being positioned beneath respective ones of the first electrodes and connected to the amplifiers, whereby the first and second electrodes of each pair are capacitively coupled together. A plurality of multidetectors can be connected in an array to form a hybrid array of any desired size. The present invention also provides a method for forming a thick polyimide film around a via hole extending through the film, wherein a first layer of polyimide is deposited on a substrate, the first layer is heated to effect precuring, a first layer of photoresist is applied to the first layer of polyimide, the photoresist is exposed and etched such that an area of the first polyimide layer is removed which is substantially larger than the intended area of the via hole, the resist is stripped from the first layer, the first layer is heated to effect partial curing, a second layer of polyimide is deposited over the first layer and the etched area, a second layer of resist is applied to the second layer of polyimide, the second layer of resist is exposed and etched such that an area of the second polyimide layer is removed which corresponds to the intended area of the vial hole, and the resultant polyimide structure is heated to effect curing. Preferably a positive working resist is used. An alkaline developeer is then applied which etches the first layer of polyimide whilst it develops the resist. The required size of the removed area of the first polyimide layer is achieved by either exposing the resist using an oversized mask or over-etching the edges of the exposed area. Thus it is possible to build up a polyimide insulating layer of substantial thickness using conventional deposition and etching techniques. The pre-curing bake may be achieved by baking at less than 120°C for approximately 30 minutes. The resist stripper used may be a 60/40 N-butyl acetate/isopropyl alcohol. The partial curing bake may be achieved by baking at approximately 200°C for approximately 15 minutes. More than two layers of polyimide may be built up using the techniques outlined above, the size of the area removed from each layer around the intended via hole pattern being less than the area removed from the preceding layer. The present invention also provides a method for assembling a detector provided with a plurality of detector electrodes and a microchannel plate electron multiplier having input and output planes, wherein a layer of polyimide is formed on the surface of the detector, holes are formed in the polyimide layer, each hole overlying a respective electrode, an electrically conductive layer is formed on the surface of the polyimide layer, and the conductive layer is positioned in direct physical contact with the output plane of the multiplier. The present invention also provides an assembly of a detector and a microchannel plate electron multiplier, wherein the multiplier has input and output planes, and the detector is provided with a plurality of detector electrodes, the assembly comprising a polyimide layer overlying the detector and provided with holes each of which registers with a respective detector electrode, and an electrically conductive layer formed on the surface of the polyimide layer, the output plate of the multiplier being in direct physical contact with the conductive layer. The present invention also provides a multidetector comprising a microchannel plate and an array of electrodes arranged to collect electrons. emerging from the microchannel plate, wherein each of the electrodes is in the form of a pair of first and second electrodes, the first electrode being positioned to capture emerging electrons and being biaised to a potential such that energising electrons are not repelled therefrom, and the second electrode being electrically insulated from but capacitively coupled to the first electrode. The first and second electrodes are preferably integrated with the multidetector by forming the second electrodes, depositing a layer of insulating material such as polyimide over the second electrodes, and forming the first electrodes on the insulating layer, Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Pig. 1 is a schematic illustration of a known multidetector electron spectrometer incorporating an electron detection system; Fig. 2 is a schematic illustration of the electron detection system of the known spectrometer illustrated in Fig. ; Fig. 3 is an illustration of a known multiple anode array which is capable of detecting simultaneous events; Fig. 4 is a schematic illustration of a multidetector in accordance with the present invention; Figs. 5, 6 and 7 illustrate processing steps followed in the preparation of the multidetector of Fig.4; Fig. 8 illustrates the input comparator circuit used in the multidetector of Fig. 4; Fig. 9 illustrates waveforms appearing in the circuit of Fig. 8 ; Fig. 10 illustrates the use of a polyimide film as a spacer between the multidetector and the microchannel plate; Fig. 11 illustrates schematically the assembly of a plurality of integrated circuits to form a combined circuit of any required size; Fig. 12 illustrates the use of a further layer of polyimide to form a double electrode structure in a detector of the type illustrated in Fig. 4; and Fig. 13 illustrates a two-dimensional multidetector in accordance with the present invention; Fig. 1 illustrates a comparator stage similar to that of Fig. 8 but provided with individual channel threshold control; and Fig. 15 illustrates waveforms appearing in the circuit of Fig. 14. " Referring to the drawings, Fig. 1 shows a typical known multidetector electron spectrometer. An electron gun 1 produces a stream of electrons having a range of energies and a monochromatic (single energy) beam of electrons is selected by an electron energy selector 2. The monochromatic beam is focussed by an electron lens 3 on a target beam 4. Scattered or emitted electrons are focussed by an electron lens 5 and then dispersed in energy using an electron analyser 6 comprising hemispherical electrostatic deflectors. Traditionally a conventional slit and single detector arrangement was used to scan across the extended electron image the location of which is indicated by dotted line 7. In the known multi-detector however the slit and single detector was replaced by an electron detection system 8 capable of simultaneously detecting electrons having a range of energies. Fig. 2 illustrates the electron detection system 8 of Fig. 1. Input electrons are directed perpendicular to an earthed entry plane of chevron microchannel plates 10. An exit plane of the microchannel plates 10 is held at 2kV. Electrons emerging from the exit plane of the microchannel plates are attracted to a phosphor screen 11 which is held at lOkV. The image appearing on the phosphor screen 11 is focussed by a lens 12 onto a CCD device 13 providing an analogue ouput signal 1. The arrangement of Fig. 2 requires an optical system incorporating either a lens as illustrated or a coherent fibre optic bundle to transport the photon image produced on the phosphor screen to the photosensitive elements of the imaging device. Fig.3 shows an alternative to such an arrangement in which the phosphor screen and optical system is replaced by an array of electrically independent anodes. Referring to Fig. 3, chevron microchannel plates 15 amplify an incoming electron signal 16 and electrons emerge from the exit plane of the microchannel plates 15. The emerging electrons are collected by an array of electrodes (anodes) 17. Each anode in the array is associated with a coupling capacitor 18, an amplifier 19, a discriminator 20 to remove signals resultant from noise and a counter 21. This large amount of external electronics represents a serious drawback to the application of such techniques. Referring now to Fig. 4, a multidetector in accordance with the* present invention is illustrated. The multidetector comprises a plurality of electrodes 22 the purpose of which corresponds to the purpose of the electrodes 17 shown in Fig. 3. Thus each electrode 22 receives electrons from a respective portion of an associated microchannel plate electron multiplier (not shown) . Each channel of the device comprises an amplifier 23 connected to a respective electrode 22, an amplifier/counter interface 24 which incorporates a comparator, and an eight bit counter 25. A scanning shift register 26 incorporates a control bus 27 which controls loading of the content of the counters 25 onto a common data bus 28. A pulse travels along the register 26 at a rate determined by an external clock signal. The time interval between successive readings of the contents of the given counter is selected to be less than the time it takes for the counter to overflow. This depends of course on the rate of arrival of single events at the respective electrodes. Thus data from single electron events is accumulated on-chip as a binary number and read out sequentially at a rate determined by the count rates anticipated in a particular apparatus. This is a particularly important feature when interfacing a multi-detector of this type with a computerised data system (as almost invariably will be the case) since it obviates the need for high speed analogue to digital conversion. The array of electrodes 22 may be fabricated as an extra layer of metalisation laid down on top of an integrated circuit forming the other components referred to in Fig. 4, the extra layer of metalisation being separated from the integrated circuit by an intervening layer of dielectric material. At the centre of each electrode a via-hole is cut through the layer of dielectric material to enable a vertical connection to be made to the input of the amplifier 23. The amplifier ' 23 senses the small quantity of charge (typically 10 6 electrons) deposited on the electrode as a result of the arrival of a single electron on the MCP multiplier. The input charge pulse is then amplified to produce a logic pulse which is subsequently used to drive the digital counter 25. Thus the device illustrated in Fig. 4 not only detects single electron events but also accumulates the resultant data, on chip, in binary counters, one counter being provided for each electrode. The data is then output in a continous self-scanning mode. The amplifier-comparator input stage essentially treats each electrode as an input to a DRAM memory cell and uses a sense amplifier to make a decision as to the presence or absence of an "event". The actual detection of an event is accomplished by means of a charge-sensitive comparator. One of the inputs to the comparator is a discrimination potential which is used for setting a threshold level above which a pulse is registered as having occurred and below which it is assumed that nothing has happened. This effectively discriminates against noise from for example the MCP multiplier. Dielectric materials conventionally used for separating metalisation layers are silicon dioxide and silicon nitride applied by chemical vapour deposition (CVD). These materials are typically of the order of 1 urn thick and have a relatively high dielectric constant, for example up to 10 for silicon dioxide. The consequent high capacitance of capacitors formed as the result of separating two metalised layers by such a material means a reduction in available signal amplitude and hence, loss of electrical sensitivity. In accordance with the present invention it is proposed to overcome these problems by the use of a thick film of polyimide (Pl-polyamic acid) which has a relatively low dielectric constant of 3.5. For a lOum film this represents a 30-fold increase in available signal as compared with a lum film of silicon dioxide. Establishing such a film of polyimide is however not simple. In the arrangement of Fig. 4 the provision of a thick layer of polyimide between the electrodes 22 and various components of the integrated circuit would be of considerable value. As shown in Fig. 4 however this requires the formation of via-holes 29 extending through the polyimide layer to enable connections to be made between the relatively large electrodes 22 and the underlying integrated circuit components. Thick films of PI can be plasma or reactive ion etched after being fully cured using an 0 2 , 0 2 /CF 4 or 0 2 /SF 6 ion species. A non-erodable mask, however, must be applied to the PI and this is essentially a research rather than a production activity. Many masks have been researched in this connection such as CVD oxides, plasma nitrides and a variety of metals. All involve much extra processing to apply and must be subsequently removed without damaging the underlying exposed aluminium. Metal masks, particularly aluminium which is the easiest to use, may be heavily oxidised by the plasma and difficult to remove successfully. Additionally a severe step will be formed at the "shoulder" of the via-hole and this will have to "rounded" to prevent step-coverage problems. Wet processing of thick films also has attendant problems. To achieve cured films of thicknesses much greater than five or six microns in "one-pass" requires the use of sophisticated spraying and curing apparatus. Additionally it must be borne in mind that there is some 75% shrinkage in film thickness during curing implying that a lOum film must be applied some 40um thick. At these thicknesses wet processing is more difficult due to a combination of factors including retained solvents, degree of i idization, the difficulty of penetration by the etchant and removal of solubalised and partially gelled material from the via holes. Multi-layering the PI using simple resist spinning apparatus is an obvious solution but this also presents problems. Unless the primary layers are taken to a sufficiently high temperature the solvent systems of the secondary layers "re-flows" the underlying PI leaving the composite layer little thicker than the initial layer. If the primary layer is taken to a sufficiently high temperature to prevent this from happening it can no longer be wet-etched without recourse to extreme chemistry. A method for overcoming these problems is illustrated in Figs. 5 to 7. The method is capable of rapidly achieving thick films with no complicated processing using only basic clean room equipment. As shown in Fig. 5, a layer 30 of PI on a substrate 32 is spin-coated with resist 31 using a resist-spinner. The substrate 32 supports an aluminium contact 33. The resultant structure is given a pre-cure bake at 120C for 30 minutes. The positive working photo¬ resist is exposed and developed. An alkaline resist developer is used which etches the PI whilst it develops the resist. The crucial step here is that the resultant via holes are made considerably larger than they are required to be to give access to the contacts 33. This is achieved by either exposing the photo¬ resist with an oversized mask or simply over-etching in the developer solution. As shown in Fig. 6, the resist is stripped using a solution of 60/40 n-butyl acetate/isopropyl alcohol as this will not attack the uncured PI. The temperature of the PI is raised to partially cure it and protect it from solvent attack - say 200C for 15m. A second layer 34 of PI is then applied which, because of its planarization properties, will almost completely "fill" the large initial viaε. 16 As shown in Fig. 7, a resist layer 35 is again applied, exposed and developed to produce the correct size via holes in the PI. The resist is now stripped and the PI cure schedule completed. The advantages of the above method are: a) Simplicity and use of commonly available clean room equipment and material. b) Wet-etching gives "rounded" via hole shoulders which give good step coverage for subsequent. metalisation. c) Via hole side-tapering can be easily adjusted--by choice of initial pre-etching bake temperature. Referring now to Fig. 8, details of the amplifier-comparator input stage of the circuit of Fig. 4 are shown. Each electrode 22 is directly connected to the input of a CMOS inverter 36. By periodically switching on a transmission gate this device is dynamically biased into its cross-over region. This "self-biasing" is particularly effective as it affords an automatic means of resetting (discharging) the electrode connected to its input. This single gain stage is capable of fast operation but insufficient gain. Furthermore, its quiescent point does not correspond to a logic level (so level shifting is required) and it cannot discriminate against noise. These difficulties can be overcome by connecting the output of the input stage (which could take different forms from the one described) to a capacitor 37 which is essentially a DRAM memory cell. A similar memory cell 38 is charged by a discriminator potential VREF. Timing waveforms for the circuit of Fig. 8 are shown in Fig. 9. The two memory cells are charged during an INTEGRATE clock pulse. During a SAMPLE clock pulse the electrode is discharged whilst charge from each memory cell is injected into the input nodes 39 and 40 of a DRAM sense amplifier. At the end of the 17 SAMPLE period (which shall be kept short as it represents system dead-time), an EVALUATE pulse turns on the sense-amplifier which registers a HIGH logic level on the node which was connected to the most positive memory cell and a LOW logic level on the other I/O node. The cycle of events is initiated by a PRECHARGE pulse which sets all the circuit nodes to the discriminator potential. It is necessary to bring the sensor array of electrodes into as close proximity as possible with the output plane of the MCP multiplier otherwise mutual repulsion will cause the beam to spread. It is also necessary to provide an electrical contact to this output plane so that a high potential difference can be established between the input plane and the output plane of the channel plates. Both these objectives can be realised by applying an additional thick "spacing" layer of polyimide over the IC after the electrodes have been fabricated. This extra layer has "windows" cut through it to the individual electrodes in the array as shown in Fig. 10. The thickness of this layer determines the spacing between the detector electrodes and the MCP and can be as small as a few microns. Fig. 10 shows a silicon substrate 41 supporting the integrated circuit components, electrodes 22 connected to the integrated circuit through a via hole in the polyimide layer 42, the spacing layer 43, and a window formed over the electrode 22. The surface of the layer 43 is aluminised to make electrical contact with the MCP multiplier. This final metalisation layer 44 makes contact with an aluminium ground pad 45 held at the local ground potential of the IC. The described arrangement is such that the channel plates can be brought into direct physical contact with the multi-detector. An insulating layer (layer 43) electrically separates the MCP multiplier from the electrodes. The surface ' of this layer is metalised to make electrical contact to the channel plates and prevent static electron build up on the chip surface. It is possible to build arbitrarily long detector arrays by juxtaposing individual detector chips on a specially prepared ceramic substrate. Fig. 11 shows a typical example consisting of four detector chips 46- 49 controlled by master chip 50. The master chip,, which makes the device operate as a single entity, is responsible for synchronising events between the detector and the host computer system. The individual chips share a common data bus and so the master chip is also responsible for bus arbitration. It would be possible, however, to dispense with the master _. controller and incorporate its functions onto the detector chips. The key point is that a novel hybridisation scheme is implemented to allow arbitrarily long arrays to be constructed by placing individual detector chips, side by side, on a ceramic substrate so that they function as a single device. The "dead" channels at the common chip boundaries will outut a constant fixed number, say zero, which can be averaged out by a suitable scanning algorithm. In the arrangements described above, detected electrons emerge from the exit plane of a microchannel plate which is at a potential of around 2kV relative to ground. The electrons emerge with low kinetic energy (e.g. lOOeV) and thus, if they are to be collected on the detector electrodes, the electrodes themselves cannot afford to have a lower potential than 2kV or they would repel the emergent electrons. This implies that the detector chip has to "float" at 2kV by means of an isolated power supply. In the arrangements described above, signals and data lines from the chip are processed at real ground. Therefore, they leave the vacuum system by way of multi-way, high voltage, feedthroughs and then undergo opto-isolation to reference them to real ground. This is clearly inconvenient as the multi-way, high voltage, feedthroughs are not "off the shelf" components and the opto-isolation adds complications to a system which claims simplicity as one of its key features. This problem can be overcome by using a dual electrode system as illustrated in Fig. 12. A "top" array of electrodes 51 physically captures the electrons and discharges them to a suitable bias potential via bond pad 52. One way of realising this may be to employ off-chip impedances to sink the current in a known manner. The extra set of electrodes 51 will operate at a high (approx. 2kV) potential and a similar array of electrodes 53, that constitute the inputs to on-chip amplification, are placed directly below these. This latter array is capacitively coupled to, but insulated from, the top array by means of a layer 54 of dielectric material (typically polyimide) that is thick enough to withstand, say, a 2kV voltage drop (25um. for PI). With the possible exception of the impedences which might be integrated as part of a thick film, hybrid substrate, the dual electrode array will be fabricated as a monolithic structure. This structure could be fabricated directly onto the surface of the integrated detector chip as discussed previously and shown schematically in Fig. 12, but it could also be introduced as a "stand alone" capacitor array connected to external components. Referring now to Fig. 13, this illustrates an integrated two-dimensional array in accordance with the present invention, that is an array in which electrodes are positioned in a rectangular pattern defining rows and columns. In contrast to the one- dimensional array of Fig. 4, although each electrode in the array is associated with a respective accumulator, the accumulators are situated on the same chip but remote from the electrodes and the contents of the accumulators associated with one column of electrodes are incremented through a common comparator/adder section. The two-dimensional structure of Fig. 13 comprises an electrode array 55 in which each electrode is represented -by a box 56, the electrodes being arranged in m columns each including n electrodes. The electrode spacing in each of the two dimensions is appropriate to the particular application, but for surface science instruments a resolution (electrode spacing) of 100 microns is appropriate. Such a high density of electrodes limits the complexity of circuitry which can be embedded in the chip adjacent the electrodes as all such circuitry must in effect be located beneath the respective electrode. Thus in the arrangement of Fig. 13 only an amplifier corresponding to the input section 23 of the circuitry of Fig. 4 is located directly beneath the respective electrode. Signals from the amplifier stage are output to an array of comparator/adder stages 57, each comparator/adder being represented by a respective box 58. Each comparator/adder 58 is responsible for sampling signals from the n electrodes of the respective column and for accessing a corresponding column of n RAM memories of a memory array 59. Each RAM memory is represented by a box 60 and can store a binary word the length of which is sufficient to store a count of the events detected at the corresponding electrode. Thus the content of each RAM memory 60 corresponds to the content of the counter 25 in the embodiment of Fig. 4. The memory array 59, the comparator/adder section 57, and the electrode array are all located on the same silicon substrate but are located in physically separate areas of the substrate. In operation, signals for each electrode amplifier in a column are sequentially accessed, the signals representing whether or not a charge pulse ( an event) has been sensed by a particular electrode. No distinction is made between single and multiple events. Thus signals derived from all n electrodes in each column are delivered to the comparator/adder section in n sequential sampling periods. The timing; of each sampling period indicates the origin of the respective signal. The comparator/adder section compares each signal with a reference to distinguish between the occurrence/non-occurrence of an event (1 or 0), accesses the content of the respective memory 60, adds the accessed memory content to the "event count" of 1 or 0, and returns the sum to the respective memory 60. Thus each memory 60 accumulates a count of the events occurring at the respective electrode, the memories 60 of corresponding electrodes in each column being incremented simultaneously. Data is read out to appropriate processing devices via an output port 61. The members in any row of memory elements 60 are simultaneously updated with data from their respective electrodes. Each time such a row is updated the contents of one of the elements is read out. Therefore m sampling periods are required to read out a complete row. As there are n rows the total number of sampling periods is m x n in order to read out the whole array. This approach to data transfer off the chip to associated processing equipment introduces no "dead time" due to data read¬ out. The electrode array will typically occupy about half the available chip surface area. Theoretically very large single substrate arrays could be produced to define for example a sensing surface 2cm by 2cm and including several thousand electrodes. To obtain an acceptably high yield for such a ' large chip might prove difficult and would probably demand the use of fault tolerant design techniques, adding to the complexity and size of the device. An alternative approach would be to combine a number of relatively smaller chips, each containing for example approximately 1000 electrodes. An array of these small chips could then be interconnected on a hybrid substrate using metalized tracks. This could be achieved by firstly covering the array of chips with an insulating layer of for example polyimide, defining contact holes through the insulating layer to contact pads on the chips, and then depositing suitable conductive tracks using standard lithographic techniques. It will be appreciated that the embodiment of Fig. 13 will be implemented using similar techniques to those described with reference to Figs. 4 to 12, the only basic differences in approach being the physical separation of the electrodes and some of the associated circuitry, and the use of time division multiplexing techniques to sample the electrodes and read out data. In the dectector circuit described with reference to Fig. 8, a threshold potential VREF is applied. An identical threshold potential is applied to each of the detector circuits, that is to the circuits associated with every one of the parallel channels in the device. In some circumstances, e.g. device mis¬ matches on silicon dies, it might be desirable to provide different (local) threshold potentials to the different detector circuits, rather than the same (global) threshold potential to all of the detectors. Figs. 14 and 15 illustrate how different local threshold voltages may be provided, the same reference numerals being used for common components in Figs. 8 and 14. The waveforms of 15 are identified in Fig. 14. With the arrangement of Figs. 14 and 15, a sampling period is initiated by the precharge phase which involves shorting together nodes of the sense amplifier in response to the pulse labelled NODCH. During this period the EVAL pulse is active. After this phase the swich labelled INT2 opens and isolates the input inverter 36 from its associated capacitor 37. The switch labelled INT1 now closes and biases . the input inverter to its cross-over point. During the same clock pulse the balancing capacitor 38 is charged to this local cross-over voltage relative to the potential labelled VREF. A reference offset is now applied by pulsing the VREF line. Alternatively the capacitor 38 could be switched between ground and a steady offset voltage.' By briefly closing the SAMPL switch charge is injected into the sense amplifier nodes after which the sense amplifier is activated by the EVAL pulse. The above operation ensures that the reference capacitor C2 is charged to a local reference voltage and then given a fixed offset prior to comparator evaluation. As an alternative to the arrangements illustrated with respect to Figures 14 and 15 it would be possible to provide each channel with a respective threshold potential by providing each channel with an addressable digital to analog converter. A digital word, unique to each channel, could be latched into the digital to analog converter during a set-up phase. The analog output of the converter would then provide the appropriate channel threshold.

Claims: CLAIMS 1. A charged particle multidetector comprising a plurality of electrodes supported on a monolithic substrate, an amplifier in respect of each electrode, the amplifier being supported on the substrate, and means for transferring output signals derived from the amplifier to output terminals adapted for connection to circuitry not supported by the substrate, wherein each amplifier is associated with a respective counter supported on the substrate, means are provided on the substrate for monitoring the outputs of the amplifiers to detect the arrival of a charged particle at the respective electrodes, means are provided on the substrate to increment the content of each counter in response to detection of the arrival of a charged particle at the respective electrode, and the transferring means comprise means for periodically reading out the accumulated contents of each counter to the output terminals. 2. A multidetector according to Claim 1, wherein the monitoring means comprises means for detecting when the output of any amplifier exceeds a predetermined threshold, and the incrementing means comprises means for incrementing the respective counter each time an amplifier output exceeding the predetermined threshold is detected. 3. A multidetector according to Claim 2, wherein a monitoring means comprises a comparator. . A multidetector according to Claim 3, wherein the amplifier and comparator circuits comprise an inverter connected to receive the output of one electrode, a transmission gate connected in parallel with the inverter, a capacitor connected between the output of the inverter and a stable voltage source, a reference capacitor one terminal ' of which is connected to a stable voltage source, a sense amplifier connected between the output of the inverter and a second terminal of the reference capacitor, and switches for alternately connecting inputs to the sense amplifier to the respective ones of the capacitors and to a common voltage source, means being provided to close the transmission gate when the sense amplifier is connected to the capacitors. 5. A multidetector according to any preceding claim, wherein each electrode is connected to a respective amplifier located beneath the electrode on the substrate. 6. A multidetector according to Claim 5, wherein each amplifier is connected to a respective counter located adjacent the respective electrode on the substrate. 7. A multidetector according to Claim 5, wherein a plurality of electrodes are connected to a respective adder located remote from the said plurality of electrodes, means being provided to sequentially sample the outputs of the amplifiers associated with the plurality of electrodes, and the adder being arranged to sequentially increment counters located on the substrate remote from the electrodes each of which counters is associated with a respective one of the plurality of electrodes. 8. A multidetector according to any preceding claim, wherein the electrodes are in the form of metal pads supported on a layer of polyimide formed over the amplifiers supported on the substrate, connections being made between the electrodes and the amplifiers through via holes formed in the polyimide layer. 9. A multidetector according to Claim 8, wherein the polyimide layer and via holes are formed by depositing a first layer of polyimide on the substrate, heating the layer to effect precuring, applying a layer of photoresist to the first layer of polyimide, exposing and etching the photoresist to remove areas of the first polyimide layer corresponding' to the intended positions of the via holes, the removed areas being larger than the intended areas of the via holes, heating the first layer of polyimide to effect partial curing, depositing a second layer of polyimide over the first layer and the etched areas, applying a second layer of photoresist to the said layer of polyimide, exposing and etching the photoresist to remove areas of the second polyimide layer corresponding to the intended positions of the via hole, the etched areas corresponding to the intended areas of the via holes, and heating the resultant structure to cure the remaining polyimide. 10. A multidetector according to any preceding claim, wherein the electrodes are located adjacent an output plane of a microchannel plate, a spacing layer of polyimide provided with openings registering with the electrodes being located over the substrate so as to be sandwiched between the microchannel plate and the substrate supporting the electrodes, and the surface of the spacing layer supporting an electrically conductive layer in direct contact with the microchannel plate and connected to a terminal held at ground potential. 11. A multidetector according to any preceding claim, wherein each electrode comprises a pair of first and second electrodes separated by an insulating layer, the first electrode being exposed to charged particles to be detected and connected to a source of bias potential, and the second electrodes being positioned beneath respective ones of the first electrodes and connected to the amplifiers, whereby the first and second electrodes of each pair are capacitively coupled together. 12. A method for forming a thick polyimide film around a via hole extending through the film, wherein a first layer of polyimide is deposited on a substrate, the first layer is heated to effect precuring, a first layer of photoresist is applied to the first layer of polyimide, the photoresist is exposed and etched such that an area of the first polyimide layer is removed which is substantially larger than the intended area of the via hole, the resist is stripped from the first layer, the first layer is heated to effect partial curing, a second layer of polyimide is deposited over the first layer and the etched area, a second layer of resist is applied to the second layer of polyimide, the second layer of resist is exposed and etched such that an area of the second polyimide layer is removed which corresponds to the intended area of the via hole, and the resultant polyimide structure is heated to effect curing. 13. A method according to Claim 12, wherein a positive working resist is used, and an alkaline developer is then applied which etches the first layer of polyimide whilst it develops the resist. 14. A method according to Claim 12 or 13, wherein the precuring is achieved by baking at less than 120°C for approximately 30 minutes. 15. A method according to Claim 14, wherein a 60/40 N-butyl acetate/isopropyl alcohol resist stripper is used. 16. A method according to Claim 15, wherein the partial curing is achieved by baking at approximately 200°C for approximately 15 minutes. 17. A method for assembling a detector provided with a plurality of detector electrodes and a microchannel plate electron multiplier having input and output planes, wherein a layer of polyimide is formed on the surface of the detector, holes are formed in the polyimide layer, each hole overlying a respective electrode, an electrically conductive layer is formed on the surface of the polyimide layer, and the conductive layer is positioned in direct physical contact with the output plane of the multiplier. 18. An assembly of a detector and a microchannel plate electron multiplier, wherein the multiplier has input and output planes, and the detector is provided with a plurality of detector electrodes, the assembly comprising a polyimide layer overlying the detector and provided with holes each of which registers with a respective detector electrode, and an electrically conductive layer formed on the surface of the polyimide layer, the output plane of the multiplier being in direct physical contact with the conductive layer. 19. A multidetector comprising a microchannel plane and an array of electrodes arranged to collect electrons emerging from the microchannel plate, wherein each of the electrodes is in the form of a pair of first and second electrodes, the first electrode being positioned to capture emerging electrons and being biased to a potential such that energising electrons are not repelled therefrom, and the second electrode being electrically insulated from but capacitively coupled to the first electrode. 20. A multidetector according to Claim 19, wherein the first and second electrodes are integrated with the multidetector by forming the second electrodes, depositing a layer of insulating material such as polyimide over the second electrodes, and forming the first electrodes on the insulating layer. 21. A multidetector substantially as hereinbefore described with reference to Figures 4 to 13 of the accompanying drawings. 22. A method for manufacturing a multidetector substantially as hereinbefore described with reference to Figures 4 to 13 of the accompanying drawings.

Inventors: HATFIELD JOHN VERNON, HICKS PETER JOHN, HATFIELD, JOHN, VERNON;, HICKS, PETER, JOHN;
Applicants: UNIV MANCHESTER, THE UNIVERSITY OF MANCHESTER INSTITUTE OF SCIENCE
Application year: 1989
Main classification: H01J49
IPC codes: G01T1, H01J49