SIGNAL PROCESSOR

Abstract: Use is made of two A/D conversion systems of low accuracy to obtain digital output signals maintaining higher conversion accuracy than that of only one A/D conversion. By using two D/A conversion systems of low accuracy, furthermore, analog output signals are obtained maintaining higher conversion accuracy than that of only one D/A conversion system. Provision is further made of digital signal clock conversion means for forming second digital data in synchronism with second clocks by the interpolation processing based on the data obtained by highly sampling first digital data series and a difference between the first clock timing and the second clock timing. Using two PCM.CODEC's (54, 55) and one DSP which are cheap and small in size, A/D and D/A conversions are realized maintaining high accuracy. Therefore, the signal processing that was so far carried out using a large-scale analog circuit is now carried out easily using one DSP. In this case, furthermore, the digital signal clock conversion means is realized in the same DSP as the digital signal processing.

Description: The present invention relates to a signal processing apparatus for performing a coding/decoding and other processes on digital PCM signals, for example, by combining a PCM.CODEC and a DSP (Digital Signal Processor), and more particularly, to a technology for realizing a practical signal processing in DSP by using equivalently high precision and inexpensive A/D or D/A converters. A signal processing apparatus according to the preamble of claim 1 is known from Patent Abstracts of Japan Vol. 97, E373, referring JP-A-60 143023. Background Technology The signal processing apparatus performs a coding/decoding and other processes, for example, on digtal PCM signals. There are representative apparatuses, an A/D converter for performing a coding between an analog telephone band signal on a subscriber line and a digital PCM signal on a relaying line, and a D/A converter for performing a decoding therebetween. Generally speaking, when an analog signal is converted to a digital signal on a receiving side, it is first sampled at predertermined intervals by using respective sampling signals, and then quantized with regard to respective sampling signals. Quantizing is executed to predivide the amplitude level of the analog signal into a plurality of ranges so that the analog signals within certain ranges can be represented by a corresponding representative digital value. The resulting quantized signal is transmitted on a transmission line as digital PCM signal coded. On the receiving side, the digital PCM signal is reconverted to an analog signal and reproduced as a telephone signal such as a human voice. During the quantizing process, a certain range of analog signals can be expressed by the same code, even if sampled values vary to some extent, and on the receiving side the sampled value within the range can be decoded as an analog signal of the same amplitude. Therefore, there may be a substantial difference, between an analog signal before coding and an analog signal after decoding. This difference is called quantization noise. The signal to quantizing noise ratio (S/N) is used to evaluate the quality of the communicated signal. The range presented by one code is called a quantizing step, and when the quantizing step is uniform, quantizing noise is constant. Therefore, if the signal, namely, the amplitude of the analog input is large, S/N is high, and if it is small, S/N is low. However, for good communication quality, S/N should be maintained constant regardless of the above amplitude. A nonlinear quantization in which the quantizing step is made small for an analog input with a small amplitude, and large for an analog input with a large amplitude, is generally adopted. This is called companding. To produce good companding characteristics for a nonlinear quantization of a telephone signal, a companding rule called µ-law is adopted in Japan and the United States, and a companding rule called A-law is adopted in other areas, including Europe and parts of Asia. Recently, 8 bit companding A/D or D/A converters for performing a signal conversion based on the above companding rule have been produced by many makers. Although their structures are complicated, they are relatively inexpensive. The ICs are generally called "PCM.CODEC." (PCM coder/decoder). On the other hand, when data transmission other than voice signals is conducted by using a telephone band signal, a signal processing circuit such as an equalizer, an attenuator or a balancing network is redundant when combined with a converter such as a PCM.CODEC. These circuits are conventionally constructed as analog circuits. On a coding side they are provided in a stage before an A/D converter, and on a decoding side in a stage after a D/A converter. Fig.1 shows a conventional digital PCM channel apparatus which can be realized as a combination of the above circuits and a PCM.CODEC. PCM.CODEC 1 comprises an A/D converting unit including a low-pass filter (LPF) 7 and an A/D converter 8, and a D/A converting unit including a D/A converter 10 and a LPF 11. A/D converter 8 and D/A converter 10 conduct data conversion based on 8-bit µ-law companding. LPFs 7 and 11 limit the frequency range of the analog signals which are respective input/output signals, to a frequency band which can be expressed by a sampling frequency, namely they are law pass filters for limiting a frequency band up to 1/2 the sampling frequency. As described above, PCM.CODEC 1 integrally forms a low-pass filter in a chip. As a result the cost of coding/decoding portions can be reduced. Hybrid transformer 3 divides an analog telephone band signal (analog data) transmitted on a 2-wire subscriber line 2 into a transmitting signal and a receiving signal. Equalizers 4 and 13 correct the loss of frequence characteristics of signals in 2-wire subscriber line 2 or 4-wire tansmission path 9 within a telephone band. Attenuaters 6 and 12 correct the signal level loss caused during propagation along a line. Balancing network 15 adjusts the impedance of hybrid transformer 3 in order to reduce leak (echoback) of signals from the receiving side to the transmitting side, the leak being caused by an impedance mismatching in hybrid transformer 3. Amplifiers 5 and 14 adjust the signal levels. Setting and controlling of the above circuits is conducted electrically by a remote control of a center (station) not shown, as designated by the dotted line in Fig.1. This control is generally called a remote provision. The above circuits 4,6,12,13 and 15 are important circuits which are necessary for increasing the communication quality. However, when they are analog circuits, they are large and the cost of the apparatus as a whole becomes high. Provision for remotely setting a plurality of analog circuits becomes complicated. However, DSPs (Digital Signal Processor) have started to become widely used in various fields, and LSIs of DSPs can be obtained at a low price. The performance of DSPs has increased annually, and a circuit portion subjected to a conventional analog process is replaced by a DSP process. This is also because the scale of the hardware can be reduced by a DSP process. Use of a DSP suppresses the effect of deviations caused among various kinds of products and in the manufacturing process, to a minimum value, although the deviations in the manufacturing process have a large effect on products in an analog circuit. Further, only a modification of an installed firmware can facilitate a change in a process operation. Based on this technology, units conventionally subjected to an analog process are replaced by a DSP in the field of telephone band signal processing. Namely, it is desired that the aforementioned equalizer, attenuator, and balancing network be replaced by a DSP. Fig.2 shows the structure of a digital PCM channel apparatus, in which the process of the above respective circuit is conducted by a DSP. In Fig. 2, portions designated by the same reference numbers as in Fig. 1 perform the same function as the portions in Fig. 1. As shown in Fig. 2, DSP 16 is provided on the digital signal side of PCM.CODEC 1, and the same function as the impedance control of hybrid transformer 3, which is conducted in balancing network 15 in Fig.1, can be realized by DSP16. Therefore, the impedance of hybrid transformer 3 is fixed at a constant value as is conceptually represented by resistance value R in Fig. 2 and an occurrence of signal leakage is allowed. Coarse attenuators 17 and 18 perform a rough adjustment of signal level in the 3dB range of analog signal, and also have a preprocessing function. As shown in Fig. 2, DSP 16 is preferably combined with PCM.CODEC1 which is available at a low cost. However, mere combination of DSP1 and PCM.CODEC 1 cannot realize a coder and decoder apparatus with a desired performance. This is because of the recited S/N ratio. According to a µ-law companding by PCM.CODEC, a digital signal coded on a transmitting side is transmitted to a receiving side through a transmission path without suffering any modification, and is decoded on the receiving side following the same companding rule as on the transmitting side and the µ-law companding is a kind of code conversion rule determined based on the above condition. Therefore, when DSP processing is applied to a digital signal after an A/D conversion, a quantizing noise instinctively occurring only upon coding is also produced upon decoding. Thus, in order to raise the communication quality the number of quantizing bits must be made as large as possible, and the respective quantizing steps made as small as possible, thereby suppressing quantizing noise to a minimum value. Most currently available PCM.CODECs perform an eight bit quantization, and the accuracy of this quantization is relatively low. Therefore, there is a problem that deterioration of communication signal S/N cannot be avoided if a PCM.CODEC currently on market is merely combined with a DSP. In order to solve the above problem of S/N deterioration, consideration is given to use of a quantization apparatus with a smaller quantizing step than an 8-bit quantizing apparatus, which can maintain the same step size up to a high level, as a converter corresponding to A/D converter 8 and D/A converter 10 in Fig. 2. For example, use of a linear converter performing 16 bit linear quantization can be considered. A linear converter for about 15 bits may be sufficient, depending on the degree of signal processing performed by the DSP but, considering that PCM.CODEC based on the 8 bit µ-law companding has a resolution which is similar to that of a 14-bit linear converter, a resolution of about 16 bits may be necessary. An A/D and D/A converter having a high resolution such as 15 or 16 bits has a more complicated circuit and a larger scale than PCM.CODECs currently on the market. Therefore 16 or 15 bit A/D or D/A converters are extremely disadvantageous in respect of cost. Further, a PCM.CODEC is installed with a low-pass filter and the above-recited linear converter with a high resolution does not have such filter. Thus, it has to be provided with a new low pass filter, thereby causing a great cost increase and increasing the chip area. Next, where a digital PCM channel apparatus is constructed by combining the A/D and D/A converter with the DSP, a technology considered to enable a DSP to perform processing similar to the aforerecited equalizer, attenuator and balancing network, as explained below. A general structure considered as a digital PCM channel apparatus based on the above structure will again be shown in Fig. 3. Here, hybrid transformer 21, A/D converter 23 and D/A converter 24 perform the same functions as those represented by the reference numbers 3, 8 and 10, respectively, in Fig. 2. The impedance of hybrid transformer 21 can be maintained constant, as in Fig. 2. 2-wire subscriber 20 and 4-wire transmission path 30 are also similar to those represented by the reference numbers 2 and 9 in Fig. 2. Preprocessing circuit 22 is shown by including amplifier 5, coarse attenuator 17 and LPF 7 in Fig. 2 and post-processing circuit 25 is represented by combining LPF 11, coarse attenuator 18 and amplifier 14 of Fig. 2. Although it is abbreviated in Fig. 2, it sometime performs the process of emphasizing a high frequency component of an analog signal in order to raise the quality of a communication signal. In contrast, post-processing circuit 25, in some cases, performs a process in which characteristics of signals emphasized on the transmitting side return to the appropriate process. In Fig. 3, input signal SIN converted to digital data by A/D converter 23 and receiving PCM signal RIN from 4-wire transmission path 30, is input to DSP 19. In DSP 19, transmission level setting equalizer 27 and receiving level setting equalizer 28 are realized as firmware and perform the same operation as equalizers 4 and 13, and attenuators 6 and 12 in Fig. 1. Namely, with regard to the above input signal SIN and receiving PCM signal RIN, a loss of frequency characteristics of signals on 2-wire subscriber line 20 or 4-wire transmission path 30 is accurately corrected within a telephone band, and a loss of signal level caused by a line is accurately corrected. At this time a part of a signal advanced from post-processing circuit 25 to subscriber line 20, is turned to input DSP 19 through hybrid transformer 21 such that it is included in input signal SIN making it necessary for the component entered into DSP 19 to be cancelled. Therefore, the above component is produced from receiving output signal ROUT in precise balance circuit 29, and this is added to input signal SIN at adder 26 (actually, this is substraction) thereby cancelling the above component. This process is performed to obtain a difference between received output signal ROUT i.e. a receiving system signal, and input signal SIN i.e. a transmitting system signal, and to bridge a receiving system and a transmitting system. A digital transmission system including the digital PCM channel apparatus of Fig. 3 has a transmission speed of , for example, 64 Kbit/sec and operates in synchronization with an 8KHz clock. As far as it is not a complete dependent synchronization network, in Fig. 3 a receiving system circuit such as D/A converter 24 operates in synchronization with a receiving clock extracted from received PCM signal RIN and a transmitting system circuit such as A/D converter 23 operates in synchronization with a transmitting clock produced within a channel apparatus not shown. In this case, a receiving clock is obtained by dividing a master clock of the other terminal station, and a transmitting clock is formed by dividing a master clock of the own station. Therefore, both transmitting and receiving clocks have an indicated frequency of 8KHz but, as they do not use the same master clock, their frequencies are slightly different in practice, and this difference is around 10 -4 at the maximum. The difference of 10 -4 means that, when transmitting system data is input 10000 times, the receiving system data becomes 10001. This results in sampling timings of received PCM signal RIN and input signal SIN, which are input to DSP19, always differing slightly. Therefore, even if a receiving signal component included in input signal SIN is intended to be cancelled by an output from precise balance circuit 29 to which a receiving PCM signal RIN is input into adder 26, the signals at different times are subjected to the addition and thus the desired result is not obtained. Moreover, when the difference is 10 -4 at 8KHz clock, data out running phenomenon occur at a rate of 1 timing per 1.25 seconds. Thus, the data at the time is lost. Therefore, it is necessary to match one clock with the other clock. In this case, receiving PCM signal RIN is a signal which has already been sampled on the transmitting side and the receiving clock thereof already exists on the transmitting side. In order to receive received PCM signal RIN, the receiving clock is needed. Thus, the receiving clock is used as a transmitting clock. Received PCM signal RIN comes from a transmitting terminal station through many repeater or relay stations. Thus, some jitter is added to the receiving PCM signal RIN through respective stations. Therefore, received PCM signal RIN already includes large jitter. Thus, if it is used as a transmitting clock it is transmitted through many relays before it reaches the other terminal station, and thereby increases the amount of jitter, greatly deteriorating the communication quality. Therefore, when a clock generator is provided in both terminal stations and it is intended to maintain the same communication quality, as in the case where these clock generators are designed to synchronize accurately with each other, the distance which causes jitter becomes the distance of going and returning, namely twice the one-way distance. Therefore, the relay distance is limited to 1/2 the ordinary relay distance. An echo canceler cancels echo signals included in transmitted signals, the echo signals being formed by signals advancing to a subscriber through hybrid transformer 21 being turned back. The echo canceler produces suitable replica echo signals based on received signals, and subtracts them from the signal being transmitted. This performs a process of bridging a transmitted signal and a received signal, thereby causing a problem similar to the above case. To solve the above problems, a digital-signal clock-changing method is necessary. In this method, a digital PCM channel apparatus as shown in Fig. 3 operates D/A converter 24, A/D converter 23 and precise balance circuit 29, in synchronization with a receiving clock. This enables a transmitting signal obtained from these signals to again be synchronized with a transmitting clock generated by the clock generator of the own station. The transmitting signal is thereby produced as output signal SOUT. In this case, it is preferable to achieve good communication quality and to be able to miniaturize the apparatus. Fig. 4 shows a block diagram of a conventional clock changing method. In Fig. 4, the first clock system digital data 34 are converted to analog data by D/A converter 31 which operates in accordance with the first clock 35. Then, after the analog data is converted to data which is continuous with time, through analog low pass filter 32, the output from low pass filter 32 is converted to the second clock system digital data 37 by A/D converter 33 which operates at the second clock 36, thereby achieving a clock changing. However, in the apparatus shown in Fig. 4, input digital data is reconverted to analog data by D/A converter 31 and the analog data is again converted to digital data by A/D converter 33, thereby resulting in a production of a quantizing noise, and deteriorating the communication quality. There is a further problem, that the apparatus shown in Fig. 4 needs an analog low pass filter 32 which, unlike a digital circuit, cannot be miniaturized even if it is integrated. Disclosure of the Invention The present invention is made in consideration of the above situation and its first object is to provide a high precision A/D and D/A converter by combining a PCM.CODEC of a low conversion precision and an inexpensive A/D and D/A, thereby providing a high precision A/D and D/A converter and realizing a practical signal processing within the DSP. This object is solved as defined in claim 1 and in claim 4. To achieve the above object, the present invention provides an A/D converting means for shifting an amplitude value of an analog input signal and individually performing a conversion of the analog input signal. This is done by using respective first and second A/D converters and arithmetically operating an average value of respective conversion results. Thus, it provides higher conversion precision digital output signal than a single A/D converter. The first A/D converter systme of the A/D converter means comprises, for example, first amplifier 38, first companding A/D converter 39, and first linear converter 42, as shown in Fig. 5. The second A/D converter system comprises, for example, a second amplifier 40, second companding A/D converter 41, and second linear converting unit 43, as shown in Fig. 5. The above arithmetic operation of the average value can be conducted by an arithmetic operation unit 44, for example, as shown in Fig. 5. Next, the present invention individually converts digital input signals by first and second D/A converter systems, detects a quantizing error caused by the first D/A converter system, adds the quantizing error to a digital input signal input to the second D/A converter system and mixes the respective conversion results of the first and second D/A converter systems in a predetermined ratio. Thus it provides a higher conversion precision analog output signal than a single D/A converter system. The first D/A converter system in the D/A converter means comprises a first companding converting unit 45 and first companding D/A converter 49, for example, as shown in Fig. 6, and the second D/A converting system comprises second companding converting unit 46 and second companding D/A converter 50, for example, as shown in Fig. 6. Quantizing error from the first D/A converting system is detected by detecting unit 49, for example, as shown in Fig. 6 and is added to the second D/A converter system by using noise adding unit 48. The respective conversion results of the first and second D/A converter systems are mixed in a predetermined ratio by the first and second amplifier 51 and 52 and adder 53, for example, as shown in Fig. 6. The structure of the above invention is realized, for example, by two PCM.CODECs and one DSP as a coding/decoding apparatus for a digital PCM signal. Namely, the A/D converting means and the D/A converting means can be realized by using a portion of a function of two PCM.CODECS and one DSP which perform 8-bit companmding coding and decoding. Therefore a small inexpensive structure comprising two PCM.CODECs and one DSP can realize high-precision A/D and D/A converting processing. Therefore, signal processing devices such as an attenuator, an equalizer and a balancing network, which are conventionally realized by an analog circuit, can be realized by digital signal processing using one DSP. As shown above, the present invention can perform high precision A/D and D/A conversion with ease by using a signal processing apparatus formed by an inexpensive PCM.CODEC and a DSP. It can therefore perform with one DSP a signal processing, which conventionally necessitates a large scale analog circuit. In addition, it can realize a digital-signal clock-changing means necessary for signal processing by using a signal processing in the same DSP. Therefore, the present invention can integrate an appratus while maintaining a high communication quality, thereby extremely miniaturizing the whole apparatus, and can realize an inexpensive, low-energy consuming, highly reliabile signal-processing apparatus. Brief Description of Drawing Fig. 1 shows a structural view of a conventional example of a digital PCM channel apparatus; Fig. 2 shows a structural view of the example which is generally used for a digital PCM channel apparatus; Fig. 3 shows a structural view of the example which is generally used for a digital PCM channel apparatus; Fig. 4 shows a structural view of the conventional example of the clock changing apparatus; Fig. 5 shows a basic structural view of an A/D conversion apparatus according to the first embodiment; Fig. 6 shows the basic structure of a D/A conversion apparatus according to the first embodiment; Fig. 7 is a table which details the relationship between various numerical values under general µ-law; Fig. 8 is a table which details the relationship between values of various portions in an A/D conversion apparatus; Fig. 9 shows a view for explaining the operation of an A/D conversion apparatus; Fig. 10 shows a view for explaining the operation of a D/A conversion apparatus; Figs. 11A and 11B are tables which detail the relationship between values of various portions of a D/A conversion apparatus; Fig. 12 is a detailed block diagram of a preferred structure of an A/D and D/A conversion apparatus according to the first embodiment; First Embodiment Firstly, the first embodiment will be explained. This embodiment is characterized in that the accuracy of A/D and D/A conversion are improved by using two sets of PCM.CODECs based on 8-bit µ-law companding. Fig. 5 shows the basic structure of an A/D converting apparatus according to the first embodiment of the present invention. In Fig. 5, analog signal A in is commonly applied to the first and second A/D converting systems. In the first A/D converting system, the signal A in is amplified k1 times in first amplifier 38 and is converted to the first PCM code P1 by the first companding A/D converter 39. In the second A/D converting system, signal A in is amplified k2 times in the second amplifier 40, and is further converted to the second PCM code P2 by the second companding A/D converter 41. k1 and k2 are real numbers satisfying the relationship k1 x k2 =1. At least first linear converting unit 42, second linear converting unit 43 and arithmetic operation unit 44 are formed in the DSP. First and second linear converting units 42 and 43 convert respective first and second PCM codes P1 and P2 into first and second linear codes L1 and L2. Arithmetic operation unit 44 performs an arithmetic operation on these linear codes L1 and L2 to derive an average value (L1 +L2)/2, and this average value becomes digital conversion output D OUT . As will be recited later by referring to Fig. 12, processes based on functions of the precise balance circuit, equalizer, and attenuator are applied to the digital conversion output. Fig. 6 shows the basic structure of the D/A converting apparatus relating to the first embodiment of this invention. In Fig. 6, after the above respective processes are performed in the DSP (later recited in Fig. 12) digital signal D in , input as a linear PCM code, is applied to first companding conversion unit 45 and is converted to the third companding PCM code P3. The third companding PCM code P3 is input to the first D/A converting system. This system comprises first companding D/A converter 49 for converting code P3 to the third analog signal A1, and third amplifier 51 for amplifying the signal A1 k3 times. At least second companding converting unit 46, detecting unit 47 and noise adding unit 48 are formed in the DSP in addition to converting unit 45. Detecting unit 47 detects a quantizing noise N in the third companding PCM code P3. Detecting unit 47 comprises linear converting unit 47-1 and subtracting unit 47-2 in Fig. 6. Quantizing noise N is applied to noise adding unit 48. It is then multiplied by k4 and added to digital signal D in . In Fig. 6, noise adding unit 48 comprises amplifying unit (gain k4) 48-1 and adding unit 48-2. The output of noise adding unit 48 is converted to the fourth companding PCM code P4 by second companding converting unit 46. The code P4 is input to the second D/A converting system. This system comprises the second companding D/A converter 50 which converts code P4 to the fourth analog signal A2, and fourth amplifier 52 which amplifies the signal A2 k5 times. The relations between k3, k4 and k5 are determined to satisfy the conditions k3 + k5 = 1, and k4 = k3/(1 - k3), where k3, k4 and k5 are all positive real numbers. Respective amplification outputs of the third and fourth analog signals, A1 and A2, obtained by the above process are added at adder 53, thereby producing analog conversion output A out . An operation of the first embodiment shown in Figs. 5 and 6 will be explained. Firstly, the A/D converting apparatus of Fig. 5 is explained. Supposing that the amplification ratio k1 of the first amplifier 38 satisfies k1 = k (therefore, the amplification ratio k2 of the second amplifier 40 satisfies k2 = 1/k) and that the amplitude of analog signal A in is α. The signal A in is amplified to provide αk and α/k, which are applied as input to corresponding companding A/D converters 39 and 41, thereby providing the first and second PCM codes P1 and P2 of digital values. These PCM codes are subjected to companding and are not real numerical values. Therefore, the PCM codes cannot be a subject of a computation and they are modified. Therefore these codes are returned to linear codes L1 and L2 representing the real numerical value by linear converting units 42 and 43. In this state, arithmetic operation unit 43 performs an arithmetic operation to obtain an average value (L1 + L2)/2. As described in detail later, in addition to a group of 255 or 256 output values which may be output as 8 bit companding CODEC, an intermediate value within two adjacent output values may be produced from the average value, thereby resulting in an increase in the kinds of output values. This means an increase in the resolution of the A/D converter. The reason is that the linear codes L1 and L2 differ from each other because of the multiplication ratio of k and 1/k and, if L1 is the same value L as L2, then the value L is the output value and, if L1 deviates from L2, the intermediate value between L1 and L2 appears as the output value. The above operation will be explained in more detail by referring to an example. In the A/D converter of Fig. 5, the amplification ratio k1 of the first amplifier 38 is set at K (=1.01), and the amplification ratio k2 of the second amplifier 40 is set at 1/k(=1/1.01). An explanation of this embodiment adopts a µ-law as an example of a companding rule. Even in case of an A-law, the effect of the present invention does not differ. Fig. 7 shows a relation between respective values under a general µ-law. In Fig. 7, the voltage range of the analog input (a column of linear input in the drawing) added to companding A/D converters 39 and 41 of Fig. 5 is set, for example, -8158 to +8158 and 2 8 (=256) times the output value (OUTPUT VALUE) are set within the input analog voltage range. The unit of the analog input voltage is, for example, milli-volts. In accordance with the respective value of the analog inputs (linear inputs in the drawing), an 8-bit digital code is determined as a µ-law PCM output, and it outputs from the A/D converter. In Fig. 7, to simply recite an explanation, only positive linear input is shown, only the complete fourth segment is recited and intermediate values in the other segments are omitted. The segment means a range of respective bent lines when a µ-Faw characteristic is expressed by a plurality of bent lines and quantizing steps are constant in respective ranges. An 8-bit digital code of the above µ-law PCM output is simply a symbol used for a classification and does not mean an actual amplitude value. Therefore, the above µ-law PCM output is converted to the corresponding digital value of 0 to 8031 (which corresponds to the output value (OUTPUT VALUE) in Fig. 7) by first and second linear converting units (µ/L converting units) 42 and 43 in the DSP of Fig. 5. Thus, the digital value has 14-bit accuracy. As the first and second linear codes L1 and L2 of Fig. 5, numerical data corresponding to αk and α/k appear, as explained above. For an 8-bit companding A/D converter, the kind of respective output level of the linear codes L1 and L2 are respectively merely of 255 or 256 types. However, the actual analog inputs are a continuous value within the range of -8158 to +8158, and the number of kinds of analog inputs is 16316 even when the integer portion only is considered. Because of the difference between the kinds of output levels of first and second linear codes L1 and L2 and the continuous value of analog input, a quantizing noise as described above occurs. Generally speaking as an evaluation item of an A/D converter and a D/A converter the above recited S/N (in units of dB) is used. For example, for an 8-bit companding A/D (D/A) converter for a telephone signal, the output obtained by inputting a sine wave signal of 1010Hz to the A/D converter is input to the D/A converter. The D/A converter provides output including a signal component, namely, a signal of 1010Hz. This signal component, represented by an "S" frequency component other than the 1010 Hz included in the output from the D/A converter, is represented by N (noise). A large part of the noise comprises quantizing noise caused by representing a certain range of analog input by an output value formed by the central value of the analog input. Therefore, a large S/N means a small quantizing noise and a small waveform distortion. In other words, to increase S/N it is necessary to decrease quantizing noise, and to decrease quantizing noise it is necessary to increase the output value from the A/D (D/A) converter and to thereby decrease the length of the quantizing steps. According to the embodiment shown in Fig. 5, use of two sets of 8-bit companding A/D converters 39 and 41 enables the above output value to increase as shown below. Further, use of a commercially available PCM.CODEC enables a signal processing apparatus to be realized at a lower cost than with one set of higher quantizing precision (or more than 8-bit) A/D converters, even if two sets of 8-bit companding A/D converters 39 and 41, are utilized. In Fig. 5, the output value of the first and second linear codes L1 and L2 are respectively D(α·k) and D (α/k). If k is not determined as k=1.01, but as k =1 , the linear codes L1 and L2 naturally have the same output value. As is shown in the preferred embodiment, if k=1.01, the first amplification ratio 1.01 is slightly different from the second amplification ratio 1/1.01. Thus, αk becomes different from α/k. If the difference between αk and α/k is small and αk and α/k is within a range of respective rows shown in a column of a linear input shown in Fig. 7, the output value D (α·k) is coincident with that of D (α/k). In contrast, if the difference between αk and α/k is outside the range of repsective rows, the output D (α·k) is different from that of D(α/k). Namely, where k≠1 but is a value near 1, or where one of them is entered into the adjacent range, the output value corresponding to the adjacent range is produced and D(α·k)≠D(α/k). In the former ( coincidence) an average value of αk and α/k, namely, 1/2 x α{(k+1/k)} is positioned near the center of the range of respective rows of the linear input shown in Fig. 7. In the latter ( non-coincidence) the above average value appears near the boundary between adjacent ranges of respective rows. In the arithmetic operation unit 44 in Fig. 5, the average value of the first and second linear codes L1 and L2 is set at D out =1/2{(D(α·k)+D(α/k)} through an arithmetic operation, and in the latter case explained above, the output D out becomes an intermediate value between the output value of one row and that of its adjacent row. In the former case, namely, when α · k and α/k are within the same range, L1 and L2 become the same, thereby enabling the average value of L1 and L2, or the output D out to become the same value as the respective output value. The output value shown in the column of the output value (OUTPUT VALUE) in Fig. 7 and a new output value mid-way between adjacent output values are obtained, thereby achieving the same result as a high resolution A/D converter. Fig. 8 shows the relationship among respective values in an A/D converter and shows concrete numerical values of an amplitude α of analog signal A in , output value αk of the first amplifier 38, output value α/k of the second amplifier 40, D(αk) which is the value of the first linear code L1, D( α/k) (the value of the second linear code L2), and 1/2{D(α·k) + D(α/k)} which is digital conversion output D out with regard to the apparatus shown in Fig. 5. It should be noted in Fig. 8 that, as shown on the right side, the output values shown by Q1, Q2, Q3 and Q4 appear as new output values in addition to ordinary quantizing output values Q2', Q3' and Q4' of companding A/D converters 39 and 41. Their relationship is shown more comprehensively in Fig. 9. Respective ones of Q2', Q3' and Q4', for example, in Fig. 9 correspond to those in Fig. 7. With regard to D(α·k) and D(α/k), if α is positioned within a region A, quantizing output of the above two values is commonly Q3'. Thus, the digital conversion output D out is also Q3', and if α is positioned in a region B, the respective quantizing outputs are divided into two parts Q4' and Q3'. Thus, the digital conversion output D out becomes an intermediate value, Q3. In a case where α is positioned in the region C, respective quantizing outputs are divided into Q3' and Q2'. Thus, the digital conversion output D out becomes an intermediate value Q2. As described above, conventionally, there are 255 kinds of output values, and in this embodiment the number of kinds of the output values doubles and the size of the quantizing steps (Δ) halves. Then, quantizing noise power (Δ 2 /12) becomes 1/4 and S/N increases by 6dB. When DSP processing is applied to the digital conversion output D out , deterioration of S/N is suppressed to a minimum value. In this case, as shown in Fig. 9, suppose that an upper value is obtained by subtracting 1/4 of a quantizing step value q from the value of the upper boundary (shown by a solid line) between two adjacent quantizing output values q of companding A/D converters 39 and 41 (Fig. 5), and that a lower value is obtained by adding 1/4 of a quantizing step value q to the value of the lower boundary. These values then constitute new boundary values (i.e. decision values shown by the dotted line), and the width of a possible range of respective newly formed output values become the same, which is the most preferable. Thereby, an amplification ratio k can be calculated as follows. k≒1 + (quantizing step)/(4 x |output values|). For a companding A/D conversion, the quantizing step is made large in a region where the output value is large (namely, the quantizing noise is large). Thus, the ratio of (quantizing step / |ouput value|) of the companding A/D conversion is generally closer to the constant value than that obtained by the linear A/D converter. If this ratio is constant, then the value of the above k can be determined. However, as is clear from Fig. 7, the ratio of (quantizing step / |output value|) is not always constant. A part of the 8th segment has a value of 256/8031(=3.18%) and a part of the second segment has a value of 4/33(=12%), and the difference between these values is large. Therefore, it is necessary to determine the most appropriate value experimentally. Therefore, according to the result of the experiment using µ-law 8 bit companding A/D converter, k=1.025 is the most appropriate value. Next, an operation of the D/A converter in Fig. 6 will be explained. In order to simplify the explanation, it is supposed that the amplification ratio of the third amplifier 51, is k3=2/3. Therefore as described above, k4=k3/(1-k3)=(2/3)/(1-2/3)=2, k5=1-k3=1/3. Under this condition, if the value of digital signal D in of Fig. 6 is β, D in is input to the first companding D/A converter 49 through the first companding converter 45 and is then converted to the third analog signal A1. Thereafter it is multiplied by 2/3 (=k3) by the third amplifier 51, the output of which is 2/3D (β). Then the third companding PCM code P3 is input to linear converting unit 47-1 and reconverted to a linear signal. Therefore, the output value (OUTPUT VALUE) D (β) corresponding to the digital signal D in (=β) on the input side can be recognized as a digital value. The difference between the value β of the digital signal D in and output value D(β) is arithmetically operated in subtracting unit 47-2. Then a voltage E corresponding to a quantizing noise N produced from companding conversion unit 45 through D/A converter 49 can be obtained. Namely, E = β - D (β) The above E is multiplied by 2(=k4) by amplifying unit 48-1 and is then added to input signal D in . Thereafter it is input to the second companding conversion unit 46. Namely, β + 2E is input to conversion unit 46 and is rewritten using the above equation (1) as follows. β + 2E = D(β) + 3E Where |E| is smaller than 1/2 a quantizing step (expressed as q) corresponding to or closest to output value D(β) because, if the voltage E of the quantizing noise N is larger than 1/2 a quantizing step, D(β) becomes an adjacent different output value. As shown in Fig. 7, if D(β) is an output value 359, β of a linear input is 351 to 366, and thus, the quantizing error is less than ± 8. This is less than 1/2 a quantizing step 16 of a segment 4. Therefore 3 |E| in equation (2) is less than 3/2 times the nearest quantizing step q of D(β). Value D(β + 2E) of the fourth analog signal A2 obtained through a process of the second D/A converter system of D in → the second companding conversion unit 46 → D/A converter 50 is classified in accordance with the following conditions 1 ○ ∼ 3 ○. 1 ○ where +1.5q > 3E ≧ 0.5 q: D (β + 2E) = D (β) + q 2 ○ where +0.5q > 3E ≧ -0.5q: D (β + 2E) = D (β) 3 ○ where -0.5q > 3E ≧ -1.5q: D (β + 2E) = D (β) -q D(β) +q is an output value adjacent to the upper side of the output value D (β), and D (β) -q is the output value adjacent to the lower side of the output value D (β). The output value is multiplied by 1/3 (=k5) by the fourth amplifier 52 in Fig. 6, and is then added to the aforementioned output 2/3 D (β) of the first D/A converter system in adder 53. Based on this output 2/3 D (β) and the result of the above equations (3) - (5), the added output A out is classified in accordance with the following conditions 1 ○ - 3 ○. 1 ○ where +1.5q > 3E ≧ 0.5q: 2/3D(β) + 1/3(D(β) + q)=D(β) + q/3 2 ○ where +0.5q > 3E ≧ -0.5q: 2/3D(β) +1/3D(β) =D(β) 3 ○ where -0.5q > 3E ≧ -1.5q: 2/3D(β) + 1/3(D(β) - q)=D(β) - q/3 The relationships shown in the equations (6) - (8) are shown in Fig. 10. For a conventional structure in which only one set comprising a companding conversion unit and a companding D/A converter is provided, all the values of input digital signal D in within a range designated by region A of Fig. 10 is represented by an analog signal D (β). Therefore, if digital signal D in is positioned within region B, quantizing error is small, but if it is in region C or D, it becomes large. In contrast, in the above embodiment, quantizing error can be decreased as described below. Condition1 ○ in the above equations (3) or (6) is rewritten as 0.5q > E ≧ 0.5q/3. Namely, this shows a range of voltage E of a quantizing noise of value β of digital signal D in and representative value D(β) under condition 1 ○. This shows that the value β of digital signal D in in Fig. 6 is within region C in Fig. 10. Namely, deviation of β from the representative value D(β) represents the value within the range is about 1/3 that of quantizing step q. In such a case, as shown in the aforementioned equations (3) and (6) the value of analog signal A out is obtained by adding q/3 to the representative value D(β) and the quantizing error between the analog signal A out and the value β of region C becomes small. In other words, if the value β of digital signal D in in Fig. 6 falls within a range C of Fig. 10, the output of first companding D/A converter 49 in Fig. 6 is D(β) and the output of second companding D/A converter 50 in Fig. 6 is D(β) + q as expressed in the above-recited equation (3). Therefore, the respective outputs of first and second amplifiers 51 and 52 are 2/3D(β) and 1/3{D(β) + q} and these outputs are added in adder 53, thereby producing analog signal A out of {D(β) + q/3} as is clear from the equation (6) of Fig. 10. Conventionally, if the value β of digital input signal D in is within a range A in Fig. 10, analog signal A out is expressed merely by D(β). In the present embodiment, if β is positioned within a range C which is included in a range A, A out can be expressed by {D(β) + q/3}, thereby reducing quantizing error included in β and A out . As a result, the quantizing error between the analog signal A out and the value β in the range C becomes small. In condition 3 ○, shown by the aforementioned equations (5) or (8), the relationship is completely opposite to that of the above condition 1 ○. The analog signal A out is obtained by subtracting q/3 from the representative value D (β), and the quantizing error between analog signal A out and the value β of the region D becomes small. For condition 2 ○, shown by the aforementioned equations (4) or (7), the value β is close to the representative value D (β). This value is produced as analog signal A out without modification. As described above and shown in Fig. 6, the above quantizing noise produced from the first D/A converting system comprising a route of D in → first companding converting unit 45 → first companding D/A converting unit 49, is superimposed on an input signal of the second D/A converting system comprising the route of D in → second companding converting unit 46 → second companding D/A converting unit 50. Therefore, the quantizing noise from the first D/A converting system is almost cancelled and the second D/A converting system produces a maximum quantizing noise of q/2. At the output of adder 53, the output from the second D/A converting system is multiplied by 1/3 (=k5) by fourth amplifier 52. Thus, the produced quantizing noise becomes q/6 at maximum, namely, 1/3 the conventional quantizing noise. In the embodiment shown in Fig. 6, the output value becomes 3 times that obtained with only an ordinary companding D/A converter, and this embodiment can provide a companding D/A converter of an equivalent high resolution corresponding to, for example, 9.5 bits (256 x 3 = 2 9.5 ). The above operation will be explained in more detail by referring to an example. In an explanation of this embodiment, a µ-law is adopted as a companding rule as in Fig. 5, and the effect of the present invention does not differ from this embodiment even if an A-law companding rule is adopted. Figs. 11A and 11B show the value of respective portions of the D/A converting apparatus shown in Fig. 6 and correspond to Fig. 7 regarding the A/D converting apparatus. Figs. 11A and 11B show amplitude β digital signal D in , third companding PCM code P3, value D (β) of analog signal Al (digital expression), quantizing noise N (digital value), the value of two times voltage E of quantizing noise N (digital value), a digital output from adder 48-2 (β +2E), fourth companding PCM code P4, fourth analog signal A2 and analog converting output A out {=(2/3 x A1) + (1/3 x A2)}, respectively, in Fig. 6. As shown in Figs. 11A and 11B, respective analog converting outputs A out appear at equal intervals of 5.333 between respective analog converting outputs. Companding D/A converters 49 and 50 in Fig. 6 completely correspond to companding A/D converters 39 and 41, and respective quantizing outputs appear at equal intervals of 16 between respective outputs for segment 4, for example, as shown in the output value (OUTPUT VALUE) in Fig. 7. Therefore, according to Figs. 11A and 11B, the output intervals of analog converting output A out can be divided into small steps which are 1/3 those of an ordinary D/A converter, and the number of output values thus becomes 3 times that of an ordinary D/A converter, by combining D/A converters 49 and 50. In the above embodiment, the case of k3=2/3 is shown. However, for k3=1/2, calculations similar to those of aforementioned equations (3) - (8) are conducted, and the number of output values from analog converting output A out are double and are equal to those of a 9-bit companding D/A converter, although an 8-bit companding D/A converter is adopted. For k3=3/4, the number of output values becomes 4 times, and is equivalent to a 10-bit companding D/A converter, although an 8-bit companding D/A converter is adopted. Fig. 12 shows a detailed circuit diagram of the preferred structure of the A/D and D/A converting apparatuses according to the present invention. The preferred structure means that it can be constructed by using two sets comprising a commercially available DSP, a commercially available PCM.CODEC, and a few other elements. According to this structure, a practical, high-resolution A/D and D/A converter apparatus can be realized by merely adding an inexpensive and commercially available PCM.CODEC. This can be done more efficiently than when a high resolution A/D and D/A converting apparatus is constructed using the aforementioned Fig. 2 structure. A hybridtrans, amplifier and coarse attenuator are omitted as shown in Fig. 12. In Fig. 12, two companding A/D converters 39 and 41, as in Fig. 5, and two companding D/A converters 49 and 50, as in Fig. 6, are provided by two companding A/D converters and two companding D/A converters being installed in first PCM.CODEC 54 and second PCM.CODEC 55 in which a pair of A/D and D/A converters is integrated. In Fig. 12, arithmetic operation amplifier 56 provides an amplification ratio k1 (Fig. 5) by using resistors R 1 and R 2 (k1=R 2 /R 1 ) and resistors R 3 and R 4 in the next stage form an amplifier ratio k2 (Fig. 5). If k1 and k2 are k and 1/k, respectively, as described above, k·R 3 /(R 3 + R 4 ) = 1/k, thereby determining the values of R 3 and R 4 . A similar analysis will be applied to an arithmetic operation amplifier 57 of a D/A converting system and an amplification ratio k3 (Fig. 6) is determined as R 7 /R 6 , and k5 is determined as R 7 /R 5 . Thus, analog conversion output A out is obtained from {(R 7 /R 6 ) x A1} + {(R 7 /R 5 ) x A2} (A1 and A2 are recited in Fig. 6). In the previous example, it is assumed that k3=2/3 and k5=1/3, and in this example, it is determined that R 6 =1.5R 7 and R 5 =3R 7 . The DSP comprises the above recited first and second linear converting units 42 and 43, an arithmetic operation unit 44 (which calculates the average level) in Fig. 5, the first and second companding converting units 45 and 46, linear converting unit 47-1, subtracting unit 47-2, amplifying unit 48-1 and adding unit 48-2 as shown in Fig. 6. Line 60 in Fig. 12 is a leak cancelling line for preventing signals from leaking into a line in a 2-wire - 4-wire converter (hybrid trans), not shown in Fig. 12. DSP function units 58 and 59 respectively comprise a function of an equalizer (EQL) and a function of an attenuator (ATT), for example. These lines, connected to DSP function units 58 and 59, are respectively connected to linear/µ converting unit (L/µ) 61 and µ/linear converting unit (µ/L) 62, and are thus connected to a transmission path. As explained above, the first embodiment provides A/D and D/A conversion apparatuses which combine an A/D and a D/A converter with a DSP, and the high resolution input and output of an A/D and D/A converter which is required by a DSP can be achieved by merely adding inexpensive amplifiers (amplifiers 38 and 40 in Fig. 5 and amplifiers 51 and 52 in Fig. 6) by utilizing an arithmetic operation function of the DSP without modifying the A/D and D/A converters.

Claims: A signal processing apparatus for converting between an analog signal (A in ) and a digital signal (D out ) comprising: first and second A/D converting means (39 to 43) for individually converting the amplified analog input signal; and means (44) for computing an average value of the results obtained by said first and second A/D converting means (39 to 43) to provide the digital output signal (D out ); characterized by means (38, 40) for amplifying an amplitude value of the analog input signal; wherein said amplifying means (38, 40) includes first and second amplifying means, said first and second amplifying means amplify the analog input signal (A in ) by k1 and k2, respectively, when k1 is a real number greater than one, and k2 is a real number satisfying k2 * k1 = 1 to produce first and second amplified analog signals, said first and second A/D converting means (39 to 43) respectively convert the first and second amplified analog signals to first and second digital signals (P1, P2), said computing means (44) computes an average value of the first and second digital signals to provide the digital output signal (D out) . The signal processing apparatus according to claim 1, wherein said first and second A/D converting means (39 to 43) comprise respectively first and second companding A/D converting means (39, 41) and first and second linear converting means (42, 43), said first and second companding A/D converting means (39, 41) respectively convert the first and second amplified analog signals to first and second companding PCM code (P1, P2), said first and second linear converting means (42, 43) respectively convert the first and second companding PCM codes (P1, P2) to first and second linear signals (L1, L2), said computing means (44) arithmetically averages the values of the first and second linear signals (L1, L2) to provide the digital output signal (D out ), and wherein said first and second linear converting (42, 43) means and said computing means (44) are provided in a digital signal processor (DSP). The signal processing apparatus according to claim 2, wherein the digital signal (D out , D in ) comprises linear PCM codes, further comprising: first companding converting means (45) for converting a digital input signal (D in ) to third companding PCM codes (P3); first D/A converting means (49) for converting the third companding PCM codes (P3) to a third analog signal (A1); third amplifying means (51) for amplifying the third analog signal (A1) by k3, where k3 is a real number greater than zero, to produce a third amplified output; detecting means (47) for detecting a quantizing error (E) in the third companding PCM (P3) codes of the digital signal; error adding means for adding to the digital signal (D in , β) a value (2E) obtained by multiplying the quantizing error (E) by k4, where k4 is selected to be a real number satisfying an equation k4 = k3/(1-k3), to provide a compensated digital signal (β+2E); second companding conversion means (46) for converting the compensated digital signal (β+2E) to fourth companding PCM codes (P4); second D/A converting means (50) for converting the fourth companding PCM codes (P4) to a fourth analog signal (A2); fourth amplifying means for amplifying (52) the fourth analog signal (A2) by k5, where k5 is selected as a real number to satisfy an equation k5 + k3 = 1, to produce a fourth amplified output; adding means (53) for adding the third and fourth amplified outputs to provide the analog output signal (A out ); and wherein said first and second companding conversion means (45, 46), said detecting (47) means and said error adding means (48) are provided in the digital signal processor (DSP). A signal processing apparatus for converting between a digital signal (D in ), and an analog signal (A out ) comprising: first (45, 49, 51) and second (46, 50, 52) D/A converting means for individually converting the digital input signal (D in ); detecting means (47) for detecting a quantizing error caused by said first converting means (45); error adding means (48) for adding the quantizing error to the digital input signal and applying the result to said second D/A converting means (46); and adding means (53) for adding respective conversion results of said first and second D/A converting means to provide the analog output signal (A out ). The signal processing apparatus according to claim 4, wherein said first D/A converting means (45, 49, 51) comprises a first converter (45), first D/A means (49) and third amplifying means (51), said first converter (45) converts the digital signal (D in , β) to a first quantizing digital signal (P3), said first D/A converting means (49) converts the first quantizing digital signal (P3) to a third analog signal (A1), said third amplifying means (51) amplifies the third analog signal (A1) by k3, where k3 is a real number greater than zero, to produce a third amplified output, said detecting means (47) detects a quantizing error (E) in the first quantizing digital signal (P3) of the digital signal, said error adding means (48) adds to the digital signal (β) a value obtained by multiplying the quantizing error (E) by k4, where k4 is selected to be a real number satisfying an equation k4 = k3/(1-k3), to provide a compensated digital signal (β+2E), said second D/A converting means (46, 50, 42) comprises second converter (46), second D/A converting means (50) and fourth amplifying means (52), said second converter (46) converts the compensated digital signal (β+2E) to a second quantizing digital signal (P4), said second D/A converting means (50) converts the second quantizing signal (P4) to a second analog signal (A2), said fourth amplifying means (52) amplifies the fourth analog signal (A2) by k5, where k5 is selected as a real number to satisfy an equation k5 + k3 = 1, to produce a fourth amplified output, said adding means (53) adds the third and fourth amplified outputs to provide the analog output signal (A out ). The signal processing apparatus according to claim 5, wherein said digital signal (D in , β) comprises linear PCM codes, and wherein said first converting means (45, 49, 51) comprises first companding conversion means (45), for converting the digital signal to third companding PCM codes (P3), said second converting means (46, 50, 52) comprises second companding conversion means (46), for converting the compensated digital signal (β+2E) to a fourth companding PCM codes (P4); and wherein said first and second companding conversion means (45, 46), said detecting means (47) and said error adding means (48) are provided in a digital signal processor (DSP). The signal processing apparatus according to claim 6, wherein the digital signal (D out , D in ) comprises linear PCM codes, further comprising: first and second amplifying means (38, 40) for amplifying an analog input signal by k1 and k2, respectively, when k1 is a real number greater than one, and k2 is a real number satisfying k2 * k1 = 1, to produce first and second amplified analog signals; first and second companding A/D converting means (39, 41) for respectively converting the first and second amplified analog signals to first and second companding PCM code (P1, P2); first and second linear converting means (42, 43) for respectively converting the first and second companding PCM codes (P1, P2) to first and second linear signals (L1, L2); computing means (44) for arithmetically averaging the values of the first and second linear signals (L1, L2) to provide the digitial output signal (D out ); and wherein said first and second linear converting means (42, 43) and said computing means (44) are provided in the digital signal processor (DSP).

Inventors: KAKUISHI MITSUO, UESHIMA TSUYOSHI, KAKUISHI, MITSUO, UESHIMA, TSUYOSHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H03H17
IPC codes: H03M1