Reduced voltage integrated-circuit

Abstract: A bipolar/CMOS integrated circuit uses an on-chip amplifier to provide an intermediate voltage supply (18) to two groups of small geometry CMOS circuits. Bipolar devices (24) may use a full five volts from the outside supply rails (12, 14).

Description: TECHNICAL FIELD OF THE INVENTION This invention relates in general to integrated circuits, more particularly to a MOS transistor integrated circuit having reduced voltages. BACKGROUND OF THE INVENTION Present day CMOS integrated circuits use a 5 volt power supply. As the size of the CMOS devices are reduced, the voltage that the device can tolerate is similarly reduced. Consequently, a smaller power supply voltage will be needed to accommodate the smaller CMOS devices. In order to maintain compatibility with CMOS integrated circuits using a 5 volt power supply, as well as other technologies such as bipolar and ECL, it is desirable that the new CMOS integrated circuits also use a 5 volt power supply at its external pins. Internally, however, it is necessary to provide a smaller voltage, such as 2.5-3.0 volts for the CMOS devices. One alternative is to use an on-chip voltage regulator which is powered by 5 volts and outputs a smaller voltage, such as 2.5 volts. Such an arrangement is inefficient since the excess voltage would be dissipated as heat, and is therefore undesirable from both a power and a reliability standpoint. Therefore, a need has arisen in the industry to provide an integrated circuit having a 5 volt power supply input which efficiently supplies the CMOS devices comprising the integrated circuit with a reduced voltage. SUMMARY OF THE INVENTION In accordance with the present invention, an integrated circuit and a method of supplying voltages to the same are provided which substantially eliminate problems associated with integrated circuits incorporating low voltage circuit blocks. According to a first aspect of the present invention there is provided an integrated circuit including a plurality of circuit blocks comprising: a first supply rail at a first predetermined voltage; a second supply rail at a second predetermined voltage, the circuit blocks being arranged in pairs of circuit blocks connected in series between said first and second supply rails by means of an interconnect circuitry; an intermediate supply rail at an intermediate voltage between said first and second predetermined voltages being arranged between the circuit blocks of each pair and connected to the interconnect circuitry between the circuit blocks of each pair; and an amplifier connected between said first and second supply rails for supplying current to said intermediate supply rail to maintain the voltage thereon at said intermediate voltage. According to a second aspect of the present invention there is provided a method of supplying voltage to a plurality of circuit blocks on an integrated circuit in which the circuit blocks are arranged in pairs, the blocks within each pair being connected in series between first and second terminals by means of an interconnect circuitry, the method comprising, supplying first and second predetermined voltages, applying the first and second voltages respectively to the first and second terminals of each pair, supplying a third voltage that is derived from the first and second voltages by means including an amplifier and that is intermediate to the first and second voltages, and applying the third voltage to the interconnect circuitry between the blocks of each pair. One example of the integrated circuit comprises first and second voltage supply rails, typically biased at O and 5 volts, respectively. CMOS circuit blocks are connected in series between the first and second supply rails with an intermediate supply rail connected between the circuit blocks. Hence, each pair of circuit blocks receives the 5 volts across the first and second supply rail, one circuit block receiving a voltage equal to the potential between the first supply rail and the intermediate supply rail and the second circuit block receiving a voltage equal to the potential between the intermediate supply rail and the second supply rail. An amplifier is connected between the first and second supply rails to supply current to the intermediate supply rail in order to maintain the voltage thereon a predetermined intermediate voltage. The present invention provides the technical advantage that devices requiring a reduced voltage may be used on an integrated circuit which receives conventional voltage supplies to be consistent with other integrated circuits on the circuit board. The present invention is more efficient than a on-chip voltage regulator, which for example would dissipate power at a 5 volt level, while performing at a 2.5 (or other intermediate) volt level. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description now taken in conjunction with the accompanying drawings in which: FIGURE 1 illustrates a block diagram of a circuit using the present invention; and FIGURE 2 illustrates a circuit diagram of two CMOS circuit blocks connected between the voltage supply rails and the intermediate supply rail. DETAILED DESCRIPTION OF THE INVENTION The preferred embodiment of the present invention is best understood by referring to FIGUREs 1-2 of the drawings, like numerals being used for like and corresponding parts of the various drawings. FIGURE 1 illustrates a block diagram of an integrated circuit using low voltage CMOS devices. The integrated circuit 10 receives its voltage from a 5 volt (relative to ground) voltage supply rail 12 and a ground voltage supply rail 14. Amplifier 16 is connected between the voltage supply rails 12 and 14 and is connected to a 2.5 volt supply rail 18. Low voltage CMOS circuit blocks 20 are grouped in pairs 22 of serially connected circuit blocks 20 such that each CMOS pair 22 is connected across the voltage supply rails 12 and 14. Hence, each CMOS circuit pair 22 receives 5 volts. The 2.5 volt supply rail 18 is connected between the CMOS circuit blocks 20 comprising each circuit pair 22. Bipolar circuits 24 are connected across the voltage supply rail 12 and 14. In operation, each CMOS circuit pair 22 receives a voltage of 5 volts. The 2.5 volt supply rail 18 is maintained at 2.5 volts by the amplifier 16 which supplies the unbalanced current to the 2.5 volt supply rail 18. Hence, each of the CMOS circuit blocks 20, individually, receives 2.5 volts. FIGURE 2 illustrates a circuit diagram of two low voltage CMOS circuits 20a and 20b as used in the integrated circuit 10 of the present invention. The first CMOS circuit 20a, an inverter, comprises a PMOS transistor 26 and an NMOS transistor 28. The PMOS transistor 26 has a first source/drain connected to the 5 volt supply rail 12 and a second source/drain connected to a source/drain of the NMOS transistor 28. The other source/drain of the NMOS transistor 28 is connected to the 2.5 volt supply rail 18. The second CMOS circuit 20b also comprises a PMOS transistor 30 and an NMOS transistor 32. The PMOS transistor 30 has a first source/drain connected to the 2.5 volt supply rail 18 and a second source/drain connected to a source/drain of the NMOS transistor 32. The other source/drain of the NMOS transistor 32 is connected to the ground supply rail 14. For purposes of illustration, CMOS circuits 20a-b are shown as inverters. These circuits are shown for exemplary purposes; more complicated circuits could be similarly implemented as would be understood by one skilled in the art. In each CMOS circuit pair 22, one of the CMOS circuit blocks 20 will have an NMOS transistor with a 2.5 volt backgate bias. Consequently, the N channel devices on opposite sides of the 2.5 volt supply rail 18 may have to be fabricated differently. Two alternative schemes may be used to compensate for the 2.5 volt backgate bias. The simplest compensation technique is to adjust the threshold voltage of one NMOS transistor differently than the other. The second compensation technique is to isolate each NMOS transistor in a P-well by using a buried N+ diffusion such that each NMOS transistor sits in its own P-well. The P channel transistors do not suffer from the same problem, since each P channel device typically sits in its own N-well. It should be noted that while the preferred embodiment shows a 2.5 volt supply rail 18, this intermediate supply rail could be held at any voltage between 0 and 5 volts, as desired. For example, the supply rail 18 could be held at 3 volts, providing for 2 volt CMOS circuits to be implemented between the intermediate supply rail 18 and the 5 volt voltage supply rail 12 and 3 volt CMOS circuits being implemented between the ground supply rail 14 and the intermediate supply rail 18. The present invention provides the technical advantage that CMOS circuits may be operated at reduced voltages, thereby avoiding hot electron effects, without the need for an on-chip regulator. On-chip regulators are undesirable, since they dissipate power at a 5 volt level, while providing the performance of a reduced supply. It should be noted that while the present invention has been discussed in connection with 0 and 5 volt external voltage supplies, the concepts embodied in the invention would be useful regardless of the actual external voltages used. It should also be noted that a plurality of intermediate supply rails 18 could be used to split the voltage from the outside supply rails 12 and 14 into more than two increments.

Claims: An integrated circuit including a plurality of circuit blocks (20) comprising: a first supply rail (14) at a first predetermined voltages; a second supply rail (12) at a second predetermined voltage, the circuit blocks being arranged in pairs (22) of circuit blocks connected in series between said first and second supply rails by means of an interconnect circuitry; an intermediate supply rail at an intermediate voltage between said first and second predetermined voltages being arranged between the circuit blocks of each pair and connected to the interconnect circuitry between the circuit blocks of each pair; and an amplifier (16) connected between said first and second supply rails for supplying current to said intermediate supply rail to maintain the voltage thereon at said intermediate voltage. An integrated circuit according to claim 1 wherein said first supply rail (14) is connected to ground and said second supply rail (12) supplies twice the voltage above ground that the intermediate supply rail (18) supplies above ground. An integrated circuit according to claim 2 wherein said second supply rail (12) supplies a voltage of 5 volts above ground, and said intermediate supply rail (18) supplies 2.5 volts above ground. An integrated circuit according to any one of claims 1 to 3, wherein said circuit blocks (20) comprise CMOS circuits (20a,20b), each having an NMOS (28,32) and a PMOS transistor (26,30), each NMOS transistor (e.g. 28) of one circuit in the pair having a P-well separate from the NMOS transistor (e.g. 32) of the other circuit of the pair and each PMOS transistor (26,30) having a separate N-well to accommodate the first and second supply voltages. An integrated circuit according to any one of claims 1 to 3, wherein said circuit blocks (20) comprise CMOS circuits (20a,20b), each CMOS circuit comprising an NMOS (28,32) and a PMOS transistor (26,30), the NMOS transistor (e.g. 28) in one circuit of each pair having an adjusted threshold voltage to compensate for a backgate bias. An integrated circuit according to claim 4 or claim 5 further comprising bipolar circuits (24) connected between said first and second supply rails. A method of supplying voltage to a plurality of circuit blocks (20) in an integrated circuit, in which the circuit blocks are arranged in pairs (22), the blocks within each pair being connected in series between first and second terminals by means of an interconnect circuitry, the method comprising, supplying first and second predetermined voltages, applying the first and second voltages respectively to the first and second terminals of each pair, supplying a third voltage that is derived from the first and second voltages by means including an amplifier (16) and that is intermediate to the first and second voltages, and applying the third voltage to the interconnect circuitry between the blocks of each pair. A method according to claim 7 wherein the third voltage is half way between the first and second voltages. A method according to claim 7 or claim 8 wherein said circuit blocks (20) comprise CMOS circuits (20a,20b) comprising an NMOS (28,32) and a PMOS transistor (26,30), the method further comprising the step of providing different threshold voltages for the NMOS transistors in each circuit block of the pair to compensate for backgate bias. A method according to claim 7 or claim 8 wherein said circuit blocks (20) comprise CMOS circuits (20a,20b) comprising an NMOS (28,32) and a PMOS transistor (26,30), the method further comprising the step of isolating the NMOS transistors in each circuit block of the pairs a separate P-well.

Inventors: SCOTT DAVID B, SCOTT, DAVID B.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1989
Main classification: H01L27
IPC codes: H01L27, H01L21