Checkpoint retry mechanism

Abstract: An improved checkpoint retry mechanism is disclosed which automatically updates checkpoint addresses to enable the retry of instruction sequences for shorter segments of recently executed code, in response to the detection of an error since the passage of the current checkpoint. It does this by updating three different types of checkpoint addresses, a first checkpoint address for the instruction which follows a memory write or I/O write operation, a second type checkpoint address for the first instruction in an interrupt service routine, and a third type checkpoint address for the first instruction in an interrupted routine following an interrupt event. The resulting checkpoint retry mechanism is more efficient and faster because it adaptively updates the checkpoint address to reduce the size of code segments which must be reexecuted during retry operations. The invention operates to avoid memory corruption and erroneous I/O outputs during retry operations and protects from erroneous retry sequences.

Description: The invention disclosed broadly relates to data processing systems and more particularly relates to improvements in recovery from fault detection in data processing systems. Data processing systems have historically suffered from both soft errors and hard errors. Soft errors are usually defined as those deviations from the expected output which occur because of electrical noise or other randomly occurring sources which result in nonreproducible fault syndromes. Hard errors are typically associated with electrical components or mechanical component failures producing errors which are reproducible. Many arrangements for fault tolerant data processing systems have been developed in the prior art. Typical examples of fault tolerant systems is the provision of two or more identical data processing elements operating on the same instruction stream and having their outputs compared with one another. When a difference is detected in the outputs of a pair of data processing elements, it can be inferred that either a soft error or a hard error has occurred. Typically in the prior art, the data processors are then restarted and the instruction stream is executed in a stepwise manner until the error is detected again. If there is no error occurring, then the initial error determination was that of a soft error. If the error is repeated in the stepwise manner, then the instruction at which the error occurs can be identified. This prior art approach to the retrial of instructions after the detection of a fault is a lengthy one. The prior art has not found suitably efficient and fast techniques for the retry of instructions after fault detection. Document "Microprocessing and microprogramming , Vol.17, No. 4, April 1986, pages 205-217, Amsterdam , NL, by A. ANTOLA et al." discloses a checkpoint retry mechanism, wherein in case of errors which are detected by a parallel signature analyser at the end of a microprogram segment, execution is restarted from the recovery point in order to repeat the microprogram segment where the error generated. It is therefore an object of the invention to provide an improved instruction retry mechanism, which is more efficient than those provided in the prior art, which enables the retrial of short segments of recently executed code, which minimizes the chances of memory corruption by erroneously over-writing the memory, which minimizes erroneous I/O outputs to storage media or printers, and which more effectively protects from erroneous retry sequences. These and other objects, features and advantages of the invention are accomplished by the checkpoint retry mechanism disclosed herein as claimed in claim 1. The invention is applied in a data processor which includes an instruction memory containing a sequence of executable instructions. The data processor will also include an arithmetic logic unit which operates in response to the instructions so as to carry out arithmetic and logical operations. The data processor can also include a status register for storing the current status of the arithmetic logic unit and the plurality of general purpose registers accessible by the arithmetic logic unit for storing current operand and address values. The improved checkpoint retry mechanism in the data processor will include an instruction decoder which has an input connected to an output of the instruction memory for decoding instructions accessed from the memory. The instruction decoder will include a write decode output, an interrupt decode output and an interrupt return decode output. The instruction decoder will also include an output connected to a control input of the arithmetic logic unit. The instruction memory includes an address register for storing the address of the next instruction to be accessed. The checkpoint retry mechanism further includes a checkpoint address register for storing the address of the first instruction following a write instruction accessed from the instruction memory, this being a first type checkpoint address. The instruction memory address register has an input connected to an interrupt vector address mechanism such as a vector table, for storing the address of the first instruction in a service routine which is pointed to by an interrupt instruction accessed from the instruction memory or alternately which is pointed to when an externally generated interrupt occurs. The address of the first instruction in the service routine is loaded into the checkpoint address register, as a second type checkpoint address which occurs in response to accessing an interrupt instruction or the occurrence of an interrupting event. An interrupt return stack is included in the data processor for storing the address of a first instruction in an interrupted program which occurs after an interrupt instruction is executed or after the occurrence of an interrupting event. The address of the first instruction in an interrupted program after the occurrence of an interrupt instruction or the occurrence of an interrupting event, is loaded into the checkpoint address register as a third type checkpoint address which occurs in response to the accessing of an interrupt return instruction from the instruction memory at the end of the service routine. An error checker is included in the checkpoint retry mechanism, which has an input connected to an output of the arithmetic logic unit, for detecting errors occurring in the arithmetic logic unit. The contents of the checkpoint address register are transferred to the instruction memory address register in response to the error checker detecting an error in the operation of the arithmetic logic unit. This results in the contents of the instruction memory address register becoming the checkpoint address which is used for retrying the sequence of instructions following the current checkpoint address value in response to the detection of an error. In this manner, checkpoint addresses are automatically updated to enable the retry of instruction sequences for shorter segments of recently executed code, in response to the detection of an error which has occurred since the passage of the current checkpoint. These and other objects, features and advantages of the invention will be more fully appreciated with reference to the accompanying figures. Fig. 1 is a functional block diagram of the improved checkpoint retry mechanism. Fig. 2 is an example of the contents of the instruction memory 20, which illustrates the operation of the improved checkpoint retry mechanism. Fig. 3 shows a logic block diagram of a dual redundant processor configuration. Fig. 4 illustrates a state diagram of the checkpoint retry sequences. Fig. 5 illustrates four different case scenarios for checkpoint retry. The improved checkpoint retry mechanism is shown in an overall functional block diagram in Fig. 1. The invention finds application in data processors which include an instruction memory 20 containing a sequence of executable instructions, an arithmetic logic unit 22 which operates in response to the instructions to carry out arithmetic and logical operations, a status register 24 for storing the current status of the arithmetic logic unit 22, and a plurality of general purpose registers 26 which are accessible by the arithmetic logic unit 22, for storing current operand and address values. The improved checkpoint retry mechanism shown in Fig. 1 includes an instruction decoder 28 which has an input connected to an output of the instruction memory 20, for decoding the instructions which are accessed therefrom. Also included with the instruction decoder 28 is a write decode output 30, an interrupt decode output 32, and an interrupt return decode output 34. The instruction decoder 28 further includes an output connected over line 36 to a control input of the arithmetic logic unit 22. The instruction memory 20 includes an address register 38 for storing the address of the next instruction to be accessed from the instruction memory 20. The improved checkpoint retry mechanism of Fig. 1 further includes a first two input AND gate 40 which has a first input 42 connected to an output of the instruction memory address register 38 and it has a second input 44 connected through the OR gate 62 to the write decode output 30 of the instruction decoder 28. Fig. 2 shows the contents of the instruction memory 20, as an example which will illustrate the operation of the improved checkpoint retry mechanism. Included in the instruction memory 20 is a main routine 50 and an interrupt service routine 56. The memory is organized as sequentially addressed storage locations and the instructions in the main routine 50 can occupy a first contiguous memory space and the instructions in the interrupt service routine 56 can occupy a second separate contiguous memory space, for example. As is well-known in the prior art, the address for the location of routines can be relocated and partitioned for various applications. In the arrangement of the contents for the instructions in Fig. 2, it is seen that the main routine 50 includes a sequence of instructions with a write instruction 52 at an address A followed by a next instruction 54 at address A+1. The main routine 50 further includes at a later portion an interrupt instruction 60 at address location B followed by a next instruction 68 at address location B+1. The interrupt service routine 56 includes a first interrupt instruction 58 at address C which is the address pointed to by the interrupt instruction 60 in the main routine 50. It is within the scope of the invention that instead of having a software interrupt instruction 60 at address B, a hardware generated interrupt can occur at the point of execution of the instruction 60 at address B in the main routine 50. The interrupt service routine 56 further includes a write instruction 59 at address D followed by a next instruction 61 at address D+1. The interrupt service routine 56 will terminate with an interrupt return instruction 72 which will return the execution to the instruction 68 at address B+1 in the main routine 50. Typically this is accomplished by having saved the address B+1 for the instruction 68 at the time that the interrupt 60 occurred during the execution of the main routine 50. The improved checkpoint retry mechanism of Fig. 1 further includes a checkpoint address register 46 which has an input connected through OR gate 64 to the output of the first AND gate 40, for storing the address A+1 of the first instruction 54 following the write instruction 52 at address A which has been accessed from the instruction memory 20 as shown in Fig. 2. In accordance with the invention, the storage of the address A+1 in the checkpoint address register 46 is a first type checkpoint address which is associated with the execution of a write instruction. Such a write instruction can be for the writing of information into the instruction memory or into the data memory of the data processor. Alternately, the write instruction 52 can be for the writing of output information to an I/O unit such as a disk storage, a tape storage or alternately a printer or a display device. The object of the first type checkpoint address is to provide a point at which retrial can be initiated if an error is detected in the operation of the arithmetic logic unit 22 prior to the execution of another subsequent write instruction, or an interrupt instruction or event. In accordance with the invention, this minimizes the chances that a retrial will cause the corruption of the memory or the state of an I/O device. Every time a write instruction such as the instruction 52 in the main routine 50 or the instruction 59 in the interrupt service routine 56 is executed, the checkpoint address register 46 will have an updated value stored therein which is the address of the next occurring instruction. In accordance with the invention, this will enable short segments of recently executed code to be retried in the event of the detection of an error. The instruction memory address register 38 has an input connected to an interrupt vector address means 48 which can be for example a vector address table located elsewhere in the instruction memory or data memory of the data processor. An example of the operation of vector address tables is described in the copending U.S. patent application serial number 770,541, filed August 29, 1985 by Bradly J. Konopik, et al., entitled "Multiple Interrupt Sharing," assigned to the IBM Corporation and incorporated herein by reference for its explanation of interrupt operations. The interrupt vector address means 48 will store the address C of the first instruction 58 in the service routine 56 of Fig. 2, which is pointed to by the interrupt instruction 60 in the main routine 50 which has been accessed from the instruction memory 20, or alternately which is pointed to as a result of the occurrence of an interrupting event. The first AND gate 40 has a second input 44 connected through the OR gate 62 to the interrupt decode output line 32 of the instruction decoder 28, for enabling the address C of the first instruction 58 in the service routine 56 which has been transferred from the interrupt vector address means 48 to the instruction memory address register 32, to be loaded through the OR gate 64 into the checkpoint address register 46. In accordance with the invention this is a second type checkpoint address which occurs in response to the accessing of an interrupt instruction 60 from the instruction memory 20 or alternately which occurs in response to the occurrence of an interrupting event at or during the execution of instruction 60 in the main routine 50. In this manner, if a fault is detected in the operation of the ALU 22 following the execution of the first interrupt instruction 58 at address C in the service routine 56, the retry of instructions will start from the first instruction 58. In this manner, short segments of recently executed code can be retried when an error has been detected. The data processor shown in Fig. 1 can further include an interrupt return address stack 66 for storing the address B+1 of the instruction 68 in the interrupted program 50 which occurs after the interrupt instruction 60 when the interrupt took place. The checkpoint retry mechanism of Fig. 1 further includes a second AND gate 70 which has a first input connected to an output of the address stack 66 and a second input connected to the instruction return decode output 34 of the instruction decoder 28. The second AND gate 70 has an output connected through the OR gate 64 to the checkpoint address register 46, for loading the first instruction 68 at address B+1 in the interrupted program 50 after the occurrence of the interrupt instruction 60 at address B, into the checkpoint address register 46. In accordance with the invention, this is a third type checkpoint address which occurs in response to the accessing of an interrupt return instruction 72 in the service routine 56, from the instruction memory 20. In this manner, if an error is detected in the operation of the ALU 22 after the execution of the instruction 68 at address B+1 in the main routine 50, retry of instructions will start from the instruction 68 at address B+1. Thus, short segments of recently executed code will be retried in the event that an error is detected in the operation of the ALU 22. The checkpoint retry mechanism of Fig. 1 includes an error checker 74 which has an input connected to an output 51 of the arithmetic logic unit 22, for detecting errors occurring in the arithmetic logic unit 22. There are several different techniques which can be employed for the error checker 74. One technique is to have two arithmetic logic units 22 and 22′ which operate in parallel to execute the same instruction stream being output from the instruction memory 20. The outputs of the pair of arithmetic logic units 22 and 22′ can then be compared and if there is a difference detected in the outputs, it can be inferred that an error has occurred in one of the two arithmetic logic units. This can cause the output of an error detection signal from the error checker 74 on the output line 92. Other examples of error checking techniques which can be employed for the error checker 74 will be discussed later in this patent application. A third AND gate 76 in Fig. 1 has a first input connected to the output of the checkpoint address register 46 and a second input connected to an output of the error checker 74, for transferring the contents of the checkpoint address register 46 to the instruction memory address register 38, in response to the error checker 74 detecting that an error has occurred in the operation of the arithmetic logic unit 22. The resulting contents of the instruction memory address register 38 will now be the current value of the checkpoint address for retrying the sequence of instructions following the current checkpoint address value. In this manner, checkpoint addresses are automatically updated to enable the retry of instruction sequences for shorter segments of recently executed code, in response to the detection of an error which has occurred since the passage of the current checkpoint. Fig. 1 further shows a shadow status register 80 for storing the contents of the status register 24 when a new checkpoint address value is stored in the checkpoint address register 46. A fourth AND gate 82 has a first input connected to an output of the status register 24 and a second input connected through the OR gate 84 and through the OR gate 62 for logically ORing the write output 30, the interrupt output 32 and the interrupt return output 34 of the instruction decoder 28. The fourth AND gate 82 has an output connected to an input of a shadow status register 80, for loading the contents of the status register 24 into the shadow status register 80, when the checkpoint address register 46 has a new checkpoint address value stored therein. The shadow status register 80 has an output 86 which is coupled through the AND gates 88 to input 90 of the status register 24, for transferring the contents of the shadow status register 80 to the status register 24 when the error checker 74 detects the occurrence of an error in the arithmetic logic unit 22 and outputs a signal on line 92. Fig. 1 shows a plurality of shadow general purpose registers 94 for storing the contents of the plurality of general purpose registers 26 through AND gate 82 when a new value for the checkpoint address has been stored in the checkpoint address register 46, in a similar manner to that described for transferring the contents of the status register 24 to the shadow status in register 80. The shadow general purpose registers 94 have an output 86 coupled through the AND gate 88 to the line 90 of the general purpose registers 26 for transferring the contents of the shadow general purpose registers 94 to the general purpose registers 26 in response to the error checker 74 outputting the output signal 92 which indicates the occurrence of an error in the arithmetic logic 22. The invention results in automatically updating checkpoint addresses to enable the retry of instruction sequences for shorter segments of recently executed code in response to the detection of an error which has occurred since the passage of the current checkpoint. This results in a more efficient and faster checkpoint retry operation which avoids the problems of memory corruption and erroneous I/O outputs. The invention also operates to protect from erroneous retry sequences. Fig. 1 shows an additional feature of the invention which is used after an error has been detected and the address register 38 has been loaded with the checkpoint retry address. A single step instruction address incrementer 35 has an output connected to the address register 38. An error latch 37 has an input connected to the output line 92 from the error checker 74 and it has an output 75 connected to an input of the instruction address incrementer 35. When the error checker 74 detects that an error has occurred, the signal on line 92 sets the latch 37 and the signal 75 from the latch 37 to the instruction address incrementer 35 indicates the commencement of a single stepping mode. When the address register 38 has the checkpoint retry address loaded therein, the instruction corresponding to the checkpoint retry address is accessed from the instruction memory 20 and is executed by the ALU 22. Then, the instruction address incrementer, under the control of the single-step mode signal 75 from the latch 37, increments by one, the value of the address in the address register 38. Thus, the next instruction in the instruction memory 20 is accessed and is executed in the ALU 22 in a sequential stepwise manner, until the instruction is accessed which causes the error condition to occur once again. When the error checker 74 outputs its second error detection signal on line 92, this signifies that the error initially detected has been detected again and the signal on line 92 is combined in the AND gate 41 with the on-state output from the latch 37, resulting in setting the latch 39 which is the error address flag latch. The error address flag latch 39 has an output 45 which signals that the error address currently in the address register 38 is the address of instruction causing the error which has been detected. In order to prevent the address register 38 from changing its value, an inhibit line from the output of the latch 39 is applied to the address register 38, thereby freezing the address contents therein to be that of the instruction causing the error which is detected by the error checker 74. When the flag signal 45 occurs for the error address flag output of latch 39, this signal can be used to enable AND gate 73 to pass the error address from the address register 38 to the error address register 71, making it available. A software branch can be made to an error analysis routine or the value of the address for the error producing instruction can be displayed or printed so that a diagnostic programmer can perform error maintenance. If an error is detected for a first time and during the first retry the error is not repeated, it is assumed that the error is a soft error. In this circumstance, when the instructions are executed down to the next checkpoint such as the address of an instruction following a next write instruction, for example, the OR gate 64 will output a signal as previously described. The OR gate 64 outputs a signal for loading the checkpoint register 46 and the signal output from the OR gate 84 will be the clear input of the latch 37 to reset that latch. In this manner, the execution of the program will continue in a normal manner, no longer in the stepwise sequential manner following the detection of the first occurrence of the error. This is because there is no longer a single-step mode signal 75 output from the latch 37 to the instruction address incrementer 35. Fig. 3 shows a dual redundant processor configuration. The processor 10 of Fig. 1 is shown in Fig. 3 and an identical processor 10′ is also shown, both coupled to a main system data bus 55 and address bus 63 and both sharing the same instruction memory 20. It is an objective of this feature of the invention to swap the master or active processor from the first processor 10 to the second processor 10′ at the occurrence of a signal on the error address flag line 45 of the processor 10, and vice versa. As can be seen in Fig. 3, a maintenance processor 48 has an input connected to the error address flag 45 from the first processor 10 and the second input connected to the error address flag 45′ from the second processor 10′. The maintenance processor 10 will decide which processor 10 or 10′ is to be the active processor for the main system data bus 55 and address bus 63. The maintenance processor 48 has an output line 43 which is coupled to a first AND gate 53 which has a second input connected to the data output 51 of the ALU 22 of the processor 10. When the maintenance processor selects the first processor 10 as the master processor to be connected to the main system bus 55, it outputs an enabling signal on line 43 which satisfies the AND gate 53, thereby coupling the ALU output line 51 to the main system data bus 55. Alternately, if an error address flag signal on line 45 from the processor 10 occurs, the maintenance processor will remove the enable signal from the output line 43 and this, when passing through the inverter 49, provides an enabling signal to the AND gate 53′, thereby coupling the output line 51′ from the ALU 22 in the processor 10′ to the main system data bus 55, while disabling the AND gate 53 which interrupts the coupling of the processor 10 to the main system data bus 55. In this manner, the maintenance processor 48 can perform a swapping operation between the dual redundant processors 10 and 10′. Another feature of the invention is shown in Fig. 3, the comparison of the contents of the address register 38 in the processor 10 with the contents of the address register 38′ in the processor 10′ by means of the comparator 57. The comparator 57 has an output connected to the maintenance processor 48. If the current addresses in the address registers 38 or 38′ are not the same, then the same instructions would not be accessed on output 77 from the instruction memory 20. This would indicate that any resultant error which is detected by the error checkers 74 or the error checker in the processor 10′ would be the result of malfunction in the checkpoint retry mechanism itself. If there is a noncompare in the address registers 38 and 38′ detected by the comparator 57, the maintenance processor 48 will not execute a retry operation. Alternately, if however there is an error detected by the error checker 74 in the processor 10 or in the corresponding error checker 74′ in the processor 10′ producing respective signals on the error address flag lines 45 or 45′, then retry operations will take place, as has been previously described. Fig. 3 also shows that the particular processor either 10 or 10′ which is selected by the maintenance processor as the master, will be the processor whose address register contains the effective address which is applied to the instruction memory 20. This is done by having the output of the address register 38 connected through an AND gate 65 to the address bus 63 which is connected to the address input 79 of the instruction memory 20. The AND gate 65 is enabled in the same manner as is the AND gate 53 previously described, by the enable line from the maintenance processor 48. Similarly, for the processor 10′, the address register 38′ has an output connected through an AND gate 65′ to the address bus 63 and the AND gate 65′ is satisfied only when the AND gate 65 corresponding to the processor 10 is not satisfied. Thus, only the active processor 10 or 10′ has its address register effectively connected to the address input 79 of the instruction memory 20 through the address bus 63. Another feature shown in Fig. 3 is that the error checker 74 in the processor 10 who has an output 67 connected to an OR gate 69 and the corresponding output 67′ of the error checker 74′ in the processor 10′ is also connected to the input of the OR gate 69. The output of the OR gate 69 is the line 92 which, as can be seen in Fig. 1, is the error signal line which is shown and exists for both processor 10 and processor 10′. When either one of the processors 10 or 10′ has its respective error checkers 74 or 74′ detect an error from the respective ALUs 22 or 22′, the OR gate 69 will produce a signal 92 which causes the instruction retry mechanism for both processors 10 and 10′ to be initiated. In this manner a full synchronization of instruction retry operations can be maintained for the dual redundant processors 10 and 10′. Fig. 4 describes a state diagram of the checkpoint retry sequences both independent of and in relation with background diagnostic and maintenance services. A normal sequence 100 in Fig. 4 is defined as the execution of a single instruction. An error sequence 102 in Fig. 4 is defined as the error management actions taken following detection of an error. Typically, a detected fault activates a retry trap. Then the retry acknowledge initiates a restoration sequence. If the error is non-solid, the threshold counter 104 is updated. The counter may be used as an on-line indication of the processor performance. Error syndrome data will also be reported via an on-chip-monitor (OCM) to a diagnostic-and-maintenance-device (DxMD) for logging and thresholding. The saved checkpoint is then unloaded and single-stepped as part of the retry sequence. A retry sequence 106 in Fig. 4 is defined as the execution of a single instruction in single-step mode following the restoration phase. Error detection in this phase will result in the identification of the failed instruction. Successful execution of this sequence will establish a new checkpoint with the next instruction before resuming normal execution. A failed sequence 108 in Fig. 4 is the result of a solid failure or the faulty execution of a retry sequence. The instruction which was executing during the error will be reported via the OCM to the DxMD for logging and higher-level recovery actions. Single-step mode is reset, fault status will be reported, retry trap is deactivated, and retry acknowledge is activated. Then the system will generate an interrupt to invoke the software-controlled recovery actions. In the case of a single event upset (SEU), transient errors may experience a long duration which results in multiple nested interrupts. The software-controlled recovery actions will function as an upset event delay which can prevent further damage to operational resources. An interrupt sequence 110 in Fig. 4 is triggered by a solid fault or excessive retries (resulting in an overthreshold condition) to invoke the software-controlled recovery, which may be either on-line or background controlled. This also allows the processor to further delay operational processing with nested interrupts during a SEU (until the current SEU is cleared) to protect operational resources from erratic executions. Four different cases of checkpoint retry scenarios are described in Fig. 5. Typically, there are four cases where transient faults occur between "writes" due to the nature of continuous hardware checkers. Recurrence of the same transient fault over a number of retry attempts results in a solid fault (cases 2 and 4). Multiple transient faults are retried in a progressive manner such that recurrence of faults is gradually eliminated by incremental checkpoints once the single stepping operation has completed without error (cases 1 and 3). These scenarios describe the adaptive characteristic of checkpoint retry strategy in handling fault duration, fault isolation, and fault identification. Case 1 depicts the recovery of a single transient fault with a single retry sequence that results in a full recovery. Case 2 depicts the recovery of a single solid fault with multiple retry sequences that results in an interrupt to initiate next level recovery with the error information and the machine state just before the error occurrence. Case 3 depicts the recovery of multiple transient faults with a multiple retry sequence that results in a progressive recovery similar to a short duration SEU. Case 4 depicts the recovery of multiple transient faults with multiple retry sequences that results in an interrupt to initiate next level recovery with the error information and the machine state just before the error occurrence. This also describes some aspects of a long duration SEU.

Claims: In a data processor including an instruction memory (20) containing a sequence of executable instructions, and an arithmetic logic (22) unit which operates in response to said instructions to carry out arithmetic and logical operations, a checkpoint retry apparatus comprising: an instruction decoder (28) having an input coupled to an output of said instruction memory (20), for decoding instructions accessed therefrom, including a write decode output (30), an interrupt decode output (32), and an interrupt return decode output (34); an instruction memory address register (38) for storing the address of the next instruction to be accessed therefrom; a checkpoint address register (46) being coupled to said write decode output (30) of said instruction decoder (28) for storing the address of the first instruction following a write instruction accessed from said instruction memory (20), as a first type checkpoint address; said checkpoint address register (46) being coupled to said interrupt decode output (32) of said instruction decoder (28), for enabling the address of a first occurring instruction in an interrupt service routine called by an interrupt instruction to be loaded into said checkpoint address register (46) as a second type checkpoint address in response to accessing said interrupt instruction from said instruction memory (20); said checkpoint address register (46) being coupled to said interrupt return decode output (34) of said instruction decoder (28), for loading a first occurring instruction in an interrupted program after the occurrence of an interrupt instruction, into said checkpoint address register (46) as a third type checkpoint address, in response to accessing an interrupt return instruction from said instruction memory (20); an error checker (74) having an input coupled to an output of said arithmetic logic unit (22), for detecting errors occurring in said arithmetic logic unit (22); transfer means (69, 76) coupled to an output of said checkpoint address register (46) and coupled to an output of said error checker (74), for transferring the contents of said checkpoint address register (46) to said instruction memory address register (38) in response to said error checker (74) detecting an error in the operation of said arithmetic logic unit (22), the resulting contents of said instruction memory address register (38) becoming the checkpoint address value for retrying the sequence of instructions following said checkpoint address value, in response to the detection of said error; whereby checkpoint addresses are automatically determined to enable the retry of instruction sequences in response to the detection of an error. The data processor of claim 1 in which said arithmetic logic unit (22) has an associated status register (24) for storing the current status thereof, the checkpoint retry apparatus which further comprises: a shadow status register (80) coupled to said instruction decoder (28) for storing the contents of said status register (24) in response to a new checkpoint address value being stored in said checkpoint address register (46); said shadow status register (80) having an output thereof coupled to an input of said status register (24), for transferring the contents of said shadow status register (80) to said status register (24) when said error checker (74) detects the occurrence of an error in said arithmetic logic unit (22). The data processor of claim 1 or 2 which said arithmetic logic unit (22) has an associated plurality of general purpose registers (26) for storing current operand and address values, the checkpoint retry apparatus which further comprises: a plurality of shadow general purpose registers (94) coupled to said instruction decoder (28) for storing the contents of said plurality of general purpose registers (26) in response to a new checkpoint address value being stored in said checkpoint address register (46); said shadow general purpose registers (94) having an output coupled to an input of said general purpose registers (26) for transferring the contents of said shadow general purpose registers (94) to said general purpose registers (26) in response to said error checker (74) detecting the occurrence of an error in said arithmetic logic unit (22). The apparatus of at least one of claims 1 to 3 which further comprises: a single step instruction address incrementer (35) coupled to said error checker (74) and to said instruction memory address register (38), for sequentially incrementing the address register (38) and executing the instructions in a stepwise manner for a retry operation. The apparatus of at least one of claims 1 to 4 which further comprises: a second arithmetic logic unit (22′) having a control input coupled through a second instruction decoder (28′) to said instruction memory (20), and having its output coupled to a second error checker (74′); said second arithmetic logic unit (22′) executing the same sequence of instructions as said first arithmetic logic unit (22), simultaneously; the output of said first error checker (74) and the output of said second error checker (74′) being coupled to said transfer means (69), thereby enabling an error detected in either said first arithmetic logic unit (22) or in said second arithmetic logic unit (22′) to initiate the retry of the sequence of instructions which follow the instruction in said instruction memory (20) stored at said checkpoint address value. The data processor of claim 1 including a status register (24) for storing the current status of the arithmetic logic unit (22), and a plurality of general purpose registers (26) accessible by the arithmetic logic unit (22), for storing current operand and address values, the checkpoint retry apparatus comprising: said instruction decoder (28) further including an output (36) connected to a control input of said arithmetic logic unit (22); a first two input AND gate (40) having a first input connected to an output of said instruction memory address register (38) and a second input connected to said write decode output (30) of said instruction decoder (28); said checkpoint address register (46) having an input connected to the output of said first AND gate (40), for storing the address of the first instruction following a write instruction accessed from said instruction memory (20), as said first type checkpoint address; said instruction memory address register (38) having an input connected to an interrupt vector address means (48), for storing the address of the first instruction in a service routine which is pointed to by an interrupt instruction accessed from said instruction memory (20); said first AND gate (40) having said second input connected to said interrupt decode output (32) of said instruction decoder (28), for enabling the address of a first instruction in said service routine which has been transferred from said interrupt vector address means (48) to said instruction memory address register (38), to be loaded into said checkpoint address register as said second type checkpoint address in response to accessing an interrupt instruction from said instruction memory (20); an interrupt return address stack (66) for storing the address of a first instruction in an interrupted program which occurs after an interrupt instruction therein; a second AND gate (70) having a first input connected to an output of said address stack (66) and a second input connected to said instruction return decode output (34) of said instruction decoder (28), and an output connected to said checkpoint address register (46), for loading the first instruction in an interrupted program after the occurrence of an interrupt instruction, into said checkpoint address register (46) as said third type checkpoint address, in response to accessing an interrupt return instruction from said instruction memory (20); a third AND gate (76) having a first input connected to the output of said checkpoint address register (46) and a second input connected to an output of said error checker (74), for transferring the contents of said checkpoint address register (46) to said instruction memory address register (38) in response to said error checker (74) detecting an error in the operation of said arithmetic logic unit (22), the resulting contents of said instruction memory address register (38) being the checkpoint address value for retrying the sequence of instructions following said checkpoint address value, in response to the detection of said error; whereby checkpoint addresses are automatically determined to enable the retry of instruction sequences in response to the detection of an error. The apparatus of claim 6 which further comprises: a shadow status register (80) for storing the contents of said status register (24) when a new checkpoint address value is stored in said checkpoint address register (46); a fourth AND gate (82) having a first input connected to an output of said status register (24), a second input connected to said instruction decoder (28), and an output connected to an input of said shadow status register (80), for loading the contents of said status register (24) into said shadow status register (80) when said checkpoint address register (46) has a new checkpoint address value stored therein; said shadow status register (80) having an output thereof coupled to an input of said status register (24), for transferring the contents of said shadow status register (80) to said status register (24) when said error checker (74) detects the occurrence of an error in said arithmetic logic unit (22). The apparatus of claim 6 or 7 which further comprises: a plurality of shadow general purpose registers (94) for storing the contents of said plurality of general purpose registers (26) when a new checkpoint address value is stored in said checkpoint address register (46); said shadow general purpose registers (94) having an output coupled to an input of said general purpose registers (26) for transferring the contents of said shadow general purpose registers (94) to said general purpose registers (26) in response to said error checker (74) detecting the occurrence of an error in said arithmetic logic unit (22). The apparatus of at least one of claims 6 to 8 which further comprises: a single step instruction address incrementer (35) having an output connected to said instruction memory address register (38), for sequentially incrementing the instruction memory address register (38) and executing the instructions in a stepwise manner for a retry operation. The apparatus of at least one of claims 6 to 9 which further comprises: a second arithmetic logic unit (22′) having a control input coupled through a second instruction decoder (28′) to said instruction memory (20), and having its output connected to a second error checker (74′); said second arithmetic logic unit (22′) executing the same sequence of instructions as said first arithmetic logic unit (22), simultaneously; the output of said first error checker (74) and the output of said second error checker (74′) being connected through an OR logic function (69) to said third AND gate (76), thereby enabling an error detected in either said first arithmetic logic unit (22) or in said second arithmetic logic unit (22′) to initiate the retry of the sequence of instructions which follow the instruction in said instruction memory (20) stored at said checkpoint address. The apparatus of claim 5 or claim 10 wherein a second instruction memory address register (38′) is associated with said second arithmetic logic unit (22′), for storing a second value of the instruction address associated with said second arithmetic logic unit (22′); an address comparator (57) having a first input coupled to said first instruction address register (38) associated with said first arithmetic logic unit (22) and having a second input coupled to said second instruction address register (38′) associated with said second arithmetic logic unit (22′), for detecting when said first and said second instruction address registers (38, 38′) fail to have identical values for their respective addresses; isolation and swapping means (48. 49, 53, 53′, 65, 65′) having a control input coupled to the output of said address comparator, for isolating said first arithmetic logic unit (22) from said second arithmetic logic unit and performing validation tests thereon in response to said address comparator (57) determining that said first and said second instruction address values are not identical.

Inventors: KOGGE PETER M, RICKARD DALE A, SCHOENIKE ROBERT L, TRUONG KHOAN T, KOGGE, PETER M., RICKARD, DALE A., SCHOENIKE, ROBERT L., TRUONG, KHOAN T.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: G06F11
IPC codes: G06F11, G06F9