TDM switching matrix controller

Abstract: An improved multiplex controller allows fast, on demand allocation of variable length time slots in a voice/data communications system. The controller circuit directly maps a triangular connection matrix into hardware, thereby providing hardware parallelism. Each one of the coordinate points of the matrix is implemented with a flip-flop (L ij ). The inputs of the flip-flops are provided by a Port Activity Register (PAR), and the outputs of the flip-flops are fed into a Priority Encoder circuit (PE) which generates the address of a switch adapter with which a connection can be established. In this manner, a high speed dynamic allocator of variable length time slots which solves controller bottleneck problems in time critical systems is realized.

Description: The present invention relates to a controller for the fast allocation of variable length time-slots in voice/data switching systems according to the preamble of claim 1. This application is related in subject matter to copending application Serial No. 07/033,437 (U.S. Patent No. 4,845,704, published July 4, 1989), filed April 1, 1987, by Georgiou et al. for "Switching System for Integrated Voice/Data Communications", and assigned to the assignee of this application. The disclosure of application Serial No. 07/033,437 is incorporated herein by reference. With the recent growth in the use of computers, there has been an increase in demand for data. Much of this demand also comes from terminal locations which also have a need for the transmission of voice or, more broadly, for synchronous transmission. Thus, there is a demand for integrated switching of voice and data. Various schemes for the switching of voice and data have been developed. The most recent of which are time division switching schemes or a combination of time and space switching schemes. However, as will be described below, these methods provide low capacity integrated voice and data switching with high costs and poor growth potential. One system for integrating the switching of circuit and packet data using both time and space switching is described in U.S. Patent No. 3,766,322 to Moffet et al. The system described therein uses a number of cross-point switching matrices for the space switching, with one dedicated matrix to each data-rate category being switched. Both circuit and packet data can be transmitted through the same matrix if they are of the same data rate. Also, individual time division switches, dedicated to each data rate being switched, are used to perform the time switching. The system described in Moffet et al. is a relatively low speed and hence low capacity system. It can also be seen that any attempt to increase the number of switched data rate categories using an apparatus of the type described by Moffet et al. would result in a complex apparatus involving a large number of individual time and space switches. This complexity is a result of the need to dedicate a time and a space switch to each data rate category. To grow with increased demand, even without increasing the number of data rate categories, could also require a number of space and time switches because of the need to dedicate individual facilities for each data rate category. Thus, the Moffet et al. switching system, by requiring a number of dedicated matrices and time switches, makes system growth relatively difficult and facility costs high. Another switching mechanism for both circuit and packet switching is disclosed in U.S. Patent No. 4,413,337 to Dauphin et al. This mechanism uses only time division switching and not space division switching. Thus, the system disclosed therein offers a relatively low capacity system servicing in the vicinity of up to 256 64-kbit/sec circuit channels. A non-blocking switching network formed with VLSI crosspoint switching chips is disclosed in C.J. Georgiou: "Fault-tolerant crosspoint switching networks", 14th Int. Conf. on Fault Tolerant Computing, 20 June 1984, Kissimee, US, pages 240 - 245. This network can be dynamically reconfigured to operate under multiple chip failures without loss in connectivity or throughput performance. This is achieved by means of the flexibility provided by the one-sided organization of the on-chip connections. In the European Patent Application No. 86 116 339.2, Publication (A2) No. 0 224 241, "A self-routing switch node combining electronic and photonic switching" is presented. This node is responsive to an address received via an electrical sublink of an input link to establish both an electrical and a photonic connection for the communication of electrical and photonic data to an output link designated by the address. The switch node selects the designated output link from a set of similarly address designated output links all of which are equally capable of establishing the path. In switching systems for integrated voice/data communications, there is a need to establish the same connections over a number of consecutive time intervals. If the time slots are of fixed size, as is common in prior art switching systems, an allocation mechanism consisting of memory and counter with associated control logic usually suffices. However, modern switching system applications require fast, on demand allocation of variable length time slots in a communications system. It is therefore an object of the present invention to provide a high speed dynamic allocator or controller of variable length time slots which solves controller bottleneck problems in time critical systems and which allows the fast, on demand allocation of variable length time slots in a communications system. The solution of this object is described in the characterizing part of claim 1. According to the invention, there is provided a controller circuit for the fast allocation of variable length time slots in voice/data switching systems in which a "Selection Matrix" examines in parallel any potential connection combination. This selection matrix comprises a triangular matrix of cells which is directly mapped into hardware corresponding to all possible combinations of connections. Each one of the coordinate points of the matrix is implemented with a flip-flop. The inputs to the flip-flops are provided by a "Port Activity" register, and the outputs of the flip-flops are fed into an "Encoder" circuit which generates the address of a switch adapter with which a connection can be established. The foregoing and other objects, aspects and advantages of the invention will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: Fig. 1 is a block diagram of the overall apparatus used in the preferred embodiment of the invention; Fig. 2 is a block diagram of a circuit used to select an available adapter as used in a prior system; Fig. 3 is an illustration of a request mask of N bits as used in a prior system; Fig. 4 is an illustration of a triangular connection matrix illustrating the principles of the present invention; Fig. 5 is an illustration of the triangular connection matrix shown in Fig. 4 shaded to show the unavailability of certain connections due to the establishment of a connection; and Fig. 6 is a block and logic diagram showing the circuit according to the present invention used to select an available adapter. Referring now to the drawings, and more particularly to Fig. 1, there is shown the overall block diagram of the apparatus used in the preferred embodiment of this invention. A plurality of port attachments (not shown) are coupled to the input-output lines 501-532 of the switching matrix 50 through the port switch adapters 301-316, and processor attachments (also not shown) are coupled to the input-output lines 533-564 of the switching matrix 50 through the processor switch adapters 317-332. The port switch adapters 301-316 are used to handle both voice and data. The processor switch adapters 317-332 are used to handle data only. A port/processor attachment is also referred to as a node. The port/processor attachments are coupled to the switch adapters by buses 900. Each port/processor switch adapter can accommodate nodes of up to approximately 1,000 terminals. Each terminal could be connected to a data set or a telephone set. This embodiment uses 1024 terminals. The port switch adapters 301-316 are connected to the switching matrix 50 via input-output lines 501-532 which are dual lines for full duplex operation. The processor switch adapters 317-332 are connected to switching matrix 50 via input-output lines 533- 564 of the matrix, which lines are also dual lines for full duplex operation. The input-output lines for transmitting synchronous signals are referred to as circuit input-output lines, while input- output lines for the transmission of asynchronous signals are referred to as data input-output lines. Connections in switching matrix 50 are established by matrix controller 70. For maximum switching speed, a microprogrammed controller is preferred. The request for various connections in the switching matrix 50 are sent from the switch adapters 301-332 to the matrix controller 70 in the form of a data request mask or circuit request mask. The system shown in Fig. 1 provides a high-capacity integrated voice and data switching system which groups voice and data bound for the same destination into a frame and stores packets bound for the same destination into a packet memory. This system is disclosed in more detail in copending application S.N. 07/033,437. In that system, the framed and stored data are transmitted through the switching matrix 50. Thus, the frame length varies as circuit connections (i.e., telephone calls) are added or removed from the system. This mechanism has the advantage of requiring a single controller 70 only, which is also used to route regular packet (i.e., data) traffic. The routing of the frames, which is equivalent to allocating time-slots of variable length, must be handled within the time interval dictated by the voice sampling frequency, which is typically 125 microseconds. The present invention improves upon the circuit shown in Fig. 8 of the copending application S.N. 07/033,437. That circuit, reproduced in Fig. 2, is part of the controller 70 and is used to generate the address of a requested available adapter. The connection information is passed to the controller from each port by means of a request mask. The controller reads this information into request mask register 42, updates controller mask 46, and extracts the address of the destination port to be selected from the encoder circuit. If no connection is possible to any destination from the requesting port, the output of the encoder will be invalid (i.e., no address) and a controller cycle will be lost. Then the controller may attempt to service the next port in sequence. However, that port may also not have a corresponding free destination port and, thus, another controller cycle will be lost. Losing controller cycles, coupled with the transmission time of the request mask, may have serious implications on the overall performance of the controller. According to the invention disclosed in copending application S.N. 07/033,437, the time slot allocation is handled as follows. Each one of the N switch adapters 301-316 and 317-332 in Fig. 1 passes to the controller 70 a mask of N bits, as shown in Fig. 3, each bit indicating whether a connection is required with the corresponding adapter. This mask is compared against a register in the controller 70 containing the current status of the switch adapters, i.e., busy or not busy, and selects one of the not busy adapters for which a connection is requested. This method requires the expense of an N-bit wide bus between the controller and switch adapters for transferring the mask and may result in time delays associated with the mask transfer. The circuit according to the present invention is described as follows. In a system with N switch adapters, there are N(N-1) possible connection combinations. If we assume that the transfers A to B and B to A between two ports A,B can be done in one operation (full duplex mode), there are only N(N-1)/2 possible connections. Fig. 4 shows a triangular matrix of all connections for six ports; e.g., 6-1, 6-2, 6-3, etc. Once a connection between two ports has been established, a number of other possible connections are eliminated. In a triangular matrix representation of the possible connections, all matrix entries that lie on the row and column that contain the entry for the established connection are eliminated. Fig. 5, for example, shows the connection ports 5,2 and the resulting elimination of the other connections. Referring now to Fig. 6, there is illustrated an example of a four port switch. Each one of the coordinate points of the matrix is implemented with a flip-flop L ij . Inputs to the flip-flops are provided by bits P k of the Port Activity Register (PAR). The output of each flip- flop L ij is fed into a Priority Encoder (PE) circuit which generates the address of a switch adapter with which a connection can be established. In the serial circuit of Fig. 2, the circuit request mask is sent to the controller from each port that requests a connection. If there is no match of available ports (to be found through the comparison of the controller mask 46 with the request mask 42), a controller cycle will be lost. Then, in the next controller cycle, another port sends in its request mask, and so on until a match is found. By contrast, the parallel circuit of Fig. 6 finds, within a single cycle, any available connections and presents that information to the controller 70. This is done by means of the triangular matrix of Fig. 6, which represents all possible connections among ports P₁ . . . P n . Each flip-flop L ij represents whether a particular connection has been made or not. The circuit of Fig. 6 works as follows. At the beginning of a port service cycle (which we can define as the period during which all ports are serviced once), all flip-flops are cleared; i.e., all bits P k of the Port Activity Register PAR are 0 and the states of the flip-flops L ij are also at 0. Thus, the outputs of the NOR gates N ij are high and the Priority Encoder circuit PE selects port P₁ as the address of the next port to be serviced P1. The controller, then, uses address P1 to set the corresponding entry in the Port Activity Register PAR; i.e., a single bit. This disables input I₁ to the PE. Then, the PE selects a port from the remaining port, e.g., P₂, and sets its corresponding entry in PAR. This sets flip-flop L₁₂ to 1 because the AND gate at its input is enabled. The outputs of the NOR gates N 1j and N₃₄ are low. Thus, I₁ and I₂ are 0 and Priority Encoder circuit PE selects port P₂. The next step is for the controller to make the connection between P₁ and P₂ in the switching matrix and send a signal P₁, saying that it has been connected to P₂ (along with the address of P₂), and vice versa. Of course these operations could take place in parallel. When the connection between P₁ and P₂ is no longer needed, P₁ and P₂ send a disconnect signal to the controller 70, which in turn clears their corresponding entries in PAR. This clears entries I₁ and I₂ to the PE but does not clear flip-flop L ij (thus indicating that connection P₁-P₂ has been serviced). PE, then, selects another pair of available ports without losing any cycles. In Fig. 5, resetting the Port Activity Register PAR entries will result in the shaded areas being cleared up. When all the connections have been serviced, i.e., all flip-flops L ij are set, a service cycle has been completed. A new service cycle can then begin by clearing all flip-flops L ij . As will be appreciated from the foregoing description, no circuit request mask is passed to the controller from a port. Both request mask 42 and controller mask 46 in Fig. 2 are replaced by PAR, which is internally set. If some connections L ij need not be established, the corresponding flip-flops can be set at system initialization and be prevented from being reset by means of an additional control line, which would gate out their CL inputs. The delay of this circuit is extremely small as it involves only the signal propagation through a NOR gate, an OR gate and the Priority Encoder. This circuit can be easily implemented on a single chip, even for relatively large size systems. For example, a 64 port switch would require 64x63/2 or a 2016 matrix, which is well within the capabilities of the current VLSI technology. In contrast to the circuit shown in Fig. 2, the circuit of Fig. 6 contains the information of both the request and controller masks and, as a result, there is no need for passing that information between the switch ports and the controller. The circuit examines in parallel any potential connection combination and will find if a connection is possible from any port to any other port. Thus, at the beginning of a port service cycle, the output of the Priority Encoder PE will give the address of a free port, for example, port P₁. The controller will read the address P₁ and will set the corresponding bit in the "Port Activity" table. Then, the Priority Encoder PE will generate the address of another free port, for example, port P₂. The controller will connect these two ports in the switching matrix 50 and will send the address P₁ to port P₂ and the address P₂ to port P₁, along with a signal indicating that they are connected. P₁ and P₂ will transmit a frame to each other. Upon completion of transmission, they will indicate to the controller via a single line per port (or a time-multiplexed line) that the transmission has ended. The controller will then clear bits P₁ and P₂ in the Port Activity Register PAR. Going back to the port selection operation, after the controller has selected ports P₁ and P₂ as described above, it will select another pair of ports as indicated by the output of the priority encoder. A service cycle will end when all potential port connections have been made. This would be indicated by all flip-flops L ij being set. The detection of this condition could be made by feeding all outputs of the flip-flops L ij in Fig. 6 into a big NAND gate. A zero output of the NAND gate will indicate an end of a service cycle. The essence of this invention is that with variable length packets, the end of a packet transmission may occur asynchronously to the end of any other ongoing transmission. This means that the connected ports will be freed in a skewed manner, thus allowing only a subset of future connections to be made. The controller 70 can only make a fast determination on which port can be connected to another port if it has access to all connection information. This is provided by the triangular array of flip-flops and associated circuitry in Fig. 6. While the invention has been described in terms of a preferred embodiment in the environment of voice/data communications systems, those skilled in the art will recognize that the invention could be used in other fast packet switching systems and, moreover, can be practiced with modification within the scope of the appended claims.

Claims: Controller (70) of a communications switching system including a switching matrix (50) having an array of cross-points to interconnect a plurality of input-output lines (501 - 532) of the matrix, said input-output lines (501 - 532) of the matrix being connected to input-output ports of said switching system, for controlling said cross-points to make requested interconnections between said plurality of input-output lines (501 - 532), and port activity register means (PAR) for storing an indication of an active or inactive status of each of said input-output ports; characterized by selection matrix means connected to said port activity register means (PAR) for examining in parallel any potential connection combination to determine if a requested connection is possible between any port and any other port, said selection matrix means comprises a triangular matrix (Fig. 4) of N(N-1)/2 cells corresponding to all possible combinations of connections between said input-output ports; and by encoder means (PE) for receiving an output from said selection matrix means and generating an address of a free port. Controller as recited in claim 1, characterized in that each of said cells, except one, comprise a flip-flop (L ij ), an AND gate and a NOR gate (N ij ), said AND gate being connected to set said flip-flop (L ij ) in response to a selected pair of stages of said port activity register means (PAR) being set to a logic 1 level indicating that ports corresponding to those stages are active, said NOR gate (N ij ) receiving as inputs an output from said flip-flop (L ij ) and row and column inputs from said port activity register means (PAR), an output from said NOR gate (N ij ) being supplied to said encoder means (PE).

Inventors: GEORGIOU CHRISTOS JOHN, GEORGIOU, CHRISTOS JOHN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1989
Main classification: H04Q11
IPC codes: H04Q11