Multilayer printed-circuit board comprising surface-mounted memories

Abstract: A multilayer printed circuit memory board is designed and constructed so that the top and bottom layers contain repetitive integrated circuit (IC) chip component hole/pad and interconnection line patterns which are mirror images of one another. The board uses surface mounted techniques in which the integrated chip components of the memory array are mounted and soldered to both sides of the board thereby doubling the density or capacity of the memory board. The integrated circuit memory chips, mounted on the top and bottom of the board, are aligned with each other for sharing common holes or vias in which logically equivalent input signal connections are exchanged in a manner for reducing the number of holes and length of connective wiring.

Description: BACKGROUND OF THE INVENTION Field of Use The present invention relates to multilayer printed circuit boards and more particularly to the construction of multilayer circuit boards using surface mount technology. Prior Art The processes for producing complex multilayer printed circuit boards are well known in the art. Examples are disclosed in U.S. Patents Nos. 3,646,399 and 4,495,479. In these printed circuit board constructions a composite circuit board assembly is formed having a laminated-type arrangement including surface layers of thermally conducting material having spaced openings for location of recessed mounting means for the electrical components. The openings can be etched after lamination of a composite layer which provides the assembly means. Alternately, a thermally conducting layer can be laminated upon a substrate already having the openings and an overlayer of electrically conducting material which provides the assembly means can be pressed into the openings and thereafter etched to form the assembly sites. The IC components are set into these openings or holes and soldered to signal conductors on different layers through the plated through holes. Various techniques, including fine line technology, have been used for increasing the number of lines or connections per 6,45 cm² (= square inch). However, this results in cost increases. Furthermore, there are limitations on the number of components which can be mounted on the board surface because of the spacing requirements between components and hole sizes. The advent of surface mount technology allows IC components to be soldered to pads which are on the board's surface. Because surface mounted component packages are smaller than DIPs and do not require large holes for mounting, more such components can be mounted on the surface of the board. This results in increased board density. Since the components are mounted on the surface of the board, surface mount technology also permits IC components to be mounted on both sides of the board. While surface mount technology allows for greater flexibility in circuit boards, it becomes difficult to provide the proper interconnection between such components when they are mounted on both sides of the board. Furthermore, because of the greater such density of components on boards, testing is complicated due to the increase in the number of leads. This can give rise to new test equipment requirements, resulting in cost increases. Accordingly, it is a primary object of the present invention to provide a multilayer printed circuit board design which uses surface mount technology without a substantial increase in board layout complexity. It is a further object of the present invention to provide a multilayer printed circuit board design which uses surface mount technology and is compatible with standardized testing equipment. The above objects are achieved in the multilayer printed circuit board according to the characteristic features of claim 1. Further advantageous embodiments may be taken from the subclaims. The novel features of the invention together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying drawings. DESCRIPTION OF THE DRAWINGS Figure 1 is a perspective view of a multilayer printed circuit board designed and produced according to the teachings of the present invention. Figure 2 shows the top artwork pattern for producing the multilayer board of Figure 1. Figure 3 shows the bottom artwork pattern for producing the multilayer board of Figure 1. Figure 4 shows the cell pattern used to produce the patterns of Figures 2 and 3. Figure 5 is a top view of a DRAM integrated circuit package of the IC components which populate the multilayer printed circuit board of Figure 1. Figure 6 shows another cell pattern which can be used to produce patterns similar to those of Figures 2 and 3. Figure 7 is a top view of another DRAM integrated circuit package of the IC which populates a multilayer printed circuit board designed using the cell pattern of Figure 6. DESCRIPTION OF THE EMBODIMENT With reference to Figure 1, a multilayer printed circuit board designed and produced according to the teachings of the present invention will now be described. As seen from Figure 1, the multilayer board 10 consists of eight layers constructed using standard multilayer techniques with the exception of the top and bottom layers. These layers are constructed using surface mounted technology. That is, the electrical integrated circuit components 12 are affixed to the top and bottom surfaces of board 10 by means of surface pads which are soldered to the board surfaces. Also, filter capacitors 13 are surface-mounted between each row of components 12 on both sides of board 10. An additional pair of filter capacitors 11 are surface-mounted to the top surface of board 10. Additionally, board 10 includes a number of holes or vias which are constructed using plated through hole multilayer board technology. A pin and socket connector 14 could be mounted on the bottom of board 10 by press fitting the connector pins 16 into plated through holes in the board eliminating the need for soldering. The top and bottom layers are constructed from the artwork patterns of Figures 2 and 3. As seen from these Figures, both top and bottom layers include a minimum pattern which is repeated horizontally and vertically. This results in the array patterns consisting of rows C through N shown in Figures 2 and 3. When the patterns of Figures 2 and 3 are compared, it will be noted that the top and bottom patterns are mirror images of each other. As explained herein, the IC components soldered onto the top and bottom layers are interconnected as duplicate pairs as discussed herein. The minimum repeatable pattern for the top and bottom layers is shown in Figure 4. In the Figure, the larger size numbers and letters contained in the elliptical-shaped elements, such as 20, designate the pin/signal assignments for the electrical components mounted on the top surface of board 10. The smaller size numbers and letters contained in the same elliptical-shaped elements designate the signal assignments for corresponding components mounted on the bottom surface of board 10. The solid circles, such as 22, correspond to plated through holes contained in board 10. The dotted circles, such as 24, denote the start of the next minimum pattern. As indicated, the minimum pattern is repeated vertically and horizontally every 1,78 and 1,27 cm (.700 and .500 inches). This can be better seen from Figures 2 and 3. The heavy solid lines in Figure 4, such as lines 26, denote the printed wiring connections contained on the top surface of board 10. The dotted filled line areas, such as lines 28, denote the printed wiring connections contained on the bottom surface of board 10. The square-shaped elements, such as 30, denote filter capacitor pads. The specific pattern of Figure 4 includes the surface mounting pads and signal connections for two DRAM IC chips and two filter capacitors. The two DRAM IC chips and the filter capacitors are mounted on each side of board 10. The specific pattern is used for mounting the DRAM chip package shown in Figure 5. The DRAM chip package contains a 1-megabit DRAM device of the type designated as TMS4C1027, manufactured by Texas Instruments Inc. In Figure 5, the pad marked "D" corresponds to pin 1 of the DRAM chip package of Figure 5. Figure 6 shows the minimum repetitive pattern for a different shaped IC element, such as the DRAM chip package shown in Figure 7. The package contains a 256K DRAM device of the type designated as TMS4256 manufactured by Texas Instruments Inc. The minimum repetitive pattern is repeated horizontally and vertically to produce artworks similar to those shown in Figures 2 and 3. In Figure 6, the pad marked "8" corresponds to pin 1 of the package of Figure 7. Specific logically equivalent signals are exchanged so as to simplify the top and bottom layer connections as follows. That is, relative to the operation of a DRAM chip, the address signals designated on opposite sides of the package may be treated as logic equivalents. This means that the address signals in Figure 5 applied to pins 9 and 18, 10 and 17, 11 and 16 and 12 and 15 can be exchanged. This exchanging takes advantage of an operational characteristic of DRAM devices which allows the scrambling of input address signals without affecting normal chip operation. That is, as long as each input address pin is connected to receive a unique address bit, the DRAM device will still operate properly. As seen from Figure 4, by exchanging the above address signals, sets of chip address pins from top and bottom DRAM devices can be connected to the same holes positioned between or to the right side of the elliptical-shaped pads by short conductor lines. In the case of the top DRAM chip device of each pair, the input address signals A0 through A8 and A9 applied via input connector 14 are wired to pins 9-18 and 22, respectively which have the same address signal designations. However, the bottom DRAM chip device of each pair has the address input signals A0 through A3 wired to pins 18-15, respectively, and address input signals A5 through A8 wired to pins 12-9 respectively. For the reasons mentioned, this reassignment of address inputs does in no way affect the operation of the bottom DRAM chip devices. The address bit signal designations of the bottom DRAM chip devices are renamed or relabeled to conform to the address bit signal designations of the top DRAM chip devices as denoted by the number shown in the plated through hole of Figure 4 (e.g. "8" in circle labeled 22). The multilayer printed circuit board 10 is fabricated using the top and bottom artworks of Figures 2 and 3 as well as six other artworks for the internal layers. As is well known, a multilayer printed circuit board comprises several layers of printed wiring patterns, each mounted on a thin layer of insulating material and carefully aligned and molded together. Essentially, the board can be viewed as consisting of layers formed by a number of single sided and double sided printed circuit boards, each of which consist of a substrate material to which a thin laminate of conductive material, such as copper alloy, is bonded to one side. Utilizing conventional photographic techniques, the copper sides of the boards are photographed utilizing the appropriate artworks. That is, photosensitive material is applied to the copper laminate and the transparency of the circuit artwork is accurately positioned relative to the board. Next, the board layer is photographed and the image is developed utilizing techniques similar to those required to produce a snapshot or film. Then the boards are subjected to chemicals which etch away the copper in the exposed areas or unexposed areas the process to form the patterns of conductors and pads including pads encompassing holes previously drilled through the board. As previously discussed, the plated through holes are placed on the grid which provides a separation distance of 0,254 cm (.100 inch) between hole centers. Typically, the holes are 0,584 mm (23 mils) while the pads are 1,17 mm (43 mils). The bottom pad board layer is photographed utilizing the artwork of Figure 3. The intermediate board layers may also include plated through holes (buried vias) for making required internal connections. In the preferred embodiment, the second, third, sixth and seventh layers as used to transfer signals while the fourth and fifth layers provide ground and voltage planes. These layers generally include patterns of parallel lines. Following the molding of the several board layers, a solder paste is screened onto the component pad patterns of the board. The DRAM devices and other components (e.g. capacitors) are then placed on the surface of the top layer. The board is next heated in an infrared heater which reflows the solder paste. This connects the pins of the DRAM devices to the elliptical-shaped pads. The corresponding DRAM devices are placed on the bottom layer surface and the soldering step is repeated. From the foregoing description is is apparent that the multilayer printed circuit memory board is designed and constructed so that the top and bottom layers contain repetitive integrated circuit chip hole or pad and interconnect line patterns which are mirror images of each other. In the applied surface mounted technology the components are mounted on the board's surface on both sides which doubles the density of the memory board. A hole grid compatible with standard testing requirements with a spacing of 0,254 centimeters (0.1 inches) is utilized. This permits the placement of vias or holes on 0,254 cm (= .100 inch) centers which eliminates the need for additional test points and special ring out fixtures. The number of vias or holes required to access the internal layers of the multilayer board are reduced by sharing common vias between paired top and bottom IC components which carry logically equivalent signals. The vias or holes are distributed in rows along the grid lines so that there are substantially equal numbers in each row. This simplifies internal connections by reducing the number and distances. It also permits a reduction in the number of layers required for interconnections. In the described embodiment, the surface mounted components are high density memory chips. Each such chip is connected to receive a number of address signals. It is recognized that notwithstanding the assignment of unique address designations, certain sets of address signals may be treated as logical equivalents based upon an operational characteristic of such memory chips. This characteristic is that the set of input addresses may be scrambled without affecting the normal operation of the devices. The logically equivalent address signals are exchanged so as to simplify the top and bottom layer patterns and to reduce the number of vias or holes as mentioned above. By designing and producing a multilayer memory board as described above, it is possible to utilize existing technology in the development of high density memory systems. Also, the same standard multilayer printed circuit board design can provide a wide range of densities through the use of memory pacs or memory daughter boards designed and constructed according to the above described technical teaching to accomodate high density memory chips. The so fabricated high-density multilayer printed circuit boards also allow the use of testing equipment which is used for testing standard multilayer boards. The pattern is repeated so as to provide a spacing which facilitates board inspection for solder defects and board repairs with no increase from the standard multilayer board size. Moreover, while the disclosed embodiment includes eight layers, it is possible to use less layers to provide the required interconnections without having to employ fine line process techniques in the construction of the signal layers. It will be appreciated that modifications may be made to the above described embodiment. For example, the teachings of the present invention may be used in conjunction with other types of DRAM devices. Also, the teachings are applicable to other types of IC packages which can be mounted on a board surface using repeatable patterns.

Claims: A multilayer printed circuit board comprising a plurality of integrated circuit packages (12) containing devices, each having a plurality of input pins (9, 18; 10, 17; 11, 16; 12, 15; 13, 14 of Fig. 5) for receiving a corresponding number of signals, said board comprising a top layer, a bottom layer and a number of intermediate layers, characterized in that said top and bottom layers have repetitive patterns of pads (20 of Fig. 4) which patterns are mirror images of each other and the patterns of pads on the top layer being mirror images of the patterns of pads on the bottom layer; each of said pad patterns includes pads for plated through holes (22 of Fig. 4) contained in said circuit board wherein a hole grid with a predetermined spacing between the centers of said holes is utilized; a plurality of conductors (26, 28 of Fig. 4) of minimum length connect predetermined ones of said pads to said plated through hole pads on said top and bottom layers of said board so that a plurality of said plated through holes are connected by corresponding ones of said conductors to be shared between corresponding integrated circuit packages mounted on said top and bottom layers; and said plurality of said integrated circuit packages is surface mounted on said pads on said top and bottom layers of said board in paired fashion for enabling an exchange of input pin signal assignments based upon an operational characteristic of said devices included in said packages so as to reduce the number of plated through holes. The board of claim 1 wherein said devices are high density DRAM integrated circuits. The board of claim 1 wherein said devices comprise addressable memories. The board of claim 1 wherein a plurality of said input signals are address signals and wherein said operational characteristic of said devices is such that said address signals applied to said input pins by said pads can be reassigned without interferring with the normal operation of said devices included in said plurality of integrated circuit packages. The board of claim 1 wherein a substantially equal number of said plated through holes in said board are distributed in rows so as to simplify internal connections. The board of claim 5 wherein said rows of holes are separated by a predetermined spacing selected to permit the use of standard test equipmant. The board of claim 1 wherein said pads (0-3, 4-9) on which said integrated circuit packages are mounted in paired fashion are in contact with pins of said devices (A0-A9) which are address input terminals of said addressable memories. The board of claim 1 wherein said board is of multilayer construction and pairs of said plurality of integrated circuit packages are mounted in the same positions above and below one another respectively on said top and bottom layers of said board using surface mount construction. The board of claim 1 wherein said repetitive pattern of pads is repeated to provide a spacing for facilitating access to check for defects. The board of claim 6 wherein said spacing is 0,254 centimeters (0.1 inches) .

Inventors: FISHER EDWIN P, QUATTRINI VICTOR L, FISHER, EDWIN P., QUATTRINI, VICTOR L.
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS INC.
Application year: 1989
Main classification: H05K1
IPC codes: H05K1, G11C5