Programmable logic device

Abstract: A programmable logic device includes: a programmable AND array (14); an OR array (17) operatively connected to the AND array; a plurality of external terminals (I/O₁∼I/O n ); and a plurality of cell blocks (12₁∼12 n ) operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, each receiving two output signals (OR1,OR2) from the OR array and outputting a signal to a corresponding external terminal based on the two output signals. By controlling an input/output of an input signal and an internally produced signal and a feedback thereof to the AND array, it is possible to realize various logic constitutions and develop a degree of freedom of the logic design in the entire device.

Description: The present invention relates to a programmable logic device (PLD). More particularly, it relates to a PLD including a cell block, hereinafter referred to as a macro cell, controlling a logic connection of an input/output of an input signal and an internally produced signal and a feedback thereof in accordance with contents stored in a programmable non-volatile memory. For example, in a PLD such as a programmable logic array (PLA), a programmable array logic (PAL; registered trade mark) or the like, the above macro cell is provided to control a logic connection of the input/output of signals and the feedback thereof, using programmable non-volatile memory elements such as an electrically programmable read only memory (EPROM) and programmable switches controlling ON/OFF operations thereof and selecting each signal based on the contents stored in the programmable non-volatile memory elements, and thus realizes various logic constitutions. It is ideally desirable that the PLD can realize any logic circuit by a single IC chip. Recently, the PLD products have been classified into several tens of types due to a variety of constitutions or structures. In view of this point, it is proposed that a single chip (PLD) including several macro cells be constituted such that it can be replaced with a plurality of types of chips. However, since a known conventional macro cell has an extremely simple constitution, it cannot realize a variety of control functions and, accordingly, it enables a replacement of only a few forms. On the other hand, to realize a PLD including such a macro cell having an extremely simple constitution that can be replaced with a plurality of forms of chips, a logic designing in a programmable AND array and a programmable OR array must be carefully effected or devised. This leads to a restriction in the degree of freedom of the logic design in the entire PLD and a complication of the logic design per se, and thus is not preferable. An example of the known macro cell is disclosed in EPLD Handbook, 1985, p.20 - p.28, published by ALTERA Corp., and an explanation thereof will be given later. Programmable logic arrays are well known. For example as disclosed in US-A-4422072. The programmable logic array disclosed in this specification includes a programmable AND gate array. The system also contains an OR array which outputs signals to cell blocks. These generate outputs based on the signals received from the OR array. Another programmable logic array is disclosed in EP-A-0307912, this specification falling within Article 54(3) of the European Patent Convention and therefore not being relevant for obviousness considerations. The logic array disclosed in this specification has a very limited capability and is therefore unsuitable for many applications. An object of the present invention is to provide a programmable logic device (PLD) which can provide a macro cell having a variety of functions and thus realize various logic constitutions, while expanding a degree of freedom of the logic design in the entire PLD. According to the present invention, a programmable logic device comprises: a programmable AND array; a plurality of external terminals; an OR array operatively connected to said AND array and divided into a number of blocks corresponding to the number of said external terminals; and a cell block provided respectively for each of the plurality of external terminals, each cell block including a logical gate for receiving two output signals from a corresponding block of the OR array independently of other cell blocks, and selecting means for selecting an output signal from the group consisting of one of said two output signals and an output of the logical gate and outputting the selected signal to a corresponding external terminal, said selecting means including: a first programmable register responsive to one of first and second clock signals, for selectively latching one signal from the group consisting of the output of the logic gate and the two output signals of the OR array; a second programmable register responsive to one of said first and second clock signals, for selectively latching the corresponding signal from among the group consisting of said two output signals of the OR array, the output of the logic gate and an external input signal fed to one of said plurality of external terminals, and for feeding the latched signal back to said AND array; a tristate buffer responsive to an output enable control signal, for feeding an output signal of said first programmable register to said one external terminal; and a third programmable register responsive to the output enable control signal and one of said first and second clock signals, for effecting a tristate control for said tristate buffer. Other objects and features of the present invention will be described hereinafter in detail by way of preferred embodiments with reference to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating an entire constitution of a prior art PLD; Fig. 2 is a circuit diagram schematically illustrating a constitution of a prior art macro cell; Fig. 3 is a block diagram illustrating an entire constitution of the PLD as an embodiment of the present invention; Fig. 4 is a circuit diagram illustrating a constitution of the macro cell shown in Fig. 3; Figs. 5A to 5D are diagrams illustrating a circuit constitution and various examples of the connection of the FF cell shown in Fig. 4; Fig. 6 is a circuit diagram illustrating a constitution of the two-input type switch shown in Fig. 4; and Fig. 7 is a block diagram illustrating an entire constitution of the PLD as another embodiment of the present invention. For a better understanding of the preferred embodiment of the present invention, the problems of the prior art will be explained with reference to Figs. 1 and 2. Fig. 1 illustrates an entire constitution of a prior art PLD. In Fig. 1, references I/O₁ ∼ I/O n denote input/output (I/O) terminals; references I₁, I₂ input terminals receiving external clock signals CLK1, CLK2, respectively; reference 1 an I/O buffer (IOB); references 2₁∼ 2 n macro cells (MC₁∼MC n ); reference 3 a feedback input buffer (FIB); reference 4 a programmable AND array 14; reference 5 an input buffer (IB); reference 6 a sense amplifier (S/A) and driver circuit; reference 7 a programmable OR array; and reference 8 a sense amplifier (S/A) circuit, respectively. According to this constitution, each of the macro cells 2₁ ∼ 2 n is allocated for each of the output term lines in the OR array 7 on a one-to-one basis. Namely, each of the macro cells receives one output signal from the OR array 7. The output signal is employed for determining an output logic of the corresponding macro cell. Figure 2 schematically illustrates a constitution of a prior art macro cell. The illustration shows the macro cell contained in the device, EP300, by ALTERA Corp. In Fig. 2, reference 51 denotes a macro cell; reference 52 a schematic diagram of an AND array, product term lines and an OR array; reference 53 an I/O terminal of a chip; reference 54 a tristate buffer responsive to an output enable signal OE; reference 55 a gate constituting a portion of the AND array; and reference 56 a buffer used for feeding a signal back to the AND array. The macro cell 51 is mainly constituted by a D-type flip-flop 57 latching an output of the OR array, an output select circuit 58 selecting one of the outputs of the flip-flop and the output of the OR array and a feedback select circuit 59 selecting one of the outputs of the flip-flop, the output of the OR array and an external input signal. In this constitution as well, the macro cell 51 receives one output signal from the OR array. Also, the constitution of the macro cell 51 is relatively simple. Accordingly, to realize that a PLD including the macro cell 51 that can be replaced with a variety of different PLDs, the logic design in the AND and OR arrays 52 must be carefully devised. This leads to a restriction in the degree of freedom of the logic design in the entire PLD and a complication of the logic designing per se. To prevent this drawback, for example, an approach is considered in which the number of product term lines in the AND and OR arrays 52 is increased to facilitate the logic design. According to this approach, however, another problem occurs in that the space occupied by the arrays on the chip is increased due to the increase in the number of product term lines. Figure 3 illustrates an entire constitution of the PLD as an embodiment of the present invention. The PLD of the present embodiment is in the form of a chip having twenty four pin terminals, which consist of twenty input/output (I/O) terminals I/O₁ ∼ I/O n , two input terminals I₁, I₂, receiving external clock signals CLK1, CLK2, respectively, and two power supply terminals receiving voltages Vcc, Vss, (see Fig. 6), respectively. Referring to Fig. 3, a signal input from each of the I/O terminals I/O₁∼ I/O n is fed via an I/O buffer (IOB) 11 to a corresponding macro cell (MC₁∼MC n ) 12₁ ∼12 n . The macro cells 12₁ ∼12 n feeds the external input signals or feedback signals internally produced (stated later) via a feedback input buffer (FIB) 13 to a programmable AND array 14. Also, the clock signals CLK1, CLK2 are fed via an input buffer (IB) 15 to the AND array 14. The AND array 14 has a non-volatile memory cell such as an EPROM cell provided at each intersection between a plurality of input term lines and a plurality of product term lines. In the AND array 14, black and round marks shown at some of the intersections indicate program points. For example, where a certain product term line includes three program points, a signal corresponding to a logical product of the three input signals appears on the corresponding product term line. Each output signal of the AND array 14 is fed via the corresponding product term line to a sense amplifier (S/A) and driver circuit 16, amplified and then fed to a programmable OR array 17. The OR array 17 has the same memory cell as the AND array 14 provided at each intersection between the plurality of product term lines and a plurality of output term lines. In the same manner as in the AND array 14, black and round marks indicate program points. For example, where a certain output term line includes two program points, a signal corresponding to a logical addition of the two input signals from the corresponding product term lines appears on the corresponding output term line. Each output signal of the OR array 17 is fed via the corresponding output term line to a sense amplifier (S/A) circuit 18, amplified and then fed to the macro cells 12₁∼12 n . In this case, each of the macro cells 12₁∼12 n receives three output signals OE, OR1 and OR2 from the OR array 17. The output signal OE is employed as an output enable control signal independently allocated to each macro cell, while the output signals OR1 and OR2 are employed for determining an output logic of the corresponding macro cell. The signals OR1 and OR2 are separated into a feedback signal and an output signal based on the output logic of the corresponding macro cell. The feedback signal is fed via the feedback input buffer 13 to the AND array 14 as described above, while the output signal is output via the I/O buffer 11 to the corresponding I/O terminal I/O₁∼ I/O n . Also, each of the macro cells 12₁ ∼12 n receives the clock signals CLK1, CLK2, and a set signal SET and a clear signal CLR from the S/A circuit 18. Reference 19 denotes a power-on load circuit (PLC) including a matrix (not shown) in which a plurality of non-volatile memory elements such as EPROMs are arrayed. The power-on load circuit 19 has the function of reading the contents stored in the matrix when the power is turned ON and loading the read contents into registers (not shown) in each of the macro cells 12₁∼12 n . Each of the macro cells 12₁∼12 n has the function of controlling ON/OFF operations of a plurality of switches (not shown) and a selection of each signal based on the contents loaded into registers and thus controlling a logic connection of the input/output of each signal and the internal feedback so as to realize various logic constitutions. Next, a constitution of the macro cell shown in Fig. 3 will be explained with reference to Fig. 4. In Fig. 4, reference 10 denotes an I/O terminal corresponding to each of the terminals I/O₁∼ I/O n shown in Fig. 3 and references 20A,20B denote programmable flip-flop (FF) cells. The FF cell is constituted such that it can be adapted to any type of Flip-Flop sach as a JK-type, a D-type or a T-type, as described later. Reference 30 denotes a D-type flip-flop, which has a function of controlling the output enable signal OE and thus switching an input cycle and an output cycle. References 21∼29, 31, 32 and 33 denote switches (SW) which can be programmed by a user. Among these switches, each of the two-input type switches 21∼29 selects one of two signals applied to its inputs a,b in accordance with a logic level of the corresponding control signal C1 ∼C9 of one bit and outputs the selected signal to its output c. Also, the three-input type switch 31 selects one of three signals applied to its input a∼c in accordance with each logic level of the corresponding control signals C11,C12 of two bits and outputs the selected signal to its output d. Also, the four-input type switch 32 selects one of four signals applied to its inputs a∼d in accordance with each logic level of the corresponding control signals C21,C22 of two bits and outputs the selected signal to its output e. Furthermore, the seven-input type switch 33 selects one of seven signals applied to its inputs a ∼g in accordance with each logic level of the corresponding control signals C31∼C33 of three bits and outputs the selected signal to its output h. Note, the control signals applied to each switch (SW) are fed via registers (not shown) from the power-on load circuit 19. Reference 34 denotes an exclusively-OR gate; reference 35 an inverter; reference 36 a tristate buffer; reference 37 a NOR gate; reference 38 an inversion input type buffer; and reference 39 a buffer. In the present embodiment, each of the macro cells 12₁ ∼12 n receives: two output signals OR1 and OR2 from the OR array 17; two external clock signals CLK1 and CLK2; the output enable signal OE from the OR array 17; the set signal SET and the clear signal CLR from the S/A circuit 18; and an active-low input enable signal IE internally produced based on the output enable signal OE. The output signal OR1 of the OR array 17 is fed to one input of the exclusively-OR gate 34, one input a of the switch 27, one input a of the switch 32, one input B of the FF cell 20B and one input a of the switch 33. On the other hand, the output signal OR2 is fed to another input of the exclusively-OR gate 34, one input B of the FF cell 20A, one input a of the switch 31 and one input b of the switch 33. Also, the output signal XOR of the exclusively-OR gate 34 is fed to one input b of the switch 27, one input b of the switch 31, one input b of the switch 32 and one input e of the switch 33. Also, the clock signals CLK1,CLK2 are fed to the inputs a,b of the switch 21(22), respectively. The switch 21 outputs a clock signal CLKA from its output c, which is fed to a clock input CK of the D-type FF 30 and a clock input of the FF cell 20A. On the other hand, the switch 22 outputs a clock signal CLKB from its output c, which is fed to a clock input of the FF cell 20B. The output enable signal OE of the OR array 17 is fed to the data input D of the D-type FF 30 and one input b of the switch 29. The output Q of the D-type FF 30 is connected to one input a of the switch 29 and the output c of the switch 29 is connected to the control input of the tristate buffer 36. Each input a of the switches 23,24 receives the set signal SET and each input b thereof is grounded. The switch 23 (24) outputs a set signal SETA (SETB) from its output c, which is fed to the FF cell 20A (20B). Also, each input a of the switches 25, 26 receives the clear signal CLR and each input b thereof is grounded. The switch 25 (26) outputs a clear signal CLRA (CLRB) from its output c, which is fed to the FF cell 20A (20B). The output c of the switch 27 is connected to another input A of the FF cell 20A and the output Q (output signal Q1) of the FF cell 20A is connected to one input c of the switch 32 and one input c of the switch 33. The output e of the switch 32 is connected to one input a of the switch 28 and connected via the inverter 35 to another input b of the switch 28. The output c of the switch 28 is connected via the tristate buffer 36 to the I/O terminal 10. On the other hand, the output d of the switch 31 is connected to another input A of the FF cell 20B and the output Q (output signal Q2) of the FF cell 20B is connected to one input d of the switch 33. One input of the NOR gate 37 is connected to the I/O terminal 10 and another input thereof receives the input enable signal IE . The output signal of the NOR gate 37 is fed via the buffer 38 to one input f of the switch 33 and one input c of the switch 31. Also, the input g of the switch 33 is grounded and the output h is connected via the buffer 39 and the feedback input buffer (not shown) to the AND array 14. Next, a circuit constitution of the FF cell shown in Fig. 4 and various examples of the connection thereof will be explained with reference to Figs. 5A to 5D. As shown in Fig. 5A, the FF cell employed in the present embodiment is constituted by a flip-flop (FF) 20a, two two-input type switches 20b,20c and an inverter 20d. The constitution and operation of the switches 20b, 20c are the same as those of the switches 21 ∼29 shown in Fig. 4 and thus the explanation thereof is omitted. Assuming that the switch 20b (20c) selects the input a when the control signal C1′(C2′) is at "L" level and selects the input b when the control signal C1′(C2′) is at "H" level, various types of FFs are constituted according to each logic level of the control signals C1′,C2′. For example, when the control signal C1′ is at "H" level an the control signal C2′ is at "L" level, the switch 20b selects the input b and the switch 20c selects the input a. Accordingly, the form of the connection constitutes a JK-type FF as shown in Fig. 5B. In the same manner, when the control signal C1′ is at "L" level and the control signal C2′ is at "H" level, the form of the connection constitutes a D-type FF as shown in Fig. 5C. Also, when the control signals C1′,C2′ are both at "L" level, the form of the connection constitutes a T-type FF as shown in Fig. 5D. Next, a constitution of the two-input type switch shown in Fig. 4 will be explained with reference to Fig. 6. In Fig. 6, reference 40 denotes an inverter; references 41,42,45 and 46 p-channel transistors; references 43,44,47 and 48 n-channel transistors; reference 49 an inverter; references a and b inputs (signals); reference c an output (signal); and reference Ci a control signal of one bit. The transistors 41∼44 and 45 ∼48 are connected in series between a higher voltage power supply line Vcc and lower voltage power supply lines Vss, respectively. Each drain of the transistors 42,43 and each drain of the transistors 46,47 are commonly connected via the inverter 40 to the output c. Each gate of the transistors 42,43 is commonly connected to the input a, and each gate of the transistors 46,47 is commonly connected to the input b. Also, the control signal Ci is fed to each gate of the transistors 41,48 and fed via the inverter 49 to each gate of the transistors 44,45. In the constitution of Fig. 6, when the control signal Ci is set to either "L" level or "H" level, one of the input signals a and b is selected to form the output signal c. When the control signal Ci is at "L" level, the transistor 41 is brought an to ON state and the transistor 48 is brought to an OFF state. Also, since the output signal of the inverter 49 is at "H" level, the transistor 44 is brought to an ON state and the transistor 45 is brought to an OFF state. In this case, since the output sides of the transistors 46,47 are brought to floating states, the input signal b becomes invalid and the input signal a becomes valid. Accordingly, when the input signal a is at "L" level, the transistor 42 is turned ON, so that the level at the input end of the inverter 40 is raised to "H" level. As a result, the level of the output signal c is lowered to "L" level. Inversely, when the input signal a is at "H" level, the transistor 43 is turned ON, so that the level of the output signal c is raised to "H" level. On the other hand, when the control signal Ci is at "H" level, the ON/OFF operation of each transistor is carried out inversely to the case when the control signal Ci is at "L" level. Namely, the input signal a becomes invalid and the input signal b becomes valid. Accordingly, when the input signal b is at "L" level, the transistor 46 is turned ON, so that the level of the output signal c is lowered to "L" level. Inversely, when the input signal b is at "H" level, the transistor 47 is turned ON, so that the level of the output signal c is raised to "H" level. According to the constitution of the macro cell employed in the present embodiment, the FF cell 20A mainly used for the output of signals and the FF cell 20B used for the feedback thereof are separately provided and the selection of the input mode or the output mode of signals is effected by the associated operation of the D-type FF 30, switch 29, tristate buffer 36 and NOR gate 37. As a result, it is possible to independently control the input of the input signal, the output of the internally produced signal and the feedback thereof to the AND array. Also, since the FF cells 20A, 20B can be modified to any type of JK-type, D-type or T-type Flip-Flop in accordance with use, it is possible to remarkably develop the function of the entire macro cell, as compared with the prior art macro cell. Also, since each macro cell receives two output signals OR1,OR2 from the OR array 17 and the output of the exclusively-OR gate 34 responsive to the output signals OR1,OR2 can be utilized when necessary, it is possible to expand a degree of freedom of the logic design without increasing the number of product term lines. Furthermore, since two clock signals CLKA, CLKB are prepared, it is convenient when the latching of the input signal and that of the output signal are carried out simultaneously or in different phases. Also, whether or not the set signals SETA,SETB and the clear signals CLRA,CLRB are fed to the FF cells 20A,20B, respectively, can be freely selected by suitably controlling the switches 23∼26. Although the OR array 17 is a programmable one in the above-described embodiment, it is not restrictive. For example, a fixed wiring type OR array may be used instead. Also, although each of the macro cells receives the output enable control signal OE from the OR array 17 in the embodiment of Fig. 3, the signal OE need not be output from the OR array. Figure 7 shows an example of the constitution in which each macro cells does not receive the signal OE.

Claims: A programmable logic device comprising: a programmable AND array (14); a plurality of external terminals (I/O₁ - I/O n , 10); an OR array (17) operatively connected to said AND array and divided into a number of blocks corresponding to the number of said external terminals; and a cell block (12i) provided respectively for each of the plurality of external terminals, each cell block including a logical gate (34) for receiving two output signals (OR1, OR2) from a corresponding block of the OR array independently of other cell blocks, and selecting means for selecting an output signal from the group consisting of one of said two output signals and an output of the logical gate and outputting the selected signal to a corresponding external terminal (10), said selecting means including: a first programmable register (20A) responsive to one of first and second clock signals (CLKA, CLKB), for selectively latching one signal from the group consisting of the output of the logic gate (34) and the two output signals (OR1, OR2) of the OR array (17); a second programmable register (20B) responsive to one of said first and second clock signals, for selectively latching the corresponding signal from among the group consisting of said two output signals of the OR array (17), the output of the logic gate (34) and an external input signal fed to one (10) of said plurality of external terminals, and for feeding the latched signal back to said AND array; a tristate buffer (36) responsive to an output enable control signal (OE), for feeding an output signal of said first programmable register to said one external terminal (10); and a third programmable register (30) responsive to the output enable control signal and one of said first and second clock signals, for effecting a tristate control for said tristate buffer. A device as set forth in claim 1, wherein said selecting means further comprises a plurality of programmable switches (21-28, 31-33), each switch being connected to at least one of a control terminal, a plurality of input terminals, and an output terminal in one of said first to third programmable registers and said tristate buffer, each switch being switched in accordance with the contents stored in a programmable non-volatile memory means (19), thereby controlling the inputting of said external input signal, the outputting of an internally produced signal, and the feedback of the external input signal or the internally produced signal to said AND array. A device as set forth in claims 1 or 2, wherein the logical gate (34) is an exclusively-OR gate. A device according to any of the preceding claims, wherein each of said first and second programmable registers (20A,20B) comprises a JK-type flip-flop (20a) and a plurality of programmable switches (20b, 20c) operatively connected to said JK-type flip-flop, and switches connections of said switches in accordance with the contents stored in said programmable non-volatile memory means to constitute one of a JK-type flip-flop, a D-type flip-flop and a T-type flip-flop. A device according to any of the preceding claims, wherein the third programmable register is a D-type flip-flop (30) latching the output enable control signal (OE) fed from said OR array in response to said first clock signal (CLKA) and selects the output signal of said D-type flip-flop or said output enable control signal to control the input/output of said input signal and said internally produced signal. A device according to any of claims 2 to 5, wherein the contents stored in said programmable non- volatile memory means (19) constitute a plurality of control signals for switching connections of said plurality of programmable switches. A device as set forth in claim 6, wherein said switch circuit includes a programmable switch (27) selecting one (OR1) of two output signals fed from said OR array or the output signal (XOR) of said exclusively-OR gate in response to a control signal (C7) and feeding the selected signal to said first programmable register (20A), and a programmable switch (31) selecting another (OR2) of two output signals fed from said OR array, the output signal (XOR) of said exclusively-OR gate or the input signal fed in externally in response to another control signal (C11, C12) and feeding the selected signal to said second programmable register (20B). A device as set forth in claim 6, wherein said switch circuit includes a first programmable switch (32) selecting one (OR1) of two output signals fed from said OR array, the output signal (XOR) of said exclusively-OR gate or the output signal (Q1) of said first programmable register in response to a control signal (C21,C22), and a second programmable switch (28) selecting the signal selected by said first programmable switch or the inverted signal in response to another control signal (C8) and outputting the selected signal to the third programmable register. A device as set forth in claim 6, wherein said switch circuit includes a programmable switch (33) responsive to a control signal (C31-C33), selecting one of two output signals (OR1, OR2) fed from said OR array, the output signals (Q1, Q2) of said first and second programmable registers, the output signal (XOR) of said exclusively-OR gate and the input signal fed from the external. A device as set forth in claim 6, wherein said switch circuit includes a pair of programmable switches (21, 22), each selecting one of two different external clock signals (CLK1, CLK2) in response to a control signal (C1, C2), a pair of clock signals (CLKA, CLKB) selected by said pair of programmable switches being used as said first and second clock signals. A device as set forth in claim 6, wherein said switch circuit includes a pair of programmable switches (23, 24), each selecting a feeding or a prohibition of said feeding of a set signal (SETA, SETB) for bringing the corresponding programmable register (20A, 20B) to the set state in response to a control signal (C3, C4). A device as set forth in claim 6, wherein said switch circuit includes a pair of programmable switches (25, 26), each selecting a feeding or a prohibition of said feeding of a clear signal (CLRA, CLRB) for bringing the corresponding programmable register (20A, 20B) to the reset state in response to a control signal (C5, C6).

Inventors: HIGUCHI MITSUO, NAKAOKA YASUHIRO, OGURA KIYONORI, SHIMBAYASHI KOHJI, HIGUCHI, MITSUO, NAKAOKA, YASUHIRO, OGURA, KIYONORI, SHIMBAYASHI, KOHJI
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1989
Main classification: H03K19
IPC codes: H03K19, H03K3, H03K17