TTL-ECL level converting circuit

Abstract: A TTL-ECL converting circuit comprises a Schottky barrier diode (D₁) having a cathode connected to an input terminal (IN) for a TTL signal and an anode connected to a first connection node, a resistor (R₁) having its one end connected to a high voltage supply line (V CC ) and its other end connected to the first connection node, a first transistor (Q₁) having a collector connected to the high voltage supply line (V CC ), a base connected to the first connection node and an emitter connected to a second connection node, a level shift resistor (R₃) having its one end connected to the second connection node and its other end connected to a third connection node, a level shift diode (D₂) having its cathode connected to the third connection node and its anode connected to a fourth connection node, a constant current source (Ics) having its end connected to the fourth connection node and its other end connected to a low voltage supply line (V EE ), a second transistor (Q₂) having a collector connected to the first connection node, a base connected to the third connection node and an emitter connected through another resistor (R₂) to an intermediate voltage supply line (GND), and an emitter follower (Q₃) connected between the intermediate voltage supply line (GND), and the low voltage supply line (V EE ) and having an input connected to the fourth connection node and an output connected to an output terminal for an ECL signal.

Description: The present invention relates to a TTL-ECL converting circuit, and more specifically to a TTL-ECL converting circuit which operates at a high speed and which is free from self-oscillation. Recently, ECL (emitter coupled logic) circuits in the form of an integrated circuit having a high integration density have been used in various fields requiring high speed operation, for example, so-called main-frames, communication instruments, LSI testers, measuring instruments, etc. In many cases, however, the above mentioned instruments are provided, as a memory, with an inexpensive standard semiconductor memory having a TTL (transistor-transistor logic) interface. Therefore, interfaces for the ECL integrated circuit having a high integration density have been provided with TTL-ECL level converting circuits and therefore, both an ECL interface and a TTL interface have been assembled within a single LSI chip. From document PATENT ABSTRACTS OF JAPAN, vol. 11, no. 312 (E-548), 12th October 1987; & JP-A-62 104 314 a TTL-ECL circuit is known that comprises a diode having a cathode connected to an input terminal for a TTL signal and an anode connected to a first connection terminal, a resistor having its one end connected to a high voltage supply line and its other end connected to said first connection node, a transistor having a collector connected to said high voltage supply line, a base connected to said first connection node and an emitter connected to a second connection node, a level shift means having its one end connected to said second connection node and its other end connected to a third connection node, a constant current source having its one end connected to said third connection node and its other end connected to a low voltage supply line, and an emitter follower connected between an intermediate voltage supply line and said low voltage supply line and having an input coupled to said third connection node and an output connected to an output terminal for an ECL signal. However, the present inventor has appreciated that the conventional TTL-ECL level converting circuits have been disadvantageous in that the base potential of a transistor receiving a TTL input signal is apt to cause self-oscillation, and the fluctuating voltage is propagated as noise to an ECL level output signal. The noise has the possibility of causing the next ECL circuit stage to malfunction. Furthermore, the conventional TTL-ECL level converting circuits have a logical amplitude of the ECL output signal much larger than the logical amplitude in ordinary ECL circuits. Therefore, the propagation delay time is inevitably large. The present invention is defined in the appended claim 1, to which reference should now be made. Advantageous features of the invention are set forth in the appendant claims. Embodiments of the invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a circuit diagram of a proposed TTL-ECL level converting circuit; Figure 2 is a circuit diagram of one embodiment of the TTL-ECL level converting circuit in accordance with the present invention; Figures 3A, 3B and 3C are circuit diagrams illustrating various modifications of the TTL-ECL level converting circuit shown in Figure 2; and Figures 4A and 4B are voltage waveform diagrams illustrating the operation of the circuit shown in Figure 2 and a comparative circuit. Referring to Figure 1, there is shown a circuit diagram of a proposed TTL-ECL level converting circuit. The circuit illustrated includes an input terminal IN for receiving a TTL level signal and an output terminal OUT for outputting an ECL level signal. The input terminal IN is connected to the cathode of a Schottky barrier diode D 1 , whose anode is connected to one end of a resistor R 1 , to the base of a first transistor Q 1 and to the collector of a second transistor Q 2 , respectively. The other end of the resistor R 1 and the collector of the first transistor Q 1 are connected to a high voltage supply line V CC . The emitter of the first transistor Q 1 is connected to a low voltage supply line V EE through a diode D 21 , a resistor R 31 and a constant current source Ics. In addition, the emitter of the second transistor Q 2 is connected to a ground line GND, and the base of the second transistor Q 2 is connected through a resistor R 21 to a connection node between the diode D 21 and the resistor R 31 . Another Schottky barrier diode D 31 is connected between the ground line GND and the connection node between the diode D 21 and the resistor R 31 . Furthermore, there is provided a third transistor Q 3 having its collector connected to the ground line GND, and its base connected to a connection node between the resistor R 31 and the constant current source Ics. The emitter of the third transistor Q 3 is connected through a resistor R 4 to the low voltage supply line V EE and is also connected to the output terminal OUT. The operation of the above mentioned TTL-ECL level converting circuit will now be explained. A TTL level signal applied to the input terminal IN is level-shifted by the diode D 1 , the transistor Q 1 , the diode D 21 and the resistor R 31 , and outputted as an ECL level signal from the output terminal OUT through an emitter follower formed of the transistor Q 3 and the resistor R 4 . The ECL level signal is set as follows: When the TTL level signal of a high level V IH is inputted, the transistor Q 1 , the diode D 21 and the transistor Q 2 are brought into the on condition, and on the other hand, the diode D 1 is brought into the off condition. If a forward direction voltage of diodes and transistors is expressed by V F , this input voltage V IH must fulfil the following condition (1) in order to render the diode D 1 off: V IH ≥ V F (Q 2 ) + V F (D 21 ) + V F (Q 1 ) - V F (D 1 ) In general, the forward direction operating voltage V F is 0.8 V in diodes and transistors, and 0.4 V in Schottky barrier diodes, and therefore, the high level condition becomes stable if V IH ≥ 2.0 V. In this condition, the high level output V OH of the ECL level signal is expressed by the following equation (2): V OH = V F (Q 2 ) - R 31 · Ics - V F (Q 3 ) ≈ - R 31 · Ics where Ics is the current value of the constant current source Ics) On the other hand, when the TTL level signal of a low level V IL is inputted, the diodes D 1 and D 31 are brought into the on condition, and the transistor Q 2 is brought into the off condition. In this condition, in order to ensure the on condition of the diode D 1 , the input voltage V IL must fulfil the following condition (3): V IL ≤ -V F (D 31 ) + V F (D 21 ) + V F (Q 1 ) - V F (D 1 ) Therefore, the low level condition becomes stable under the condition of V IL ≤ 0.8V. In this condition, a low level output V OL of the ECL level signal is expressed by the following equation (4): V OL = -V F (D 31 ) - R 31 · Ics - V F (Q 3 ) As seen from the equations (2) and (4), the ECL level output of the circuit shown in Figure 1 has a logical amplitude (a difference between V OH and V OL ) corresponding to the sum of the forward direction operating voltage of one transistor and the forward direction operating voltage of one Schottky barrier diode (about 1.2V). In the circuit shown in Figure 1, when the input TTL level signal is brought from the low level to the high level, the base potential of the transistor Q 1 is elevated to follow the input TTL level signal, and the elevating potential is level-shifted by the transistor Q 1 , the diode D 21 and the resistor R 21 and applied to the base of the transistor Q 2 so as to cause the transistor Q 2 to turn on. Namely, a current flows through the resistor R 1 with the result that a balanced and stable condition is established. In the above mentioned process, the present inventor has appreciated that a propagation delay will occur in the course of the level shifting, and therefore, the base potential of the transistor Q 1 is apt to cause oscillation due to a delay of the turning-on of the transistor Q 2 and a voltage drop caused across the resistor R 1 by an abruptly increasing operation current. Specifically, when the input signal on the input terminal IN changes from the low level to the high level, the base potential of the transistor Q 1 elevates towards the potential of the high voltage supply V CC through the resistor R 1 . This elevated voltage is propagated to the base of the transistor Q 2 through the transistor Q 1 , the diode D 21 and the resistor R 21 with a delay corresponding to the propagation delay time of these elements. As a result, the current of the transistor Q 2 is increased, and the collector potential of the transistor Q 2 is correspondingly decreased due to the voltage drop across the resistor R 1 . The drop of the collector potential of the transistor Q 2 is propagated to the base of the transistor Q 2 after a constant delay time, so that the base potential of the transistor Q 2 is decreased, and therefore, the collector current of the transistor Q 2 is correspondingly decreased. As result, the collector potential of the transistor Q 2 is elevated at this time. The above mentioned operation is repeated and therefore the base potential of the transistor Q 1 fluctuates or oscillates. This oscillating waveform is level-shifted, and thereafter, is propagated as noises to the high level of the ECL level output signal. The noise has the possibility of cause the next ECL circuit stage to malfunction. Furthermore, in the circuit shown in Figure 1 the logical amplitude of the ECL output signal corresponds to the sum of the forward direction operating voltage of one transistor Q 2 and the forward direction operating voltage of one Schottky barrier diode D 31 . This logical amplitude of the ECL output signal is much larger than a logical amplitude of 0.6V in ordinary ECL circuits. Therefore, the propagation delay time inevitably becomes large. Referring to Figure 2, there is shown the circuit diagram of one embodiment of the TTL-ECL level converting circuit in accordance with the present invention. In Figure 2, elements similar or corresponding to those shown in Figure 1 are given the same reference characters, and explanation thereof will be omitted for simplification of description. As seen from Figures 1 and 2, a level shift circuit in the conversion circuit shown Figure 2 connected to the emitter of the transistor Q 1 is composed of a series circuit consisting of a resistor R 3 and a diode D 2 in such a manner that the resistor R 3 is connected at its one end to the emitter of the transistor Q 1 and at its other end to the anode of the diode D 2 , and the cathode of the diode D 2 is connected to the current source Ics. A connection node between the resistor R 3 and the diode D 2 is connected directly to the base of the transistor Q 2 . In addition, a resistor R 2 is connected between the emitter of the transistor Q 2 and the ground line GND. The cathode of an anode-grounded diode D 3 for low level clamping is connected to the cathode of the diode D 2 which forms an output end of the level shift circuit. The operation of the TTL-ECL level converting circuit shown in Figure 2 will now be explained. When the TTL level input signal is at a high level V IH , the transistors Q 1 and Q 2 and the diode D 2 are brought into the on condition, and, on the other hand, the diodes D 1 and D 3 are brought into the off condition. In other words, the operation current of the transistor Q 2 flows through the resistor R 1 so that an anode potential of the diode D 1 is maintained at a constant level. Therefore, the voltage difference V(D 1 ) between the anode potential of the diode D 1 and the high level TTL level signal applied at the cathode of the diode D 1 becomes smaller than the forward direction operation voltage V F (D 1 ) of the diode D 1 , and therefore, the diode D 1 is turned off. With this, the status is balanced. In this condition, the operating current I F (Q 2 ) of the transistor Q 2 is expressed by the following equation (5): I F (Q 2 ) = {V CC - V F (Q 1 ) - R 3 · Ics - V F (Q 2 )}/(R 1 + R 2 ) In addition, the voltage difference V(D 1 ) applied across the Schottky barrier diode D 1 is expressed by the following equation (6): V(D 1 ) = V F (Q 1 ) + R 3 · Ics + V F (Q 2 ) + R 2 · I F (Q 2 ) - V IH The condition for maintaining the Schottky diode D 1 in the off condition can be expressed by the following equation (6a): V(D 1 ) < V F (D 1 ) Here, assuming V F (Q 1 ) = V F (Q 2 ) = 0.8V, R 3 = 2KΩ, Ics = 0.3mA, R 2 = 1KΩ, V CC = 5V, R 1 = 20KΩ, V IH ≥ 2.0V, and V F (D 1 ) = 0.4V, the above mentioned condition is fulfilled. In this case, the high level V OH of the ECL level output is expressed by the following equation (7): V OH = R 2 · I F (Q 2 ) + V F (Q 2 ) - V F (D 2 ) - V F (Q 3 ) ≈ R 2 · I F (Q 2 ) - V F (Q 3 ) On the other hand, when the TTL level signal of a low level V IL is inputted, the diodes D 1 and D 3 are brought into the on condition, and the transistor Q 2 is brought into the off condition. In this condition, the cathode potential of the diode D 2 becomes a low voltage sufficient to turn on the diode D 3 . The condition for this is expressed by the following equation (8): |V IL + V F (D 1 ) - V F (Q 1 ) - R 3 · I CS - V F (D 2 ) | ≥ V F (D 3 ) Here, assuming V IL ≤ 0.8V, V F (D 1 ) = 0.4V, V F (Q 1 ) = V F (D 2 ) = V F (Q 3 ) = 0.8V, R 3 = 2KΩ, and Ics = 0.3mA, the above mentioned condition (8) is fulfilled. In this condition, a low level output V OL of the ECL level signal is expressed by the following equation (9): V OL = - V F (D 3 ) - V F (Q 3 ) As seen from the above equations (7) and (9), the logical amplitude of the ECL output signal of the converting circuit shown in Figure 2 is expressed by the following equation (10): V OH - V OL = R 2 · I F (Q 2 ) + V F (D 3 ) Here, if I F (Q 2 ) is calculated in accordance with the equation (5) in the example in which the respective elements have the above mentioned values, respectively, the logical amplitude of the ECL level output signal of the converting circuit shown in Figure 2 is about 0.93V, which is apparently smaller than that of the circuit shown in Figure 1. In addition, if a Schottky barrier diode is used as the diode D 3 and the value of the resistor R 2 is 1.5KΩ, the logical amplitude of the ECL level output signal can be reduced to 0.6V under the condition that the equations (6a) and (8) are fulfilled. Next, an oscillation restraining effect obtained by inserting the resistor R 2 between the emitter of the transistor Q 2 and the ground line GND will be explained on the basis of the result of a simulation. Figure 4A shows a graph illustrating voltage variations on various points in the converting circuit shown in Figure 2 in which the resistor R 2 is removed and the emitter of the transistor Q 2 is directly connected to the ground line GND. Figure 4B is a graph illustrating voltage variations on various points in the converting circuit shown in Figure 2. These figures show transitions when the TTL input signal is brought from the low level to the high level. In each of these figures, the line A shows the TTL level input signal, and the line B shows the base potential of the transistor Q 1 . The lines C, D and E indicate the cathode potential of the diode D 2 , the ECL level output signal, and a reference voltage for the ECL level signal, respectively. In addition, the values of the respective elements used in the circuit for the simulation is in accordance with the values as mentioned hereinbefore. As shown in Figure 4A, in the case of no resistor R 2 , the base potential of the transistor Q 2 greatly oscillates, and therefore, the ECL level output signal correspondingly fluctuates. If this fluctuation exceeds the reference voltage for the ECL level signal indicated by the line E, a malfunction will occur. On the other hand, in the circuit shown in Figure 2, the oscillation of the base potential of the transistor Q 1 is almost perfectly restrained, and therefore, there is little possibility of malfunction. Turning to Figures 3A, 3B and 3C, there are shown some modifications of the level shift circuit portion of the converting circuit shown in Figure 2. In the modification shown in Figure 3A, the level shift circuit is composed of a series circuit consisting of two diodes D 21 and D 2 . In this modified converting circuit, since the level shift circuit is composed of a low impedance circuit formed of only the diodes, the propagation delay can be shortened to a minimum extent. In the modification shown in Figure 3B, the level shift circuit is composed of a series circuit consisting of two resistors R 3 and R 32 . In this modified converting circuit, since the constant current flows through the resistors of the level shift circuit, temperature dependency of the threshold of the converting circuit is eliminated. Ordinarily, the forward direction operating voltage of diodes and transistors has a temperature dependency of about 2mV/°C. In the circuit shown in Figure 2, the temperature dependencies of the Schottky barrier diode D 1 and the transistors Q 1 are countervailed or compensated to each other. In the modification shown in Figure 3B, on the other hand, the level shift circuit does not have a temperature dependency. As a result, the converting circuit modified in accordance with the modification shown in Figure 3B has a threshold with no temperature dependency. This is very advantageous in that even if the converting circuit and an ECL circuit which generates a large amount of heat due to power consumption are integrated in the same chip, the converting circuit maintains its threshold at a constant level regardless of temperature change. In the modification shown in Figure 3C, the level shift circuit is composed of a series circuit consisting of a diode D 21 and a resistor R 32 in such a manner that the diode D 21 is connected at its anode to the emitter of the transistor D 21 and at its cathode to one end of the resistor R 32 and the base of the transistor Q 2 . This modified converting circuit has an excellent balance concerning both the delay time and the threshold temperature dependency. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A TTL-ECL converting circuit, comprising a Schottky barrier diode (D 1 ) having a cathode connected to an input terminal (IN) for a TTL signal and an anode connected to a first connection node, a resistor (R 1 ) having its one end connected to a high voltage supply line (Vcc) and its other end connected to said first connection node, a first transistor (Q 1 ) having a collector connected to said high voltage supply line, a base connected to said first connection node and an emitter connected to a second connection node, a level shift means (R 3 , D 2 ; D 21 , D 2 ; R 3 , R 32 ; D 21 , R 32 ) having its one end connected to said second connection node, an intermediate node forming a third connection node, and its other end connected to a fourth connection node, a constant current source (Ics) having its one end connected to said fourth connection node and its other end connected to a low voltage supply line (Vee), a second transistor (Q 2 ) having a collector connected to said first connection node, a base connected to said third connection node and an emitter connected through a second resistor (R 2 ) to an intermediate voltage supply line (GND), and an emitter follower (Q 3 , R 4 ) connected between said intermediate voltage supply line and said low voltage supply line and having an input connected to said fourth connection node and an output connected to an output terminal (OUT) for an ECL signal. A circuit claimed in claim 1, further including a diode (D 3 ) having its anode connected to said intermediate voltage supply line and its cathode connected to said fourth connection node. A circuit claimed in claim 1 or 2, wherein said level shift means includes a resistor (R 3 ) having its one end connected to said second connection node and its other end connected to said third connection node, and a diode (D 2 ) having its anode connected to said third connection node and its cathode connected to said fourth connection node. A circuit claimed in claim 1 or 2, wherein said level shift means includes a diode (D 21 ) having its anode connected to said second connection node and its cathode connected to said third connection node, and another diode (D 2 ) having its anode connected to said third connection node and its cathode connected to said fourth connection node. A circuit claimed in claim 1 or 2, wherein said level shift means includes a resistor (R 3 ) having its one end connected to said second connection node and its other end connected to said third connection node, and another resistor (R 32 ) having its one end connected to said third connection node and its other end connected to said fourth connection node. A circuit claimed in claim 1 or 2, wherein said level shift means includes a diode (D 21 ) having its anode connected to said second connection node and its cathode connected to said third connection node, and a resistor (R 32 ) having its one end connected to said third connection node and its other end connected to said fourth connection node.

Inventors: MATSUMOTO KOUJI, MATSUMOTO, KOUJI, MATSUMOTO, KOUJI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: H03K19
IPC codes: H03K19