CURRENT CONTROL CIRCUIT

Abstract: A current control circuit for a circuit board carrying a parallel circuit comprising an input capacitor (Cb) shunted by an electronic circuit (IC) constituted by CMOS devices which do not dissipate power as long as no clock signal (CK) is applied to them. This control circuit limits voltage variations across other parallel circuits on other circuit boards already coupled to a power supply (PS), i.e. with charged input capacitors, when the present circuit board is newly coupled to this power supply or source. This is done by first intercoupling the parallel circuit and the source via a resistance and meanwhile preventing the clock signal (CK) from being applied to the electronic circuit (IC), and by allowing this clock signal to be applied to the electronic circuit (IC) during gradually increasing time periods (Th) after the resistance has been short-circuited.

Description: CURRENT CONTROL CIRCUIT The present invention relates to a current control circuit for a circuit board carrying a parallel circuit comprising an input capacitor shunted by a load impedance , said control circuit including a current limiting resistance able to be first coupled between an electric power source and said parallel circuit and to be then short-circuited. Such a current control circuit is already known from the article "Insert Boards Into A Live System Without Any Hitches", by B. Barnes, published in "Electronic Design" of May 11, 1989, pp. 75-80. Therein the problem is considered of inserting a so-called cold printed circuit board, i.e. carrying an uncharged decoupling input capacitor, into a power supply connector of a so-called hot rack, i.e. to which a number of active printed circuit boards have already been connected previously, the decoupling input capacitor of such an active board being in charged condition. During the insertion of the cold printed circuit board first a connection is established between the above parallel circuit and the electric power source via the current limiting resistance and afterwards this resistance is short-circuited. Because of the inductive character of the power supply source the current required to charge the uncharged capacitor on the newly inserted circuit board is essentially provided by the charged decoupling input capacitors of the already connected SUBSTITUTE SHEET circuit boards. In order that the variation of the voltage across the charged capacitors and therefore across the already connected printed circuit boards should be small at the moment the current limiting resistance is short-circuited, this resistance should be much smaller than the load resistance of the newly inserted circuit board. On the other hand this limiting resistance should be sufficiently high to form with the capacitor on the newly inserted board a time constant which is sufficient to ensure a gradual charging of this capacitor in the time interval during which the power source cannot directly supply current to the newly inserted board. This means that for the current limiting resistance a compromise value has to be chosen. An object of the present invention is to provide a current control circuit of the above type but which allows a more adequate control of the current supplied to the circuit board. According to the invention this object is achieved due to the fact that said control circuit further includes control means which when said current limiting resistance is coupled to said parallel circuit prevent current flow in said load impedance, and which when said current limiting resistance is short-circuited allow current flow in said load impedance during gradually increasing time periods. By first preventing the flow of current in the load impedance the current limiting resistance may be given a value sufficient to realize the above mentioned required time constant. On the other hand, by afterwards allowing current to flow in the load impedance during gradually increasing time periods the current to be provided by the electric power source varies gradually too. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to SUBSTITUTE SHEET the following description of an embodiment taken in conjunction with the accompanying drawings wherein : Fig. 1 represents a printed circuit board PCBl able to be connected through a connector CP1 to an electric power source PS to which a plurality of other printed circuit boards PCB have already been connected. Fig. 2 represents a printed circuit board PCB2 able to be connected to the electric power source PS of Fig. 1 through a connector CP2 and carrying a current control circuit according to the invention. Fig. 3 shows control signal generator circuit PGC of Fig. 2 in detail. Fig. 4 represents a control signal generated at the output PO of this generator circuit. Principally referring to Fig. 1 the latter shows an electric power source PS whose inductive character is schematically represented by coils Lo. This electric power source PS is supposed to be already connected to a plurality of printed circuit boards PCB which are represented by their equivalent circuit comprising a charged decoupling input capacitor Co and a load resistance Ro connected in parallel across terminals VP and GP. A further printed circuit PCBl is able to be connected to the power source PS through contact fingers Po and PI of a connector CP1. The printed circuit boards PCBl carries - connected in parallel between terminals VB and GB - a decoupling input capacitor Cb, a clock circuit CL ' K generating a clock signal CK, and an integrated electronic circuit IC controlled by the clock signal. It is assumed that the integrated circuit IC is constituted by CMOS active devices. Such devices are controlled by the clock signal CK and as long as this clock signal is not applied to them they do not dissipate electric power. On the other hand, their power consumption increases/decreases when the duty cycle with which the SUBSTITUTE SHEET clock signal is aplied increases/decreases. When the contact fingers Po and PI are both closed the clock circuit CLK is operated so that the clock signal CK is applied to the circuit IC which therefore consumes electric power and behaves as a load impedance coupled in parallel with capacitor Cb . Without precaution a considerable voltage variation would be produced across the parallel circuit Ro, Co. To avoid this, use is made of a suitable current control circuit shown in Figs. 2 and 3. Reference is first made to Fig. 2 which shows a printed circuit PCB2 similar to PCBl of Fig. 1 but carrying a current control circuit and able to be coupled to the electric power source PS of Fig. 1 through a connector CP2 different from CP1. The printed circuit board PCB2, just like PCBl also includes a parallel circuit connected between terminals VB and GB and comprising an integrated electronic circuit IC» a clock circuit CLK and a decoupling input capacitor Cb . The current control circuit includes a resistance R and a control signal generator circuit PGC also fed between terminals VB and GB and moreover controlled from a terminal VB3. It has an output PO which is connected to the input of an AND gate AND having another input connected to the clock output CK of the clock circ.uit CLK. The output of the AND-gate AND is connected to a control input of the integrated circuit IC. The connector CP2 includes contact fingers Po to P3 : - Po allows the interconnection of ground terminal GP of connector CP2 to terminal GB which is connected to Cb , IC, PGC and CLK; - PI, P2 and P3 allow the interconnection of the live terminal VP at 5 Volts of connector CP2 to terminals VB1, VB2 and VB3 respectively. VB1 is directly connected to VB, VB2 is connected to VB via the above resistor R and VB3 is a control terminal of PGC, SUBSTITUTE S The contact fingers are in fact constituted by pins Po and P2 having a same length, and are longer than PI which is itself longer than P3. Principally referring to Fig. 3 the control signal generator circuit PGC shown therein has input terminals VB, GB and VB3, and output terminal PO. The input terminal VB3 is connected to terminal GB, on the one hand via resistor R2 and on the other hand through resistor Rl in series with capacitor Cl together forming an integrator circuit. The junction point of Rl and Cl is connected to the non-inverting input of an isolating operational amplifier 0A1 which is fed between VB and GB and has an output directly connected to its inverting input. The output of 0A1 is also connected via resistor R3 to the non-inverting input of operational amplifier 0A2 which is also fed between VB and GB whose output PO is also connected to this non-inverting input through a positive feedback resistor R4. The output PO of 0A2 is also connected to its inverting input via a negative feedback resistor R6. Finally this inverting input is also linked to the junction point of resistors R5 and R7 which are branched between terminals VB and GB, resistor R7 being shunted by capacitor C2 ' . The operation of the above described current control circuit is as follows. When the printed circuit board PCB2 is inserted in the connector CP2 the contact fingers Po, P2, PI and P3 are successively closed during first, second and third steps respectively. During the first and second steps the operation of the control signal generator circuit PGC is inhibited because contact P3 is open, so that the output signal PO is de-activated. As a consequence the AND-gate AND is inhibited due to which integrated circuit IC is prevented from being operated. It therefore consumes no electric SUBSTITUTE SHEET power and may be considered as a very high impedance. During the first step wherein contact fingers PO and P2 are closed, resistor R is connected between terminals VP and VB . It thus interconnects PS and PCB on the one hand, and the uncharged input capacitor Cb on the other hand. Before the electric power supply source PS can supply current to charge the latter capacitor Cb, due to its inductive character, this charge current is supplied by capacitor Co. But due to the fact that no current can flow through the integrated circuit IC the latter presents a load impedance which is much larger than , so that the resistor R may be given any value sufficient to provide with Cb a time constant large enough to ensure a gradual charging of this capacitor in the time interval during which the electric power source cannot supply charge current. Thus, the voltage variation across the parallel circuit RO, CO, i.e. across the already connected presented circuit boards PCB remains very small. During the first step also a voltage is established across capacitor C2 (Fig. 3). During the second step wherein contact finger PI is closed resistor R is short-circuited so that the electric power source PS can then freely supply current. Because the voltage VB on Cb nearly equals the supply voltage VP, no significant voltage drop will occur on Co at this closure of PI . Also the voltage across capacitor C2 is increased and since no voltage is yet applied to the input terminal VB3 of the pulse generator circuit PGC the voltage at the inverting input of 0A2 is larger than that at its non-inverting input so that the output P0 of 0A2 is at the logical level 0. During the third step wherein contact finger P3 is closed capacitor Cl is gradually charged towards VP = 5 Volts through resistor Rl. Because the voltage at the SUBSTITUTE SHEET non-inverting input of 0A1 gradually increases the same is true for the voltage applied to the non-inverting input of 0A2 via resistor R3. When the voltage at this input exceeds that at its inverting input the output signal PO of 0A2 goes to the logical level 1. As a consequence the voltage at the non-inverting input of 0A2 suddenly increases, whilst on the other hand capacitor C2 is further charged via resistor R6. As soon as the voltage at the inverting input of 0A2 becomes larger than the voltage at the non-inverting input thereof the output signal PO switches to logical level 0. When this happens the voltage at the non-inverting input decreases suddenly, whilst that at the inverting input gradually decreases due to capacitor C2 being discharged. In this way and during the whole charging time interval of capacitor Cl the duration of the intervals Th during which the operational amplifier output PO is at logical level 1 gradually increase. This is schematically represented in Fig. wherein Th and Tl are used to indicate the time periods during which PO is activated and de-activated respectively. This signal has a duty cycle Th/(Th + Tl) which increases in a substantially linear way from a minimum value close to 0% (when PO would be continuously de-activated) to a maximum value close to lOOJi (when PO would be continuously activated). The control signal PO applied to the AND-gate AND controls the supply of the clock signal CK to the integrated circuit IC. And because this clock signal CK is supposed to be constituted by pulses whose period is fraction of the minimum duration of the active interval Th of PO the clock pulses CK are allowed to the circuit IC during the active time intervals Th of PO. This means that the clock pulses are allowed to the circuit IC during gradually (and even linearly) increasing time periods. As a consequence the current supplied by the power source PS SUBSTITUTE SHEET during these time periods also varies gradually. It may be calculated that the voltage ripple DV produced across capacitor Cb is equal to In Th.Tl DV = Cb+CO Th+Tl wherein In is the nominal current provided by PS to PCB2 and flowing through the circuit IC when the clock signal CK is continuously applied Hence DV is function of the duty cycle Th/(Th+Tl) and of Tl so that for a linear increase of the duty cycle (as described above) the value of DV may be determined by a suitable choice of Tl When the printed circuit board PCB2 is extracted from the connector CP2 the contact fingers are opened in the reverse order i.e. P3, PI and Po , P2. By the opening of P3 capacitor Cl is discharged to ground via Rl and R2 in series. The above duty cycle then decreases linearly. It should be noted that instead of resistor R use can be made of a coil. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention. SUBSTITUTE SHEET

Claims: CLAIMS 1. Current control circuit for a circuit board carrying a parallel circuit comprising an input capacitor (Co, Cb) shunted by a load impedance (Ro, IC), said control circuit including a current limiting resistance (R) able to be first coupled between an electric power source (PS) and said parallel circuit and to be then short-circuited, characterized in that said control circuit further includes control means (PGC, AND, CLK) which when said current limiting resistance (R) is coupled to said parallel circuit (Cb, IC) prevent current flow in said load impedance (IC), and which when said current limiting resistance (R) is short-circuited allow current flow in said load impedance (IC) during gradually increasing time periods (Th). 2. Current control circuit according to claim 1, characterized in that said load impedance (IC) is constituted by an electronic circuit including at least one active device having substantially no power dissipation when no operating signal (CK) is applied to it, and that said control means include a source of said operating signal (CLK), a control signal (PO) generator (PGC) and a gating circuit (AND) which couples said source (CLK) to a control input of said electronic circuit (IC) and is controlled by said control signal (PO) which inhibits said gating circuit (AND) during de-activated time intervals (Tl) and enables said gating circuit during said time periods (Th). SUBSTITUTE SHEET 3. Current control circuit according to claim 1, characterized in that said control signal (PO) has a variable duty cycle (Th/(Th+Tl). <\ . Current control circuit according to claim 1, characterized in that said operating signal is a clock signal (CLK) whose period is a fraction of the smallest . activated time period (Th). 5. Current control circuit according. to claim 2, characterized in that said gating circuit is an AND-gate. 6. Current control circuit according to claim 2, characterized in that said control signal generator (PGC) includes an integrator circuit (Rl, Cl) whose output is coupled to the non-inverting input (+) of a first operational amplifier via the series connection of an isolating second operational amplifier (OAl) and a first resistance (R3), said first amplifier having a positive feedback second resistance (R ), a negative feedback third resistance (R6)» an output (PO) which constitutes the output of the generator, and an inverting input which is connected to the junction point of a resistive voltage divider (R5, R7) constituted by fourth (R5) and fifth (R7) resistances, said fifth resistance (R7) being shunted by a capacitor (C2) . 7. Current control circuit according to claim 1, characterized in that said time periods increase linearly. SUBSTITUTE SHEET

Inventors: DE GROOTE JAN LIEVEN BERT, DE GROOTE, JAN, LIEVEN, BERT
Applicants: ALCATEL NV, BELL TELEPHONE MFG, ALCATEL N.V., BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE VEN
Application year: 1989
Main classification: H02H9
IPC codes: G05F3, G06F13, H02H9