Semiconductor device having a buffer structure for eliminating defects from a semiconductor layer grown thereon

Abstract: A semiconductor device having a group III-V compound semiconductor layer (15) formed on a buffer structure for intercepting propagation of defects, in which the buffer structure comprises a first material layer (13) of a group III-V compound semiconductor material, and a second material layer (14) of a group III-V compound semiconductor material provided on the first material layer, the second material layer containing a first group III element and a second group III element different from the first group III element with a graded compositional profile in which the content of the second group III element is decreased towards an upper boundary and a lower boundary of the second material layer.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to semiconductor devices and more particularly to a buffer structure interposed between an upper compound semiconductor layer and a lower material layer for eliminating defects from the upper compound semiconductor layer on which semiconductor devices are to be formed. Gallium arsenide (GaAs) is a typical compound semiconductor material used for laser diodes and various fast speed semiconductor devices such as metal-semiconductor field effect transistor (MESFET), high electron mobility transistor (HEMT), heterojunction bipolar transistor (HBT) and the like because of its characteristic band structure and high electron mobility. Such a semiconductor device is constructed on a GaAs wafer sliced from a GaAs crystal ingot or on a GaAs layer grown epitaxially on a surface of a silicon wafer. In the latter construction, one can avoid the difficulty of handling heavy and brittle GaAs wafer during the fabrication process of the device by using a light and strong silicon wafer fabricated by well established process for the base of the wafer. Further, a large diameter wafer can be obtained easily in such a construction. As a result, one can handle the wafer easily and reduce the manufacturing cost of the device. Further, such a wafer is suited for fabrication of a so called optoelectronic integrated circuit (OEIC) devices wherein GaAs laser diode and the like are assembled together with silicon transistors on a common semiconductor chip. When growing GaAs on silicon wafer, however, one encounters various difficulties. Such difficulties arise mainly due to the large difference in the lattice constant and thermal expansion coefficient between silicon and GaAs. For example, the lattice constant of silicon is smaller than that of GaAs by about 4 % and the thermal expansion coefficient of silicon is smaller than that of GaAs by about 230 %. From simple calculation based on the difference in the lattice constant, it is predicted that the GaAs substrate constructed as such contains dislocations with a density in the order of 10¹²/cm². Thus, a simple growth of GaAs layer made directly on silicon substrate is usually unsuccessful. Even if successful, such a layer involves significant defects and is useless for the substrate of a semiconductor device. In order to eliminate these problems and to obtain a GaAs layer grown on the underlying silicon wafer, it is proposed to interpose a buffer layer between the silicon wafer and the GaAs layer so as to reduce defects caused as a result of the mismatch in the lattice constant and thermal expansion coefficient. In one example, it is proposed to interpose a GaAs buffer layer between the silicon substrate and the GaAs layer (Akiyama, M. et al., Ext. Abst., 18th Int. Conf. SSDM p.16, 1986). FIG.1 shows a typical structure in which a thin buffer layer 2 of gallium arsenide is grown on a silicon wafer 1 and before growing a gallium arsenide layer 3 to serve as the substrate of semiconductor device. In this approach, the buffer layer 2 is deposited on the silicon wafer 1 in the amorphous state for a thickness of about 10-20 nm (100 - 200 Å) at a temperature of about 400 - 450°C and then the gallium arsenide layer 3 is grown for a thickness of about 3 - 5 µm. When the gallium arsenide layer 3 is grown, the underlying gallium arsenide buffer layer 2 is crystallized into a single crystal phase and the gallium arsenide substrate layer 3 deposited thereon grows while maintaining epitaxial relation with the gallium arsenide buffer layer 2 underneath. In the foregoing method, although the gallium arsenide layer 3 is grown successfully on the silicon wafer 1, there is a problem in that the dislocation density in the gallium arsenide layer grown on the substrate cannot be reduced below about 10⁸/cm². Such dislocations occur mainly at the interface between the silicon wafer 1 and the buffer layer 2 as illustrated in FIG.1 by a line 4, due to the lattice mismatch between silicon and GaAs. The buffer layer 2 is thus not effective in intercepting the propagation of the dislocations and the dislocations are extended into the gallium arsenide layer 3 on which the semiconductor devices are to be formed. In addition to the dislocations originating at the foregoing interface, dislocations are also created due to the surface defects or intrinsic defects involved in the wafer 1. The problem of the latter type of dislocations becomes conspicuous when a single crystal gallium arsenide wafer is used in place of the silicon wafer 1. In a semiconductor device such as field effect transistor (FET) formed on the gallium arsenide layer 3, the threshold voltage scatters unacceptably when the dislocation density exceeds about 10⁶ cm⁻² and accordingly, the yield of the fabricated semiconductor device is inevitably decreased. Further, the existence of the dislocations causes a decrease of lifetime of the carrier or increase of the leak current across the p-n junction. When the device is an optical semiconductor device such as laser diode, the optical output is also decreased. Meanwhile, it is known that the dislocation density of a GaAs bulk crystal grown by Czochralski method can be reduced to about 100 cm⁻² by adding indium (In) with a concentration level of 2 X 10¹⁹ cm⁻² (Mil'vidsky, M.G., Osvensky, V.B. and Shifrin, S.S., J. Crystal. Growth, 52, p.396, 1981). However, the wafer sliced from such a bulk crystal has a composition of InGaAs and the utility of the wafer is limited. Further, addition of In to the GaAs layer grown on another GaAs buffer layer as in the case of FIG.1 is generally unsuccessful as the addition of In with such an amount inevitably causes an unacceptable lattice mismatch. Even successful, the growth of the GaAs layer containing In would create a significant amount of dislocations at the boundary to the underlying layer, with a worse result. Growth of another GaAs layer on the buffer layer thus added with In is not possible because of the same reason. A method for growing single epitaxial films of group III-V compounds on a GaAs-material is disclosed in US-A-3 821 033, wherein an intermediate non-linear or graded deposition e.g. of GaAs to GaAsP is initially applied on the substrate. The purpose of this deposition is essentially to prevent the occurrence of bowing camber or other geometric deformities. For an analysis of dislocations in GaAs grown on Si by molecular beam epitaxy and how they may be controlled, reference can be made to J.S. Ahearn et al in Vacuum Science and Technology, B5-4, July/August 1987, pages 1156-1161. The solutions proposed in this prior art rest essentially on the the use of strained layer In x Ga 1-x /GaAs superlattices. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a novel and useful buffer structure wherein the aforementioned problems are eliminated. Another object of the present invention is to provide a buffer structure interposed between an upper III-V compound semiconductor layer and a lower silicon material layer for intercepting propagation of dislocations from the underlying silicon material layer to the overlying III-V compound semiconductor layer. Another object of the present invention is to provide a buffer structure comprising a buffer layer interposed between an upper III-V compound semiconductor layer and a lower silicon material layer, as defined in claim 1. According to the present invention, propagation of dislocations into the upper compound semiconductor layer is effectively intercepted by the buffer layer containing the group III element. Further, the lattice mismatch which would occur between the buffer layer and the compound semiconductor layer or between the buffer layer and the underlying material layer as a result of the admixing of the group III element, is successfully avoided by providing the graded compositional profile to the buffer structure. Furthermore, creation of new dislocations at the boundary to the underlying layer or to the overlying layer is suppressed minimum because of the lattice matching thus achieved. As a result, a buffer structure which is effective for intercepting the propagation of the dislocations is obtained. By choosing the compositional profile of the buffer structure such that the content of the group III element changes stepwise, in other words, by constructing the buffer structure as a stacking of a number of thin layers each having its own content of the group III element, the dislocations are not only intercepted by the group III element but also trapped at the boundary between the layers and the efficiency of intercepting the dislocations is further improved. Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a cross sectional view showing a prior art buffer structure; FIG.2 is a diagram showing a buffer structure according to an embodiment of the present invention; FIG.3 is a compositional profile of the buffer structure of FIG.2; FIG.4 is a compositional profile of the buffer structure according to a second embodiment; FIG.5 is a diagram showing a schematical construction of an apparatus used for growing the buffer structure of FIG.2 in the present invention; FIGS.6(A) - (F) are diagrams showing various steps of forming the buffer structure of FIG.2; and FIG.7 is a compositional profile of the buffer structure according to a third embodiment. DETAILED DESCRIPTION Hereinafter, a first embodiment of the buffer structure according to the present invention will be described with reference to FIG.2 showing a cross section of a compound semiconductor device 10 such as a field effect transistor (FET) constructed on the buffer structure of the present invention. Referring to the drawing, the semiconductor device comprises a silicon substrate or wafer 11 on which a first buffer layer 12 of GaAs is grown for a thickness of 10 nm (100 Å), and on the first buffer layer 12, a first mixed crystal layer 13 of GaAs, a second buffer layer 14 of InGaAs constituting the essential part of the present invention and having a composition Ga 1-x In x As, and a second mixed crystal layer 15 of GaAs are grown successively with thickness of 1-5 µm, 0.2 µm, and 1.5 µm, respectively. The semiconductor device 10 is constructed on the second mixed crystal layer 15. In other words, it is desired to suppress the dislocation density in the layer 15 as low as possible. Note that the first buffer layer 12 is in the amorphous phase when it is initially grown on the silicon wafer 11 but is later crystallized to a single crystal phase when the second buffer layer 13 is grown thereon. FIG.3 shows a compositional profile of the second buffer layer 14. The content of In represented by the parameter x in the foregoing formula is set zero at the upper boundary (y = 1) in contact with the second mixed crystal layer 15 and at the lower boundary (y = 0) in contact with the first mixed crystal layer 13, while the parameter x reaches maximum (x = 0.9) at the central part of the buffer layer 14 (y = 0.5). Note that the axis y represents the thickness of the second buffer layer 14 measured perpendicularly to the substrate 11. In this embodiment, the parameter x is increased stepwise by an amount of 0.1 in each 10 nm (100 Å) thickness of the layer 14. In other words, the buffer layer 14 comprises a number of thin InGaAs layers 14a - 14t (FIG.2) each having its own In-content and a thickness of about 10 nm (100 Å). Next, the function of the foregoing buffer structure will be described. In the foregoing structure, the distortion caused as a result of the lattice mismatch between Si and GaAs is absorbed by the first buffer layer 12 interposed between the silicon wafer 11 and the first mixed crystal layer 13. As already described, the first buffer layer 12 is grown in a form of the amorphous state and thus covers the surface of the silicon wafer 11 with reliability. When the first mixed crystal layer 13 is grown thereon, the first buffer layer 12 is crystalized. Thereby, the dislocation density in the first mixed crystal layer 13 is reduced to about 10⁸ cm⁻². This dislocation density, however, is not acceptable for constructing semiconductor devices on the mixed crystal layer 13. Increase of the thickness of the first buffer layer 12 or the first mixed crystal layer 13 is not effective in reducing the dislocation density below the foregoing level, as the dislocations are propagated without substantial interception through these layers as shown in FIG.1. In the second buffer layer 14 containing In, dislocations 4₁ (FIG.2) passed through the first buffer layer 12 and further through the first mixed crystal layer 13 are intercepted by In which is believed to induce a local strain in the host crystal structure, and the dislocations are trapped in such a strained region (Mil'vidsky et al. op.cit.). As the In-content x is graded as shown in FIG.3 such that the parameter x is zero at the upper and lower boundary of the second buffer layer 14, the composition of the second buffer layer becomes identical to that of the underlying first mixed crystal layer 13 or the overlying second mixed crystal layer 15 and the problem of lattice mismatch at the upper and lower boundaries of the second buffer layer is eliminated. Further, it is believed that some of the dislocations 4₂ are diverted by the In atoms and thereby trapped at the interface between the layers 14a - 14t constituting the layered second buffer layer 14 as shown in FIG.2. Thus, the stepwise increment of the In-content in the buffer structure of the present embodiment is particularly preferable from the view point of intercepting the dislocations effectively. In one experiment for demonstrating the effect of the buffer structure of the present invention, measurement of the dislocation density of the mixed crystal layer 15 is undertaken by processing the structure of FIG.2 in a potassium hydroxide (KOH) solution at 370°C for 10 minutes and counting the etch pits appearing on the surface of the layer 15, with a result that the dislocation density of 10⁸ cm⁻² in the underlying GaAs layer 13 is reduced to 2 X 10⁶ cm⁻² in the second mixed crystal layer 15. This level is acceptable for constructing a FET on the layer 15. In another measurement, it was observed that the dislocation density in the layer 15 is reduced to about 1 X 10⁶ cm⁻². Further, by repeating the compositional profile of FIG.3 for a number of times in the second buffer layer 14 as shown in FIG.4 showing a second embodiment, the dislocation density in the second mixed crystal layer 15 at the top of the structure is decreased further. From the foregoing observation, the dislocation density is decreased by a factor of 10² for each repetition of the compositional profile. Note that mere extension of the thickness of the second buffer layer 14, which causes formation of a region enriched in InAs at the central part of the layer 14, would be ineffective in intercepting the dislocations, as the interception of the dislocations is not caused by the In atom itself but the strain induced in the crystal structure of GaAs by the addition of In. In such an almost pure InAs structure, there would be no such strain in the structure. This means, on the other hand, that the element to be added to the buffer structure with the compositional profile of FIG.3 is not limited to In but other element different from Ga such as boron (B) or aluminium (Al) may also be used in the based buffer layer 14 as is supported by Mil'vidsky et al. (op. cit.). Next, the steps of constructing the buffer structure of FIG.2 will be described with reference to FIGS.6(A) - (F) together with the apparatus used for growing the crystal layers. FIG.5 shows the general construction of a MOCVD apparatus used for growing the compound semiconductor layers in the structure of FIG.2. Referring to the drawing, the silicon wafer 11 is placed on a susceptor 18 in a reaction chamber 17 and is heated together with the susceptor 18 by energization of a radio frequency coil 16. Further, a suitable combination of arsine (AsH₃), trimethyl gallium (TMG: (CH₃)₃Ga), and trimethyl indium (TMI: (CH₃)₃In) are introduced to the reaction chamber 17 together with a hydrogen (H₂) carrier gas. TMI and TMG are liquid in the normal state and are held in thermostatted containers 21 and 22 at a temperature of 15°C and 30°C, respectively. By bubbling the liquids using H₂, the gaseous molecules of TMG and TMI are supplied to the reaction chamber 17 through control valves 12 and 13. Further, arsine, held at a temperature of 0°C, is introduced to the reaction chamber 17 through a control valve 14. In a first step, the silicon wafer 20 is held at 1000°C for about 10 minutes in the reaction chamber 17 and then the temperature of the wafer 11 is set to 450°C. Further, TMG and arsine are introduced to the reaction chamber 17. Thereby, the gaseous molecules thus introduced are reacted at the surface of the substrate 20 and the first buffer layer 22 is grown on the wafer 20 covering its surface in the amorphous state as shown in FIG.6(A). Next, the temperature of the wafer 11 is raised to 700°C and TMG and arsine are introduced into the reaction chamber 17. As a result, the first mixed crystal layer 13 is grown on the first buffer layer 12 and a structure shown in FIG.6(B) is obtained. During this step, the previously grown amorphous buffer layer 22 is crystalized into a single crystal phase. Further, the flow rate of arsine and TMG are set to 200 cc/min and 70 cc/min, respectively and a first layer 14a of the second buffer layer 14 which is free from In is grown on the first mixed crystal layer 13 for a thickness of about 10 nm (100 Å) as shown in FIG. 6(C). Next, TMI is introduced further to TMG and arsine with a flow rate of 143 cc/min, and a structure shown in FIG.6(D) is obtained in which a second layer 14b having a composition Ga 0.9 In 0.1 As is grown on the first layer 14a. Note that the flow rate of TMG and arsine are set similarly to the case of FIG.6(C). Further, by changing the flow rate of TMG and TMI stepwise, a number of layers of InGaAs each having a thickness of about 10 nm (100 Å) are grown one after another as shown in FIG.6(E) with a stepwise increment of the In-content. In a tenth layer 14j, the In-content becomes maximum and the parameter x takes a value of 0.9. In other words, the composition of the InGaAs layer is represented as Ga 0.1 In 0.9 As. Next, an eleventh layer 14k is grown on the tenth layer 14j with a composition identical to the layer 14j for a thickness of 10 nm (100 Å) and further, other layers are grown thereon with a stepwise decrease of the In-content with a decrement of 0.1 in each layer by changing the ratio of TMG and TMI stepwise until a twentieth layer 14t is grown in which the In-content is zero as shown in FIG.6(F). In each of the layers 14k through 14t, the thickness of the layer is maintained at 100 Å and thus, a symmetrical compositional profile having a maximum of the In-content at the center of the buffer layer 14 as shown in FIG.3 is obtained. After the twentieth layer 14t is grown, the supply of TMI is stopped and the second mixed crystal layer 15 is grown while supplying arsine and TMG. As a result, the structure shown in FIG.2 is completed. The apparatus used for constructing the structures of FIGS. 6(A) - (F) is of course not limited to the MOCVD apparatus of FIG.5 but a MBE apparatus may also be used. In this apparatus, too, a stepwise compositional profile as shown in FIG.3 is easily obtained. Further, by changing the temperature of cells (not shown) holding the source material in such an apparatus, or by changing the ratio of TMG and TMI continuously in the apparatus of FIG.5, a compositional profile shown in FIG.4 in which the In-content x is changed continuously instead of stepwise is also achieved. In this compositional profile, too, the dislocations are intercepted by the In atoms and at the same time, the lattice mismatch to the neighbouring layers 13 and 15 by incorporating In to the buffer layer 14 is avoided by providing the compositional gradation. Further, the stepwise compositional increment is not limited to 0.1 as shown in FIG. 3. Similarly, the thickness of the layers 14a - 14t is not limited to 10 nm (100 Å) either. As a matter of fact, a continuous compositional profile shown in FIG.7 is obtained as an extreme case in which the thickness of each layer is reduced to infinitesimal and the compositional increment of In is also reduced to infinitesimal. From the view point of trapping the dislocations at the boundary between the layers, however, it is preferred to form a distinct interface between the layers of the buffer layer 14 by providing the stepwise compositional profile. For this purpose, a stepwise increment of In-content of less than 0.1 and a layer thickness of more than 10 nm (100 Å) are preferred, wherein the stepwise increment of 0.1 for the In-content and the layer thickness of 10 nm (100 Å) as described are most preferred. Obviously, the maximum of the In-content at the central part of the buffer layer 14 is not limited to 0.9 as described but may be smaller or larger and the central part of the buffer layer 14 may comprise pure InAs. Further, the compositional profile of In is not necessarily be symmetrical about the central part of the buffer layer 14 but may be asymmetrical. Furthermore, the In-content at the top and bottom boundary of the buffer layer 14 need not necessarily be zero but may have a finite level unless unacceptable lattice mismatch is induced at the boundaries. The present invention includes also a case in which the first mixed crystal layer 13 and the second mixed crystal layer 15 have different compositions. In such a case, the compositional profile is asymmetric and the In-content may not be equal at the top boundary and at the bottom boundary of the buffer layer 14. As already described, the element incorporated to the GaAs buffer layer is not limited to In but other group III element such as B or Al may also be used. Further, the present invention is effective also when the first buffer layer 12 comprises gallium phosphide (GaP) and the second buffer layer 14 comprises GaP added with In. For this case, the first and second mixed crystal layers 13 and 15 also comprises GaP and the second buffer layer 14 is provided with the compositional profile similar to FIG.3. Further, the present invention is not limited to the buffer structure constructed on the silicon wafer but is applicable also to a case when growing a semiconductor layer free from dislocations or other defects on a semiconductor substrate or wafer of a same composition. For example, the present invention is effective in growing a GaAs layer free from such defects on a GaAs wafer which usually contains a significant amount of defects. In this case, the GaAs wafer is used as the wafer 11 in the structure of FIG.2. Further, the semiconductor material to be used as the wafer 11 and as the layers 13 and 15 in such a construction is not limited to GaAs but other materials such as germanium (Ge), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and the like may be used similarly. When the buffer layer 14 in the structure of FIG.2 comprises a compound semiconductor material containing Ga such as GaAs, GaP or GaSb, elements such as In, B or Al are effective as the group III element for intercepting the dislocations while when the buffer layer 14 comprises a compound semiconductor material containing In such as InAs, InP or InSb, elements such as Ga, B or Al are effective as the group III element in agreement with the report by Mil'vidsky et al. (op. cit.) for the case of bulk crystal. In any of these cases, the content of the group III elements for intercepting the dislocations should be graded as shown in FIG.3, preferably with stepwise profile.

Claims: A semiconductor device having a group III-V compound semiconductor layer (15) formed on a buffer structure overlying a silicon substrate (11) for intercepting propagation of defects, said buffer structure comprising a first material layer (13) of a group III-V compound semiconductor material, and a second material layer (14) of a group III-V compound semiconductor material provided on the first material layer, said second material layer containing a first group III element and a second group III element different from the first group III element, characterized in that said second material layer (14) has a graded compositional profile in which the content of the second group III element is decreased in going towards an upper boundary where said second layer meets said group III-V semiconductor layer (15), and in going towards a lower boundary of the second material layer where said second layer meets said first material layer, such that no unacceptable lattice mismatch is induced at said boundaries. A semiconductor device as claimed in claim 1 characterized in that the content of the second group III element is changed stepwise in the second material layer (14). A semiconductor device as claimed in claim 1 characterized in that the content of the second group III element is changed continuously in the second material layer (14). A semiconductor device as claimed in claim 1 characterized in that the content of the second group III element is zero at the upper boundary and the lower boundary. A semiconductor device as claimed in claim 1 characterized in that there is a single maximum in the content of the second group III element in the second material layer (14). A semiconductor device as claimed in claim 1 characterized in that there are a plurality of maxima in the content of the second group III element in the second material layer (14). A semiconductor device as claimed in claim 1 characterized in that said first group III element comprises gallium and said second group III element comprises indium. A semiconductor device as claimed in claim 1 characterized in that the first material layer (13) forms a substrate of a group III-V compound semiconductor substrate identical in composition to the group III-V compound semiconductor layer (15). A semiconductor device as claimed in claim 8 characterized in that the first material layer (13) comprises gallium arsenide.

Inventors: INOUE TOSHIKAZU, INOUE, TOSHIKAZU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H01L29
IPC codes: H01L29, H01L21, H01S5