Logarithmic amplifier

Abstract: In order to improve the large signal handling capability of a logarithmic amplifier comprising amplifier stages (Bi,Ai) successively performing their limiting actions in response to an increase of the input signal, and an adder stage for the output signals of the amplifier stages, the signal of the amplifier stage (B1) which is the last to perform its limiting action in response to an increase of the signal is amplified by a value which is higher than that of the signals of the other amplifier stages.

Description: The invention relates to a logarithmic amplifier comprising a plurality of limiting amplifier stages (B1, B2, A1-A6) which successively perform their limiting actions in response to an increase of an input signal applied to an input terminal (1) of the logarithmic amplifier, whose signal outputs are coupled to an adder circuit (S) for supplying an output signal which varies substantially logarithmically as a function of the input signal, at least a part of said limiting amplifier stages (A1-A6) being arranged in cascade, in which the signal gain between the inputs of two amplifier stages successively performing their limiting actions is G. Logarithmic amplifiers of this type in which the outputs of the amplifier stages are coupled either directly or via respective demodulation circuits to the adder circuit are known, for example, from the Article "A True Logarithmic Amplifier for RADAR IF Applications", IEEE, Journal of Solid State Circuits, Vol. SC-15, No. 3, June 1980, pp. 291-295 or from the journal Frequenz, Vol. 39, No. 12, December 1985, pp. 320-324. Such logarithmic amplifiers are used, inter alia, for amplifying signals having a large dynamic range in which compression of large signal amplitudes is desired as, for example, in radar applications or in radiation detectors. Such logarithmic amplifiers may also be used advantageously in amplifiers for AM-modulated signals, for example, or radio or TV receivers. The logarithmic range of such logarithmic amplifiers is the number of amplifier stages. The gain per stage should be chosen comparatively low (for example, 12 db) in order to ensure a sufficiently correct logarithmic variation. The logarithmic range can thus be increased by incorporating more amplifier stages in cascade. It is an object of the invention to provide a logarithmic amplifier of the type described in the opening paragraph in which a further improvement of the logarithmic variation can be achieved and to this end the logarithmic amplifier according to the invention is characterized in that the amplifier stage (B1) which is the last to perform its limiting action in response to an increase of an input signal is adapted to supply signals to the adder circuit (S) with a gain which is approximately G/(G-1) higher than the gain with which the other amplifier stages (B2, A1-A6) supply signals to the adder circuit (S). or more db's higher than the gain with which the other amplifier stages supply signals to the adder circuit. The invention will now be described in greater detail, by way of example, with reference to the accompanying drawings in which Figure 1 is a block diagram of an embodiment of a logarithmic amplifier according to the invention, Figure 2 is a detailed circuit diagram of a logarithmic amplifier according to the invention, and Figure 3 shows some characteristic curves to elucidate the operation of a logarithmic amplifier according to the invention. The logarithmic amplifier of Figure 1 comprises a cascade of limiting amplifier stages A1 to A6 all having the same gain G. An input terminal 1 connected to the input of the amplifier A1 receives an input signal Vi and the output signals of the stages A1 to A6 are demodulated in demodulation circuits D1 to D6, respectively. The demodulated signals are added in an adder circuit S. The output of the adder circuit is connected to an output terminal from which the logarithmically amplified and demodulated output voltage V log is derived. In such a cascade of 6 amplifier stages each having a gain of 12 db and a limiting level of approximately 200 mV, the logarithmic range of the amplifier is between approximately 20 µV and 20 mV. If more amplifier stages are added to the cascade, the range of the logarithmic amplifier increases but it does not provide the possibility of improving the large-signal handling capability of the amplifier. By increasing the number of amplifier stages in the cascade, the sensitivity of the amplifier is enhanced but this is often unnecessary and, moreover, it jeopardizes the stability of the amplifier. The large-signal handling capability of the circuit arrangement of Figure 1 is essentially improved by the addition of two cascade-arranged attenuation circuits V1 and V2 each having an attenuation of 1/G and by the addition of a limiting amplifier stage B1 connected to the output of V2 and a limiting amplifier stage B2 connected to the output of V1. The amplifier stage B2 has a gain G and the amplifier stage B1 has a gain The output signals of B1 and B2 are demodulated in demodulation circuits C1 and C2, respectively, and the signals thus demodulated are added in the adder circuit S to the demodulated signals of the demodulation circuits D1 to D6. Due to these measures the range of the amplifier in the case of large signals has increased from approximately 20 mV to approximately 800 mV. The attenuation circuits hardly impair the noise behaviour of the amplifier because it is the noise of the input of the stage A1 which, in view of the 6-stage gain for this noise, is by far the greatest contribution to the noise factor of the amplifier, whilst the noise generated by the additions described is negligible. The stability of the amplifier is neither jeopardized because no more than 6 amplifier stages each having a 12 db gain, hence a total of 72 db, are arranged in cascade. The reference numerals in Figure 2 have the same significance as those in Figure 1. The input signals are applied symmetrically or asymmetrically with respect to ground between the input terminals 1 and 2 which are connected to the base electrodes of two emitter-coupled transistors 3 and 4. A constant current source 5 is incorporated between the coupled emitter electrodes and ground. The collector electrodes of the transistors 3 and 4 are connected to a positive power supply terminal via series-arranged resistors 6, 7 and 8, 9, respectively. These collector electrodes are also connected to the base electrodes of two emitter-coupled transistors 10 and 11, respectively, whose collector electrodes are connected to the positive power supply terminal and whose coupled emitter electrodes are connected to a node P via a resistor RD1. The elements 3, 4, 5, 6, 7, 8 and 9 jointly constitute the limiting amplifier stage A1 which is known to have a tanh transfer function. Its output voltage between the collector electrodes of the transistors 3 and 4 is full-wave rectified in the demodulation circuit D1 which is constituted by the elements 10, 11 and RD1. The signal amplified by the amplifier stage A1 and demodulated by the demodulation circuit D1 is applied via the resistor RD1 to the node P which, in conjunction with a current source 17 connected to the node constitutes the adder circuit. The output signal V log of the logarithmic amplifier is taken off the node P. A signal amplified with a gain of G by the amplifier stage A1 occurs between the connection of the collector resistors 6 and 7 and of the collector resistors 8 and 9, which signal is applied to the input terminals of the second amplifier stage A2 with the demodulation circuit D2. The stage A2/D2 is identical to the stage A1/D1 and therefore does not require any further description. The stages A1 and A2 are arranged in cascade, likewise as the subsequent stages A3 to A6. Each demodulation circuit D2 to D6 supplies its output signal to the node P via resistors RD2 to RD6. The amplifier stage A6 has undivided collector resistors because there is no subsequent amplifier stage. A reference voltage V ref is connected via two resistors 18 and 19 to the input terminals 1 and 2, respectively, in order to give these input terminals the correct bias. A dc stabilization can be obtained by providing, instead of the resistors 18 and 19, a dc negative feedback between the input terminals 1/2 and the collector electrodes of, for example, the amplifier stage A6. The two amplifier stages B1 and B2 with their respective demodulation circuits C1 and C2 are constituted similarly as the stage A1/D1, but with undivided collector resistors. A series arrangement of five resistors 12, 13, 14, 15 and 16 is connected between the input terminals 1 and 2. These five resistors operate as the cascade of the two attenuation circuits V1 and V2 of Figure 1. The input terminals of the amplifier B2 are connected between the connection of the resistors 12 and 13 and the connection of the resistors 15 and 16. The input terminals of the amplifier B1 are connected between the connection of the resistors 13 and 14 and the connection of the resistors 14 and 15. The attenuation from the terminals 1, 2 to the input terminals of B2 is: and the attentuation from the input terminals of B2 to the inputs terminal B1 is: With R12=R16=1200Ω, R13=R15=300Ω and R14=200Ω each of the two attenuations equals 1/G=1/4≈-12db. The gain factors of the amplifier stages are dimensioned by means of the collector resistors and of the current sources in the common emitter leads of the amplifier stages in such a way that the stages A1 to A5 have the correct gain G between their input terminals and the input terminals of the subsequent stage of the cascade, which gain corresponds to the attenuation of the two attenuation circuits (thus, G=4 in the example). The gain of all stages and their demodulation circuits for the signals to the node P are mutually equal (but not necessarily equal to G) with the exception of the stage B1/C1 which has a gain for these signals which is higher. This can be realized, for example, by choosing a higher value for the emitter current or for the collector resistors of B1 or a lower value for the resistor RC1. For the purpose of illustration figure 3 shows some transfer characteristic curves V log versus V i of logarithmic amplifiers. For all characteristic curves it holds that the amplifier stages have a tanh transfer function, a gain factor of G=4 and a limiting output level of approximately 200 mV. The characteristic curve I holds for a logarithmic amplifier with a cascade of four amplifier stages. The characteristic curve II holds for a cascade of six amplifier stages and the characteristic curve III holds for a cascade of eight amplifier stages. It is clearly apparent that there is no longer any question of a logarithmic transfer function at Vi > approximately 20 mV. The characteristic curve IV holds for a logarithmic amplifier with a cascade of six amplifier stages A1 to A6 and two additional stages B1 and B2 coupled to the input via attenuators, with all amplifier/demodulation stages having the same gain G=4 for the signals applied to the adder circuit. The characteristic curve V holds for the same logarithmic amplifier for which characteristic curve IV holds but in which the gain of the stage B1/C1 is increased by a factor of 4/3=G/(G-1). The transfer function is now logarithmic until approximately 800 mV. It is to be noted that the improvement of the logarithmic variation due to the higher gain of the amplifier stage which is the last to perform its limiting action in response to an increase of the input signal can also be utilized in logarithmic amplifiers which do not use attenuation circuits for the input signal.

Claims: A logarithmic amplifier comprising a plurality of limiting amplifier stages (B1, B2, A1-A6) which successively perform their limiting actions in response to an increase of an input signal applied to an input terminal (1) of the logarithmic amplifier, whose signal outputs are coupled to an adder circuit (S) for supplying an output signal which varies substantially logarithmically as a function of the input signal, at least a part of said limiting amplifier stages (A1-A6) being arranged in cascade, in which the signal gain between the inputs of two amplifier stages successively performing their limiting actions is G, characterized in that the amplifier stage (B1) which is the last to perform its limiting action in response to an increase of an input signal is adapted to supply signals to the adder circuit (S) with a gain which is approximately G/(G-1) higher than the gain with which the other amplifier stages (B2, A1-A6) supply signals to the adder circuit (S).

Inventors: GARSKAMP ARNOLDUS, VAN GILS CORNELIS JOHANNES MAR, GARSKAMP, ARNOLDUS, VAN GILS, CORNELIS JOHANNES MARIA
Applicants: PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN
Application year: 1989
Main classification: H03G7
IPC codes: G06G7, H03G7, H03D1, H03G11