ANALOG SIGNAL SWITCHING DEVICE FOR USE IN AN OPTICAL MEMORY DEVICE

Abstract: An analog signal switching device for use in an optical memory device having a recording/erasing mode and a mode other than the recording/erasing mode is disclosed. Switching device includes a source (28) for producing a switch control signal (SCS) which is HIGH during the record­ ing/erasing mode and LOW during the mode other than the recording/erasing mode. An analog switch (21) is provided for receiving a direct input analog signal and held input signal and for producing the direct input signal during the LOW state of the switch control signal, and the held input signal during the HIGH state of the switch control signal by a switching operation. Further provided are mask signal generator (24) for generating a mask signal which covers a period during the HIGH state of the switch control signal so as to cover a period during the switching operation of the analog switch, and a gate circuit (27) controlled by the mask signal for allowing the direct input analog signal to pass therethrough during the absence of the mask signal and for preventing the held input signal to pass therethrough during the presence of the mask signal. Thus, noise signals produced by the switching operation of the analog switch are eliminated.

Description: The present invention relates to analog signal switching devices for use in optical memory devices which record, playback, and erase information by irradiating the optical data storage medium with a light beam. Conventionally, optical memory devices include a magneto-optical memory device which records information on a magneto-optical disk. An anisotropic magnetic thin film with an axis of easy magnetization in a direction perpendicular to the film surface is formed on the magneto-optical disk used in the magneto-optical memory device. This enables information to be recorded as a magnetic orientation in a large number of minute areas. To record information on a magneto-optical disk of this type, the magnetic thin film is irradiated with a focused laser beam with a diameter of, for example, approximately 1 micrometer. This raises the local temperature of that part of the thin film irradiated by the laser beam dropping the coercive force and allowing the magnetic orientation of the film to be changed more easily. It is possible, therefore, to record or erase information at a point of raised local temperature by changing the magnetic orientation to the desired orientation by, for example, applying an external magnetic field to reverse the magnetic orientation. To play back the information recorded in the manner described above, the magnetic film is irradiated with a laser beam having a strength which will not cause the temperature to rise to the level necessary to allow the magnetic orientation to be changed easily. The plane of polarization of the linear polarized light in the transmitted and reflected laser beam is rotated by the Faraday effect and the Kerr effect on incidence with the magnetic thin film. By detecting the transmitted and reflected light using an analyzer, and converting it into an electrical signal with an optical sensor, a pulse-type playback signal is obtained. As well as receiving the weak laser light during playback, the optical sensor also receives strong laser light transmitted and reflected by the magnetic thin film during data recording or erasing. Because the laser beam emitted during recording or erasing is stronger than that used during playback, the optical sensor outputs an excessively high level signal. When this is input to a playback analog circuit connected to the optical sensor, the signal greatly exceeds the dynamic range, and affects subsequent playback operation. Accordingly, an analog signal switching device 10 as shown in Fig. 1 has conventionally been used. Specifically, the analog signal switching device 10 is constructed so that the input terminal 12 is connected to terminal 11a directly on one side of analog switch 11, and also through a sample hold circuit 13 to the other terminal 11b. The analog switch 11 is constructed so that the terminal 11a is connected to the terminal 11c when the switch control signal SCS is low and to the terminal 11c when the switch control signal SCS is high. The sample hold circuit 13 is arranged so as to enter a sampling state and to output the unmodified signal sent from input terminal 12 when the switch control signal SCS is low, and to enter a hold state to hold and output the signal sent from the input terminal 12 immediately before the switch control signal SCS becomes high. As shown in Fig. 2, by using this type of analog signal switching device 10, when the switch control signal SCS goes high during input of an excessively high level signal from input terminal 12, i.e. a signal several times the playback signal level, which will occur during information recording or erasing, the analog switch 11 provides a signal to the terminal 11c from which the excessively high level signal has been removed. As a result, the voltage generator 14 and comparator 15 connected to the analog switch 11 operate normally, and a binary converted playback digital signal is output. However, in the above described analog signal switching device 10, although it is possible to remove the excessively high level signal, switching noise signals tend to be generated during the switching operation. Noise signals of this type result in the noise signal often remaining as a noise pulse even after the binary converted playback digital signal is generated by the voltage generator 14 and comparator 15, thus causing improper operation of digital signal processing circuits, such as demodulation and PLL (phase locked loop) circuits, thus reducing the reliability of the optical memory device. The present invention has been developed with a view to substantially solving the above described disadvantages and aims to provide an improved analog signal switching device for use in optical memory devices in which the switching noise signal can be eliminated. In accordance with the present invention there is provided a signal switching device for use in an optical memory device having a main signal input an analog switch which is selectively operable to connect at least one input thereof to a switch output thereof in accordance with the state of a switch signal (SCS) characterised in that the signal switching device further comprises: a mask signal generator for generating a mask signal which is present during operation of the analog switch; and gate means responsive to the mask signal for connecting the switch output and a signal output of the device in the absence of the mask signal and inhibiting connection in the presence of the masking signal, whereby noise signals produced during operation of the analog switch is substantially eliminated. According to the aforementioned construction, when the analog switch switches, the mask signal generator generates a mask signal for at least the period in which switching noise is generated by the switching operation. This mask signal masks the signal output by the analog switch by, for example, a gate circuit, and stops or resets the demodulation circuit or PLL circuit connected to the analog switching device. Because it is possible to prevent misoperation of a digital signal processing circuit, etc., due to switching noise the reliability of the optical memory device is improved. These and other objects and features of the present invention will become apparent from the following description taken in conjunction with a preferred embodiment thereof with reference to the accompanying drawings, throughout which like parts are designated by like reference numerals, and in which: Fig. 1 is a block diagram of a conventional analog switching device; Fig. 2 is a graph showing waveforms of signals obtained at various parts of the analog switching device of Fig. 1; Fig. 3 is a block diagram of an analog switching device according to the present invention; Fig. 4 is a circuit diagram of the sample hold circuit used in the circuit of Fig. 3; Figs. 5, 6 and 7 are circuit diagrams showing different embodiments of the mask generation circuit used in the circuit of Fig. 3; Fig. 8 is a circuit diagram of the gate circuit used in the circuit of Fig. 3; and Fig. 9 is a graph showing waveforms of signals obtained at various parts of the analog switching device of Fig. 1. Referring to Fig. 3, an analog signal switching device 20 for optical memory devices is shown which includes an analog switch 21, a sample hold circuit 23 and a mask signal generator 24. An input terminal 22 is directly connected to terminal 21a of analog switch 21, and indirectly to another terminal 21b of analog switch 21 through a sample hold circuit 23. The analog switch 21 is operated by a switch control signal SCS produced from a switch control signal generator 28. The switch 21 operates so that generator 28 is set to produce a HIGH level SCS signal (see Fig. 3) when the optical memory device employing switching device 20 is set to a mode for recording or erasing, and a LOW level SCS signal when the optical memory device is set to a mode other than the recording and erasing modes. When SCS is HIGH, i.e., during the recording or erasing mode, terminal 21b is connected to terminal 21c, and when SCS is LOW terminal 21a is connected to terminal 21c. The switch control signal SCS is also used in the sample hold circuit 23 and in the mask signal generator 24, as described below. As shown in Fig. 4, the sample hold circuit 23 includes an analog switch 32 for receiving the signal from input terminal 22 through a resistor 31, a capacitor 33 for holding the input signal when the analog switch 32 is open, and a buffer 34. the LOW and HIGH levels respectively turn the switch control signal SCCH analog switch 32 on and off. Accordingly, when the optical memory device is in the recording or erasing mode, the analog switch 32 opens so that capacitor 33 holds a signal immediately before the opening of analog switch 32. Thus, during the recording or erasing mode, sample hold circuit 23 produces a constant signal held in capacitor 33, and during a mode other than the recording and erasing mode, sample hold circuit 23 produces a signal relative to the signal obtained from input terminal 22. Referring to Fig. 5 a mask signal generator 24-1 according to one preferred embodiment is shown. The mask signal generator 24-1 includes a monostable multivibrator 41, a NOR gate 44, a low pass filter 45 and an inverter 46. One input A of multivibrator 41 receives the signals SCS and the other input B thereof receives a constant voltage signal. The Q output of multivibrator 41 is connected to one input of the NOR gate 44. The other input of the NOR gate 44 receives the signal SCS. AN output of the NOR gate 44 is applied to the inverter 46 through the low pass filter 45 to produce a mask signal. The mask signal generator 24-1 operates such that in response to the leading edge of the switch control signal SCS, the NOR gate 44 produces a LOW level signal which is filtered in the low pass filter 45 and inverted to a HIGH level signal by the inverter 46. Thereafter, in response to the trailing edge of the switch control signal SCS, the multivibrator 41 is activated to produce a pulse having a pulse width T1. T1 is determined by the resistor 42 and the capacitor 43 coupled to the multivibrator 41. The pulse produced from the multivibrator 41 is applied to the NOR gate 44. Accordingly, when the switch control signal SCS goes LOW, the output from the NOR gate 44 remains LOW for time T1. Although some overshoot or preshoot ripples may appear at the trailing edge and/or leading edge of the switch control signal SCS, these ripples can be eliminated by the low pass filter 45. The inverter 46 produces a HIGH level signal, which is used as a mask signal, that begins in response to the leading edge of the switch control signal SCS and continues until a period T1 after the trailing edge of the signal SCS, as shown in Fig. 9. Referring to Fig. 6 a mask signal generator 24-2 according to another preferred embodiment is shown. Mask signal generator 24-2 includes an inverter 51 for receiving the switch control signal SCS, a clock generator 52, an N-bit shift register 53 defined by a plurality of flip-flops, and an inverter 54. The mask signal generator 24-2 operates such that in response to the leading edge of the switch control signal SCS, the inverter 51 produces a LOW level signal which clears the N-bit shift register 53. The shift register 53 is maintained in the cleared condition for the whole time that the LOW level signal from the inverter 51 is provided to the shift register 53. Thus, when the signal from inverter 51 is LOW, i.e., when the SC signal is HIGH, the last flip-flop, as well as the others in the shift register 53 produced a LOW level signal from its Q terminal, and a LOW level signal is applied to the inverter 54 from the output terminal Q of the last flip-flop. Thereafter, when the switch control signal SCS goes LOW, the inverter 51 produces a HIGH level signal to activate the shift register 53. The LOW level signal carried by each flip-flop is shifted towards the inverter 54 in response to each clock from the clock generator 52 and, at the same time, a HIGH level signal applied to the input terminal D of the shift register is sequentially shifted towards the inverter 54. Even after the switch control signal SCS has changed from HIGH to LOW, the last flip-flop in the shift register 53 continues to produce a LOW level signal for a time T1, i.e., until the HIGH level signal from the input terminal D of the shift register 53 is shifted to the output terminal Q. Accordingly, the inverter 54 produces a HIGH level signal, which is used as a mask signal that begins in response to the leading edge of the switch control signal SCS and continues for a time T1 after the trailing edge of the signal SCS, as shown in Fig. 9. Referring to Fig. 7 a mask signal generator 24-3 according to a further preferred embodiment is shown. Mask signal generator 24-3 includes an inverter 61 for receiving the switch control signal SCS, a clock generator 62, an N-bit counter 63, and flip-flops 64 and 65. The mask signal generator 24-3 operates such that in response to the leading edge of the switch control signal SCS, the inverter 61 produces a LOW level signal which clears the N-bit counter 63 and, at the same time, presets the flip-flops 64 and 65. Thus, the Q terminal of the flip-flops 64 and 65 produces a HIGH level signal. Thereafter, when the switch control signal SCS is changed to LOW, the inverter 51 produces a HIGH level signal for activating the counter 63 to start counting clock pulses from the clock generator 62. When the counter 63 counts N clock pulses corresponding to a time T1, it produces a negative going pulse to the D terminal of the flip-flop 64, and in turn, the Q terminal of the flip-flop 64 produces a negative going pulse for clearing the flip-flop 65. Thus, the flip-flop 65 changes its output from HIGH to LOW. Thus, even after the change of the switch control signal SCS from HIGH to LOW, the flip-flop 65 continues to produce a HIGH level signal from its Q terminal for a further time T1, i.e., until the counter 63 counts N clock pulses. Accordingly, the flip-flop 65 produces a HIGH level signal from its Q terminal which is used as a mask signal that begins in response to the leading edge of the switch control signal SCS and continues for an extra time T1 beyond the trailing edge of the signal SCS, as shown in Fig. 9. In general, the mask signal generator 24 generates a mask signal when the switch control signal SCS is HIGH until a specified time T1 has elapsed after the signal SCS becomes low. That is, at least for the period during which switching noise is generated by the switching operation of the analog switch 21. Referring back to Fig. 3, the terminal 21c of analog switch 21 is connected to a non-inverting input of the comparator 25, and is also connected through the voltage generator 26 to an inverting input of the comparator 25. Output signals from the comparator 25 and the mask signal generator 24 are applied to a gate circuit 27 defined, as shown in Fig. 8, by an AND gate 71 and an inverter. In operation, during a mode other than the recording/erasing mode, the playback analog signal applied to the input terminal 22 is relatively small compared to the analog signal applied to input terminal 22 during the recording/erasing mode, as shown in Fig. 9. Thus, during the mode other than the recording/erasing mode, the switch control signal SCS is maintained LOW, so that the analog switch 21 is switched to the position shown in Fig 3 to connect the terminals 21a and 21c. In this case, the mask signal generator 24 produces a LOW level signal to open the gate circuit 27 to permit the output signal from the comparator 25 to pass through the gate circuit 27. Then, when the mode is changed to the recording/erasing mode, the analog signal applied to the input terminal 22 is several times greater than that applied during the mode other than the recording/erasing mode, as shown in Fig. 9. During the recording/erasing mode, the switch control signal SCS is made HIGH, so that the analog switch 21 is switched to connect the terminals 21b and 21c and, also so that the sample hold circuit holds the analog signal immediately preceding the switch control signal SCS changing to HIGH. Thus, the analog switch 21 continues to output a reasonable level analog signal during the mode other than the recording/erasing mode. Although the signal output from the terminal 21c of the analog switch 21 is one from which excessively high level signals have been removed, the signal output still contains switching noise signals N1 and N2 generated when the analog switch 21 switches. The signals containing switching noise signals N1 and N2 is then compared with the output signal of the voltage generator 26 by the comparator 25 to produce a binary signal which is used as a digital signal. At this point the digital signal contains noise pulses P1 and P2 based on the switching noise signals N1 and N2. More specifically, noise signals N1 and N2 shown in Fig. 9 appear at the output of analog switch 21 in response to the leading edge and the trailing edge of the HIGH level switch control signal SCS. This results in unwanted noise pulses P1 and P2 produced by the comparator 25. Here, even if a peak detection method, or the like, is used in place of a method using the comparator 25 and the voltage generator 26 to binary convert the analog signal to a digital signal, the digital signal can still contain noise pulses P1 and P2. Furthermore, in response to the switch control signal SCS, the mask signal generator 24 produces a HIGH level mask signal which lasts longer than the HIGH level switch control signal SCS, by a time T1 as shown in Fig. 9. In other words, the mask signal generator 24 outputs a high mask signal when the switch control signal SCS is high and for the additional period T1 after the signal becomes low, i.e. for the period until time T1 has elapsed after the terminal connected to the terminal 21c of the analog switch 21 switches from the terminal 21a to the terminal 21b and then returns to terminal 21a again. While the mask signal is high, the gate circuit 27 closes to prevent the signal output from the comparator 25 passing therethrough. Accordingly, noise pulses P1 and P2 are removed from the output signal of the gate circuit 27. Only appropriate digital signals are output from the gate circuit 27. Therefore, improper operation of digital signal processing circuits etc., as a result of switching noise signals N1 and N2 generated during switching of the analog switch 21 is easily avoided. It is to be noted that according to a preferred embodiment of the present invention in which the output signal of the comparator 25 based on the mask signal output from the mask signal generator 24 is masked using a gate circuit 27, has been described. The present invention is not, however, limited to this embodiment. It is also impossible to prevent improper operation by, for example, stopping or resetting a digital signal processing circuit for the period in which switching noise signals N1 and N2 are generated by using a mask signal output from the mask signal generator 24 to control a digital signal processing circuit such as a demodulation circuit or PLL circuit (phase locked loop circuit) connected to the analog signal switching device 20. Furthermore, a particularly significant effect is obtained when preventing the effects of signal noise generated when an analog switch is switched between signals to remove excessively high level playback analog signals in the aforementioned manner. The effect is not, however, limited to this, and a similar effect can also be obtained when switching between multiple input analog signals.

Claims: A signal switching device for use in an optical memory device having an analog switch (21) which is selectively operable to connect one of a plurality of inputs (21a, 21b) thereof to a switch output (21c) thereof in accordance with the state of a switch control signal (SCS) characterised in that the signal switching device further comprises: a mask signal generator (24) for generating a mask signal which is present during operation of the analog switch; and gate means (27) responsive to the mask signal for connecting the switch output (21c) and a signal output of the device in the absence of the mask signal and inhibiting connection in the presence of the masking signal, whereby noise signals produced during operation of the analog switch can be substantially eliminated. A signal switching device according to claim 1 wherein the signal switching device is operable for use in an optical memory device having a first recording/erasing mode and a second mode other than the recording/erasing mode, further comprising means (28) for generating the switch control signal, the switch control signal (SCS) having a first (HIGH) state providing the mask signal during the first mode and a second (LOW) state providing the absence of a masking signal during the second mode, and wherein the analog switch (21) connects the switch output (21c) with the input (21a) providing a first (direct) signal during the second (LOW) state of the switch control signal, and with the input (21b) providing a second (held) signal during the first (HIGH) state of the switch control signal. A signal switching device according to claim 2 wherein the first (direct) signal is analog and further comprising sample hold circuit means (23) for holding the first (direct) signal during the second (LOW) state of the switch control signal (SCS) to provide the second (held) signal, and a digital signal generator (25, 26) for converting the signal at the switch output (21c) into a digital signal. An analog signal switching device according to any one of claims 1 to 3 wherein said mask signal starts in response to the change in the state of said switch control signal and ends a predetermined time (T1) after the change in state of said switch control signal. An analog signal switching device according to any one of claims 1 to 3 wherein the mask signal generator (24-1) comprises a multivibrator (41) for producing a pulse having a predetermined time width (T1) after the change from second to first state of said switch control signal (SCS). An analog signal switching device according to any one of claims 1 to 4, wherein the mask signal generator (24-2) comprises a shift register (53) for shifting data a predetermined time (T1) after the change from the second to the first state of said switch control signal (SCS). An analog signal switching device according to any one of claims 1 to 4, wherein said mask signal generator (24-3) comprises a counter (63) for counting a predetermined time (T1) after the change from the second to the first state of said switch control signal.

Inventors: DEGUCHI, TOSHIHISA, FUJI, HIROSHI, KOJIMA, KUNIO, MAEDA, SHIGEMI, TERASHIMA, SHIGEO, YAMAGUCHI, TAKESHI
Applicants: SHARP KABUSHIKI KAISHA
Application year: 1989
Main classification: G11B13
IPC codes: G11B7, G11B19, G11B11, G11B20