Color signal processing apparatus

Abstract: A color signal processing apparatus of the kind demodulating a carrier chrominance signal of the PAL system into color-difference signals, processing the color-difference signals and modulating the processed color-difference signals back into the carrier chrominance signal is arranged to demodulate the carrier chrominance signal to obtain demodulated color-difference signals by using a clock signal which is phase-locked to a reference phase of the carrier chrominance signal; to add the cur­ rently demodulated color-difference signals to the color-difference signals demodulated one horizontal scanning period before; and after that, to process the color-difference signals to be output. This arrange­ ment enables the apparatus to form the process the color-­ difference signals with an unvarying hue without being affected by variations in temperature and power supply voltage.

Description: This invention relates to a a color signal processing apparatus arranged to convert a carrier chrominance signal conforming to the PAL system into color-difference signals; to perform various color signal processing actions; and, after that, to modulate the signals back into the carrier chrominance signal. In carrying out a digital processing operation such as a noise reduction process on a composite video signal using, for example, a field memory, etc., the video signal is preferably demodulated into baseband signals such as a luminance signal and color-difference signals for the digital processing action. In this instance, the demodulation of the composite video signal necessitates two different processes including (1) a process of separating the signal into a luminance signal (hereinafter referred to as a Y signal) and a carrier chrominance signal (hereinafter referred to as a C signal) and (2) a process of demodulating the C signal into color-difference signals. In the process (2), baseband color-difference signal components are obtained in a digital signal form by directly A/D (analog-to-digital) converting the C signal using two different sampling clock signals which are locked to the color burst signal of the C signal. In the case of the color TV signal of the NTSC system, for example, an NTSC composite video signal is first separated into Y and C signals. After that, the C signal is A/D converted with a sampling clock signal of a frequency which is four times as high as the frequency of the color burst signal. During this A/D converting process, if the sampling clock signal is accurately phase-locked to the phase 0°, 90° 180° or 270° of the color burst signal, sample data obtained at 180° can be regarded as a color-difference B-Y signal and sample data obtained at 270° as another color-difference R-Y signal. The carrier chrominance signal is demodulated into two color-difference signals by sorting out these sample data by means of a subcarrier frequency fsc. Further, in modulating the color-difference signal components into the C signal, data of 0° is obtained from the data of 180° phase and data of 90° from the data of 270° phase by inverting the polarity of the data. They are thus D/A converted one after another. For example, with the 180° phase data which is obtained by A/D converting the C signal assumed to be expressed as D180, the 0° phase data D0 can be expressed as follows: D0 = - (D180 - Dce), wherein Dce represents the DC offset value of the C signal. While the NTSC system color TV signal is processed in the above-stated manner, the digital process for the PAL system signal is performed as follows: In this case, the carrier wave of the color-difference R-Y signal is inverted for every scanning line. Therefore, the data to be sorted out must be changed from one data over to the other for every scanning line by monitoring the burst phase of the scanning lines. In the case of the PAL system, the B-Y signal carrier wave is fixed at 90°. The R-Y signal component is at 0° (the color burst phase at this time is 315° and at 180° (the color burst phase at that time is 225°). Demodulation is performed by sorting A/D converted data of them. In the noise reduction process, etc. on the signal of the NTSC, the series of processes, i.e., demodulation, signal processing and modulation, can be carried out without any difficulty as long as the quadratic relation is maintained even if the demodulation axis is not absolutely determined as mentioned above. Therefore, the sampling clock signal to be used for the A/D conversion is only required to be in synchronism with a frequency which is four times as high as the frequency of the carrier wave. The phasic relation of the sampling clock signal is ignorable. Whereas, the signal of the PAL system presents the following problem: Fig. 1 of the accompanying drawings is a vectorial representation of quadrature demodulation performed without phase-locking the demodulation axis to B-Y and R-Y axes. The carrier chrominance signal is shown as a vector OA by a line A and as a vector OB by a line B. The carrier chrominance signal is demodulated by A/D converting it with a sampling clock signal which deviates as much as a phase  from the B-Y and R-Y axes. Then, the color components becomes as expressed below: Line A --- C XA = r cos ( - ) C YA = r sin ( - ) Line B --- C XB = r cos ( + ) C YB = r sin ( + ) wherein r represents the absolute value of vectors OA and OB, ie., the amplitude of the carrier chrominance signal. Since the color signal components thus vary with the scanning line, it is impossible to maintain an adequate hue when inter-field processing is performed. In GB-A-2145903 there is described a sampled data signal processing apparatus for digital signal processing in a color television receiver. In this apparatus the composite color television signal is converted into a digital signal and then a digital chrominance signal is separated from the digital signal and a digital (R - Y) signal and digital (B - Y) signal are demodulated from the separated digital chrominance signal. According to the present invention a color signal processing apparatus for processing a carrier chrominance signal conforming to the PAL system by converting the carrier chrominance signal into a base band signal, performing a predetermined processing on the base band signal and then converting the base band signal back into the carrier chrominance signal, characterised by: (A) clock signal forming means for forming a clock signal which is phase-synchronized with a reference phase of the carrier chrominance signal and has a frequency four times as high as a carrier frequency; (B) first conversion means for converting said carrier chrominance signal into a digital signal on the basis of the clock signal formed by said clock signal forming means and for outputting the digital signal; (C) latching means for phase-synchronizing the digital signal outputted from said conversion means with the clock signal outputted from said clock signal forming means and for latching the digital signal at two different timing points, thereby extracting first and second digital signals; (D) first delay means for delaying the first digital signal latched by said latching means and for outputting the delayed signal; (E) first addition means for adding the first digital signal latched by said latching means and the first digital signal outputted from said first delay means and for outputting the added signal; (F) second delay means for delaying the second digital signal latched by said latching means and for outputting the delayed signal; (G) second addition means for adding the second digital signal latched by said latching means and the second digital signal outputted from said second delay means and for outputting the added signal; (H) digital signal processing means arranged to input the first digital signal outputted from said first addition means and the second digital signal outputted from said second addition means, to perform digital signal processing on said first digital signal and second digital signal and to output the processed signal; (I) second conversion means arranged to input said first digital signal and second digital signal outputted from said digital signal processing means, to convert said first digital signal and second digital signal into analog carrier chrominance signals on the basis of the clock signal formed by said clock signal forming means; and (J) means for forming DC offset component signals corresponding to DC offset components of the first and second digital signals latched by said latching means and for subtracting said DC offset component signals from the first and second digital signals outputted from said signal processing means. How the invention may be carried out will now be described by way of example only and with reference to the accompanying drawings in which: Brief Description of the Drawings: Fig. 1 is a vectorial representation showing the quadrature demodulation of a carrier chrominance signal. Fig. 2 is a block diagram showing in outline the arrangement of a color signal processing apparatus arranged according to this invention as an embodiment thereof. Figs. 3A, 3B and 4 are wave-form charts showing the operation of the embodiment shown in Fig. 2 through wave forms of signals output from the various parts of Fig. 2. Fig. 5 is a block diagram showing in outline the arrangement of a color signal processing apparatus arranged as another embodiment of the invention. Fig. 6 shows the sampling points of color-difference signals of the PAL system as in relation to lines. Detailed Description of the Preferred Embodiments: An embodiment of this invention is arranged as described below with reference to the drawings, in which: Fig. 2 shows in outline the arrangement of a color signal processing apparatus as an embodiment of the invention. Figs. 3A, 3B and 4 show the operation of the color signal processing apparatus through the wave forms of signals output from the various parts of the apparatus. Referring to Fig. 2, the illustration includes an A/D (analog-to-digital) converter 10; latch circuits 12, 14 and 16; full adders 18, 19, 20, 21, 22, 23 and 24; inverters 26, 27 and 28; latch circuits (OC latch circuits) 30, 32, 34 and 36 which are provided with output control (output/high impedance change-over) devices; a D/A (digital-to-analog) converter 38; a PLL circuit 40; a timing controller 42; line memories 43 and 44 for 1 H; and full adders 45 and 46. The latch circuits 12 to 16 and 30 to 36, the inverters 26, 27 and 28 are provided in quantities corresponding to the number of output bits of the A/D converter 10. An input terminal 50 is arranged to input a C signal obtained by Y/C separating a composite video signal. An input terminal 51 is arranged to input a clock signal generated during a horizontal or vertical synchronizing period. An input terminal 52 is arranged to receive a timing signal indicating an interval for a color burst signal. An output terminal 53 is arranged to output the C signal. Input terminals 54, 56 and 58 are arranged to input a fixed value "01" (a hexadecimal value). The output 40A of the PLL circuit 40 is a clock signal of a quadruple frequency locked to the color burst signal of the carrier chrominance signal. The output 40B of the PLL circuit 40 is a clock signal obtained by dividing by four the output 40A and is of a carrier period which is in a fixed phasic relation to the color burst signal of the carrier chrominance signal. The timing controller 42 is arranged to output a clock signal 42A for A/D conversion; clock signals 42B and 42C for C signal demodulation; timing signals 42D, 42E, 42F, 42G and 42H for data transfer; and a clock signal 42J for D/A conver-sion. These outputs of the timing controller 42 are phase-locked to the output 40B of the PLL circuit 40 i.e., to the color burst signal). Data buses 70 and 72 are provided for demodulated color-difference signals. Data buses 74 and 76 are provided for conveying data of opposite polarities generated by a modulation process. The PLL circuit 40 extracts the color burst signal from the C signal obtained from the input terminal 50 in accordance with the timing signal obtained from the input terminal 52. The PLL circuit 40 then produces the clock signal 40B of the carrier period which is in synchronism with the average of the burst signal (180° phase with the B-Y carrier wave assumed to be 90° and also produces the clock signal 40A which is of a frequency four times as high as that of the clock signal 40B (4fsc: fsc represents a color subcarrier frequency). In accordance with this, the timing controller 42 applies the A/D conversion clock signal 42A (of frequency 4fsc) to the A/D converter 10. The C signal from the input terminal 50 is thus converted into digital data. The digital data is supplied to the latch circuits 12, 14 and 16. The timing controller 42 also generates clock signals 42B and 42C (frequency fsc) which is in a fixed phasic relation to the color burst signal. These clock signals 42B and 42C are respectively supplied to the control input terminals of the latch circuits 12 and 14. By this, the data output from the A/D converter 10 is separated into color-difference signal components and demodulated into artificial color-difference signals. Then, the timing controller 42 detects the phase of the color burst signal of the carrier chrominance signal (C signal) obtained from the input terminal 50 and changes the polarity of the clock signal 42C from one polarity over to the other. The artificial color-difference signal components (the outputs of the latch circuits 12 and 14) thus obtained would vary with line if the demodulation axis (A/D sampling phase) fails to coincide with the axes of the B-Y and R-Y components as mentioned in the foregoing. Therefore, the line memories 43 and 44 and the full adders 45 and 46 are arranged to perform inter-line adding operations on the artificial quadrature color-difference signal components. In other words, the signal of the line A and the signal of the ensuing line B are inter-line added. The sums thus obtained can be expressed as follows: C X = C XA + C XB = r [cos( - ) + cos( + )] = 2r cos · cos C Y = C YA + C YB = r [sin( ) + sin( + )] = 2r cos · sin As a result, each of the color components is obtained in the form of having the B-Y or R-Y signal multiplied by a given scalar quantity 2 cos . This makes the hue unvarying. The color-difference signals thus become perfect B-Y and R-Y signals including DC offsets therein. The two signals thus obtained are supplied to the digital signal processing circuit (DSP) 100. The circuit 100 then performs a predetermined signal processing action including image enlarging and composing processes, a noise reduction process, etc. by using a field memory. The signal processing action is performed in a known manner and therefore the detailed description of it is omitted from the description given herein. The color-difference signals of two kinds which have undergone these processes are output from the circuit 100. The digital color-difference signals thus obtained through the digital signal processing circuit (DSP) 100 are modulated to obtain a carrier chrominance signal in the following manner: The latch circuit 16 latches the output of the A/D converter 10 produced during the horizontal synchronizing (hereinafter referred to as sync for short) period in accordance with the timing signal received via the input terminal 51. The A/D converter 10 produces data which includes a DC offset. Assuming that the color signal component is expressed as C X and the DC offset as Dce, data C DX thus obtained is expressed as follows: C DX = C X + Dce Assuming that the data of the opposite polarity to be formed is C PX , the data C PX can be expressed as: C PX = - C X + Dce = - (C DX - Dce) + Dce Therefore, with the full adder and the inverter used, this computation can be expressed as follows: C PX = Dce + C DX + Dce + 1 + 1 In the case of the embodiment described, the latch circuit 16 is caused by the timing signal from the input terminal 51 to hold the A/D converted data of the sync period during which there is no carrier chrominance signal. The value of the data thus held corresponds to the DC offset component Dce shown in the formulas given above. This data is inverted by the inverter 26 and "1" is added to it by the full adder 18. Since the data C DX is obtained from the digital signal processing circuit 100, the data C DX is obtained by means of the full adders 19 and 20. After that, the above-stated computing operation is carried out by means of the full adders 21 to 24 and the inverters 27 and 28. Through the above-stated process, the desired data of the inverted polarity are obtained from the full adders 23 and 24. These data are then supplied to the inverted polarity data buses 74 and 76. The color-difference components output from the digital signal processing circuit 100 are latched together with the data of the inverted polarity data buses 74 and 76 by the latch circuits 30, 32, 34 and 36 in accordance with the clock signal 42D. The output sequence of the data, i.e., digital signals, from these latch circuits is controlled by the output control signals 42E, 42F, 42G and 42H in supplying them to the D/A converter 38. The D/A converter 38 converts these input digital signals into an analog signal in accordance with the clock signal 42J and outputs the analog signal therefrom. The output of the D/A converter 38 is a carrier chrominance which has undergone the predetermined signal processing action. If the DC offset value Dce extracted does not coincide with the A/D converted data of the DC offset of the C signal in the apparatus of the kind arranged as described above, the discrepancy would cause a distortion in the modulated wave form. Whereas, in the case of this embodiment, the A/D converted data obtained during the horizontal sync period which is devoid of the carrier chrominance signal is used as the DC offset value Dce to be added. This ensures that the DC offset value extracted is very accurate. This effectively prevents any modulation distortion that results from the individual variations of the analog circuit element constants, variations of the power supply voltage, etc.. In the arrangement described, the DC offset of the color-difference signals supplied to the latch circuits 30 and 32 is processed by the digital signal processing circuit 100 at a timing different from a timing at which the DC offset value Dce output from the latch circuit 16. However, this timing discrepancy presents no problem as a period of time required for any variation in the DC offset is sufficiently longer than the processing period of time required by the digital signal processing circuit 100. Further, for increased accuracy of the DC offset value Dce, the DC offset value may be sampled a plurality of times during one horizontal sync period and a value obtained by averaging these sampled values may be used as the value Dce in the above-stated computing process. In the embodiment described, the inter-line addition is performed within one and the same field by means of the line memories 43 and 44. However, this may be changed to an inter-frame adding operation. Fig. 5 is a block diagram showing the arrangement of another embodiment of the invention. In Fig. 5, the components which are arranged in the same manner as those shown in Fig. 2 are indicated by the same reference numerals and the details of them are omitted from the following description. Referring to Fig. 5, the PLL circuit 40 is arranged to extract the color burst signal from the C signal from the input terminal 50 in accordance with the timing signal coming via the input terminal 52. The PLL circuit 40 then produces a clock signal 40B which is synchronized with the average of the color burst signal (180° phase with the phase of the B-Y carrier wave assumed to be at 90°) and another clock signal 40A which is of a frequency four times as high as that of the clock signal 40B (4fsc: fsc represents a color subcarrier frequency). The timing controller 42 is arranged to produce an A/D conversion clock signal 42A (of the frequency 4fsc) according to the clock signal 40A. The clock signal 42A is supplied to the A/D converter 10. By this, the C signal received at the input terminal 50 is converted into digital data. The digital data is then supplied to latch circuits 12, 14 and 16. The timing controller 42 further generates clock signals 42B and 42C (of frequency fsc) which are in a given phasic relation to the color burst signal. These clock signals 42B and 42C are supplied to the control terminals of the latch circuits 12 and 14 respectively. By this, the data output from the A/D converter 10 is separated and demodulated into color-difference components. Artificial color-difference signals are thus obtained. Then, the timing controller 42 detects the phase of the color burst signal of the carrier chrominance signal (or the C signal) obtained via the input terminal 50 and changes the polarity of the clock signal 42C from one polarity over to the other polarity. The artificial color-difference components (the outputs of the latch circuits 12 and 14) which are thus obtained would vary with the line if the demodulation axis (the A/D conversion sampling phase) does not coincide with the axes of the B-Y and R-Y components as mentioned in the foregoing. To solve this problem, an inter-line adding operation is performed on each of the artificial color-difference components by means of line memories 43 and 44, a delay circuit 47 which is arranged to delay its input for a period of time corresponding to one sampling period of time (i.e., a D type flip-flop), a selection circuit 48 which is arranged to select either the output of the line memory 44 or that of the delay circuit 47 and full adders 45 and 46. In other words, an inter-line adding operation is performed on the signals of alternate lines A and B. The sums thus obtained can be expressed as follows: C X = C XA + C XB = r [cos( - ) + cos( + )] = 2r cos · cos C Y = C YA + C YB = r [sin( - ) + sin( + )] = 2r cos · sin As a result, each color component is obtained in the form of having the B-Y or R-Y signal multiplied by a given scalar quantity 2 cos . The hue becomes unvarying. This arrangement gives perfect B-Y and R-Y color-difference signals although they include some DC offset. In the embodiment shown in Fig. 5, the inter-line adding operation on the artificial R-Y component is carried out by switching a signal obtained by delaying the input signal to a degree corresponding to 283 samples over to a signal obtained by delaying the input signal to a degree corresponding to 284 samples and vice versa by means of the line memory 44, the delay circuit 47, the selection circuit 48 and the full adder 46. The reason for this: In the case of the color-difference signals conforming to the PAL system, the phase of the B-Y color-difference signal varies 90 degrees between lines. Then, the phase of the R-Y color-difference signal varies between +90 degrees and -90 degrees relative to that of the B-Y signal on alternate lines. In view of this, the embodiment is arranged to perform a thinning-out process on each color-difference signal that only has different polarities within one and the same carrier wave period. The relation of the sampling points at which the B-Y and R-Y signals are sampled to the lines is as shown in Fig. 6. Referring to Fig. 6, with respect to the B-Y signal, picture element values delayed by 284 samples are inphase signals located closest on the picture. In the case of the R-Y signal, inphase signals located closest alternate between picture element values delayed by 283 samples and picture element values delayed 284 samples on alternate lines. The embodiment is thus arranged to have the delayed R-Y signal alternate between a signal delayed by 283 samples from the input signal and a signal delayed 284 samples on every other line in adding the delayed signal. Compared with the embodiment shown in Fig. 2, this embodiment further enhances the accuracy of demodulation of the color-difference signals by virtue of this arrangement. The outputs of the full adders 45 and 46 are supplied to the digital signal processing circuit (DSP) 100. The DSP 100 performs a predetermined digital signal processing action with a field memory, including image enlarging and composing processes, a noise reducing process, etc.. The digital signal processing action is performed in a known manner and, therefore, its details are omitted from description. As a result of these processes, color-difference signals of two different kinds are output from the digital signal processing circuit 100. The digital color-difference signal output from the circuit 100 is modulated into a carrier chrominance signal in the same manner as in the case of the embodiment shown in Fig. 2 and described in the foregoing. In accordance with this invention, color-difference signals having a constant hue are obtainable by the inter-line adding operation on the demodulated artificial color-difference signal components. The demodulated color-difference signal components become accurate B-Y and R-Y color-difference signals. Therefore, a color signal processing operation can be carried out without strictly adjusting the phase of the A/D converting clock signal to that of the carrier chrominance signal. Further, the invention prevents modulation distortions due to the individual deviations of constants of analog circuit elements, variations in the power supply voltage, etc..

Claims: A color signal processing apparatus for processing a carrier chrominance signal conforming to the PAL system by converting the carrier chrominance signal into a base band signal, performing a predetermined processing on the base band signal and then converting the base band signal back into the carrier chrominance signal, characterised by: (A) clock signal forming means (40) for forming a clock signal which is phase-synchronized with a reference phase of the carrier chrominance signal and has a frequency four times as high as a carrier frequency; (B) first conversion means (10) for converting said carrier chrominance signal into a digital signal on the basis of the clock signal formed by said clock signal forming means (40) and for outputting the digital signal; (C) latching means (12, 14, 16) for phase-synchronizing the digital signal outputted from said conversion means (10) with the clock signal outputted from said clock signal forming means (40) and for latching the digital signal at two different timing points, thereby extracting first and second digital signals; (D) first delay means (43) for delaying the first digital signal latched by said latching means and for outputting the delayed signal; (E) first addition means (45) for adding the first digital signal latched by said latching means (12) and the first digital signal outputted from said first delay means and for outputting the added signal; (F) second delay means (44) for delaying the second digital signal latched by said latching means and for outputting the delayed signal; (G) second addition means (46) for adding the second digital signal latched by said latching means (14) and the second digital signal outputted from said second delay means and for outputting the added signal; (H) digital signal processing means (100) arranged to input the first digital signal outputted from said first addition means and the second digital signal outputted from said second addition means, to perform digital signal processing on said first digital signal and second digital signal and to output the processed signal; (I) second conversion means (38) arranged to input said first digital signal and second digital signal outputted from said digital signal processing means, to convert said first digital signal and second digital signal into analog carrier chrominance signals on the basis of the clock signal formed by said clock signal forming means; and (J) means (16 to 24) for forming DC offset component signals corresponding to DC offset components of the first and second digital signals latched by said latching means and for subtracting said DC offset component signals from the first and second digital signals outputted from said signal processing means. An apparatus according to Claim 1, wherein said first delay means is arranged to effect a delay of the first digital signal latched by said latching means for one horizontal scanning period and to output the delayed signal. An apparatus according to Claim 1 or 2, wherein said second delay means is arranged to effect a delay of the second digital signal for one horizontal scanning period and to output the delayed signal. An apparatus according to claim 1, 2 or 3 wherein said means (J) is arranged to extract, from a digital signal outputted from said conversion means, a third digital signal corresponding to a part of the carrier chrominance signal corresponding to a horizontal synchronisation period, and to form the DC offset component signals by using the third digital signal in combination with the first and second digital signals outputted from said signal processing means. An apparatus according to any preceding claim, wherein said second delay means is arranged to selectively effect delaying of the second digital signal latched by said latching means for a first period or a second period and to output the delayed signal. An apparatus according to Claim 5, wherein said first period is one horizontal scanning period and said horizontal scanning period and said second period is a period which is longer than the one horizontal scanning period by one sample clock period. An apparatus according to Claim 6, wherein said second delay means is arranged to selectively effect delaying of the second digital signal latched by said latching means for said first period or for said second period in every one horizontal scanning period and to output the delayed signal. An apparatus according to any preceding claim, wherein said digital signal processing means includes a digital memory which is arranged to input the first digital signal outputted from said first addition means and the second digital signal outputted from said second addition means, to store said first digital signal and said second digital signal and to read out the first digital signal and the second digital signal and output these digital signals. An apparatus according to any preceding claim, wherein said digital signal processing means includes a digital computing circuit which is arranged to input the first digital signal outputted from said first addition means and second digital signal output from said second addition means, and to digital computing processing to said first digital signal and said second digital and output the processed digital signals.

Inventors: FUKATSU TSUTOMU, YOSHIMURA KATSUJI, FUKATSU, TSUTOMU, YOSHIMURA, KATSUJI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1989
Main classification: H04N9
IPC codes: H04N9