GATE DIELECTRIC FOR A THIN FILM FIELD EFFECT TRANSISTOR

Abstract: A thin film field effect transistor utilizes a double-layer of dielectric material with a first layer (14) of an insulating crystalline or amorphous material and a second layer (16) of silicon nitride. The first layer has a high dielectric constant and the second layer eliminates pinholes which could occur in the first layer.

Description: GATE DIELECTRIC FOR A THIN FILM FIELD EFFECT TRANSISTOR BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a thin film transis¬ tor device, and more particularly, to an improved gate dielec¬ tric for a thin film transistor. Description of the Related Art In recent years, there has been growing interest in thin film transistors and devices incorporating such thin film transistors, such as various integrated circuits and flat panel displays such as those which employ liquid crystals. Thin film transistors generally comprise source and drain electrodes interconnected by a central layer of semiconductor material having a thickness less than lμ . In a typical thin film field effect transistor, the device operates by creating a conducting channel beneath a source electrode and a drain electrode. The current flow between the electrodes is controlled by the application of a voltage to a gate which is adjacent to, but insulated from, a portion of the semiconductor material. When a positive bias is applied to the gate electrode, negative charges accumulate in the otherwise low conductivity layer of semiconductor material. Thus, the conductivity of the semiconductor material layer is increased, and a source-drain current can be made to flow under the appropriate bias. A gate dielectric material used to provide electrical isolation while permitting an electric field to be applied to the semiconductor and to reduce shorts and capacitance between the gate and the source or the drain. The gate dielectric mate¬ rial is patterned to form a central portion over a planar por¬ tion of the gate region and to cover any exposed gate edges. Sometimes, when the dielectric material is of inferior quality, atomic level defects in the dielectric material or at the dielectric/ semiconductor interface can occur causing charges to become trapped in the dielectric layer. Any charge trapped in the dielectric layer or at the dielectric/semiconductor inter¬ face can degrade performance of the thin film transistor and give rise to hysteresis in the performance and other time depen ¬ dent phenomenon that limit the usefulness of the device in SUBSTITUTESHEET -2- practical applications. ;:Additionally, charge leakage lowers the on/off source-drain current ratio of the device. Furthermore, when the dielectric matrial is of inferior quality, pinholes can occur which can .cause short circuits to occur if a pinhole is under the source or drain. It would be desirable to have a gate dielectric mate¬ rial for a thin film transistor which effectively prohibits charges from becoming trapped in the dielectric layer or at the dielectric/semiconductor interface and which is free of pin¬ holes. It would further be desirable to have a dielectric mate¬ rial with a high dielectric constant for good electrical isola¬ tion characteristics thereby permitting high electric fields to be applied to the semiconductor thus improving performance and permitting high voltages to be switched. And it would also be desirable to have a gate dielectric material comprised of a thin film material thereby maintaining the thin aspect of the overall thin film field effect transistor. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a gate dielectric material with a high dielectric con¬ stant and which prevents charges from becoming trapped in the dielectric layer. It is a further object of the invention to provide a gate dielectric layer which is free of pinholes. It is an additional object of the invention to provide a gate dielectric layer which is made of a thin film material. Additional objects and advantages of this invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instru¬ mentalities and combinations particularly pointed out in the appended clams. To achieve the objects and in accordance with the pur¬ pose of the invention, as embodied and broadly described herein, the invention comprises a dielectric for a gate of a thin film field effect transistor, comprising a first layer of an insu¬ lating thin film crystalline or amorphous material formed on the gate and a second layer of silicon nitride formed on the first layer. The accompanying drawing, which is incorporated in and constitutes a part of this specification, illustrates an embodi¬ ment of the invention and, together with the description, serves to explain the principles of the invention. BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a cross-sectional diagram illustrating a gate dielectric for a thin film field effect transistor in accordance with an embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the drawing. The transistor is formed on a substrate 10 of a suit¬ able material, such as glass. A gate electrode 12 is deposited on the substrate 10. The gate electrode 12 is formed of a suit¬ able metal, such as nichrome or molybdenum. Then, a first layer of gate dielectric material 14 is comprised of insulating thin film material is deposited on the gate electrode 12 and the substrate 10 by a process of atmo¬ spheric chemical vapor deposition using a 5 to 6 percent (atom¬ ic) solution of SiH in N2 and O2. The first layer of gate dielectric material 14 may be comprised of silicon dioxide (Siθ2). Preferably, the first thin film layer is deposited at about 540°C to form a layer of gate dielectric material 14 approximately 800 to 2,500 angstroms thick when measured from the gate electrode 12 to the top of the first layer of gate dielectric material 14. The first layer of gate dielectric material 14 may also be comprised of tantalum pentoxide (Ta2θs) or silicon dioxide or a compound of silicon and nitrogen having a chemical formula SiN x , where x is a number in the range of 0.1 to 1.33 and is prefereably equal to 1.33. The device can be further improved by exposing the first layer of gate dielectric material 14 to a plasma etch using a solution of CF4-O2 or NF3 in order to remove any contam¬ ination due to atmospheric exposure, oxidation, or moisture. -4- - * >r--Ne " t. -a. " second layer of gate dielectric material 16 is deposited on the first layer of gate dielectric material 14. Preferably " ,- the second layer of- gate dielectric material 16 is silicon nitride and is approximately 1,000 angstroms thick when measured from the gate electrode 12 to the top of the gate dielectric material 16. The first layer of gate dielectric material 14 of in¬ sulating thin film material is chosen to provide a high dielec¬ tric constant. For example, silicon dioxide has a dielectric constant equal to 4 and tantalum pentoxide has a dielectric material constant equal to 25. The second layer of dielectric 16 should also have a high dielectric constant, but it is pri¬ marily chosen in order to eliminate pinholes which could occur in the first layer 14 and to provide a clean interface to the subsequent semiconductor layer. Silicon nitride, for example, appears to cover up any pinholes that may occur in the first layer of dielectric material 14. Also, any charge leakage which could cause charges to become trapped in the first layer 14 thereby lowering the on/off source-drain current ratio is pre¬ vented. The device of the present invention achieves an on/off source-drain current ratio equal to about 10' and a breakdown voltage which is greater than 100 volts, as opposed to a break¬ down voltage in prior thin film transistors of from 20 to 40 volts. After the gate dielectric layers 14 and 16 are deposited, a semiconductor layer 30 is deposited over the second gate dielectric layer 16, the first gate dielectric layer 14, the gate electrode 12, and over the substrate 10 preferably by using a glow discharge plasma of silane method. This method of deposition, which is well known to those in the art as glow dis¬ charge, is described in U.S. Patent No. 4,064,521, which is hereby incorporated herein by reference. Semiconductor layer 30 is preferably hydrogenated amorphous silicon (a-Si:H) which pro¬ vides desirable properties for a thin film field effect transis¬ tor such as would be known to one of ordinary skill in the field of thin film transistor fabrication. However, other suitable semiconductor materials may be used, such as crystalline or polycrystalline silicon and gallium arsenide as would be known to one skilled in the art of thin film transistor design. Next, a layer of n+ conductivity type semiconductor material 32 is deposited over the semiconductor layer 30, which can also be comprised of hydrogenated amorphous silicon. N-type conduction occurs when a material has been doped to create excess charge carriers which thereby increase the on-current flow. Lastly, a source electrode 18 and a drain electrode 20 are deposited over the layer 32. The source electrode 18 and the drain electrode 20 are acid etched and then patterned. Source electrode 18 and drain electrode 20 are spaced apart and layer 32 is subjected to a plasma etch leaving a portion of the semiconductor layer 30 exposed which partially overlays the sec¬ ond layer of gate dielectric material 16, the first layer of gate dielectric material 14, and the gate electrode 12. The source electrode 18 and drain electrode 20 are preferably alumi¬ num, however, magnesium, molybdenum, nichrome, or other suitable conductive metals, mixtures of these metals, or alloys of these metals may be used. The double-layer gate dielectric of the present inven¬ tion prevents pinholes from occurring in the gate dielectric material and prevents charge leakage which could give rise to undesirable time dependent phenomenon and which could lower the on/off source-drain current ratio. Moreover, both layers of dielectric material are chosen to obtain high dielectric con¬ stants, thereby achieving a high breakdown voltage. It will be apparent to those skilled in the art that various modifications and variations can be made in the appara¬ tus of the present invention without departing from the scope or spirit of the invention. Thus, it is intended that the present invention cover the modif cations and variations of this inven¬ tion provided they come within the scope of the appended claims and their equivalents.

Claims: WHAT IS CLAIMED IS: 1. A dielectric for a gate of a thin film field effect transistor, comprising: a first layer of insulating thin film crystalline or amorphous material formed on said gate; and a second layer of silicon nitride formed on said first layer. 2. The dielectric of claim 1 wherein said first layer is comprised of silicon dioxide (Siθ2). 3. The dielectric of claim 1 wherein said first layer is comprised of tantalum pentoxide (Ta2θs). 4. The dielectric of claim 1 wherein said first layer is 800 to 2,500 angstroms thick and wherein said second layer is 1,000 angstroms thick. 5. The dielectric of claim 1 wherein said first layer is fabricated by depositing a layer of silicon dioxide using chemical vapor deposition and a 5 to 6 percent (atomic) solution of SiH in N2 and O2. 6. The dielectric of claim 5 wherein said chemical vapor is deposited at about 540°C. 7. The dielectric of claim 1 wherein said first layer is copmrised of silicon dioxide and a compound of silicon and nitrogen having the chemical formula SiN x , where x is a num¬ ber in the range of 0.1 to 1.33. 8. The dielectric of claim 1 wherein the first layer has a dielectric constant approximately equal to 4.0. 9. The dielectric of claim 3 wherein the first layer has a dielectric constant approximately equal to 25.

Inventors: CATALANO ANTHONY W, KERNS RALPH C, CATALANO, ANTHONY, W., KERNS, RALPH, C.
Applicants: SOLAREX CORP, SOLAREX CORPORATION
Application year: 1989
Main classification: H01L27
IPC codes: H01L29