INTERPOLATION CIRCUIT OF AN ENCODER

Abstract: Position data of 2M bits are divided into data of lower M bits and data of higher M bits. The data of lower M bits are stored in a lower memory region (14a) of a ROM (14), the data of higher M bits are stored in a higher memory region (14b), the most significant bit of address data is set to "0", "1" successively by an address changing unit (15), the data of lower and higher M bits are read out from the lower memory region (14a) and the higher memory region (14b) and are synthesized together through a synthesizing unit (17) to obtain position data of 2M bits.

Description: This invention relates to an encoder interpolator circuit which outputs movable element position data by using an A-phase signal and a B-phase signal. An absolute position encoder is available which is capable of detecting, as absolute position, the rotational position of a rotary shaft of a motor or the like for driving a machine tool, etc. Fig. 3 is a block diagram of the interpolator circuit of such an absolute position encoder. An A-phase/B-phase signal generating unit 1 is constituted by a rotary coding disk, a stationary coding disk, a light-emitting element, a light-receiving element and a signal output circuit, none of which are shown. The signal generating unit outputs sinusoidal and cosinusoidal A-phase and B-phase signals of predetermined cycles per revolution. AD converters 2, 3 subject the A- and B-phase signals, respectively, to an analog-digital conversion (AD conversion) to obtain address information in the form of a set of the AD converter output data. Angle data (position data) D A conforming to the A- and B-phase signal levels is read out of the storage area of a ROM 4 designated by the address information. Such an arrangement is disclosed in EP-A-0213904. Though the foregoing is described with regard to one channel, an arrangement can be adopted in which a plurality of channels having different numbers of cycles of the A- and B-phase signals are provided, a predetermined number of items of angle information are interpolated in one wavelength of each channel, and the absolute position of a movable element is detected by using the interpolated data on each channel. An absolute position encoder adapted to detect the angle information by using a plurality of channels having different numbers of cycles has already been filed for patent as International Serial No. PCT/JP89/00506 (US-A-5,121,116). EP-A-0318597 is relevant under Article 54(3) EPC and also discloses a plurality of channels. If the resolution of the AD converters is, say, eight bits, then, when an A-phase signal K·sinϑ and a B-phase signal K·sinϑ are subjected to an AD conversion, a resolution in which the result of calculation with regard to the angle ϑ is 10 bits can be expected. However, the ROM used in the conventional encoder is one in which the output is composed of eight bits; hence, angle data composed of more than eight bits cannot be delivered as an output. If a ROM having an output of 16 bits is used, the expected angle data can be outputted and highly precise position detection is possible. However, the configuration in such case is larger in size and possessed of a greater number of signal lines and therefore cannot be employed in an absolute position encoder which requires to be reduced in size. Accordingly, an object of the present invention is to provide an encoder interpolator circuit in which, even if a ROM having an M-bit output is used, data consisting of a maximum of M·2 m bits data can be outputted in equivalent terms. According to the present invention there is provided an interpolator circuit of an encoder according to the attached claim 1. Preferably, 2M-bit position data is divided into lower-order M-bit data and higher-order M-bit data, the lower-order M-bit data is stored in a lower-order storage area of the ROM, the higher-order M-bit data is stored in a higher-order storage area of the ROM, the lower-order and higher-order items of M-bit data are read out of the lower-order storage area and higher-order storage area by making the most significant bit of address data "0", "1" successively, and these items of data are combined to obtain 2M-bit position data. Brief Description of the Drawings Fig. 1 is a block diagram of an interpolator circuit according to the present invention; Fig. 2 is an operating time chart according to the present invention; and Fig. 3 is an explanatory view of a conventional interpolator circuit. Fig. 1 is a block diagram showing an interpolator circuit in an encoder according to the present invention. Numeral 11 denotes an A-phase/B-phase signal generating unit, which is constituted by a rotary coding disk, a stationary coding disk, a light-emitting element, a light-receiving element and a signal output circuit, none of which are shown, for outputting a sinusoidal and cosinusoidal A-phase signal VAS and B-phase signal VBS. Numerals 12, 13 denote AD converters having an n-bit (eight bits in Fig. 1) resolution for subjecting the A-phase and B-phase signals VAS, VBS, respectively, to an analog-digital conversion. Numeral 14 designates a ROM having (2n+m)-number of address terminals and M-number of output terminals for storing angle data conforming the A-phase and B-phase signals. In actuality, the ROM 14 has 2n (= 16) address terminals A₀ - A₁₅, m (= 1) address terminal A₁₆ to which address data ADm is inputted, and output terminals O₀ - 0₇ of M (= 8) bits. Lower-order eight-bit data of the 2·M (= 16)-bit data is stored in the lower-order storage area 14a for which the address data ADm is "0", and higher-order eight-bit data is stored in the higher-order storage area 14b for which the address data ADm is "1". Accordingly, by making the address data ADm, which applied to the address terminal A16, "0", "1" successively, two items of eight-bit data each are read out of the ROM 14 and data consisting of a total of 2·M (= 16) bits can be obtained by combining these two items of eight-bit data. Numeral 15 denotes an address changing unit for modifying the address data ADm which enters the m (= 1)-bit address terminal A₁₆ of the ROM 14. Numeral 16 designates a timing pulse generating unit for generating a clock signal indicating the timing of AD conversion performed by the AD converters 12, 13 and the timing of address data modification performed by the address changing unit 16. Numeral 17 represents a combining unit for outputting 16-bit angle data upon combining the higher-order eight bit data and lower-order eight-bit data outputted by the ROM 14. Fig. 2 is a time chart for describing the operation of the present invention. AD2n denotes address data of 2n (= 16) bits applied to the address terminals A₀ - A₁₅ of ROM 14, ADm address data of m (= 1) bit applied to the terminal A₁₆ of ROM 14, and DT data of M (= 8) bits outputted by the ROM 14. The overall operation of the present invention will now be described in accordance with Figs. 1 and 2. The first and second AD converters 12, 13 respectively subject the A-phase signal VAS and B-phase signal VBS outputted by the A-phase/B-phase signal generating unit 11 to an AD conversion in synchronism with a clock CLK outputted by the timing pulse generating unit 16, and digital data consisting of a total of 2n (= 16) bits outputted by the AD converters enters the 2n-number of address terminals A₀ - A₁₅ of the ROM 14 as address data AD2n. The address changing unit 15 also inputs "1" address data ADm to the address terminal A₁₆ of the ROM 14 in synchronism with the clock pulse. As a result, eight-bit higher-order data DT is read from the output terminals O0 - O7 of ROM 14 and inputted to the combining unit 17, where the data is stored in a register 17a. Thereafter, the address changing unit makes the address data ADm "0" at a predetermined timing and applies this data to the address terminal A₁₆ of the ROM 14. As a result, now eight-bit lower-order data DT is read from the output terminals O₀ - O₇ of ROM 14 and inputted to the combining unit 17. The combining unit 17 combines the higher-order eight-bit data inputted at the first timing instant and the lower-order eight-bit data inputted at the next timing instant and outputs, to the next stage, position data consisting of a total of 16 bits. Though the present invention has been described in detail based on an embodiment thereof, the invention is not limited to this embodiment but can be modified in various ways within the scope of the claims. For example, though the invention has been described for a case where m = 1, m can be 2 or more, in which case position data having a maximum of 2 m ·M bits would be produced. In accordance with the present invention as described above, digital data consisting of a total of 2n bits obtained by subjecting A- and B-phase signals to an analog-digital conversion is inputted as address data to 2n-number of address terminals of a ROM, and items of M-bit data successively outputted by the ROM by changing m-bit address data inputted to the remaining address terminals of the ROM are combined to produce position data. As a result, even if a ROM having an M-bit output is used, data consisting of a maximum of M·2 m bits data can be outputted in equivalent terms.

Claims: An interpolator circuit of an encoder for outputting position data of a movable element by using an A-phase signal and a B-phase signal, and comprising: AD converters (12,13) for subjecting the A-phase signal and the B-phase signal respectively to analog-digital conversion; and a ROM (14) having address terminals (A₀-A₁₅) coupled to output terminals (B₁-B₈) of the AD converters (12,13), and storing position data conforming to levels of the A-phase signal and B-phase signal; characterised in that: said address terminals of the ROM (14) comprise (2n+m) bits of which n bits are of a lower order and n bits of a higher order; each AD converter (12,13) has a resolution of n bits corresponding to a respective n bits of the ROM (14); the ROM (14) has M-bit output terminals (O₀-O₇); the AD converters (12,13) together output digital data having 2n bits obtained by the analog-digital conversion, with n bits thereof going to the n lower order address terminals of the ROM (14) and the other n bits thereof going to the n higher order address terminals of the ROM (14); an address changing unit (15) is provided for changing the address data inputted to the or each of the m higher order address terminals of the ROM (14); a combining unit (17) is provided for combining successive groups of M data bits outputted from the output terminals (O₀-O₇) of the ROM (14); and the address data inputted to the or each of the m higher order address terminals of the ROM (14) is successively changed by the address changing unit (15), thereby to cause the ROM (14) to output to the combining unit (17) the lower order n bits and the higher order n bits, the combining unit (17) combining these 2n bits to increase the number of bits of position data outputted by the interpolator circuit. An interpolator circuit of an encoder according to claim 1, characterised by having a timing signal generating unit (16) for outputting a clock signal indicating analog-digital conversion timing and a clock signal indicating address data change timing. An interpolator circuit of an encoder according to claim 1 or 2, characterised in that m = 1.

Inventors: TANIGUCHI MITSUYUKI F MANSHON, TANIGUCHI, MITSUYUKI, F.MANSHON HARIMOMI 8-205
Applicants: FANUC LTD, FANUC LTD.
Application year: 1989
Main classification: G01D5
IPC codes: G01D5