Data processor with zero execution clock count for conditional branch instruction

Abstract: The data processor of this invention makes zero the execution clock count of a branch instruction, a compare instruction, or a compare instruction and follow­ ing branch instruction when a series of instructions executed in the past is again executed. The data processor of this invention is provided with a history storage unit (4a; 4b; 4c; 4d) which stores as its address tag the address of an instruction executed before the branch instruction or compare instruction, and stores the address of an instruction to be executed next the branch or compare instruction or both instruction code of an instruction to be executed next the branch or compare instruction and an address used for pre-fetching an instruction following the instruction code. While the instruction before the branch or compare instruction is decoded, the history storage unit is searched to obtain an instruction to be next executed. The obtained instruction is executed immediately after the execution of the instruction immediately before the branch or compare instruction. If the instruction for which execution clock count is to be made zero, includes a compare instruction, in parallel with the execution of the obtained instruc­ tion, a comparison is carried out by using the operand information of the compare instruction stored in the history storage unit. If the instruction for which execution clock count is to be made zero, includes a conditional branch instruction, in parallel with the execution of the obtained instruction, a verification of a branch prediction is carried out by using the condition code of the branch instruction stored in the history storage unit.

Description: BACKGROUND OF THE INVENTION The present invention relates to a data processor capable of making zero the execution clock count for a branch instruction, a compare instruction, or a compare instruction with its following branch instruction when a series of instructions executed once is again executed during pipeline processing. A conventional data processor which executes a branch instruction at high speed is known as shown having the arrangement of Fig. 4. In Fig. 4, reference numeral 11 designates an instruction pre-fetch unit for pre-fetching an instruction code; 12 an instruction decoding unit for decoding an instruction code pre-fetched by the instruction pre-fetch unit 11; 13 an instruction execution unit for executing an instruction in accordance with the control information obtained from the instruction decoding unit 12; 14 a history storage unit for storing a branch target instruction code and its address when a branch instruction is executed; 15 a branch prediction unit for obtaining the branch target instruction code and its address from the history storage unit 14 and outputting them to the instruction decoding unit 12 and instruction pre-fetch unit 11, respectively, prior to the execution of the branch instruction, 16 a branch target comparison unit for comparing the branch target address outputted from the branch prediction unit 15 with the address of an instruction to be executed next the branch instruction; 17 an input-output bus for the connection to a memory, an I/O device and the like; and 18 a bus control unit for controlling the input-output bus 17 under arbitration among data input-output requests from the instruction pre-fetch unit 11 and instruction execution unit 13. Fig. 5 shows the structure of the history storage unit 14 shown in Fig. 4, wherein reference numeral 141 designates an address tag field for storing the address of an instruction executed immediately before a branch instruction; 142 a branch target instruction field for storing an instruction code of a predetermined word length located at the branch target address of a branch instruction; 143 a branch target address field for storing the branch target address of a branch instruction; and 144 a valid bit indicating that the data in the corresponding entry are valid. In the conventional data processor constructed as above, a branch instruction, if it is executed for the first time is decoded by the instruction decoding unit 12 and thereafter executed at the instruction execution unit 13. If the branch is taken, the branch target address calculated at the instruction execution unit 13 is given to the instruction pre-fetch unit 11 to read a new branch target instruction code. In this case, the history storage unit 14 stores in the address tag field 141 the address of an instruction which was executed immediately before the branch instruction and is held in the instruction execution unit 13, in the branch target address field 143 the branch target address calculated by the instruction execution unit 13, and in the branch target instruction field 142 the read-out branch target instruction code, respectively in the same entry. The valid bit 144 is set to "1" indicating that the data in the entry are valid. Assume that the same branch instruction is thereafter executed again. The instruction decoding unit 12 decodes an instruction immediately before this branch instruction, and at the same time the branch prediction unit 15 searches the history storage unit 14 by using the address of the instruction under decoding. In this case, the address hits the address tag field 141, and the branch prediction unit 15 predicts a taken branch without waiting for the execution of the branch instruction, and obtains the branch target instruction code and its address respectively from the branch target instruction field 142 and branch target address field 143 to send them to the instruction decoding unit 12 and instruction pre-fetch unit 11, respectively. The instruction decoding unit 12 starts decoding the branch target instruction code received from the branch prediction unit 15 immediately after the end of decoding the branch instruction. The instruction pre-fetch unit 11 cancels the pre-fetched instruction and pre-fetches an instruction at the address advanced from the branch target address received from the branch prediction unit 15 by the amount corresponding to the word length of the branch target instruction field 142. After the branch instruction is executed at the instruction execution unit 13 to determine the address of an instruction which is to be executed next the branch instruction, the branch target comparison unit 16 compares the determined address with the branch target address outputted from the branch prediction unit 15, to thereby verify the false/true of the branch prediction. If the comparison result shows a difference therebetween, the valid bit 144 is reset to "0". The instruction decoding unit 12 cancels the instruction under decoding, and the instruction pre-fetch unit 11 cancels the pre-fetched instruction and pre-fetches a new instruction in accordance with the address of the instruction to be executed next the branch instruction, the address having been determined by the instruction execution unit 13. If a branch instruction was taken in the past, there is a high possibility that the same branch instruction is taken when it is executed again. In such a case, the instruction execution 13 can execute the branch target instruction after the execution of the branch instruction, without any wait time. Fig. 6 is a timing chart illustrating the operation of the data processor described above. Instructions processed in the instruction pre-fetch unit 11, branch prediction unit 15, instruction decoding unit 12, instruction execution unit 13 and branch target comparison unit 16 are illustrated in units of clock. It is assumed herein that the clock count necessary for each unit is one clock. When the branch prediction unit 15 searches at clock t2 the history storage unit 14 in accordance with the address of an instruction (instruction b ) immediately before a branch instruction, the address hits the address tag field 141 so that the branch prediction unit 15 sends the branch target instruction code and its address respectively to the instruction decoding unit 12 and instruction pre-fetch unit 11. In this case, however, the instruction decoding unit 12 does not decode it immediately at that time. The presence of the branch instruction (instruction c ) is detected at clock t3 upon decoding of the branch instruction by the instruction decoding unit 12. The instruction decoding unit 12 then starts decoding a branch target instruction code (instruction m ), and the instruction pre-fetch unit 11 pre-fetches an instruction (instruction n ) in accordance with the address advanced from the branch target address by the amount corresponding to the word length of the branch target instruction field 142. The pre-fetch timings other than the instruction n are not shown in Fig. 6 . The instruction execution unit 13 executes the branch instruction (instruction c ) at clock t4 to determine an actual branch target address. It is compared, at clock t5 by the branch target comparison unit 16, with the branch target address outputted from the branch prediction unit 15, to thereby verify the false/ true of the branch prediction. The vertification results show that the prediction was true so that the data processing further continues. The branch target instruction (instruction m ) is executed at clock t5. With the conventional data processor, it is necessary, however, that the instruction decoding unit 12 first decodes the branch instruction and then the instruction execution unit 13 determines the address of an instruction to be executed next the branch instruction. The execution clock count for the branch instruction does not become zero even if the prediction by the branch prediction unit 15 is correct. Further, if the branch instruction is an unconditional branch instruction, the branch is necessarily taken and the verification of the prediction is not needed. However, since the same arrangement is applied also to the unconditional branch instruction, the execution clock count for the unconditional branch instruction does not become zero. Furthermore, with the conventional data processor, a compare instruction is executed by the instruction execution unit 13 so that the execution clock count for a compare instruction, which is present in advance of a branch instruction at high possibility, does not become zero even if the prediction by the branch prediction unit 15 is correct, but takes a predetermined number larger than or equal to one. Another branch prediction scheme is known from MICROPROCESSING AND MICROPROGRAMMING. vol. 24, no. 1-5, August 1988, AMSTERDAM NL pages 573 - 580; J. CORTADELLA AND T. JOVE: 'Designing a branch target buffer for executing branches with zero time cost in a RISC processor'. It discloses a data processor comprising: an instruction execution unit for executing a first instruction; an instruction decoding unit for decoding a second instruction following said first instruction while said instruction execution unit executes said first instruction; an instruction pre-fetch unit for pre-fetching a third instruction following said second instruction while said instruction decoding unit decodes said second instruction; a history storage unit (46) for storing, if a fifth one of the instructions immediately succeeding to a fourth instruction is a conditional branch instruction which may branch to a seventh instruction in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is taken, a pre-fetched instruction code of said seventh instruction, a condition code for judging the conditional branch of said fifth instruction and an address of said fourth instruction; and a branch prediction unit for searching, while said instruction decoding unit decodes said fourth instruction, said history storage unit by using the address of said fourth instruction, and if this address is being stored in said history storage unit, outputting the instruction code of said seventh instruction to said instruction decoding unit. According to the present invention there is provided a data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; and an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; and further comprising: a history storage unit for (i) storing, if a fifth one of the instructions immediately succeeding to a fourth one of the instructions is a conditional branch instruction which may branch to a seventh one of the instructions in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is not taken, a pre-fetched instruction code of a sixth one of the instructions which is immediately succeeding to said fifth instruction, an address used for pre-fetching an instruction succeeding to said sixth instruction, a condition code for judging the conditional branch of said fifth instruction and an address of said fourth instruction when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions and (ii) storing, if said fifth instruction is a conditional branch instruction which may branch to said seventh instruction in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is taken, a pre-fetched instruction code of said seventh instruction, an address for pre-fetching an instruction succeeding to said seventh instruction, a condition code for judging the conditional branch of said fifth instruction and an address of said fourth instruction when said fifth instruction is executed at least in a first cycle of the cyclic executions of said instructions; a branch prediction unit for searching, while said instruction decoding unit decodes said fourth instruction, said history storage unit for its contents by using the address of said fourth instruction under decoding and for (i) outputting, when the address of said fourth instruction is stored in said history storage unit, the instruction code of said sixth or seventh instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said sixth or seventh instruction to said instruction pre-fetch unit so that said instruction execution unit executes said sixth or seventh instruction after execution of said fourth instruction and (ii) causing, when the address of said fourth instruction is not stored in said history storage unit, said instruction execution unit to execute said fifth instruction after execution of said fourth instructions; and a branch verification unit for verifying, while said instruction execution unit executes said sixth or seventh instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction in accordance with the condition code stored in said history storage unit and causing, when an instruction now executed is not an instruction to be executed, said instruction execution unit to cancel an execution result of said sixth or seventh instruction and execute said seventh or sixth instruction respectively after execution of said fourth instruction. The invention will be described now by way of example only, with particular reference to the accompanying drawings. In the drawings: Fig. 1 shows the arrangement of a data processor according to an embodiment of this invention, capable of making zero the execution clock count for a conditional branch instruction; Fig. 2 shows the structure of the history storage unit 4b of the data processor of the embodiment of Fig. 1; Fig. 3 is a timing chart illustrating the operation of the embodiment; Fig. 4 shows the arrangement of a conventional data processor executing a branch instruction at high speed; Fig. 5 shows the structure of the history storage unit of the conventional data processor shown in Fig. 4; and Fig. 6 is a timing chart illustrating the operation of the conventional data processor shown in Fig. 4. Fig. 1 shows the arrangement of a data processor according to an embodiment of this invention, capable of making zero the execution clock count for a conditional branch instruction. In Fig. 1, reference numeral 1 designates an instruction pre-fetch unit for pre-fetching an instruction code; 2 an instruction decoding unit for decoding an instruction code pre-fetched by the instruction pre-fetch unit; 3 an instruction execution unit for executing an instruction in accordance with the control information obtained from the instruction decoding unit 2; 7 an input-output bus for connection to a memory, an I/O device and the like; and 8 a bus control unit for controlling the input-output bus 7 under arbitration among data input-output requests from the instruction pre-fetch unit 1 and the instruction execution unit 3. In Fig. 1 reference numeral 4b designates a history storage unit for storing an instruction code and its address of an instruction to be executed next the conditional branch instruction, the address of another instruction executable next the conditional branch instruction, a condition code of the conditional branch instruction, and the information on whether the conditional branch is taken or not taken, respectively when the conditional branch instructions is executed; 5b a branch prediction unit for obtaining from the history storage unit 4b the instruction code and its address of an instruction predicted to be executed next the conditional branch instruction and outputting them to the instruction decoding unit 2 and instruction pre-fetch unit 1, respectively, prior to the execution of the conditional branch instruction; and 6b a branch verification unit for verifying the false/true of the branch prediction in accordance with the condition code of the branch instruction and the information on whether the branch prediction indicates a taken branch or not, respectively received from the branch prediction unit 5b, and in accordance with the information on the status of flags received from the instruction execution unit 3. Fig. 2 shows the format of the history storage unit 4b shown in Fig. 1, wherein reference numeral 401b designates an address tag field for storing the address of an instruction executed immediately before a branch instruction; 402b a candidate instruction field; 403b a candidate address field; and 404b a secondary candidate address field. When the branch of the branch instruction is taken, the fields 402b, 403b and 404b store the instruction code of a predetermined word length located at the branch target address of the branch instruction, the branch target address, and the address of an instruction following the branch instruction, respectively. When the branch of the branch instruction is not taken, the fields 402b, 403b and 404b store the instruction code of a predetermined word length located at the address of the instruction following the branch instruction, the address of the instruction following the branch instruction, and the branch target address of the branch instruction. Reference numeral 407b designates a condition code field for storing a condition code which judges whether the branch of a branch instruction is taken; 408b a taken prediction field which indicates that the branch of a branch instruction is taken; and 409b a valid bit indicating that the data in the corresponding entry are valid. The operation of the data processor of the embodiment constructed as above will be described hereinunder. When an instruction pre-fetched by the instruction pre-fetch unit 1 is decoded by the instruction decoding unit 2, at the same time the branch prediction unit 5b searches the history storage unit 4b in accordance with the address of the instruction under decoding. Even if the instruction under decoding at the instruction decoding unit 2 is an instruction immediately before a branch instruction, the address tag field 401b of the history storage unit 4b is not hit on condition that the instruction is executed for the first time or that upon execution thereof another instruction causes the entry of the history storage unit 4b to be replaced. If the address tag field 401b is not hit, the data processing is further continued, and the instruction is decoded by the instruction decoding unit 2 and thereafter executed by the instruction execution unit 3. First, the description will be given for the case where a branch instruction is executed without hitting the address tag field 401b, and the branch is taken. When a branch instruction is executed by the instruction execution unit 3, this unit 3 calculates the branch target address and judges if the branch is taken or not. If the branch is taken, the instruction pre-fetch unit 1 receives the branch target address calculated by the instruction execution unit 3 to thereby pre-fetched a new branch target instruction code. In this case, the history storage unit 4b stores in the address tag field 401b the address of an instruction which was executed immediately before the branch instruction and is held in the instruction execution unit 3, in the candidate instruction field 402b the branch target instruction code pre-fetched by the instruction pre-fetch unit 1, in the candidate address field 403b the branch target address calculated by the instruction execution unit 3, in the secondary candidate address field 404b the address, held in the instruction decoding unit 2, of an instruction following the branch instruction, and in the condition code field 407b the condition code of the branch instruction held in the instruction execution unit 3, respectively in the same entry. The taken prediction field 408b is set to "1" indicating that the branch is taken, and the valid bit 409b is set to "1" indicating that the data in the entry are valid. Next, the description will be given for the case where the same branch instruction is executed after the above-described operation. In this case there is an ample possibility of a taken branch so that the following operation is carried out. The instruction decoding unit 2 decodes an instruction immediately before the branch instruction, and at the same time the branch prediction unit 5b searches the history storage unit 4b by using the address of the instruction under decoding. In this case, the address hits the address tag field 401b, and without waiting for the execution of the branch instruction the branch prediction unit 5b predicts a taken branch on the basis of past history, obtains the branch target instruction code and its address respectively from the candidate instruction field 402b and candidate address field 403b, and sends them to the instruction decoding unit 2 and instruction pre-fetch unit 1, respectively. The instruction decoding unit 2 starts decoding the branch target instruction code received from the branch prediction unit 5b immediately after the end of decoding the instruction immediately before the branch instruction. The instruction pre-fetch unit 1 cancels the pre-fetched instruction and pre-fetches an instruction at the address advanced from the branch target address received from the branch prediction unit 5b by the amount corresponding to the word length of the candidate instruction unit 402b. In parallel with the instruction execution unit 3 executing the instruction predicted to be executed next the branch instruction, the branch verification unit 6b verifies the false/true of the branch prediction, in accordance with the condition code of the branch instruction stored in the condition code field 407b and the information on the taken prediction field 408b indicating a taken branch, respectively received from the branch prediction unit 5b, and in accordance with the information on the status of the flags received from the instruction execution unit 3. If this verification indicates that the prediction is true, the processing continues in a usual manner. On the other hand if the verification indicates that the prediction is false, in response to a signal from the branch verification unit 6b, the instruction execution unit 3 cancels the execution results of the instruction predicted to be executed next the branch instruction, the instruction decoding unit 2 cancels the decoding results of the instruction under decoding, and the instruction pre-fetch unit 1 cancels the pre-fetched instruction and receives from the branch prediction unit 5b the address of the instruction following the branch instruction stored in the secondary candidate address field 404b to pre-fetch a new instruction in accordance with the received address. In this case, there is an ample possibility of a not-taken branch if the same branch instruction is again executed. For this reason, the history storage unit 4b replaces the entry whose address tag field 401b was hit, in the following manner. Namely, the candidate instruction field 402b stores the instruction code of the instruction following the branch instruction pre-fetched by the instruction pre-fetch unit 1, the candidate address field 403b stores the contents (the address of the instruction following the branch instruction) previously stored in the secondary candidate address field 404b, the secondary candidate address field 404b stores the contents (the branch target address of the branch instruction) previously stored in the candidate address field 403b, and the taken prediction field 408b is reset to "0" indicating that the branch is not taken. Fig. 3 is a timing chart illustrating the operation of the data processor when the branch prediction is true. Instructions processed in the instruction pre-fetch unit 1, branch prediction unit 5b, instruction decoding unit 2, and branch verification unit 6b are illustrated in units of clock. It is assumed herein that the clock count necessary for each unit is one clock. When the branch prediction unit 5b searches at clock t2 the history storage unit 4b in accordance with the address of an instruction (instruction b ) immediately before a branch instruction, the address hits the address tag field 401b so that the branch prediction unit 5b sends the branch target instruction code and its address respectively to the instruction decoding unit 2 and instruction pre-fetch unit 1. At clock t3 the instruction decoding unit 2 starts decoding a branch target instruction code (instruction m), and the instruction pre-fetch unit 1 pre-fetches an instruction (instruction n ) in accordance with the address advanced from the branch target address by the amount corresponding to the word length of the candidate instruction field 402b. The pre-fetch timings other than the instruction n are not shown in Fig. 3. At clock t4, in parallel with the instruction execution unit 3 executing the instruction (instruction m) predicted to be executed next the branch instruction, the branch verification unit 6b verifies the false/true of the branch prediction. The verification result indicates that the prediction is true, so that the processing further conditions. As described above, when the prediction of taken branch is true,the branch target instruction (instruction m ) is executed immediately after the execution of the instruction (instruction b) immediately before the branch instruction, thereby making zero the execution clock count for the branch instruction (instruction c ). Next, the description will be given for the case where a branch instruction is executed without hitting the address tag field 401b, and the branch is not taken. If the branch is not taken, when a branch instruction is executed by the instruction execution unit 3, the history storage unit 4b stores in the address tag field 401b the address of an instruction which was executed immediately before the branch instruction and is held in the instruction execution unit 3, in the candidate instruction field 402b the instruction code of the instruction following the branch instruction pre-fetched by the instruction pre-fetch unit 1, in the candidate address field 403b the address of the instruction following the branch instruction held in the instruction decoding unit 2, in the secondary candidate address field 404b the branch target address of the branch instruction calculated by the instruction execution unit 3, and in the condition code field 407b the condition code of the branch instruction held in the instruction execution unit 3, respectively in the same entry. The taken prediction field 408b is reset to "0" indicating that the branch is not taken, and the valid bit 409b is set to "1" indicating that the data in the entry are valid. Next, the description will be given for the case where the same branch instruction is executed after the above-described operation. In this case there is an ample possibility of a not-taken branch so that the following operation is carried out. The instruction decoding unit 2 decodes an instruction immediately before the branch instruction, and at the same time the branch prediction unit 5b searches the history storage unit 4b by using the address of the instruction under decoding. In this case, the address hits the address tag field 401b, and without waiting for the execution of the branch instruction the branch prediction unit 5b predicts a not-taken branch on the basis of past history, obtains the instruction code of the instruction following the branch instruction and its address respectively from the candidate instruction field 402b and candidate address field 403b, and sends them to the instruction decoding unit 2 and instruction pre-fetch unit 1, respectively. The instruction decoding unit 2 starts decoding the instruction code received from the branch prediction unit 5b immediately after the end of decoding the instruction immediately before the branch instruction. The instruction pre-fetch unit 1 cancels the pre-fetched instruction and pre-fetches an instruction at the address advanced from the address received from the branch prediction unit 5b by the amount corresponding to the word length of the candidate instruction unit 402b. In parallel with the instruction execution unit 3 executing the instruction predicted to be executed next the branch instruction, the branch verification unit 6b verifies the false/true of the branch prediction, in accordance with the condition code of the branch instruction stored in the condition code field 407b and the information on the taken prediction field 408b indicating a not-taken branch, respectively received from the branch prediction unit 5b, and in accordance with the information on the status of the flags received from the instruction execution unit 3. If this verification indicates that the prediction is true, the processing continues in a usual manner. On the other hand if the verification indicates that the prediction is false, in response to a signal from the branch verification unit 6b, the instruction execution unit 3 cancels the execution results of the instruction predicted to be executed next the branch instruction, the instruction decoding unit 2 cancels the decoding results of the instruction under decoding, and the instruction pre-fetch unit 1 cancels the pre-fetched instruction and receives from the branch prediction unit 5b the branch target address stored in the secondary candidate address field 404b to pre-fetch a new instruction in accordance with the received address. In this case, there is an ample possibility of a taken branch if the same branch instruction is again executed. For this reason, the history storage unit 4b replaces the entry whose address tag field 401b was hit, in the following manner. Namely, the candidate instruction field 402b stores the instruction code of the branch target instruction pre-fetched by the instruction pre-fetch unit 1, the candidate address field 403b stores the contents (the branch target address of the branch instruction) previously stored in the secondary candidate address field 404b, the secondary candidate address field 404b stores the contents (the address of the instruction following the branch instruction) previously stored in the candidate address field 403b, and the taken prediction field 408b is set to "1" indicating that the branch is taken. As described above, also in the case where the prediction of a not-taken branch is true, the instruction following the branch instruction is executed immediately after the execution of the instruction immediately before the branch instruction, thereby making zero the execution clock count for the branch instruction. As seen from the foregoing description of this embodiment, while an instruction immediately before the branch instruction is decoded, the branch prediction unit 5b searches the history storage unit 4b by using the address of the instruction under decoding, and obtains the instruction code and its address of an instruction to be executed next the branch instruction. Without decoding and executing the branch instruction, the instruction predicted to be executed next the branch instruction is decoded and executed after the instruction immediately before the branch instruction. In parallel with the execution of the instruction predicted to be executed next the branch instruction, the branch verification unit 6b verifies the false/true of the prediction, thereby making zero the execution clock count for the conditional branch instruction with the true prediction, irrespective of either a taken or not-taken branch. Further, in this embodiment, the branch target address or the address of the instruction following the branch instruction is stored in the candidate address field 403b. When the address of the instruction under decoding by the instruction decoding unit 2 hits the address tag field 401b, the instruction pre-fetch unit 1 starts pre-fetching an instruction at an address advanced from the address obtained from the branch prediction unit 5b by the amount corresponding to the word length of the candidate instruction field 402b. Instead, the candidate address field 403b may store beforehand an address obtained by adding a number corresponding in amount to the word length of the candidate instruction field 402b to the branch target address or the address of the instruction following the branch instruction, so that the instruction pre-fetch unit 1 may be made to start pre-fetching an instruction in accordance with the address obtained from the branch prediction unit 5b, when the address under decoding by the instruction decoding unit 2 hits the address tag field 401b. Further, in this embodiment, when the address of an instruction under decoding by the instruction decoding unit 2 hits the address tag field 401b and a taken branch is predicted, the instruction pre-fetch unit 1 cancels the pre-fetched instruction and starts pre-fetching a new branch target instruction. Instead, the first pre-fetched instruction may not be canceled but stored, so that when the prediction becomes false and the branch is not taken, the stored instruction is read out and sent to the instruction decoding unit 2. Still further, in this embodiment, the history storage unit 4b and branch prediction unit 5b predict the branch of the branch instruction on the basis of the history of the singular latest execution of its branch instruction. Instead, the branch may be predicted on the basis of the history of the plural latest execution of its branch instructions. Further, in this embodiment, if the branch prediction is judged as false, the contents of the candidate address field 403b are replaced with the contents of the secondary candidate address field 404b. Instead, the branch target address may be stored always in the candidate address field 403b, and the address of the instruction following the branch instruction in the secondary candidate address field 404b, so that when the address under decoding by the instruction decoding unit 2 hits the address tag field 401b, the contents of the candidate address field 403b are sent to the instruction pre-fetch unit 1 if the taken prediction field 408b is "1", and the contents of the secondary address field 404b if "0".

Claims: A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit (3) for executing a first one of the instructions; an instruction decoding unit (2) for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; and an instruction pre-fetch unit (1) for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; and further comprising: a history storage unit (4b) for (i) storing, if a fifth one of the instructions immediately succeeding to a fourth one of the instructions is a conditional branch instruction which may branch to a seventh one of the instruction in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is not taken, a pre-fetched instruction code of a sixth one of the instructions which is immediately succeeding to said fifth instruction, an address used for pre-fetching an instruction succeeding to said sixth instruction, a condition code for judging the conditional branch of said fifth instruction and an address of said fourth instruction when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions and (ii) storing, if said fifth instruction is a conditional branch instruction which may branch to said seventh instruction in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is taken, a pre-fetched instruction code of said seventh instruction, an address for pre-fetching an instruction succeeding to said seventh instruction, a condition code for judging the conditional branch of said fifth instruction and an address of said fourth instruction when said fifth instruction is executed at least in a first cycle of the cyclic executions of said instructions; a branch prediction unit (5b) for searching, while said instruction decoding unit decodes said fourth instruction, said history storage unit for its contents by using the address of said fourth instruction under decoding and for (i) outputting, when the address of said fourth instruction is stored in said history storage unit, the instruction code of said sixth or seventh instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said sixth or seventh instruction to said instruction pre-fetch unit so that said instruction execution unit executes said sixth or seventh instruction after execution of said fourth instruction and (ii) causing, when the address of said fourth instruction is not stored in said history storage unit, said instruction execution unit to execute said fifth instruction after execution of said fourth instructions; and a branch verification unit (6b) for verifying, while said instruction execution unit executes said sixth or seventh instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction in accordance with the condition code stored in said history storage unit and causing, when an instruction now executed is not an instruction to be executed, said instruction execution unit to cancel an execution result of said sixth or seventh instruction and execute said seventh or sixth instruction respectively after execution of said fourth instruction.

Inventors: DEGUCHI MASASHI, MATSUZAKI TOSHIMICHI, MIYAZAKI MASAYA, NISHIKAWA YUKINOBU, SAKAO TAKASHI, SUZUKI MASATO, DEGUCHI, MASASHI, MATSUZAKI, TOSHIMICHI, MIYAZAKI, MASAYA, NISHIKAWA, YUKINOBU, SAKAO, TAKASHI, SUZUKI, MASATO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1989
Main classification: G06F9
IPC codes: G06F9