Analog to digital converter

Abstract: One of analog input voltages applied to a plurality of analog input terminals (CH1, CH2) is selected by means of analog switches (P₁, N₁, P₂, N₂) connected to the respective analog input terminals (CH1, CH2) and supplied to a common terminal (A). In this case, each of the analog switches (P₁, N₁, P₂, N₂) permits selective supply of the potential of a corresponding one of the plurality of analog input terminals (CH1, CH2) in response to a control signal supplied from a controller (12). The common terminal (A) is connected to the positive input terminal of a comparator (1). The comparator (1) compares the voltage with a digital output value from the controller (12) which is converted into an analog voltage by means of a D/A converter (2). Further, the controller (12) generates a preset control signal ( PR ) in an inhibition period during which supply of a voltage from the plurality of analog input terminals (CH1, CH2) to the common terminal (A) is inhibited. An initial potential setting circuit (11) sets the potential of the common terminal (A) to a voltage level equal to substantially one-half the maximum voltage level of the analog input voltages applied to the plurality of analog input terminals (CH1, CH2).

Description: This invention relates to an analog/digital (A/D) converter, and more particularly to an A/D converter having a plurality of analog channels. Various types of A/D converters having a plurality of analog channels are known. Fig. 1A shows the construction of a successive approximation type A/D converter as an example of the above A/D converter in which the number of analog channels is "2", and Fig. 1B shows the timing chart of control signals used in the A/D converter of Fig. 1A. In Fig. 1A, CH1 and CH2 each denote an analog input terminal. When control signal  AIN1 is set to a high (H) level, selected analog switches P 1 and N 1 are turned on, permitting a potential of analog input terminal CH1 to be supplied to the positive input terminal of comparator 1. Further, when control signal  AIN2 is set to a high (H) level, selected analog switches P 2 and N 2 are turned on, permitting a potential of analog input terminal CH 2 to be supplied to the positive input terminal of comparator 1. A reference potential which is used as a reference for the comparing operation is supplied to negative input terminal of comparator 1 by means of digital/analog (D/A) converter 2. In this case, comparator 1 effects the comparison operation for one bit (or one cycle of comparison operation) by comparing the potential of analog input terminal CH1 or CH2 selected by the control signal with the reference potential. After one-bit comparison operation is completed, the comparison result is supplied to controller 3. Controller 3 causes the output of D/A converter 2 to be changed according to the comparison result or whether the comparison result is positive or negative when the compared potentials are not equal to each other. As a result, the potential of the negative input terminal of comparator 1 is changed and then the next comparison operation is effected. After this, the same operation is repeatedly effected until the compared potentials are determined to be equal to each other. When the compared potentials are set equal to each other, controller 3 supplies a digital value which has been given to D/A converter 2 to output terminal OUT. In this way, the A/D converting operation is effected. Now, assume that the potential of analog input terminal CH1 is subjected to the A/D conversion and then the potential of analog input terminal CH2 is subjected to the A/D conversion. In this case, as shown by the timing chart of Fig. 1B, a blanking period (in which  AIN1 =  AIN2 = low (L) level) is generally provided between signals  AIN1 and  AIN2 . The reason why such a blanking period is provided is that a D.C. current path must be prevented from being created between analog input terminals CH1 and CH 2 by simultaneously turning on analog switches P 1 and N 1 and analog switches P 2 and N 2 when signals  AIN1 and  AIN2 are switched from one to the other. In practice, as shown in Fig. 1A, RC filters 4 1 and 4 2 are generally connected to analog input terminals CH1 and CH2 in order to stabilize the analog input (or suppress noise). Assume now that the potential of analog input terminal CH1 is completed and analog switches P 1 and N 1 are turned off. In this case, parasitic capacitor C 1 (C 2 in Fig. 1A is also a parasitic capacitor) associated with the common terminal (point A) which is the positive input terminal of comparator 1 of Fig. 1A is charged to potential V AIN1 of analog input terminal CH1. Immediately after analog switches P 2 and N 2 are turned on at timing  AIN2 , initial value V A0 of the potential of the common terminal (point A) can be determined by the capacitive division (charge sharing) of capacitors C 1 and C EX2 if the impedance of each of analog switches P 2 and N 2 is sufficiently smaller than that of resistor R 2 . That is, the following equation can be obtained: V A0 = V AIN1 + C EX2 C EX2 + C 1 (V AIN2 - V AIN1 ) When the potential of capacitor C EX2 is changed by the charge sharing, charges are supplied from analog input terminal CH2 to capacitor C EX2 , thereby preventing the potential variation. However, in practice, the potential of the common terminal (point A) cannot be restored to the level of potential V AIN2 of analog input terminal CH2 before the A/D converting operation is completed, particularly, in a case where the time constant of RC filters 4 1 and 4 2 is large. In this case, the result of the A/D conversion may contain an error. The error may become larger as the potential difference between potentials V AIN1 and A IN2 becomes larger and the capacitance of capacitor C 1 becomes larger with respect to that of capacitor C EX2 . Basically, it is impossible to eliminate the influence by the charge sharing and therefore it becomes important to suppress the potential variation. That is, the influence by the charge sharing can be observed in the form of on-channel input current and therefore it is important to suppress the on-channel input current to a minimum and attain the highly precise A/D conversion. The features of the preamble of claim 1 are known from JP-A-58 084 342. An object of this invention is to provide an A/D converter in which the analog input potential in a comparator can be prevented from being deviated from the potential of a selected analog channel by the charge sharing when the analog input channel is switched, that is, the on-channel input current of the analog input channel can be suppressed to a minimum. According to this invention, there is provided an A/D converter as set out in claim 1. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1A is a circuit diagram of the conventional A/D converter; Fig. 1B is a timing chart of control signals used in the A/D converter of Fig. 1A; Fig. 2A is a circuit diagram of an A/D converter according to a first embodiment of this invention; Fig. 2B is a timing chart of control signals used in the A/D converter of Fig. 2A; Fig. 3 is a circuit diagram of an A/D converter according to a second embodiment of this invention; Fig. 4 is a circuit diagram of an A/D converter according to a third embodiment of this invention; and Fig. 5 is a circuit diagram of an A/D converter according to a fourth embodiment of this invention. The will now be described first to forth embodiments of this invention with reference to Figs. 2A to 5. First, the first embodiment of this invention is explained with reference to Figs. 2A and 2B which correspond to Figs. 1A and 1B showing the conventional A/D converter. That is, the A/D converter is a successive approximation type A/D converter of two input channels and includes two analog input terminals CH1 and CH2 as shown in Fig. 2A. Analog potential V AIN1 is applied to analog input terminal CH1 via RC filter 4 1 constituted by resistor R 1 and capacitor C EX1 . Likewise, analog potential V AIN2 is applied to analog input terminal CH2 via RC filter 4 2 constituted by resistor R 2 and capacitor C EX2 . Analog input terminal CH1 is connected to the positive input terminal of comparator 1 via analog switches P 1 and N 1 which are turned on or off by first control signal  AIN1 from controller 12. Likewise, analog input terminal CH2 is connected to the positive input terminal of comparator 1 via analog switches P 2 and N 2 which are turned on or off by second control signal  AIN2 from controller 12. As shown in Fig. 2B, a blanking period (in which  AIN1 =  AIN2 = "L" level) is set between first and second control signals  AIN1 and  AIN2 in order to prevent a D.C. current path from being formed between analog input terminals CH1 and CH2 by simultaneously turning on switches P 1 and N 1 and switches P 2 and N 2 when signals  AIN1 and  AIN2 are switched from one to the other. Therefore, when first control signal  AIN1 is set to "H" level, selected analog switches P 1 and N 1 are turned on, permitting the potential of analog input terminal CH1 to be supplied to the positive input terminal of comparator 1. Likewise, when second control signal  AIN2 is set to "H" level, selected analog switches P 2 and N 2 are turned on, permitting the potential of analog input terminal CH2 to be supplied to the positive input terminal of comparator 1. A reference potential serving as a comparison reference and generated from D/A converter 2 for D/A converting a digital value output from controller 12 is supplied to the negative input terminal of comparator 1. Comparator 1 effects one-bit comparison operation (or one cycle of comparing operation) by comparing the potential of analog input switch CH1 or CH2 selected by first and second control signals  AIN1 and  AIN2 with the reference potential. After the one-bit comparison operation is completed, the comparison result is supplied to controller 12. Controller 12 changes the output potential of D/A converter 2 according to the comparison result or whether it is positive or negative when the compared potentials are not equal to each other. As a result, the potential of the negative input terminal of comparator 1 is changed and then the next bit comparison operation is effected. After this, the same operation is repeatedly effected until the compared potentials are determined to be equal to each other. When the compared potentials are determined to be equal to each other, controller 12 outputs a digital value which has been given to D/A converter 2 to output terminal OUT. In this way, the A/D conversion is effected. The positive input terminal of comparator 1, or common terminal (point A) in Fig. 2A, is connected to initial potential setting circuit 11. Initial potential setting circuit 11 includes two N-channel transistors N 11 and N 12 serially connected between power source V DD and the ground terminal. A connection node between transistors N 11 and N 12 is connected to the common terminal (point A). The gates of transistors N 11 and N 12 are supplied with third control signal  PR as shown in Fig. 2B from controller 12. That is, initial potential setting circuit 11 creates an initial potential of an intermediate potential level between power source potential V DD and the ground potential which is determined by the resistance ratio of N-channel transistors N 11 and N 12 which are both turned on during the blanking period in the case of switching the analog input signals or while third control signal  PR between the high-level periods of first and second control signals  AIN1 and  AIN2 is kept at "H" level. The initial potential is also set as initial potential V INITIAL of the common terminal (point A). That is, in the case of Fig. 2A, initial potential V INITIAL of the common terminal (point A) can be expressed as follows: V INITIAL = V DD × R N1 R N1 + R N2 where R N1 denotes the ON-resistance of N-channel transistor N 11 and R N2 denotes the ON-resistance of N-channel transistor N 12 . As is clearly understood from equation (2), initial potential V INITIAL of the common terminal (point A) can be set to (1/2) V DD by selectively setting the ON-resistances of N-channel transistors N 11 and N 12 equal to each other. In the conventional A/D converter shown in Fig. 1A, when analog input terminal CH2 is selected instead of analog input terminal CH1, or when the analog input potential is switched from V AIN1 to V AIN2 , positive input potential V A0 of comparator 1 can be expressed by equation (1) as follows: V A0 = V AIN1 + C EX2 C EX2 + C 1 (V AIN2 - V AIN1 ) Therefore, when the analog input potential is switched from V AIN1 = 0 V to V AIN2 = 5 V, positive input potential V A0 of comparator 1 can be expressed as follows: V A0 = 0 + C EX2 C EX2 + C 1 (5 - 0) = C EX2 C EX2 + C 1 × 5 In contrast, in this embodiment, desired initial potential V INITIAL can be set by means of initial potential setting circuit 11. That is, when the analog input potential is switched from V AIN1 to V AIN2 , initial potential V INITIAL which is determined by means of initial potential setting circuit 11 is set instead of input potential input potential V AIN1 . Therefore, if initial potential V INITIAL which is determined by means of initial potential setting circuit 11 is set to 2.5 V, for example, positive input potential V A0 of comparator 1 can be expressed as follows: V A0 = 2.5 + C EX2 C EX2 + C 1 (5 - 2.5) = 2.5 + C EX2 C EX2 + C 1 × 2.5 Assuming that capacitance C 1 =1 PF and capacitance C EX2 =100 PF, equation (3) can be rewritten as follows: V A0 = 100/(100 + 1) × 5 = 4.95 V and equation (4) can be rewritten as follows: V A0 = 2.5 + 100/(100 + 1) × 2.5 = 4.98 V As is clearly understood from the above, the analog input potential to comparator 1 in the conventional A/D converter is varied by 50 mV (5 V - 4.95 V = 0.05 V) by the charge sharing. In contrast, in the A/D converter of this embodiment, variation in the analog input potential can be suppressed to 20 mV (5 V - 4.98 V = 0.02 V). In other words, since a potential difference of 5 V which is the analog input potential range for the A/D conversion may occur between input potentials V AIN1 and V AIN2 in the conventional A/D converter, a maximum potential difference caused by the charge sharing will be as much as 5 V. In contrast, since the input potential is initially set to an intermediate potential, for example, 2.5 V during the blanking period in the A/D converter of this embodiment, a potential difference caused by the charge sharing may be only 2.5 V at maximum. Therefore, in the A/D converter of this embodiment, variation in the analog input potential of comparator 1 can be suppressed, that is, an error can be suppressed and an ON-channel input current in the analog input channel can be reduced, thereby making it possible to enhance the operation speed. In this case, it is preferable to set initial potential V INITIAL determined by means of initial potential setting circuit 11 to one-half the voltage which is equal to the analog input potential range for the A/D conversion. That is, it is preferable to set the initial potential to a potential level equal to one-half the rated input voltage. Fig. 3 is a circuit diagram of an A/D converter according to the second embodiment of this invention. The A/D converter of this embodiment includes initial potential setting circuit 13 constituted by P-channel transistors P 11 and P 12 instead of initial potential setting circuit 11 of the A/D converter shown in Fig. 2A. That is, initial potential setting circuit 13 includes two P-channel transistors P 11 and P 12 connected between power source V DD and the ground terminal. A connection node between two transistors P 11 and P 12 is connected to the common terminal (point A). Initial potential setting circuit 13 further includes inverter 14. Third control signal  PR supplied from controller 12 and shown in Fig. 2B is inverted by inverter 14 and supplied as control signal  PR to the gates of transistors P 11 and P 12 . That is, in initial potential setting circuit 13, when third control signal  PR in the blanking period at the switching time of analog input signals is set at "H" level or when control signal  PR is set at "L" level, P-channel transistors P 11 and P 12 are both turned on to create an initial potential equal to a desired intermediate potential which lies between power source potential V DD and the ground potential and which is determined by the resistance ratio of transistors P 11 and P 12 . The initial potential is used as initial potential V INITIAL of the common terminal (point A). Since initial potential V INITIAL of the common terminal (point A) can be freely set to a desired value by means of initial potential setting circuit 13, the same effect as is obtained in the first embodiment can be attained by setting initial potential V INITIAL to 2.5 V, or one-half of 5 V which is the analog input potential range for the A/D conversion. Fig. 4 is a circuit diagram of an A/D converter according to the third embodiment of this invention. The A/D converter of this embodiment includes initial potential setting circuit 15. Initial potential setting circuit 15 is constituted by N-channel transistor N 21 and P-channel transistor P 21 serially connected between power source V DD and the common terminal (point A). The gate of transistor P 21 is also connected to the common terminal (point A). Further, the gate of transistor N 21 is supplied with third control signal  PR shown in Fig. 2B from controller 12. That is, in initial potential setting circuit 15, the potential of point A (parasitic capacitance C 1 ) is initially set to a desired intermediate potential level between power source potential V DD and the ground potential when third control signal PR in the blanking period at the switching time of analog input signals is set at "H" level. With initial potential setting circuit 15, initial potential V INITIAL at point A can be expressed as follows: V INITIAL = V DD - (V thn21 + ΔV thn21 ) - V thp21 where V thn21 and V thp21 respectively denote threshold voltages of transistors N 21 and P 21 , and ΔV thn21 denotes an amount of variation in threshold voltage V th due to the back-gate bias effect. For example, in initial potential setting circuit 15, initial potential V INITIAL can be set approx. to (1/2)V DD as indicated by the following equation: V INITIAL = 5 V - (0.8 V + 1 V) - 0.8 V = 2.4 V As described above, with initial potential setting circuit 15, initial potential V INITIAL of the comnon terminal (point A) can be set to a desired value, and therefore the same effect as that obtained in the first embodiment can be obtained by setting initial potential V INITIAL to 2.4 V, or approximately one-half of 5 V which is the analog input potential range for the A/D conversion. Fig. 6 is a circuit diagram of an A/D converter according to the fourth embodiment of this invention. The A/D converter of this embodiment includes initial potential setting circuit 16 which is constituted by analog switches N 31 and P 31 connected between D/A converter 2 and point A. The analog switches are supplied with third control signal  PR as shown in Fig. 2B and control signal  PR obtained by inverting control signal  PR by means of inverter 17. That is, in initial potential setting circuit 16, when third control signal  PR in the blanking period at the time of switching the analog input signals is set at "H" level, analog switches N 31 and P 31 are both turned on, permitting the output potential of D/A converter 2 to be supplied to the common terminal (point A). Since the output potential of D/A converter 2 can be set to a desired value according to a digital value supplied from controller 12, potential V INITIAL of the common terminal (point A) can also be set to a desired value. With initial potential setting circuit 16, since initial potential V INITIAL of the common terminal (point A) can be set to a desired value, the same effect as that obtained in the first embodiment can be obtained by setting initial potential V INITIAL to 2.5 V, or one-half of 5 V which is the analog input potential range for the A/D conversion. It is possible to form various types of initial potential setting circuits with other constructions. Further, the first to third control signals may be generated in a software or hardware fashion instead of using the above controller. It should be understood that this invention is not limited to the 2-input channel successive approximation type A/D converter shown in the above embodiments. This invention can be applied if a plurality of input channels are used. Further, this invention can be applied to a flash A/D converter or another type of A/D converter which uses a plurality of comparators for comparing an input signal with the respective reference potentials instead of using the D/A converter and controller to generate the reference potential. As described above, according to the A/D converter of this invention, a positive input to the comparator (or the parasitic capacitance of the input terminal thereof) is previously set to an initial potential level in the blanking period of the control signal at the time of switching the analog input signals so as to suppress variation in the potential due to the charge sharing. Recently, the precision and operation speed of the A/D converter becomes higher and therefore influence of the charge sharing on the conversion precision cannot be neglected. However, according to this invention, influence of the charge sharing can be effectively reduced only by additionally using a simple initial potential setting circuit and the like without necessitating a complicated timing control.

Claims: An analog to digital (A/D) converter comprising: a plurality of analog input terminals (CH1, CH2) to which analog input voltages are respectively applied; switching means (P 1 , N 1 , P 2 , N 2 ) for selectively supplying the voltage level of the analog input voltages applied to said plurality of analog input terminals (CH1, CH2) to a common terminal (A); control means (12) for controlling selection of said plurality of analog input terminals (CH1, CH2) by said switching means (P 1 , N 1 , P 2 , N 2 ), said control means (12) changing the selecting operation in an inhibition period during which supply of the voltage level from said plurality of analog input terminal (CH1, CH2) to said common terminal (A) is inhibited; comparing means (1) for comparing the voltage of said common terminal (A) with a reference voltage; and initial potential setting means (11; 13; 15; 16) for setting the potential of said common terminal (A) to a desired potential level in the inhibition period, characterized in that said initial potential setting means (11; 13; 15; 16) sets as the desired potential level a potential level equal to substantially intermediate level of the maximum voltage level (V DD ) and the minimum voltage level (0V) of the plurality of analog input terminals (CH1, CH2). The A/D converter according to claim 1, characterized in that said control means (12) includes control signal generating means for generating a control signal ( PR ) indicating the inhibition period; and said initial potential setting means (11; 13; 15; 16) sets the potential of said common terminal (A) to a desired potential level according to the control signal ( PR ). The A/D converter according to claim 2, characterized in that said initial potential setting means (11) includes first and second N-channel transistors (N 11 , N 12 ) serially connected between a power source (VDD) set at a preset potential and a ground terminal, the gates of said first and second N-channel transistors (N 11 , N 12 ) being connected to said control signal generating means to receive the control signal ( PR ) and a connection node between said first and second N-channel transistors (N 11 , N 12 ), being connected to said common terminal (A). The A/D converter according to claim 2, characterized in that said initial potential setting means (13) includes first and second P-channel transistors (P 11 , P 12 ) serially connected between a power source (V DD ) set at a preset potential and a ground terminal and an inverter (14) connected to the gates of said first and second P-channel transistors (P 11 , P 12 ); a connection node between said first and second P-channel transistors (P 11 , P 12 ) is connected to said common terminal (A); and said inverter (14) is connected to said control signal generating means to receive the control signal ( PR ) and supply an inverted signal (  PR ) of the control signal ( PR ) to the gates of said first and second P-channel transistors (P 11 , P 12 ). The A/D converter according to claim 2, characterized in that said initial potential setting means (15) includes an N-channel transistor (N 21 ) and a P-channel transistor (P 21 ) serially connected between a power source (V DD ) set at a preset potential and said common terminal (A), the gate of said N-channel transistor (N 21 ) being connected to said control signal generating means to receive the'control signal ( PR ) and the gate of said P-channel transistor (P 21 ) being connected to said common terminal (A). The AID converter according to claim 2, characterized by further comprising: digital value generating means (12) for generating a digital value corresponding to the comparison result of said comparator means (1); and a digital/analog (D/A) converter for converting the digital value generated from said digital value generating means (12) into an analog voltage and supplying the converted analog signal to said comparator means (1) as the reference voltage; and characterized in that said initial potential setting means (16) includes an N-channel transistor (N 31 ) constituting an analog switch and a P-channel transistor (P 31 ) constituting an analog switch which are connected in parallel between said D/A converter (2) and said common terminal (A) and an inverter (17) connected to the gate of said P-channel transistor (P 31 ); and the gate of said N-channel transistor (N 31 ) is connected to said control signal generating means to receive the control signal ( PR ), the gate of said P-channel transistor (P 31 ), is connected to said inverter (17) which is connected to said control signal generating means and supplies an inverted signal (  PR ) of the control signal ( PR ).

Inventors: SAITO TOMOTAKA, SAKAI HIDEO, YAMAZAKI AKIHIRO, SAITO, TOMOTAKA, SAKAI, HIDEO, YAMAZAKI, AKIHIRO, SAITO, TOMOTAKA C/O INTELLECTUAL PROPERTY DIV., SAKAI, HIDEO C/O INTELLECTUAL PROPERTY DIV., YAMAZAKI, AKIHIRO C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H03M1
IPC codes: H03M1