Semiconductor device comprising a logic circuit and a memory

Abstract: A semiconductor device comprises a logic circuit (132) and a memory (12) including a timing signal generator circuit, both formed on a substrate (11), and a wiring connecting the logic circuit (132) to the memory (12), in which a diffusion layer-fixed potential zone (15) to which a predetermined potential is applied is formed under an area of the wiring which is situated between the logic circuit (132) and the memory (12) whereby it is possible to alleviate an effect from minority carriers and a substrate potential variation.

Description: The present invention relates to a semiconductor device comprising a substrate, a memory device formed in the substrate, a gate array formed in the substrate, and wiring connecting the memory device to the gate array. Conventionally, a device is known which includes a logic circuit and small-capacity RAM (Random Access Memory) formed in a common substrate. In order to meet a growing demand for a memory capacity, a greater-capacity RAM is formed in the common substrate. Furthermore, as the logic circuit, use has been made of a gate array which can freely be formed by the user. In a conventional device shown in Fig. 7, large-capacity RAM4, made up of memory cell 2, timing signal generator circuit and so on, and gate array 5 (logic circuit) are formed on substrate 1. Gate array 5 is connected by metal wiring 6 to large-capacity RAM4 to provide a RAM-to-gate array interface. If the gate array and large-capacity RAM are formed in a common substrate, there is a risk that an operation error will occur due to the interference of noise. That is, the gate array cannot, of necessity, be prepared against minority carriers and a variation in a substrate potential because the user cannot know in detail how a circuit is configured for the gate array. Furthermore, in the gate array, there is a possibility that unused gates will be left unconnected in which case the gate is electrically "floated". The unused gate is turned ON or OFF due to the occurrence of "couplings" and it may be adequately predicted that noise comes from the unused gates. The occurrence of such a noise whose level may be somewhat disregarded in an often statically-operated gate array circuit poses a greater problem in an often dynamically-operated memory circuit. If a memory is used as a dynamic memory in particular, minority carriers encounter the dropping of charges and a noise at the time of refreshing will cause a write-in error. Furthermore, a variation in substrate potential will cause a variation in threshold level and hence mistiming will occur at a timing signal generator circuit, causing a readout error or write-in error. If, as set out above, a memory and gate array are built in a common substrate, a serious situation will arise from a variation in minority carriers and in substrate potential. US-A-4701884 discloses a semiconductor device which comprises a substrate, a memory device formed in the substrate and including a timing signal generator, and a gate array formed in the substrate. The memory device is connected to the gate array via two level layer interconnections. In the surface of a p-type layer, an N-well and an N+ diffusion layer are provided. The N+ diffusion layers are biased to a positive voltage for preventing minority carriers rushing into the memory array to cause loss of stored data. It is an object of the present invention to provide a semiconductor device in which a diffusion layer-fixed potential zone is formed under an area of a wiring between a logic circuit and a memory including a timing signal generator circuit, both formed in a substrate, and is connected to receive a predetermine potential, whereby it is possible to alleviate an effect from minority carriers and substrate potential variation. According to the invention, there is provided a semiconductor device comprising: a substrate; a memory device formed in said substrate, said memory device including a timing signal generator circuit; a gate array formed in said substrate; a first wiring formed on an insulating layer on said substrate, said first wiring connecting said gate array to said memory device; a P+ type diffusion layer well formed in said substrate below said first wiring between said gate array and said memory device; an N+ type diffusion layer well formed in said substrate below said first wiring between said gate array and said memory device; a P++ type diffusion layer fixed potential zone having a voltage Vss applied thereto by a second wiring connected to power source terminals, and formed in the P+ type diffusion layer well, said voltage Vss fixing said P++ type diffusion layer fixed potential zone at a first potential; and an N++ type diffusion layer fixed potential zone having a voltage V CC applied thereto by the second wiring connected to power source terminals and formed in said N+ type diffusion layer well, said second voltage fixing said N++ type diffusion layer fixed potential zone at the second potential. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention; Fig. 2 is a cross-sectional view showing one form of a diffusion layer-fixed potential zone in the semiconductor device of Fig. 1; Fig. 3 is a cross-sectional view showing another form of a diffusion layer-fixed potential zone of the semiconductor device of the present invention; Fig. 4 is a plan view showing a semiconductor device according to a second embodiment of the present invention; Fig. 5 is a plan view showing a semiconductor device according to a third embodiment of the present invention; Fig. 6 is a plan view showing a fourth embodiment of the present invention; and Fig. 7 is a plan view showing a conventional semiconductor device. Semiconductor devices of the present invention will be explained below with reference to the accompanying drawings. Fig. 1 shows a semiconductor device according to one embodiment of the present invention. Memory 12, such as a large-capacity DRAM, and gate array 13, such as a logic circuit, are built in substrate 11, noting that memory 12 is formed of a memory peripheral circuit including a memory cell for a DRAM (Dynamic Random Access Memory) and a timing signal generator circuit for supplying various timing signals to the DRAM cell. Gate array 13 is connected to memory 12 by metal wiring 14 to provide a memory-to-gate array interface. Metal wiring 14 is constituted of a few tens of wires for, for example, an address signal and I/O signal. In view of the readiness with which a connection can freely be made at gate array 13, wiring 14 extends substantially horizontal to gate array 13, occupying a considerable area. A plurality of diffusion layer-fixed potential zone 15 are formed below wiring 14 which is situated between gate array 13 and memory 12. A portion of diffusion layer-fixed potential zone 15 is so formed as to surround memory 12 including the timing signal generator circuit. For diffusion layer-fixed potential zone 15 use can be made of one or a plurality of N type, diffusion layer-fixed potential zones and of P-type, diffusion layer-fixed potential zones, in which case it is possible to obtain more effective result. Furthermore, if the memory is surrounded with diffusion layer-fixed potential zone 15, it is possible to alleviate an effect from minority carriers migrated around the memory and from a variation in substrate potential. A CMOS (Complementary Metal Oxide Semiconductor) is sometimes manufactured in P- and N-type, diffusion layer well formation processes. As shown in Fig. 2, N + type, diffusion layer well 16 and P + type, diffusion layer 17 are formed in substrate 11, and N ++ type, diffusion layer-fixed potential zone 15 and P ++ type, diffusion layer-fixed potential zone 15 are formed in N + type, diffusion layer well 16 and P + type, diffusion well 17, respectively. As shown in Fig. 3, as wiring 14 use is made of a plurality of layers formed over substrate 11 with respective insulating layer 18 formed therebetween. In the case where memory 12 and gate array 13 are to be formed in common substrate 11, there is a risk that an operation error, such as a readout error and write-in error, will occur due to a pronounced adverse effect from minority carriers and from a variation in substrate potential. With a voltage Vcc applied to diffusion layer-fixed potential zone 15 in N + type, diffusion layer well 16 and a voltage Vss applied to diffusion layer-fixed potential zone 15 in P + type, diffusion layer well 17, the well is so defined as to have a configuration partway as show in Fig. 2. Although a well potential variation is readily transmitted in a well of the same low resistance type, if different diffusion layer-fixed potential zone 15 is provided in the well as shown in Fig. 2, a variation in well potential is suppressed, alleviating an effect from the minority carriers and from a variation in substrate potential. Diffusion layer-fixed potential zones 15 are connected to corresponding power source terminals Vcc and Vss by means of a different wiring than that for memory 12 and gate array 13. By so doing, there is less variation in potential and hence a greater absorption effect against minority carriers and substrate potential variation. Diffusion layer-fixed potential zones 15 may be connected to the corresponding power source terminals by means of the same wiring as that for memory 12 and gate array 13. Although wiring 14 constituting an interface of memory 12 and gate array 13 requires a broader area, if diffusion layer-fixed potential zone 15 is formed in that portion of substrate situated under the wiring, wiring can be formed without increasing any chip area. In this case, a greater effect can be obtained at diffusion layer-fixed zone 15 if the wires (wiring) are increased in number. Although, in the first embodiment, gate array 13 has been explained as being employed as the logic circuit, a whole area element type gate array 131 may be employed as gate array 13 as shown in Fig. 4. Use may also be made of logic circuit 132 including a gate array as shown in Fig. 5 or semicustom IC 133 may be used as logic circuit 132 as shown in Fig. 6. According to the present invention, as set out above, the diffusion layer-fixed potential zone is provided under the wiring area between the logic circuit and the memory including a timing signal generator circuit, thereby alleviating an effect from minority carriers across the memory and the logic circuit and from a substrate potential variation.

Claims: A semiconductor device comprising: a substrate (11); a memory device (12) formed in said substrate (11), said memory device including a timing signal generator circuit; a gate array (13) formed in said substrate; a first wiring (14) formed on an insulating layer on said substrate (11), said first wiring connecting said gate array (13) to said memory device (12); a P+ type diffusion layer well (17) formed in said substrate (11) below said first wiring (14) between said gate array (13) and said memory device (12); an N+ type diffusion- layer well (16) formed in said substrate (11) below said first wiring (14) between said gate array (13) and said memory device (12); a P++ type diffusion layer fixed potential zone (15) having a voltage Vss applied thereto by a second wiring connected to power source terminals, and formed in the P+ type diffusion layer well (17), said voltage Vss fixing said P++ type diffusion layer fixed potential zone at a first potential; and an N++ type diffusion layer fixed potential zone (15) having a voltage V CC applied thereto by the second wiring connected to power source terminals and formed in said N+ type diffusion layer well (16), said second voltage fixing said N++ type diffusion layer fixed potential zone at the second potential. A semiconductor device according to claim 1 in which said P++ type and N++ type diffusion layer fixed potential zones (15) surround said memory device (12). A semiconductor device according to claim 1 or 2 wherein said second wiring is separate from said first wiring (14). A semiconductor device according to any preceding claim in which said first wiring (14) extends between said memory device (12) and said gate array (13) in a parallel relation to the gate array (13). A semiconductor device according to any preceding claim in which said memory (12) comprises dynamic random access memory. A semiconductor device according to any preceding claim wherein said first wiring includes a first layer and a second layer of wirings, and a first insulator layer (18) disposed between said first layer and said second layer of wirings.

Inventors: SAKURAI TAKAYASU, SAWADA KAZUHIRO, SHIROTORI TSUKASA, SAKURAI, TAKAYASU, SAWADA, KAZUHIRO, SHIROTORI, TSUKASA, SAKURAI, TAKAYASU C/O PATENT DIVISION, SAWADA, KAZUHIRO C/O PATENT DIVISION, SHIROTORI, TSUKASA C/O PATENT DIVISION
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1989
Main classification: H01L27
IPC codes: H01L21, H01L27, G11C11, H01L23