DIGITAL TO ANALOGUE CONVERTER

Abstract: An n bit DAC of the kind having at least 2<n>-1 sources, typically current sources, especially for use in oversampling ADCs to enable a resolution accuracy in excess of 18 bits, wherein at least 2<n>-1 sources are switchable by at least 2<n>-1 switches responsively to inputs on at least 2<n>-1 digital input lines, and a source selection circuit, typically an at least 2<n>-1 to 2<n>-1 multiplexer, is connected between the digital input lines and the switches and is adapted to select the sources in a dynamic manner, based on a predetermined algorithm which converts DAC errors into noise and puts the noise energy into unwanted parts of the spectrum.

Description: Title: Digital to Analogue Converter Field of invention This invention relates to a digital to analogue converter (DAC) and in particular to an n bit DAC of the kind having at least 2 -1 sources, where the sources may be current, charge or voltage sources, most typically current sources . The DAC of the invention is intended more especially but not exclusively for use in oversampling analogue to digital converters (ADC's). Background to the invention A DAC is a device that will output an analogue parameter, usually a voltage, current, or charge, that is representation of a digital input to it. Thus an 8 bit digital word can have one of 256 values, so an 8 bit DAC will output a voltage or current which can have one of 256 different values. Since the analogue values which can be output are limited in number, any particular analogue value produced is accurate only within upper and lower limits. Thus, digitally, each one of the 256 different values is precisely defined, whereas the analogue output can only have a defined degree of accuracy associated with it. There is not absolute agreement on the precise definition of accuracy, but an 8 bit, ' 8 bit accuracy DAC will output analogue voltage or currents which are ' +/- 0.5 lsbs accurate. Multibit high accuracy oversampling ACDs require DACs which have relatively few bits (say 4 ^ -to 8) and are very accurate (say +/- 0.01 lsbs). Another way of describing the accuracy required is that a DAC of n bits with m bit accuracy is needed, where m >> n. Such DACs are very difficult to construct and 16 bits for m is the currently available limit, although in theory 18 bits or more would be required. There exist many ways of constructing DACs. For example, DACs may incorporate current sources, where the current sources have different values. One conventional technique is, for an 8 bit DAC, to use 8 current sources which are each a factor of 2 larger than the next one. One digital input control line is then connected to each current source. Another technique, feasible with the advent of VLSI, for the same 8 bit DAC, is to use 255 equal current sources, where the msb digital control line switches on 128 sources, the next switches 6-4, the next 32, and so on, as diagrammatically indicated in Figure 1. It is to be noted that an n bit DAC needs at least 2 -1 current sources. Various combinations of these two approaches have also been used, such as 16 equal current sources, followed by another 4 sources which are each half the magnitude of the preceding one, for an 8 bit DAC. Oversampling ADCs put a low accuracy ADC with an accurate DAC in a feedback loop, and sample the signal many (eg 128) times faster than the required rate. The effect of the feedback loop is to correlate up quantising noise from the ADC in such a way that the noise spectrum is shaped, and is very low in the required part of the spectrum. A digital filter on the output of the ADC then filters out all signals (including noise) from the unwanted parts of the spectrum, and then decimates the output data rate, frequency shifting it if necessary. The wanted part of the spectrum is usually, but not always, the low frequency part (eg the first 1/128th) of the spectrum. The invention According to the invention, an n bit DAC of the kind described, having at least 2 -1 sources switched by at least 2 n -1 switches responsively to inputs on at least 2 - 1 digital input lines, includes a source selection circuit, connected between the digital input lines and the source switches, which is adapted to select the sources in a dynamic manner, based on a preselected algorithm. The closest prior art approach to this technique is to select the sources randomly. The present invention shows substantial advantages over both selection in an absolutely fixed manner and random selection. For further understanding, when the invention is applied to a A bit DAC, for example, one conversion may require the digital word "3" to be converted, and current sources 2, 5, 8 are chosen, whilst on the next conversion, to convert "3" sources 11, 16, 4 are chosen, etc. The selection algorithm is desirably chosen first of all to convert DAC errors into noise, and secondly and most importantly to put all (or most) of that noise energy in the unwanted parts of the spectrum. The mechanism by which it does this is different from the way a basic oversampling ADC works and is entirely dependent on the algori hm. Brief description of drawings ^ The DAC in accordance with the invention is exemplified with reference to the accompanying drawings, in which: Figure 1 shows a conventional DAC; Figure 2A is a block diagram for illustrating the invention; Figure 2B diagrammatically illustrates one embodiment of DAC in accordance with the invention; and Figure 3 is a diagram showing the noise spectrum of a DAC in accordance with the invention. Description of Embodiment Referring to Figure 2, an n-bit DAC in accordance with the invention has 2 current sources (one more than is absolutely necessary). A digital input requiring s1 current sources to be turned on selects the first si. The next conversion requires s2 current sources, and selects s2, starting from sl+1. If this requires sources beyond 2s, counting starts again from the beginning, and the final source used is designated q(L). The next conversion requires s3 sources, and selects s3 using q(L+1) as the first. The process continues ad infinitum. The block diagram of Figure 2A illustrates the basic system. In Figure 23, showing a low hardware implementation of the invention, reference 10 denotes the n digital inputs. A decoder operating in accordance with the algorithm is referenced 12, and is associated with an n-loop feedback circuit 14 for shaping the . Reference 16 denotes the switchable current sources and reference 18 designates the output. A sample clock input to the decoder is referenced 20. Figure 3 shows the noise spectrum of the DAC in accordance with the invention, and is labelled in self-explanatory manner. The algorithm producing the noise spectrum of Figure 3 can reduce the accuracy requirements for the current sources by at least a factor of 30 in an oversampling ADC using a 3 bit DAC, and oversampling by at least 16 times. It makes feasible multibit oversamplers with a resolution substantially in excess of 18 bits.

Claims: CLAIMS 1. An n bit DAC of the kind having at least 2 -1 current, charge or voltage sources switched by at least 2 n -l switches responsively to inputs of at least 2 -1 digital input lines, including a source selection circuit, connected between the digital input lines and the source switches, which is adapted to select the sources in a dynamic manner, based on a preselected algorithm. 2. An n bit DAC according to claim 1, wherein the selection algorithm is chosen first to convert DAC errors into noise and secondly to put substantially all of the noise energy in unwanted parts of the spectrum. 3. An n-bit DAC according to claim 1 = or claim 2 , having 2 current sources, wherein a digital input requiring si current sources to be turned on selects the first si, the next conversion requiring s2 current sources selects s2, starting from sl+1, and if this requires sources beyond 2s, counting starts again from the beginning, whilst if the final source used is designated 1(L), the next conversion requiring s3 sources selects s3 using q(L+l) as the first, and the process continues ad infinitum. 4. An n-bit DAC according to claim 1 or claim 2 or claim 3, wherein the source selection circuit comprises an at least 2 -1 to 2 -1 multiplexer having algorithm processing, stepped by a clocked input. 5. An n-bit OAC according to claim 1 or claim 2 or claim 3, wherein the source selection circuit comprises a decoder operating in accordance with the algorithm responsively to a clocked input, and an n-loop feedback circuit connected to the decoder and for shaping the quantising noise. 6. An n-bit DAC having a noise spectrum generally in accordance with the dashed-line characteristic shown in Figure 3 of the accompanying drawings. 7. An n-bit DAC substantially as shown in Figure 2A or Figure 2B of the accompanying drawings.

Inventors: STOREY MICHAEL JOHN, STOREY, MICHAEL, JOHN
Applicants: DATA CONVERSION SYSTEMS LTD
Application year: 1989
Main classification: H03M1
IPC codes: H03M1