VOLTAGE CONTROLLED OSCILLATOR

Abstract: A voltage controlled oscillator (VCO) comprises the series arrangement of two signal inverters (I₁, I₂) whose outputs (B, A) are coupled to the input of the first signal inverter (I₁) through a feedback loop (FBL) having a resistor (R₁) and a capacitor (C₁) connected to the outputs (B, A) of the inverters (I₁, I₂). The VCO further includes a simple control circuit (SC) with a second resistor (R₂) which is connected to the junction (C) of the first resistor (R₁) and the capacitor (C₁), and to a series arrangement of two diodes (D₁, D₂) arranged in the same direction, whose interconnected electrodes are connected to the second resistor (R₂) and coupled to the input of the first inverter (I₁). The other electrodes of the diodes (D₁, D₂) form inputs for two control voltages (+U, -U) varying symmetrically with respect to the mean value of the capacitor voltage, with which the frequency of the VCO can be varied over a continuous range. The VCO can be used over a wide range of frequency values and does not require any particular measures for obtaining a practically symmetrical signal shape of the voltage at the output (A) of the second inverter (I₂).

Description: The invention relates to voltage controlled oscillators of the type comprising a series arrangement of a first and a second signal inverter, each signal inverter producing a substantially binary signal with preset voltage levels and the output of the second signal inverter operating as the output of the oscillator, and a feedback loop comprising a resistor whose one end is connected to the output of one of such first and second signal inverters, and a capacitor whose one end is connected to the output of the other of such first and second signal inverters and whose remaining interconnected ends are connected to the input of the first signal inverter through a coupling circuit. Voltage controlled oscillators (VCO's) of this type can be used as independent voltage frequency converters, but are especially used as parts of control systems such as phase-locked loops (PLL's). A VCO of the type mentioned hereinbefore is known from the United States Patent 4,146,849. In this known VCO the feedback loop comprises a third signal inverter for coupling the junction of the capacitor and the resistor, which are connected to the output of the first and the second signal inverter, respectively, to the input of the first signal inverter. The three signal inverters are designed in complementary MOS technology (CMOS), the second CMOS signal inverter being arranged between complementary MOS field effect transistors (CMOS FET's) which are connected to the respective supply voltages and function as resistors whose values can be modified with the aid of two oppositely varying control voltages at their gate electrodes. Thus, the output resistance of the second CMOS signal inverter can be modified externally and hence the frequency of the signal generated by the VCO. At a given value of the control voltages, however, the oscillation frequency still depends rather strongly on the properties of the CMOS FET's and, more specifically, on the so-called "pinch-off voltage", the threshold of the gate voltage at which a FET just begins to be conductive. For a FET having the same channel type as well as for the FET's having a complementary channel type, this "pinch-off voltage" shows a relatively large variation, whilst the deviations with respect to the nominal value can be ± 0.8 Volt in practice and thus the accidental value of the difference may rise to 1.6 Volts. In addition, with this VCO the charging and discharging of the capacitor in each oscillation period takes place via the output resistor of the second CMOS signal inverter which is determined during the charging operation by the resistance of the FET of the one channel type and during the discharging operation by the resistance of the FET of the other channel type. For obtaining the practically desired symmetrical signal shape of the oscillator signal (that is to say, a signal having a duty factor of 50%) additional provisions are required for this VCO in order to neutralize accidental inequalities in the charging and discharging resistors. In an article entitled "send/receive indent" appearing on page 7-79 of the publication ELEKTOR, vol. 11, No. 123-124, published July-August 1985, there is disclosed an oscillator comprising first and second signal inverters N2 and N3, connected in that order in series, and a feedback loop comprising a capacitor C4 having one end connected to the output of N3 and the other end connected through resistors R4 and R3 to, respectively, an input of N3 and an input of N2. A transmit-receive key PTT is also coupled to such input to N2 and has associated therewith circuitry causing the oscillator to emit signals of slightly different frequency when the key is pressed and when it has just been released. The invention has for its object to provide a voltage controlled oscillator of the type mentioned in the preamble which is suitable for use in a wide range of frequency values and has an easily implementable control circuit, the active elements of the signal inverters in this oscillator having substantially no effect on the control of the oscillation frequency by the control voltages and no particular provisions being required for obtaining a practically symmetrical signal shape of the oscillator signal. The voltage controlled oscillator according to the invention is characterised in that a part of the coupling circuit is a control circuit for varying the frequency of the oscillator over a continuous range in accordance with a continuously variable control voltage, which control circuit comprises a second resistor whose one end is connected to the interconnected ends of the first resistor and the capacitor, and a series arrangement of two equally directed diodes, whose interconnected electrodes are connected to the other end of the second resistor and whose remaining electrodes form the respective control inputs for two oppositely varying control voltages having a symmetrical position with respect to the mean value of the voltage in the interconnected ends of the first resistor and the capacitor, the interconnected electrodes of the diodes being coupled to the input of the first signal inverter. By implementing the measures according to the invention it is achieved that both the charging and the discharging of the capacitor is effected via the first resistor (thus with a first time constant) when the capacitor voltage is situated in the range between the two control voltages, and that both the charging and the discharging of the capacitor is effected via the first and via the second resistor (thus with a second, smaller time constant) when the capacitor voltage is situated outside the range between the two control voltages. While maintaining a symmetrical signal shape the frequency of the oscillator signal can be varied by varying the two control voltages symmetrically with respect to the mean values of the capacitor voltage, so that the width of the voltage range for the charging and discharging of the capacitor according to the first, larger time constant is increased or reduced symmetrically and hence also the duration of an oscillation period is varied accordingly. The signal inverters used in practice generally have such a low output impedance that their active elements have substantially no effect on the control of the oscillation frequency by the control voltages. The latter also holds for the two diodes of the control circuit, since the characteristics of two diodes of the second type generally show few differences and these differences can practically be disregarded for two diodes from one and the same wafer. The signal inverters used in the present VCO can be realized in a known manner as hard-limiting inverting amplifiers, the voltage levels of the binary output voltage being determined by the two supply voltages of the amplifier. These signal inverters can also be realized as inverting logic gates. An embodiment of the VCO according to the invention which is attractive for use in a phase-locked loop (PLL), is characterized in that each of the signal inverters is arranged as an EXOR gate having two inputs, a direct voltage representing a logic value "1" being constantly present at the one input and the other input constituting the signal input proper. The use of a VCO applied thus enables to implement the PLL as a whole by utilizing four EXOR gates, a pair of diodes and further only resistors and capacitors. The phase detector of this PLL is arranged as an EXOR gate having two inputs, a binary reference signal voltage being present at the one input and the binary output voltage of the VCO at the other input, and a binary error voltage which is representative of a phase difference between the binary reference signal voltage and the binary VCO output voltage occurring at the output of this EXOR gate. In this PLL the binary error voltage is logically inverted with the aid of a signal inverter which again is arranged as an EXOR gate having two inputs, a direct voltage representing a logic value "1" being permanently present at the one input and the error voltage to be inverted being present at the other input. The error voltage and the logically inverted error voltage are applied to identically arranged RC low-pass filters for producing the respective control voltages for the VCO. With this use of the PLL only a single specimen of a current type of integrated circuit which is known by the name of "Quad EXOR Gate" and comprises four EXOR gates will suffice. Such "Quad EXOR Gates" are available as standard components in the known circuit techniques, including the ECL technique which is suitable for use in the frequency range of the order of 100 MHz. The invention and its advantages will now be further explained in the following description of embodiments with reference to the drawings, in which: Fig. 1 shows a circuit diagram of a fixed frequency oscillator forming the basis for a first embodiment of a VCO according to the invention; Fig. 2 shows three time diagrams to explain the operation of the oscillator in Fig. 1; Fig. 3 shows a circuit diagram of the first embodiment of a VCO according to the invention; Fig. 4 shows several time diagrams to explain the operation of the VCO in Fig. 3; Fig. 5 shows a circuit diagram of a PLL in which is included a VCO according to Fig. 3; Fig. 6 shows in greater detail a circuit diagram of a PLL in which is included a second embodiment of the VCO according to the invention; and Fig. 7 shows a circuit diagram of a third embodiment of the VCO according to the invention using a slightly different basic oscillator from that according to Fig. 1. The fixed frequency basic oscillator shown in Fig. 1 comprises a series arrangement of two signal inverters I₁ and I₂, the output A of the second signal inverter I₂ also constituting the output of the oscillator. This oscillator further comprises a positive feedback loop FBL with a resistor R₁ and a capacitor C₁ which are connected to the output B of the first signal inverter I₁ and the output A of the second signal inverter I₂, respectively, the junction C of the capacitor C₁ and the resistor R₁ being directly connected to the input of the first signal inverter I₁. The inverters I₁ and I₂ are arranged as hard-limiting inverting amplifiers, in which the voltage levels of the binary output voltage are provided by the positive supply voltage +E and the equally large negative supply voltage -E, and in which the threshold voltage at the input has the mean value of these supply voltages and thus has the value 0. The operation of the basic oscillator is illustrated with the aid of the time diagrams of Fig. 2 for the substantially ideal case of signal inverters having a very high input impedance, a very high gain and a very low output impedance. Fig. 2A shows the binary voltage at output A of the second signal inverter I₂ for voltage levels -E and +E. Fig. 2B shows the binary voltage at output B of the first inverter I₁ for voltage levels -E and +E. Fig. 2C shows in a stylized form the variation of the voltage in the junction C whose mean value is equal to the mean value 0 of the voltage at output B of the first inverter I₁. At the instant t = t₁ , at which the voltage in junction A jumps from the value -E to the value +E and that in junction B from the value +E to the value -E, the voltage in junction C jumps from the mean value 0 to the value +2E, so that the voltage difference between the junctions C and B has the value +3E. After the instant t = t₁ the capacitor C₁ is discharged through the resistor R₁ with a time constant τ₁ = R₁C₁ . This discharging is continued until at an instant t = t₁ + T/2 the voltage in junction C reaches the value 0 forming the threshold voltage for inverter I₁, resulting in the voltage at the output B of inverter I₁ jumping from the value -E to the value +E at this instant. Consequently, also at this instant, the voltage in junction A moves from the value +E to the value -E. This voltage jump of -2E in junction A is conveyed unchanged to junction C so that the voltage difference between the junctions C and B now has the value -3E. After the instant t - t₁ + T/2 the capacitor C₁ is charged through resistor R₁ again with the time constant τ₁ = R₁C₁ . The charging and the discharging of the capacitor C₁ is thus effected with the same time constant. At instant t = t₁ + T the voltage in junction C has again reached the value 0 and the voltage at output B of inverter I₁ will jump from the value +E to the value -E at instant t = t₁ + T , after which the process of discharging and charging described hereinbefore will be repeated with the period T. Since the charging and discharging of capacitor C₁ is effected symmetrically, the period T of the oscillator voltage can be simply determined with the aid of Fig. 2C by choosing for t₁ the reference instant t₁ = 0. At instant t = 0 there is across resistor R₁ a voltage of +3E which decreases exponentially according to exp[-t/τ₁] until, after a half oscillation period, there is a voltage with a value +E across resistor R₁ at instant t = T/2 , so that the following holds: 3E exp[-T/(2τ₁)] = E from which it follows that the oscillation period T is provided by the relationship: T = (2τ₁)ln3 = (2R₁C₁)ln3. From this formula it appears that the frequency f = 1/T of the output voltage of the oscillator in Fig. 1 can be changed by changing the value of resistor R₁ or that of capacitor C₁. A voltage controlled oscillator (VCO) having a frequency f = 1/T which is varied over a continuous range, can thus be obtained by providing the oscillator of Fig. 1 with a control circuit which, for example, varies the value of resistor R₁ according to a continuously variable control voltage. The invention now provides a VCO whose frequency f = 1/T can be varied over a continuous range without utilizing continuously variable resistors or capacitors. A first embodiment of the VCO according to the invention which is based on the oscillator in Fig. 1, is represented in Fig. 3. In Fig. 1 and Fig. 3 the corresponding elements are denoted by the same references. According to the invention the VCO in Fig. 3 comprises a control circuit SC which couples the junction C of capacitor C₁ and resistor R₁ to the input of the first signal inverter I₁. This control circuit SC comprises a second resistor R₂ connected on one end to the junction C, and further includes the series arrangement of two diodes D₁ and D₂ arranged in the same direction, whose interconnected electrodes are connected to the other end of resistor R₂ and also to the input of the first signal inverter I₁. The two remaining electrodes of these diodes D₁, D₂ form respective control inputs for two control voltages varying in opposite directions with the values +U and -U which are symmetrical with respect to the average value 0 of the capacitor voltage at junction C and the value 0 of the threshold voltage of the first signal inverter I₁. The operation of the VCO according to Fig. 3 will now be explained with reference to the time diagrams of Fig. 4. This explanation is based on a number of suppositions forming a realistic approach to the practical situation. For example, it is again assumed that the inverters I₁ and I₂ are substantially ideal inverters having a very high input impedance, a very high gain and a very low output impedance. It is also assumed that the diodes D₁ and D₂ have substantially ideal diode characteristics with a negligible forward voltage and a negligible reverse current. It is further assumed that the control voltages +U and -U are supplied by substantially ideal voltage sources having an extremely low internal impedance. The binary voltages at the outputs A and B of the two inverters I₂ and I₁ again have the shape which is represented in the respective time diagrams of Fig. 2A and Fig. 2B. The voltage in the junction C of resistor R₁ and capacitor C₁ again has a mean value equal to the mean value 0 of the voltage in junction B, but has a shape different from the one represented in the time diagram of Fig. 2C in the case of Fig. 1. This different shape of the voltage in junction C of the VCO according to Fig. 3 is represented in Fig. 4 in a scaled-up manner for two different magnitudes of the two control voltages +U and -U, in which Figure stylization is again used for clarity. In the time diagram of Fig. 4A the two control voltages have a magnitude E so that it holds that +U = +E and -U = -E. At the instant t = t₁ , at which the voltage in junction A jumps from the value -E to the value +E and in junction B from the value +E to the value -E (compare Fig. 2A and Fig. 2B), the voltage in junction C of Fig. 3 jumps from the mean value 0 to the value +2E, so that the voltage difference between the junctions C and B then has the value +3E. Since the voltage in junction C at the instant t = t₁ has a value +2E which exceeds the voltage at the control input of diode D₁ having a value of +U = +E, diode D₁ will be conductive. On the other hand, diode D₂ will not be conductive because the voltage at its control input with a value of -U = -E is lower than the value +2E of the voltage in junction C. After the instant t = t₁ capacitor C₁ will be discharged via resistor R₁ as well as via resistor R₂ and the time constant τ₂ of this discharge is given by: τ₂ = R₁R₂C₁/(R₁+R₂). This time constant τ₂ thus has a smaller value than the time constant τ₁ = R₁C₁ . The discharging of capacitor C₁ with the time constant τ₂ is continued till the instant t = t₂ , at which the voltage is equal to the control voltage +U = +E of diode D₁ and diode D₁ is no longer conductive. After this instant t = t₂ the two diodes D₁ and D₂ are non-conductive, so that capacitor C₁ can then be further discharged only through resistor R₁ with a time constant τ₁ = R₁C₁ . This discharging is continued till the instant t = t₁ + T/2 , at which the voltage in junction C reaches the value 0 of the threshold voltage of inverter I₁, resulting in the voltage in junction B jumping from the value -E to the value +E and that in junction A from the value +E to the value -E. The latter voltage jump of -2E in junction A is conveyed unchanged to junction C, so that the voltage in junction C jumps from the mean value 0 to the value -2E and the voltage difference between the junctions C and B then has the value -3E. Since just after the instant t = t₁ + T/2 the voltage in junction C has a value -2E, which is lower than the control voltage -U = -E of diode D₂, diode D₂ will be conductive, whereas diode D₁ remains non-conductive because the voltage +U = +E at its control input exceeds the voltage in junction C. After the instant t = t₁ + T/2 capacitor C₁ will be charged through resistor R₁ as well as resistor R₂, so that this charging operation is effected again with the time constant τ₂. This charging operation of capacitor C₁ with time constant τ₂ is continued till the instant t = t₃ , at which the voltage in junction C is equal to the control voltage U = -E of diode D₂ and diode D₂ is no longer conductive. After this instant t = t₃ both diodes D₁ and D₂ are non-conductive and capacitor C₁ is charged only through resistor R₁ and thus again with the time constant τ₁ = R₁C₁ till the instant t = t₁ + T , at which the voltage in junction C again reaches the value 0 of the threshold voltage of inverter I₁, resulting in the voltage in junction B jumping from the value +E to the value -E and that in junction A from the value -E to the value +E. The process of the discharging and charging of capacitor C₁ as described for the time interval (t₁, t₁ + T) will repeat itself with a period T after the instant t = t₁ + T . The above has shown that both the charging and the discharging of capacitor C₁ is effected through the fixed resistors R₁ and R₂, that is to say, through resistor R₁ (and thus with the time constant τ₁ = R₁C₁ ) when the voltage in junction C is situated in the range between the control voltages +U and -U (thus for the time intervals (t₂, t₁ + T/2) and (t₃, t₁ + T)), but through both resistors R₁, R₂ (and thus with the time constant τ₂ which is smaller than τ₁) when the voltage in junction C is situated outside the range between the control voltages +U and -U (thus for the time intevals (t₁, t₂) and (t₁ + T/2, t₃). Since these control voltages are situated symmetrically with respect to the mean value 0 of the capacitor voltage and the value 0 of the threshold voltage of the converter I₁, the capacitor voltage in Fig. 4A has a symmetrical signal shape and the same holds for the signal shape of the binary voltage at the output A of the VCO in Fig. 3. Thus, in the VCO according to the invention no particular provisions are required for the in practice desired symmetrical signal shape of the oscillator signal (that is to say, a binary signal with a 50% duty factor). Fig. 4B likewise shows the shape of the capacitor voltage, but in this case the two control voltages have a smaller magnitude than in Fig. 4A, that is, a magnitude of 0.2E so that in Fig. 4B it holds that +U = + 0.2E and -U = - 0.2E. The process of the charging and the discharging of the capacitor C₁ proceeds in the same way as in Fig. 4A, but owing to the smaller value of the control voltages +U and -U in Fig. 4B the duration of the time intervals (t₂, t₁ + T/2) and (t₃, t₁ + T) with the time constant τ₁ is smaller than in Fig. 4A and on the other hand the duration of the time intervals (t₁, t₂) and (t₁ + T/2, t₃) with the smaller time constant τ₂ is greater than in Fig. 4A. The result is that the duration of the oscillation period T in the case of Fig. 4B is smaller than in the case of Fig. 4A. The frequency f = 1/T of the output voltage of the VCO in Fig. 3 can thus be simply varied by varying the two control voltages +U and -U symmetrically with respect to the mean value 0 of the capacitor voltage (thus the value 0 of the threshold voltage of the first signal inverter I₁), whilst maintaining the symmetrical signal shape of the capacitor voltage and thus of the output voltage. On the basis of this symmetry the duration of the oscillation period T as a function of the magnitude U of the control voltages can be derived from the duration of the time intervals (t₁, t₂) and (t₂, t₁ + T/2), which can be determined in a way similar to the one described for the oscillator represented in Fig. 1. This deriving is very simple, but owing to its length it is deemed sufficient in this case to mention the relationship between the period T and the magnitude U of the control voltages: T = 2τ₂ ln [3 + (2-U/E)R₁/R₂] + 2(τ₁-τ₂) ln [1+U/E] in which τ₁ and τ₂ are the aforementioned time constants with: τ₁ = R₁C₁ τ₂ = R₁R₂C₁/(R₁+R₂). From the above relationship as well as the time diagrams of Fig. 4 it appears that the magnitude of the control voltages for controlling the duration of the period T should be situated between the values U = 0 and U = 2E, the range between the values U = 0 and U = E being the most important range in practice. Although the above explanation of the VCO in Fig. 3 has been given for signal inverters I₁, I₂ and diodes D₁, D₂ with supposedly ideal properties, the deviations from these ideal properties which prove to be unavoidable in practice, appear not to have any substantial effect on the frequency and the symmetrical signal shape of the output voltage of the VCO. For example, the technically available signal inverters generally have such a low-value output impedance that the active elements of these inverters do not substantially affect the VCO frequency which is set by the control voltages. This also applies to the diodes of the control circuit, because the differences in the forward voltage of two diodes of the same type are generally little and these differences can practically be disregarded for two diodes from one and the same wafer. The control circuit of the VCO according to the invention which is easy to implement renders this VCO also attractive for use in closed control systems such as phase-locked loops (PLL's). For illustration Fig. 5 shows how the VCO according to Fig. 3 can be included in a simple way in a PLL, corresponding elements in Fig. 3 and Fig. 5 being denoted by the same references. In addition to this VCO the PLL of Fig. 5 includes a phase detector PD which produces an error signal which is representative of the phase difference between a reference signal REF and the binary signal at the output A of the VCO. This error signal is applied to a loop filter LF for obtaining the control voltage +U which is fed to the control input of diode D₁ in the VCO. The control voltage -U for the control input of diode D₂ is derived from the control voltage +U at the output of loop filter LF with the aid of a signal inverter I₃. The signal inverter I₃ in Fig. 5 is arranged in a known manner with the aid of an operational amplifier, whose non-inverting input is coupled to earth and whose output is fed back via a resistor R to its inverting input which is connected to the output of loop filter LF via an equally large resistor R. In the explanation of the VCO in Fig. 3 it was assumed that its control voltages +U and -U originate from substantially ideal voltage sources with a very low internal impedance. As regards the control voltage -U, this condition is satisfied, since signal inverter I₃ in Fig. 5 usually has a very low output impedance. As regards the control voltage +U, this condition is satisfied in a simple way by arranging loop filter LF as an active low-pass filter that also includes an operational amplifier. In the embodiments of the VCO according to the invention described so far, the signal inverters I₁ and I₂ are arranged as hard-limiting inverting amplifiers, the voltage levels being determined by a positive control voltage +E and an equally large negative supply voltage -E and the threshold voltage at the input having the value 0. These signal inverters, however, can also be arranged as inverting logic gates known as NOT-gates. In many currently used logic gates one of the voltage levels of the binary output voltage is determined by the supply voltage (positive or negative), whereas the other voltage level is determined by the earth potential and thus has the value 0. In that case the threshold voltage at the input of the logic gate is equal to half the supply voltage. When a NOT-gate used thus is incorporated as signal inverter I₁, I₂ in the VCO of Fig. 3, the mean value of the capacitor voltage in junction C is also equal to half the supply voltage. For obtaining a symmetrical signal shape of the voltage at output A of the VCO the control voltages for the diodes D₁, D₂ should be symmetrical with respect to this half control voltage. It will be evident that this shift of the control voltages over the half supply voltage does not in any way affect the operation of the VCO as has been explained hereinbefore. Fig. 6 shows a second embodiment of a VCO according to the invention which, as in Fig. 5, forms a part of a PLL and enables an attractive use of the PLL as a whole because of a special choice of the signal inverters I₁, I₂ in the VCO. Corresponding elements in Fig. 3, Fig. 5 and Fig. 6 are denoted by the same references. In Fig. 6 each of the inverters I₁, I₂ of the VCO is arranged as an EXOR gate with two inputs, at the one input a direct voltage being permanently present representing a logic value "1" and the other input constituting the signal input proper. With the EXOR gate shown in Fig. 6 the voltage level of this logic value "1" is formed by a positive supply voltage +2E, the voltage level of the logic value "0" being formed by the earth potential having the value 0. The threshold voltage at the input of the EXOR gate is thus equal to half the supply voltage +E. The permanent supply of the logic value "1" to one of the two inputs of EXOR gates I₁, I₂ is effected in Fig. 6 by connecting the supply voltage +2E to the associated input through the parallel circuit of a resistor R₅ and a decoupling capacitor C₅. The phase detector PD of the PLL in Fig. 6 is now also arranged as an EXOR gate with two inputs, at the one input a substantially binary reference signal REF and at the other input the binary VCO output voltage (the voltage levels of the two signals at the inputs of this EXOR gate have the values +2E and 0). At the output of the EXOR gate PD a binary error voltage occurs which is representative of a phase difference between the binary reference signal voltage REF and the binary VCO output voltage (also the voltage levels at the output of this EXOR gate have the values +2E and 0). This binary error voltage at the output of EXOR gate PD is now logically inverted by means of a signal inverter I₃, which is also arranged as an EXOR gate, whose one input is connected to the supply voltage +2E through the parallel circuit of resistor R₅ and decoupling capacitor C₅ and whose other input receives the error voltage to be inverted. The error voltage at the output of EXOR gate PD and the inverted error voltage at the output of EXOR gate I₃ are now applied to identically arranged passive low-pass filters LF₁ and LF₂, respectively, for producing the respective control voltages (E + U) and (E - U) for the diodes D₁ and D₂ of the VCO. These control voltages are symmetrical with respect to the half supply voltage +E which forms the threshold voltage of EXOR gate I₁. Each of the low-pass filters LF₁, LF₂ in Fig. 6 is formed by a RC-network comprising a series resistance R₃, R₄ between in and output and the capacitor C₃, C₄ between output and earth. In the explanation of the first embodiment of the VCO according to the invention with reference to Fig. 3 it was assumed that the control voltages for the diodes D₁ and D₂ originate from substantially ideal voltage sources having a very low internal impedance. When using the second embodiment of the VCO according to the invention in the PLL of Fig. 6, these control voltages are produced from the error voltage and the inverted error voltage at the output of the EXOR gates PD and I₃ with the aid of passive low-pass filters LF₁ and LF₂ in the form of identically arranged RC-networks. Since the EXOR gates have a very low output resistance in practice, it can be stated that the control voltages (E + U) and (E - U) in Fig. 6 originate from the voltage sources with an internal resistance which is provided in practice by the series resistances R₃, R₄ of the low-pass filters LF₁, LF₂. The effect of the (mutually identical) internal resistances of the two voltage sources on the operation of the VCO in Fig .6 can be simply allowed for by basing the dimensioning on an enhancement of the value of resistor R₂ by the value of the internal resistance of the voltage sources which is provided in practice by the value of the mutually identical resistors R₃ and R₄. For, in the case when diode D₁ is conductive, capacitor C₁ is discharged on the one hand through resistor R₁ and on the other through the series arrangement of the resistors R₂ and R₃. For the case of a conductive diode D₂ it also holds that capacitor C₁ is charged on the one hand through resistor R₁ and discharged on the other through the series arrangement of the resistors R₂ and R₄. Furthermore, the symmetrical signal shape of the output voltage is not affected because the internal resistance of the two control voltage sources in Fig. 6 has one and the same value. In the practical implementation of the VCO in Fig. 6 resistor R₂ is bridged by a capacitor C₂. This capacitor C₂ promotes a fast passing through of the (very small) input voltage range for which EXOR gate I₁ has a large voltage gain and hence avoids when exceeding the threshold voltage of EXOR gate I₁ the occurrence of brief parasitic very high frequency oscillation as a consequence of crosstalk of signals both inside and outside this gate to the input thereof. Without this capacitor C₂ the threshold voltage of EXOR gate I₁ is exceeded too slowly as a result of the relatively large time constant of resistor R₂ and the total effective capacity at the input of EXOR gate I₁ in the range of the large voltage gain. The capacitance of this capacitor C₂ is substantially determined by the type of EXOR gate used, irrespective of the desired oscillation frequency f = 1/T of the VCO. Thus, the special choice of the inverters I₁, I₂ in the second embodiment of the VCO according to the invention enables to incorporate the PLL as a whole with the aid of four EXOR gates, a pair of diodes, five resistors and five capacitors. In addition, the use of four EXOR gates provides the practical advantage that only a single example of a current type of integrated circuit known by the name of "Quad EXOR Gate" will suffice. Such "Quad EXOR Gates" with four EXOR gates are available as standard components in the known circuit techniques, including also the ECL technique which can be implemented for a PLL which is to function in the frequency range around 100 MHz. For the purpose of illustration the details are stated hereinbelow of a practical implementation of a PLL according to Fig. 6 which is arranged for synchronizing the oscillator signal with a 4.096 MHz reference signal: All embodiments of the VCO according to the invention described so far are based on a basic oscillator in its forms shown in Fig. 1 wherein the elements C₁ and R₁ in its feedback loop are coupled to, respectively, the output of the second inverter I₂ and the output of the first inverter I₁. However, the invention is not restricted thereto, but can also be applied in a VCO in which the elements C₁ and R₁ are differently coupled in the feedback loop of the oscillator. For illustration Fig. 7 shows a VCO according to the invention based on an oscillator in which those elements C₁ and R₁ are so differently coupled. Corresponding elements in Fig. 3 and Fig. 7 are denoted by the same references. The VCO according to Fig. 7 differs from that according to Fig. 3 as regards the connection of resistor R₁ and capacitor C₁ to the output of the signal inverters I₁ and I₂, in Fig. 7 resistor R₁ being connected to output A of second inverter I₂ and capacitor C₁ to output B of first inverter I₁. The junction C of resistor R₁ and capacitor C₁ is coupled to the input of the first inverter I₁ through a control circuit SC that comprises an additional signal inverter I₄ between the junction of diodes D₁, D₂ and resistor R₂ and the input of first inverter I₁. This additional inverter I₄ is arranged in the same way as the inverters I₁ and I₂. As can be verified in an easy way with reference to the signal shape of the voltages in the junctions A, B and C of the VCO according to Fig. 7, this additional inverter I₄ is required to meet the condition for oscillation, but there is no further basic difference in operation between the VCO's according to Fig. 3 and Fig. 7. Since the VCO according to Fig. 7 should comprise an additional inverter I₄, a VCO according to Fig. 3 is to be preferred.

Claims: A voltage controlled oscillator, comprising a series arrangement of a first and a second signal inverter (I₁, I₂), each signal inverter producing a substantially binary signal with preset voltage levels and the output of the second signal inverter operating as the output of the oscillator, and a feedback loop comprising a resistor (R₁) whose one end is connected to the output of one of such first and second signal inverters, and a capacitor (C₁) whose one end is connected to the output of the other of such first and second signal inverters and whose remaining interconnected ends are connected to the input of the first signal inverter through a coupling circuit, CHARACTERISED IN THAT a part of the coupling circuit is a control circuit for varying the frequency of the oscillator over a continuous range in accordance with a continuously variable control voltage, which control circuit comprises a second resistor (R₂) whose one end is connected to the interconnected ends of the first resistor (R₁) and the capacitor (C₁), and a series arrangement of two equally directed diodes (D₁, D₂), whose interconnected electrodes are connected to the other end of the second resistor (R₂) and whose remaining electrodes form the respective control inputs for two oppositely varying control voltages having a symmetrical position with respect to the mean value of the voltages in the interconnected ends of the first resistor (R₁) and the capacitor (C₁), the interconnected electrodes of the diodes being coupled to the input of the first signal inverter (I₁). A voltage controlled oscillator as claimed in claim 1, wherein each of the signal inverters is arranged as an EXOR gate having two inputs, a direct voltage representing a logic value "1" being constantly present at the one input and the other input constituting the signal input. A phase-locked loop comprising a signal controlled oscillator, a phase detector (PD) for generating an error signal which is representative of a phase difference between a reference signal and a signal taken from the oscillator, and a loop filter for producing from the error signal a control signal for the signal controlled oscillator, wherein the oscillator is a voltage controlled oscillator as claimed in claim 2, the phase detector is arranged as an EXOR gate with a first input for a substantially binary reference signal voltage and a second input for the substantially binary output voltage of the oscillator, and having an output which is connected to the one control input of the oscillator through a first passive low-pass filter (LF₁) and to the other control input of the oscillator through an EXOR gate (I₃) operating as a logic signal inverter and a subsequent second passive low-pass filter (LF₂) corresponding with the former low-pass filter (LF₁).

Inventors: RUIJS, JAN BEMEDICTUS FRIEDRICK WILHELM
Applicants: AT&T NETWORK SYSTEMS INTERNATIONAL B.V., AT&T NETWORK SYSTEMS NEDERLAND B.V.
Application year: 1989
Main classification: H03K3
IPC codes: H03L7, H03K3