Clock supply circuit

Abstract: Disclosed is a clock supply circuit. The clock supply circuit is composed of a first phase and a second phase. Each buffer (11) provided in each channel (CH) in the second phase has the same drive ability, and the number of flip-flops (F/F) which are dependent on each buffer (11) is the same. When the number of the flip-flops (F/F) is not the same, capacity means (C) is provided in each channel (CH) in order to render the conditions of the second phase uniform.

Description: CLOCK SUPPLY CIRCUIT BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a clock supply circuit as specified in the preamble part of claim 1. Description of the Prior Art A clock supply circuit as specified in the preamble part of claim 1 is known from the publication IEEE Journal of solid-state circuits, Vol. SC-21, No. 2, April 1986, pages 240-246. EP-A-1 181 059 discloses dealing with the clock skew problem in a semiconductor integrated circuit by use of flip-flops. In a clock supply circuit in large-scale integration (LSI), the number of flip-flops (F/Fs) which are connected to clock lines is extremely large, and the length of the lines between these F/Fs is long. Therfore the design of a clock system becomes difficult, and other various problems occur. For example, a delay between two of the F/Fs or an inner clock skew and a time delay while a clock signal supplied from the outside of a chip is inputted into the F/Fs in the chip or an outer clock skew are increased. When the outer clock skew is increased, the performance of LSI is lowered. Accordingly, it is desired to make the outer clock skew as small as possible. While, when the inner clock skew (hereinafter called only clock skew) is increased, a data transfer error occurs between F/Fs which are connected in series and the error causes wrong operation of the LSI. For example, in the case that two F/Fs are connected in series, when the degree of a signal transmission delay between a Q output of F/F in a front stage and a D input of F/F in a rear stage is smaller than the clock skew, the F/F in the rear stage inputs the Q output in the same clock cycle, so that the wrong operation occurs. To avoid the occurrence of the phenomenon, the delay between the Q output and the D input of the two F/F is controlled larger than the clock skew. However, when the value becomes increased, the operation speed of the LSI becomes slower. Accordingly, it is required to control the clock skew as small as possible. Fig. 1 shows an example of a centralized, system which is also a clock drive system of a group of F/Fs according to the prior art. In the same drawing, means flip-flop and BU means clock buffer or buffer. Each the F/F is so connected to a buffer (BU) 1 and a buffer (BU) 2 as to construct a branch structure. The outer clock is inputted into the buffer 1 first, then inputted into the buffer 2, thereafter transmitted into each F/F from the buffer 2. By arranging the inner clock lines into such a branch form, a difference in the line distance between the buffer 2 to each F/F is made small, so that the delay between the lines can be controlled to be relatively small. Accordingly, the clock skew can be also controlled to be small. However, when the circuit scale of LSI becomes so large as is seen recently, the number of F/Fs in some chips reaches several thousands, the total length of the clock lines becomes collectively large, and the difference in the line length from the output of the buffer 2 to each F/Fs also becomes large. Fig. 2 shows an example of a distributed drive system which is another clock drive system according to the prior art. In the same drawing, as similar to Fig. 1, F/F means flip-flop and BU 1a , BU 2a , ..., BU Na-1 , and BU Na (N is a natural number of 1 or more) mean buffer. Each F/F is connected in series to each of the BU 2a , BU 3a , ..., and BU N3 . In this example, the buffers are composed in two phases. The buffer 1a in a first phase drives the buffers 2a, ..., to Na (N is a natural number of 2 or more) in a second phase, and also drives each of the F/Fs which are dependent on each buffer. In the drive system, for example, drive ability β₂ and β Na-1 of the buffer 2a and the buffer Na-1 which respectively have different numbers of F/Fs are determined in the following manner. Namely, a delay time t 2A2B between a point 2A and a point 2B, and a delay time T 2A2C between a point 2A and a point 2C are determined, and then load C 2D2E between a point 2D and a point 2E in a clock line, and load C 2F2G between a point 2F and a point 2G in another clock line are determined, then β₂ and β Na-1 are so determined as to satisfy the following equation: t 2A2B + T (β₂, C 2D2E ) = t 2A2C + T (β Na-1 , C 2F2G ) = Constant, (where T is delay time for driving each load). In the centralized drive system shown in Fig. 1, for example, the linear length from a point 1A to a point 1B is different that from the point 1A to a point 1D. Accordingly, a clock delay caused by RC delay on the line occurs, and a clock skew corresponding thereto also occurs. Namely, the clock skew can not be avoided by the drive system in principle. Particularly, when the scale of the LSI is large, the magnitude of the clock skew can not be ignored. Moreover, since the system is a collective drive system, it is necessary for the buffer 2 to have a big drive ability to operate a plurality of F/Fs. Accordingly, a large amount of current should flow locally in the buffer, thus noise and wrong operation are likely to be caused. While, in the distributed drive system in Fig. 2, a complex calculation is required in order to minimize the clock skew, and a plurality of the buffers respectively having different drive ability are also required, the circuit design of the system becomes very complex. While, when the number of the F/Fs which is connected to a specific buffer becomes large, a clock skew which occurs between both of the terminals of these F/Fs can not be ignored. SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock supply circuit of the type initially mentioned hereinabove, which can effectively control an inner clock skew in order to solve the above-mentioned problem. This object is achieved by providing the features of the characterizing part of claim 1. Further improvements are specified in the sub-claims. A clock supply circuit according to the present invention may comprise a first phase which includes a first buffer and at least one line from a predetermined point on the output side of the first buffer to an input point of each second buffer in each channel, and a dependent phase which is composed of each second buffer and a group of flip-flops which is dependent thereon, and-the circuit is so constructed as to uniformalize line length and capacitive load or F/F in each phase, to unify drive ability of the buffers in the dependent phase, and adjust load capacity by providing extra capacities for adjustment of a clock skew. By the construction of the clock supply circuit as mentioned above, uniformalized load can be driven by the buffers having the same drive ability , so that the clock skew can be reduced. These and other objects, features and advantages of the present invention will be more apparent from the following description of a preferred embodiment, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram of a clock supply circuit of a centralized drive system according to the prior art, Fig. 2 is a diagram of a clock supply circuit of a distributed drive system according to the prior art, Fig. 3 is a diagram of a clock supply circuit using a drive system that is a first embodiment of the present invention, and Fig. 4 is a diagram of a clock supply circuit using a drive system that is a second embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS Fig. 3 shows a first embodiment of a clock supply circuit according to the present invention. In the drawing, CH N (N is a natural number) means channel. In the drawing, each line length, and each line width from a point 3A on the output side of a buffer (BU) 10 to each of buffers 11₋₁, 11₋₂, ..., 11- (N-1) , to 11 -N (N is a natural number) in a first phase are respectively constructed to be the same. Moreover, in a second phase, the drive ability of the buffers 11₋₁, 11₋₂, ..., 11 -(N-1) , and 11 -N are respectively arranged to be the same. The number of F/F of each channel (CH N ), e.i. the number of each of F/F 1m , F/F 2m , ..., F/F (N-1)m , to F/F Nm (m = 1, 2, ..., m) connected to each buffer, and each linear length for connecting these in a second phase are respectively different. Namely, the line conditions from a point 4A on the output side of a buffer 10 to points 4C, 4D, ..., 4F, and 4G which are respectively input points of buffers 11₋₁, 11₋₂, and 11₋₃, ..., 11 -N dispersed into the respective channels in the first phase are the same. For example, in the second phase of the same drawing, a channel CH₁ has the largest number of F/Fs in these channels. In this case, load capacities C₂, C₃, ..., C N-1 , and C N for RC delay adjustment are respectively connected to the end terminals of channels CH₂, CH₃, ..., and CH N to which belong the buffers 11₋₂, 11₋₃, ..., and 11 -N respectively having the smaller number of F/Fs on the basis of the number of F/F 1p (p = 1, 2, ..., P) of the buffer 11₋₁ in the channel CH₁. Each of the load capacities has an adjusted value in accordance with the number of F/Fs which are connected to each of the buffer 11₋₂, 11₋₃, ..., and 11 -N in each of the channels CH₂, CH₃, ..., and CH N , furthermore it is so adjusted as to be substantially the same delay as a signal delay in the standard channel CH₁ in consideration of the linear length of the respective channels CH₂, CH₃, ..., and CH N . Namely, the load capacity C N is calculated by the following equation: C N = Difference in the stray capacity of the line to the standard channel + a gate capacity corresponding to the number of F/Fs which is less than the standard channel. As a manner of embodying the respective load capacity, if it can be realized as a gate capacity of a MOS transistor, the design becomes easy and an area overhead becomes minimized. With respect to the line length of the standard channel CH₁ having a largest number of F/Fs, it is required to determine the range from just after the output to the end terminal of F/F where a bad influence of the clock skew by the RC delay does not occur. Fig. 4 shows a second embodiment of a clock supply circuit according to the present invention. In this embodiment, the construction of a second phase is the same as that of the embodiment in Fig. 3, and the determination manner of the values of the capacities for the respective adjustments is also the same as that of the embodiment in Fig. 3, thus the detailed description on the matter will be omitted herein. In this embodiment, input line lengths from a point 5A on the output side of a first buffer 10 each of points 5C, 5D, ..., 5F, and 5G which are respectively input points of buffers 11₋₁, 11₋₂, ..., 11 -(N-1) , and 11 -N in a first phase are different from one another. In order to minimize a clock skew caused by the differences of the line length, there are provided adjustment capacities C₁₂, C₁₃, ..., and C 1N for prevention of the clock skew caused by the RC delay of the input lines having different lengths on the basis of a specific buffer having a longest input line, for example, the buffer 11₋₁ in the same drawing. In this case, each value of the respective adjustment capacities can be determined in accordance with the respective shortages of capacity in the input lines. Incidentally, in the above embodiments, the cases in which the number of the phases is two are described, however, the present invention is not limited by the number of the phases. As mentioned above, in the clock supply circuit according to the present invention, the construction thereof is divided into the first phase which includes the lines from the first buffer to the input points of the respective buffer which belong to the respective channels in the next phase, and the second phase comprises the respective buffers and the respective channels including the F/Fs which are connected to thereon, and the F/Fs as the load are driven in the substantially uniformalized state of line conditions in the respective phases. Therefore, the clock skew can be controlled to be small. Since the respective buffers in the respective channels in the second phase may be the same kind, and may have the same performance or the same drive ability, it becomes easy to design the circuit. Moreover, even when there are differences in the line length and the number of the F/F which are dependent on the respective channels in the first phase or the second phase or in the both, the adjustment can be easily achieved by adding adjustable capacities so as to adjust the states of the circuit of the respective channels or the line conditions thereof into substantially uniform. As the result, the clock skew can be controlled to be uniform and small even when the drive ability of the respective buffers in the respective channels fluctuate a little.

Claims: A clock supply circuit, comprising (a) a primary buffer (10) for driving a clock signal; (b) a first buffer (11-1) connected to said primary buffer (10) through a first line for receiving the clock signal from said primary buffer (10); (c) at least one second buffer (11-2; 11-(N-1); 11-N) connected to said primary buffer (10) through at least one second line for receiving the clock signal from said primary buffer (10); said first and second lines being equal in length, characterized by (d) a first channel (CH1) connected to said first buffer (11-1) for supplying the clock signal from said first buffer (11-1) to more than one first flip-flops (F/F11 to F/F1p) connected to said first channel (CH1); (e) at least one second channel (CH2; CH-(N-1); CH-N) respectively connected to said at least one second buffer (11-2; 11-(N-1); 11-N) for supplying the clock signal from said at least one second buffer (11-2; 11-(N-1); 11-N) to more than one second flip-flops (F/F21 to F/F2k; F/F(N-1)1 to F/F(N-1)n; F/FN1 to F/FNm) respectively connected to said at least one second channel (CH2; CH(N-1); CHN); and (f) at least one circuit means (C2; C(N-1); CN) respectively connected to at least one second channel (CH2; CH(N-1); CHN) for substantially equalizing delays of the clock signals respectively passing through said first channel (CH1) and said at least one second channel (CH2; CH(N-1); CHN); wherein (g) said first buffer (11-1) and said at least one second buffer (11-2; 11-(N-1); 11-N) have the same drive ability; (h) a total load of said first channel (CH1) is greater than a total load of said at least one second channel (CH2; CH-(N-1); CH-N), respectively, excluding said at least one circuit means (C2; C(N-1); CN); and (i) said at least one circuit means (C2; C(N-1); CN) is a capacitance. The clock supply circuit as claimed in claim 1, wherein said at least one circuit means (C2; C(N-1); CN) is connected to said at least one second channel (CH2; CH(N-1); CHN) at a side opposite to said at least one second buffer (11-2; 11-(N-1); 11-N), respectively. A clock supply circuit, comprising (a) a primary buffer (10) for driving a clock signal; (b) a first buffer (11-1) connected to said primary buffer (10) through a first line for receiving the clock signal from said primary buffer (10); (c) at least one second buffer (11-2; 11-(N-1); 11-N) connected to said primary buffer (10) through at least one second line for receiving the clock signal from said primary buffer (10); characterized by (d) a first channel (CH1) connected to said first buffer (11-1) for supplying the clock signal from said first buffer (11-1) to more than one first flip-flops (F/F11 to F/F1p) connected to said first channel (CH1); (e) at least one second channel (CH2; CH-(N-1); CH-N) respectively connected to said at least one second buffer (11-2; 11-(N-1); 11-N) for supplying the clock signal from said at least one second buffer (11-2; 11-(N-1); 11-N) to more than one second flip-flops (F/F21 to F/F2k; F/F(N-1)1 to F/F(N-1)n; F/FN1 to F/FNm) respectively connected to said at least one second channel (CH2; CH(N-1); CHN); and (f) at least one circuit means (C2; C(N-1); CN) respectively connected to at least one second channel (CH2; CH(N-1); CHN) for substantially equalizing delays of the clock signals respectively passing through said first channel (CH1) and said at least one second channel (CH2; CH(N-1); CHN); wherein (g) said first buffer (11-1) and said at least one second buffer (11-2; 11-(N-1); 11-N) have the same drive ability; (h) a total load of said first channel (CH1) is greater than a total load of said at least one second channel (CH2; CH-(N-1); CH-N), respectively, excluding said at least one circuit means (C2; C(N-1); CN); (i) said at least one circuit means (C2; C(N-1); CN) is a capacitance; (j) at least one second circuit means (C12; C1(N-1); C1N) respectively connected to at least one second line for substantially equalizing delays of the clock signals respectively passing through said first line and said at least one second line; wherein (k) a total load of said first line is greater than a total load of said at least one second line excluding said at least one second circuit means (C12; C1(N-1); C1N), respectively; and (l) said at least one second circuit means (C12; C1(N-1); C1N) is a capacitance. The clock supply circuit as claimed in any of the preceding claims, wherein the total load of said first channel (CH1) is determined by its length and said first flip-flops (F/F11 to F/F1p) and the total load of said at least one second channel (CH2; CH(N-1); CHN) respectively is determined by its length and said at least one second flip-flops (F/F21 to F/F2k; F/F(N-1)1 to F/F(N-1)n; F/FN1 to F/FNm). The clock supply circuit as claimed in any of claims 1 to 4, wherein said first channel (CH1) and said at least one second channel (CH2; CH(N-1); CHN) are equal in number of flip-flops respectively connected thereto, and differ in length. The clock supply circuit as claimed in any of claims 1 to 4, wherein said first channel (CH1) and said at least one second channel (CH2; CH(N-1); CHN) are equal in length, and differ in number of flip-flops respectively connected thereto.

Inventors: MASUDA EIJI, NISHIMURA AKIRA SOEI BLDG, WATANABE HIROYUKI, MASUDA, EIJI, NISHIMURA, AKIRA SOEI BLDG. 301, WATANABE, HIROYUKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G06F1
IPC codes: H01L21, G06F1, H03K5, H01L27