Pipeline circuit for timing adjustment

Abstract: The pipeline circuit comprises a selection signal generating circuit for outputting, when an input indicating signal entered corresponding to one datum out of a series of m input data indicates invalidity, a selection signal indicating the value next to that indicated by the preceding selection signal out of n periodic values and, when the input indicating signal indicates validity a selection signal indicating the same value as that indicated by the selection signal, and a data holding circuit responsive to the selection signal generated by said selection signal generating circuit corresponding to said datum for inputting, depending on the selecting signal, the datum to a respective stage of data holding means and outputting via respective data holding means the datum respective timing cycles later than the inputting of the datum where said data and said input indicating signals are entered and valid data among the data are successively outputted at respective timing cycles. This pipeline circuit for timing adjustment is able to send out at proper timings only such data as are effective for ensuing processings even if the input timings of different data are irregular or the input data include invalid ones.

Description: The present invention relates to a pipeline circuit for adjusting the data timing in a data processing system. Usually, a timing-adjusting pipeline circuit is used for adjusting the timing of data transfers between processing units, particularly for adjusting the timing of data transfers to an interleave type processing unit from another processing unit. An interleave type processing unit in this context typically is a memory unit consisting of a plurality of banks which are used in a time-share manner. Another example of interleave type processing unit is an arithmetic system comprising a plurality of low-speed arithmetic units which are used in a time-share manner to let the whole system achieve high-speed arithmetic operation. In an actual data processing system, in order that data to be written into a memory match their interleave timing as input data to an interleave type processing unit, some kind of timing adjustment is required. A conceivable method of timing adjustment is to adjust the actuating timing of a data processing instruction so that the processed data reach the input crossbar at the interleave timing referred to above. This method necessitates no particular timing adjuster. However, it entails complex control of the instruction actuating timing, thereby affects the processing start times of other processing units than the memory and may deteriorate the overall performance of the data processing system. Therefore, a timing-adjusting circuit should be provided immediately before the input crossbar. If a series of data A = (a 1 , a 2 , ..., a m ) is inputted, the output timing of the first datum a 1 is adjusted with a selection signal S and those of the succeeding data a 2 , a 3 ,... as inputs to the interleave type processing unit are so controlled as to be identical with the interleave timing by maintaining the selection signal S at the time of the outputting of the datum a 1 . However, this circuit cannot be used when, for instance, the input timings of different data are irregular as is the case with the output data of a processing unit whose processing time differs with the value of each datum or when the series of data include invalid ones that cannot be processed with an interleave type processing unit, such as data for masked vector processing. WO-86/03608 discloses a queue administration system which performs validity checks on stored requests for execution. An object of the present invention is, therefore, to provide a pipeline circuit for timing adjustment designed to be able to send out at proper timings such data as are effective for ensuing processings even if the input timings of different data are irregular or the input data include invalid ones. This object is solved with the features of the claims. According to a first embodiment the selection signal generating circuit for generating selection signals to determine the durations of data holding by the data holding circuit is controlled with input indicating signals T 1 , T 2 . ..., T j , T m indicating the validity or invalidity of the input data A 1 , A 2 . ..., A j , ..., A m . If the input indicating signals T 1 , T 2 . ..., T j , ..., T m consecutively indicate validity, the selection signal will retain its value for the first input datum, but if an input indicating signal T j indicating invalidity is inputted midway, the selection signal will change to its next value. This operation makes it possible, even if the imput timings of different data are irregular or the input data include both valid and invalid ones, to send out at proper timings only effective data for ensuing processings by making ready input indicating signals T 1 , T 2 . ..., T j ,..., T m matching them. The data holding circuit, even if the input timings of different data are irregular or the input data include both valid and invalid ones, sends out at proper timings only effective data for ensuing processings by controlling the data holding durations and the validity or invalidity of the input data A j in accordance with the selection signals generated by said selection signal generating circuit and said input indicating signals. According to a second embodiment the selection signal generating circuit for generating selection signals to determine the durations of data holding by the data holding circuit is controlled with input indicating signals T 1 , T 2 . ..., T j , ..., T m indicating the validity or invalidity of the input data A 1 , A 2 . ..., A j , ..., A m . If the input indicating signals T 1 , T 2 . ..., T j , ..., T m consecutively indicate validity, the selection signal will retain its value for the first input datum, but if an input indicating signal T j indicating invalidity is inputted midway, the selection signal will change to its next value. Further, the output indicating signal V j Indicating whether the input to the n-th data holding means R n of the data holding circuit is to be validated or invalidated is generated by the indicating signal holding circuit on the basis of the input indicating signal T j and the selection signal S j . The data holding circuit, even if the input timings of different data are irregular or the input data include both valid and invalid ones, sends out at proper timings only effective data for ensuing processings by controlling the data holding durations and the validity or invalidity of the input data A j in accordance with the selection signals generated by the selection signal generating circuit and the output indicating signals generated by the indicating signal holding circuit. Features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of a first preferred embodiment of the invention; FIG. 2 is a time chart illustrating the operation within the pipeline circuit which is the first preferred embodiment of the invention; FIG. 3 is a time chart illustrating one example of a method to stagger the operating timings of the pipeline circuit illustrated in FIG. 1; FIG. 4 is a timing chart illustrating an example of the operation of an input crossbar using an output from the pipeline circuit which is the first preferred embodiment of the invention; FIG. 5 is a block diagram of a second preferred embodiment of the invention; FIG. 6 is a timing chart illustrating an example of the operation of an input crossbar using an output from the pipeline circuit which is the second embodiment of the invention; FIG. 7 is a block diagram of an example of the configuration of memory-peripheral circuits to which the pipeline circuit, which is the second embodiment, is applied; FIG. 8 is a block diagram of an example of the configuration of a data processing apparatus having a memory comprising four banks; FIG. 9 is a time chart illustrating an example of the operation of the input crossbar 903 of FIG. 8; FIG. 10 is a block diagram of a third preferred embodiment of the invention; FIG. 11 is a time chart illustrating the operation within the pipeline circuit which is the third preferred embodiment of the invention; FIG. 12 is a time chart illustrating one example of method to stagger the operating timings of the pipeline circuit illustrated in FIG. 10; FIG. 13 is a timing chart illustrating an example of the operation of an input crossbar using an output from the pipeline circuit which is the third preferred embodiment of the invention; FIG. 14 is a block diagram of a fourth preferred embodiment of the invention; FIG. 15 is a block diagram of a fifth preferred embodiment of the invention; FIG. 16 is a block diagram of a sixth preferred embodiment of the invention; FIG. 17 is a time chart illustrating the operation within the pipeline circuit which is the sixth preferred embodiment of the invention; FIG. 18 is a time chart illustrating one example of a method to stagger the operating timings of the pipeline circuit illustrated in FIG. 16; FIG. 19 is a timing chart illustrating an example of the operation of an input crossbar using an output from the pipeline circuit which is the sixth preferred embodiment of the invention; FIG. 20 is a block diagram of a seventh preferred embodiment of the invention; and FIG. 21 is a block diagram of a eighth preferred embodiment of the invention. In the figures, the same reference numerals denote respectively the same constituent elements. FIG. 8 is a typical block diagram of memory-peripheral circuits of a data processing apparatus capable of writing a series of data A = (a 1 , a 2 , ..., a m ) and another series of data B = (b 1 , b 2 , ..., b m ) into a memory 904 comprising four banks, BANK1, BANK2, BANK3 and BANK4. FIG. 9 is a time chart illustrating the operation of an input crossbar 903 in FIG. 8. Referring to FIGS. 8 and 9, each of the banks BANK1 to BANK4 of the memory 904 requires two timing cycles of time for the data to be written into. An input register RIA, whose input is the series of data A = (a 1 , a 2 , ..., a m ), is assigned a reference timing cycle 1 of the crossbar control an another input register RIB, whose input is the series of data B = (b 1 , b 2 , ..., b m ) , is assigned a reference timing cycle 3 of same. An output register ROR1 has a decoder D1 or decoding a selection signal SL1 and a selecting circuit SE1 for selecting and outputting an input corresponding to the output of the decoder D1, and selects and stores the output data from the input register RIA when the reference timing cycle is 1; selects and stores the output data from the input register RIB when the reference timing cycle is 3, and holds the previous data when the reference timing cycle is 2 or 4. Output registers ROR2, ROR3 and ROR4 respectively have decoders D2, D3 and D4 for decording selection signals SL2, SL3 and SL4 and selecting circuits SE2, SE3 and SE4 for selecting and outputting their inputs corresponding to the outputs of the decoders D2, D3 and D4, and operate in the same manner as the output register ROR1 in response to the selection signals SL2, SL3 and SL4, respectively. Referring now to FIG. 9, the output register ROR1 selects the output datum a 1 from the input register RIA at timing t1 in response to the value "1" of the selection signal SL1, stores it at timing t2 and holds it until timing t3. As it selects the output datum b 1 from the input register RIB in response to the value "3" of the selection signal SL1, the datum b 1 is stored at timing t4 and is held until timing t5. In this manner, the 4xk+1-th (k is a natural number) data a 1 , b 1 , a 5 , b 5 , a 9 , b 9 , ... of the two serial data A and B are successively stored into the output register ROR1, and become input data for the bank BANK1 of the memory 904. Similarly, the 4 x k+2-th data a 2 , b 2 , a 6 , b 6 , a 10 , b 10 , ... of the two serial data A and B are successively stored into the bank BANK2 through the output register ROR2; the 4 x k+3-th data a 3 , b 3 , a 7 , b 7 , a 11 , b 11 , ... of the two serial data A and B are successively stored into the bank BANK3, and the 4 x k+4-th data a 4 , b 4 , a 8 , b 8 , a 12 , b 12 , ... of the two serial data A and B are successively stored into the bank BANK4. The operations described with reference to FIG. 9 presupposes that 4 x k + 1-th data a 1 , a 5 , a 9 , ... of the serial data A is entered into the input register RIA and the 4 x k + 3-th data b 3 , b 7 , b 11 , ... of the serial data B are entered into the input register RIB when the reference timing cycle of the input crossbar 903 is "1", the 4 x k + 2-th data a 2 , a 6 , a 10 , ... of the serial data A and the 4 x k + 4-th data b 4 , b 8 , b 12 , ... of the serial data B are entered into the input registers RIA and RIB, respectively, when the reference timing cycle is "2", the 4 x k + 3-th data a 3 , a 7 , a 11 , ... of the serial data A and the 4 x k + 1-th data b 1 , b 5 , b 9 , ... of the serial data B are entered into the input registers RIA and RIB, respectively, when the reference timing cycle is "3", and the 4 x k + 4-th data a 4 , a 8 , a 12 , ... or the serial data A and the 4 x k + 2-th data b 2 , b 6 , b 10 , ... of the serial data B are entered into the input registers RIA and RIB, respectively, when the reference timing cycle is "4". Now will be explained a form of data to which the present invention applies and the way in which the form of data is described below. One of the types of data to which the invention applies is a series x of data x 1 , x 2 , ..., x m , wherein the intervals between the elemental data x 1 , x 2 , ... are irregular. An example of this type is output data from a processing unit whose processing time differs with the value of each datum or the like. Data R = (r 1 , r 2 , ..., r m ) outputted from an arithmetic unit or a processor in which arithmetic operations, differing with a datum-corresponding control signal V = (v 1 , v 2 , ... v m ), take place between a series Y of operand data y 1 , y 2 ,..., y m and another series W of operand data w 1 , w 2 , ..., w m , and the processing time differs with the type of operation, the value of datum and the like, are an example of the irregular intervals between elemental data as mentioned above. Where data are successively outputted at irregular intervals, for instance the second datum r 2 appears five timing cycles after the first datum r 1 and the third r 3 does three timing cycles after that, if the arithmetic unit is a type which holds a datum until the next datum is outputted, a description of equal intervals on the time axis (i.e. at every timing cycle) will be D = (r 1 , r 1 , r 1 , r 1 , r 1 , r 1 , r 2 , r 2 , r 2 , r 3 , ..., r m ), and a case in which invalid data appear between valid data will be represented in such a way as E = (r 1 , -, -, -, -, r 2 , -; -, r 3 , ..., r m ). Outputs of such an arithmetic unit require signals indicating the timings of valid data for ensuring data correspondence. Validity being represented by "1" and invalidity, by "0", a signal F indicating a valid datum and the above data D or E will be F = (1, 0, 0, 0, 0, 1, 0, 0, 1, ..., 1), and correspond to data G = (g 1 , g 2 , ..., g t ) representing D and E. In the foregoing examples, g 1 = r 1 , g 6 = r 2 , g 9 = r 3 ..., g t = r m , and all other elemental data g 2 , g 3 , g 4 , g 5 , g 7 , g 8 , ... are invalid data whose values are irrelevant here. Another example of irregular intervals between elemental data of a data series is found in data read out of a memory whose access time varies with the address. Further, if data from a processing system whose data transfer rate varies with the mode of use or the state of hardware (for instance, where three processing units are normallv used and two of them continue processing in the event of one running into trouble, the number of processing units at work at a given point of time) are to be placed under the same control irrespective of the mode of use or the state of hardware, there will be required, as described above, the combination of a data series including both valid and invalid data and, corresponding to these data, a signal indicating the validity or invalidity of each elemental datum, and the data and the indicating signal can be represented like the aforementioned data G and indicating signal F, respectively. In still another type of data to which the present invention applies, the validity or invalidity of individual data is indicated by another set of data. In a vector data processing apparatus, for instance, the concept of mask bit is used to distinguish between valid and invalid elemental data among vector data. A mask bit indicates valid data among operand vector data, so that valid data alone can be put to arithmetic operation or the operation is executed for all data and the validity or invalidity of the data resulting from the operation is indicated with a mask bit. These manners of operation are known as masked operations. Like the data of the first type described above, the vector data can be represented by H = (h 1 , h 2 , ..., h t ) and the mask data, by J = (j 1 , j 2 , ..., j t ). Now, in the following description, said first and second types will be represented by an input data series A (a 1 , a 2 , ..., a m ) and indicating signals T = (1, 0, ..., 1) indicating the validity or invalidity of the data. This means that, where elemental data a 1 , a 2 ..., a m are consecutively inputted in every timing cycle, a 1 is a valid datum, a 2 , an invalid datum, and ..., a m are valid data. Referring now to FIG. 1, a pipeline circuit 1000 in the first preferred embodiment of the present invention receives an input indicating signal T and a data series A = (a 1 , a 2 , ..., a m ) as inputs, and outputs a data series Y = (y 1 , y 2 ..., y m ). A selection signal S from a selection signal generating circuit 101 is inputted to a data holding circuit 102, and is decoded by a decoder DCD to generate selections signals S 1 , S 2 , S 3 and S 4 for four stages of data holding means R1, R2, R3 and R4, respectively, into one or another of which is stored the input data A. If the selection signal S 3 out of the selection signals S 1 , S 2 , S 3 and S 4 is valid (logical "1"), the data A will be stored into the data holding means R3. The data A stored in the data holding means R3 are stored into the data holding means R4 one timing cycle later, and supplied as the output data of the data holding circuit 102, i.e. the output data Y of the pipeline circuit 1000. The data holding means R2 can be realized, for instance as illustrated, with a register RG2 having a two-input one-output selecting circuit SE12 to whose first and second stage inputs are respectively supplied the output of the first data holding means R1 and the input data A and a gate G12 which provides the inverted signal of the selection signal S 2 to the first stage of the selecting circuit SE12 and at the same time the uninverted selection signal S 2 to the second stage of the selecting circuit SE12. This data holding means R2 selects and stores the data A when the selection signal S 2 is valid or the output data of the data holding means R1 when the selection signal S 2 is invalid (logical "0"). The data holding means R3 and R4, like the data holding means R2, can be respectively realized with registers RG3 and RG4 having two-input one-output selecting circuits SE13 and SE14 to whose first and second stage inputs are supplied the outputs of the preceding-stage data holding means R2 and R3 and the input data A, respectively, and gates G13 and G14 which provide the inverted signals of the selection signals S 3 and S 4 to the first stages of the selecting circuits SE13 and SE14 and at the same time the uninverted selection signals S 3 and S 4 to the second stages of the selecting circuits SE13 and SE14. The data holding means R1 can be realized with a register RG1 having a selecting circuit SE11 which outputs the data A when the selection signal S 1 is valid and stores the data A through this selecting circuit SE11. The selection signal generating circuit 101, when the input indicating signal T entered corresponding to the data A indicates invalidity (logical "0"), generates and outputs a selection signal S indicating the value next to that indicated by the preceding selection signal S out of four periodic values 1, 2, 3, 4, 1 and 2, ... . For instance, if an input indicating signal T = 0 is inputted when the selection signal S indicates "1", the selection signal S will indicate "2" at the next timing. Similarly, if an input indicating signal T = 0 is inputted when the selection signal S indicates "2", the selection signal S will indicate "3" at the next timing; if an input indicating signal T = 0 is inputted when the selection signal S indicates "3", the selection signal S will indicate "4" at the next timing, and if an input indicating signal T = 0 is inputted when the selection signal S indicates "4", the selection signal S will indicate "1" at the next timing. Conversely, if the input indicating signal T indicates validity (logical "1"), the selection signal generating circuit 101 will hold the value indicated by the preceding selection signal S. If, for instance, an input indicating signal T = 1 is inputted when the selection signal S indicates "1", the selection signal S will indicate "1" at the next timing, too. The selection signal generating circuit 101 referred to above, as illustrated, can be realized with a cycle counter CNT having a two-input one-output selecting circuit SE21 to whose first and second stage inputs are respectively supplied the output of a +1 circuit AD and the current value of the selection signal S and a gate G21 which provides the inverted signal of the input indicating signal T to the first stage of the selecting circuit SE21 and at the same time the uninverted selection signal T to the second stage of same. This cycle counter CNT varies the value of the selection signal in synchronism with the timing cycle by selecting the value "S+1", which is the output of the +1 circuit AD, when the input indicating signal T is "0" or the value "S" when T is "1". This selection signal S can indicate one of four values, 1, 2, 3 and 4. The operation of the pipeline circuit 1000 will be described below with reference to the time chart of FIG. 2, in which said registers RG1 to RG4 in the data holding means R1, R2, R3 and R4 are represented by first, second, third and fourth registers, respectively, and a register which receives the inputting of and stores the output data Y of the pipeline circuit 1000 and outputs them as data Z is represented by a Z register 103. In FIG. 2, input indicating signals T corresponding to the input data series A = (a 1 , a 2 , a 3 , ...) are supposed to be (0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0 and 0, ...). Thus a 2 , a 5 , a 6 , a 10 , and a 13 , ... are valid data and, conversely, a 1 , a 3 , a 4 , a 7 , a 8 , a 9 , a 11 , a 12 , a 14 , a 15 , a 16 , a 17 , and a 18 , ... are invalid data. Further, the timing at which the first elemental datum a 1 of the input data series A is entered is supposed to be t1, and the selection signal S at that time, to indicate "2". Before the datum a 1 is entered, i.e. before timing t1, the selection signal S periodically varies to indicate one or another of four recurring values, 1, 2, 3, 4, 1, 2, 3, 4 and 1, ... until it indicates "2" at timing t1. Referring to FIG. 2, the datum a 1 inputted at timing t1 is entered into the second register RG2 in response to the selection signal S (= 2) at that time, and stored at the next timing t2. The selection signal S at timing t2 indicates "3", the value next to that of the selection signal S (= 2) of timing t1 in response to the input indicating signal T (= 0) at the preceding timing t1. Then, the datum a 2 inputted at timing t2 is entered into the third register RG3 in response to the selection signal S (= 3) at that time, and stored at the next timing t3. The datum a 1 stored into the second register RG2 is not stored into the third register RG3 at timing t3 and instead is invalidated. The selection signal S at timing t3, in response to the input indicating signal T (= 1) at the preceding timing t2, is stored at timings t4, t5, t9, t10, t11, t12, t16 and t17, ... to become an element datum of the output data series Y of the pipeline circuit 1000, and stored into the Z register 103 at the respectively next timings t5, t6, t10, t11, t12, t13, t17 and t18, ... . The intervals of the output timings of the valid data a 2 , a 5 , a 6 , a 10 , a 13 , ... among the elemental data of the input serial data A = (a 1 , a 2 , a 3 , ...) are 4xk+1 timing cycles (k is an integer), such as 5 (= 4 x 1 + 1) timing cycles between the data a 2 and a 5 , 1 (= 4 x 0 + 1) timing cycle between the data a 5 and a 6 , 1 timing cycle between the data a 6 and a 10 , 5 timing cycles between the data a 10 and a 13 , ... . If the pipeline circuit 1000 is used as pipeline circuits 901 and 902 in FIG. 8, said Z register 103 will correspond to the input registers RIA and RIB. Now will be described with reference to the time chart of FIG. 3 an example of the operation of the pipeline circuit 902 when a reference timing cycle "1" of the input crossbar 903 is assigned to the input register RIA, another reference timing cycle "3" of same, to the input register RIB, and timing t5 shown in FIG. 2 (the timing at which the data a 2 is stored into the Z register 103, i.e. the input register RIA) coincides with the crossbar reference timing "1" (namely the operation shown in FIG. 2 is that of the pipeline circuit 901). It is not meant that each reference timing cycle shown here has hardware items, such as a cycle counter, but it is a virtual timing cycle for designing or verifying a circuit for controlling data transfers, so that nothing more is required than for the timings of different parts within the data processing apparatus to be consistent with one another. Referring now to FIG. 3, at timings before timing t0, a selection signal S B varies one timing cycle ahead of the crossbar reference timing. Thus, if the first valid datum is inputted (accompanied by the input indicating signal T (= 1)) in this state, the valid datum will be stored into the Z register 103 (i.e. the input register RIB) when the crossbar reference timing is "1". Since the crossbar reference timing of "3" is assigned to the input register RIB whose inputs are the data series B as stated above, the operating timing has to be shifted. If, for instance, a dummy input indicating signal T = 1 is inputted twice at timings preceding the inputting of the first valid datum, the pipeline circuit 902 can store the first effective datum into the input register RIB when the crossbar reference timing is "3". Thus, referring to FIG. 3, by inputting the dummy input indicating signal T = 1 at timings t2 and t3, the pipeline circuit 902 will be standing by at timing t4 in a state one timing cycle behind the crossbar reference timing. If, in that state, the input data series B (= b 1 , b 2 , b 3 , ...) and the input indicating signals T (= 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, ...) corresponding to the data are entered from timing t5 on, the pipeline circuit 902 will operate in the same manner as the pipeline circuit described with reference to FIG. 2, and data b 1 , b 3 , b 4 , b 5 , b 7 , ... are stored into the fourth register, which also is an output register of the pipeline circuit 902, at timings t6, t10, t11, t12, t13, ..., respectively, and into the Z register, i.e. the input register RIB, at the respectively next timings t7, t11, t12, t13, t14, ... . The data entered into the input registers RIA and RIB by the operations illustrated in FIGS. 2 and 3 are further entered into the banks BANK1, BANK2, BANK3 and BANK4 of the memory 904 by the operation shown in the time chart of FIG. 4. As stated above, a reference timing cycle of "1" is assigned to the input register RIA, and one of "3" to the input register RIB. The output register ROR1 selects and enters an output datum of the input register RIA when the reference timing cycle is "1"; stores it when the cycle is "2"; selects and enters an output datum of the input register RIB while holding the preceding datum when the cycle is "3"; stores it when the cycle is "4"; selects and enters another output datum of the input register RIA while holding the preceding datum when the cycle is again "1"; stores it when the cycle is again "2", ......, and repeats these same operations in the four timing cycles. As also described above, the output register ROR2 operates in the same manner as the output register ROR1 except that the former is one timing cycle behind the latter. Thus, it repeats in four timing cycles the operations of selecting and entering an output datum of the input register RIA, storing it at the next timing when the reference timing cycle is "2", selecting and entering an output datum of the input register RIB, and storing it at the next timing when the reference timing cycle is "4". The output register ROR3 operates in the same manner as the output register ROR2 except that the former is another timing cycle behind the latter, and this correspondingly applies to the output register ROR4. As a result of these operations, as shown in FIG. 4, when the reference timing cycle is "1", the datum a 2 stored into the input register RIA at timing t5 is stored into the output register ROR1 at timing t6, and the datum a 4 stored into the input register RIA at timing t6 is stored into the output register ROR2 at timing t7; and when the reference timing cycle is "3", the datum b 1 stored into the input register RIB at timing t7 is stored into the output register ROR1 at timing t8. Similar operations are repeated thereafter, and the data a 2 , b 1 , b 3 , a 11 , b 8 , a 13 , ... are entered into the bank BANK1 of the memory via the output register ROR1, the data a 4 , a 5 , b 4 , b 10 , a 16 , ... are entered into the bank BANK2 of the memory via the output register ROR2, the data a 6 , b 5 , ... are entered into the bank BANK3 of the memory via the output register ROR3, and the data a 10 , b 7 , ... are entered into the bank BANK4 of the memory via the output register ROR4. To consider here a serial data D (= d 1 , d 2 , d 3 , d 4 , d 5 , ... = a 2 , a 5 , a 6 , a 10 , a 13 , ...) comprising only valid ones out of the serial data A (= a 1 , a 2 , a 3 , ...) and a serial data F (=f 1 , f 2 , f 3 , f 4 , f 5 , ... = b 3 , b 4 , b 5 , b 7 , b 8 , ...) only valid ones out of the serial data B (= b 1 , b 2 , b 3 , ...), it is seen that the 4xk+1-th (k is an integer) data d 1 (= a 2 ), f 1 (=b 3 ), d 5 (= a 13 ), f 5 (= b 8 ), ... of the serial data D and F are entered into the bank BANK1 of the memory; the 4xk+2-th (k is an integer) data d 2 (= a 5 ), f 2 (=b 4 ), ... of the data series D and F, into the bank BANK2 of the memory; the 4xk+3-th data d 3 (= a 6 ), f 3 (= b 5 ), ... of the data series D and F, into the bank BANK3 of the memory; and the 4xk+4-th data d 4 (= a 10 ), f 4 (= b 7 ), ... of the data series D and F, into the bank BANK4 of the memory. Thus it is seen that the pipeline circuit according to the present invention is effective for adjusting the timing to supply data, even if the input data include invalid data, to an interleave type processing apparatus in a sequence for valid data alone. FIG. 5 is a block diagram of a second preferred embodiment of the present invention, where the advantage of the pipeline circuit according to the invention is increased by having not only the input data series A but also the input indicating signals T, as referred to in the first embodiment shown in FIG. 1, inputted to a data holding circuit 502. Referring to FIG. 5, a pipeline circuit 5000 has input indicating signals T and a data series A (= a 1 , a 2 , ..., a m ), and supplies output indicating signals H and a data series Y. The data holding circuit 502 receives a selection signal S from a selection signal generating circuit 501, decodes it with a decoder DCD into selection signals S 1 , S 2 , S 3 and S 4 for four stages of data holding means R1, R2, R3 and R4, respectively, and stores data P, each of which consists of a pair of one of the data A and an input indicating signal T corresponding to that datum, into one of the four-stage data holding means R1, R2, R3 and R4. If, for instance, the selection signal S 3 out of the selection signals S 1 , S 2 , S 3 and S 4 is valid, the data P will be stored into the data holding means R3. The data P stored in the data holding means R3 are stored into the data holding means R4 one timing cycle later to become the output data of the data holding circuit 502, i.e. of the pipeline circuit 5000. There are a Z register 503 and an E register 504 for respectively storing output data Y, which correspond to the input data A of the output data of the data holding circuit 502, and data H corresponding to the input indicating signals T of same, and outputting them as data Z and E. Description of other parts of the pipeline circuit 5000 is dispensed with because they are equivalent to those of the pipeline circuit 1000 of FIG. 1. If the pipeline circuit 5000 is used as the pipeline circuits 901 and 902 in FIG. 8, a register combining said E register and Z register will correspond to the input registers RIA and RIB of the input crossbar 903, but partial registers corresponding to the E register will be referred to as EIA and EIB and those corresponding to the Z register, as RIA and RIB here as illustrated in FIG. 7 for the convenience of description. The registers RIA and EIA operate in the same manner, and so do the registers RIB and EIB. Similarly, partial registers EOR1 to EOR4, as shown in FIG. 7, are also added as output registers, and it is supposed that the registers ROR1 and EOR1 operate in the same manner and so do the pair of registers ROR2 and EOR2, that of registers ROR3 and EOR3 and that of registers ROR4 and EOR4. An example of operation in the input crossbar 903 when the pipeline circuit 5000 is used as the pipeline circuits 901 and 902 in FIG. 7 will be described below with reference to the block diagram of FIG. 7 and the time chart of FIG. 6. Input indicating signals corresponding to the input serial data A = (a 1 , a 2 , a 3 , ...) to the pipeline circuit 901 being represented by T A (= 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, ...) and those corresponding to the input serial data B = (b 1 , b 2 ,b 3 , ...) to the pipeline circuit 902 being represented by T B (= 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, ...), these data are entered into the input registers RIA, EIA, RIB and EIB of the crossbar 903 as shown in FIG. 6 in the same manner as in the first embodiment described with reference to FIGS. 1 to 4. Referring to FIG. 6, when the reference timing cycle is "1", the datum a 2 and the indicating signal "1" for the data a 2 respectively stored at timing t5 into the input registers RIA and EIA are stored at timing t6 into the output registers ROR1 and EOR1; the datum a 4 and the indicating signal "0" for the data a 4 respectively stored at timing t6 into the input registers RIA and EIA are stored at timing t7 into the output registers ROR2 and EOR2, and when the reference timing cycle is "3", the datum b 1 and the indicating signal "0" for the data b 1 respectively stored at timing t7 into the input registers RIA and EIB are stored at timing t8 into the output registers ROR1 and EOR1. Similar operations are repeated thereafter, so that the data a 2 , b 1 ,b 3 , a 11 , ... are stored into the output register ROR1; indicating signals 1, 0, 1, 0, ... respectively corresponding thereto are stored into the output register EOR1; the data a 4 , a 5 ,b 4 , ... are stored into the output register ROR2; indicating signals 0, 1, 1, ... respectively corresponding thereto are stored into the output register EOR2; the data a 6 ,b 5 , ... are stored into the output register ROR3; indicating signals 1, 1, ... respectively corresponding thereto are stored into the output register EOR3; and the data a 10 , b 7 , ... are stored into the output register ROR4, indicating signals 1, 1, ... respectively corresponding thereto are stored into the output register EOR4. The datum a 2 and the indicating signal "1" for it stored into the output registers ROR1 and EOR1 at timing t6 are entered into the bank BANK1 of the memory and, as the indicating signal is "1", the datum a 2 is stored into the bank BANK1 of the memory at timing t7. The datum a 4 and the indicating signal "0" for it stored into the output registers ROR2 and EOR2 at timing t7 are entered into the bank BANK2 of the memory, but, as the indicating signal is "0", the datum a 4 is not stored therein. Thereafter, by similar operations, the data a 2 , b 3 , ... are stored into the bank BANK1, the data a 5 , b 4 , ..., into the bank BANK2, the data a 6 , b 5 , ..., into the bank BANK3, and the data a 10 , b 7 , ..., into the bank BANK4 of the memory. By the operations described so far, the valid data a 2 , a 5 , a 6 , a 10 , a 13 , ... out of the input serial data A (= a 1 , a 2 , a 3 , ...) and the valid data b 3 , b 4 , b 5 , b 7 , b 8 , ... out of the input serial data B (= b 1 , b 2 , b 3 , ...) entered into the pipeline circuit are stored in the memory in the sequence of valid data alone. Thus the pipeline circuit 5000 of FIG. 5 represents an addition, to the functions of the pipeline circuit 1000 of FIG. 1, of another function to convey the indication of validity or invalidity of the output data to another circuit downstream. Referring now to FIG. 10, a pipeline circuit 3000 in a third preferred embodiment of the present invention has input indication signals T and a serial data A (= a 1 , a 2 , ..., a m ) as its inputs and outputs a serial data Y (y 1 , y 2 , ..., y t ). A data holding circuit 302 receives the inputting of a selection signal S from a selection signal generating circuit 101, generates selection signals S 1 , S 2 , S 3 and S 4 for four stages of data holding means R1', R2', R3' and R4', respectively, by decoding the selection signal S, and stores the input data A into one of the four-stage data holding means R1', R2', R3' and R4'. If, for instance, the selection signal S 3 out of the selection signals S 1 , S 2 , S 3 and S 4 is valid (logical "1" for example), the data A will be stored into the data holding means R3'. If, however, the input indicating signal is invalid (logical "0" for example), the data A will be invalidated and not stored into the data holding means R3′. The data A, stored into the data holding means R3′ when the input indicating signal T is valid, are stored into the data holding means R4′ one timing cycle later, and supplied as the output data of the data holding circuit 302, i.e. as the output data Y of the pipeline circuit 3000. The data holding means R2′, for instance as illustrated, can be realized with a register RG2 having a two-input one-output selecting circuit SE12 to whose first and second-stage inputs are supplied the output of the first data holding means R1′ and the input data A, respectively, a gate G12 which provides the inverted signal of the selection signal S 2 to the first stage of the selecting circuit SE12 and at the same time outputs the uninverted selection signal S 2 and a gate G16 which supplies the logical product of the input indicating signal T and the selection signal S 2 to the second stage of the selecting circuit SE12. It selects and stores the data A when both the input indicating signal T and the selection signal S 2 are valid or the output data of the data holding means R1′ when the selecting signal S 2 is invalid. The data holding means R3′ and R4′, like the data holding means R2′, can be respectively realized with registers RG3 and RG4 having two-input one-output selecting circuits SE13 and SE14 to whose first and second stage inputs are supplied the outputs of the preceding-stage data holding means R2′ and R3′ and the input data A, respectively, and gates G15 and G17 which provide the inverted signals of the selection signals S 3 and S 4 to the first stages of the selecting circuits SE13 and SE14 and at the same time the uninverted selection signals S 3 and S 4 to the second stages of the selecting circuits SE13 and SE14. The data holding means R1′ can be realized with a register RG1 having a selecting circuit SE11 which outputs the data A when the output of a gate G11 supplying the logical product of the selection signal S 1 and the input indicating signal T is valid, and stores the data A through this selecting circuit SE11. The selection signal generating circuit 101, when the input indicating signal T entered corresponding to the data A indicates invalidity (logical "0"), generates and outputs a selection signal S indicating the value next to that indicated by the preceding selection signal S out of four periodic values 1, 2, 3, 4, 1 and 2, .... For instance, if an input indicating signal T = 0 is inputted when the selection signal S indicates "1", the selection signal S will indicate "2" at the next timing. Similarly, if an input indicating signal T = 0 is inputted when the selection signal S indicates "2", the selection signal S will indicate "3" at the next timing; if an input indicating signal T = 0 is inputted when the selection signal S indicates "3", the selection signal S will indicate "4" at the next timing, and if an input indicating signal T = 0 is inputted when the selection signal S indicates "4", the selection signal S will indicate "1" at the next timing. Conversely, if the input indicating signal T indicates validity (logical "1"), the selection signal generating circuit 101 will hold the value indicated by the preceding selection signal S. If, for instance, an input indicating signal T = 0 is inputted when the selection signal S indicates "1", the selection signal S will indicate "1" at the next timing, too. The selection signal generating circuit 101 referred to above can be realized, as illustrated, with a cycle counter CNT having a two-input one-output selecting circuit SE21 to whose first and second stage inputs are respectively supplied the output of a +1 circuit AD and the current value of the selection signal S and a gate G21 which provides the inverted signal of the input indicating signal T to the first stage of the selecting circuit SE21 and at the same time the uninverted selection signal T to the second stage of same. This cycle counter CNT varies the value of the selection signal in synchronism with the timing cycle by selecting the value "S+1", which is the output of the +1 circuit AD, when the input indicating signal T is "0" or the value "S" when the input indicating signal T is "1". This selection signal S can indicate one of four values, 1, 2, 3 and 4. The operation of the pipeline circuit 3000 will be described below with reference to the time chart of FIG. 11, in which said registers RG1 to RG4 in the data holding means R1′, R2′, R3′ and R4′ are representec by first, second, third and fourth registers, respectively, and a register which receives the inputting of and stores the output data Y of the pipeline circuit 3000 and outputs them as data Z is represented by a Z register 103. In FIG. 11, input indicating signals T corresponding to the input serial data A = (a 1 , a 2 , a 3 , ...) are supposed to be (0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0 and 0, ...). Thus a 2 , a 5 , a 6 , a 10 , and a 13 , ... are valid data and, conversely, a 1 , a 3 , a 4 , a 7 , a 8 , a 9 , a 11 , a 12 , a 14 , a 15 , a 16 , and a 17 , ... are invalid data. Further, the timing at which the first elemental datum a 1 of the input data series A is entered is supposed to be t1, and the selection signal S at that time, to indicate "2". Before the datum a 1 is entered, i.e. before timing t1, the selection signal S periodically varies to indicate one or another of four recurring values, 1, 2, 3, 4, 1, 2, 3, 4 and 1, ... until it indicates "2" at timing t1. Referring to FIG. 11, the datum a 1 inputted at timing t1 is not entered into the second register RG2 and is invalidated instead, though the selection signal S is "2" at that time, because the input indicating signal is invalid (logical "0"). The selection signal S at timing t2 indicates "3", the value next to that of the selection signal S (= 2) of timing t1 in response to the input indicating signal T (= 0) at the preceding timing t1. Then, the datum a 2 inputted at timing t2 is entered into the third register RG3 in response to the selection signal S (= 3) at that time because the input indicating signal T is valid (logical "1"), and stored at the next timing t3. The selection signal S at timing t3 holds the selection signal S (= 3) of timing t2 in response to the input indicating signal T (= 1) at the preceding timing t2. In response to the selection signal S (= 3) of timing t3, the output datum a 2 of the third register RG3 is entered into the fourth register RG4, and stored at the next timing t4. Further, the datum a 3 entered at timing t3 is not entered into the third register RG3 at timing t3 and instead is invalidated, though the selection signal S at that time indicates "3", because the input indicating signal T indicates "0". The selection signal S at timing t4, in response to the input indicating signal T (= 0) of timing t3 and the selection signal of "3", indicates the next value "4". The datum a 4 entered at timing t4 is not entered into the fourth register RG4 and is invalidated instead because the selection signal S and input indicating signal T at that time are "4" and "0", respectively. The selection signal S at timing t5, in response to the input indicating signal T (= 0) and the selection signal of "4" at timing t4, indicates the next value "1". Similar operations are repeated at and after timing t5, and into the fourth register RG4, which also is the output register of the pipeline circuit 3000, are stored the data a 2 , a 5 , a 6 , a 10 , a 13 , ... at timings t4, t9, t10, t11, t16 ..., respectively, each to become an element datum of the output data series Y of the pipeline circuit 3000, and stored into the Z register 103 at the respectively next timings t5, t10, t11, t12, t17 ... Here, the intervals of the output timings of the valid data a 2 , a 5 , a 6 , a 10 , a 13 , ... among the elemental data of the input data series A = (a 1 , a 2 , a 3 , ...) are 4xk+1 timing cycles (k is an integer), such as 5 (= 4 x 1 + 1) timing cycles between the data a 2 and a 5 , 1 (= 4 x 0 + 1) timing cycle between the data a 5 and a 6 , 1 timing cycle between the data a 6 and a 10 , 5 timing cycles between the data a 10 and a 13 , ... If the pipeline circuit 3000 is used as the pipeline circuits 901 and 902 in FIG. 8, said Z register 103 will correspond to the input registers RIA and RIB. Now will be described with reference to the time chart of FIG. 12 an example of the operation of the pipeline circuit 902 when a reference timing cycle "1" of the input crossbar 903 is assigned to the input register RIA, another reference timing cycle "3" of same, to the input register RIB, and timing t5 shown in FIG. 11 (the timing at which the data a 2 is stored into the Z register 103, i.e. the input register RIA) coincides with the crossbar reference timing "1" (namely the operation shown in FIG. 11 is that of the pipeline circuit 901). Referring now to FIG. 12, at timings before timing t0, a selection signal S B varies one timing cycle ahead of the crossbar reference timing. Thus, if the first valid datum is inputted (accompanied by the input indicating signal T (= 1)) in this state, the valid datum will be stored into the Z register 103 (i.e. the input register RIB) when the crossbar reference timing is "1". Since the crossbar reference timing of "3" is assigned to the input register RIB whose inputs are the data series B as stated above, the operating timing has to be shifted. If, for instance, a dummy input indicating signal T = 1 is inputted twice at timings preceding the inputting of the first valid datum, the pipeline circuit 902 can store the first valid datum into the input register RIB when the crossbar reference timing is "3". Thus, referring to FIG. 12, by inputting the dummy input indicating signal T = 1 at timings t2 and t3, the pipeline circuit 902 will be standing by at timing t4 in a state one timing cycle behind the crossbar reference timing. If, in that state, the input data series B (= b 1 , b 2 , b 3 , ...) and the input indicating signals T (= 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 1, ...) corresponding to the data are entered from timing t5 on, the pipeline circuit 902 will operate in the same manner as the pipeline circuit described with reference to FIG. 2, and data b 3 , b 4 , b 5 , b 7 , b 8 , ... are stored into the fourth register, which also is an output register of the pipeline circuit 902, at timings t10, t11, t12, t13, t14 ..., respectively, and into the Z register, i.e. the input register RIB, at the respectively next timings t11, t12, t13, t14, t15, ... The data entered into the input registers RIA and RIB by the operations illustrated in FIGS. 11 and 12 are further entered into the banks BANK1, BANK2, BANK3 and BAND4 of the memory 904 by the operation shown in the time chart of FIG. 4. As stated above, a reference timing cycle of "1" is assigned to the input register RIA, and one of "3" to the input register RIB. The output register ROR1 selects and enters an output datum of the input register RIA when the reference timing cycle is "1"; stores it when the cycle is "2"; selects and enters an output datum of the input register RIB while holding the preceding datum when the cycle is "3"; stores it when the cycle is "4"; selects and enters another output datum of the input register RIA while holding the preceding datum when the cycle is again "1"; stores it when the cycle is again "2", ......, and repeats these same operations in the four timing cycles. As also described above, the output register ROR2 operates in the same manner as the output register ROR1 except that the former is one timing cycle behind the latter. Thus, it repeats in four timing cycles the operations of selecting and entering an output datum of the input register RIA, storing it at the next timing when the reference timing cycle is "2", selecting and entering an output datum of the input register RIB, and storing it at the next timing when the reference timing cycle is "4". The output register ROR3 operates in the same manner as the output register ROR2 except that the former is another timing cycle behind the latter, and this correspondingly applies to the output register ROR4. As a result of these operations, as shown in FIG. 13, the datum a 2 stored into the input register RIA at timing t5 is stored into the output register ROR1 at timing t6 when the reference timing cycle is "1", the datum a 5 stored into the input register RIA at timing t10 is stored into the output register ROR2 at timing t11 when the reference timing cycle is "2"; and the data a 2 and b 3 stored into the input registers RIA and RIB at timing t11 are stored into the output registers ROR3 and ROR1, respectively, at timing t12 when the reference timing cycle is "3". Similar operations are repeated thereafter, and the data a 2 , b 3 , b 8 , a 13 ... are entered in the bank BANK1 of the memory via the output register ROR1, the data a 5 , b 4 , ... are entered into the bank BANK2 of the memory via the output register ROR2, the data a 6 , b 5 , ... are entered into the bank BANK3 of the memory via the output register ROR3, and the data a 10 , b 7 , ... are entered into the bank BANK4 of the memory via the output register ROR4. To consider here a serial data D (= d 1 , d 2 , d 3 , d 4 , d 5 , ... = a 2 , a 5 , a 6 , a 10 , a 13 , ...) comprising only valid ones out of the data series A (= a 1 , a 2 , a 3 , ...) and a data series F (= f 1 , f 2 , f 3 , f 4 , f 5 , ... = b 3 , b 4 , b 5 , b 7 , b 8 , ...) comprising only valid ones out of the data series B (= b 1 , b 2 , b 3 , ...), it is seen that the 4xk+1-th (k is an integer) data d 1 (= a 2 ), f 1 (= b 3 ), d 5 (= a 13 ), f 5 (= b 8 ), ... of the data series D and F are entered into the bank BANK1 of the memory; the 4xk+2-th (k is an integer) data d 2 (= a 5 ), f 2 (=b 4 ), ... of the data series D and F, into the bank BANK 2 of the memory; the 4xk+3-th data d 3 (= a 6 ), f 3 (= b 5 ), ... of the data series D and F, into the bank BANK3 of the memory; and the 4xk+4-th data d 4 (= a 10 ), f 4 (= b 7 ), ... of the data series D and F, into the bank BANK4 of the memory. Thus it is seen that the pipeline circuit according to the present invention is effective for adjusting the timing to supply data, even if the input data include invalid data, to an interleave type processing apparatus in a sequence for valid data alone. FIG. 14 is a block diagram of a fourth preferred embodiment of the present invention, where the advantage of the pipeline circuit according to the invention is increased by having not only the input serial data A but also the input indicating signals T, as referred to in the third embodiment shown in FIG. 10, inputted to a data holding circuit. In FIG. 14, the same reference numerals as in FIG. 10 denote respectively the same constituent elements. Referring to FIG. 14, a pipeline circuit 6000 has input indicating signals T and a serial data A (= a 1 , a 2 , ..., a m ), and supplies output indicating signals H and a data series Y. The data holding circuit 602 receives the inputting of a selection signal S from a selection signal generating circuit 101, decoders it with a decoder DCD into selection signals S 1 , S 2 , S 3 and S 4 for four stages of data holding means R1″, R2″, R3″ and R4″, respectively, and stores data P, each of which consists of a pair of one of the data A and an input indicating signal T corresponding to that datum, into one of the four-stage data holding means R1″, R2″, R3″ and R4″. If, for instance, the selection signal S 3 out of the selection signals S 1 , S 2 , S 3 and S 4 is valid, the data P will be stored into the data holding means R3″, though the data P will be invalidated and not stored into the data holding means R3″ if the input indicating signal indicates invalidity (logical "0" for instance). The data P stored in the data holding means R3″ when the input indicating signal T indicates validity (logical "1" for instance) are stored into the data holding means R4″ one timing cycle later to become the output data of the data holding circuit 602, i.e. of the pipeline circuit 6000. There are a Z register 603 and an E register 604 for respectively storing output data Y, which correspond to the input data A of the output data of the data holding circuit 602, and data H corresponding to the input indicating signals T of same, and outputting them as data Z and E. As the data Y outputted from the data holding circuit 602 at the timings at which the output data H, namely the output data E of the E register 604 indicate validity, i.e. the output data Z of the Z register 603, are always valid, the data H can be used as control signals for the data Y (for instance as write enable signals or the like) in another circuit downstream. Other parts of the pipeline circuit 6000 are equivalent to those of the pipeline circuit 3000 of FIG. 10. FIG. 15 is a block diagram of a fifth preferred embodiment of the present invention, where the advantage of the pipeline circuit according to the invention is increased by inputting not only the input serial data A and the input indicating signals T, as referred to in the third embodiment shown in FIG. 10, but also a selection signal initial value S0 and an initial value setting indicating signal ST. Equivalent constituent elements to those in FIG. 10 are denoted by respectively the same reference numerals. Referring to FIG. 15, a selection signal generating circuit 303, having the selection signal initial value S0, the initial value setting indicating signal ST and the input indicating signal T as inputs, outputs the selection signal initial value S0 as the selection signal S of the next timing when the initial value setting indicating signal ST indicates validity; generates and outputs the selection signal indicating the value next to what was indicated by the preceding selection signal S out of the four periodic values 1, 2, 3, 4, 1, 2, ... when both the initial value setting indicating signal ST and the input indicating signal T indicate invalidity; and holds the value indicated by the preceding selection signal S when the initial value setting indicating signal ST and the input indicating signal T respectively indicate invalidity and validity. The selection signal generating circuit 303 referred to above, as illustrated, can be realized with a cycle counter CNT2 having a three-input one-output selecting circuit SE31 to whose first, second and third stage input are respectively supplied the selection signal initial value S0, the output of a +1 circuit AD and the current value of the selection signal S; a gate G31 which provides the initial value setting indicating signal ST to the first stage of the selecting circuit SE31 and at the same time generates its inverted signal; a gate G32 which outputs the input indicating signal T and its inverted signal; a gate G33 which provides the logical product of the inverted signal of the initial value setting indicating signal ST and that of the input indicating signal T to the second stage of the selecting circuit SE31; and a gate G34 which provides the logical product of the inverted signal of the initial value setting indicating signal ST and the input indicating signal T to the third stage of the selecting circuit SE31. This cycle counter CNT2 varies the value of the selection signal in synchronism with the timing cycle by selecting the value of the selection signal initial value S0 when the initial value setting indicating signal ST indicates "1", the value "S+1" when both the initial value setting indicating signal ST and the input indicating signal T indicate "0", or the value "S" when the initial value setting indicating signal ST indicates "0" and the input indicating signal T indicates "1". This selection signal S can indicate one of four values, 1, 2, 3 and 4. Other parts of the pipeline circuit 7000 are equivalent to those of the pipeline circuit 3000 of FIG. 10. The pipeline circuit 7000 described above, if used, for instance, as the pipeline circuit 902 described with reference to FIGS. 12 and 8, can adjust the timing of the selecting signal S, so that the first valid datum can be stored into the input register RIB when the crossbar reference timing is "3", by inputting a value one timing cycle behind the crossbar reference timing as the selection signal initial value S0 together with the initial value setting indicating signal ST. Now referring to FIG. 16, a pipeline circuit 2000 has input indicating signals T and a serial data A (= a 1 , a 2 , ..., a m ), and outputs a serial data Y. The data holding circuit 202 receives the inputting of a selection signal S from a selection signal generating circuit 101, decodes it with a decoder DCD1 into selection signals S 1 , S 2 , S 3 and S 4 for four stages of data holding means R1, R2, R3 and R4″, respectively, and stores input data A into one of the four-stage data holding means R1, R2, R3 and R4″. If, for instance, the selection signal S 3 out of the selection signals S 1 , S 2 , S 3 and S 4 is valid (logical "1" for instance), the data A will be stored into the data holding means R3. If, however, the selection signal S 4 is invalidated when the output indicating signal from an indicating signal holding circuit 203 is invalid (logical "0" for example), the data A will not be stored into the data holding means R4″ and invalidated instead. The data A stored in the data holding means R3 are stored into the data holding means R4 one timing cycle later to be supplied as the output data of the data holding circuit 202, i.e. the output data Y of the pipeline circuit 2000. If, however, the output indicating signal V one timing cycle later than the timing at which the data A were stored into the data holding means R3 indicates invalidity, the output data of the data holding means R3 will not be stored into the data holding means R4 and be invalidated instead. The data holding means R2, as illustrated, can be realized with a register RG2 having a two-input one-output selecting circuit SE12 to whose first and second stage inputs are respectively supplied the output of the data holding means R1 and the input data A, and a gate G12 which provides the inverted signal of the selection signal S 2 to the first stage of the selecting circuit SE12 and at the same time the uninverted selection signal S 2 to the second stage of the selecting circuit SE12. It selects and stores the data A when the selecting signal S 2 is valid or the output data of the data holding means R1 when the selection signal S 2 is invalid (logical "0"). The data holding means R3 like the data holding means R2, can be realized with registers RG3 having two-input one-output selecting circuits SE13 to whose first and second stage inputs are supplied the outputs of the preceding-stage data holding means R2 and the input data A, respectively, and a gate G13 which provides the inverted signal of the selection signal S 3 to the first stage of the selecting circuit SE13 and at the same time the uninverted selection signal S 3 to the second stage of the selecting circuit SE13. The data holding means R1 can be realized with a register RG1 having a selecting circuit SE11 which outputs the data A when the selection signal S 1 is valid and stores the data A through this selecting circuit SE11. The data holding means R4 can be realized with a register RG4 having a two-input one-output selecting circuit SE14 to whose first and second stage inputs are respectively supplied the output of the preceding-stage data holding means R3 and the input data A; a gate G14 which supplies the selection signal S 4 and its inverted output; a gate G19 which obtains the logical product of the output indicating signal V and the inverted output of said selection signal and supplies the output to the first stage of the selecting circuit SE14, and a gate G18 which obtains the logical product of the selection signal S 4 and the output indicating signal V and supplies the output to the second stage of the selecting circuit SE14. When the selection signal S 4 is valid (logical "1") and the output indicating signal V is also valid (logical "1"), the output of the gate G18 is validated, and the second stage of the selecting circuit SE14 is selected, so that the data A are stored into the register RG4; when the selecting signal S 4 is invalid (logical "0") and the output indicating signal V is valid, the output of the gate G19 is validated and the first stage of the selecting circuit SE14 is selected, so that the output data of the data holding means R3 are stored into the register RG4; or when the output indicating signal V is invalid, nothing is stored and the input data are invalidated (all the bits are "0" for instance). The selection signal generating circuit 101, when the input indicating signal T entered corresponding to the data A indicates invalidity (logical "0"), generates and outputs a selection signal S indicating the value next to that indicated by the preceding selection signal S out of four periodic values 1, 2, 3, 4, 1 and 2, ... For instance, if an input indicating signal T = 0 is inputted when the selection signal S indicates "1", the selection signal S will indicate "2" at the next timing. Similarly, if an input indicating signal T = 0 is inputted when the selection signal S indicates "2", the selection signal S will indicate "3" at the next timing; if an input indicating signal T = 0 is inputted when the selection signal S indicates "3", the selection signal S will indicate "4" at the next timing, and if an input indicating signal T = 0 is inputted when the selection signal S indicates "4", the selection signal S will indicate "1" at the next timing. Conversely, if the input indicating signal T indicates validity (logical "1"), the selection signal generating circuit 101 will hold the value indicated by the preceding selection signal S. If, for instance, an input indicating signal T = 1 is inputted when the selection signal S indicates "1", the selection signal S will indicate "1" at the next timing, too. The selection signal generating circuit 101 referred to above, as illustrated, can be realized with a cycle counter CNT1 having a two-input one-output selecting circuit SE21 to whose first and second stage inputs are respectively supplied the output of a +1 circuit AD and the current value of the selection signal S, and a gate G21 which provides the inverted signal of the input indicating signal T to the first stage of the selecting circuit SE21 and at the same time the uninverted input indicating signal to the second stage of the selecting circuit SE21. This cycle counter CNT1 varies the value of the selection signal in synchronism with the timing cycle by selecting the value "S+1", which is the output of the +1 circuit AD, when the input indicating signal T indicates "0", or the value "S" when the input indicating signal indicates "1". This selection signal S can indicate one of four values, 1, 2, 3 and 4. The indicating signal holding circuit 203 receives the inputting of the selection signal S, from which it generates with a decoder DCD2 selection signals S 1 , S 2 and S 3 for three stages of indicating signal holding means F1, F2 and F3, respectively, and a selection signal S 4 for a selecting circuit SE34 for supplying the output indicating signal V, and decides whether to store the input indicating signal T into one of the three-stage indicating signal holding means F1, F2 and F3 or to supply it as the output indicating signal V. If the selection signal S 3 , for instance, out of the selection signals S 1 , S 2 , S 3 and S 4 is valid, the input indicating signal T is stored into the indicating signal holding means F3. The input indicating signal T stored into the indicating signal holding means F3 is supplied one timing cycle later from the selecting circuit SE34 as the output indicating signal V. If the selection signal S 4 out of the selection signals S 1 , S 2 , S 3 and S 4 is valid, the input indicating signal T will be directly supplied as the output indicating signal V from the selecting circuit SE34. The indicating signal holding means F2, for instance as illustrated, can be realized with a register RG12 having a two-input one-output selecting circuit SE32 to whose first and second stage inputs are respectively supplied the output of the preceding-stage indicating signal holding means F1 and the input indicating signal T, and a gate G31 which provides the inverted signal of the selection signal S 2 to the first stage of the selecting circuit SE32 and at the same time the uninverted selection signal S 2 to the second stage of the selecting circuit SE32. It selects and stores the input indicating signal T when the selection signal S 2 is valid (logical "1") or the output data of the indicating signal holding means F1 when the selection signal S 2 is invalid (logical "0"). The indicating signal holding means F3, like the indicating signal holding means F2, can be realized with a register RG13 having a two-input one-output selecting circuit SE33 to whose first and second-stage inputs are supplied the output of the preceding-stage indicating signal holding means F2 and the input indicating signal T, respectively, and a gate G32 which provides the inverted signal of the selection signal S 3 to the first stage of the selecting circuit SE33 and at the same time the uninverted selection signal S 3 to the second stage of same. The indicating signal holding means F1 can be realized with a register RG11 having a selecting circuit SE31 which outputs the input indicating signal T when the selection signal S 1 is valid and stores the input indicating signal T through this selecting circuit SE31. Further, a gate G33 supplies the inverted signal of the selection signal S 4 to the first stage of a selecting circuit SE34 and at the same time the uninverted selection signal S 4 to the second stage of same. The selecting circuit SE34 supplies the output of the indicating signal holding means F3 as the output indicating signal V when the first stage is selected by the gate G33 or the input indicating signal T as the output indicating signal V when the second stage is selected. The operation of the pipeline circuit 2000 will be described below with reference to the time chart of FIG. 17, in which said registers RG1 to RG4 in the data holding means R1, R2, R3 and R4 are represented by first, second, third and fourth registers, respectively, and a register which receives the inputting of and stores the output data Y of the pipeline circuit 2000 and outputs them as data Z is represented by a Z register 10B. In FIG. 17, input indicating signals T corresponding to the input data series A = (a 1 , a 2 , a 3 , ...) are supposed to be (0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0 and 0, ...). Thus a 2 , a 5 , a 6 , a 10 , and a 13 , ... are valid data and, conversely, a 1 , a 3 , a 4 , a 7 , a 8 , a 9 , a 11 , a 12 , a 14 , a 15 , a 16 and a 17 , ... are invalid data. Further, the timing at which the first elemental datum a 1 of the input data series A is entered is supposed to be t1, and the selection signal S at that time, to indicate "2". Before the datum a 1 is entered, i.e. before timing t1, the selection signal S periodically varies to indicate one or another of four recurring values, 1, 2, 3, 4, 1, 2, 3, 4 and 1, ... until it indicates "2" at timing t1. Referring to FIG. 17, the datum a 1 inputted at timing t1 is entered into the second register RG2 and stored at the next timing t2. The selection signal S at timing t2 indicates "3", the value next to that of the selection signal S (= 2) of timing t1 in response to the input indicating signal T (= 0) at the preceding timing t1. Then, the datum a 2 inputted at timing t2 is entered into the third register RG3 in response to the selection signal S (= 3) at that time and stored at the next timing t3. The datum a 1 stored into the second register RG2 at timing t 2 is not stored into the third register RG3 and instead invalidated at timing t3. The selection signal S at timing t3 holds the selection signal S (= 3) of timing t2 in response to the input indicating signal T (= 1) at the preceding timing t 2 . Meanwhile, the input indicating signal T (= 1) of timing t2 is inputted to the register RG13 in response to the selection signal S (= 3) at that time and stored at the next timing t3. As the selecting circuit SE34 selects the output of the register RG13 in response to the selection signal S (= 3 ≠ 4) at timing t3, the output indicating signal V is validated (logical "1"). In response to the selection signal S (= 3) of timing t3, the output datum a 2 of the third register RG3 is entered into the fourth register RG4, and stored at the next timing t4. Further, the datum a 3 entered at timing t3 is entered into the third register RG3 in response to the selection signal S (= 3) at that time and stored at the next timing t4. The selection signal S at timing t4, in response to the input indicating signal T (= 0) of timing t3 and the selection signal of "3", indicates the next value "4". The datum a 4 entered at timing t4 is not entered into the fourth register RG4 and is invalidated instead because the selection signal S and input indicating signal T at that time are "4" and "0", respectively. The selection signal S at timing t5, in response to the input indicating signal T (= 0) and the selection signal (= 4) of timing t4, indicates the next value "1". Similar operations are repeated at and after timing t5, and into the fourth register RG4, which also is the output register of the pipeline circuit 2000, are stored the data a 2 , a 5 , a 6 , a 10 , a 13 , ... at timings t4, t9, t10, t11, t16 ..., respectively, each to become an element datum of the output data series Y of the pipeline circuit 2000, and stored into the Z register 103 at the respectively next timings t5, t10, t11, t12, t17 ... Here, the intervals of the output timings of the valid data a 2 , a 5 , a 6 , a 10 , a 13 , ... among the elemental data of the input data series A = (a 1 , a 2 , a 3 , ...) are 4xk+1 timing cycles (k is an integer), such as 5 (= 4 x 1 + 1) timing cycles between the data a 2 and a 5 , 1 (= 4 x 0 + 1) timing cycle between the data a 5 and a 6 , 1 timing cycle between the data a 6 and a 10 , 5 timing cycles between the data a 10 and a 13 , ... If the pipeline circuit 2000 is used as the pipeline circuits 901 and 902 in FIG. 8, said Z register 103 will correspond to the input registers RIA and RIB. Now will be described with reference to the time chart of FIG. 18 an example of the operation of the pipeline circuit 902 when a reference timing cycle "1" of the input crossbar 903 is assigned to the input register RIA, another reference timing cycle "3" of same, to the input register RIB, and timing t5 shown in FIG. 17 (the timing at which the data a 2 is stored into the Z register 103, i.e. the input register RIA) coincides with the crossbar reference timing "1" (namely the operation shown in FIG. 17 is that of the pipeline circuit 901). Referring now to FIG. 18, at timings before timing t0, a selection signal S B varies one timing cycle ahead of the crossbar reference timing. Thus, if the first valid datum is inputted (accompanied by the input indicating signal T (= 1)) in this state, the valid datum will be stored into the Z register 103 (i.e. the input register RIB) when the crossbar reference timing is "1". Since the crossbar reference timing of "3" is assigned to the input register RIB whose inputs are the data series B as stated above, the operating timing has to be shifted. If, for instance, a dummy input indicating signal T (= 1) is inputted twice at timings preceding the inputting of the first valid datum, the pipeline circuit 902 can store the first valid datum into the input register RIB when the crossbar reference timing is "3". Thus, referring to FIG. 18, by inputting the dummy input indicating signal T (= 1) at timings t2 and t3, the pipeline circuit 902 will be standing by at timing t4 in a state one timing cycle behind the crossbar reference timing. If, in that state, the input data series B (= b 1 , b 2 , b 3 , ...) and the input indicating signals T (= 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0 and 1, ...) corresponding to the data are entered from timing t5 on, the pipeline circuit 902 will operate in the same manner as the pipeline circuit described with reference to FIG. 17, and data b 3 , b 4 , b 5 , b 7 and b 8 , ... will be stored into the fourth register, which also is an output register of the pipeline circuit 902, at timings t10, t11, t12, t13 and t14 ..., respectively, and into the Z register, i.e. the input register RIB, at the respectively next timings t11, t12, t13, t14 and t15, ... The data entered into the input registers RIA and RIB by the operations illustrated in FIGS. 17 and 18 are further entered into the banks BANK1, BANK2, BANK3 and BANK4 of the memory 904 by the operation shown in the time chart of FIG. 19. As stated above, a reference timing cycle of "1" is assigned to the input register RIA, and one of "3" to the input register RIB. The output register ROR1 selects and enters an output datum of the input register RIA when the reference timing cycle is "1"; stores it when the cycle is "2"; selects and enters an output datum of the input register RIB while holding the preceding datum when the cycle is "3"; stores it when the cycle is "4"; selects and enters another output datum of the input register RIA while holding the preceding datum when the cycle is again "1"; stores it when the cycle is again "2", ......, and repeats these same operations in the four timing cycles. As also described above, the output register ROR2 operates in the same manner as the output register ROR1 except that the former is one timing cycle behind the latter. Thus, it repeats in four timing cycles the operations of selecting and entering an output datum of the input register RIA, storing it at the next timing when the reference timing cycle is "2", selecting and entering an output datum of the input register RIB, and storing it at the next timing when the reference timing cycle is "4". The output register ROR3 operates in the same manner as the output register ROR2 except that the former is another timing cycle behind the latter, and this correspondingly applies to the output register ROR4. As a result of these operations, as shown in FIG. 19, the datum a 2 stored into the input register RIA at timing t5 is stored into the output register ROR1 at timing t6 when the reference timing cycle is "1", the datum a 5 stored into the input register RIA at timing t10 is stored into the output register ROR2 at timing t11 when the reference timing cycle is "2"; and the data a 6 and b 3 stored into the input registers RIA and RIB at timing tll are stored into the output registers ROR3 and ROR1, respectively, at timing t12 when the reference timing cycle is "3". Similar operations are repeated thereafter, and the data a 2 , b 3 , b 8 , a 13 , ... are entered in the bank BANK1 of the memory via the output register ROR1, the data a 5 , b 4 , ... are entered into the bank BANK2 of the memory via the output register ROR2, the data a 6 , b 5 , ... are entered into the bank BANK3 of the memory via the output register ROR3, and the data a 10 , b 7 , ... are entered into the bank BANK4 of the memory via the output register ROR4. To consider here a data series D (= d 1 , d 2 , d 3 , d 4 , d 5 , ... = a 2 , a 5 , a 6 , a 10 , a 13 , ...) comprising only valid data out of the data series A (= a 1 , a 2 , a 3 , ...) and a data series F (= f 1 , f 2 , f 3 , f 4 , f 5 , ... = b 3 , b 4 , b 5 , b 7 , b 8 , ...) comprising only valid data out of the data series B (= b 1 , b 2 , b 3 , ...), it is seen that the 4xk+1-th (k is an integer) data d 1 (= a 2 ), f 1 (= b 3 ), d 5 (= a 13 ), f 5 (= b 8 ), ... of the data series D and F are entered into the bank BANK1 of the memory; the 4xk+2-th data d 2 (= a 5 ), f 2 (= b 4 ), ... of the data series D and F, into the bank BANK2 of the memory; the 4xk+3-th data d 3 (= a 6 ), f 3 (= b 5 ), ... of the data series D and F, into the bank BANK3 of the memory; and the 4xk+4-th data d 4 (= a 10 ), f 4 (= b 7 ), ... of the data series D and F, into the bank BANK4 of the memory. Thus it is seen that the pipeline circuit according to the present invention is effective for adjusting the timing to supply data, even if the input data include invalid data, to an interleave type processing apparatus in a sequence for valid data alone. FIG. 20 is a block diagram of a seventh preferred embodiment of the present invention, where the advantage of the pipeline circuit according to the invention is increased by supplying the output indicating signal H besides the output data Y, as referred to in -he sixth embodiment shown in FIG. 16. In FIG. 20, the same reference numerals as in FIG. 16 denote respectively the same constituent elements. Referring to FIG. 20, an indicating signal holding circuit 205 receives the inputting of the selection signal S from a selection signal generating circuit 101, generates from it, with a decoder DCD2, selection signals S 1 , S 2 , S 3 , and S 4 for four stages of indicating signal holding means F1, F2, F3 and F4, respectively, and stores the input indicating signal T into one of the four-stage indicating signal holding means F1, F2, F3 and F4. If the selection signal S 3 , for instance, out of the selection signals S 1 , S 2 , S 3 and S 4 is valid, the input indicating signal T is stored into the indicating signal holding means F3. The input indicating signal T stored into the indicating signal holding means F3 is supplied one timing cycle later as the output indicating signal V, at the same time entered into the indicating signal holding means F4, and stored and outputted another timing cycle later. If the selection signal S 4 out of the selection signals S 1 , S 2 , S 3 and S 4 is valid, the input indicating signal T will be directly supplied as the output indicating signal V from a selecting circuit SE34, entered into the indicating signal holding means F4, and stored and outputted one timing cycle later. The output of the indicating signal holding means F4 is supplied as the output data H of the pipeline circuit 4000 stored into an E register 207 and, together with the output Z of a Z register 103, handed over to a succeeding circuit. Since the data Y outputted from the data holding circuit 202 at a timing at which the output data H are valid (logical "1" for example) are always valid, the data H, i.e. the output E of the E register 207, can be used as a control signal (for instance a write enable signal or the like) for the output Z of the Z register 103 in a circuit down-stream. Other parts of the pipeline circuit 4000 are equivalent to those of the pipeline circuit 2000 of FIG. 16. FIG. 21 is a block diagram of an eighth preferred embodiment of the present invention, where the advantage of the pipeline circuit according to the invention is increased by inputting not only the input data series A and the input indicating signals T, as referred to in the sixth embodiment shown in FIG. 16, but also a selection signal initial value S0 and an initial value setting indicating signal ST. Equivalent constituent elements to those in FIG. 16 are denoted by respectively the same reference numerals. Referring to FIG. 21, a selection signal generating circuit 208, having the selection signal initial value S0, the initial value setting indicating signal ST and the input indicating signal T as inputs, outputs the selection signal initial value S0 as the selection signal S of the next timing when the initial value setting indicating signal ST indicates validity; generates and outputs the selection signal indicating the value next to what was indicated by the preceding selection signal S out of the four periodic values 1, 2, 3, 4, 1 and 2, ... when both the initial value setting indicating signal ST and the input indicating signal T indicate invalidity; and holds the value indicated by the preceding selection signal S when the initial value setting indicating signal ST and the input indicating signal T respectively indicate invalidity and validity. The selection signal generating circuit 208 referred to above, as illustrated, can be realized with a cycle counter CNT2 having a three-input one-output selecting circuit SE41 to whose first, second and third stage inputs are respectively supplied the selection signal initial value S0, the output of a +1 circuit AD and the current value of the selection signal S; a gate G41 which provides the initial value setting indicating signal ST to the first stage of the selecting circuit SE41 and at the same time generates its inverted signal; a gate G42 which outputs the input indicating signal T and its inverted signal; a gate G43 which provides the logical product of the inverted signal of the initial value setting indicating signal ST and that of the input indicating signal T to the second stage of the selecting circuit SE41; and a gate G44 which provides the logical product of the inverted signal of the initial value setting indicating signal ST and the input indicating signal T to the third stage of the selecting circuit SE41. This cycle counter CNT2 varies the value of the selection signal in synchronism with the timing cycle by selecting the value of the selection signal initial value S0 when the initial value setting indicating signal ST indicates "1", the value "S+1" when both the initial value setting indicating signal ST and the input indicating signal T indicate "0", or the value "S" when the initial value setting indicating signal ST indicates "0" and the input indicating signal T indicates "1". This selection signal S can indicate one of four values, 1, 2, 3 and 4. Other parts of the pipeline circuit 6000 are equivalent to those of the pipeline circuit 2000 of FIG. 16. The pipeline circuit 6000 described above, if used, for instance, as the pipeline circuit 902 described with reference to FIGS. 18 and 8, can adjust the timing of the selecting signal S, so that the first valid datum can be stored into the input register RIB when the crossbar reference timing is "3", by inputting a value one timing cycle behind the crossbar reference timing as the selection signal initial value S0 together with the initial value setting indicating signal ST. As hitherto described, the pipeline circuit according to the present invention offers the benefits that, even if data input timings are irregular or the data include both valid and invalid ones, valid data alone can be sent out at appropriate timings by controlling the generation of selection signals for determining the duration of data holding within the pipeline circuit by using a signal indicating the validity or invalidity of input data, and that the circuit for said control can be realized with simple and small hardware.

Claims: A pipeline circuit comprising: a selection signal generating circuit (101, 501, 303) for outputting, when an input indicating signal T j-1 entered corresponding to one datum A j-1 out of a series of m input data A 1 , A 2 . ..., A m indicates invalidity, a selection signal S j indicating the value next to that indicated by the preceding selection signal S j-1 out of n periodic values 1, 2, ... , n, 1, 2, ... and, when the input indicating signal T j-1 indicates validity, a selection signal S j indicating the same value as that indicated by the selection signal S j-1 , and a data holding circuit (102, 502, 302, 602) responsive to the selection signal S j generated by said selection signal generating circuit corresponding to said datum A j for inputting, when the value indicated by the selecting signal S j is i, the datum A j to data holding means Ri, the i-th among n stages of data holding means R 1 , R 2 , ..., R n and outputting via n-i stages of data holding means R i+1 , R i+2 , ..., R n the datum A j n-i + 1 timing cycles later than the inputting of the datum A j ; where said m data A 1 , A 2 . ..., A j , ..., A m and said m input indicating signals T 1 , T 2 . ..., T j , ..., T m are entered and valid data among the m data are successively outputted at n x k + 1 (k is an integer) timing cycles. A pipeline circuit, as claimed in Claim 1 , wherein the same units of information as said m input indicating signals T 1 , T 2 , ..., T m are entered into said data holding circuit as part of said m input data A 1 , A 2 , ..., A m . A pipeline circuit as claimed in claim 1 or 2, wherein the data holding circuit, is responsive to said datum A j and said input indicating signal T j , for inputting, when the value indicated by said selecting signal S j is i, said input indicating signal T j to said data holding means Ri, the i-th among n stages of data holding means R 1 , R 2 , ..., R n , and outputting via n-i stages of data holding means R i+1 , R i+2 , ..., R n the datum A j n-i + 1 timing cycles later than the inputting of the datum A j when said input indicating signal T j indicates validity, and invalidating said datum A j when said input indicating signal T j indicates invalidity. A pipeline circuit comprising: a selection signal generating circuit (101, 208) for outputting, when an input indicating signal T j-1 entered corresponding to one datum A j-1 out of a series of m input data A 1 , A 2 . ..., A m indicates invalidity, a selection signal S j indicating the value next to that indicated by the preceding selection signal S j-1 out of n periodic values 1, 2, ..., n, 1, 2, ... and, when the input indicating signal T j-1 indicates validity, a selection signal S j indicating the same value as that indicated by the selection signal S j-1 , and an indicating signal holding circuit (203, 205) for outputting an output indicating signal V j = T j when the value indicated by the selection signal S j corresponding to the inputting of said input indicating signal T j and said selection signal S j is n or, when the value indicated by the selection signal S j is i (i < n), inputting said input indicating signal T j to indicating signal holding means F i , the i-th among the n-1 stages of indicating signal holding means F 1 , F 2 , ..., F n-1 , and outputting it via n-i-1 stages of indicating signal holding means F i+1 , F i+2 , ..., F n-1 as the output indicating signal V j n-i timing cycles later than the inputting of the input indicating signal T j , a data holding circuit (202) for inputting, when the value indicated by said selecting signal S j for the inputting of said datum A j , said selection signal S j corresponding to said datum A j and said output indicating signal V j is i (i < n), the datum A j to data holding means Ri, the i-th among n stages of data holding means R 1 , R 2 ..., R n , conveying it as a datum P via n-i-1 stages of data holding means R i+1 , R i+2 , ..., R n n-i timing cycles later than the inputting of the datum A j or, when the value indicated by said selection signal S j is n, conveying the datum A j as the datum P to said n-th data holding means R n and, when said output indicating signal V j indicates invalidity, invalidating the input to said n-th data holding means R n or, when said output indicating signal V j indicates validity, conveying said datum P to said n-th data holding means R n and outputting said datum P 1 timing cycle later; where said m data A 1 , A 2 . ..., A j , ..., A m and said m input indicating signals T 1 , T 2 . ..., T j , ..., T m respectively corresponding to said data are entered and valid data among the m data are successively outputted at n x k + 1 (k is an integer) timing cycles.

Inventors: FUJIWARA YOSHIFUMI, FURUI TOSHIYUKI, ISHIZUKA AKIRA, FUJIWARA, YOSHIFUMI, FURUI, TOSHIYUKI, ISHIZUKA, AKIRA, FUJIWARA, YOSHIFUMI C/O NEC CORPORATION, FURUI, TOSHIYUKI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: G06F5
IPC codes: G06F15