DIGITAL CLIPPING CIRCUIT WITH SOFT CLIP CHARACTERISTICS

Abstract: In a digital clipping circuit for clipping a digital input signal according to the present invention, a comparator (12) compares the digital input signal with a reference signal, and outputs a first comparison signal when the level of the digital input signal is higher than that of the reference signal, and outputs a second comparison signal when the level of the digital input signal is lower than that of the reference signal. A selector (13) selects the reference signal when the selector (13) receives the first comparison signal, and selects the digital input signal when the selector (13) receives the second comparison signal. A compensation signal generator (15, 16) receives the first comparison signal, and outputs a compensation signal for compensat­ ing the reference signal selected by the selector (13). A synthesizer (17) synthesizes the reference signal selected by the selector (13), and the compensation signal output from the compensation signal generator (15, 16), thereby to produce a compensated output signal.

Description: The present invention relates to a digital clipping circuit, and, in particular, to a video signal clipping circuit used, for example, in a digital video tape recorder (hereinafter, referred to as "digital VTR"). Recently, a digital recording system, which eliminates drawbacks of an analog recording system and achieves high image quality, has been employed in a conventional video tape recorder. A video tape recorder employing such a system is called a digital VTR. A signal processing circuit used in the digital VTR comprises a Y-C separation circuit for obtaining a luminance signal (Y signal) and a chrominance signal (C signal) from an NTSC signal, a pre-emphasis circuit for pre-emphasizing the luminance signal, and a digital clipping circuit for clipping a spike produced by the pre-emphasis at a predetermined level. One example of a conventional digital clipping circuit comprises a comparator for comparing an input signal and a reference signal (clip level signal), and a switching circuit for selecting one of the input signal and the reference signal. When the level of the input signal is above the clip level, the input signal is clipped at the clip level and the clipped signal is output from the switching circuit. When the level of the input signal is equal to or lower than a clip level, the input signal is output from the switching circuit with no level changes. The clipped signal loses a soft-clip characteristic (or a rounded portion) and has a so-called hard-clip waveform. Thus, in the conventional digital clipping technique, the output signal is degraded. As an example, prior art document US-A-4 326 223 discloses an apparatus for reproducing a video signal which is recorded on a recording medium with a luminance component thereof non-linearly pre-emphasized and the signal portions thereof greater than a predetermined level being clipped. This apparatus comprises a non-linear de-emphasizing circuit which non-linearly attenuates the reproduced luminance component in a manner substantially complementary to the amount of the non-linear pre-emphasis, a gain control element in the form of a transistor, having a variable gain, and a compensating circuit for substantially recovering the clipped signal portions upon reproduction of the video signal, and in which the compensating circuit increases the gain of the gain control element for the portions of the reproduced luminance component at the predetermined level. The compensating circuit includes a switching diode connected at one terminal to the collector of the gain control transistor and to a reference voltage at the other terminal such that the diode is made conductive for the portions of the reproduced luminance component of the video signal at the predetermined level to increase the gain of the transistor at the collector thereof. Further, prior art document US-A-4 658 305 describes a video signal recording and reproducing apparatus which comprises a circuit for separating a luminance and carrier chrominance signals from a color video signal and for recording on and reproducing from a recording medium a multiplexed signal. A frequency modulated luminance signal and a frequency converted carrier chrominance signal which is frequency-converted into a low frequency band are multiplexed. A reproduced luminance signal, and a reproduced carrier chrominance signal which is in an original frequency band and has an original phase by subjecting a reproduced frequency converted carrier chrominance signal to a signal processing are obtained. A de-emphasis circuit is supplied with the reproduced luminance signal and/or an input signal or the reproduced carrier chrominance signal of the processing circuit, for relatively attenuating the level of a high-frequency component in a temporal frequency of the reproduced luminance signal and/or an input signal or the reproduced carrier chrominance signal of the processing circuit compared to a low-frequency component. A mixer mixes the reproduced luminance signal and the reproduced carrier chrominance signal so as to produce a reproduced color video signal. There has been a great demand for a digital clipping circuit having a soft-clip characteristic, to prevent degradation of an output signal. It is an object of the present invention to provide a digital clipping circuit wherein degradation of an output signal can be minimized. To solve this object the present invention provides a digital clipping circuit as specified in claim 1. The foregoing aspects and other features of the invention will now be explained in the following description in connection with the accompanying drawings wherein: Fig. 1 is a circuit diagram showing a first embodiment of the digital clipping circuit according to the present invention; Fig. 2 is a circuit diagram showing a second embodiment of the digital clipping circuit wherein a bit-shift circuit is applied to Fig. 1; Fig. 3 is a circuit diagram showing a third embodiment of the digital clipping circuit according to the invention; and Fig. 4 is a circuit diagram showing a fourth embodiment of the digital clipping circuit according to the invention, which is constituted by combining the first embodiment of Fig. 1 and the third embodiment of Fig. 3. Fig. 1 is a circuit diagram showing a first embodiment of the digital clipping circuit according to the present invention. Input terminal 11 is connected to one input terminal of comparator 12 and to one of the fixed contacts of switch 13. Input terminal 14 is connected to the other input terminal of comparator 12 and to the other fixed contact of switch 13. An output terminal of comparator 12 is connected to switch 13 and to constant generator 15. A movable contact of switch 13 is connected to adder 17. Constant generator 15 is connected to integration circuit 16, and integration circuit 16 is connected to adder 17. Adder 17 is connected to output terminal 18. The operation of the above-described circuit will now be explained. A digital signal is input to input terminal 11. Thus, the digital signal appears in each section of the circuit of Fig. 1. However, analog waveforms are shown in Fig. 1 for the sake of convenience. Digital input signal S1 supplied to input terminal 11 is input to one input terminal of comparator 12 and to one fixed contact of switch 13. Reference signal S2 is supplied to input terminal 14. Reference signal S2 is input to the other input terminal of comparator 12 and to the other fixed contact of switch 13. The level of reference signal S2 is set to a clip level at which input signal S1 is clipped. Comparator 12 compares levels L1 and L2 of signals S1 and S2, and outputs a comparison result (for example, when L1 is higher than L2, level "1" is output, and when L1 is equal to or lower than L2, level "0" is output). The comparison result is fed to switch 13 and constant generator 15. When switch 13 receives the comparison result of level "1" (i.e., input signal level L1 is higher than clip level L2), switch 13 selects reference signal S2. On the other hand, when switch 13 receives the comparison result of level "0" (i.e., input signal level L1 is equal to or lower than clip level L2), switch 13 selects input signal S1. In this manner, switch 13 outputs signal S3 which is obtained by hard-clipping input signal S1. When the comparison result of level "1" (i.e., input signal level L1 is higher than clip level L2) is supplied from comparator 12 to constant generator 15, constant generator 15 outputs constant signal S4 representative of a predetermined constant. Constant signal S4 is supplied to integration circuit 16 and is integrated therein by a predetermined time constant. More specifically, integration circuit 16 receives constant signal S4 and produces integrated signal S5, the level of which gradually increases with a time constant and then gradually decreases. Integrated signal S5 and the signal selected by switch 13 are added by adder 17. Then, adder 17 produces clipped output signal S6, the level of which gradually increases when input signal level L1 is higher than clip level L2, and gradually decreases when level L1 is equal to or lower than clip level L2. This clipped output signal is fed to output terminal 18. As seen from the above, in the first embodiment of the invention, the input signal is hard-clipped by a hard-clip circuit comprising comparator 12 and switching circuit 13, and the hard-clipped signal is added to the integrated output signal, thereby to obtain a soft-clipped signal. Since the waveform of hard-clipped signal S3 is changed to a gradually varying waveform according to the integrated output, clipped output signal S6 having a desired soft clip characteristic can be obtained. Fig. 2 is a circuit diagram showing a second embodiment of the invention. In the second embodiment, the comparison result of comparator 12 is bit-shifted by bit-shift circuit 21 to generate constant signal S4. With this structure, a clipped signal having a soft-clip characteristic can also be obtained. In Fig. 2, the elements which have already appeared in Fig. 1 are indicated by the same reference numerals. The above description has been directed to the case where an upper portion of an input signal is clipped, as shown in Fig. 1. However, when input signal S11 and reference signal S21, which have opposite polarities, are input to comparator 25, it is possible to soft-clip a lower portion of the input signal by employing a circuit structure as shown in Fig. 3. When the lower portion of the input signal is equal to or lower than a clip level, integrated signal S51 from integration circuit 28 is subtracted from hard-clipped signal S31 to obtain output signal S61. By combining this embodiment with the first embodiment, a circuit wherein an upper portion and a lower portion of an input signal are simultaneously clipped can be realized. Fig. 4 shows a circuit constituted by combining a clipping circuit for clipping an upper portion of an input signal (hereinafter, called "upper clip circuit") and a clipping circuit for clipping a lower portion of the input signal ("lower clip circuit"). In Fig. 4, signals relating to the clipping of the upper portion of the input signal, and the levels of these signals, are indicated by symbol "H", which is used in combination with the reference numerals used in Fig. 1. Signals relating to the clipping of the lower portion of the input signal, and the levels of these signals, are indicated by symbol "L". Also, signals relating to the clipping of the upper and lower portions of the input signal are indicated by symbol "HL". In Fig. 4, an upper clip circuit is constituted by comparator 12, switch 13, constant generator 15, and integration circuit 16. On the other hand, an lower clip circuit is constituted by another comparator 25, switch 26, constant generator 27, and integration circuit 28. Reference signal SL2 supplied to input terminal 29 has a reference level for the lower clipping. Switch 26 used for the lower clipping is connected at the rear stage of switch 13, so as to hard-clip the lower portion of upper-clip signal SH3. By this structure, switch 26 outputs signal SH3 which is obtained by hard-clipping the upper and lower portions of the input signal. Adder 30 adds hard-clipped signal SHL3 and integrated output signal SH5 from integration circuit 16, and subtracts integrated output signal SL5 from the sum of signals SHL3 and SH5. Thus, adder 30 outputs clipped signal SHL6 in which the upper and lower portions of the input signal are soft-clipped. As described above, the present invention can provide a digital clip circuit wherein an input signal can be soft-clipped and the signal degradation inherent in a conventional digital clipping technique can be overcome. The present invention is not limited to the above four embodiments, and various modifications and changes may be made to the invention.

Claims: A digital clipping circuit for clipping a digital input signal, comprising: means (11) for receiving a digital input signal; first comparing means (12) for comparing the digital input signal received by said receiving means (11) with a first reference signal, and outputting a first comparison signal when the level of the digital input signal is higher than that of the first reference signal, and outputting a second comparison signal when the level of the digital input signal is lower than that of the first reference signal; first selection means (13) for selecting the first reference signal when said selection means (13) receives the first comparison signal from said first comparing means (12), and for selecting the digital input signal when said selection means (13) receives the second comparison signal therefrom; characterized in that said circuit further comprises: first compensation signal generating means (15, 16) comprising a first constant generating circuit (15) for receiving the first comparison signal and generating a signal representative of a predetermined constant, and a first integration circuit (16) for receiving the signal representative of the predetermined constant generated from said first constant generating circuit (15) and producing a corresponding integrated first compensation signal for compensating the first reference signal selected by said first selection means (13); and synthesizing means (17; 30) for synthesizing the first reference signal selected by said first selection means (13), and the first compensation signal output from said first compensation signal generating means (15, 16), thereby to produce a compensated output signal. The circuit according to claim 1, characterized in that said selection means (13) includes a switch (13). The circuit according to claim 1, characterized in that said synthesizing means (17) includes an adding circuit (17). The circuit according to claim 1, characterized in that said synthesizing means (17) includes a subtracting circuit (31). A digital clipping circuit according to claim 1, characterized by: second comparing means (25) for comparing said digital input signal received by said receiving means (11) with a second reference signal, and outputting a third comparison signal when the level of the digital input signal is higher than that of the second reference signal, and outputting a fourth comparison signal when the level of the digital input signal is lower than that of the second reference signal; second selection means (26) for selecting the second reference signal when said selection means (26) receives the third comparison signal from said second comparing means (25), and for selecting the digital input signal when said selection means (26) receives the fourth comparison signal therefrom; and second compensation signal generating means (27, 28) comprising a second constant generating circuit (27) for receiving the third comparison signal and generating a signal representative of a predetermined constant, and a second integration circuit (28) for receiving the signal representative of the predetermined constant generated from said second constant generating circuit (27) and producing a corresponding integrated second compensation signal for compensating the second reference signal selected by said second selection means (26); wherein: said synthesizing means (30) synthesizes the first reference signal selected by said first selection means (13), the second reference signal selected by said second selection means (26), and the first and second compensation signals generated from said first and second compensation signal generating means (15, 16, 27, 28), thereby to produce said compensated output signal. The circuit according to claim 1 or 5, characterized in that said first constant generating circuit (15) includes a bit-shift circuit (21). The circuit according to claim 5, characterized in that said second constant generating circuit (27) includes a bit-shift circuit. The circuit according to claim 5, characterized in that each of said first and second selection means (13, 26) includes a switch (13, 26).

Inventors: OHNO, TATSUYUKI C/O PATENT DIVISION
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H03G11
IPC codes: H04N5, G11B20, H03G11