Coherent PSK demodulator using bit error rate and S/N ratio to establish synchronization

Abstract: In a coherent M-ary PSK demodulator, an M-ary PSK detector (1) demodulates a received M-ary PSK modulated convolutional code with a carrier recovered by a voltage-controlled oscillator to produce first and second channels of demodulated convolutional codes. A convolutional decoder (7) decodes the signals of the first and second channels while correcting bit errors. An error rate detector is provided for detecting when the number of such errors occurring during a specified period of time is smaller than a predetermined value and generates a signal indicating that the convolutional decoder (7) is synchronized with the demodulated signals. The power levels of signal and noise components of the demodulated channels are detected by a power detector (11). In a frequency control circuit, a series of VCO control signals of a different value are generated as candidates for precise synchronization in response to the signal from the error rate detector in order to synchronize the PSK detector (1) successively at the candidate frequencies, and signal-to-noise ratios are successively derived from the outputs of the power detector (11). A maximum value of the derived signal-to-noise ratios is then detected and one of the candidate VCO control signals which corresponds to the detected maximum signal-­ to-noise ratio is adopted as a valid VCO control signal.

Description: The present invention relates generally to coherent PSK (phase shift keying) demodulators for M-ary PSK modulated convolutional codes, and more specifically, the present invention relates to a technique for recovering a carrier from a received PSK modulated convolutional code by precisely establishing synchronization with the received signal. According to coherent detection which is used to demodulate a received M-ary PSK modulated convolutional code, the received signal is mixed with a local carrier to produce I- and Q-channel signals for coupling to a convolutional decoder and phase comparison is made between the demodulated signal and the local carrier to establish carrier synchronization. As described in Japanese Provisional Patent Publication (Tokkaisho) 59-12654, synchronization is established between the frequency of the recovered carrier and the symbol rate of received convolutional codes by detecting the error rate of the demodulate I- and Q-channel signals and reducing the error rate below a specified value through a feedback circuit. In this publication, a convolutional encoder is coupled to a convolution decoder. The output of the convolutional encoder and one input of the convolutional decoder are supplied to a correlator to determine their correlation. Since the output of the convolutional encoder is a replica of the original codeword, the correlator produces a signal which increases in amplitude with the error rate of the signal at the input of the convolutional decoder. A maximum detector is connected to the correlator to control the phase relation of the input signals of the convolutional decoder when the error rate exceeds a specified value. However, the prior art technique tends to establish carrier synchronization even when the carrier frequency is not precisely coherent with the symbol rate of the received signal. Under this condition, the demodulator is said to be in a "quasi-coherent" state. As an example of this quasi-coherent state, consider a BPSK system in which a 7-stage shift register S and exclusive OR gates A1 and A2 are used as a convolutional encoder as shown in Fig. 1. The bits stored in the first, second, third, fourth and seventh stages of the shift register S are supplied to exclusive OR gate A1 to produce a code word "171", and the bits stored in the first, third, fourth and sixth stages are supplied to exclusive OR gate A2 to produce a code word "133." Let the input data stream at the input of a convolutional encoder be denoted by D n (D n = ±1) and let the output data stream from the convolutional encoder be denoted by C n 171 and C n 133 , then the following relations hold: C n 171 = D n × D n-1 × D n-2 × D n-3 × D n-6 C n 133 = D n × D n-2 × D n-3 × D n-5 D n-6 where, all binary data are represented by +1 and -1. If carrier synchronization is precisely established, the demodulated data streams become equal to C n 171 and C n 133 and by decoding such data stream by an error correction circuit, or convolutional decoder, the original data D n can be recovered. However, if carrier synchronization is not precise, the demodulated data streams will become C n 171′ and C n 133′ and the following relations will hold between error corrected data D' n and the original data stream D n : D' n = D n (-1) n Therefore, a decoding process properly proceeds and a decision is made that synchronization has been established. It is appropriate to discuss to some length BPSK modulation and demodulation processes for codewords C n 171' and C n 133' . Bit-parallel codewords C n 171 and C n 133 are converted to bit-serial data and supplied to a BPSK modulator producing the following data B m : At the receive end, the demodulator produces bit-serial demodulated codewords B' m which are converted to bit-parallel codewords. If the codewords B' m have the following relations with the transmit data B' m data streams C n 171' band C n 133' will result from a demodulation process. The demodulated data stream B" m will be given as follows if the frequency of the recovered carrier deviates as much as f s /4, where f s is the svmbol rate of the transmitted signal: The value B" m is equal to B' m if binary levels are used for discrimination between a valid coherent state and a quasi-coherent state. Even if the frequency of the recovered carrier deviates by as small as 1/8 of the symbol rate, a quasi-coherent state can occur. In EP-A-0 243 589, a demodulator is connected to a signal processor whose error information is supplied to a false-lock decision circuit for detecting when the demodulator is synchronized to false lock points. A sweep generator is connected to the false-lock decision circuit for sweeping the frequency of a VCO to supply a variable frequency carrier to the demodulator. The VCO frequency is swept continuously from a given lock point to the next. The process is repeated until an optimum lock point is reached. The search for the optimum lock point is made by the loop comprising demodulator, signal processing circuit, false-lock decision circuit, sweep generator and VCO. FR-A-2 614 155 discloses a Costas phase locked loop including two demodulators, a local oscillator that supplies in-phase and quadrature-phase carriers to the demodulators, respectively, and a controller that receives signals from the demodulators and supplies a sync indicating signal E when the S/N ratio at the output of the demodulator is higher than a predetermined value. It is therefore an object of the present invention to provide a coherent PSK demodulator capable of establishing a valid coherent state with a received PSK modulated convolutional code and a method for establishing synchronization between a received PSK modulated convolutional code and a recovered carrier. This object is achieved by the features of claim 1 and 4, respectively. The present invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 shows a representative convolutional encoder used in a modulator at the transmit end of a satellite communications system; Fig. 2 is a block diagram of a synchronous demodulator at the receive end of the system according to the present invention; Fig. 3 is a flowchart describing steps performed by the frequency control circuit of Fig. 2; Fig. 4 is a flowchart describing additional steps performed by the frequency control circuit of Fig. 2; and Fig. 5 is a graph representing signal-to-noise ratio plotted as a function of energy-to-noise ratio. Referring now to Fig. 2, there is shown a coherent M-ary PSK demodulator according to a preferred embodiment of the present invention. The demodulator comprises a PSK detector 1 by which a received M-ary PSK signal is demodulated into an in-phase, or I-channel signal and a quadrature signal, or Q-channel signal. The demodulated signals are supplied to a phase detector 2 where a phase difference between the I- and Q-channel signals is detected and are supplied through a loop filter 3 to a variable phase shifter 4 to introduce a variable amount of delay to a carrier supplied from a voltage controlled oscillator 5 in accordance with the detected phase difference. The I- and Q-channel signals also are supplied through a phase shifter 6 to a convolutional decoder, or forward error correction (FEC) decoder 7 such as Viterbi decoder. FEC decoder 7 includes a copy of the convolutional encoder to decode the convolutional codes of both channels to generate a replica of the original data stream as a demodulator output in a known manner. The error correction signal, which is generated for the decoding process, is supplied to an integrator 8. The output of integrator 8 will increase as the error rate of the demodulated signals increase and hence it increases as a function of the amount of deviation of the recovered carrier frequency from the symbol rate of the received signal. A threshold comparator 9 is connected to the output of integrator 8 to generate a logical-1 output when the integrator output exceeds a predetermined threshold level. The logical-1 output thus indicates that a substantial amount of bit errors exists in the demodulated signals and hence it gives an indication that VCO 5 is not in synchronization with the symbol rate of the received PSK signal. The output of threshold comparator 9 is supplied to the phase shifter 6 which may comprise a switch to establish "through" connections between the outputs of PSK detector 1 and FEC decoder 7 in the presence of a logical-0 output from the threshold comparator 9 and establish crosscoupled connections between them in response to a logical-1 output from comparator 9 so that FEC decoder 7 reestablishes synchronization with the demodulated signals. A number of techniques are available to produce such phase control signals as described in Japanese Provisional Patent Publication 59-12654. The output of comparator 9 is applied to a frequency control circuit 10 which supplies a frequency control voltage to the VCO 5. When the output of comparator 9 is at logic-0, frequency control circuit 10 interprets it as an indication that FEC decoder 7 is in synchronism with the demodulated signals and proceeds to compute the signal-to-noise ratio of the received PSK signal in a manner as will be described in detail hereinbelow. To derive signals representative of the power levels of both signal and noise components, a power detector 11 is connected to one of the outputs of PSK detector 1. Power detector 11 comprises an absolute value converter 12 which converts the Q-channel signal to a signal having an absolute value, which is averaged by an averaging circuit 13. The output of averaging circuit 13 is squared by a squaring circuit 14 to supply a signal P S representative of the power level of the signal component to frequency control circuit 10. The Q-channel output is also squared by a squaring circuit 15 whose output is averaged by an averaging circuit 16 to provide a signal P T representative of the total power level of both signal and noise components. The power representative signals P S and P T are supplied to a subtractor 17 to provide the frequency control circuit 10 with an output signal P N representative of the power level of the noise component. Frequency control circuit 10 is a microprocessor-based controller having programmed steps as shown in Fig. 3. Program execution starts with operations block 30 which directs the sweeping of frequency control voltage V by incrementing it by a predetermined amount Δ V . Exit then is to decision block 31 which checks to see if there is a logical-0 input from threshold comparator 9 indicating that FEC decoder 7 is synchronized with the demodulated signals. If the answer is negative, blocks 30 and 31 are repeated until synchronization is established in decoder 7 by the closed-loop synchronizer formed by phase shifter 6, integrator 8 and threshold comparator 9. Thus, the VCO control voltage is swept across a range of voltages in search of synchronization. If there is a logic-0 input from comparator 9, the answer is affirmative in block 31 and control proceeds to operations block 32 which directs the initialization of a variable i to one. The initialization step is followed by operations block 33 which directs the setting of the control voltage V to a voltage V i which is one of a plurality of voltage levels stored in a lookup table as corresponding to possible frequency values, or candidate lock points at which the demodulator is likely to be synchronized with the symbol rate of the incoming PSK signaL Therefore, VCO 5 is driven at one of the candidate voltages, and the demodulator is synchronized with the symbol rate of the incoming signal in a lock point which may be either false or valid. Exit then is to block 34 which directs the computing of the formula 10 log 10 (P S /P N ) using the power level signals P S and P N supplied from power detector 11 to derive the signal-to-noise ratio S/N of that lock point. The signal-to-noise ratio value S/N derived in step 34 is stored in a location of the lookup table adjacent the corresponding candidate voltage V i to form with it a data set DS (block 35). Control exits to block 36 in which the variable i is compared with a constant K representing a maximum number of the voltage levels stored in the lookup table. If i is not equal to K, exit is to block 37 which increments the variable i by one and control returns to block 33 to set the control voltage V to the next candidate by selecting one from the lookup table. In this way, the VCO frequency is successively shifted from one candidate frequency value to another so that the demodulator is successively synchronized in different lock points. When all frequencies of the candidate lock points are tested, control exits from decision block 36 to operations block 38 which directs the detecting of data set DS having a maximum value of the signal-to-noise ratios stored in the lookup table, and proceeds to block 39 to set the control voltage V to the candidate voltage V i at which the maximum signal-to-noise ratio is derived. Synchronization that occurs at the lock point having the maximum signal-to-noise ratio is interpreted as a valid lock and synchronizations at all the other lock points are interpreted as false locks. In a preferred embodiment, frequency control circuit 10 is further programmed to repeat the process of Fig. 3 as shown in Fig. 4 to determine whether the lock point detected in a manner described above is one that occurs at a maximum likelihood frequency. This program starts with an initialization step 40 which directs the setting of a variable n to one. Control exits to block 41 to execute the frequency control subroutine of Fig. 3 to derive a frequency control voltage V(1) . This voltage is stored in a memory (block 42) and control proceeds to block 43 to increment the variable n by one. The frequency control subroutine is repeated (block 44) to derive another frequency control voltage V(n) which is stored in the memory (block 45). Exit then is to decision block 46 in which any two of the stored voltages V(n) are compared with each other to detect equality therebetween. If frequency control signals having an equal value are not detected, control returns to block 43 to further increment the variable n to repeat the frequency control subroutine again to obtain another frequency control voltage V(n) for comparison with each of the stored voltage values V ( n ). The process is repeated until equality is detected between at least two stored values. When this occurs, the voltages V ( j ) having the equal value are interpreted as corresponding to a most likely frequency (where j = 1, 2, ... n ), and and control proceeds to block 47 to set the control voltage V to the most likely voltage V ( j ) with which VCO 5 is subsequently controlled. It is seen from the foregoing that valid synchronization is established when the signal-to-noise ratio of a received convolutional PSK code signal is at a maximum if the bit error rate of the signal as detected at the output of FEC decoder 7 is smaller than a predetermined value. Fig. 5 is a plot of signal-to-noise ratio of the demodulated signal as a function of the ratio of energy per bit to noise of the incoming signal for a zero frequency deviation and non-zero frequency deviations obtained from computer simulation for purposes of comparison. It is seen that significant differences exist between the curve designated Δf = 0 in which valid coherent state occurs and the curves designated Δf = f s /8, f s /4 and f s /2 in which quasi-coherent states exist (where f s indicates frequency deviation of the recovered carrier from the symbol rate of received M-ary PSK convolutional codes). The foregoing description shows only preferred embodiments of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiments shown and described are only illustrative, not restrictive.

Claims: A coherent PSK (phase shift keying) demodulator comprising PSK detector means (1) for demodulating a received PSK modulated convolutional code with a recovered carrier and producing therefrom first- and second-channel convolutional codes, carrier recovery means (2, 3, 4, 5) for generating a variable frequency carrier, detecting a phase difference between said first- and second-channel convolutional codes and controlling the phase of said variable frequency carrier according to the phase difference, convolutional decoder means (7) for decoding said first- and second-channel convolutional codes and correcting errors in said convolutional codes, error detector means (8, 9) connected to said convolutional decoder means (7) for comparing the number of said errors generated during a predetermined period of time with a threshold value, and frequency control means (10) for causing said carrier recovery means to vary the frequency of said carrier to a suboptimum value until the number of said errors becomes smaller than said threshold value, characterized in that power detector means (11) is provided for detecting power levels of a signal component and a noise component of one of said first- and second-channel convolutional codes, and in that said frequency control means (10) includes means for causing said carrier recovery means (2, 3, 4, 5) to successively vary the frequency of said carrier by discrete values from said suboptimum value to produce frequency deviations, successively deriving signal-to-noise ratios from the power levels detected by said power detector means corresponding to said frequency deviations, and causing said carrier recovery means (2, 3, 4, 5) to set the frequency of said carrier to an optimum value which corresponds to a maximum value of said signal-to-noise ratios. A coherent PSK demodulator as claimed In claim 1, characterized in that said frequency deviations correspond respectively to possible lock points at which said demodulator is likely to be synchronized to a symbol rate of said PSK signal. A coherent PSK demodulator as claimed in claim 1 or 2, characterized in that said frequency control means (10) includes means for causing said carrier recovery means to repeatedly generate a plurality of said carriers having said maximum value as candidates and detecting two of said candidates of equal frequency and causing said carrier recovery means to set the frequency of said carrier to the frequency of the detected candidates. A method for establishing synchronization between a received PSK (phase shift keying) modulated convolutional code and a recovered carrier, comprising the steps of: (a) demodulating a received PSK modulated convolutional code with a recovered carrier and producing therefrom first- and second-channel convolutional codes, (b) generating a variable frequency carrier, detecting a phase difference between said first- and second-channel convolutional codes and controlling the phase of said variable frequency carrier according to the phase difference, (c) decoding said first- and second-channel convolutional codes and correcting errors in said convolutional codes, (d) comparing the number of said errors generated during a predetermined period of time with a threshold value, and (e) varying the frequency of said carrier to a suboptimum value until the number of said errors becomes smaller than said threshold value, characterized by (f) detecting power levels of a signal component and a noise component of one of said first- and second-channel convolutional codes, and wherein the frequency of said carrier is successively varied by discrete values from said suboptimum value to produce frequency deviations, (g) successively deriving signal-to-noise ratios from the power levels corresponding to said frequency deviations, and (h) setting the frequency of said carrier to an optimum value which corresponds to a maximum value of said signal-to-noise ratios. A method as claimed in claim 4, characterized in that said frequency deviations correspond respectively to possible lock points at which synchronization to a symbol rate of said PSK signal is likely to be established. A method as claimed in claim 4 or 5, characterized by repeatedly generating a plurality of said carriers having said maximum value as candidates and detecting two of said candidates of equal frequency and setting the frequency of said carrier to the frequency of the detected candidates.

Inventors: IWASAKI MOTOYA, OTANI SUSUMU, IWASAKI, MOTOYA, OTANI, SUSUMU, IWASAKI, MOTOYA C/O NEC CORPORATION, OTANI, SUSUMU C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: H04L27
IPC codes: H04L27