METHOD FOR MAKING A SEMICONDUCTOR SUBSTRATE INCLUDING A STRAINED LAYER SUPERLATTICE STRUCTURE

Abstract: A semiconductor substrate comprising: a single-crystalline semiconductor wafer substrate; a strained layer superlattice (SLS) structure layer formed on the wafer substrate; and a compound semiconductor epitaxial layer formed on the SLS structure layer. According to the present invention, the SLS structure layer consists of pairs of a first compound semiconductor thin layer and a second compound semiconductor thin layer, the first and second thin layers having the same components in a compound system having a miscibility gap, and having different compositions outside of the miscibility gap including the limit line of the miscibility gap, respectively, at a temperature higher than that of heat-treatments applied to the compound semiconductor substrate, without a decay of the SLS structure.

Description: The present invention relates to semiconductor substrates for the production of semiconductor transistor devices or photoelectronic devices, and more particularly to a method for making such a semiconductor substrate comprising a single-crystalline semiconductor wafer substrate, a compound-semiconductor epitaxial layer and a strained layer superlattice (SLS) structure layer between the wafer layer and the epitaxial layer. An SLS structure layer is formed as a buffer layer between the semiconductor wafer substrate, such as a GaAs wafer or Si wafer, and a compound-semiconductor layer, such as an InGaP layer and GaAs layer, for the following reasons: (1) the SLS buffer layer reduces dislocations in the grown compound-semiconductor layer by preventing the extension of threading dislocations from the substrate into the compound-semiconductor layer, due to the strain field in the SLS; and (2) the SLS buffer layer allows epitaxial growth of the compound-semiconductor layer of a different lattice constant from that of the substrate by absorbing the lattice mismatch by virtue of the alternate expansion and contraction of the strained thin layers of the SLS structure layer. This means that, instead of using a single-crystalline GaAs wafer substrate, a substrate of GaAs grown on Si (GaAs/Si) can be produced using the SLS structure layers, thus making possible a larger wafer size, increased mechanical strength and thermal conductivity, and reduced costs, compared with the GaAs wafer substrate. The lattice constant of GaAs is larger than that of Si by about 4% (e.g., cf. N.El-Masry et al, "Defect Reduction in GaAs Epilayers on Si Substrate Using strained Layer Superlattices", Mat. Res. Soc. Sympo. Proc. Vol. 91, 1987, pp. 99 - 103). Furthermore, it is often necessary to form (grow) a compound-semiconductor layer having a lattice constant different from or the same as that of the wafer substrate for light-emitting devices or lasers having a desired emission wavelength, while reducing the number of crystal defects such as dislocations. A discussion of an InGaAs SLS structure lattice matched to an InP substrate, so as to give rise to very few misfit dislocations, is given in the Journal of Applied Physics, Vol. 59 (1986) pp. 2447-2450. Currently, there is a tendency to overestimate the effectiveness of the SLS buffer. In practice, although an SLS buffer uses a pair of compound-semiconductor layers having a large lattice mismatch therebetween, a compound-semiconductor epitaxial layer grown on the SLS buffer will have a high density of dislocations, five or six times larger than that of the wafer substrate, and when a graded layer is additionally grown between the wafer substrate and the SLS buffer, the compound-semiconductor epitaxial layer also has a high density of dislocations. Therefore, its effectiveness at reducing the number of dislocations in the SLS buffer is very low. To obtain the required dislocation-reducing effect, the compound-semiconductor substrate including the SLS buffer should preferably be heat-treated at a high temperature so as to anneal out excessive dislocations. A conventional SLS buffer, however, is not proof against a heat-treatment (annealing) at a high temperature, even for a short time, and a decay of the SLS structure by an interdiffusion of the alternating thin layers thereof occurs. Such diffusion is described, for instance, in the Japanese Journal of Applied Physics, Vol. 23 no. 8 (1984) pages L623-624 for an AlAs-GaAs superlattice. Therefore, although the number of dislocations is reduced, the decay of the SLS structure causes variations in the characteristics of the devices, for example an increase of a full-width at a half maximum (FWHM) of an LED, and prevents further annealing or thermal cycling improvement. It is thus desirable to provide an improved strained layer superlattice (SLS) buffer layer which is not deformed (interdiffused) by a heat-treatment at a high temperature, including annealing for reducing the number of dislocations, heating for the epitaxial growth of an additional compound semiconductor layer, or annealing after ion-implantation; it is further desirable to improve the SLS structure layer between the wafer substrate and the epitaxial layer. According to the present invention there is provided a method of making a semiconductor substrate as claimed in claim 1. It is preferable that the temperature difference is 10°C or more. The wafer substrate may be composed of a compound semiconductor (e.g., GaAs, InP, GaSb, GaP, InAs) or of silicon (Si). Compound-semiconductor systems having a miscibility gap are described in Applied Physics Letters 46(7) (1985), pages 659-661, but no mention is made here of the relationship between the compositions used, nor of any annealing treatment. The present invention will be more apparent from the description of the preferred embodiments set forth below, with reference to the accompanying drawings, in which: Fig. 1 is a pseudo-binary phase diagram of an ABC (In x Ga 1-x P) system of BC (GaP) - AC (InP); Fig. 2 is a graph showing a relationship between a composition of the ABC (InGaP) and a chemical potential of A (In) at a temperature T₁; Fig. 3A is a fragmented sectional view of a semiconductor substrate for explaining the present invention; Fig. 3B is a graph of a lattice constant and a composition variation of the substrate of Fig. 3A; Fig. 4A is a fragmented sectional view of another semiconductor substrate for explaining the present invention; Fig. 4B is a graph of a lattice constant variation and composition variation of the substrate of Fig. 4A; Fig. 5A is a fragmented sectional view of a GaAs/Si substrate for explaining the present invention; and Fig. 5B is a graph of a lattice constant variation of the substrate of Fig. 5A. According to the present invention, an SLS structure is thermally stabilized by utilizing a miscibility gap in a ternary or quaternary compound semiconductor system determining the alternating first and second compound semiconductor thin layers. Figure 1 shows a pseudo-binary phase diagram of a ternary ABC (e.g., In x Ga 1-x P) system at a combination of BC (III-V compound semiconductor, e.g., GaP) and AC (another III-V compound semiconductor, e.g., InP). The abscissa and ordinate of Fig. 1 indicate a ratio of "x" of component A (In) of the composition and temperature, respectively. In Fig. 1, points P₁ (P₂ , P₃) and Q₁ (Q₂ , Q₃) are limiting values of a complete solid solution state at a temperature T₁ (T₂ , T₃), between the points P₁ (P₂ , P₃) and Q₁ (Q₂ , Q₃) of a miscibility gap region. The continuous line L is a critical value, and the miscibility gap region is inside the line L. For example, in the In x Ga 1-x P system points P₁ , P₂ , P₃ and Q₁ , Q₂ , Q₃ indicate the following compositions, at temperatures T₁ , T₂ and T₃ , and the degree of mismatch (strain value) given by the ratio of Δa to the lattice constant a of In 0.5 Ga 0.5 P: T₁ = 510°C: P₁ = In 0.3 Ga 0.7 P Δa/a = ±1.5%: Q₁ = In 0.7 Ga 0.3 P T₂ = 560°C: P₂ = In 0.37 Ga 0.63 P Δa/a = ±1.0%: Q₂ = In 0.63 Ga 0.37 P T₃ = 590°C: P₃ = In 0.43 Ga 0.57 P Δa/a = ±0.5%: Q₃ = In 0.57 Ga 0.43 P The maximum temperature Tc of the miscibility gap is about 630°C. A GaPSb system or an InGaAsP system can be adopted instead of the InGaP system. A chemical potential µA of component A (In) at a temperature T₁ varies as shown in Fig. 2. The abscissa and ordinate of Fig. 2 indicate the composition ABC (In x Ga 1-x P) and the chemical potential, respectively. The decay of the SLS structure due to a high temperature heat-treatment is caused by an interdiffusion of elements of each of the compound-semiconductor thin layers. When a gradient of the characteristic curve of the chemical potential exists, the gradient generates this interdiffusion, but between the points P₁ and Q₁ , the gradient is zero; in this region the following formula is valid and thus interdiffusion does not occur: Therefore, if the SLS structure is formed on the one hand of compound-semiconductor thin layers having a composition at P₁ or in its vicinity which lies outside of the miscibility gap, and on the other hand and alternately of compound-semiconductor thin layers having another composition at Q₁ or in its vicinity which lies outside the miscibility gap, the SLS structure is extremely thermodynamically stable against a heat-treatment at a temperature T₁ , and thus the SLS structure does not decay. For example, for the SLS structure consisting of thin layers of In 0.3 Ga 0.7 P and In 0.7 Ga 0.3 P the limiting temperature is 510°C. If the temperature of the heat-treatment is 550°C, the SLS structure should be formed of In 0.37 Ga 0.63 P and In 0.63 Ga 0.37 P layers. The GaAsSb system of GaAs-GaSb, or the InGaAs system of GaAs-InAs can be used for an SLS structure utilized in the growth of an epitaxial InP layer, since these systems have pseudo-binary phase diagrams similar to that of Fig. 1. The GaAs 1-x Sb x system has the following data: T₁ ≈ 770°C: P₁ = GaAs 0.7 Sb 0.3 Δa/a = 1.5%: Q₁ = GaAs 0.3 Sb 0.7 T₂ ≈ 790°C: P₂ = GaAs 0.63 Sb 0.37 Δa/a = ±1.0%: Q₂ = GaAs 0.37 Ga 0.63 T₃ ≈ 820°C: P₃ = GaAs 0.566 Sb 0.434 Δa/a = 0.5%: Q₃ = GaAs 0.434 Sb 0.566 Tc ≈ 830°C Here Δa/a indicates a degree of mismatch (strain value), Δa of GaAs 1-x Sb x being taken with reference to the lattice constant a of GaAs 0.5 Sb 0.5 . The In x Ga 1-x As system has the following data: T₁ = 580°C P₁ = In 0.72 Ga 0.28 As Δa/a = ±1.5% Q₁ = In 0.28 Ga 0.72 As T₂ ≈ 600°C P₂ = In 0.65 Ga 0.35 As Δa/a = ±1.0% Q₂ = In 0.35 Ga 0.65 As T₃ ≈ 620°C P₃ = In 0.57 Ga 0.43 As Δa/a = ±0.5% Q₃ = In 0.43 Ga 0.57 As Tc ≈ 630°C Again, Δa/a indicates a degree of mismatch, Δa of In x Ga 1-x As being referred to the lattice constant of In 0.5 Ga 0.5 As. In 0.47 Ga 0.53 As has the same lattice constant as that of InP. Preferably the GaAsSb system is adopted, because the SLS structure of the GaAsSb system can withstand higher temperatures than the InGaAs system. Example 1 Referring to Figs. 3A and 3B, a semiconductor substrate illustrating the present invention consists of a single-crystalline GaAs wafer substrate 1, an SLS structure layer formed of In 0.7 Ga 0.3 P thin layers 2A having a constant thickness, and In 0.3 Ga 0.7 P thin layers 2B having a constant thickness, and an epitaxial In 0.51 Ga 0.49 P layer 3 having the same lattice constant as that of the GaAs wafer substrate 1. In this case, the degree of mismatch (strain value), given by the ratio of Δa of the thin layers 2A and 2B to the lattice constant of In 0.5 Ga 0.5 P, is ±1.5%. Each of the thin layers 2A and 2B has a thickness of from 5 to 30 nm. Note, the thickness of the individual thin layers should be below the maximum critical thickness corresponding to the self-generation of misfit dislocations. In the SLS structure the lattice constant "a₁₁" of an individual thin layer in a face parallel to the wafer substrate surface is determined by the following formula: wherein: a A and a B are unstrained lattice constants of the thin layers 2A and 2B, respectively; h A and h B are thicknesses of the thin layers 2A and 2B, respectively; and G A and G B are rigidities of the thin layers 2A and 2B, respectively. This lattice constant "a₁₁" of the SLS structure can thus be made to coincide with that of the wafer substrate 1, as shown in Fig. 3B, by controlling the ratio ( h A /h B ) of the thickness of the thin layer 2A to that of the thin layer 2B. For instance, the lattice constant "a₁₁" of the ten-period In 0.3 Ga 0.7 P (10.5 nm) - In 0.7 Ga 0.3 P (9.5 nm) SLS structure layer is equal to that of the GaAs wafer substrate, h A /h B being about 21/19. After the formation of the SLS structure layer 2, the In 0.51 Ga 0.49 P layer 3 is epitaxially grown under the condition that the lattice constant of the layer 3 is equal to that of the SLS structure layer 2, as shown in Fig. 3B. Next, the obtained compound substrate is annealed, to reduce the number of dislocations, at a temperature of 500°C. The annealing reduces the number of dislocations, and thus stabilises the SLS structure without decay. The AlGaInP lower clad layer, GaInP active layer, AlGaInP upper clad layer, and GaAs cap layer are then epitaxially and successively grown on the obtained compound-semiconductor substrate (i.e. the In 0.51 Ga 0.49 P layer 3) to produce an LED having an emission wavelength of about 650 nm. Example 2 Referring to Figs. 4A and 4B, another compound-semiconductor substrate illustrating the present invention consists of the GaAs wafer substrate 1, an SLS structure layer 2 formed of In 0.3 Ga 0.7 P thin layers 2A₁ , 2A₂ ... 2A n and In 0.7 Ga 0.3 P thin layers 2B₁ , 2B₂ ... 2B n , and an epitaxial In 0.4 Ga 0.6 P layer 4 having a smaller lattice constant than that of the GaAs wafer substrate 1. To change the lattice constant "a₁₁" of the SLS structure layer from that of GaAs to that of In 0.4 Ga 0.6 P, as shown in Fig. 4B the ratio of the thickness h A1 (h A2 ... h An ) of the thin layer 2A₁ (... 2A n ) to that h B1 (h B2 ... B n ) of the thin layer 2B₁ (... 2B n ) of each pair of adjacent thin layers is gradually varied as follows: For example, a ten-period In 0.3 Ga 0.7 P (10.5 to 15 nm) - In 0.7 Ga 0.3 P (9.5 to 5 nm) SLS structure layer (in which h A1 /h B1 = 21/19 , h A10 /h B10 = 3/1 and one period thickness of 20 nm = constant) is suitable. The In 0.4 Ga 0.6 P layer 4 is epitaxially grown on the resulting SLS structure layer 2, the lattice constant of the layer 4 coinciding with the varied lattice constant "a₁₁" of the layer 2, as shown in Fig. 4B. The obtained substrate is then annealed at 500°C to reduce the number of dislocations and stabilize the SLS structure without decay. Instead of the above-mentioned thickness ratio variation In x Ga 1-x P, wherein "x" starts at about 0.3 and is gradually reduced, can be used for the thin layers 2A₁ , 2A₂ ... 2A n under the condition h A1 /h B1 = h A2 /h B2 = ... = h An /h Bn . In this case, the value "x" is from 0.3 to the minimum critical value, beyond which misfit dislocations are generated. Example 3 Referring to Figs. 5A and 5B, another semiconductor substrate illustrating the present invention is shown. This substrate consists of a single-crystalline silicon (Si) wafer substrate 11, a GaAs buffer layer 12, an SLS structure layer 13 of the ten-period In 0.37 Ga 0.63 P (9.2 nm) - In 0.63 Ga 0.37 P (10.8 nm), and a GaAs epitaxial layer 14. The amorphous GaAs buffer layer 12 is deposited on the Si wafer substrate 11 by a conventional MOCVD process. A graded GaAs buffer layer could also be formed. Then, the SLS structure layer 13 consisting of In 0.37 Ga 0.63 P thin layers and In 0.63 Ga 0.63 P thin layers is formed on the GaAs buffer layer 12 by a MOCVD process to provide a lattice constant "a₁₁" equal to that of GaAs, as shown in Fig. 5B. Next, the GaAs epitaxial layer 14 is grown on the SLS structure layer 13 to obtain a GaAs/Si substrate. The obtained semiconductor (GaAs/Si) substrate is annealed to reduce the number of dislocations without a decay of the SLS structure. As described above, according to the present invention, each pair of compound-semiconductor thin layers of the SLS structure layer has compositions at both limit positions or the vicinity of the miscibility gap at a temperature corresponding to that of a heat-treatment, so that temperatures at or below that temperature do not affect the SLS structure. Therefore, suitable heat-treatments (annealing, etc.) can be applied to the obtained semiconductor substrate to reduce the number of dislocations, without decay of the SLS structure. The difference between the miscibility gap temperature and the heat-treatment temperature is preferably 10°C or more, since the compositions of the thin layers of the SLS structure layer may vary due to variation in the growth conditions.

Claims: A method of making a semiconductor substrate comprising a single-crystalline semiconductor wafer substrate (1), a strained layer superlattice structure layer (2) formed on the said wafer substrate and a compound-semiconductor epitaxial layer (3) formed on the strained layer superlattice structure layer (2), the strained layer superlattice structure layer (2) comprising alternate thin layers (2A,2B) of a first compound semiconductor and a second compound semiconductor, wherein the first and second thin layers have the same components in a compound system having a miscibility gap but have different compositions lying outside the miscibility gap to each side respectively and on or in the vicinity of the limit line at a predetermined temperature, and the method includes the step of subjecting the substrate to a heat treatment at or below the said predetermined temperature. A method according to claim 1, wherein the wafer substrate (1) is itself composed of a compound semiconductor. A method according to claim 2, wherein the said compound-semiconductor material of the substrate consists of GaAs, InP, GaP, GaSb, or InAs. A method according to claim 3, wherein the wafer substrate (1) is composed of GaAs, the epitaxial layer (3) is composed of InGaP, and the first and second thin layers (2A,2B) are composed of compounds in the GaP-InP system. A method according to claim 1, wherein the wafer substrate (1) is composed of silicon. A method according to claim 5, wherein the compound-semiconductor substrate further comprises a GaAs buffer layer (12) on the silicon wafer substrate (11), the epitaxial layer (14) is composed of GaAs, and the first and second thin layers (13) are composed of compounds from the InP-GaP system, the GaP-GaSb system or the GaP-InAs system. A method according to claim 1, wherein the lattice constant of the epitaxial layer (3) is equal to that of the wafer substrate (1). A method according to claim 7, wherein the ratio of the thicknesses of adjacent thin layers (2A,2B) of the first and second compound semiconductors is constant throughout the thickness of the superlattice. A method according to any of claims 1 to 6, wherein the lattice constant of the epitaxial layer (3) is different from that of the wafer substrate (1). A method according to claim 9, wherein the ratio of the thicknesses of adjacent thin layers (2An,2Bn) of the first and second compound semiconductors varies gradually with distance perpendicular to the substrate. A method according to claim 9, wherein the ratio of the thicknesses of the adjacent thin layers is constant, and the composition of either the first or the second thin layers, or both, gradually varies. A method according to any preceding claim, wherein the difference between the miscibility gap temperature and the heat-treatment temperature is 10°C or more.

Inventors: OKUDA, HIROSHI, SUGAWARA, MITSURU
Applicants: FUJITSU LIMITED
Application year: 1989
Main classification: H01L21
IPC codes: H01L21, H01L33, H01L29