Method and apparatus for frame synchronization

Abstract: A frame synchronization method in which a synchro­ nization detection of a frame synchronization signal using one of n-multiplexed frame synchronization signals derived from a sequence of frame synchronization signals each delayed by one bit from the preceding frame synchronization signal, a synchronization confirmation as synchronization guard by detecting a repetition of the synchronization detections of the frame synchroni­ zation signal, a confirmation of the subsequent frame identification signal based on the synchronization confirmation, and a separation of the received multi­ plexed signals into a plurality of channels based on the synchronization confirmed frame synchronization signal and the confirmed frame identification signal are carried out. A frame synchronization apparatus including latch means (3), a frequency division portion (4), frame synchronization detection and control means (5) and a demultiplexer (6).

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is related to a method and apparatus for frame synchronization in data transmission. The method and apparatus according to the present invention are used for a high speed transmission of PCM signals in a data communication network. 2. Description of the Related Arts In a frame synchronization method, the detection of frame synchronization is carried out by successively shifting the frame synchronization pattern by one clock cycle. Accordingly, for example, the detection and identification of the frame synchronization pattern should be carried out, in the case where three groups of data of 50 Mbps are 3-multiplexed to form data of 150 Mbps, within one clock period of 150 Mbps. In such a short period, i.e., at such a high speed, it is difficult to carry out frame synchronization pattern detection reliably. In order to reduce the speed requirement of the operation, another method may be considered in which a latch portion, parallel synchronization detection portion, and data separation portion are provided. In this method, since the data is converted into eight groups of parallel data, latched every 8 bits, and detection of frame synchronization pattern is carried out per latch period, the speed requirement of the operation is reduced by one-eighth in comparison with the method mentioned first. However, since the number of frame synchronization pattern detection portions is required to correspond to the number of frame synchronization patterns for multiplexing, the scale and complication of the circuits of the apparatus tends to be increased. Such an increase of the scale and complication of the circuits of the apparatus is disadvantageous. From US-A-3 909 541 a low speed framing arrangement for a high speed digital bit stream is known. The high speed digital bit speed comprises information from a plurality of multiplexed channels and framing bits. The bit stream is unconditionally divided into a number of lower speed bit streams. The lower speed bit streams are then conditionally divided to form a new group of bit streams, and the new bit streams are examined by a framing detector. The framing detector shifts the timing of the conditional division in relation to the lower bit streams until a predetermined frame pattern appears among the new bit streams. From JP-A-61-49 533 a time divisional multiplex communication system is known in which a common synchronizing signal and an address signal of each channel are added to the multiple channels and accordingly a time divisional multiplexing of the digital signals is carried out. From US-A-4 602 367 a method for framing and demultiplexing multiplexed digital data is known, including the steps of splitting multiplexed data into n-separate data channels which have a predetermined circular permutation relationship; detecting the channel identity of one of the n data channels; time delaying data bits of some n-1 of the data channels according to a predetermined algorithm if the identity of the detected channel is other than a given channel; and rerouting the channels as output to provide a set of time synchronized parallel output bits while maintaining the predetermined circular permutation relationship. From US-A-4 802 192 (corresponding to JP-A-62 188 446 published on 18.08.1987) a circuit for detecting a synchronizing pattern from a code series containing a synchronizing code is known, in which the synchronizing code detection circuit includes dividing means for dividing an original code series containing a synchronizing code into a code series, n in number, having a bit rate of 1/n of that of the original code series n being a positive integer; delay means for delaying a code series, (n-m) in number m being a positive integer ranging from 1 to m, out of the code series, m in number delivered from the dividing means, for a time equivalent to one time slot of the bit rate of 1/n, respectively; and synchronizing pattern detecting means for detecting a pattern corresponding to any of the synchronizing patterns of m kinds obtained by rotating an original synchronizing pattern. SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved method and apparatus for carrying out frame synchronization in which the detection of a frame synchronization signal at a low speed is enabled without increasing the scale and complication of the circuit of the apparatus. In accordance with the present invention there is provided a frame synchronization method comprising the steps of: receiving a serial bit stream including frame synchronization signals frame identification signals and data transmitted serially through a transmission line in n-multiplexed predetermined sequential relation such that n identical frame synchronization signals of n multiplexed channels are followed by n frame identification signals which are followed by data, each frame synchronization signal and each frame identification signal comprising the same predetermined number of bits; converting the received serial bit stream into a signal stream by conversion means; selecting and latching a signal of said signal stream; carrying out synchronization detection of said selected signal by comparing said selected signal with parallel patterns of said frame synchronization signal, each pattern being shifted by one clock cycle; if said comparison indicates identity of said selected signal with one of said parallel patterns selecting the associated frame identification signal from the serial bit stream on the basis of the particular pattern and of the predetermined sequential relation; deriving a synchronization signal from said selected frame identification signal and said particular pattern. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, Fig. 1 shows a pattern of data received in the form of a frame in a multiplexed signal transmission system; Fig. 2 shows a fundamental constitution of a multiplexed signal transmission system; Fig. 3 shows the patterns of a transmission signal before and after multiplexing; Fig. 4 shows a prior art apparatus for carrying out frame synchronization; Fig. 5 illustrates the operation of the prior art apparatus of Fig. 4; Fig. 6 shows an apparatus for carrying out frame synchronization according to an embodiment of the present invention; Fig. 7 illustrates the operation of the apparatus of Fig. 6; Fig. 8 illustrates the operation of synchronization detection in the apparatus of Fig. 6; Fig. 9 shows a device for carrying out the synchronization detection in the apparatus of Fig. 6; and Fig. 10 illustrates the detection of the frame identification information. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a preferred embodiment of the present invention, the general pattern of signals received in a multiplexed signal transmission system will be explained with reference to Figs. 1, 2, and 3, and a prior art apparatus for carrying out frame synchronization in a multiplexed signal transmission system will be explained with reference to Fig. 4. The operation of the prior art apparatus of Fig. 4 will be explained with reference to Fig. 5. In a high speed transmission network, used for, for example, PCM communication, a plurality of information in the form of frames as shown in Fig. 1 are to be transmitted. Each of the frames of information is constituted by first a frame synchronization signal FS, second a frame identification signal ID, and the rest is data. Data No. 1, No. 2, ... No. n through channel No. 1, No. 2 ... No. n are multiplexed in the multiplexer 1 on the sender side (Figs 2 and 3) and the multiplexed data is transmitted through the transmission line 2 to the demultiplexer 6' on the receiver side. In the demultiplexer 6', the received multiplexed data is demultiplexed to be separated into data No. 1, No. 2, ... No. n for the channel Nos. 1 to n. For identification of each of the data No. 1, No. 2, ... No. n, a byte frame synchronization signal FS, and a frame identification signal ID are placed at the beginning of each of the data No. 1, No. 2, ... No. n. In the prior art apparatus of Fig. 4, there are provided a frame synchronization processing unit 7 including a serial to parallel conversion portion 71, a frame synchronization pattern detection portion 72, a counter 73, a synchronization guard portion 74, and an AND gate 75, and a data separation unit 8 including a serial to parallel conversion unit 81, a latch 82, and a decoder 83. As shown in Fig. 5, the received serial data is converted into parallel data in the serial to parallel conversion portion 71, and the converted parallel data is supplied to the frame synchronization pattern detection portion 72. In the frame synchronization pattern detection portion 72 a shifting operation is carried out successively by one clock cycle. Due to this shifting operation, a coincidence of frame synchronization must occur at one phase of the shifting, so that the detection of frame synchronization can be carried out. When frame synchronization is detected, a coincidence pulse is supplied from the frame synchronization pattern detection portion 72 to the synchronization guard portion 74 for ensuring the reliability of detection of synchronization. After detecting a predetermined number of coincidence pulses, the synchronization guard portion 74 delivers an output signal to the AND gate 75. Receiving the output signal of the synchronization guard portion 74 and the coincidence pulse from the frame synchronization pattern detection portion, the AND gate 75 delivers a reset signal to the counter 73. The counter 73 is operated with this reset signal as timing of the beginning of the frame synchronization. The information of the beginning of the frame synchronization is supplied from the counter 73 to the decoder 83 of the data separation unit 8. In the decoder 83, latch timing of the latch 82 is determined based on the information of the beginning of the frame synchronization and the frame identification signal from the transmission line 2. Thus, in the latch 82, the separation of the received data into channel No. 1, No. 2, ... No. n is carried out. An apparatus for carrying out frame synchronization according to an embodiment of the present invention is shown in Fig. 6. The apparatus of Fig. 6 includes a latch unit 3 having a serial to parallel conversion portion 31, a latch 32, and a 1/8 frequency divider portion 33, a frequency division-by-n portion 4, a synchronization detection & control unit 5 having a latch 51, a frame synchronization pattern detection portion 52, a frame identification information detection portion 53, and a control and guard portion 54, and a demultiplexer 6. In the serial to parallel conversion portion 31, serially transmitted 3-multiplex signals are converted into parallel signals, as illustrated in Fig. 7, where the multiplex number n is assumed to be 3. In the latch 32, data are latched in units of 8 bits per 1/8 frequency division of the clock signal from the 1/8 frequency division portion 33. In the latch 51, the converted parallel data from the latch 32 is further latched to produce parallel data. In the frame synchronization pattern detection portion 52, one of the FS patterns as a frame synchronization signal is detected from a sequence of signals each shifted by one bit from the preceding signal supplied from the latch 51. This sequence of signals is illustrated in Fig. 8. The first FS pattern corresponds to bit 1 to bit 8; the second, bit 2 to bit 9; the third, bit 3 to bit 10; and so on, to the eighth, bit 8 to bit 15. The function of the frame synchronization pattern detection portion 52 is illustrated in Fig. 9. In the sequence of comparator Nos. 1 to 8, the sequence of frame synchronization patterns FS-1 to FS-8 is compared with the reference frame synchronization pattern supplied from a reference FS pattern generation member which generates a reference FS pattern constituted by a sequence of bit 1, bit 2, bit 3, ... as shown in Fig. 8. Each of the comparators produces a "0" output when two inputs do not coincide, but produces a "1" output only when two inputs coincide. Therefore, in the sequence of the comparator Nos. 1 to 8, only one comparator which receives the same frame synchronization pattern as the reference FS pattern produces a "1" output, and this "1" output indicates the detection of the frame synchronization pattern in question. In the frame identification information detection portion 53, the detection of frame identification information is carried out based on the detected frame synchronization pattern from the FS pattern detection portion 52. If the detected frame synchronization is the first FS, the 8 bit frame identification signal ID1 follows the detected 8 bit FS signal as shown in Fig. 10. In the control and guard portion 54, synchronization confirmation is carried out as a synchronization guard by detecting a repetition of the synchronization detections of the frame synchronization signal, based on the FS pattern detection signal from the FS pattern detection portion 52 and the frame identification information detection portion 53. After that, in the control and guard portion 54, a shift signal is produced based on the detection in the FS pattern detection portion 52 and the produced signal is supplied to the frequency division portion 33 of the latch unit 3 to regulate the timing of frequency division. Also, the control signal from the control and guard portion 54 which is the information indicating the beginning of frame synchronization in the channel in question is supplied to the 1/n frequency division portion 4. In the 1/n frequency division portion 4, the 1/8 frequency divided clock signal is further frequency divided by n. The produced frequency divided clock signal from the 1/n frequency division portion 4 is supplied as a detection timing control signal to the FS pattern detection portion 52 and the frame identification information detection portion 53. Also, the frequency divided clock signal produced from the 1/n frequency division portion 4 is supplied to the demultiplexer 6. Based on this frequency divided clock signal from the 1/n frequency division portion 4, the beginning position of selection in the demultiplexer 6 is determined, and the received data is separated into predetermined channels No. 1 to No. n in the demultiplexer 6 based on this determination. As described above, in the apparatus of Fig. 6, the received serial data is converted into parallel data, and latched in groups of 8 bits to form parallel 8 bit data. The detection of an 8 bit frame synchronization pattern by comparison with the reference frame synchronization pattern is carried out at a 1/n frequency divided timing. A detection of frame synchronization is required with regard to only one frame synchronization pattern. For example, even in the case where three groups of data of 50 Mbps are 3-multiplexed to form data of 150 Mbps, the detection and identification of the frame synchronization pattern must be carried out within one clock period of only 50 Mbps. Thus it is possible to detect the frame synchronization at a low speed which cannot be attained by the prior arts. This advantage of the apparatus of the present invention is attained regardless of the multiplex number n. Accordingly, an increase in scale and complication of the circuits involved in the apparatus is prevented according to the apparatus of the present invention, even if the multiplex number n is increased. Therefore, a practical and advantageous method and apparatus can be provided according to the present invention.

Claims: A frame synchronization method comprising the steps of: receiving a serial bit stream including frame synchronization signals (FS), frame identification signals (ID1, ID2,...IDn) and data transmitted serially through a transmission line in n-multiplexed predetermined sequential relation such that n identical frame synchronization signals of n multiplexed channels are followed by n frame identification signals which are followed by data, each frame synchronization signal and each frame identification signal comprising the same predetermined number of bits; converting the the received serial bit stream into a signal stream by conversion means (31); selecting and latching a signal of said signal stream; carrying out out synchronization detection of said selected signal by comparing said selected signal with parallel patterns (FS(1)...FS(8)) of said frame synchronization signal, each pattern being shifted by one clock cycle; if said said comparison indicates identity of said selected signal with one of said parallel patterns (FS(1)...FS(8)) selecting the associated frame identification signal from the serial bit stream on the basis of the particular pattern and of the predetermined sequential relation; deriving a synchronization signal from said selected frame identification signal and said particular pattern. A method according to claim 1, characterized by carrying out synchronization confirmation as a synchronization guard by detecting a repetition of coincidences of selected signals with said pattern. A frame synchronization apparatus for carrying out the method of claim 1 comprising: latch means (3) connected to said transmission line (2) for latching parallel signals converted from a received serial bit stream, the latch means (3) including a serial to parallel conversion portion (31), a first latch portion (32), and a first frequency division portion (33) for providing a frequency divided clock signal; a second frequency division portion (4) receiving said frequency divided clock signal for carrying out 1/n frequency division to produce a detection timing control signal as a synchronization signal; frame synchronization detection and control means (5) connected to said latch means (3) including a frame pattern detection portion (52), and a frame identification detection portion (53), both receiving said detection timing control signal from said second frequency division portion (4), a second latch portion (51), and a control and guard portion (54) for detecting coincidence of a latched parallel signal with any of said parallel patterns (FS(1)...(FS(8)), and in case of coincidence generating a second control signal for said first and second frequency division portions. A frame synchronization apparatus according to claim 3, characterized by demultiplexer means (6) for receiving the output of said first latch portion (32) and said detection timing control signal from said second frequency division portion (4) and separating said received multiplexed signals into a plurality of channels.

Inventors: IGUCHI KAZUO, SOEJIMA TETSUO, WATANABE TOSHIAKI, IGUCHI, KAZUO, SOEJIMA, TETSUO, WATANABE, TOSHIAKI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H04J3
IPC codes: H04J3, H04L7