Solid-state camera and solid-state memory apparatus

Abstract: A solid-state camera includes a loading detecting unit (26) for detecting loading of a detachable solid-state memory apparatus, a checking unit for checking the loaded solid-state memory apparatus, and a control unit for performing control of each section which includes predetermined display control (32) in accordance with a check result of the checking unit. Conveniently the detachable memory apparatus may be adapted to provide identification information in either stored or mechanical form to facilitate interchange of different types of memory.

Description: The present invention relates to a solid-state camera for use with detachable solid-state image storage means as a recording medium for a photographed image and a detachable solid-state image storage means for use therewith. An electronic still camera using a memory not requiring a movable mechanism for recording/reproduction of information (to be referred to as a solid-state camera hereinafter) has attracted attention as a successor of a silver chloride still camera and a video floppy electronic still camera. In an electronic still camera, instantaneous reproduction of a photographed image, image transfer, computer image processing, electronic image filing and the like can be easily performed by electronically processing image information. In the case of using a compact magnetic sheet called a video floppy as a recording medium, however, movable portions such as a rotating mechanism for the magnetic sheet and a head moving mechanism for positioning a magnetic head with precision of several tens to hundreds of µm in terms of a track pitch are required, thereby increasing a manufacturing cost of a camera and limiting use environments and an operation speed. These problems are similarly posed when an optical disk or optical magnetic disk is used as a recording medium. The solid-state camera has been proposed as a camera capable of solving the above problems. Fig. 1 shows an arrangement of a solid-state camera system. Referring to Fig. 1, a memory cartridge 12 as a solid-state memory apparatus for storing image information can be detached from a camera main body 10 of the solid-state camera. A reproducing apparatus 14 reproduces stored information in the memory cartridge 12. The memory cartridge 12 comprises, e.g., an IC memory device, a memory controller, and a backup power source therefor. As the IC memory device, an SRAM, a DRAM, an EPROM, an EEPROM, or the like is used. The memory cartridge 12 and the camera main body 10 are connected by using, e.g., a metal connector, a transmit coil, or a photocoupler. An image photographed by the camera main body 10 is stored in a predetermined format by the memory cartridge 12. By connecting the memory cartridge 12 to the reproducing apparatus 14 to reproduce the stored image, electronic image data can be transmitted from the reproducing apparatus to a TV monitor, a printer, a transmitter, a filing apparatus, and the like. In the conventional solid-state camera having the above arrangement, however, since the memory cartridge 12 can be detached from the camera main body 10, communication between the memory cartridge 12 and the camera main body 10 must be perfect upon photographing. In addition, in the memory cartridge 12 circuit defects can occur and there can be insufficient backup power source capacity, and the like. If a user operates the camera release button without noticing the occurrence of these defects, he or she fails to photograph because no photographic image can be recorded. Furthermore, the camera main body 10 must include a power source for driving various signal processors and exposure control means such as a lens driving means and an aperture driving means. A user, therefore, must perform a maintenance operation for, e.g., checking the voltage of a power source battery of the camera main body 10 or replacing the battery before he or she uses the camera, resulting in a very cumbersome operation for a user. Even if the power source capacity of the camera main body 10 is increased, not only this maintenance operation is not basically omitted, but also the size of the camera main body 10 is increased by the increase in capacity. Moreover, a write speed (or time) of the IC memory device in the memory cartridge 12 largely changes in accordance with the type of device. Therefore, as the memory capacity is increased, a difference between write times is increased. If data transfer is not performed at a proper speed corresponding to the write speed, data may be lost. In order to commercialise the solid-state camera and the solid-state memory apparatus as described above, the size, connecting pins, and the like of the solid-state memory apparatus such as the memory cartridge 12 must be standardised. If, however, techniques for realising large capacity, high speed, and low power consumption of the IC memory device of the memory cartridge 12 rapidly progress, standardisation of the size may prevent use of advanced circuit devices. United States Patent No. 4837628 discloses a solid state camera which is designed to receive a memory card solid state image store. Completed loading of the memory card is checked by the user who can view the alignment of an alignment pattern through a window in the camera body. The information flow is one way from the camera to the memory card. The memory card includes a backup battery and random access memory elements. While data can be written in this memory card the only data written in is image data and information such as date and shutter speed identifying the photographic image but not the characteristics of the card itself. German Patent Application DE-A-3235735 also concerns a solid state camera which will accept detachable solid state image stores. Operation of this camera is controlled by a central processing unit (CPU). In this camera the absence of a loaded memory sub-unit, or the presence of a defective sub-unit, is detected as an open circuit across the camera input contacts. In the event of such detection the CPU 33 controls operation of the camera so that the next loaded and effective memory sub-unit is accessed. Other than in the detection of open circuit, the flow of information is one way, being from camera to image store. The image store cartridge in addition to including image store sub-units includes checking circuits. The cartridge also incorporates a display area which allows visual display of the number of photographs taken/sub-units used and units which are missing or defective. These latter indications are visual and not accessible by the camera itself. No means are provided in the camera for inhibiting operation once all sub-units have been used and the memory capacity exhausted. United States Patent No. 4,420,773 describes a solid state camera and cartridge. The cartridge has an electro-optical element such as a liquid crystal or electrochromic segmented display which shows the number of current frame. When the camera release button is depressed fully a running count is conducted and compared with frame number. Only if the running count exceeds storage capacity is a warning or indication given that the memory capacity has been exceeded. The present invention is provided as a remedy. In accordance with a first aspect of the present invention there is provided a solid state camera for use with a detachable solid state image storage means which camera comprises: detection means, co-operable with said solid state image storage means to detect from indications provided by said solid state image storage means one or more of the following respective parameters: (a) a remaining memory storage capacity of said solid state image storage means at time of loading of said detachable solid state image storage means and directly following each exposure; (b) a remaining power capacity of a back-up power source incorporated in said solid state image storage means; and (c) a maximum write speed for recording into a memory storage of said solid state image storage means image data produced by said camera; and camera operation control means responsive to said detection means to control operation of said camera, to perform the following operations: (i) to inhibit operation and give warning prior to exposure release in the event that it is detected that either there is no remaining memory storage capacity, or the remaining power capacity is below a predetermined level; and/or (ii) to control a rate of transfer of image data from said camera to said solid state image storage means in dependence upon the maximum write speed both indicated by said solid state image storage means and detected by said detection means; and/or (iii) to control a speed of continuous photography in dependence upon said maximum write speed which is both indicated by said solid state image storage means and detected by said detection means. According to a second aspect of the invention there is provided a detachable solid state image storage means for use with, and attachable to, a solid state camera as claimed in claim 1, which image storage means includes: image data memory storage for storing image data; and information means for storing any one or more of the respective parameters (a) to (c), which information means is co-operable with said solid-state camera and is effective to transfer indication of said one or more parameters from said image storage means to said solid state camera, to control automatic setting and operation thereof. Preferably the said information means contains information providing indication of, all parameters (a) to (c) just specified. Structured as aforesaid the camera can cope automatically with image stores having different memory capacity or writing speed or both. It can give warning or display indication when no further photographing is possible - i.e. when storage capacity has been used up or when back-up power is used up. In the accompanying drawings: Fig. 1 is a perspective view showing an arrangement of a conventional solid-state camera system; Fig. 2 is a perspective view showing an outer appearance of solid-state camera according to an embodiment of the present invention; Fig. 3A is a sectional view showing a state in which a cartridge insertion portion is open; Fig. 3B is a sectional view showing a state in which a cartridge is inserted; Fig. 4 is block diagram showing an electric circuit arrangement of the embodiment; Fig. 5 is a flow chart for explaining an operation of the embodiment; Fig. 6 is a schematic view showing a format of communication data; Fig. 7 is a block diagram showing an arrangement of another embodiment of the present invention; Fig. 8 is a flow chart for explaining the embodiment; Fig. 9 is a block diagram showing an arrangement of still another embodiment of the present invention; Fig. 10 is a block diagram showing an embodiment of a solid-state memory apparatus of the present invention; Fig. 11 is a timing chart of a command; and Fig. 12 is a timing chart upon a recognition code read operation. Embodiments of the present invention will be described below with reference to the accompanying drawings. The following description is given by way of example only. Fig. 2 is a perspective view showing an outer appearance of an embodiment of the present invention, Fig. 3A is a sectional view showing a state in which an insertion portion for a memory cartridge as a solid-state memory apparatus is open, and Fig. 3B is a sectional view showing a state in which the memory cartridge is inserted in the insertion portion and the insertion portion is closed. In these drawings, a camera main body 20 comprises a cover 22, a cartridge holder 24 which can pivot about a pivot centre 24a, a loading detection switch 26, electric contacts 28 for communicating with the memory cartridge, a release button 30, a liquid crystal display (LCD) device 32, a cover member 34, a cover biasing compression coil 36, a memory cartridge 38, memory contacts 38a of the memory cartridge 38, an eject button 40 for the memory cartridge 38, and a power switch 42 of the camera main body 20. An operation of each section will be described below. In order to perform photographing, the eject button 40 is operated to set the open state shown in Fig. 3A, and the memory cartridge 38 is inserted in the holder 24 in a direction indicated by an arrow shown in Fig. 3A. If a barrier shutter for protecting a contact is provided for the memory cartridge 38, the barrier shutter is opened by opening means (not shown) during insertion. When the memory cartridge 38 reaches a predetermined position deep in the holder 24, the cartridge 38 is locked by a locking mechanism (not shown). Thereafter, by closing the cover 22, the memory contacts 38a are brought into contact with and electrically connected to the electric contacts 28 of the camera body 20, as shown in Fig. 3B. After insertion is completed, the loading detection switch 26 is operated, and the state shown in Fig. 3B is held by a cover locking mechanism (not shown). Fig. 4 is a block diagram showing an arrangement of electric circuits of this embodiment. In Fig. 4, the same reference numerals as in Figs. 2, 3A, and 3B denote the same parts. Referring to Fig. 4, the camera main body 20 includes a photographic lens 50, a CCD image pickup device 52, a signal processor 54, an A/D converter 56, an interface circuit 58 with respect to the memory cartridge 38, a controller 60 constituted by a microcomputer for controlling the overall system, and a switch 62 for inputting various commands. The image pickup device 52 converts an optical image of an object photographed by the photographic lens 50 into an electrical signal, and the signal processor 54 performs predetermined image signal processing. The A/D converter 56 digitizes an output from the signal processor 54. An output from the A/D converter 56 is supplied to and stored in the memory cartridge 38 via the interface circuit 58 and the contacts 28 and 38a. Fig. 5 shows a control operation flow chart for performing checking in the above solid-state camera. Referring to Fig. 5, when a power source is switched on by the power switch 42 (S1), the controller 60 checks an open/close state of the loading detection switch 26 (S2). If an unloaded state is detected, the controller 60 performs warning by the display device 32 and/or a sound so as to cause the user to load the memory cartridge 38 (S4). If the memory cartridge 38 is already loaded, the controller 60 reads out various pieces of specification information stored beforehand in the loaded memory cartridge 38 (S5 and S6) and displays the readout information on the display device 32 (S7). Fig. 6 shows the format of communication data from the memory circuit 38 to the camera main body 20. If no memory capacity is left, the controller 60 displays on the display device 32 (S9) a warning indicating that photographing cannot be performed, and prohibits photography (S10). If, however, sufficient memory capacity is left, the controller 60 reads the backup battery capacity of the memory cartridge 38 (S11) remaining. If the battery capacity is below a predetermined value, the controller 60 displays that photographing cannot be performed on the display device 32 and prohibits photographing (S9 and S10). If the battery capacity is over the predetermined value, the controller 60 displays that photographing can be performed (S13), waits for release (S14), and performs photographing/recording (i.e., writes an output from the image pickup device 52 in the memory cartridge 38) (S15). After recording (S15), the controller 60 updates information concerning the number of photographed frames, the remaining memory capacity, and the like (S16). The flow then returns to step S6, and the controller 60 checks the memory capacity and the backup battery capacity and waits for the next release. The flow may be modified such that a communication with the memory cartridge 38 is directly performed without checking the open/close state of the loading detection switch 26 immediately after the power source is switched on, and if the communication cannot be performed, non-loading or defective loading of the memory cartridge is warned to prohibit photographing. In the above embodiment, the switch 26 is separately provided to detect loading completion of the memory cartridge 38. Some of the electric contacts 28 of the camera main body 20, however, may be used to detect loading. In this case, two contacts 28a of a plurality of electric contacts 28 are used for loading detection, and remaining contacts 28b are used for communication. One of the contacts 28 for loading detection is to be grounded. When loading of the memory cartridge 38 is completed, the memory contacts 38a are electrically connected to the contacts 28. In accordance with whether an electrical signal (voltage value or current value) from the contact 28a is lower or higher than a predetermined level, the controller 60 of the camera main body 20 checks whether loading is completed. It is a matter of course that all the electric contacts 28 can be used for both loading detection and communication in such a manner that loading detection and data communication are performed at different timings. In this manner, the number of contacts 28 and 38a can be reduced. As is apparent from the above description, according to this embodiment, whether an image to be photographed can be recorded in the memory cartridge is automatically checked. Therefore, photographing can be performed more reliably and more rapidly. A solid-state camera according to another embodiment of the present invention will be described below with reference to Figs. 7 to 9. Fig. 7 is a block diagram showing an arrangement of the embodiment in which the present invention is applied to a solid-state camera using a solid-state memory apparatus similar to the memory cartridge 38 of the above embodiment as a still image recording medium. Referring to Fig. 7, a solid-state memory apparatus 65 comprising various IC memory devices and a CPU as a controller for controlling the IC memory devices can be detached from a camera main body 64. The solid-state memory apparatus 65 exchanges various information with the camera main body 64 via a predetermined bus line. The camera main body 64 comprises a photographic lens 66, a shutter 67, a solid-state image pickup device 68 such as a CCD, a signal processor 69, an A/D converter 70, a driver 71 for the image pickup device 68, a CPU 72 for controlling the overall system, a timing controller 73 for defining operation timings of the processor 69, the converter 70, and the driver 71 of the image pickup device 68, and a display/switch unit 74 including various switches and a display device. An operation of Fig. 7 will be described below with reference to a flow chart shown in Fig. 8. When a power switch of the camera main body 64 is turned on (S1), loading of the solid-state memory apparatus 65 is awaited (S2). The CPU 72 communicates with the loaded solid-state memory apparatus 65 and detects specification information (e.g., memory device classification, a transfer speed upper limit, and a remaining capacity shown in Fig. 6) of the solid-state memory apparatus 65 (S3). On the basis of this information, the CPU 72 determines operation speeds of the device 68, the processor 69, the converter 70, and the driver 71 and controls the timing controller 73. When a user depresses a shutter switch of the display/switch unit 74, the shutter 67 is opened, and an output from the image pickup device 68 is transferred to and written in the solid-state memory apparatus 65 at the above timings via the signal processor 69 and the A/D converter 70. Since a maximum continuous photographing speed is determined on the basis of the memory information obtained in step S3, the CPU 72 displays a possible maximum continuous photographing speed (S4), and monitors unloading of the solid-state memory apparatus 65 (S5). Fig. 9 is a block diagram showing an arrangement of still another embodiment of the present invention. In Fig. 9, the same reference numerals as in Fig. 7 denote the same parts. In this embodiment, image data digitized by an A/D converter 70 is temporarily stored in a frame memory 75. The image data temporarily stored in the frame memory 75 is read out from the frame memory 75 at a speed corresponding to a transfer speed of a memory device of a solid-state memory 75 and written in the solid-state memory apparatus 65. The above embodiment employs an arrangement in which when the solid-state memory 65 is loaded, the CPU 72 of the camera main body 64 inquires classification of a memory device used as the solid-state memory apparatus 65. The arrangement, however, may be made such that the above various types of information are mechanically set in the solid-state memory apparatus 65 and detecting means for detecting the mechanically set information may be provided for the camera main body 64. With this arrangement, the CPU need not communicate with the memory. In this embodiment, the maximum continuous photographing speed of the solid-state camera is limited to a write enable speed of the solid-state memory apparatus 65 and displayed. Therefore, operability of the solid-state camera, especially its continuous photographing operability is improved. In the above description, the solid-state camera has been exemplified. The present invention, however, can be generally applied to an apparatus for recording a certain kind of information in a detachable solid-state memory apparatus. As is apparent from the above description, according to this embodiment, information can be reliably recorded even when solid-state memory apparatuses using various types of memory devices are replaced and used. An embodiment of a solid-state memory apparatus according to the present invention will be described below with reference to Figs. 10 to 12. Note that the solid-state memory apparatus according to this embodiment is obtained by applying the present invention to the memory cartridge and the solid-state memory apparatus of the above embodiments. Fig. 10 is a block diagram showing an arrangement of the embodiment of the present invention. Referring to Fig. 10, a solid-state memory apparatus 65 according to this embodiment includes a status output line 76, an address/control input line 77, a clock input line 78, and a data input/output line 79. In the case of a serial signal, the data input/output line 79 is constituted by one signal line. In the case of a parallel signal, however, the data input/output line is constituted by signal lines in the number corresponding to the number of parallel signals. The solid-state memory apparatus 65 also includes a memory device 80, an address counter 81, an address preset circuit 82, a controller 83, a recognition code storing circuit 84, and a buffer 85. The input lines 77 and 78 and the input/output line 79 are connected to a solid-state camera via electric contacts as shown in Fig. 3. When the camera sends a predetermined command to the address/control input line 77, an operation mode of the solid-state memory apparatus 65 is set. That is, a clock signal is supplied to the clock input line 78 and a binary signal is supplied to the address/control input line 77 at timings shown in Fig. 11. A relationship between binary values at portions A, B, C, and D in Fig. 11 and the operation modes is shown in Table 1 below. Note that a maximum of 16 commands can be used by using four bits in this embodiment. In synchronism with a clock supplied from the clock input line 78, the controller 83 decodes a command from the address/control input line 77 and operates the respective sections by the designated operation mode. For example, in this embodiment, by storing memory addresses corresponding to the number of photographs in the address preset circuit 82, image data can be randomly accessed by designating the number of a photograph. That is, when the number of photographs to be read is designated, the address preset circuit 82 loads its start address in the address counter 81, and the address counter 81 sequentially counts up. In this manner, write or read of a storage area corresponding to the designated number can be performed. Similarly, a recognition code can be output from the recognition code storing circuit 84 to the camera main body. More specifically, when "0111" is supplied from the camera main body to the address/control input line 77, the controller 83 sends a command to the recognition code storing circuit 84 to output a stored recognition code. This recognition code is output to the camera main body via the output buffer 85 and the data input/output line 79. Note that the recognition code storing circuit 84 stores various types of specification information as shown in Fig. 6. Fig. 12 is a timing chart for explaining the above operation. A clock signal is normally supplied from the camera main body to the solid-state memory apparatus 65, and the internal circuit in the solid-state memory apparatus 65 operates in synchronism with this clock. A readout command "0111" of memory recognition code is supplied from the camera main body to the address/control input line 77 at the timing shown in Fig. 12. The first "0" is a start bit. The controller 83 interprets this command and sets a status bit at "H", thereby informing the camera main body that the data is effective. In synchronism with a clock, the controller 83 causes the recognition code storing circuit 84 to output storage data (in this embodiment, "00101100") to the data input/output line 79 via the buffer 85. A read-only memory or a combinational logic circuit, e.g., is used as the recognition code storing circuit 84. When this recognition code may be determined to include information such as a memory capacity, a transfer rate, and an image size, its length is not limited to 8 bits. In the above embodiment, the recognition code is read out by a command response scheme. An exclusive readout terminal, however, may be used to read out the code. In addition, in the above embodiment, data exchange is performed by four types of signal lines. Data exchange, however, may be performed by using a larger or smaller number of signal lines. As is easily understood from the above description, according to the embodiments of the present invention, regardless of an outer shape or standardization of an interface, a new electronic device can be used to achieve a large capacity and a high speed.

Claims: A solid state camera (10) for use with a detachable solid state image storage means (12,38,65) which camera comprises: detection means (28,58,60,72), co-operable with said solid state image storage means (38,65) to detect from indications provided by said solid state image storage means (38,65) one or more of the following respective parameters: (a) a remaining memory storage capacity of said solid state image storage means (38,65) at time of loading of said detachable solid state image storage means and directly following each exposure; (b) a remaining power capacity of a back-up power source (-) incorporated in said solid state image storage means (38,65); and (c) a maximum write speed for recording into a memory storage of said solid state image storage means (38,65) image data produced by said camera; and camera operation control means (60,72) responsive to said detection means (28,58,60,72) to control operation of said camera, to perform the following operations: (i) to inhibit operation and give warning prior to exposure release in the event that it is detected that either there is no remaining memory storage capacity, or the remaining power capacity is below a predetermined level; and/or (ii) to control a rate of transfer of image data from said camera (10) to said solid state image storage means (38,65) in dependence upon the maximum write speed both indicated by said solid state image storage means (38,65) and detected by said detection means (28,58,60,72); and/or (iii) to control a speed of continuous photography in dependence upon said maximum write speed which is both indicated by said solid state image storage means (38,65) and detected by said detection means (28,58,60,72). A camera as claimed in claim 1, wherein: said detection means (28,58,60,72) is operable to detect all of said respective parameters (a) to (c); and said camera operation control means (60,72) is operable to perform all of said operations (i) to (iii). A camera as claimed in either of claims 1 and 2, wherein said detection means (28,58,60,72) and said camera operation control means (60,72) comprise a microcomputer (60,72). A camera as claimed in any preceding claim wherein said detection means (28,58,60,72) comprises: access means (60,72) for accessing specification data stored in said solid state image storage means (38,65); and interface means (28,58) for receiving said specification data; which specification data shall provide said indications of the one or more respective parameters (a) to (c). A camera as claimed in claim 4, wherein said access means (60) is operable to read-out said specification data stored in said solid state image storage means (38). A camera as claimed in claim 5, wherein said access means (60) is operable to read-out sequentially specification data indicative of parameters (a) and (b) respectively. A camera as claimed in claim 6, comprising up-date means (60) which up-date means is co-operable with said solid-state image storage means (38) to up-date said respective parameters (a) and (b) following operation of said access means (60) and following a recordal of image data in said solid state image storage means (38). A camera as claimed in any preceding claim, in which said detection means (28,58,60) is co-operable with said solid state image storage means (38) to detect at least either one of said respective parameters (a) or (b), said camera having a display panel (32), and said camera operation control means (60) is cooperable with said display panel (32) to cause said display panel (32) to display a warning indication in the event that it is detected by said detecting means (28,58,60) that either there is no remaining storage capacity, or the remaining power capacity is below said predetermined level, respectively. A camera as claimed in any preceding claim, wherein said detection means (28,58,60) includes means, cooperable with said detachable solid state image storage means (12,38,65) for detecting classification information mechanically set in said solid state image storing means (38,65) and including said maximum write speed. A camera as claimed in any preceding claim and including a frame store buffer means (75) for storing image data produced by said camera prior to transfer to said solid state image means (65). A camera as claimed in any preceding claim, including a loading detection means (26) for detecting completed loading of said detachable solid state image storage means, and warning means (32) responsive to said loading detection means (26) to give warning in the event that loading is incomplete. A camera as claimed in claim 11, wherein said loading detection means (26) comprises a loading detection switch (26). A detachable solid state image storage means (65) for use with, and attachable to, a solid state camera as claimed in claim 1, which image storage means (65) includes: image data memory storage (80) for storing image data; and information means (79, 84, 85) for storing any one or more of the respective parameters (a) to (c) recited in claim 1, which information means (79, 83, 84, 85) is co-operable with said solid-state camera and is effective to transfer indication of said one or more parameters from said image storage means (65) to said solid state camera, to control automatic setting and operation thereof. Image storage means, as claimed in claim 13, wherein said information means (79, 84, 85) comprises a recognition code storage (84) containing transferable indication data for any one or more of the respective parameters (a) to (c). A loaded camera comprising the cooperable combination of a solid state camera as claimed in claim 1 and a detachable solid stage image storage means (65) as claimed in either of claims 13 or 14.

Inventors: DATE NOBUAKI, HORII HIROYUKI, KAWAMURA HIDEAKI, MIMURA TOSHIHIKO, MURATA YOSHITAKA, OZAKI SEIICHI, SUZUKI TAKASHI, TAKAIWA KAN, TOJO AKIHIKO, DATE, NOBUAKI, HORII, HIROYUKI, KAWAMURA, HIDEAKI, MIMURA, TOSHIHIKO, MURATA, YOSHITAKA, OZAKI, SEIICHI, SUZUKI, TAKASHI, TAKAIWA, KAN, TOJO, AKIHIKO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1989
Main classification: H04N5
IPC codes: H04N5, H04N1