Dielectrically isolated semiconductor substrate

Abstract: A dielectrically isolated semiconductor wafer substrate includes first and second semiconductive layers bonded to each other by a direct bonding tech­ nique in such a manner that an insulative layer is sand­ wiched therebetween. The first semiconductive layer is a first silicon layer having a (100) or (110) crystal surface orientation, while the second semiconductive layer is a second silicon layer having a (111) crystal surface orientation. Thereafter, a peripheral portion of the resultant substrate is removed, and a substrate of a slightly smaller size is obtained which is provided with an additionally formed new orientation flat.

Description: The present invention relates to a semiconductor wafer direct bonding technique and, more particularly, to a pair of semiconductor wafers bonded to each other to have a dielectrically isolated structure, and a method of manufacturing the same. A substrate comprising two wafers with an insulating layer sandwiched therebetween is described in EP-A-0 217 288. A method for joining silicon wafers in a stacked structure is disclosed in EP-A-0 226 772. One technique for directly bonding a pair of semiconductor substrates such as silicon wafers to each other at clean, mirror-polished surfaces thereof to provide an integrated wafer has been developed. This technique is well known as "Silicon-to-Silicon direct bonding technique". When this direct bonding technique is used, various types of semiconductor wafers can be fabricated. For example, when a silicon wafer having a resistivity of 1/1,000 Ω·cm and a silicon wafer having a resistivity of several hundreds Ω·cm are directly bonded to each other, a silicon wafer having a laminated structure of low- and high-resistivity semiconductor layers can be easily obtained. When one or both of these wafers to be bonded to each other are subjected to surface-oxidation, a wafer having a dielectrically isolated silicon laminated structure can be obtained. When a dielectrically isolated silicon substrate is fabricated using the direct bonding technique, the following advantages can be obtained as compared with other isolation technologies such as p-n junction isolation, conventional dielectric isolation using a thick polysilicon body, and an SIMOX method wherein oxygen ions are implanted to inside the silicon bulk to form an oxide film therein. That is, (1) the quality of the silicon layer serving as an active layer can be kept to be excellent, (2) the thickness of the silicon layer can be arbitrarily set, and (3) manufacturing processes can be relatively easily performed. Because of the above reasons, the above-mentioned "Silicon-to-Silicon direct bonding technique" is widely utilized for formation of a dielectrically isolated and directly bonded pair of silicon substrates having different characteristics. The dielectrically isolated substrate fabricated by the direct bonding method, however, has the following problems. The first problem is a warp of bonded substrates. Two silicon substrates are directly bonded during a thermal treatment. When a substrate temperature returns to room temperature, a stress is generated between the silicon substrates and a silicon oxide film sandwiched therebetween due to a difference in thermal shrinkage. Since the thermal expansion coefficient of the silicon substrates is larger than that of the silicon oxide film, a shrinkage of the silicon substrates due to decrease in temperature is more considerable. As a result, at room temperature, a tensile stress is generated in the silicon substrates, while a compressive stress is generated in the silicon oxide film. In general, one silicon substrate on which circuit elements such as transistors are formed is polished so as to be thinner than the other silicon substrate serving as a support base layer. These facts result in warpage of the substrate structure. Such a warp in the directly bonded silicon substrates prevents effective execution of the following wafer manufacturing process such as a PEP process. In particular, as an increase in diameter of the wafer and miniaturization of circuit elements progress, the above problems become more serious. The second problem is that it is difficult to achieve bonding of peripheral portions of the directly bonded semiconductor wafers without failure. Initially manufactured silicon wafers have poor parallel geometry in their peripheral portions. If two silicon substrates with such poor parallel geometry are bonded directly, incomplete bonding occurs in their peripheral portions, and their mechanical strength is decreased (particularly in the peripheral portion of a thinner wafer). The decrease in mechanical strength causes a problem that the wafer may be broken in the following circuit element formation steps. In order to solve the above problems, it is necessary to remove a predetermined area of the incompletely bonded peripheral wafer portions, and to use only completely bonded central wafer portion. However, when the peripheral wafer portion is removed, an orientation flat formed therein is also removed. If no orientation flat is provided, accurate fabrication of element isolation V-shaped groove and integrated circuit patterns onto the wafer in the following steps cannot be performed. It is therefore an object of the present invention to provide a new and improved dielectrically isolated and bonded semiconductor substrate having excellent basic characteristics, and a method of manufacturing the same. In accordance with the above object, the present invention provides a semiconductor substrate comprising a first silicon layer, and a second silicon layer bonded to said first silicon layer through an insulative layer sandwiched between said first and second silicon layers, said first silicon layer being thinner than said second silicon layer, wherein said silicon layer has a (100) or (110) crystal surface orientation, and said second silicon layer has a (111) crystal surface orientation. The present invention and its objects and advantages will become more apparent in a detailed description of a preferred embodiment to be presented hereinafter. In the detailed description of a preferred embodiment of the present invention presented below, reference is made to the accompanying drawings of which: Figs. 1A to 1E are diagrams showing main sectional views of main structures obtained in main processes for a method of manufacturing a dielectrically isolated and directly bonded silicon wafer according to a preferred embodiment of the present invention; Fig. 2 is a diagram showing a plan view of a wafer obtained by directly bonding an initially prepared pair of silicon substrates; Fig. 3 is a diagram showing a sectional structure along the III - III of the wafer shown in Fig. 2; Fig. 4 is a diagram showing a plan view of a wafer of a slightly smaller size obtained by removing a peripheral portion of the wafer shown in Fig. 2; Fig. 5 is a diagram showing a sectional structure along the III - III of the wafer shown in Fig. 2; Figs. 6A to 6B are diagrams showing main sectional views of main structures obtained in main processes of a modification of the manufacturing method of the dielectrically isolated and directly bonded silicon wafer shown in Fig. 1; and Figs. 7A and 7B are diagrams showing main sectional views of main structures obtained in main processes of another modification of the manufacturing method of the dielectrically isolated and directly bonded silicon wafer shown in Fig. 1. Referring now to Fig. 1A, first, a pair of semiconductor wafers having mirror-polished surfaces and different characteristics are prepared. In this embodiment, a wafer 10 is a silicon substrate having an n-type conductivity, a resistivity of 20 to 30 Ω·cm, and a diameter of 4 inches (1 inch = 2.54 cm). A wafer 12 is a silicon substrate having a p-type conductivity, a resistivity of 0.01 to 0.02 Ω·cm, and a diameter of 4 inches. The thickness of the silicon substrate 10 is 500 µm. Silicon oxide films 14a and 14b each having a thickness of 1 µm are formed on the upper and lower surfaces of the silicon substrate 10 by thermal oxidation. The thickness of the silicon substrate 12 is 500 µm. It should be noted that the crystal surface orientation of the silicon substrate 12 is different from that of the silicon substrate 10: the surface orientation of the silicon substrate 10 is (100), and the surface orientation of the silicon substrate 12 is (111). These substrates 10 and 12 are bonded to each other through the insulating thin film 14b sandwiched therebetween using a direct bonding technique. Therefore, a bonded wafer substrate 16 shown in Fig. 1B is obtained. In Fig. 1A, in order to clearly show the difference between the crystal surface orientations of the substrates 10 and 12, reference numerals "(100)" and "(111)" are written for the sake of convenience. First, the first and second silicon substrates 10 and 12 are subjected to a hydrophilic surface formation process. More specifically, these substrates 10 and 12 are cleaned by an H₂SO₄ - H₂O₂ solution mixture, aqua regia, or the like. Thereafter, the resultant substrates 10 and 12 are cleaned with water for about ten minutes, and are dried by a spinner. Thereafter, these substrates 10 and 12 are brought into direct contact with each other at their mirror-polished surfaces in a clean atmosphere at room temperature without the use of any bonding material. The bonding strength between the substrates 10 and 12 is further improved after they are thermally treated at a temperature of, e.g., 200°C or more. The thermal treatment in this case may be carried out in an atmosphere of, e.g., oxygen, hydrogen, an inert gas, steam, or a mixture of these gases. According to this embodiment, H₂SO₄ - H₂O₂ and HCℓ - H₂O₂ was used to clean the substrates 10 and 12. The thermal treatment for the substrates 10 and 12 was carried out in a nitrogen atmosphere containing a small amount of oxygen at a temperature of 1,100°C for about two hours. The bonded silicon wafer 16 is subjected to an additional orientation flat formation process. More specifically, as shown in Fig. 2, the wafer 16 obtained by directly bonding the initially prepared pair of silicon substrates 10 and 12 has an orientation flat 18. The orientation flat 18 has a <011> crystallographic axis. An entire sectional structure of the wafer 16 along the III - III in this case is shown in Fig. 3. In a plan view of the wafer 16 in Fig. 2, a peripheral wafer portion 20 hatched for convenience tends to have poor bonding characteristics as compared with the central remaining portion of the wafer. After the substrates 10 and 12 are directly bonded, in order to remove the peripheral portion 20, the wafer 16 is cut along a virtual cutting line 22 and a wafer 16′ of a slightly smaller size is obtained, as shown in Fig. 4. In this embodiment, the wafer 16′ has a diameter of, e.g., 3 inches. In the wafer 16′, a new orientation flat 24 is formed. This new orientation flat 24 has a <011> crystallographic axis in the same manner as in the original orientation flat 18. The sectional structure of the wafer 16 along the V - V in this case is shown in Fig. 5. When the new orientation flat 24 is formed in the cut wafer 16′, before the peripheral portion 20 of the wafer 16 is removed, a line mark (not shown) parallel (or perpendicular) to the original orientation flat 18 is marked on the surface of the wafer 16. After the peripheral portion 20 of the wafer 16 is removed, the new orientation flat 24 is formed on the basis of the line mark. In this case, the deviation allowance of an offset from the reference crystallographic axis along a formation direction of the new orientation flat 24 is about ±5°. Referring now to Fig. 1, after the above-mentioned additional orientation flat formation process is completed, a surface of a first silicon substrate 10′ (which functions as an active layer) serving as a prospective element formation region of the wafer 16′ is polished. As a result, the thickness of the silicon substrate 10′ is decreased to 60 µm. At this time, the silicon substrate 10′ has a polished top surface 30 from which the insulating thin film 14a is removed, as shown in Fig. 1C. As shown in Fig. 1D, element isolation V-shaped grooves 32 and 34 are formed in the polished surface 30 of the first silicon substrate 10′ by well-known anisotropic etching. Then, isolation insulating thin films 36 and 38 are respectively formed in the V-shaped grooves 32 and 34 by thermal oxidation or the like, as shown in Fig. 1E. Then, polysilicon layers 40 and 42 are respectively buried in the grooves 32 and 34, and therefore, a dielectrically isolated substrate is completed. According to a manufacturing technique of the present invention, the pair of silicon substrates 10 and 12 to be directly bonded have different crystal surface orientations: the silicon substrate 10 has a (100) surface orientation; and the silicon substrate 12 has a (111) surface orientation. Such a difference between the crystal surface orientations of the first and second substrates 10 and 12 effectively suppresses or prevents a warp in the peripheral portion 22 of the wafer 16 formed by directly bonding the substrates 10 and 12. The reason for this is as follows. As described above, a cause of the warp of the dielectrically isolated substrate is a stress generated due to a difference between thermal expansion coefficients of the silicon and oxide film. A degree of the warp when a given stress is generated is determined in accordance with a Young's modulus and Poisson's ratio of a material which constitutes a substrate. In the case of a dielectrically isolated substrate, the Young's modulus and Poisson's ratio of the second silicon layer serving as a support base largely affect the degree of the warp, since the second layer is thinner than the other. In this case, a state of only a two-layered structure wherein a silicon oxide film is formed on a silicon substrate is considered. A warp X of this substrate is defined using the Young's modulus E, Poisson's ratio ν, and proportion constant c of the silicon, as follows. X = c·(1 - ν)/E In a silicon substrate having a (100) surface orientation, E = 1.31 × 10¹² dyn/cm² 1 dyn/cm² = 0.1 Pa and ν = 0.28. On the contrary, in a silicon substrate having a (111) surface orientation, E = 1.70 × 10¹² dyn/cm², and ν = 0.26. The warp of the (100) silicon substrate is compared with that of the (111) silicon substrate in accordance with the above values. When the warp of the former substrate is "1", that of the latter substrate is "0.79". In other words, the warp of the (111) silicon substrate is smaller than that of the (100) silicon substrate. Thus, when the thick second silicon layer serving as a base has a (111) crystal surface orientation and the first silicon layer serving as an active layer has a (100) crystal surface orientation, the warp is smaller than the case wherein the surface orientations of both the first and second silicon layers are (100). When the first silicon layer has a (110) crystal surface orientation, the same effect can be obtained. In particular, the above-mentioned function is important in a dielectrically isolated substrate obtained by a direct bonding technique. This is because, as described above, the surface orientation of the active layer is generally selected to be (100) for reasons associated with manufacturing processes and element design. However, in the direct bonding technique, the surface orientation of the second silicon layer can be selected not taking the surface orientation of the first silicon layer serving as an active layer into consideration. Even if a spin-on-glass bonding method, an anodic bonding method utilizing a voltage application, or the like is employed besides the direct bonding method to obtain a dielectrically isolated substrate, the same effect can be obtained, as a matter of course. The present inventors manufactured some samples corresponding to the polished wafer 16′ shown in Fig. 1C in practice, and an experiment was performed using the obtained samples. Warps in the peripheral portions of the samples were measured. As a result, in wafer samples having conventional arrangements wherein the surface orientation of the second silicon substrate 12 to be directly bonded to the first silicon substrate 10 is set to be the same as that of the first silicon substrate 10, i.e., (100), the warps in their peripheral portions fell within the range of 11.3 µm to 15.3 µm. The average value of the warps was 13.2 µm. On the contrary, the above-mentioned measurement was performed for experimental samples wherein the first and second substrates 10 and 12 had different surface orientations according to a concept of the present invention. As a result, the warps of the peripheral portions fell within the range of 8.4 µm to 10.3 µm, and the average value was 9.8 µm. In addition, the present inventors manufactured some samples corresponding to the completed dielectrically isolated wafer shown in Fig. 1E in practice, and an experiment was performed using these samples. Warps in the peripheral portions of the samples were measured. As a result, in wafer samples having conventional arrangements wherein the surface orientation of the second silicon substrate 12 to be directly bonded to the first silicon substrate 10 is set to be the same as that of the first silicon substrate 10, i.e., (100), the warps in their peripheral portions fell within the range of 10.3 µm to 15.1 µm. The average value was 12.7 µm. On the contrary, the above-mentioned measurement was performed for experimental samples wherein the first and second substrates 10 and 12 had different surface orientations according to a concept of the present invention. As a result, the warps of the peripheral portions fell within the range of 8.0 µm to 10.0 µm, and the average value was 9.5 µm. These experimental results apparently demonstrate the superiority in warp prevention of the wafer obtained by the direct bonding manufacturing technique of the present invention. Thus, an increase in diameter of the direct bonding silicon wafer having the dielectrically isolated structure, and miniaturization of integrated circuit elements on this wafer substrate are facilitated. Although the crystal surface orientation of the first silicon substrate 10 serving as an active layer is set to be (100) in this embodiment, the surface orientation may be (110). However, the (100) crystal surface orientation is preferably set in view of excellent basic characteristics of circuit elements when metal insulator semiconductor field effect transistors are formed on the substrate 10 as circuit elements. According to the above embodiment, after the first and second substrates 10 and 12 are directly bonded, an outer circumferential surface region (which tends to be insufficiently or incompletely bonded even if the manufacturing technique of the present invention is employed, as described above) 22 of the integrated wafer 16 is removed. This removal allows an improvement of the physical strength of the peripheral portion of the dielectrically isolated direct bonding wafer 16′ to be finally obtained. The ground wafer 16′ is provided with a new orientation flat 24 by an additional orientation flat formation process. This new orientation flat allows effective formation of the integrated circuit patterns on the dielectrically isolated direct bonding wafer 16′ to be finally obtained. When a dielectrically isolated wafer is formed by directly bonding a pair of silicon substrates 10 and 12, in order to suppress generation of a warp between the substrates 10 and 12, the impurity concentration of silicon substrate 12 may be partially increased. When the impurity concentration of the silicon substrate 12 is partially increased, the impurity concentration in a partial region including at least a surface region (a surface to be bonded) subjected to direct bonding is increased. More specifically, before the direct bonding process, impurities are doped in at least the surface portion to be bonded of the silicon substrate 12 by a doping technique such as diffusion, as indicated by arrows 50 in Fig. 6A. As a result, as shown in Fig. 6B, the impurity concentration of a surface portion 52 of the silicon substrate 12 is increased. Thereafter, when the direct bonding processing is performed, generation of the warp of the dielectrically isolated wafer 16′ can be effectively suppressed. Alternatively, as shown in Fig. 7A, a BPSG (Boron-phosphorus silicate glass) layer 54 is formed on the bonding surface of the silicon substrate 12 before the substrates are subjected to direct bonding, so that generation of warp in the dielectrically isolated wafer 16′ can be effectively suppressed. In this case, the BPSG layer 54 serves to suppress its warp and distortion of substrate 12. Thereafter, as shown in Fig. 7B, when the direct bonding processing is performed, warp generation in the dielectrically isolated wafer 16′ can be effectively suppressed.

Claims: A semiconductor substrate comprising a first silicon layer (10), and a second silicon layer (12) bonded to said first silicon layer through an insulative layer (14b) sandwiched between said first and second silicon layers (10, 12), said first silicon layer (10) being thinner than said second silicon layer (12), characterized in that said first silicon layer has a (100) or (110) crystal surface orientation, and that said second silicon layer has a (111) crystal surface orientation. The substrate according to claim 1, characterized in that said first silicon layer (10) serves as an active layer on which integrated circuit elements are formed, while said second silicon layer serves as a base layer for supporting said active layer. The substrate according to claim 2, characterized in that said insulative layer includes a silicon oxide thin film (14b). The substrate according to claim 3, characterized in that said first and second silicon layers (10, 12) are provided with an orientation flat (24). A method of manufacturing a dielectrically isolated semiconductor substrate, comprising the steps of mirror polishing respective first major surfaces of first and second silicon wafers (10, 12); forming an insulative layer (14b) on said first major surface of said first silicon wafer (10); bonding said first major surfaces of said first and second silicon wafers by a thermal treatment so that said insulative layer (14b) is sandwiched therebetween to provide a bonded substrate; polishing the second major surface of said first silicon wafer (10), so that said first silicon wafer (10) is thinner than said second silicon wafer (12); and removing a peripheral portion of said bonded substrate to provide a processed substrate (16′ ), characterized in that said first silicon wafer has a (100) or (110) crystal surface orientation and that said second silicon wafer (12) has a (111) crystal surface orientation. The method according to claim 5, characterized in that each of said first and second silicon wafers (10, 12) has an initially formed orientation flat (18). The method according to claim 6, characterized in that said initially formed orientation flat (18) is removed when the peripheral portion of said bonded substrate (16) is removed. The method according to claim 7, characterized by further comprising the step of additionally forming an orientation flat (24) on said processed substrate (16′ ). The method according to claim 8, characterized in that said first silicon wafer (10) serves as an active layer, integrated circuit elements being formed in said polished second major surface thereof. The method according to claim 9, characterized in that insulating layers (36, 38, 40, 42) serving as insulating isolation layers of said integrated circuit elements are formed in said polished second major surface of said first silicon wafer (10).

Inventors: FUKUDA KIYOSHI C O PATENT DIVI, FURUKAWA KAZUYOSHI C O PATENT, NAKAGAWA AKIO C O PATENT DIVIS, TANZAWA KATSUJIRO C O PATENT D, WATANABE KIMINORI C O PATENT D, YAMAGUCHI YOSHIHIRO C O PATENT, FUKUDA, KIYOSHI C/O PATENT DIVISION, FURUKAWA, KAZUYOSHI C/O PATENT DIVISION, NAKAGAWA, AKIO C/O PATENT DIVISION, TANZAWA, KATSUJIRO C/O PATENT DIVISION, WATANABE, KIMINORI C/O PATENT DIVISION, YAMAGUCHI, YOSHIHIRO C/O PATENT DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: H01L21
IPC codes: H01L27, H01L21