Power saving low frequency power amplifier

Abstract: A power saving low frequency power amplifier includes a first stage amplifier (11) for receiving and amplify­ ing data signal, a second stage amplifier (12) for amplifying the output of the first stage amplifier (11), and a power amplifier (13) for amplifying the output of the second amplifier (12). The first stage amplifier (11) is operated in response to a driving current. The second stage amplifier (12) receives a first idling current (I IDd ) for obtaining a predetermined amplification, and the power amplifier (13) receives a second idling current (I IDf ) for obtaining a predetermined amplification. A first switching circuit (15) is provided for making and braking paths for the first (I IDd ) and second (I IDf ) idling currents provided for producing a power save signal to the first switching means (15) for braking the first switching circuit (15) when the power save signal is present.

Description: The present invention relates to a power-saving low-frequency power amplifier, and more particularly, to a circuit adapted to restrict the power consumption in an amplifier circuit of low frequency power in a system having a waiting condition for an irregular time interval. Recently, many developments have been made on pocket size receiver, for example, cordless telephones, radio pagers or portable telephones, which can effect wireless communication between a base unit and a handset unit. The handset unit of the above described type is generally operated by a battery, and usually has a waiting (or stand-by) state during which the circuit power is cut off so as to prevent the power consumption therein, and a operating (or in-use) state during which the circuit is energized to effect the amplification of the received signal. The setting of the stand-by state or operating state is effected by a control signal produced from CPU (central processing unit). In Fig. 1, a block diagram of a prior art power-saving low-frequency power amplifier is shown, which is employed in a handset unit such as in a handset of cordless telephone. In Fig. 1, the handset unit includes an antenna 1 for receiving electric waves 8 from the base unit (not shown), a processing circuit 2 for processing the received signals, a low frequency power amplifier 3 for amplifying low frequency signal, a speaker 4 connected to low frequency power amplifier 3 through an output coupling capacitor Co, a CPU 5 and a switching circuit 6 coupled with a power source 7 such as a battery. By the control of CPU, the electric power from power source 7 is supplied through switching circuit 6 to processing circuit 2, amplifier 3, CPU 5, and other circuits. When the handset unit employs an intermittent power saving system, CPU 5 produces a control signal which is a pulse signal having a predetermined frequency. During the pulse period, it is detected whether any data signal is being transmitted to the handset unit, or not, at received signal processing circuit 2. If no data signal is being received, switching circuit 6 continues to provide no electric power to low frequency power amplifier 3. If, on the other hand, data signal is received during the pulse period, CPU 5 controls switching circuit 6 to start providing electric power to low frequency power amplifier 3. Thus, output coupling capacitor Co for DC cutting is charged rapidly. By such a rapid electric charge in the output coupling capacitor Co, speaker 4 produces short but annoying shock noise each time when the low frequency power amplifier 3 is powered. When the handset unit employs an active/inactive power saving system, CPU 5 produces the control signal which is an ID signal indicating the presence and absence of the data signal from the base unit. When the ID signal from the base unit is not detected, the switching circuit 6 provides no electric power to the low frequency power amplifier 3 to maintain the amplifier 3 in inactive condition. On the other hand, when the ID signal from the base unit is detected, the switching circuit 6 provides electric power to the low frequency power amplifier 3 to switch on the amplifier 3 in active condition. When the low frequency power amplifier 3 is powered on, speaker 4 produces the same annoying shock noise due to the rapid electric charge in the output coupling capacitor Co. As described above, although the low frequency power amplifier 3 is switched between power on and power off conditions to save the battery power while the handset unit is not in use, undesirable shock noise is produced from the speaker 4 each time the low frequency power amplifier 3 is powered on. EP-A-0 106 953 discloses an amplifier in which noise due to undesired oscillation of an amplifier circuit during the period of source voltage setting up is avoided. To this end a supply voltage detector having a hysteresis is used such that during the period of power turn on and power turn off no biasing current is applied to the amplifier circuit. EP-A-0 043 707 discloses an amplifier having a main amplifier stage and an inverse amplifier stage. After turn on of the power switch the main amplifier stage is activated and thereafter the inverse amplifier stage is activated. The voltage difference between the main and the inverse stage amplifiers is zero the main amplifier stage starts the operation when a stable condition is achieved so that pop-noises are avoided. EP-A-0 159 079 discloses an audio amplifier control circuit capable of delaying the audio amplifier switch-on time upon each new switching on of the equipment in order to reduce the "switch-on noise" occurring in case of subsequent switching on. It is an object of the invention to provide an improved power saving low frequency power amplifier which will not produce any shock noise when the low frequency power amplifier is powered on. This object is achieved by a power saving low frequency power amplifier as defined in claim 1; the dependent claims are related to further developments of the invention. Furthermore, power saving low frequency power amplifier according to the present invention further comprises a second switching means for restricting the supply of said driving current to said first stage amplifier when said power saving signal is present. Moreover, a power saving low frequency power amplifier according to the present invention further comprises a third switching means for supplying two kinds of DC current to said first stage amplifier in accordance with said power saving signal. These and other objects and features of the present invention will become apparent from the following description taken in conjunction with preferred embodiments thereof with reference to the accompanying drawings, throughout which like parts are designated by like reference numerals, and in which: Fig. 1 is a block diagram of a prior art telephone handset employing power-saving low frequency power power amplifier; Fig. 2 is a block diagram showing a principle of a power-saving low-frequency power amplifier according to a first embodiment of the present invention; Fig. 3 is a circuit diagram of of the circuit according to the first embodiment; Fig. 4 is a detailed circuit diagram of the circuit according to the first embodiment; Fig. 5 is a block diagram similar to Fig. 2, but showing a second embodiment of the present invention; and Fig. 6 is a circuit diagram similar to Fig. 3, but according to the second embodiment of the present invention. Referring to Fig. 2, a block diagram of a power saving low frequency power amplifier according to a first embodiment of the present invention is shown. It is to be noted that although the circuits shown in the preferred embodiments are described as employed in a handset unit of a cordless telephone for receiving data signal, such as audio signal, from the base unit (not shown), such circuits can be employed in any other unit which is powered by battery, or the like, for the purpose of saving power. The power saving low frequency power amplifier according to the present invention employs an active/semi-inactive power saving system. The data signal emitted from the base unit is received by an antenna (not shown) in the handset unit and is suitably processed in a processing circuit (not shown). The processed data signal from the processing circuit is then applied to a power saving low frequency power amplifier of the present invention which comprises input circuit 9 for receiving the processed data signal, a first stage amplifier 11, second stage amplifier 12 and power amplifier 13. The output signal from power amplifier 13 is applied through an output coupling capacitor Co to speaker 4. According to the preferred embodiment, amplifiers 11, 12 and 13 are formed by a monolithic IC 10, as diagrammatically shown in Fig. 2. The output of power amplifier 13 is fedback to the first stage amplifier 11 through a suitable feedback circuit 19. The power saving low frequency amplifier according to the first embodiment further comprises a first switching circuit 15 for controlling the supply of idling currents I IDd and I IDf to amplifiers 12 and 13, respectively, a second switching circuit 14 which is provided in input circuit 9 and a third switching circuit 17 for supplying a constant operating current to first stage amplifier 11. The first, second and third switching circuits 15, 14 and 17 are preferably formed by analog switches and are controlled by power saving signal PSS produced from CPU 16 in response to the detection of ID signal indicating that data signal is being transferred from the base unit to the handset unit. Thus, during the handset being used for communication with the base unit, the power saving signal PSS is absent, and during the handset being not used for communication with the base unit, the power saving signal PSS is present. Referring to Fig. 3, details of the switching circuits 15, 14 and 17 are shown in connection with surrounding circuits. The switching circuit 15 is an ON/OFF switch and is coupled with a constant current source I2 which is provided for supplying idling current I ID to amplifiers 12 and 13. The switching circuit 17 is also an ON/OFF switch and is coupled with a constant current source I1 which is provided for supplying a portion of constant driving current I COM to the first stage amplifier I1. Another constant current source I3 is connected parallel to constant current source I1 and switch 17. The current source I1 is arranged to supply (1 1 n ).I COM , and the current source I3 is arranged to supply 1 n .I COM . The switching circuit 14 is a two position switch having an arm c connect-able to either one of contacts a and b. The arm c is connected to non-inverting input of operational amplifier 10, contact a is connected through input coupling capacitor Ci to data signal source V such as the signal processing circuit, and contact b is connected to battery Ba. A bias resistor Rc is connected between contacts a and b. The capacitor Ci, resistor Rc, battery Ba and switching circuit 14 define input circuit 9. The feedback circuit 19 is defined by resistor Rf1 connected between the output P and inverting input of operational amplifier 10 and a series connection of resistor Rf2 and capacitor Cf connected between inverting input and ground. In operation, when the power saving signal PSS is not present, meaning that the handset is in use mode, the switching circuits 15 and 17 are both turned on, and the switching circuit 14 is turned to contact a, simultaneously, as shown in Fig. 3. Thus, by the turn on of switch 15, constant current source I2 is activated for supplying idling current I ID to amplifiers 12 and 13. By the turn on switch 17, the constant current source I1 is activated for supplying a portion of constant driving current I COM to the first stage amplifier 11 so that, together with the current from a current source I3, the first stage amplifier 11 is supplied with a full driving current I COM . By the turning of switch 14 to contact a, data signal is applied to non-inverting input of operational amplifier 10. When the power saving signal PSS is present, meaning that the handset is in stand-by mode, the switching circuits 15 and 17 are both turned off, and the switching circuit 14 is turned to contact b, simultaneously. By the turn off of switch 17, amplifier 12 receives minimum driving current 1 n .I COM for driving the first stage amplifier 11 which is maintained powered on, but has no ability to amplify the input signal. By the turn off of switch 15, idling currents I IDd and I IDf to amplifiers 12 and 13, respectively, are cut off. Accordingly, during the presence of the power saving signal PSS, the power consumed in amplifiers 11, 12 and 13 is greatly reduced to save the electric power. Also, during the presence of the power saving signal PSS, since the power to amplifiers 11, 12 and 13 is not completely cut off, the DC voltage level at output P of amplifier 13 is maintained the same as the DC voltage level observed at output P during the absence of the power saving signal PSS. Thus, the output coupling capacitor Co is maintained in charged condition even after the presence of the power saving signal PSS, resulting in no shock noise produced from speaker 4 in response to the mode change, i.e., switching of switching circuits 15 and 17. The same can be said even when the feedback circuit 19 is present, since the negative feedback operation is never influenced even after the idling current IDf is cut off. Also, during the presence of the power saving signal PSS, switching circuit 14 is turned to contact b so that noiseless signal is applied to operational amplifier 10 to improve the S/N ratio. Referring to Fig. 4, a detailed circuit diagram of the power saving low frequency power amplifier according to the first embodiment of the present invention is shown. The circuit shown is an SEPP (single ended pushpull) type power amplifier circuit. The input circuit 9 is the same as that shown in Fig. 3. When the power saving signal PSS is present, the switching circuit 14 is turned to be connected directly to the battery Ba, as shown in Fig. 4, to provide noiseless DC voltage signal to the first stage amplifier 11. When the power saving signal PSS is absent, switching circuit 14 is so turned as to receive input data signal through input coupling capacitor Ci, and the data signal is applied to the first stage amplifier 11. The first stage amplifier 11 is a differential amplifier which comprises PNP transistors Q₁₁₁-Q₁₁₄, NPN transistors Q₁₁₅-Q₁₁₈, and NPN transistors Q₁₇₁, Q₁₇₂ operating as a current source. A switch SW4 corresponds to switching circuit 17. When switch SW4 is opened in response to the presence of the power saving signal PSS, the differential amplifier 11 is driven with a portion 1 n ·I COM of the necessary driving current I COM . Thus, the differential amplifier loses or reduces the amplifying ability, but merely produces from collectors of transistors Q₁₁₃ and Q₁₁₇ a DC voltage signal corresponding to input DC voltage signal from the input circuit 9. When the power saving signal PSS is absent, switch SW4 is turned on so that the differential amplifier 11 operates with full driving current I COM with necessary amplification. The second stage amplifier 12 comprises PNP transistors Q₁₂₁-Q₁₂₄ and NPN transistors Q₁₂₅-Q₁₂₁₀, and an idling circuit 18 for improving the switching distortion. Idling circuit 18 includes PNP transistors Q₁₅₁, Q₁₅₂, NPN transistors Q₁₅₃, Q₁₅₄, bias resistors Ra1-Ra4 and a switch SW3. When the power saving signal PSS is present, switch SW3 opens to provide no idling current from idling circuit 18 to the bases of transistors Q₁₂₁-Q₁₂₄. Thus, amplifier 12 loses or reduces the amplifying ability and produces from collectors of transistors Q₁₂₂ and Q₁₂₄ a DC voltage signal corresponding to input DC voltage signal. When the power saving signal PSS is absent, switch SW3 closes to provide necessary idling current to transistors Q₁₂₁-Q₁₂₄ so that amplifier 12 operates with necessary amplification. The power amplifier 13 comprises constant current sources I21 and I22 for improving the cross-over distortion, NPN transistors Q₁₃₁ and Q₁₃₂, and switches SW1 and SW2. Switches SW1, SW2 and SW3 correspond to the first switching circuit 15. When the power saving signal PSS is present, switches SW1 and SW2 open to provide no idling currents to transistors Q₁₃₁ and Q₁₃₂. Thus, transistor Q₁₃₁ and Q₁₃₂ are operated by the output DC signal from amplifier 12 to produce a predetermined DC level voltage from output P. Thus, output coupling capacitor Co is maintained in the predetermined charged condition. When the power saving signal PSS is not present, switches SW1 and SW2 close to provide necessary idling currents to transistor Q₁₃₁ and Q₁₃₂ so that power amplifier 13 operates with necessary amplification. A negative feedback circuit is defined by elements Rf1, Rf2 and Cf, but can be eliminated when the balance in the single ended pushpull amplifier can be maintained within a tolerable range. Referring to Figs. 5 and 6, a power saving low frequency power amplifier according to a second embodiment of the present invention is shown. When compared with the first embodiment, the third switching circuit 17 is eliminated in the second embodiment. Accordingly, as shown in Fig. 6, the first stage amplifier 11 is always driven by the driving current I COM from constant current source 11. In the second embodiment, the power saving is mostly done in the second stage amplifier 12 and in the power amplifier 13. It is to be noted that since the second switching circuit 14 is provided for improving the S/N ratio during the stand-by mode, the second switching circuit 14 can also be eliminated in such a manner as to have the non-inverting input of operational amplifier 10 shown in Fig. 6 directly coupled to input coupling capacitor Ci. As is fully described hereinabove, according to the present invention, since the present invention employs an active/semi-inactive power saving system, the output coupling capacitor Co can be maintained in the charged condition even during the stand-my mode. Thus, undesirable shock noise will no be produced when the mode is changed from the stand-by mode to use mode, or vice versa.

Claims: A power saving low frequency power amplifier comprising: a first stage amplifier (11) for receiving and amplifying data signal containing an identification signal, and for producing a first output signal, said first stage amplifier being operated in response to a driving current; a second stage amplifier (12) connected to said first stage amplifier for amplifying said first output signal and for producing a second output signal; a power amplifier stage connected (13) to said second stage amplifier for amplifying said second output signal and for producing a third output signal; a negative feedback circuit (19) connected between an output of said power amplifier stage and an input of said first stage amplifier for maintaining said third output signal constant; a first idling means (15) connected to said second stage amplifier for providing a first idling current (I IDd ) to said second stage amplifier; a second idling means (15) connected to said power amplifier stage for providing a second idling current (I IDf ) to said power amplifier stage; a first switching means (15) for making and breaking at least one of paths for said first and second idling currents; a control means (16) for producing a power saving signal (PSS) to said first switching means for breaking said first switching means when said power saving signal is present, said power saving signal being generated in response to said identification signal, thereby suppressing the power consumption when the power saving signal is generated, and maintaining the output voltage from said power amplifier stage constant regardless of make and break of the path of said first and second idling current by said first switching means. A power saving low frequency power amplifier as claimed in claim 1, further comprising a second switching means (17) for restricting the supply of said driving current to said first stage amplifier when said power saving signal is present. A power saving low frequency power amplifier as claimed in claim 2, wherein said driving current is supplied by a first constant current source (I1) connected to said first stage amplifier (11) and also to said second switching means (17), and also by a second constant current source (I3) connected to said first stage amplifier (11), said second switching means (17) being broken, when said power saving signal is present, to operate said first stage amplifier (11) only by said second constant current source (I3). A power saving low fequency power amplifier as claimed in claim 1 or 2, further comprising a third switching means (14) for cutting off the data signal and for supplying a stable DC voltage to said first stage amplifier (11) when said power saving signal (PSS) is present. A power saving low frequency power amplifier as claimed in claim 1, wherein said first stage amplifier (11) has a first input for receiving said data signal, and a second input for connection with said negative feedback circuit (19), said first stage amplifier (11) being a differential amplifier. A power saving low frequency power amplifier as claimed in claim 5, wherein said second stage amplifier (12) comprises first and second transistors (Q₁₂₂, Q₁₂₄) for receiving said first output signal, said first idling means (15) supplying said first idling current to the base of said first and second transistors (Q₁₂₂,Q₁₂₄). A power saving low frequency power amplifier as claimed in claim 6, wherein said power amplifier stage (13) comprises third and fourth transistors (Q₁₃₁,Q₁₃₂) for receiving output signals from said first and second transistors (Q₁₂₂,Q₁₂₄), said second idling means (15) providing said second idling current (I IDf ) to the base of said third and fourth transistors (Q₁₃₁,Q₁₃₂). A power saving low frequency power amplifier as claimed in claim 4, wherein said control means (16) supplies said power saving signal to said first and second switching means (15, 17) to break said first and second switching means (15, 17) in response to said power saving signal, and supplies said power saving signal to said third switching means (14) to cut off the data signal by turning said third switching means and to supply stable DC voltage to said first stage amplifier (11).

Inventors: ISHIGURO KAZUHISA, SEKIGUCHI YUTAKA, ISHIGURO, KAZUHISA, SEKIGUCHI, YUTAKA
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1989
Main classification: H03F1
IPC codes: H03F3, H03F1, H04B1