Semiconductor device with a high breakdown voltage

Abstract: A semiconductor device has PN junction in architecture of PN⁻N⁺, P⁺NN⁺, PIN, or PγN. Such semiconductor device comprises a first surface layer (2) dopped with a first type impurity at a predetermined first concentration for forming a high resistant layer, a second layer (3) formed below the first layer (2) and doped with a second type impurity which is different from the first impurity at a predetermined limited second concentration, the second layer (3) forming PN junction between the first layer, and a third layer (4) formed below the second layer (3) and dopped with the second impurity at a predetermined third concentration higher than the second concentration. The semiconductor device also has a first edge section extending over the first layer and the second layer and formed into a first Bevel structure having a first taper angle, and a second edge section extending over the second and third layer so as to adjoin with the first edge section at an intersection oriented at a portion in the second layer and formed into a second Bevel structure having a second taper angle.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to a semiconductor device which has enhanced withstand voltage property. More particularly, the invention relates to a structure of a semiconductor device having PN junction with improved withstand voltage. Description of the Background Art For semiconductor devices, such as semiconductor diode, gate turn-OFF thyristor and so forth, it is essential to weaken electric field of surface of PN junction so as to maintain withstand voltage at high level and to prevent the device from causing avalanche at relatively low voltage. In order to weaken the electric field at the PN junction surface, Bevel structure is generally employed by providing taper for the surface to which the end of the junction is exposed. There is two way of providing Bevel structure for the surface. One way is to form a positive Bevel structure, in which cross section is gradually increased from the upper high resistance layer which has relatively low concentration of doped N-type impurity to the lower low resistance layer which has relatively high concentration of doped P-type impurity. The other way is to form a negative Bevel structure, in which cross section is gradually decreased from the upper high resistant layer to the lower low resistant layer. In the recent years, there have been proposed improved constructions of semiconductor devices which has lower ON voltage. Such recently proposed semiconductor devices has architecture of PN⁻N⁺, P⁺NN⁺, PIN, PγN and so forth. In the PN⁻N⁺ architecture, N-type high resistant layer is separated into N layer which has low N-type impurity concentration and N⁺ layer which has high N-type impurity concentration. The PN⁻N+ architecture has been advantageously employed in the modern semiconductor devices because it achieves lower ON voltage by reducing width of N⁻N⁺ layer by terminating depletion region with the N⁺ layer. For such modernized semiconductor devices, the positive and negative Bevel structures are not effective for reducing strength of the surface electric field. Therefore, such a conventionally known Bevel structure is not applicable of the modernized semiconductor devices such as that set forth above. Namely, when the positive Bevel structure is employed for PN⁻N⁺ architecture electric fields concentrate to the N⁺layer to cause lowering of the withstand voltage For improving this, various attempts have been made. One such attempt is disclosed in the document JP-A-52-89474. This document discloses a semiconductor device in which the withstanding voltage is increased by decreasing the electrical field intensity on the side surface of the PN junction by forming a negative or positive bevel. The bevel is formed by preparing a convex part on the side exposed surface of the PN junction or in the neighbourhood of the PN junction. The junction is composed of a P layer and N layer and the impurity concentration of the P layer is higher than that of the N layer. The side surface of the N layer is divided into two pieces after preparing a convex part on it on the exposed part of the PN junction or on its neighbourhood. The angle between the PN junction and this convex part which is protruding from the inner convex part of the side surface of the N layer is negative bevelled and the angle between the lower part of the N layer and the junction is acute. Although the withstanding voltage of the PN junction is increased by providing a convex part on the side exposed the surface of the PN junction or in the neighbourhood, this documents does not disclose that it is advantageous to provide a convex part at a distance from the PN junction. In the EP-A- 0 144 876 it is disclosed that the withstand voltage of a semiconductor device as in the preamble of claim 1 can be increased in that the thickness (S) over the stopping region and the total quantity of donors are so selected that they satisfy the equation where e = the elementary charge, ε = the dielectric constant of the semiconductor, N D = the donor concentration in the end stopping region in cm⁻³, x = is the path coordinating centimetres, k = is a content for which 0,8 ≦ k ≦ 1,0, E n = is the field strength at the position from the n-to n region at the break through voltage of the component. The device of the EP-A- 0 144 876 is further characterized in that a recess is provided at the edge of the end stopping region. In this document the geometry of the recess is described by two angles which according to this document may be varied in a wide range without deteriorating the breakdown voltage of the semiconductor device. Therefore it is not disclosed that certain ranges of these angles are advantageous compared with other ranges. In either case, configuration of the semiconductor devices become complete to cause difficulty in forming dust proof and/or shielding layer with polyimide or silicon rubber. In addition, such prior proposed structure requires process of relatively wide area to cause reduction of the effective area. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a semiconductor device which can solve the problems set forth above. Another object of the present invention is to provide a semiconductor device which has satisfactorily high withstand voltage and with construction to be easily processed. These objects are achieved by the features of the characterizing portion of claim 1. Advantageous embodiments of the invention are described in the dependant claims 2 and 3. Brief description of the drawings The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to limit the invention to the specific embodiment but are for explanation and understanding only. In the drawings: Fig. 1 is a section of the preferred embodiment of a semiconductor device according to the present invention; Fig. 2 is a section showing process of forming novel Bevel structure structure employed in the preferred embodiment of the semiconductor device of Fig. 1 ; Fig. 3 is a graph showing variation of withstand voltage depending upon a taper angle ϑ ₁ of the Bevel structure in the preferred embodiment of the semiconductor device; Fig. 4 is a graph showing variation of withstand voltage depending upon a taper angle ϑ ₂ of the Bevel structure in the preferred embodiment of the semiconductor device; Fig. 5 is a graph showing variation of withstand voltage depending upon variation of the position of the intersection between surfaces having taper angles ϑ ₁ and ϑ; Fig. 6 is a graph showing distribution of impurity concentration in a gate turn-OFF thyristor as one example of practical implementation of the semiconductor device according to the present invention; and Fig. 7 is a graph showing voltage withstanding characteristics of the preferred embodiment of the gate turn-OFF thyristor of Fig. 6 . DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings, particularly to Fig. 1 , the preferred embodiment of a semiconductor device, according to the present invention, will be discussed herebelow in terms of the semiconductor device employing PN⁻N⁺ architecture. As seen from Fig. 1 , the shown embodiment of the semiconductor device is fabricated with P-type layer 2 , N⁻-type layer 3 and N⁺-type layer 4 . As discussed in the introduction of the disclosure, the P-type layer 2 is formed on the surface of the semiconductor device and doped with P-type impurity. The concentration of P-type impurity doped in the P-type layer 2 is relatively low to form high resistance layer. The N⁻-type layer 3 is formed below the P-type layer 2 and is doped with N-type impurity at relatively low concentration. The N⁺-type layer 4 is formed below the N⁻-type layer 3 . The N⁺-type layer 4 is doped with N-type impurity at relatively high concentration. The N⁺-type layer 4 forms a high resistance layer together with the N⁻ type layer 3 . The N⁺-type layer 4 is bonded on a reinforcement 6 by brazing material 5 . The semiconductor device has a first Bevel processed section A and a second Bevel processed section B. The first and second Bevel processed sections A and B are adjoining to each other at an intersection I . In the preferred embodiment, the intersection I is oriented at a position distanced from the surface at L₁ and from the bottom at L₂ . Furthermore, the orientation of the intersection I is set in the N ⁻-type layer. The distance from the PN junction between the P-type layer and the N⁻ type layer is set at L₃ which is approximately 4/5 of the overall thickness L₄ of the N⁻-type layer. The first Bevel processed section A has taper angle ϑ ₁ with respect to the vertical axis χ in a range of 0 ± 15°. On the other hand, the second Bevel processed section B is provided negative Bevel with a taper angle ϑ ₂ with respect to the vertical axis χ in a range of 40 ± 20°. The taper angles ϑ ₁ and ϑ ₂ are selected through experiments. Experimentally measured withstand voltage relative to the taper angles ϑ ₁ and ϑ ₂ are shown in Figs. 3 and 4 . Fig. 3 shows results of experiments performed with fixing the taper angle ϑ ₂ of the second Bevel processed section B at 40 ° and with varying the taper angle ϑ ₁ of the first Bevel processed section A within a range of -25° to +30°. On the other hand, Fig. 4 shows results of experiments performed with fixing the taper angle ϑ ₁ of the first Bevel processed section A at 3° and with varying the taper angle ϑ ₂ within a range of 0° to 80°. As can be seen from Fig. 4 , when the taper angle ϑ ₂ is fixed at 40°, the withstand voltage becomes maximum in a range approximately -15° to +15°. From this, the preferred range of the taper angle ϑ ₁ is set in a range of 0 ± 15°. On the other hand, from Fig. 4 , it can be seen that the withstand voltage is maintained about 9 KV at the taper angle ϑ ₂ in a range of 20° to 60°. Further preferred range of the tape angle ϑ ₂ may be within a range of 20° to 40°. In the experiments, it was observed that when the negative taper angle of the taper angle ϑ ₁ is smaller than -15°, concentration of electric field to the N⁺-type layer occurred. On the other hand, if the positive tape angle of ϑ ₁ is greater than +15°, concentration of the electric field to the N⁺type layer was not observed. However, the electric field strength in the P-type layer and N⁻-type layer could not be reduced. Further experiments were performed in order to determine the orientation of the intersection I . Results of the additional experiments is shown in Fig. 5 . The experiments were performed by fixing taper angles ϑ ₁ and ϑ ₂ respectively within ranges of 0 ± 15° and 40 ± 20°. As can be seen from Fig. 5 , the withstand voltage becomes maximum when L₃ is 80 to 100% of L₄ . As can be clear herefrom, it is preferred to set the orientation of the intersection I in a position where L₃/L₄ is in a range of 80 to 100%. This structure is successfully employed for increasing of the surface area of the N⁺-type layer exposed to the end for reducing electric field strength. In processing the first and second Bevel processed sections A and B , sand blasting technology may be conveniently utilized. One example of processing of the first and second Bevel processed sections A and B is shown in Fig. 2 . In the example of Fig. 2 , a sand blasting nozzle 7 is provided with a taper angle ϑ ₃ with respect to the vertical axis χ. The preferred taper angle ϑ ₃ is within a range of 5 ± 3°. At this nozzle angle, the first Bevel processed section A can be processed. Furthermore, the sand blasted from the nozzle 7 is deflected by the reinforcement 6 to curve the second Bevel processed section B . In order to demonstrate advantages to be accomplished by the present invention, a gate turn-OFF thyristor was produced utilizing epitaxial and diffusion technologies. Target withstand voltage was set at 9000V to 10000V. Principle dimension of the produced thyristor is as shown in Fig. 6 . Bevel processing was performed by sand blasting with a nozzle angle of 5°. Distortion caused by sand blasting was removed by HNO₃-HF type etchant. Polyimide and silicon rubber coating layer was then provided on the surface of the processed thyristor. For this thyristor, withstand voltage test was performed for checking the property of the produced device. The result of the test is shown in Fig. 7 . As will be clear from Fig. 7 , the produced device achieved the targeted withstand voltage. After testing, the surface coating layer was removed and the cross-section of the wefer was observed. The wefer section shows the configuration substantially conforming the section as illustrated in Fig. 1 . While the present invention has been disclosed in terms of the preferred embodiment in order to facilitate better understanding of the invention, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modifications to the shown embodiments which can be embodied without departing from the principle of the invention set out in the appended claims. For example, the shown embodiment is disclosed to perform Bevel process by sand blasting technology, it may be possible to for the Bevel processed sections A and B by various ways. For example, it may be possible to initially form the Bevel processed section in advance of alloy junction with the reinforcement. Subsequently, after alloy junction, the Bevel processed section A can be formed. Furthermore, it should be appreciated that, though the shown embodiment is concentrated to an example of the semiconductor device taking PN⁻N⁺ architecture, the same or similar technology of providing Bevel structure is applicable for semiconductor devices having P⁺NN⁻ , PIN, P γ N architecture and so forth.

Claims: A semiconductor device, comprising a) a first layer (2) having at least one of a P⁺ type highly doped low resistance layer or a P type low doped high resistance layer, said first layer extending horizontally; b) an N type second layer (3), formed below and contacting said first layer and extending horizontally, said second layer having a relatively low impurity concentration; c) an N type third layer (4), formed below and contacting said second layer and extending horizontally, said third layer having a higher impurity concentration than the second layer, d) a first edge section extending through said first layer and into said second layer forming a first bevelled structure having a first tapered angle (ϑ1) defined counterclockwise with respect to a vertical axis (1); and e) a second edge section extending through said third layer and into said second layer forming a second bevelled structure having a second tapered angle (ϑ2) defined clockwise with respect to said vertical axis (1) so as to adjoin with said first edge section at an intersection in said second layer; characterized in that in order to improve the breakdown voltage said first tapered angle (ϑ1) falls in a range of 0° ± 15° and said second tapered angle (ϑ2) falls in a range of 40° ± 20° and that said intersection is approximately placed at 4/5 of said second layer along its vertical direction (L₃) measured from said first layer. The semiconductor device as set forth in claim 1, characterized in that said third layer (4) is bonded to a reinforcement layer (6) through a brazing layer (5), said reinforcement layer (6) extending horizontally beyond said third layer (4). The semiconductor device as set forth in claim 1 or 2, characterized in that said second layer (3) is an N⁻ type layer.

Inventors: KEKURA MITSURU, KEKURA, MITSURU
Applicants: MEIDENSHA ELECTRIC MFG CO LTD, KABUSHIKI KAISHA MEIDENSHA
Application year: 1989
Main classification: H01L29
IPC codes: H01L29, H01L21