PARALLEL STRING PROCESSOR AND METHOD FOR A MINICOMPUTER

Abstract: A processor is disclosed for use in a computer system for comparing a number of bytes simultaneously in order to locate a particular character in a string of data. The processor includes a register (B) for holding the data bytes, a register (A) for storing the particular character, a comparison circuit (102, 109) for simultaneously comparing the bytes of the first register (B) with the bytes of the second register (A), and a circuit (115, 122) for generating indicator bits when a match has been found between the two registers. Microcode instructions cause the system to branch to a predetermined memory location when the control character has been located and to branch to a second predetermined memory location when no control character is found in the data string. A second portion of the processor finds the indicator bits generated from the circuit (115, 122) which have a predetermined characteristic and thus identifies the position of a particular byte in the data word that has the selected predetermined characteristic. In particular, four instructions are provided which find the first matching byte; the first non-matching byte; the first matching byte after the first non-matching byte: and the first non-matching byte after the first matching byte.

Description: PARAI_LEL STRING PROCESSOR AND METHOD FOR A MINICOMPUTER Notice Regarding Copyrighted Subject Matter A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Background of the Invention The present invention relates generally to computer systems for processing strings of data, and also to a parallel string processor for a minicomputer and a method of searching strings of bits and bytes for the presence of a desired keyword. Prior art computers and microprocessors process data strings one byte at a time. One of the most frequently occurring processing tasks is to attempt to locate one or more control characters in a data string. Prior art systems compare the data one byte at a time to the control or reference characters which are loaded into a CPU (central processing unit) register. After a byte is compared, the data string is rotated one byte so that the next byte in the data string is compared, continuing until all bytes are compared. The foregoing is a time-consuming procedure and utilizes a substantial amount of computer time as numerous repetitions of the comparison process are required to check each byte sequentially in order to determine whether it contains the reference character. For example, there may be only one "carriage return 1 * (CR) character found per 80- character line, but all 80 characters must be compared one at a time. If a data string has 512 bytes, and each byte is separately compared to the control character, the comparison must be executed 512 times. Thus, a need exists for reducing the amount of time required to compare strings of data and find control characters embedded in the strings. Eight bytes of data are simultaneously compared. Thus, the number of comparisons necessary is reduced by a factor of 8 relative to a single byte comparison, resulting in a substantial reduction of processing time. Since the comparison procedure is commonly executed numerous times in any given program, a significant saving in processing time may be achieved by this simultaneous comparison of a number of bytes. In other computer applications it is desirable to have the capability to search long strings of bytes for the presence of a selected pattern of bytes. One such application that is relatively well known is used in the word processing context. This application allows one to search a portion of text for a particular word or phrase. For example, one may want to find each occurrence of the word "country" within a particular document so that the word "county" can be substituted therefor. Alternatively, one may want to find each occurrence of "couty" so that it ca be replaced with the proper spelling "county." These ar known as search and replace operations. Search and replac operations are also used in connection with automati spelling check programs that are offered by man commercially available word processing programs. In word processing programs and other programs in whic words and letters are used, each letter of the alphabet a well as each symbol such as an asterisk or hyphen i represented as a unique string of eight 1 or 0 logic bits, also known as a byte. In order to determine whether tw byte strings represent the same word, the corresponding bit in each byte are compared to determine whether they are th same. If all of the bits in the two byte strings ar identical, the two byte strings represent the same word. A portion of text can be thought of and is represente as a long, continuous string of bytes, one byte for eac letter appearing in the portion of text. To determin whether a particular word, or "keyword," appears in portion of text, current string processors typically, starting at the beginning of the byte string that represents the portion of text, or the "character string," compare the first byte of the keyword with the first byte of the character string. If these two bytes match (the first letter of the keyword matches the first letter in the portion of text) , then the processor compares the second byte in the keyword to the second byte in the character string. If these two bytes match, then the processor compares the next pair of bytes in the two strings, and so on. If all of the respective bytes in the two strings match, the processor has found an occurrence of the keyword in the portion of text. However, the keyword does not usually appear as the first word in the portion of text being searched. Consequently, one of the bytes of the keyword will not match one of the bytes in the character string (the keyword is not the first word in the portion of text) . In this case, the character string is shifted one byte relative to the keyword so that the first byte of the keyword is compared to the second byte of the character string. If these two bytes match, then the second byte of the keyword is compared to the third byte of the character string, and so on. If one of the pairs of bytes do not match, then the character string is again shifted one byte relative to the keyword so that the first byte of the keyword is now compared to the third byte of the character string. This general process repeats, usually until all occurrences of the keyword in the portion of text have been found. As an example, let the keyword be the word "the" and the character string be "that time is the essence." Initially, as described above and set forth below, the byte representing the "t" in "the" will be compared to the byte representing the "t" in "that": Data String: that time is the essence Keyword: the This comparison will yield a match, and so the byte representing the "h" in "the" will be compared with the byte representing the "h" in "that." These bytes will also match, and so the byte representing the "e" in "the" will be compared to the byte representing the "a" in "that." These bytes will not match, and so the character string will be shifted one byte with respect to the keyword so that the first byte of "the" will be compared with the second byte in the character string. The relative position of the keyword and the character string are set forth below, and the "3" above the letter "t" in the word "that" iε the number of comparisons that were required to determine whether or no there was a match. Comparisons: 3 Data String: that time is the essence Keyword: the Only one comparison will be needed at this point t determine that the keyword is not present at this portion o the character string, and the character string will b shifted again: Comparisons: 31 Data String: that time is the essence Keyword: the This process will continue to repeat until the match i found, at which point the character string will have bee shifted to the position set forth below: Comparisons: 31121211111114 Data String: that time is the essence Keyword: the Note that this particular example required 21 comparisons to find the keyword "the" in the character string "that time iε the essence." In particular, four comparisons were required even where the keyword matched the same word in the character string (the blank space required one comparison) . In other computer applications it is desirable to test bit patterns for the presence of a particular bit string. Examples of such applications are encryption and decryption algorithms used to scramble and unscramble binary information to protect it from unauthorized reception. Such algorithms are often used in the intelligence field to protect highly classified information from being intercepted and used by foreign countries having adverse interests. These algorithms are also used by corporations to safeguard their valuable commercial information and trade secrets. In general, these encryption and decryption algorithms may perform similar search and replace operations as described above in connection with word processing programs. In addition, it would be desirable to be able to perform operations on strings of binary information that are not an integral number of bytes long, for example, a string of five bits. Processors such as those described above in connection with word processing programs do not even have this capability since they shift strings of eight bits, or one byte, at a time. Even if such processors had the capability to shift strings of data one bit at a time, their use as described above on strings of bits would be even slower due to the large number of comparisons that would be necessary. As an example, assume that the bit string "11001110011011" is to be searched for the presence of the keyword "1101." Initially, as described above, the first bit of the keyword would be compared to the first bit in the bit string as set forth below: Bit String: 11001110011011 Keyword: 1101 The processor would need to make four comparisons before it could determine that the four bits in the keyword do not match the first four bits in the bit string. Again, as described above, the processor would then shift the bit string relative to the keyword string as set forth below and compare the respective bits again: Again, the "4" above the first "1" in the bit string means that four comparisons were required in order to determine that the keyword did not match. After the keyword was shifted as shown above, two comparisonε would be required to teεt the next portion of the bit εtring. As shown below, 22 comparisonε would be needed to find the portion of the bit string that matched the keyword. Comparisons: 4211242114 Bit String: 11001110011011 Key Word: 1101 A greater number of comparisonε are required overall in bit searching than are required in byte or character searching since it is more likely that a pair of bits each having one of two possible values will match than a pair of letters each having one of 26 possible values. Thus, a processor performing operations on bit stringε in this manner would have an unduly large amount of computing overhead. g τ-ma-1- *F -frfte Invention The preεent invention comprises a portion of a computer syεtem for comparing a number of bytes simultaneously. The parallel procesεor of the present invention includes a first register for receiving bytes of data, a εecond register for storing a number of copies of a byte representing a selectable control or reference character and a comparison circuit for simultaneously comparing the data in the two registers to determine whether any of the bytes in the first register are equal to the bytes representing the control character in the second register, and generating control bits which are in a first state if the corresponding byte in the first register is equal to the control character in the second register, and in a second state when the corresponding byte in the first register is not equal to the control character in said second register. The parallel byte procesεor haε the ability to branch to a predetermined memory location if any of the byte pairs being simultaneously compared are equal. If any byte of data in the first register is equal to the bytes comprising the control characters in the second register, the microcode instruction brancheε or proceeds to a predetermined memory location. If no control character iε located in the data in the first register, the instruction branches or proceeds to a second predetermined memory location. Thus, a number of bytes may be moved and checked for control characters with a single instruction, thereby substantially reducing the processing time. In an exemplary embodiment of the present invention, eight bytes of data are simultaneously compared. Another aspect of the invention is directed towards a novel parallel bit and byte string proceεsor for a minicomputer. In its byte mode, the proceεεor storeε a portion of a string of bytes that is to be tested for the presence of a desired keyword in a first register location and storeε the keyword in a second register location. Instead of testing the portion of the byte string one byte at a time, the processor simultaneously tests each byte in the keyword with a respective byte in the byte string. Thus, only a single comparison is required to determine whether the keyword is present in any portion of the byte string. If the keyword is not present in the portion of the byte εtring teεted, then the proceεεor εhiftε the byte string with respect to the keyword and then akeε a single compariεon of the keyword with the new portion of the byte εtring. This single-compare-and-test procesε continues until either the keyword is found or the end of the byte string is reached. Aε a reεult of simultaneously testing each byte in the keyword with a respective byte in the byte string, the processing time is kept to an absolute minimum. In its bit mode of operation, the procesεor stores a portion of a bit string that is to be tested for the presence of a desired string of bytes in a first registe location and the desired keyword in a second registe location. The processor simultaneously tests each bit i the keyword with a respective bit in the bit εtring. As result of this simultaneouε teεting, only one comparison i needed to determine whether the keyword is present in th portion of the bit εtring being tested. If the keyword i not present, the bit string is shifted one bit relative t the keyword and a single comparison of the keyword with th new portion of the bit string is made. Thiε proceε continues until the keyword is found or until the end of th bit string is reached. Because each bit in the keyword i simultaneously tested with a respective bit in the bi string, only a single comparison is required to determin whether the keyword matches a portion of the bit string, an as a result, proceεεing time is minimized. Another feature of the invention is the capability o the processor to automatically function either as a paralle bit procesεor or aε a parallel byte processor. When th processor is given a first control signal, the procesεo functions aε a parallel byte processor, and when th processor is given a second control signal, the processo functions as a parallel bit procesεor. Aε a result, tw separate processors are not required, thus resulting in cos εaving that a separate procesεor would otherwise entail. Another aspect of the present invention is a set o novel instructionε that are particularly useful for testin the outputs of byte comparisons. One such instruction find the location of the firεt byte (i.e., moεt significant) in a first data word that is identical to the corresponding byte in a second data word. A similar instruction finds the location of the first byte in the first data word that does not match the corresponding byte in the second data word. A third instruction finds the first byte in the first data word that matches the correεponding byte in the second data word so long as the matching byte is less significant than a byte in the first data word that does not match the corresponding byte in the second data word. A fourth instruction finds the first byte in the first data word that does not match the corresponding byte in the second data word so long aε the matching byte iε leεε significant than a byte in the firεt data word that matcheε the correεponding byte in the second data word. The processor includes novel circuitry to implement these instructions. In particularly preferred embodiments, the processor includes a replication instruction and associated circuitry that duplicates a single input byte into all the bytes of a multiple byte data word. The replication instruction is particularly useful for comparing an input data string to a predetermined control character or other delimiter. These and other objects, features, and advantages of this invention will be apparent in view of the following detailed description of several preferred embodiments, which are explained with reference to the figures, a brief description of which is provided below. Brief Description of the Drawings Figures 1 and 2 are block diagrams of two registers of the parallel byte comparison procesεor; Figure 3 is a circuit diagram of the comparison circuit of the parallel byte comparison processor; Figure 4 is a representative instruction sequence of the parallel byte comparison processor; Figure 5 is a schematic circuit diagram of a parallel string procesεor in accordance with the invention; Figure 6 is a detailed circuit diagram of a portion of one embodiment of a shift register in accordance with the invention; Figure 7 is a detailed circuit diagram of a portion of the parallel string processor of Figure 5; Figure 8 is a detailed flowchart of the operation of the parallel proceεεor of Figure 5 in its byte mode of operation; Figure 9 is a detailed flowchart of the operation of the parallel processor of Figure 5 in its bit mode of operation; Figure 10 is a block diagram illustrating the circuitr to implement instructions to find specific occurrences o hits and misses in the hit register; Figure 11 is a block diagram illustrating the operatio of circuitry to implement a replicate instruction to cauε the data in one byte to be replicated in all the byteε of data word; and Figure 12 is a logic diagram of the replication circui of Figure 11 showing a particular implementation of th replication circuit. Detailed Description of Several Preferred Embodiments Referring to Fig. 1, a selected control character, suc as "EOS" (end of sector) , is loaded into a Register A. Referring to Fig. 2, an 8-byte (64 bit) data string i loaded into a Register B and compared to the "EOS" referenc characters in Regiεter A in order to determine whether ther are any "EOS" characterε in any byte of the data εtring i the Regiεter A. The results of the comparison, whether an particular byte of Register A matches the corresponding byt in Register B, is stored in a Processor Status Register 10 (alεo referred to as the "hit register") . It will be appreciated that with the present invention any number of byteε may be simultaneously compared, th number depending on the particular computer syεtem utilized In the preferred embodiment discussed herein, the compute iε a 64-bit machine; therefore, 8 byteε are simultaneously compared to determine whether they contain a control character. Each bit in the data string in the Register B is compared to the bits comprising the control characters in Regiεter A. Thiε iε εhown in more detail in Fig. 3, wherein each bit of each byte 0-7 in the Register B is compared with the corresponding bit of each correεponding control character byte 0-7 in the Register A, utilizing "exclusive- NOR" circuits 102-109, one "exclusive-NOR" circuit associated with each bit pair. It should be understood, however, that Fig. 3 is a functional diagram to illustrate the invention. In the actual embodiment, an arithmetic logic unit (ALU) is utilized to perform the exclusive-OR function as shown in Fig. 5 and discussed in further detail hereinafter. In Fig. 3, only the excluεive-NOR circuitε 102a and 102h corresponding to byte 0, bit 0 (the least significant bit) and byte 0, bit 7 respectively, and 109a and 109h corresponding to byte 7, bits 0 and 7, respectively are shown. It should be understood, however, that there are 64 suc exclusive-NOR circuits. In addition, only the portions of Registers A and B containing bytes 0 and 7, corresponding to the least significant bytes and most significant bytes, respectively, are shown in Fig. 3. The designations within Registers A and B denote the register, the byte number and the bit within the bytes. For example, "A67" refers to bit 7 of byte 6 of the Register A. The components of the exclusive-NOR circuit 109 are also shown in Fig. 3 as compriεing firεt and second AND gates 110 and 111, first and second inverters 112 and 113, and OR gate 114. The bit pairs, for example, A77 and B77, are input to the AND gate 110. The bits A77 and B77 are also inverted by inverters 112 and 113, respectively, and are input into the second AND gate 111 of the exclusive-NOR circuit. The output of the first AND gate 110 and the output of the second AND gate 111 are input to the OR gate 114. The output of each OR gate iε provided aε an input to one of eight 8-input NAND gateε 115-122 (the NAND gateε 116- 121 are not εhown) . There iε one 8-input NAND gate for each byte being compared. The output of any of the 8-input NAND gates 204-210 will be low or logical "0" only when all eight bits being compared are equal and thus will indicate that the particular byte pair is equal to each other (e.g., when all the bits A00-A07 of the Regiεter A are equal to the correεponding bitε BOO-B07 of the Register B, the output of the 8-input NAND gate 115 will be low) . The output of NAND gates 115-122 are stored in the Procesεor Statuε Regiεter 100 or "hit" register (Fig. 2) . An instruction (BAH) causes the syεtem to branch or proceed to a predetermined memory location when any of the bitε in the Procesεor Status Register 100 indicate that any of the eight bytes being compared are equal. Alternatively, if there are no bitε in the Proceεεor Statuε Regiεter 100, indicating that no byte pairε match and no control characte was found, the syεtem proceeds to execute the instructio found in the next sequential memory location in the contro memory of the proceεεor. If a hit occurε, the location o the particular byteε which do match can be determined b looking at which bitε of the Proceεεor Status Register 10 indicate a match. For example, if byte 3 of the Register A is equal t byte 3 of the Register B, bit 3 in the Processor Statu Register will be zero, indicating that the byte 3 pai matches. Fig. 4 shows a representative instruction sequence The left column correspσndε to the line number in th control program of the proceεεor. The inεtruction at lin 80 causes the control character being compared to be loade into the Regiεter A. The inεtruction at line 82 cauεes th loading of Register B with the first eight bytes of dat (data word 1, indicated as "DATA1" in Fig. 4) . Th inεtruction at line 84 performs the multibyte "exclusive NOR" operation of the preεent invention on the data in the Regiεter B and the Regiεter A. The instruction at line 86 causeε the εyεtem to branch to a memory location 400 if any of the bitε in the Proceεεor Statuε Regiεter 100 (Fig. 2) are zero indicating that a match was found between the Registers A and B. At memory location 400, which is executed if a hit is found, is the beginning of a routine which examines the bits of the Processor Status Register 100 to determine the location of the characters within data word 1 which match the control character "EOS" for example. Then at line 88, Register A iε loaded with a second control character and at line 90 the exclusive-NOR operation is performed to determine whether the second control character is present in any of the eight bytes of data in DATA1. If the second control character is found in DATA1, then at line 92 the program branches to memory location 400. When there are no control characterε found in the data, the inεtruction at line 94 iε executed and the data in Register B is stored in a buffer. Thereafter, the syεtem proceeds to execute the instruction at line 80 and the process described above repeats. Thuε, eight byteε are checked for two different control characterε with only two compare cycleε in contrast to the 16 compare cycles required in prior art machines. A "branch on no-hits" may be utilized as an alternative to the "branch on any hit" instruction, which branches to a memory location if none of the bytes in the data word contain the control character. When the data iε checked for more than one εet of characters, the Register A may be reloaded with the characters for each compare sequence. However, to increase the execution speed, reloading the register may be avoided by various methods known to thoεe skilled in the art. An n- to-1 multiplexer may be substituted for the Register A, where n is the number of character setε to be εearched for in the data. For example, if the data is to be searched for two sets of characters, "EOS" and "CR," a 2-to-l multiplexer may be utilized, with the registers containing "EOS" and "CR" εerving aε input to the multiplexer. In the preferred embodiment, the architecture of the CPU permits the selection of the desired register for input to the exclusive-NOR circuit. Instructions cause the CPU to route the contentε of the selected register to the excluεive-NOR circuit. Alternatively, tri-state devices may be utilized. In the actual embodiment, an arithmetic logic unit (ALU) is utilized to perform the exclusive-OR function. Referring to Fig. 5, the End of Sector (EOS) or other control characters are loaded into the A register file. The data which is to be εearched for the End of Sector flag is loaded in register B via the B bus 172. The EOS flag is input to the ALU through the A latch 142 and the data to b compared to determine whether it contains "EOS" characters is input to the ALU through B latch 144. The ALU compare each bit of input from the A register to the correspondin bit of input from the B register. For each matching bi pair, the ALU will generate a zero on the respective outpu line. The output of the ALU is input to the zero detec circuit (which compriseε 8-input NOR gateε) via the F bu 148. The zero detect circuit determines whether all of th bits within a byte are zero. If all of the bitε within particular byte are zero, a one iε generated by the zer detect circuit indicating that a particular byte from the regiεter matches the byte from the B register. Th foregoing embodiment utilizes inverse logic from th illustrative circuit shown in Fig. 3. In the circuit show in Fig. 3, a zero iε generated when the byte pairε match. A parallel εtring proceεεor in accordance with anothe aεpect of the invention iε εhown in Fig. 5. The proceεεo includes a dual register file 120 comprising an A registe file and a B register file. Although only nine register are shown in each register file, each regiεter file include 1024 registers, and may include more if desired. In this embodiment, the procesεor of Fig. 5 iε for a 64-bit minicomputer, and so each of the registers in the A and B register files is 64 bits, or eight bytes, wide. The A register file is shown to include an address register 122, a length register 124, a bit mask register 126, a byte mask regiεter 128, and a test register 130. The addresε regiεter 122 is used to store the address of a data string, either a bit string or a character string, that is to be searched by the procesεor for a particular keyword. The length regiεter 124 is used to store the length of the portion of the data string that remains to be tested. The bit mask register 126 is used to store a desired pattern of bits that is used to mask the keyword. For example, the bit mask regiεter 126 might be used to ignore capital letters so that the processor would consider the letter "a" to be equivalent to the letter "A." The byte mask register 128 contains a desired pattern of bytes used to mask the keyword. For example, the byte mask register 128 might be used to ignore the second letter of a word so that the procesεor would equate the word "εtring" with "εpring." The teεt register 130 contains the desired keyword after it has been masked with the desired byte mask. The B register file contains a bit count register 132 and a byte count register 134 which, as is explained in more detail hereinafter, determine when the next portion of the data string being tested for the presence of the keyword needs to be fetched from memory. A keyword regiεter 136 containε the binary data string corresponding to the desired keyword, and the end-of-string (END) flag register 138 contains a flag that indicateε whether or not a data εtring has been completely εearched for the preεence of a deεired keyword. The A and B register files are connected to an arithmetic logic unit (ALU) 140 through an A latch 142 and a B latch 144, respectively. The ALU 140 is a conventional arithmetic logic unit, which in thiε embodiment may includ SN54LS381A ('381), SN54LS382 ('382), or similar integrate circuit chips commercially available from Texaε Instrument of Dallas, Texaε. The arithmetic logic unit 140 perform various operations on the data supplied to its dual dat inputs, depending upon the combination of binary signal supplied to its control inputs by an ALU function selec circuit 146. For example, when the ALU 140 receives particular combination of control inputε, the ALU 140 add its two data inputε. In response to a different combinatio of its control inputε, the ALU 140 performs an excluεive-o operation on itε data inputε. The A and B register files are deεigned so that at an time, the binary information stored in each register i equal to the binary information stored in its adjacen register so that the A regiεter file iε a copy of the regiεter file, and vice-versa. This regiεter organizatio εpeedε up the operation of the proceεεor. In order t perform an operation on two operands, one operand must b tranεmitted to the A latch 142 and the other to the B latc 144. If there were only an A regiεter file, the proceεεo would require an extra cycle to perform any given AL operation. The output of the ALU 140 iε connected via an 64-bit wide F-buε 148 to a zero-detect circuit 150 which detect when all the outputε of the ALU 140 are zero. The ALU 140 ALU function select circuit 146, and zero detect circuit 15 are εhown in detail in Fig. 7. The ALU function selec circuit 146 is εhown functionally (in dotted lineε) fo purposes of explaining the invention. In reality, th function select circuit 146 iε implemented with programmabl array logic integrated circuitε commercially available fro Monolithic Memorieε, Inc. of Santa Clara, California, tha are programmed with many equations that do not facilitat explanation. Theεe equations are, however, included in thi specification aε Appendix 1, and they completely describ the actual embodiment of the ALU function select circuit 146. The ALU compriseε 16 separate, 4-bit '381 integrated circuit chips 152. For purposes of clarity, the data inputs of the ALU chips 152 that are connected to the A and B latches 142, 144 have been omitted from Fig. 7, and only the outputs of the chips 152 are shown. Each pair of the chips 152 iε connected to a respective multiplexer 154 which supplies the control inputs for the chips 152. Each of the multiplexers 154 either supplies a desired 3-bit FUNCTION signal or a 3-bit CLEAR signal to the control inputs of the pair of chips 152 to which it iε connected, depending upon the value of itε addreεε signal sent from a register 156 which storeε the 8 bitε of the byte mask. As explained above, the byte mask causeε the proceεεor to ignore certain bytes in the data string being searched so that, for example, the procesεor would equate the keyword "εtring" with the word "spring" in the data string, in which case the second bit of the byte maεk would be εet to logic "1" εo that the "p" in "εpring" iε ignored. Similarly, if it were desired that the fourth letter of a word were to be ignored, the fourth bit of the byte maεk would be εet to logic "1." The multiplexers 154 either supply a specified FUNCTION signal or a CLEAR signal to the chips 152, depending upon whether the value of the particular bit of the byte mask in the register 156 is logic "1" or "0." If the bit in the byte mask is logic "0," the desired 3-bit FUNCTION signal is transmitted, and if the bit in the byte mask is logic "1," the 3-bit CLEAR signal is sent, which causes the outputs of the ALU chipε 152 to which it iε connected to be forced to logic "0." The zero detect circuit 150 comprises 16 NOR gates 158 connected to receive the outputs of the ALU chips 152. The outputs of the NOR gates 158 are connected to eight AND gates 160, which in turn are connected to a pair of NAND gates 162 which are connected to a NOR gate 164. If all outputε of the ALU chipε 152 are logic "0," then it can be seen that the outputs of the NOR gateε 158 will be forced to logic "1," which forceε the outputs of the AND gateε 160 to logic "1," the NAND gateε 162 to logic "0," and the NOR gate 164 to logic "1." Thuε, the output of the NOR gate 164 will be logic "1" only when all the outputε of the ALU chipε 152 are logic "0." Aε set forth below, when the keyword matcheε a portion of the data string to which it is being compare using the exclusive-or function, all the ALU chip outputs will be logic "0," so that in essence a logic "l" output of the NOR gate signalε a match. Thiε logic "1" output iε εupplied to a flip-flop 166 which can then be checked t determine that there was a match. The particular logic gates uεed in the zero detec circuit 150 are not important to the invention since othe circuits could be easily designed to detect that all output of the ALU chips were logic "0," such as, for example, single 64-bit NOR gate. Referring now to Fig. 5, the F-buε 148 iε connected t an A-buε 168 via a buffer 170 and a B-buε 172 via anothe buffer 174. The zero-detect circuit 150 is coupled to th B-bus 172 through a buffer 176. A memory 178 is connecte to the bus 180 that connects the output of the A latch 14 to the ALU 140 through a buffer 182 connected to an M-bu 184. Because this embodiment is for a 64-bit minicomputer the A-bus 168, the B-bus 172, and the M-bus 184 are also 6 bits wide. A pair of serially connected 64-bit shif registers, comprising a J shift register 186 and a K shif register 188, are connected to the B-buε 172. A maε regiεter 190 iε connected to the J εhift regiεter 186 via mask bus 192. As is explained in more detail below, thes shift registers are used to store portions of the dat string to be tested for the presence of a desired keyword. A trio of control signals is supplied to each of th two shift registers 186, 188. A LOAD signal causes th register to which it is attached to be parallel-loaded wit a portion of a data string. The data is loaded into the registerε 186, 188 from the memory 178 through a data route consisting of the ALU 140, the F-bus 148, the buffer 174, and the B-bus 172. A second signal SI causes its respective shift register to be shifted left one bit, and a third signal S8 causes its respective shift register to be shifted left eight bits, or one byte. Fig. 6 iε a portion of a substantially functional equivalent of the J shift register 186 used for purposes of explaining the invention. The actual embodiment of the J and K shift registers 186, 188 comprises specially programmed conventional programmable array logic integrated circuits commercially available from Monolithic Memories, Inc. of Santa Clara, California, and the equations used to program these integrated circuits are included in this specification aε Appendix 2 and completely describe the actual embodiment of the J and K εhift registers 186, 188. Referring now to Fig. 6, a portion of the J shift register 186 consisting of logic gates and flip-flops 196 is shown. Although only six flip-flops 196 are shown, the J shift register 186 is 64 bitε wide and thus includes 64 serially connected flip-flops 196. In Fig. 6 the flip-flops 196 are numerically ordered, with the rightmost flip-flop being the Nth flip-flop, the flip-flop to the left of the Nth flip-flop being the (N+l)st flip-flop, etc. Each of the flip-flops 196 has a data input D connected to the output of a logic circuit 198 and a clock input C connected to receive a CLOCK signal that controls the speed of operation of the shift registers 186, 188. The logic circuits 198 control the loading and shifting operations of the flip-flops 196. Each of the logic circuits 198 comprises a three-input OR gate 200 and three two-input AND gates 202. One of the AND gates 202a has a first input connected to one of the 64 lines of the B-bus 172 and has its second input connected to the LOAD signal. This AND gate 202a in each of the logic circuits 198 causes the flip-flop to which it is connected to be loaded with the binary value of the B-buε 172 when the LOAD signal iε activated, which occurε when the LOAD signal is logic "1." In this state, the output of the AND gate 202a, which equals the binary value of the B-buε input, iε supplied to its respective flip-flop 196 through its OR gate 200. The outputε of the other two AND gateε 202b, 202c do not interfere with this loading process since the SI and S8 signals are forced to logic "0" when the LOAD signal is activated. After a portion of a data string iε loaded into the flip-flopε 196 of the εhift regiεterε 186, 188, the portion iε periodically εhifted either one bit or eight bitε at a time, depending on whether the proceεsor is performing a bit-by-bit comparison or a byte-by-byte compariεon. If bit comparisons are being performed, the SI signal is activated to logic "1" while the LOAD and S8 signals remain at logic "0." Each AND gate 202c to which the SI signal is supplie has its other input connected to the output of the first upstream flip-flop, "upstream" meaning the direction fro which data iε being shifted. In Fig. 6, data is bein shifted from right to left, and thus with respect to an particular flip-flop or other circuit element, the firs "upstream" flip-flop is the first flip-flop to the right o the circuit element and the first "downstream" flip-flop i the firεt flip-flop to the left of the circuit element. Thuε, when the SI signal is activated, the output of the AN gate 202c to which it is connected is equal to the output o the upstream flip-flop. Since the output of the AND gat 202c iε passed through its reεpective OR gate 200 to th input of the downstream flip-flop, the activation of the S signal causeε the εhift regiεterε 186, 188 to perform a one bit logical left εhift on the portion of the data εtrin stored therein. The activation of the S8 signal causeε an eight-bit, o one-byte, logical left shift to be performed by the shif registers 186, 188. Each AND gate 202b to which the S8 signal is connected has its other input connected to the output of the eighth upstream flip-flop so that when the S8 signal is logic "1," the output of each of the flip-flopε 196 is pasεed to the eighth reεpective downstream flip-flop so that the portion of the data string is shifted eight bits to the left. Another portion of the J shift register 186 performs a bit mask operation so that any desired bits of the string being searched may be ignored. For example, as deεcribed above, it might be desirable to ignore capital letters so that the proceεεor would consider the letter "a" to be equivalent to the letter "A." To thiε end, the output of each of the flip-flopε 196 is supplied to one input of a two-input AND gate 204 having its other input connected to receive the output of a NAND gate 206. One input of the NAND gate 206 is connected to receive a respective bit of the bit mask from the mask register 190 connected to the J shift regiεter via the maεk bus 192. The NAND gate 206 is also connected to receive a BIT MASK ENABLE signal that selectively activates or deactivateε the bit mask operation. In particular, when the BIT MASK ENABLE signal is logic "0," the outputs of all of the NAND gates 206 are forced to logic "1" so that the outputs of the AND gateε 204 equal the output of the flip-flops to which they are connected and are not affected by the outputs of the NAND gates 206. However, when the BIT MASK ENABLE signal is logic "1" and the corresponding mask input bit iε also logic "1," the output of the NAND gate 106 is forced to logic "0," and as a result, the output of the AND gate 204 is also forced to logic "0." This operation thus causeε logic "0"s to be placed in each bit of the data string which is to be ignored by the procesεor. As is described in more detail below, each of these logic "0"s causes a forced match when the masked portion of the data string is compared to the keyword εtring by the processor. Finally, the output of each of the AND gates 204 is connected to the B-bus 172 so that the masked or unmasked portion of the data string stored in the shift regiεterε may be supplied to the ALU 140 for comparison to the keyword string. The particular logic used for the masking functions is not important, and alternative logic could be used. For example, selected bits in a bit string could be masked off if the corresponding bitε in the bit maεk were logic "0" instead of logic "1" if the NAND gates 206 were replaced with OR gates, in which case the bit mask enable signal would be activated when logic "0" instead of logic "1." The functional circuit diagram of the K shift register 188 is substantially identical to the diagram of the J shift register shown in Fig. 6, except that the AND gates 204 and the NAND gateε 206 uεed in connection with the bit maεk an the BIT MASK ENABLE εignal are not required since only th output of the J shift 186 register iε εent to the ALU 140 for comparison to the keyword, as is explained in mor detail below. In its byte mode of operation, the processor compares selected string of bytes to determine the presence of selected keyword. Both the byte string and the keyword ar selectable by the user of the procesεor. The basic proces by which the processor testε for the preεence of a εelecte keyword εtring within a εelected data εtring include initially loading the J and K shift registers 186, 188 wit the first portion of the data string to be tested. Then the entire contents of the J shift register 186 ar simultaneously compared with the keyword stored in the tes regiεter 130. If there iε a match, the preεence of a matc is indicated by the processor. Then, the contentε of the and K regiεterε 186, 188 are shifted left one byte and th contents of the J register 186 are again compared with th contents of the test register 130. Any match is indicated and the procesε is repeated. Periodically, the K registe 188 will become empty since its contents are graduall εhifted into the J regiεter 186, and so the K register will be periodically reloaded with the next portion of the data string to be tested. In this manner, the entire keyword is simultaneously compared with a corresponding portion of the data string. This process reduces the number of comparisons required as shown by the example shown below, in which the keyword is "the," the data string is "that time is the essence," and each number above the data string represents the number of comparisonε that were required to determine whether or not the keyword matched that particular portion of the data εtring: Compariεonε: 11111111111111 Data String: that time iε the essence Keyword: the Note that this particular example required 14 comparisonε to find the keyword "the" in the character εtring "that time iε the eεεence" in contrast to the 21 comparisonε that were required by a conventional data εtring proceεεor aε εhown above. Thiε reduction results from the entire keyword simultaneously being compared with a portion of the data εtring, instead of being compared one byte at a time. The detailed operation of the byte mode of the processor iε explained with reference Fig. 8 and Table 1. Fig. 8 is a flowchart of the microcode that controls the operation of the processor shown in Fig. 5, and Table 1 includes a software program that is substantially functionally equivalent to the microcode actually used. The operation is explained with reference to Table l and not the actual microcode used because the actual microcode would be incomprehensible since it is merely a collection of "l"s and "0"s. TABLE 1 1 MOV #0, ENDFLAG ;reset end-of-string flag to 0 2 MOV BITMASK, A ;mask keyword with bit mask MOV KEYWORD, B AND A, B 5 MOV ALU, TEST ;put masked keyword i test register MOV § ADDRESS, J ;load J with first 8 bytes of data string 7 LOADK: MOV ADDRESS, A 8 MOV #8, B ;increment addres to get next 8 bytes 9 ADD A,B of data string and then load in K 10 MOV ALU, ADDRESS 11 MOV § ADDRESS, K ° DAVIN COMPUTER CORP. 1987 At the start of the byte operation of the processor indicated by the start step 210 of Fig. 8, the binary representation of the keyword is stored in the keyword register 136 in the B register file and the binary representation of the data string is stored in the memory 178. Also, the desired bit mask is stored in the bit mask register 126 and in the mask register 190, the desired byte mask is stored in the byte mask register 128 and in the register 156, the address of the byte string in memory 178 to be searched is stored in the address register 122, and the length in bytes of the byte string being searched is stored in the length regiεter 124. The value of the end-of-εtring (END) flag indicates whether or not the data string haε been completely εearched for the presence of the keyword. At step 212 of Fig. 8, the value of the END flag is reset to indicate that the end of the string has not yet been reached. Then, at step 214, the keyword is masked with the bit mask to enεure that the proceεsor ignores any bits in any desired byte as selected by the user. This step is carried out by instructions 2-5 of Table 1. Instructions 2 and 3 supply the bit mask to one data input of the ALU 140 and the keyword to the other data input. Instruction 4 causes the appropriate control signal to be supplied to the ALU so that its two data inputs are logically "anded" together, and the ALU output, which is the value of the masked keyword, is stored in the test register 130 in the A regiεter file via a data path consisting of the F-bus 148, the F-A bus buffer 170, and the A-bus 168. Thus, any bits of the keyword which are to be ignored by the processor are masked to logic "0," and these masked zero bits will force a match with the corresponding bit position in the data string during subsequent comparisonε aε iε explained in more detail below. Next, at εtep 216, the J shift register 186 is loaded with the first word of the data string to be tested, "word" meaning a block of binary data eight bytes long to correεpond to the eight-byte width of the J εhift regiεte 186. The step 216 is accomplished by instruction 6 in Tabl 1 which moves the contents of the memory at the addreε where the data εtring is stored to the J shift register 18 through a path including the memory buffer 182, the M-bu 184, the ALU 140, the F-bus 148, the F-to-B buffer 174, an the B-buε 172. Next, at step 218, the next word, or eigh bytes, of the data string are loaded into the K εhif regiεter 188 from the memory 178 in a similar manner b instructions 7-11. Specifically, instructions 7-10 caus the addresε to be incremented by eight εo that th incremented addreεε will point to the next eight bytes o the data string in memory 178. Then instruction 11 cause the next eight byteε to be fetched from memory 178 and pu into the K εhift regiεter 188 via the εame data path a described in connection with the loading of the J shif register 186. When the K shift register 188 has just been loaded, a step 220 and by instruction 12, the numeric value eight i εtored in the byte count regiεter 134 since there are no eight bytes of string data in the K register 188. Becaus the contents of the K register 188 are periodically shifte left into the J shift register 186, it iε important to kn how many byteε of the data εtring are left in the K regiεt 188 εo that the processor will know when to reload the register with the next portion of the data εtring. Next, at step 222, the masked keyword stored in t test register 130 is compared to the portion of the da string εtored in the J register 186. This step implemented by the inεtructionε 13-16 of Table Specifically, inεtruction 13 cauεeε the maεked keywo εtored in the teεt regiεter 130 to be εent to the A lat 142. Then, inεtruction 14 cauεeε the contentε of the shift register 186 to be moved to the B latch 144 via the bus 172. If the BIT MASK ENABLE signal is logic "1," th the contents of the J register 186 are logically "ande with the bit maεk by the AND gateε 204 prior to being εent to the B latch 144. At instruction 15, the binary value of the masked keyword is compared to the binary value of the masked portion of the data string by providing the ALU FUNCTION εignal with the binary values that cause the ALU 140 to perform a bit-by-bit logical "exclusive-or" of itε two data inputs. The logical exclusive-or operation, which iε conventional and well known, is a sum modulo 2 operation. Thus, a bit-by-bit logical exclusive-or provides a logic "0" output if its two bit inputs are both logic "1" or logic "0," and hence match, and a logic "1" output if its two bit inputs are different. As a result, for each byte of the data string that matches the correεponding byte in the keyword, a logic "0" will be produced in the corresponding byte position. After the keyword iε compared with the portion of the data word in the J register 186, upon a match at step 224 the processor proceeds to the user's program so that the user program may perform its programmed function, for example, replace the keyword that was located with a different word, whereupon the user program returns control to the processor so that any other occurrences of the keyword can be found. The existence of a match is determined by the zero detect circuit at inεtruction 16. Instruction 16 causeε the contents of the ALU 140 to be sent to the zero detect circuit 150. As mentioned above, for each byte position of the ALU 140 in which there was a match, the ALU output will be zero. Consequently, at instruction 17, the zero detect circuit 150 tests each byte of the ALU to determine whether all bytes are zero, in which case all unmasked bytes of the keyword match all unmasked bytes of the data string portion. When the masked bytes are compared by the ALU 140 during itε exclusive-or operation, the ALU output corresponding to each masked byte is forced to logic "0," which is the εame logical output that the ALU provideε in case of a match. Thus, each logic "1" bit in the byte mask forces a match in its correεponding byte position in the keyword. Upon a match, instruction 18 will cause a return to the user's program, and the user progra will return control to the procesεor at instruction 19. I there is no match, instruction 17 will cause instructions 18 and 19 to be skipped. At step 226, the' length of the data string will b decremented by one byte since one byte has just been teste and thus there iε one leεε byte in the data string tha needs to be tested. Thiε step is implemented b instructions 20-23. Instruction 20 causes the number one t be moved to the B latch 144, and instruction 21 causeε th current data εtring length to be εent to the A latch 142. Instruction 22 causeε the ALU 140 to subtract one from th current length, and the new length is stored in the lengt regiεter 124 by inεtruction 23. Next, at step 228, the new data string length εtored i the length register 124 is tested to determine whether al of the bytes in the data εtring have already been compare to the keyword, which will be the caεe if the numeric valu of the length iε zero. Thiε iε accompliεhed at inεtructio 24 which sends the output of the ALU 140 to the zero detec circuit 150. If the value of length is zero, then step 23 iε executed, causing the END flag to be set to logic "1" t indicate that the end of the string has been reached, an control is returned to the user's program. This i accompliεhed by instructions 26 and 27. If the value of length is nonzero and the data strin has not been completely tested, the program branches to ste 232 at which the contents of the J and K registers 186, 18 are shifted left by one byte. This iε accompliεhed b instruction 28, which causeε a logic "1" S8 εignal to b εent to the shift registerε 186, 188 εo that their content are shifted left one byte as explained above. The content of the byte count register 134 are then decremented by on at step 234 to indicate that there is one less byte in the εhift register 188 since it has just shifted one of its bytes into the J shift register. This step iε accomplished by instructions 29-31. Next, at step 236, the numeric value of byte count is tested to determine if it is zero, in which case the next eight bytes of the data string need to be moved from the memory 178 into to K shift register 188, and so the program branches back to step 218 so that the K shift register 188 is reloaded. If the byte count is nonzero, the shift register 188 does not need to be reloaded, and the program branches to step 222 εo that the current portion of the data εtring in the J regiεter 186 may be compared to the maεked keyword. Step 236 iε executed by instructions 32-35. Instruction 32 causes the contents of the ALU 140 to be sent to the zero detect circuit 150. If the zero detect circuit 150 detects a zero, inεtruction 33 causes a branch to instruction 7. Instruction 34 saves the decremented value of the byte count if it is nonzero, and instruction 35 causes a branch back to instruction 13. The bit mode of operation of the processor is generally similar to its byte mode of operation. In its bit mode of operation, the processor compares a selected string of bits to determine the presence of a selected keyword. Both the bit string and the keyword are selectable by the user of the procesεor. The basic process by which the processor testε for the preεence of a selected keyword within a selected bit εtring includeε initially loading the J and K εhift regiεterε 186, 188 with the firεt portion of the bit εtring to be tested. Then, the entire contents of the J shift register 186 are simultaneously compared with the keyword stored in the test register 130. If there is a match, the presence of a match is indicated by the procesεor. Then, the contentε of the J and K regiεterε 186, 188 are shifted left one bit and the contents of the J register 186 are again compared with the contents of the test register. Any match is indicated, and the process is repeated. Periodically, the K register 188 will become empty since its contents ar gradually shifted into the J register 186, and so the register 188 will be periodically reloaded with the nex portion of the bit string to be tested. In this manner, th entire keyword iε simultaneouεly compared with corresponding portion of the bit string. This proces reduces the number of comparisons required as shown by th example shown below, in which the keyword is "1101," the bi string is "11001110011011," and each number above the bi string representε the number of comparisonε that wer required to determine whether or not the keyword matche that particular portion of the bit string: Comparisonε: 1111111111 Bit String: 11001110011011 Keyword: 1101 Note that thiε particular example required only 1 comparisons to find the keyword "1101" in the bit strin "11001110011011" in contrast to the 22 comparisons tha were required by a conventional bit εtring processor a shown above. This reduction reεultε from the entire keywor simultaneously being compared with a portion of the bi string, instead of being compared one bit at a time. The detailed operation of the bit mode of the proceεεo iε very similar to the byte mode, and can be understood wit reference to Fig. 9 and Table 2 set forth below. Fig. 9 which is a flowchart of the microcode that controls th operation of the procesεor, iε very similar to the flowchar of Fig. 8, except that in a number of instanceε differen operations are executed since the processor is in its bi mode of operation and not its byte mode. Likewiεe, th software implementation set forth in Table 2 iε very εimila to that of Table 1, εo that only the differences need b explained to provide a clear understanding of the detailed operation of the bit mode of operation. TABLE 2 1 MOV #0, ENDFLAG ;reset end-of-εtrin flag to 0 2 MOV BITMASK, A ;mask keyword with bit mask 3 MOV KEYWORD, B 4 AND A, B 5 MOV ALU, TEST ;put masked keyword in test register MOV § ADDRESS, J ;load J with first 64 bits of data string 7 LOADK: MOV ADDRESS, A 8 MOV #8, B ;increment address by 8 to get next 64 bitε of data ADD A,B string and then load in K 20 NOMATCH: MOV #1, B ;decrement length o data string tested by 1 bit 21 MOV LENGTH, A 22 SUB A, B 23 MOV ALU, LENGTH 24 MOV ALU, ZD 25 BNZ NEXT ;data string completel tested? 26 EOS: MOV #1, ENDFLAG ;εet end-of-data-strin 27 END flag to 1 28 NEXT: LLS BIT ;left-shift J, K by 1 bit 29 MOV #1, B ;decrement # of bits in K by 1 30 MOV BITCOUNT, A 31 SUB A, B 32 MOV ALU, ZD ;if no bits left in K, get next 64 bitε of data εtring to load in K 33 BZ LOADK 34 MOV ALU, BITCOUNT 35 BR COMPARE ;test for match again • DAVIN COMPUTER CORP. 1987 In particular, at step 240 in Fig. 9 and instruction 12 in Table 2, the contents of the bit count register 132 are set to 64 εince the K shift register 188 will be shifted one bit at a time and 64 bits are initially loaded into the K register 188. At step 242 and instruction 28, the contents of the J and K shift regiεterε 186, 188 are εhifted left one bit instead of byte. At step 244 and instructions 29-31, the contents of the bit count register 132 instead of the byte count register 34 are decremented by one. Finally, at step 246 and instructions 32-35, the conditional branch occurε when the value of the bit count regiεter 132 has reached zero, and not the byte count register 134. The two modeε of operation just deεcribed are invoked by a uεer by including appropriate software instructions in the user'ε program. Specifically, the byte mode of operation iε invoked by the instruction "SCANS" and the bit mode of operation is invoked by the inεtruction "BITSCAN." Deεcription of Branch Instructions that utilize Parallel Byte Checking The above-deεcribed branch on any hit (BAH) inεtruction iε particularly advantageouε in determining when an input character string contains the byte or bytes in the keyword. Thus, by uεing the BAH inεtruction, the software can branch to a location to further procesε the input εtring. One of the firεt itemε of information that iε desirable to determine related to the input string is the location of the firεt byte that matcheε the correεponding byte of the keyword. For example, many programs parse input data by εearching for certain delimiters (e.g., a space, a comma, a period, a semicolon, or the like) . When a delimiter is found, the εoftware will cause the input data up to the delimiter to be evaluated in accordance with a predetermined rule. Thereafter, the data following the delimiter may be evaluated according to a separate rule. Thus, it is important to know where the delimiter is located in the input string. The conventional manner of finding delimiters is to take the input string and search through it on a character-by-character basis (i.e., a byte-by-byte basis) until the delimiter iε found. As set forth above, the parallel byte comparison operation of the present invention substantially reduces the amount of time required by identifying the multiple byte portion of the input εtring where the byte iε located εo that the byte-by-byte comparison need only be performed on that portion of the input εtring where the byte is located. Nevertheless, in a 64-bit computer having word lengths of eight bytes, each of the eight bytes would have to be compared to find the particular byte where the delimiter is located. A further improvement of the preεent invention comprises four instructionε to greatly improve the efficiency of locating the preciεe byte where the delimiter iε located or to find the firεt byte following the delimiter. The first instruction to improve the efficiency of the byte location operations iε a "find first hit" (FFH) instruction. The FFH instruction operates upon the hit register portion of the procesεor status register 100 of Figure 2 to identify the first byte in the input data string that is equal to the byte or bytes to which the input data string is being compared. For example, in the case where a single character (such as a control character or a delimiter) is reproduced in all eight bytes of a 64-bit word, and the input data string is being compared to the εingle character, the FFH inεtruction will generate an output code that identifieε the location of the firεt byte that iε equal to the εingle character. Aε a εpecific example, assume that the ASCII character code for a space (i.e., the hexadecimal value 20χg) is reproduced in all eight byteε of the regiεter A of Figure 2 aε follows: REGISTER A: 2020202020202020 and the following eight-byte portion of an input string, corresponding to "time iε ", iε loaded into the regiεter B of Figure 2: REGISTER B: 74696D6520697320 With this input data portion, after performing the exclusive-OR inεtruction described above, the eight-bit hit register portion of the proceεεor status register 100 of Figure 2 will comprise the following bits: Hit Register: 1 1 1 1 0 1 1 0 It should be recalled that in accordance with the convention chosen herein, a zero in the hit registe portion of the proceεεor status register 100 corresponds t a byte where the input data string matches the compariso byte and a one in the hit register portion of the processo statuε register 100 corresponds to a byte where the inpu data εtring does not match the comparison byte. Thus, ther are two zeros in the hit register portion of the procesεo status register corresponding to the two εpaces in the inpu data string. Given the foregoing example, the FFH instruction cause a location value of "4" to be generated to indicate tha byte 4 of the current portion of the input data string i the register B iε the first byte that matcheε th correεponding byte of the regiεter A. In the preferre embodiment of the preεent invention, the byteε are numbere from left to right rather than right to left. Thuε, "byt 0" referε to the most significant (i.e., leftmost) byte an "byte 7" refers to the leaεt significant (i.e., rightmost byte in a 64-bit word. It should be noted that thi convention is different from the labelling of the bits i which "bit 0" referε to the leaεt εignificant bit and "bi 63" referε to the moεt εignificant bit. Thiε convention also differs from the byte numbering convention illuεtrated in Figure 3 which refers to the byte number within the register. The choice of conventions relates to the particular application. In the description of the find instructions, the leftmost byte corresponds to the first data received in a string or a string portion and iε thus identified as byte 0 since the following bytes are referenced to the first byte. In the preferred embodiment of the present invention, the value of 4 is stored in a selected register where it iε available for subsequent instructions to operate upon the value. For example, the preferred format of the FFH instruction iε aε follows: FFH RXX where Rxx deεignates a particular register in the computer. As a specific example, the instruction FFH R27 when operating on the string example and character example set forth above, will cause the value of 4 to be generated and stored in the register 27 of the computer, where the register 27 is the deεtination for a particular regiεter in the A or B register file of Figure 5. From the foregoing, it can be seen that when the leftmost (most significant) byte of data in the register B matches the corresponding byte in the regiεter A, a location value of 0 iε generated; when the next moεt significant byte matcheε a location value of 1 iε generated; and so on. Thus, when the rightmost (least significant) byteε matcheε, a location value of 7 is generated. If none of the bytes compare, then a location value of 8 is generated to indicate that none of the bytes compared. Thus, a four-bit location value or code provides all the information necessary to determine whether there is a hit, and, if there is a hit, the location of the first hit. The next novel inεtruction that iε uεed in conjunction with the hit regiεter portion of the processor status register 100 is a "find first misε" (FFM) inεtruction. The FFM inεtruction iε similar to the FFH instruction; however, as its name implies, it identifies the location of the first byte in the input data string that is not equal to the byte or bytes to which the input data string iε being compared. The FFM inεtruction has utility, for example, in finding the firεt non-blank character in an input line. Aε a specific example, assume once again that the regiεter A of Figure 2 iε loaded with eight byteε of data representing eight spaces, as follows: REGISTER A: 2020202020202020 The following eight-byte portion of an input string, corresponding to " ABC ", is loaded into the register B of Figure 2: REGISTER B: 2020202020414243 With this input data portion, the pertinent eight-bit hi register portion of the procesεor statuε regiεter 100 o Figure 2 will comprise the following bits: Hit Register: 0 0 0 0 0 1 1 1 where a zero again representε a hit and a one representε miss. Thus, the location value generated by the FF inεtruction will be a "5" to indicate that the firεt miεs i in byte 5. As with the FFH instruction, the FFM instructio includes a register identifier to designate the regiεte where the location value identifying the byte location o the firεt miss is to be stored. For example, th instruction: FFM R23 cauεeε the location value 5 to be stored in the register 2 for the example presented above. Again, a location valu between 0 and 7 designates the location of the first miss. A location value of 8 indicates that there were no misses. The present invention also includes a "find first miss after firεt hit" (FFMAFH) inεtruction that iε uεeful for finding the beginnings or words in a text stream and other similar operations. For example, using the space character aε an example, it iε often desirable to skip to the next space character to find the end of a word and then skip over the next space character or characterε to find the beginning of the next word. The FFMAFH instruction performs this operation as a single instruction. This can be understood by referring again to the original example wherein the register A is loaded with eight space characters as follows: REGISTER A: 2020202020202020 The regiεter B iε again loaded with the string portion corresponding to "time is ", aε follows: REGISTER B: 74696D6520697320 With this input data portion, the pertinent eight-bit hit regiεter portion of the processor status register 100 of Figure 2 will again compriεe the following bitε: Hit Register: 1 1 1 1 0 1 1 0 Unlike the FFH hit instruction which generated a location value of 4 corresponding to the zero which indicates the byte where the firεt εpace character iε located, the FFMAFH instruction causes a location value of 5 to be generated which is the first misε (i.e., firεt non-blank character) after the firεt hit. Thus, with the location value generated by the FFMAFH instruction, a text processing program can immediately go to the beginning of the next word without having to methodically search each of the eight bytes in the string portion to find the first blank character and then find the first non-blank character that follows the firεt blank character. Aε with the previouε instructions, the full FFMAFH instruction format specifies the register into which the generated value is to be stored as follows: FFMAFH Rxx where Rxx is one of the registers in the register file, aε discussed above. A location value between 0 and 7 identifies the location of the first miss after the first hit. A location value of 8 indicates that there waε no firεt miεε after a firεt hit. A εimilar inεtruction to the FFMAFH inεtruction iε a "find firεt hit after firεt miεε" (FFHAFM) inεtruction. Unlike the FFMAFH inεtruction, the FFHAFM inεtruction looks for the first miεε in the input εtring portion and then finds the first hit thereafter. Using the space character as an example, a text proceεεor can advantageouεly uεe thiε inεtruction to skip from the end of one word to the end of the next word. For example, all eight bytes of the register A is again filled with data repreεenting the blank characte as follows: REGISTER A: 2020202020202020 The regiεter B is loaded with an eight-byte portion of a input data string having the characters " is the " aε follows: REGISTER B: 2069732074686520 With the foregoing data in the register A and the registe B, the hit register portion of the procesεor statuε registe 100 will compriεe the following bitε: Hit Regiεter: 0 1 1 0 1 1 1 0 The FFHAFM inεtruction will cause a value of 3 to b generated indicating the first hit (byte 3) after the firs misε (byte 1) in the eight-byte portion of the data string. Aε before, the FFHAFM instruction has the format: FFHAFM Rxx where Rxx designates a particular register into which the generated value will be loaded. A location value between 0 and 7 identifies the location of the firεt hit after the firεt miεε. A location value of 8 indicates that there was no first hit after a first miss. The foregoing find instructions also operate with string portions greater than a byte. For example, in some applications, it is desirable to determine whether a sixteen-bit portion of an input data string is equal to another sixteen-bit data string. In such applications, the find inεtructionε operate on a εixteen-bit (i.e., double byte) basis. For example, assume that the register A is loaded with the following data: REGISTER A: FE3CFE3CFE3CFE3C Further assume that the register B is loaded with the following data: REGISTER B: FE78BC3CFE3C8D56 The hit register portion of the procesεor εtatuε register 100 will comprise the following eight bits: Hit Register: 0 1 1 0 0 0 1 1 Although there a four byteε with hits, only one sixteen-bit portion of the input data string matches the sixteen-bit pattern in the register A. Thus, the FFH instruction will cause a location value of 4 to be generated to indicate that the εixteen-bit portion that compared starts in byte 4 of the input data string. When the FFH instruction iε operating on a double-byte baεis, the single byte compares of byte 0 and 3 do not cause a location value to be output. For example, the two compares in a row on bytes 3 and 4 will not cause a location value to be generated because the two bytes are in separate sixteen-bit groups. Since the FFH inεtruction operateε on two-byte boundarieε, the four poεεible location value outputs are 0, 2, 4 and 6 when a hit occurs and a value of 8 when no hit occurε. The find instructions also operate on a half-word (four-byte) baεiε by comparing 32 bitε in the comparison register with 32 bits of the input data string. For example, assume that the register A is loaded with the following εtring: REGISTER A: 1234567812345678 Further assume that the input data string is loaded into the register B as follows: REGISTER B: 1234567A12345678 The hit register portion of the procesεor εtatuε regiεte 100 will comprise the following bits: Hit regiεter: 0 0 0 1 0 0 0 0 The FFH inεtruction will generate a location value of 4 t indicate that the εecond 32-bit half-word matcheε th comparison εtring. The two possible location value output when a hit occurε are 0 and 4 which are the two half-wor boundaries. As before, a location value output of indicates that no hit occurred for the two half-words. The FFH instruction alεo operates on a full word basis. When operating on a full word basis, the location valu generated by the inεtruction will either be a 0 to indicat that the entire word matched beginning in byte 0 or an 8 t indicate that the word did not match. The FFM inεtruction operateε in a similar manner to th FFH instruction on multiple byte lengths. The FFMAFH and FFHAFM instructions operate on th double-byte length in a manner similar to the operation on single byte. However, it should be understood that th first misε after a firεt hit or the first hit after a firs misε can only occur in byteε 2, 4 or 6. Thuε, the onl valid location values generated by these instructions whe operating on double-byte lengths are 2, 4, 6 and 8. Wit reεpect to half-wordε, the only valid location value output are 4 and 8, since the first hit or miss after the firs miss or hit respectively must necessarily occur in th second half-word beginning in byte 4 or not occur at all. With respect to full word operations, the FFMAFH and FFHAF instructions always generate a location value of 8 sinc there can be no misε after a full word hit or a hit after full word miεε. The foregoing find instructions are implemented as εingle cycle instructions in the present invention i accordance with the block diagram of Figure 10. Fo simplification only the pertinent portions of the overall processor are shown. In particular, the procesεor εtatuε register 100 is shown along with a portion of the M-bus 184. The present invention further includeε an addreεε buffe circuit 500 that receives the eight bits from the hit register portion of the processor status register 100 via an eight-bit bus 502. (Although described above only with respect to the hit register portion, it should be understood that the processor status register 100 includes other status bits such as a carry bit, an overflow bit, a zero bit and a sign bit, that are conventionally available from the arithmetic logic unit of a proceεεor.) The addreεε buffer 500 further receiveε four bitε from an inεtruction regiεter 504 (shown in phantom) that latches the operation code data from an instruction memory (not εhown) and holdε i throughout an instruction cycle. The four bits from the instruction register 504 are labelled as A, B, C and D an are provided as inputs to the addreεε buffer on reεpective lineε 510, 511, 512 and 513. The output of the address buffer 500 comprises twelve bits on an address bus 520 that is provided to the address inputs of a PROM (programmable read only memory) 522. In the preferred embodimen described herein, the PROM 522 is a 4096 word by 4-bit PROM. It can thus be seen that the addresε input to the PROM 522 compriεeε eight bitε from the hit regiεter portion of the processor statuε register 100 and four bits from the instruction regiεter 504. Preferably, the leaεt significant eight address bits applied to the PROM 522 comprise the hit register bits and the most significant four bits comprise the four bits from the inεtruction regiεter 504. Alεo preferably, the eight bitε from the hit register portion of the proceεεor status register 100 are interchanged so that the least significant bit (bit 0) of the hit register iε connected to addreεε bit 7 of the PROM 522, bit 1 of the hit regiεter iε connected to addreεε bit 6 of the PROM 522, and so on such that bit 7 of the hit register is connected to address bit 0 of the PROM 522. The interconnection of the hit register bits to the addresε bitε of the PROM 522 iε matter of convenience in programming the PROM 522. I εhould be understood that the particular selection o address bits can be varied εo long aε the PROM 522 i programmed with the correct data for each addreεε. The PROM 522 provideε four output data bitε on a four bit PROM output buε 530. The PROM output buε 522 i provided aε an input to a εet of tri-εtate gateε 532. Th tri-εtate gateε 532 have outputε that are connected to th M-buε 184. The tri-εtate gateε 532 are enabled via a enable line 534 during the execution of the εelected fin inεtruction εo that the output bitε from the PROM 522 ar enabled onto the M-bus 184. The enable line 534 i connected to an output of an instruction decode circuit 53 (shown in phantom) which receives inεtruction data from th inεtruction regiεter 504 and provides a plurality of decode instruction outputs, one of which is the output on th enable line 534. The enable output on the line 534 i activated when the operation code correεponding to the fin instructions iε decoded by the inεtruction decode circui 536. The data on the M-buε 184 iε tranεferred to a selecte register via the buffer 170 and the A-buε 168 or via th buffer 174 and the B-buε 172 in a conventional manner i accordance with the destination register portion of the fin instruction, as discussed above. The four most significant address bits to the PROM 522 from the instruction register 502 are responsive to the particular find instruction and to the data length of the compares, aε diεcussed above. Bits A and B, the two most significant pair of bits from the instruction register 502, define the particular find instruction as follows: The second pair of bits from the instruction register, bits C and D, define the groupings of the data strings for finding the hits or the misses as follows: Group Len th One Byte Two Bytes Four Byteε (half word) Eight Byteε (full word) Thus, the entire memory area of the PROM 522 can be considered as being divided into four major groups with the addresεes 000-3FF (hexadecimal) defining the memory locations for the FFH instruction, the addresεes 400-7FF defining the memory locationε for the FFM inεtruction, the addresseε 800-BFF defining the memory locationε for the FFMAFH instruction, and the addresεes COO-FFF defining the memory locations for the FFHAFM instruction. Within each group of memory locations, the bits C and D define the memory locations for the various byte groupings. For example, for the FFH instruction, the memory locations 000- 0FF define the memory locations for the single byte FFH instruction, the memory locations 100-lFF define the memory locationε for the two byte FFH instructions, the memor locations 200-2FF define the memory locationε for the hal word (four byte) FFH instructionε, and the memory location 300-3FF define the memory locations for the full wor instructions. Similar groupings are provided for each o the FFM, FFMAFH and FFHAFM instructions. As can be seen from the foregoing, each of the fou byte groupings for each of the four instructions comprise 256 memory locations. The 256 memory locations correspon to each of the 256 possible combinations of the eight bit from the hit register aε provided by the eight leas significant address bits to the PROM 522. Thus, the PRO 522 provides a unique four-bit output for each combinatio of data from the hit regiεter for each byte grouping fo each of the four instructions. The data programmed into th PROM 522 can be readily determined in accordance with th above-described rules for generating the location values fo each instruction and each byte grouping. For convenience Appendix 3 provides a data listing for the 4096 addresεe of the PROM 522 programmed in accordance with the above described rules. In order to more clearly understand th PROM programming and the data conventions, a portion of th PROM liεting for the addresses 000-OOF for the single byt FFH instruction is εhown below: For compactness, only the hexadecimal codes for th addresses are shown in Appendix 3. However, the conversio from the hexadecimal codes to the individual bits is readil accomplished, as illustrated above. Before discussing the PROM programming in detail, i should be again noted that the hit register bits have bee reversed in the PROM addresses set forth above so that th least significant bit of the PROM addresε correεpondε to th moεt significant bit of the hit register. Furthermore, i is again noted that a hit is represented in the foregoin hit register bits aε a zero. Thus, addreεε 000 abov corresponds to all eight byteε of the two eight byte dat strings being equal. On the other hand, address OO corresponds to the least significant four bytes being equal (as represented by the zeros) and the four most significan bytes not being equal. Similarly, the address 00 correspondε to the moεt εignificant byte not being equa and the εeven least significant bytes being equal. Thus, for example, it can be seen that the addresε 007 produceε a location value output of "3" to indicate that byte 3 of th input εtring is the first byte to be equal to th corresponding byte in the compariεon εtring. A similar listing for the first sixteen addresseε fo the εingle byte FFM inεtruction iε εet forth below: 40E 0100 00001110 1 40F 0100 00001111 0 It εhould be noted that the location value output correεponding to the address 400 is an 8 to indicate that there were no misses. The location value outputs for the other addreεεeε indicate the location of the firεt one counting from .the right, thus corresponding to the first byte of the input string that is not equal to the corresponding byte of the comparison string. As set forth above, the remaining programming of the PROM 522 can be determined in accordance with the above- described rules and can be verified in Appendix 3. Since the PROM 522 is responsive to the change in the input addresses in accordance with the instruction in th instruction register 502 and in accordance with the hi register portion of the procesεor εtatuε regiεter 100, th data output from the PROM 522 can readily be provided in εingle instruction cycle. Thus, it can be seen that single find inεtruction quickly identifies a particular byt in an input string compared to the many instruction required in a conventional procesεor. Although described above in connection with a 64-bi procesεor, it should be underεtood that the fin instructions can be used with proceεsors having more o fewer bitε per word with suitable alterations in th circuitry to accommodate the different numbers of bitε. Description of Replicate Instruction As set forth above, in many of the operations performe with the -above-described parallel byte procesεor utilize repeated character in all eight byteε of a particula regiεter. Although there are known apparatuε and method fo duplicating the data in all eight bytes, such aε uεin εhift and OR instructions, the present invention provides novel replicate instruction that inserts the same data i all eight bytes in a single instruction cycle. The novel apparatus for replicating a single byte o data into all eight bytes of the 64-bit word is illustrate in Figure 11. The replication apparatuε comprises replication circuit 550 that has an input connected t receive eight bits (one byte) of data from the F-bus 148 an that generates 64 bitε (eight bytes) of data as an output t the M-bus 184. Preferably, the eight bits of input dat from the F-bus 148 comprise the eight least significant bit of the F-bus 148 and thus comprise the eight leas significant bits of the selected source that is enabled ont the F-bus 148. For example, the data on the F-bus 148 ca advantageously be the output of one of the registerε in th A register file or the B register file gated through the AL 140 of Figure 5, or alternatively, can be data from th M-bus 184. The 64 bits of output data generated by th replicate circuit 550 are gated onto the M-bus 184 i response to an active signal on an enable line 552, which i connected to an output of the instruction decode circuit 53 (shown in phantom) . The instruction decode circuit 53 decodes the instruction data from the instruction registe 504 (Figure 10) and enables the enable line 552 whenever th operation code for the replicate instruction appears in th instruction register 504. Preferably, as illustrated i Figure 12, the output circuits of the replicate circuit ar tri-εtate output circuits that enable data onto the M-bu 184 whenever the enable line 552 iε active. The operation of the replicate circuit is illustrate pictorially in Figure 11, wherein a first data word (i.e. eight bytes) on the F-bus 148 is illustrated as having th seven most significant bytes as X'ε, which designate don' cares in conventional terminology, and having a D in th least significant byte to illustrate the data to b replicated. The output data provided by the replicat circuit 550 onto the M-bus 184 is shown as an eight-byt output data word having a D in each of the eight bytes t indicate that the data byte D has been replicated in al eight bytes. Since the data has been gated onto the M-bus 184, the data can be transferred to a register in the regiεter file or the B regiεter file in a conventiona manner. Figure 12 illustrates a preferred implementation of th replicate circuit 550. As illustrated, the replicat circuit 550 compriseε an eight-bit data buffer 560 tha receiveε the eight bitε of data from the eight leaε εignificant bits (i.e., bits 0-7) of the F-bus 148 an provides eight buffered output bits. The buffered outpu bits are provided aε inputε to eight εetε of tri-εtate bu driverε 570-577. Each set of tri-state buε driverε 570-57 compriεeε eight buε driver gateε. For example, the tri εtate buε driverε 570-577 are advantageouεly SN74LS24 octal line driverε, available from Texaε Instrument Incorporated, or an equivalent circuit. As illuεtrated each octal line driver 570-577 receiveε all eight of th buffered output bitε from the data buffer 560. Each octa line driver 570-577 provideε one of the eight output byte of the replicate circuit 550. Thus, the eight bits of eac octal line driver 570-577 are connected to a reεpectiv eight-bit segment of the M-bus 184. For example, the eigh outputs of the octal line driver 570 are connected to bit 0-7 of the M-buε 184, the eight outputε of the octal lin driver 571 are connected to bits 8-15 of the M-bus 184, an so on, such that the eight outputs of the octal line drive 577 are connected to bits 56-63 of the M-buε 184. Each of the octal line driverε has a pair of enabl inputs, which, when activated by a logic 0 signal, enabl the data inputs onto the reεpective data outputs. Th enable inputs of each octal line driver 570-577 ar connected to a replicate enable line 580, which is connecte to the output of the instruction decode circuit 536 (show in phantom) . Thus, when the inεtruction decode circuit 53 decodeε the replicate instruction and activates th replicate enable line 580, the eight bits of data input t the data buffer 560 are replicated in the eight output bytes of the M-bus 184, as discuεsed above in connection wit Figure 11. Since there is relatively little propagatio delay through the data buffer 560 and the line drivers 570- 577, the replicate instruction is easily accomplished in a single procesεor instruction cycle. Although the foregoing embodiments of the present invention have been described in connection with a 64-bit data width, it should be understood that the same advantages can be provided in achineε having more or fewer bitε per data word (e.g., 16-bit, 32-bit and 128-bit parallel processors) . The differences between these embodiments include the data width of the buses, buffers, ALU, A and B latches, and registers. Otherwise, the operation of these additional embodiments is the same. Modifications and alternative embodiments of the invention will be apparent to thoεe skilled in the art in view of the foregoing description. Accordingly, thiε description is to be construed as illustrative only, and is for the purposes of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which come within the scope of the appended claims iε reserved. O module D8C7L8; flag '-r0' ; title 'PAL16L8 PAL DESIGN SPECIFICATION D8C7L8 U186 UN JAN 21, 1987 ALU FUNCTION SELECT BYTE 0, 1 DAVIN COMPUTER IRVINE, CALIFORNIA -Translated by TOABEL-' ; D8C7L8 device 'P16L8' ; "declarations TRUE,FALSE = 1,0; H,L - 1,0; Λ ? Z - x - t -' .Λ. , .._£. , .O. j GND.VCC pin 10,20; UALUO,UALUl,UALU2,WS0,WS1,DLB, !ICMPR, !UDI ,SHCY,UAS pin 1,2,3,4,5,6,8,9,11,7; S0B1.S2B0 pin 12,19; !ASUBB,ALUSUB,S2B1,S1B1,S1B0,SOBO pin 13,14,15,16,17,18; equations !S0B0 - 'UALUO & !UDIV & 'ICMPR # JUALUO & 'UDIV & ICMPR & ! S0 # WSO & 'UDIV & ICMPR ; !S1B0 - 'UALUl & 'UDIV & !ICMPR # !UALUl & !UDIV & ICMPR & !WS1 # SO & !UDIV & ICMPR # UDIV & !SHCY & 'ICMPR ; !S2B0 = ΪUALU2 & !UDIV & !ICMPR # IUALU2 & !UDIV & ICMPR & !WS2 # WS2 & !UDIV & ICMPR # UDIV & !ICMPR ; ASUBB = 1UALU2 & !UALUl & UALUO ; "UDIV =-> CONTROL FUNCTION SHT GROUP DIV "ICMPR ==> INSTRUCTION STATUS UPDATE CLASS 3, 4 OR MATCH ONLY JS0B1 = !UALUO & !UDIV & !ICMPR # 'UALUO & !UDIV & ICMPR & !WS0 # WSO & '.UDIV & ICMPR # DLB & iUAS & !ICMPR ; SUBSTITUTE SHEET !S1B1 = IUALU1 & !UDIV & !ICMPR _ J # IUALU1 & !WS1 & !UDIV & ICMPR # WS1 & !UDIV & ICMPR # UDIV & !SHCY & !ICMPR # DLB & !UAS & 'ICMPR ; !S2B1 - ΪUALU2 & !UDIV & 'ICMPR # JUALU2 & !WS2 & !UDIV & ICMPR # WS2 & 1UDIV & ICMPR # UDIV & 'ICMPR # DLB & !UAS ; 'ALUSUB - UALU2 # !UALU2 & !UALUl & !UALUO # IUALU2 & UALUl & UALUO ; "UDIV -=> CONTROL FUNCTION SHT GROUP DIV "ICMPR —=> INSTRUCTION STATUS UPDATE CLASS 3, 4 end _D8C7L8; SUBSTITUTE SHeCT module _D13C3R4; flag '-r0'; S 2. title 'PAL16R4 PAL DESIGN SPECIFICATION D13C3R4 U29 UN MAY 23, 1987 Z, U BIT (PSR, USR) DAVIN COMPUTER IRVINE, CALIFORNIA -Translated by TOABEL-' ; D13C3R4 device 'P16R4' ; "declarations TRUE,FALSE - 1,0; H,L - 1,0; vcc pin 20; CIB, «FDPSR,F14, !ZL, !ZU, IUPDUSR, !UPDBZ, IENUSET,UDATA3 pin 1,2,3,6,7,8,9,4,5; !ZERO, !USRZI,U,USRZ,ZBIT pin 13,14,15,16,17; !UPDCZ, !RSTD,F32 pin 12,18,19; equations !ZBIT :- UPDBZ & .'ZERO & 'FDPSR # FDPSR & !F14 # UPDCZ & ZERO & !ZBIT & !FDPSR # UPDCZ & .ZERO & ZBIT & 'FDPSR # !UPDBZ & IFDPSR & 'UPDCZ & IZBIT ; IUSRZ := UPDUSR & .ZERO # JUPDUSR & IUSRZ ; USRZI := UPDUSR & ZERO # !UPDUSR & USRZI ; !U :- FDPSR & !F32 & !U # ENUSET & ΪUDATA3 # RSTD # I FDPSR & IRSTD & I ENUSET & !U ; end D13C3R4 ; SUBSTITUTE SH5ET module _D13B4L8; flag '-r0'; title 'PAL16L8 PAL DESIGN SPECIFICATION D13B4L8 U27.U53 UN FEB 27, 1988 N BIT (HALF WORD, WORD) MICRO N DAVIN COMPUTER IRVINE, CALIFORNIA -Translated by TOABEL-' ; D13B4L8 device 'P16L8'; "declarations TRUE,FALSE - 1,0;. H,L - 1,0; f * j -** ..X.. , ./•. , . L>. GND.VCC pin 10,20; DLW,F63,AL63,BL63,COUT,DLHW,F31,AL31,BL31,CIN32 pin 1,2,3,4,5,6,7,8,9,11; IUNA, IUNB pin 12,19; !ASUBB, !ZEROA, IZEROB,N_C, IZU, !ZL pin 13,14,15,16,17,18; equations enable UNA - DLHW ; UNA = IAL31 & BL31 & ASUBB # IAL31 & IBL31 & ICIN32 & IZL & ASUBB # AL31 δ. BL31 & CIN32 & IZL & ASUBB # F31 & IASUBB ; "PIN 12 enable UNB = DLW ; UNB *= IAL63 & BL63 & ASUBB # IAL63 & IBL63 & ICOUT & IZL & IZU & ASUBB # AL63 & BL63 & COUT & IZL & IZU & ASUBB # F63 & IASUBB ; enable ZEROA - DLHW ; ZEROA = DLHW & ZL ; enable ZEROB = DLW ; ZEROB = DLW & ZL & ZU ; "PIN 19 " SAME EQ AS B, DB end D13B4L8; SUBSTITUTE SHξET module _JPAL; flag ' -r0 ' ; < J title 'PAL16R4 PAL DESIGN SPECIFICATION JPALR4 PAO AUG 07, 1986 SHIFTER J NUMBER 0 OF 31 (START WITH 0) *** APPLY TO ALL SHIFTER J 16R4 **** DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; JPAL device 'P16R4' ; "declarations TRUE,FALSE -= 1,0; H,L - 1,0; X,Z>,G - z »Λ. , ./-.. ,.C. j vcc pin 20; JCL A,JSOA,JSIA,JS2A,EN_JOUTA, IMULDIVA,JOSL,SHJ02,SHK56 pin 1,2,3,4,5,6,7,8,9; SHJ00,SHJ01,M0,M1 pin 14,15,16,17; G,SHK57,B0,B1 pin 11,12,18,19; JS - [JS2A , JSIA , JSOA] ; JCK •= JCLKA; OUT = EN_J0UTA ; MUL = MULDIVA ; equations enable Bl = EN_JOUTA ; IB1 = IJS2A & JSOA & ISHJOl & IMULDIVA # JSIA & JSOA & IM1 & IMULDIVA # JSIA & IJSOA & ISHJOl & IMULDIVA # IJS2A & JSIA & IJSOA & ISHJOO & MULDIVA # JS2A & JSIA & IJSOA & ISHJ02 & MULDIVA # JS2A & JSIA & JSOA & ISHJOl & IMULDIVA # JSIA & JSIA & JSOA & IM1 & IMULDIVA ; "OUT J.BIT SCAN "BIT,BYT SCN /(MSK*SHJ01) "SHL J, SHR J "DIV "MUL "BYT SCAN enable BO - EN_JOUTA ; IBO = IJS2A & JSOA & ISHJOO & IMULDIVA # JSIA & JSOA & IMO & IMULDIVA # JSIA & IJSOA & ISHJOO & IMULDIVA # IJS2A & JSIA & IJSOA & IJOSL & MULDIVA # JS2A & JSIA & IJSOA & ISHJOl & MULDIVA # JS2A & JSIA & JSOA & ISHJOO & IMULDIVA # JSIA & JSIA & JSOA & IMO & IMULDIVA ; "OUT J,BIT,BYT SCAN "BIT,BYT SCN /(MSK*SHJ00) "SHL J, SHR J "DIV "MUL "BYT SCAN IM1 :- JS2A & IJSIA & JSOA & !B1 # IJS2A & IM1 # JSIA & I l # IJSOA & IM1 ; "LD MASK "(ALL OTHER "CASE EQ "TO /Ml) IMO :- JS2A & IJSlA & JSOA & IBO # IJS2A & IMO # JSIA & IMO # IJSOA & IMO ; "LD MASK "(ALL OTHER "CASE EQ "TO /MO) ISHJOl := IJS2A & IJSIA & ISHJOl # IJS2A & JSIA & ISHJOO # JS2A & IJSIA & IJSOA & IB1 # JS2A & IJSIA & JSOA & ISHJOl # JS2A & JSIA & IJSOA & ISHJ02 # JS2A & JSIA & JSOA & ISHK57 ; "HOLD J, OUT J "SHL J, BIT SCAN "LOAD J "LD MSK, "SHR J "BYT SCAN ISHJOO := IJS2A & IJSIA & ISHJOO # IJS2A & JSIA & IJOSL # JS2A & IJSIA & IJSOA & IBO # JS2A & IJSIA & JSOA & ISHJOO # JS2A & JSIA & IJSOA & ISHJOl # JS2A & JSIA & JSOA & ISHK56 ; "HOLD J, OUT J "SHL J, BIT SCAN "LOAD J "LD MSK, "SHR J "BYT SCAN 90/05334 JS = [JS2A , JSIA , JSOA] S(* JCK - JCLKA; OUT - EN_JOUTA ; MUL = MULDIVA ; test vectors ( end JPAL; SUBSTITUTE S title 'PAL20R4 PAL DESIGN SPECIFICATION KPALR4 PAO OCT 29, 1986 SHIFTER K NUMBER 15 OF 15 (START WITH 0) *** APPLY TO SHK 2 TO 15 **** DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; KPAL device 'P20R4'; "declarations TRUE,FALSE - 1,0; H,L - 1,0; VCC pin 24; KCLKB, IKSOB, IKSIB, IKS2B, !EN_KOUTB, IKCLRB pin 1,2,3,4,5,6; SHK59,K63SR,SHK55,SHK54,SHK53,G,SHK52 pin 7,8,9,10,11,13,14; SHK60,SHK61,SHK62,SHK63 pin 17,18,19,20; B60,B61,B62,B63 pin 15,16,21,22; IB63 = ISHK63 & IKCLRB # KCLRB ; "OUT K enable B62 = EN KOUTB ; SUBSTITUTE SHEET IB62 = ISHK62 & IKCLRB - ξ # KCLRB ; "OUT K enable B61 EN KOUTB IB61 - ISHK61 & IKCLRB # KCLRB ; "OUT K enable B60 - ENJOUTB ; ΪB60 -= ISHK60 & IKCLRB # KCLRB ; "OUT K ISHK63 :- IKSOB & ISHK63 # IKS2B & IKSIB & KSOB & IB63 # IKS2B & KS1B & KSOB & ISHK62 # KS2B & IKSIB & KSOB & IK63SR # KS2B & KS1B & KSOB & ISHK55 "HOLD PRESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN, SH K LEFT BYT "K CLEAR ISHK62 :- IKSOB & ISHK62 # IKS2B & IKSIB & KSOB & IB62 # IKS2B & KS1B & KSOB & ISHK61 # KS2B & IKSIB & KSOB & ISHK63 # KS2B & KS1B & KSOB & ISHK54 "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN, SH K LEFT BYT "K CLEAR ISHK61 :~~ IKSOB & ISHK61 # IKS2B & IKSIB & KSOB & IB61 # IKS2B & KS1B & KSOB & ISHK60 # KS2B & IKSIB & KSOB & ISHK62 # KS2B & KS1B & KSOB & ISHK53 "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN, SH K LEFT BYT "K CLEAR ISHK60 :- IKSOB & ISHK60 # IKS2B & IKSIB & KSOB & IB60 # IKS2B & KS1B & KSOB & ISHK59 # KS2B & IKSIB & KSOB & ISHK61 # KS2B & KS1B & KSOB & ISHK52 "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN, SH K LEFT BYT "K CLEAR test vectors ( end KPAL; SUBSTITUTE SHEET module _KPALS; flag '-r0'; ζ,ό title 'PAL16R4 PAL DESIGN SPECIFICATION KPALSR4 PAO OCT 29, 1986 SHIFTER K NUMBER 0 OF 15 (START WITH 0) >» APPLY TO SHK 0 & 1 <« DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; KPALS device 'P16R4' ; "declarations TRUE,FALSE - 1,0; H,L - 1,0; vcc pin 20; KCLKA, IKSOA, IKSIA, IKS2A, !EN_KOUTA, !KCLRA,K0SL,SHK04 pin 1,2,3,4,5,6,7,8; SHKOO,SHK01,SHK02,SHK03 pin 14,15,16,17; SK3 - SHK03 equations enable B3 - EN_KOUTA ; IB3 - ISHK03 & IKCLRA # KCLRA ; "OUT K enable B2 - EN_KOUTA ; IB2 = ISHK02 & IKCLRA # KCLRA ; "OUT K enable Bl - EN_KOUTA ; . IB1 = ISHK01 & IKCLRA # KCLRA ; SUBSTITUTE SHEET I KCLRA 6 / "OUT K ISHK03 :- IKSOA & ISHK03 # IKS2A & IKSIA & KSOA & IB3 # IKS2A & KSIA & KSOA & ISHK02 # KS2A 6= IKSIA & KSOA & ISHK04 # KS2A & KSIA & KSOA ; "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN 0 IN "K CLEAR ISHK02 := IKSOA & ISHK02 # IKS2A & IKSIA & KSOA & IB2 # IKS2A & KSIA & KSOA & ISHK01 # KS2A & IKSIA & KSOA & ISHK03 # KS2A & KSIA & KSOA ; "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN 0 IN "K CLEAR ISHKOl := IKSOA & ISHKOl # IKS2A & IKSIA & KSOA & IB1 # IKS2A & KSIA & KSOA & ISHKOO # KS2A & IKSIA & KSOA & ISHK02 # KS2A & KSIA & KSOA ; "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN 0 IN "K CLEAR ISHKOO := IKSOA & ISHKOO # IKS2A & IKSIA & KSOA & IBO # IKS2A & KSIA & KSOA & IKOSL # KS2A & IKSIA & KSOA & ISHKOl # KS2A & KSIA & KSOA ; "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN 0 IN "K CLEAR end KPALS ; SUBSTITUTE SHEET module _SH12B5L8 ; flag ' -rO ' ; , title 'PAL16L8 PAL DESIGN SPECIFICATION . SH12B5L8 PAO MAY 05, 1986 SHIFTER CARRY GENERATOR DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH12B5L8 device 'P16L8' ; "declarations TRUE,FALSE - 1,0; H,L - 1,0; X.,Z,C *•*•*•* .. . ,.- . t .C„ i GND.VCC pin 10,20; ISHRIGHTX, !SHLEFT,SD1,SD0, ISHWAITRQ, ISHF_OP,SHKOO, IMUL, ILONG,SHJOO pin 1,2,3,4,5,6,7,8,9,11; ISHCYX pin 12; SHJ07,SHJ15,SHJ31,SHJ63, IUCY pin 13,14,15,16,18; SR - SHRIGHTX ; SL - SHLEFT ; J63 -= SHJ63 J31 - SHJ31 J15 - SHJ15 J7 - SHJ07 JO = SHJOO KO - SHKOO SD - [ SD1 , SDO ] ; equations SHCYX - SHLEFT & SD1 & SDO & SHJ63 & SHWAITRQ # SHLEFT & SD1 & ISDO & SHJ31 & SHWAITRQ # SHLEFT & ISD1 & SDO & SHJ15 & SHWAITRQ # SHLEFT & ISD1 & ISDO & SHJ07 & SHWAITRQ # SHRIGHTX & ILONG & IMUL & SHJOO & SHWAITRQ # SHRIGHTX & ILONG & MUL & SHKOO & SHWAITRQ # SHRIGHTX & LONG & SHKOO & SHWAITRQ; "WORD & LONG LEFT "HWORD LEFT "DBYTE LEFT "BYTE LEFT "NOT LONG RIGHT NOT MUL "NOT LONG RIGHT MUL "LONG RIGHT " ALL OF ABOVE ALSO QUALIFIED BY SHWAITRQ SR = SHRI nTX SL - SHLEFT ; &H J63 - SHJ63 J31 - SHJ31 J15 - SHJ15 J7 - SHJ07 JO - SHJOO SD - [ SD1 , SDO ] ; KO - SHKOO test vectors ( end SH12B5L8 ; mo u e _ ; ag -r ; title ' PAL16R4 PAL DESIGN SPECIFICATION SH12B7R4 PAO MAY 12, 1987. BEGIN OF SHIFTER OPERATION INDICATER DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH12B7R4 device 'P16R4' ; "declarations TRUE,FALSE - 1,0; H,L - 1,0; X, ,C * B * = .X.,. . f .C,j VCC pin 20; C2SHB, ISHRIGHTX,UGR2,UGR1,UGRO, lUDATAOX, IUDATA1X, IUDATA2X, IUDATA3X pin 1,2,3,4,5,6,7,8,9; ISHF_OP, ISHCYX, ISHCYXD,DIVTST pin 17,16,15,14 ; G, IGCTRCY, IJOSLB, ISHCY.C2SHBX pin 11,12,13,18,19; C2 - C2SHB ; UGR = [UGR2 , UGR1 , UGRO ] ; equations DIVTST :•= IGCTRCY & JOSLB # GCTRCY & DIVTST ; SHCYX :•= SHCY ; SHCYXD :-= IUGR2 & UGR1 & UGRO & SHCYX # I ( IUGR2 & UGR1 & UGRO ) & SHCYXD " WHEN IN SHIFTER GROUP UPDATE SHCYXD " WHEN NOT IN SHIFTER GROUP HAVE SHCYXD THE SAME SHF OP := IUGR2 & UGR1 & UGRO ; C2 - C2SHB ; UGR = [UGR2 , UGR1 , UGRO ] ; test_vectors ([ C2, G ISHF OP, ISHCY , ISHCYXD DIVTST C H Z Z Z Z C L H L X X C L L H L X C L L L H L C L L H L H c L L L H L SUBSTITUTE SHEET SUBSTITUTE SHEET module _SH11C7L8; flag '-r0'; title 'PAL16L8 PAL DESIGN SPECIFICATION SH11C7L8 PAO AUG 08, 1986 SHIFTER ENABLE, DIRECTION & DATA LENGTH CONTROL DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL- ' ; SH11C7L8 device 'P16L8'; "declarations TRUE.FALSE - 1,0; H,L == 1,0; , ,G ~ .X.,.Z.,.G«.J GND.VCC pin 10,20; UGR2,UGRl,UGRO,MEQl,UDATA5,UDATA4,GCTRSGN,15,14,UDTO pin 1,2,3,4,5,6,7,8,9,11; !SHLEFT, ISHRIGHTY pin 12,19; UDT1,UDT2,SDO,SD1, ISHRIGHTX, IEN_SHIF pin 13,14,15,16,17,18; UGR - [UGR2 , UGRl , UGRO ] ; SHR - [SHRIGHTX , SHRIGHTY ] ; SHL - SHLEFT ; GSIGN - GCTRSGN ; UDT - [UDT2 . UDT1.UDT0]; equations "COMMENT: SDO, SD1 ARE DECODED FROM U-CODE TO INDICATE THE DATA LENGTH. " SD1 SDO LENGTH EN_SHIF - IUGR2 & UGRl & UGRO & IMEQl ; "EN SHJK SHRIGHTX - IUGR2 & UGRl & UGRO & IMEQl & UDATA5 & IUDATA4 # IUGR2 & UGRl & UGRO & IMEQl & IUDATA5 & UDATA4 & IGCTRSGN ; "EN SHJK "DIR RIGHT SHRIGHTY - IUGR2 & UGRl & UGRO & IMEQl & UDATA5 & IUDATA4 # IUGR2 & UGRl & UGRO & IMEQl & IUDATA5 & UDATA4 & IGCTRSGN ; SUBSTITUTE SHEET "EN SHJK 6 % "DIR RIGHT SHLEFT - IUGR2 & UGRl & UGRO & IMEQl & UDATA5 & UDATA4 # IUGR2 & UGRl & UGRO & IMEQl & IUDATA5 & UDATA4 & GCTRSGN "EN SHJK "DIR LEFT ISDO = IUGR2 & UGRl & UGRO & IMEQl & IUDT2 & UDT1 & IUDTO # IUGR2 & UGRl & UGRO & IMEQl & UDT2 & 15 & 114 # IUGR2 & UGRl & UGRO & IMEQl & IUDT2 & IUDT1 & IUDTO # IUGR2 & UGRl & UGRO & IMEQl & UDT2 & 115 & 114 ; "NOT HWORD "& BYTE ISD1 = IUGR2 & UGRl & UGRO & IMEQl & IUDT2 & IUDT1 & UDTO # IUGR2 & UGRl & UGRO & IMEQl & UDT2 & 115 & 14 # IUGR2 & UGRl & UGRO & IMEQl & IUDT2 & IUDT1 & IUDTO # IUGR2 & UGRl & UGRO & IMEQl & UDT2 & 115 & 114 ; "NOT DBYTE "δ BYTE UGR - [UGR2 , UGRl , UGRO ] ; SHR - [SHRIGHTX , SHRIGHTY ] SHL - SHLEFT ; GSIGN - GCTRSGN ; UDT - [UDT2,UDT1,UDTO] ; test vectors UGR ,MEQ1 UDATA5 UDATA4 A hO H X X A h3 L L L A h3 L H L A h3 L H H A h3 L L H A h3 L L H A h3 L L H A h3 L L H A h3 L L H end SH11C7L8; SUBSTITUTE SHEET module _SH12C1L8 ; flag ' -r0 ' ; title 'PAL16L8 PAL DESIGN SPECIFICATION SH12C1L8 PAO AUG 08, 1986 SHIFTER K FUNCTION CONTROL DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH12C1L8 device 'P16L8' ; "declarations TRUE,FALSE - 1,0; H,L - 1,0; X, ,G ** = * X.,.Z.,.G,j GND.VCC pin 10,20; ISHLEFT, ISHRIGHTX,ZFG, IGCTRCY pin 1,2,3,4; lUDATAOX, IUDATAlX, IUDATA2X, IUDATA3X, !LD_SHK, !EN_SHIF pin 5,6,7,8,9,11; IKSIB, IKSIA pin 12,19; IKS2B, IKS2A, IKSOB, IKSOA pin 15,16,17,18; UDATA2X , UDATAlX , UDATAOX ] ; "NOTE SHLEFT,SHRIGHTX ARE ALSO USED AS QUALIFY SIGNAL FOR SHIFTER FUNCTION KSOA - LD_SHK # IUDATA3X & IUDATA2X & UDATAlX & UDATAOX & EN_SHIF & IGCTRCY # IUDATA3X & UDATA2X & IUDATAlX & EN_SHIF & IGCTRCY # UDATA3X & IUDATA2X & IUDATAlX & EN_SHIF & IGCTRCY # UDATA3X & UDATA2X & IUDATAlX & lUDATAOX & SHLEFT & IGCTRCY # UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IZFG & IGCTRCY ; "LOAD K "LOAG ROTATE LEFT,RIGHT "LONG LSH,ASH,LEFT,RIGHT "MUL,DIV "SHK LEFT BYTE "BIT,BYT SCAN KSIA = IUDATA3X & IUDATA2X & UDATAlX & UDATAOX & SHLEFT & IGCTRCY # IUDATA3X & UDATA2X & IUDATAlX & SHLEFT & IGCTRCY SBBflWϊfc SKEET # UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHLEFT & IGCTRCY # UDATA3X & UDATA2X & IUDATAlX 6c lUDATAOX & SHLEFT & IGCTRCY # UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IZFG & IGCTRCY ; "LOAG ROTATE LEFT "LONG LSH,ASH,LEFT "DIV "SHK LEFT BYTE "BIT,BYT SCAN KS2A - IUDATA3X & IUDATA2X & UDATAlX & UDATAOX & SHRIGHTX & IGCTRCY # IUDATA3X & UDATA2X & IUDATAlX & SHRIGHTX & IGCTRCY # UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX & SHRIGHTX & IGCTRCY # UDATA3X & UDATA2X & IUDATAlX & '.UDATAOX & SHLEFT & IGCTRCY # UDATA3X & UDATA2X & UDATAlX & '.UDATAOX & SHLEFT & IZFG & IGCTRCY ; "LOAG ROTATE RIGHT "LONG LSH,ASH,RIGHT "MU "SHK LEFT BYTE "BYT SCAN KSOB = LD_SHK # IUDATA3X & IUDATA2X & UDATAlX & UDATAOX & EN_SHIF & IGCTRCY # IUDATA3X & UDATA2X & IUDATAlX & EN_SHIF & IGCTRCY # UDATA3X & IUDATA2X & IUDATAlX & EN_SHIF & IGCTRCY # UDATA3X & UDATA2X & IUDATAlX & lUDATAOX & SHLEFT & IGCTRCY # UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IZFG & IGCTRCY ; "LOAD K "LOAG ROTATE LEFT,RIGHT "LONG LSH,ASH,LEFT,RIGHT "MUL,DIV "SHK LEFT BYTE "BIT,BYT SCAN KS1B = IUDATA3X & IUDATA2X & UDATAlX & UDATAOX & SHLEFT & IGCTRCY # IUDATA3X & UDATA2X & IUDATAlX & SHLEFT & IGCTRCY # UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHLEFT & IGCTRCY # UDATA3X & UDATA2X & IUDATAlX & lUDATAOX & SHLEFT & IGCTRCY # UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IZFG & IGCTRCY ; "LOAG ROTATE LEFT "LONG LSH,ASH,LEFT "DIV "SHK LEFT BYTE "BIT,BYT SCAN KS2B = IUDATA3X & IUDATA2X & UDATAlX & UDATAOX & SHRIGHTX & IGCTRCY # IUDATA3X & UDATA2X & IUDATAlX & SHRIGHTX & IGCTRCY # UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX & SHRIGHTX & IGCTRCY # UDATA3X & UDATA2X & IUDATAlX & lUDATAOX & SHLEFT & IGCTRCY # UDATA3X & UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IZFG & IGCTRCY ; SUBSTITUTE SHEET atr → aa_- , aaat_- , aι- ι aaa a t-'at- , ar , at- , at- 4 at- , aaaa x aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaf . . . . - - t → t- J ^ tr-' lr- , -r < _r^ t , ^ tr C-' < lr-' t-' tr^ t- , t^ tr^ < tr → aa t - ι aacaaara f aaar , a t - , a t - , a ! -'a t7 , ar-- . a t _-,aaa t -' aair , aat- , a __aat- , at- , aaat- , at- , ai- i air- ' ar i at- , atr* , aaair , - - aat- , aat- < aaa ι- ι aaaaar'aaar , aaatr , aaat-*aaaa aa t - ι aat- , aaat- ι aaaaat- , aaat- , aaat- , aaat- , aaaa aat- , aat-*aaa aat- | aaaaar , aaat- , aaa - , aaaaaa aa t - , aat-*aaa aa t - | aaaaar , aaatr , aaat- , aaaaaa module _SH11C5L8 ; flag r -r0 ' ; title 'PAL16L8 PAL DESIGN SPECIFICATION SH11C5L8 PAO MAY 07, 1987 SHIFTER K LINK CONTROL NUMBER 1 OF 2 (U50) DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH11C5L8 device 'P16L8'; "declarations TRUE,FALSE - 1,0; H,L - 1,0; , ,G - He .X. ,.Z.,.G.^ GND.VCC pin 10,20; IUCY, ISHLEFT, ISHCYX,UDATA6,SHJ63, ISHRIGHTY pin 1,2,3,4,5,6; IUDATA3X, IUDATA2X, IUDATAlX, lUDATAOX pin 7,8,9,11; KOSL, ISHCYJ pin 12,19; IMULDIVD, IMULDIVC, IMULDIVB, IMULDIVA,SHKOO, !SHF_OP pin 13,14,15,16,17,18; UDATA - [ UDATA3X , UDATA2X , UDATAlX , UDATAOX ] ; SL - SHLEFT ; SR = SHRIGHTY ; MDABCD - [MULDIVA , MULDIVB , MULDIVC , MULDIVD] ; OP - SHFJOP ; KO - SHKOO ; equations IKOSL - SHLEFT & IUDATA6 & ISHJ63 & IUDATA3X & IUDATA2X & UDATAlX & UDATAOX # SHLEFT & IUDATA3X & UDATA2X ξ_ IUDATAlX # SHLEFT & UDATA2X & UDATAlX & lUDATAOX # SHLEFT & UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & !SHF_OP & ISHKOO # SHLEFT & UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHF_OP & UCY # !SHF_OP & SHLEFT & UDATA6 & IUCY & IUDATA3X & IUDATA2X & UDATAlX & UDATAOX # SHF_OP & SHLEFT & UDATA6 & ISHCYX & IUDATA3X & IUDATA2X & UDATAlX & UDATAOX ; "LONG ROL, SHJ63 "LONG LOG,ARTH SHL, 0 IN "BIT,BYT SCAN, 0 IN "DIV 1ST CYC SHKOO SUBSTITUTE SHEET "DIV REST CYC IUCY "LONG ROL THRU CY FIRST CYCLE, KOSL - UCY "LONG ROL THRU CY RESET OF CYCLE , KOSL - SHCYX SHCYJ - SHF_OP & SHCYX # !SHF_OP & UCY ; "DIV "MUL MULDIVA - UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHLEFT # UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX & SHRIGHTY ; "DIV "MUL MULDIVB - UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHLEFT # UDATA3X & IUDATA2X & 'UDATAlX & lUDATAOX & SHRIGHTY ; "DIV "MUL MULDIVC - UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHLEFT # UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX & SHRIGHTY ; "DIV "MUL MULDIVD - UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHLEFT # UDATA3X & IUDATA2X & !UDATAlX & 'UDATAOX & SHRIGHTY ; "DIV "MUL - [ UDATA3X , UDATA2X , UDATAlX , UDATAOX ] ; - SHLEFT ; - SHRIGHTY ; - [MULDIVA , MULDIVB , MULDIVC , MULDIVD] ; - SHF_OP ; - SHKOO ; IMDABCD A hF A hF A hF A hF A hF A hF A hF A hF A hF A hF A hF hF Λ hF Λ hF A hO 7 if end SH11C5L8 ; SUBSTITUTE SHEET module _SH11B3L8 ; flag ' -r0 ' ; IS title 'PAL16L8 PAL DESIGN SPECIFICATION SH11B3L8 PAO MAY 06, 1987 SHIFTER J LINK CONTROL (U63) DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH11B3L8 device 'P16L8'; "declarations TRUE,FALSE - 1,0; H.L - 1,0; X,Z,G β .X.,.Z.,.G.^ GND.VCC pin 10,20; ISHRIGHTY,SDO,SD1,UDATA6, lUDATAOX, lUDATAlX, IUDATA2X, IUDATA3X,SHJOO, ISHCY pin 1,2,3,4,5,6,7,8,9,11; J15SR.J31SR pin 12,19; ISHCYJ,SHJ31,SHJ15, IUCY,SHJ32,SHJ16 pin 13,14,15.,16,17,18; SRY - SHRIGHTY ; SD - [ SD1 , SDO] ; UDATA - [ UDATA3X , UDATA2X , UDATAlX , UDATAOX ] ; JO - SHJOO J15 - SHJ15 J16 - SHJ16 J31 - SHJ31 J32 - SHJ32 equations IJ15SR - SHRIGHTY & ISDl & SDO & IUDATA3X & IUDATA2X & IUDATAlX & lUDATAOX # SHRIGHTY & ISDl & SDO & ISHJ15 & IUDATA3X & IUDATA2X & lUDATAlX & UDATAOX # SHRIGHTY & ISDl & SDO & IUDATA6 & ISHJOO & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX # SHRIGHTY & ISDl & SDO & UDATA6 & ISHCYJ & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX # SHRIGHTY & ISDl & SDO & UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX # SHRIGHTY & ISHJ16 & SD1 ; "LOG SHR DBYTE, 0 IN "ASH SHR DBYTE, SB SELF "ROR DBYTE,SHJOO "RRC DBYTE,SHCYJ "MUL DBYTE,0 IN "DIR RIGHT W,HW , SHJ16 IJ31SR = SHRIGHTY & SDl & ISDO & IUDATA3X & 1UDATA2X & IUDATA1X & lUDATAO # SHRIGHTY & SDl & ISDO & ISHJ31 & IUDATA3X & IUDATA2X δ. lUDATAlX & UDATAOX # SHRIGHTY & SDl & ISDO & IUDATA6 & ISHJOO & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX # SHRIGHTY & SDl & ISDO & UDATA6 & ISHCYJ & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX # SHRIGHTY & SDl & ISDO & UDATA3X & IUDATA2X & IUDATAlX & '.UDATAOX # SHRIGHTY & ISHJ32 & SDl & SDO ; "LOG SHR HWORD, 0 IN "ASH SHR HWORD,MSB SELF "ROR HWORD,SHJOO "RRC HWORD,SHCYJ "MUL HWORD,0 IN "DIR RIGHT W.SHJ32 SRY - SHRIGHTY ; SD - [ SDl , SDO] ; UDATA - [ UDATA3X , UDATA2X , UDATAlX , UDATAOX ] ; JO = SHJOO J15 - SHJ15 J16 - SHJ16 J31 - SHJ31 J32 - SHJ32 test vectors ( >[J15SR >[ H SUBSTITUTE SHEET end SH11B3L8 ; module _SH11B1L8 ; flag ' -rO' ; title 'PAL16L8 PAL DESIGN SPECIFICATION SH11B1L8 PAO MAY 06, 1987 SHIFTER J LINK CONTROL (U62) DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH11B1L8 device 'P16L8' ; "declarations TRUE,FALSE -= 1,0; H,L -= 1,0; J , /__» t *-* •• " • - • Λ.. f ■ • • • , ■ G • ϊ GND.VCC pin 10,20; ISHRIGHTY,SDO,SDl.UDATA6, lUDATAOX, lUDATAlX, IUDATA2X, IUDATA3X.SHJ00, ISHC pin 1,2,3,4,5,6,7,8,9,11; J63SR.J7SR pin 12,19; SHJ63,SHJ08,SHKOO, IUCY,SHJ07, ISHCYJ pin 13,14,15,16,17,18; SRY - SHRIGHTY ; SD - [ SDl , SDO] ; UDATA = [ UDATA3X , UDATA2X , UDATAlX , UDATAOX ] ; JO - SHJOO J7 = SHJ07 J8 = SHJ08 J63 •= SHJ63 KO = SHKOO equations IJ7SR *= SHRIGHTY & ISDl & ISDO & IUDATA3X & IUDATA2X & lUDATAlX & lUDATAOX # SHRIGHTY & ISDl & ISDO & ISHJ07 & IUDATA3X & IUDATA2X & IUDATAlX & UDATAOX # SHRIGHTY & ISDl & ISDO & IUDATA6 & ISHJOO & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX # SHRIGHTY & ISDl & ISDO & UDATA6 & ISHCYJ & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX # SHRIGHTY & ISDl & ISDO & UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX # SHRIGHTY & ISHJ08 & SDl # SHRIGHTY & ISHJ08 & SDO ; "LOG SHR BYTE, 0 IN "ASH SHR BYTE,MSB SELF "ROR BYTE,SHJOO "RRC BYTE,SHCYJ "MUL BYTE.O IN "DIR RIGHT W,HW , SHJ08 "DIR RIGHT W,DB r SHJ08 SUBSTITUTE SHEET IJ63SR = SHRIGHTY & SDl & SDO & IUDATA3X & lUDATAlX & lUDATAOX # SHRIGHTY & SDl & SDO & ISHJ63 & IUDATA3X & lUDATAlX & UDATAOX # SHRIGHTY & SDl & SDO & IUDATA66= ISHJOO & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX # SHRIGHTY & SDl & SDO & IUDATA6 & ISHKOO & IUDATA3X & IUDATA2X & UDATAlX & UDATAOX # SHRIGHTY & SDl & SDO & UDATA6 & ISHCYJ & IUDATA3X & IUDATA2X & UDATAlX # SHRIGHTY & SDl & SDO & UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX ; "(LONG) LOGIC SHR WORD, 0 IN "(LONG) ASH SHR WORD,MSB SELF "ROR WORD,SHJOO "LONG ROR WORD,SHJOO "RRC.LRRC WORD,SHCYJ "MUL WORD.O IN UDATAlX , UDATAOX ] ; SUBSTITUTE SHEET end _SH11B1L8; _ title 'PAL16L8 PAL DESIGN SPECIFICATION SH12C3L8 PAO OCT 28, 1986 SHIFTER FUNCTION I/O CONTROL (U8) DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH12C3L8 device 'P16L8' ; "declarations TRUE,FALSE - 1,0; H . L - 1,0; X,Z,C — .X.,.Z.,.C.; GND.VCC pin 10,20; ISHLEFT, ISHCY, ISHCYX, IGCTRCY,ZFG pin 1,2,3,4,5; lUDATAOX, IUDATAlX, IUDATA2X, IUDATA3X.C2SHB pin 6,7,8,9,11; ISHWAITRQ, IENA_JOUT pin 12,19; UGR2,UGRl,UGRO,MEQl pin 13,14,17,18; SL - SHLEFT ; GC - GCTRCY ; UDATA - [UDATA3X , UDATA2X , UDATAlX , UDATAOX ] ; C2 - C2SHB ; UGR - [UGR2 , UGRl , UGRO] ; equations "NOTE SHLEFT ARE USED AS ENABLE SIGNAL FOR SHIFTER FUNCTIONS ENA_JOUT = UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IZFG & IGCTRCY & C2SHB # IMEQl & IUGR2 & UGRl & UGRO & UDATA3X & IUDATA2X & !UDATAlX & IGCTRCY & C2SHB ; "C2SHB*(BIT,BYT SCAN) "C2SHB*(MUL,DIV) SHWAITRQ - IMEQl & IUGR2 & UGRl & UGRO & IUDATA3X & IUDATA2X & IGCTRCY # IMEQl & IUGR2 & UGRl & UGRO & IUDATA3X 6= IUDATAlX & IGCTRCY # IMEQl & IUGR2 & UGRl & UGRO & IUDATA2X & IUDATAlX & IGCTRCY # IMEQl & IUGR2 & UGRl & UGRO & UDATA3X & UDATA2X & IUDATAlX & lUDATAOX & IGCTRCY # IMEQl & IUGR2 & UGRl & UGRO & UDATA2X & UDATAlX & lUDATAOX & IGCTRCY & IZFG # IMEQl & IUGR2 & UGRl & UGRO & IUDATA3X & UDATA2X & UDATAlX & UDATAOX & IGCTRCY & .'SHCYX SUBSTITUTE SHEET "LOGSHF,ARSHF,ROT S "LONG LOGSHF,ARSHF,ROT "MUL,DIV "SHK LEFT BYTE "BIT BYT SCAN "LOC LEAD "1 BIT SL - SHLEFT ; GC - GCTRCY ; UDATA - [UDATA3X , UDATA2X , UDATAlX , UDATAOX ] ; C2 - C2SHB ; UGR - [UGR2 , UGRl , UGRO] ; test vectors ->[ IENAJOUT, ISHWAITRQ]) end _SH12C3L8 ; SUBSTITUTE SHEET module _SH9B1R4 ; flag ' -r0 ' ; <ζ$ title 'PAL16R4 PAL DESIGN SPECIFICATION SH9B1R4 PAO MAY 07, 1987 SHIFTER K NUMBER 0 OF 15 (START WITH 0) >» APPLY TO SHK 0 & 1 <« DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH9B1R4 device 'P16R4' ; "declarations TRUE,FALSE - 1,0; H,L - 1,0; VCC pin 20; KCLKA, IKSOA, IKSIA, IKS2A, !EN_KOUTA, IKCLRA,KOSL.SHK04, IMULDIV pin 1,2,3,4,5,6,7,8,9 ; SHKOO,SHK01,SHK02,SHK03 pin 14,15,16,17; G,B0,B1,B2,B3 pin 11,12,13,18,19; enable B3 = EN OUTA ; IB3 - ISHK03 & IKCLRA # KCLRA ; "OUT K enable B2 - ENJKOUTA ; IB2 = ISHK02 & IKCLRA # KCLRA ; "OUT K enable Bl •= ENJCOUTA ; IB1 = ISHKOl & IKCLRA # KCLRA ; "OUT K SUBSTITUTE SHEET enable BO - EN_K0UTA ; *g * 1 I BO = I SHKOO & IKCLRA # KCLRA ; "OUT K ISHK03 := IKSOA & ISHK03 # IKS2A & IKSIA & KSOA & IB3 # IKS2A & KSIA & KSOA & ISHK02 # KS2A & IKSIA & KSOA & ISHK04 # KS2A & KSIA & KSOA ; "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN 0 IN "K CLEAR ISHK02 :- IKSOA & ISHK02 # IKS2A & IKSIA & KSOA & IB2 # IKS2A & KSIA & KSOA & ISHKOl # KS2A & IKSIA & KSOA & ISHK03 # KS2A & KSIA & KSOA ; "HOLD K,RESERVED "LOAD K "SH K LEFT "SH K RIGHT "BYT SCAN 0 IN "K CLEAR ISHKOl :- IKSOA & ISHKOl # IKS2A & IKSIA & KSOA & IBl # IKS2A & KSIA & KSOA & IMULDIV & ISHKOO # IKS2A & KSIA & KSOA & MULDIV & IKOSL # KS2A & IKSIA & KSOA & ISHK02 # KS2A & KSIA & KSOA ; "HOLD K,RESERVED "LOAD K "SH K LEFT NORMAL CASE "SH K LEFT DIVID CASE "SH K RIGHT "BYT SCAN 0 IN "K CLEAR ISHKOO := IKSOA & ISHKOO # IKS2A & IKSIA & KSOA & IBO # IKS2A & KSIA & KSOA & IMULDIV & IKOSL # IKS2A & KSIA & KSOA & MULDIV # KS2A & IKSIA & KSOA & ISHKOl # KS2A & KSIA & KSOA ; "HOLD K,RESERVED "LOAD K "SH K LEFT NORMAL CASE FROM KOSL "SH K LEFT DIVID CASE 0 IN "SH K RIGHT KSOA] test vectors ([KC [C [C [C [C [C [C [c [c [c [c [C [C [C [C [c [C [c [C [C [C [C end SH9B1R ; SUBSTITUTE SHEET module _SH12C7L8 ; flag ' -r0 ' ; ^& title 'PAL16L8 PAL DESIGN SPECIFICATION SH12C7L8 PAO MAY 13, 1987 SHIFTER FUNCTION CONTROL DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH12C7L8 device 'P16L8'; "declarations TRUE,FALSE - 1,0; H,L - 1,0; GND.VCC pin 10,20; ISHLEFT, ISHRIGHTX, ISHCY, IGCTRCY,ZFG pin 1,2,3,4,5; lUDATAOX, IUDATAlX, IUDATA2X, !UDATA3X,C2SHB, ISHCYX, ISHCYXD, ISHCYDLP pin 6,7,8,9,11,13,14,15 ; JSHJS1B.ISHJS2A pin 12,19; ISHJS1A, ISHJSOA pin 17,18; SL - SHLEFT ; SR - SHRIGHTX ; GC - GCTRCY ; UDATA - [UDATA3X , UDATA2X , UDATAlX , UDATAOX] ; C2 - C2SHB ; equations "NOTE SHLEFT,SHRIGHTX ARE USED AS QUALIFY SIGNAL FOR SHIFTER FUNCTION SHJSOA = UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IGCTRCY & IZFG ; "BIT,BYT SCAN "ALL SHIFT RIGHT RELATED CASE ARE IN SH12B7R4.ABL SHJS1A - IUDATA3X & IUDATAlX & SHLEFT & IGCTRCY # IUDATA3X & IUDATA2X & SHLEFT & IGCTRCY # IUDATA3X & UDATA2X & UDATAlX & UDATAOX & SHLEFT & IGCTRCY & ISHCY # UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHLEFT & IGCTRCY & C2SHB # UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IGCTRCY & IZFG ; "LOG SHL, ARTH SHL,ROL "(LONG & NO LONG) "LOC LEAD 1 BIT SUBSTITUTE SHEET "DIV (2ND HALF CYC WILL "LOAD J FROM ALU) S7 "BIT,BYT SCAN SHJS2A - IUDATA3X & lUDATAlX & SHRIGHTX & IGCTRCY # IUDATA3X & IUDATA2X & SHRIGHTX & IGCTRCY # UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX & SHRIGHTX & IGCTRCY & C2SHB # UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX & SHRIGHTX & IGCTRCY & IC2SHB # UDATA3X & UDATA2X & UDATAlX & lUDATAOX & SHLEFT & IGCTRCY & IZFG # UDATA3X & IUDATA2X & IUDATAlX & UDATAOX & SHLEFT & IGCTRCY & IC2SHB ; "LOG SHR.ARTH SHR,ROR "(LONG & NO LONG) "MUL & 1ST HALF CYC "MUL & 2ND HALF CYC WILL BE LOAD J "LOAD J FROM ALU "BYT SCAN "DIVID 2ND CYC WILL BE LOAD J SHJS1B - IUDATA3X & IUDATAlX & SHRIGHTX & IGCTRCY # IUDATA3X & IUDATA2X & SHRIGHTX & IGCTRCY # UDATA3X & IUDATA2X & IUDATAlX & lUDATAOX & SHRIGHTX & IGCTRCY & C2SHB ; "LOG SHR.ARTH SHR,ROR "(LONG & NO LONG) "MUL(2ND HALF CYC WILL " LOAD DATA FROM ALU) SHCYDLP - UDATA3X & IUDATA2X & IUDATAlX & SHCY # !( UDATA3X & IUDATA2X & IUDATAlX ) & SHCYXD ; "FOR MUL & DIV CASE CY TO DLOOP WILL BE NO DELAY "ALL THE OTHER CASE CY TO DLOOP WILL BE DELAY BY 2 u-CYC SL - SHLEFT ; SR •= SHRIGHTX ; GC - GCTRCY ; UDATA - [UDATA3X , UDATA2X , UDATAlX , UDATAOX] C2 - C2SHB ; CARY - [ SHCY , SHCYX] ; test_vectors ( UBSTITUTE SH H ] H ] H ] L ] H 3 H 3 H ] L 3 S 3 H ] H ] L ] H ] H ] H 3 L ] H 3 H 3 H ] H 3 H 3 H 3 H ] L j H ] H ] H 3 H 3 H 3 H ] H ] H ; H H H H H end SH12C7L8 ; SUBSTITUTE SHEET module _SH11C3L8 ; flag ' -rO' 9 title 'PAL16L8 PAL DESIGN SPECIFICATION SH11C3L8 PAO AUG 08, 1986 SHIFTER K LINK CONTROL NUMBER 2 OF 2 (U19) DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH11C3L8 device 'P16L8'; "declarations TRUE,FALSE - 1,0; H,L - 1,0; A., Z., ---*■ . .. } .Z- * , . *. , GND.VCC pin 10,20; ISHRIGHTY, ILONG,SHJOO,SDl,SDO,SHK08,SHK16,SHK32, IMUL pin 1,2,3,4,5,7,8,9,11; K31SR,K15SR pin 12,19; K63SR.K7SR pin 16,17; SD - [ SDl , SDO ] ; SR - SHRIGHTY; JO -= SHJOO; K8 - SHK08; K16 - SHK16; K32 - SHK32; equations ** ***** NOTE: SHRIGHTY IS AN ENABLE SIGNAL FOR SHIFTER FUNCTION ALSO IK7SR - SHRIGHTY & LONG & ISHK08 # SHRIGHTY & MUL & SDO & ISHK08 # SHRIGHTY & MUL & SDl & ISHK08 # SHRIGHTY &---MUL & ISDl & ISDO & ISHJOO ; "LONG RIGHT, SHK08 "DBYTE, ORD MUL, SHK32 "HWORD, ORD MUL, SHK32 "BYTE MUL, SHJOO IK15SR = SHRIGHTY & LONG & ISHK16 # SHRIGHTY & MUL & SDl & ISHK16 # SHRIGHTY & MUL & ISDl & SDO & ISHJOO ; "LONG RIGHT, SHK16 "HWORD, ORD MUL, SHK16 "DBYTE MUL, SHJOO SUBSTITUTE SH . # SHRIGHTY & MUL & SDl & SDO & ISHK32 # SHRIGHTY & MUL & SDl & ISDO & ISHJOO "LONG RIGHT, SHK32 "WORD MUL, SHK32 "HWORD MUL, SHJOO IK63SR - SHRIGHTY & LONG & ISHJOO # SHRIGHTY & MUL & SDl & SDO & ISHJOO X H L X X X X X X L H end SH11C3L8; SUBSTITUTE SHEET module _SH11B5L8 ; flag ' -r0 ' ; I title 'PAL16L8 PAL DESIGN SPECIFICATION SH11B5L8 PAO AUG 07, 1986 SHIFTER J LINK CONTROL NUMBER 1 OF 2 DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH11B5L8 device 'P16L8' ; "declarations TRUE,FALSE - 1,0; H . L - 1,0; X,Z,C — .X.,.Z.,.C.; GND.VCC pin 10,20; SHJ07,SDO,SDl, ISHLEFT, lUDATAOX, IUDATAlX, IUDATA2X, IUDATA3X, IUCY.SHK63 pin 1,2,3,4,5,6,7,8,9,11; IJOSLA, IJOSLAX pin 12,19; SHJ63,SHJ31,SHJ15.UDATA6, ISHCY, ISHF_OP pin 13,14,15,16,17,18; SL - SHLEFT; SD - [SDl , SDO] ; UDATA - [UDATA3X , UDATA2X , UDATAlX , UDATAOX] ; J7 - SHJ07 J15 - SHJ15 J31 - SHJ31 J63 - SHJ63 K63 = SHK63 OP - SHF_0P ; equations enable JOSLAX - UDATA6 ; JOSLAX - !SHF_OP & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX & UCY & SHLEFT # SHF_OP & IUDATA3X & IUDATA2X & UDATAlX & lUDATAOX & SHCY & SHLEFT # SHLEFT & IUDATA3X & UDATA2X & IUDATAlX & SHK63 # SHLEFT & IUDATA3X & IUDATA2X & UDATAlX & UDATAOX & SHK63 ; "RLC FIRST CYCLE, JOSL = UCY "RLC REST CYCLE, JOSL = SHCY "LONG LEFT SHIFT, SHK63 "LONG LEFT ROTATE, SHK63 enable JOSLA = IUDATA6 9* JOSLA - SHLEFT & SDl δc SDO δc SHJ63 δc IUDATA3X & IUDATA2X δc UDATAlX δc lUDATAOX # SHLEFT δc SDl δ= ISDO δc SHJ31 δc IUDATA3X δc IUDATA2X δc UDATAlX δ. lUDATAOX # SHLEFT δc ISDl δc SDO δc SHJ15 δc IUDATA3X δc IUDATA2X δ. UDATAlX & lUDATAOX # SHLEFT & ISDl & ISDO δc SHJ07 δc IUDATA3X & IUDATA2X δc UDATAlX δc lUDATAOX # SHLEFT δc IUDATA3X δc UDATA2X & IUDATAlX δc SHK63 # SHLEFT δc IUDATA3X δc IUDATA2X δc UDATAlX δc UDATAOX δc SHK63 "WORD ROL, SHJ63 "HWORD ROL, SHJ31 "DBYTE ROL, SHJ15 "BYTE ROL, SHJ07 "LONG LEFT SHIFT, SHK63 "LONG LEFT ROTATE, SHK63 SL - SHLEFT SD - [SDl , SDO] UDATA - [UDATA3X , UDATA2X , UDATAlX , UDATAOX] J7 - SHJ07 J15 - SHJ15 J31 - SHJ31 J63 - SHJ63 K63 - SHK63 OP - SHF OP test vectors ( ->[!JOSLA IJOSLAX ->[ z H L H L L H L H L H L H L H L H Z Z Z Z Z Z Z Z Z Z Z Z 9 end SH11B5L8; SUBSTITUTE SHEET module _SH11B7L8 ; flag ' -r0' ; ^> title 'PAL16L8 PAL DESIGN SPECIFICATION SH11B7L8 PAO DEC 19, 1986 MULTIPLY, DIVISION, & BIT SCAN LINK CONTROL FOR JOSL (U17) DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH11B7L8 device 'P16L8'; "declarations TRUE, FALSE - 1, 0 ; H,L - 1,0; GND .VCC pin 10 , 20 ; IUDATA3X, IUDATA2X, lUDATAlX, lUDATAOX,SDl,SDO,SHK07,SHK15,SHK31,SHK63 pin 1,2,3,4,5,6,7,8,9,11; IARSH, IJOSLB pin 12,19; ISHLEFT, ISHFJDP, IMUL, ILONG pin 13,14,17,18; UDATA - [UDATA3X.UDATA2X,UDATAlX,UDATAOX] ; SD - [SDl,SDO]; K7 - SHK07; K15 = SHK15; K31 - SHK31; K63 - SHK63; SL - SHLEFT; equations " COMMENT: 1 BIT SCAN WILL BE IN WORD ONLY JOSLB - SHLEFT δc IUDATA3X δc UDATA2X δ UDATAlX δ= lUDATAOX & SDl δc SDO δc SHK63 # SHLEFT δc UDATA3X δc IUDATA2X δc IUDATAlX δc UDATAOX & SDl δc SDO δc SHK63 # SHLEFT δc UDATA3X & IUDATA2X δc IUDATAlX δc UDATAOX δc SDl δc ISDO δc SHK31 # SHLEFT & UDATA3X δc IUDATA2X δc IUDATAlX δc UDATAOX δc ISDl δ. SDO δc SHK15 # SHLEFT δc UDATA3X & IUDATA2X δc IUDATAlX δc UDATAOX δc ISDl δc ISDO δc SHK07 ; "BIT SCAN, SHK63 "WORD DIV "HWORD DIV "DBYTE DIV "BYTE DIV ARSH = IUDATA3X δc IUDATAlX δc UDATAOX ; "ARITH SH.LONG ARITH SH < LONG - IUDATA3X δc IUDATA2X δc UDATAlX δ UDATAOX # IUDATA3X c UDATA2X δc IUDATAlX ; "LONG ROTATE "LONG LOGIC AND "ARITHMETIC SHIFT MUL - UDATA3X δc IUDATA2X δc IUDATAlX δc lUDATAOX ; "MULTIPLY UDATA - [UDATA3X,UDATA2X,UDATAlX,UDATAOX] ; SD - [SDl,SDO] ; K7 - SHK07; K15 - SHK15; K31 - SHK31; K63 - SHK63; SL - SHLEFT; test vectors ( end SH11B7L8; module _SH12B3R4; flag '-rO'; title ^ 'PAL16R4 PAL DESIGN SPECIFICATION SH12B3R4 PAO DEC 23, 1986 OVERFLOW FLAG GENERATOR (U41) DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH12B3R4 device 'P16R4' ; "declarations TRUE,FALSE - 1,0; H,L - 1,0; Λ,_Z,C •*= ._v«, •__.,. .ϊ GND.VCC pin 10,20; C2, ISHLEFT,SDl,SDO, !ARSH,SHJ63,SHJ31,SHJ15,SHJ07,G pin 1,2,3,4,5,6,7,8,9,11; ISHAROV,Ql, ISHWAITRQD,Q0 pin 17,15,16,14; IOVFL2, IOVFL1, ISHWAITRQ, ISHCYX pin 12,13,18,19; SL = SHLEFT ; J63 - SHJ63 J31 - SHJ31 J15 - SHJ15 J7 - SHJ07 SD = [SDl , SDO ]; SHRV - SHAROV ; SHCX - SHCYX ; SW - SHWAITRQ ; SWD - SHWAITRQD ; VI = OVFL1 ; V2 - OVFL2 ; SV = SHAROV ; " States 50 = A bll; 51 = A blO; 52 = A b00; equations OVFL2 = ARSH δ_ SHLEFT δc SHWAITRQD & SDl δc SDO δc SHJ63 δc ISHCYX # ARSH δc SHLEFT δc SHWAITRQD & SDl δc SDO δc ISHJ63 δc SHCYX # ARSH δc SHLEFT & SHWAITRQD δc SDl δ. ISDO δc SHJ31 δc ISHCYX # ARSH δc SHLEFT δc SHWAITRQD δc SDl δc ISDO δc ISHJ31 δc SHCYX ; OVFL1 = ARSH δc SHLEFT δc SHWAITRQD δc ISDl δ. SDO δc SHJ15 δc ISHCYX # ARSH δc SHLEFT δc SHWAITRQD δc ISDl δc SDO δc ISHJ15 δc SHCYX # ARSH δc SHLEFT & SHWAITRQD δc ISDl δc ISDO δc SHJ07 δc ISHCYX # ARSH δc SHLEFT δ. SHWAITRQD δc ISDl δc ISDO δc ISHJ07 δc SHCYX ; "ASHL WORD,LONG WORD "ASHL HWORD 7 "ASHL DBYTE "ASHL BYTE SHWAITRQD :- SHWAITRQ ; SHAROV :- !Q0 # 'SHWAITRQD δc Ql δc QO δc SHAROV # SHWAITRQD δc Ql δc QO δc ( OVFL2 # OVFLl ) ; state_diagram [Q1.Q0] State SO: IF SHLEFT δc ARSH δc SHWAITRQD δc (OVFLl # 0VFL2) THEN SI ELSE SO ; State SI: IF SHWAITRQD THEN SI ELSE S2 ; State S2 : GOTO SO ; i ISL, IARSH, ISW, ISHCX,J63,J31,J15, J [->[ ISWD, IV2, IVl, QO.ISV]) H X X X X X X X H H Z X H H H X X X X H H H H X L L L L X H X L H H H X L L L H X H X L L H L X L L H H X H X H H H L L H L H H X H X H H H L L H L H H X H X H H H H L end SH12B3R4; SUBSTITUTE SHET _ - ^ title 'PAL16L8 PAL DESIGN SPECIFICATION SH12C5L8 PAO JAN 13, 1987 SHIFTER IN/OUT CONTROL (U9) DAVIN COMPUTER IRVINE CALIFORNIA -Translated by TOABEL-' ; SH12C5L8 device 'P16L8' ; "declarations TRUE,FALSE - 1,0; H,L - 1,0; X,Z,C - .X.,.Z.,.C; GND.VCC pin 10,20; UFD0,UFD1,UFD2,UFD3,UBS0,UBS1,UBS2,UBS3,C2SHB pin 1,2,3,4,5,6,7,8,11; IEN_KOUTA, IENB_JOUT pin 12,19; IKCLRA, IKCLRB, !LD_SHK, !EN_KOUTB, ISHJS2B, ISHJSOB pin 13,14,15,16,17,18; UFD - [UFD3 , UFD2 , UFDl , UFD0] ; UBS - [UBS3 , UBS2 , UBS1 , UBSO] ; C2 - C2SHB; KC - [KCLRA , KCLRB] ; equations SHJS0B == IUBS3 δc UBS2 δc IUBS1 δc UBSO δc C2SHB # UFD3 δc UFD2 δc UFDl δc IUFD0 δc IC2SHB "OUT J FIRST HALF "ALU FD E,(LD MASK) SECOND HALF SHJS2B "ALU FD5,8,C,D,E,F (LD J) LOAD J 2ND HALF ENB_JOUT - IUBS3 δc UBS2 & IUBS1 δc UBSO δ: C2SHB ; "ALU B BUS SOURCE AT "1ST HALF CYC EN OUTA = IUBS3 δc UBS2 δc UBS1 δ= IUBS0 δc C2SHB # UBS3 δc IUBS2 & IUBS1 δc UBSO δc C2SHB ; SUBSTITUTE SHET "ALU B BUS SOURCE "ALU B BUS 0 SOURCE ϋt> ENJKOUTB - IUBS3 δc UBS2 δc UBS1 δc IUBS0 δc C2SHB # UBS3 δc IUBS2 δc IUBS1 δc UBSO & C2SHB ; "ALU B BUS SOURCE "ALU B BUS 0 SOURCE LD_SHK - IUFD3 δc UFD2 δc UFDl δc IUFD0 δc IC2SHB # UFD3 & IUFD2 δc IUFDl δc UFDO & IC2SHB ; "LOAD K 2ND HALF AND ALU FD6,9 KCLRA - UBS3 δc IUBS2 & IUBS1 δc UBSO; "ALU B BUS 0 SOURCE KCLRB = UBS3 δc IUBS2 δc IUBS1 δc UBSO; "ALU B BUS 0 SOURCE UFD - [UFD3 , UFD2 , UFDl , UFDO] ; UBS - [UBS3 , UBS2 , UBS1 , UBSO]; C2 - C2SHB; KC - [KCLRA , KCLRB] ; test_vectors ( HJS0B.ISHJS2B, EN H H H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H L H H L L H H L H H L L H H H L H H H L H H H L H , H , A h3 H , H , A h3 end SH12C5L8 ; m mi FFH LOOKUP TABLE (FUNC: FFH, DATA LENGTH: BYTE) Page 1 ol 16 SU&STITUTE SHEET FFH LOOKUP TABLE (FUNC: FFH. DATA LENGTH: HALF-WORD) Page 3 of 16 SUBSTITUTE SHEET SUBSTITUTE SHEET FFH LOOKUP TABLE (FUNC: FFM, DATA LENGTH: BYTE) Page 5 of 16 SUBSTITUTE SHEET ADDR. OUTPUT ADDR. OUTPUT (HEX) (HEX) (HEX) (HEX) 500 8 540 6 501 0 541 0 502 0 542 0 503 0 543 0 504 2 544 2 505 0 545 0 506 0 546 0 507 0 547 0 508 2 548 2 509 0 549 0 50A 0 54A 0 50B 0 54B 0 50C 2 54C 2 50D 0 54D 0 50E 0 54 E 0 5CE 0 50F 0 54 F 0 5CF 0 510 4 550 4 5D0 4 511 0 551 0 5D1 0 512 0 552 0 5D2 0 513 0 553 0 5D3 0 514 2 554 2 554 2 515 0 555 0 555 0 516 0 556 0 556 0 517 0 557 0 557 0 518 2 558 2 5D8 2 519 0 559 0 5D9 0 51A 0 55A 0 5DA 0 51 B 0 55B 0 5DB 0 51 C 2 55C 2 5DC 2 51 D 0 55D 0 5DD 0 51 E 0 55E 0 5DE 0 51 F 0 55F 0 5DF 0 520 4 560 4 5E0 4 521 0 561 0 5E1 0 522 0 562 0 5E2 0 523 0 563 0 5E3 0 524 2 564 2 5E4 2 525 0 565 0 5E5 0 526 0 566 0 5E6 0 527 0 567 0 5E7 0 528 2 568 2 5E8 2 529 0 569 0 5E9 0 52A 0 56A 0 5EA 0 52B 0 56B 0 5EB 0 52C 2 56C 2 5EC 2 52D 0 56D 0 5ED 0 52E 0 56E 0 5EE 0 52F 0 56F 0 5EF 0 530 4 570 4 5F0 4 531 0 571 0 5F1 0 532 0 572 0 5F2 0 533 0 573 0 5F3 0 534 2 574 2 5F4 2 535 0 575 0 5F5 0 536 0 576 0 5F6 0 537 0 577 0 5F7 0 538 2 578 2 5F8 2 539 0 579 0 5F9 0 53A 0 57A 0 5FA 0 53B 0 57B 0 5FB 0 53C 2 57C 2 5FC 2 53D 0 57D 0 5FD 0 53E 0 57E 0 5FE 0 53F 0 57F 0 5FF 0 SUBSTITUTE SHET FFH LOOKUP TABLE (FUNC: FFM, DATA LENGTH: HALF-WORD) Page 7 of 16 ADDR. OUTPUT (HEX) (HEx) 680 4 681 0 682 0 683 0 684 0 685 0 686 0 687 0 688 0 689 0 68A 0 68B 0 68C 0 68D 0 68E 0 68F 0 690 4 691 0 692 0 693 0 694 0 695 0 696 0 697 0 698 0 699 0 69A 0 69B 0 69C 0 69D 0 69E 0 69F 0 6A0 4 6A1 0 6A2 0 6A3 0 6A4 0 6A5 0 6A6 0 6A7 0 6A8 0 6A9 0 6AA 0 6AB 0 6AC 0 6AD 0 6AE 0 6AF 0 6B0 4 6B1 0 6B2 0 6B3 0 6B4 0 6B5 0 6B6 0 6B7 0 6B8 0 6B9 0 6BA 0 6BB 0 6BC 0 6FC 6BD 0 6FD 6BE 0 6FE 6BF 0 6FF SUBSTITUTE SHEET SHEET no FFH LOOKUP TABLE (FUNC: FFHAFM, DATA LENGTH: BYTE) Page 9 of 16 FFH LOOKUP TABLE (FUNC: FFHAFM, DATA LENGTH: DOUBLE-BYTE) Page 10 of 16 FFH LOOKUP TABLE (FUNC: FFHAFM, DATA LENGTH: HALF-WORD) Page 11 of 16 : , : ADDR. OUTPUT (HEX) (HEX) B40 8 B41 8 B42 8 B43 8 B44 8 B45 8 B46 8 B47 8 B48 8 B49 8 B4A 8 B4B 8 B4C 8 B4D 8 B4E 8 B4F 8 B50 8 B51 8 B52 8 B53 8 B54 8 B55 8 B56 8 B57 8 B58 8 B59 8 B5A 8 B5B 8 B5C 8 B5D 8 B5E 8 B5F 8 B60 8 B61 8 B62 8 B63 8 B64 8 B65 8 B66 8 B67 8 B68 8 B69 8 B6A 8 B6B 8 B6C 8 B6D 8 B6E 8 B6F 8 B70 8 B71 8 B72 8 B73 8 B74 8 B75 8 B76 8 B77 8 B78 8 B79 8 B7A 8 B7B 8 B7C 8 B7D 8 B7E 8 B7F 8 SUBSTITUTE SHEET FFH LOOKUP TABLE (FUNC: FFMAFH, DATA LENGTH: BYTE) Page 13 of 16 SUBSTITUTE SHEET , - ADDR. OUTPUT ADDR. OUTPUT (HEX) (HEX) (HEX) (HEX) D00 8 D80 6 D01 8 D81 6 D02 8 D82 6 D03 8 D83 6 D04 2 D84 2 D05 8 D85 6 D06 8 D86 6 D07 8 D87 6 D08 2 D88 2 D09 8 D89 6 DOA 8 D8A 6 DOB 8 4B 6 D8B 6 DOC 2 D4C 2 D8C 2 DOD 8 D4D 6 D8D 6 DOE 8 D4E 6 D8E 6 DOF 8 D4F 6 D8F 6 D10 4 D50 4 D90 4 D11 4 D51 4 D91 4 D12 4 D52 4 D92 4 D13 4 D53 4 D93 4 D14 2 D54 2 D94 2 D15 8 D55 8 D95 8 D16 8 D56 8 D96 8 D17 8 D57 8 D97 8 D18 2 D58 2 D98 2 D19 8 D59 8 D99 8 D1A 8 D5A 8 D9A 8 D1 B 8 D5B 8 D9B 8 D1C 2 D5C 2 D9C 2 D1D 8 D5D 8 D9D 8 D1E 8 D5E 8 D9E 8 D1 F 8 D5F 8 D9F 8 D20 4 D60 4 DAO 4 D21 4 D61 4 DA1 4 D22 4 D62 4 DA2 4 D23 4 D63 4 DA3 4 D24 2 D64 2 DA4 2 D25 8 D65 8 DA5 8 D26 8 D66 8 DA6 8 D27 8 D67 8 DA7 8 D28 2 D68 2 DA8 2 D29 8 D69 8 DA9 8 D2A 8 D6A 8 DAA 8 D2B 8 D6B 8 DAB 8 D2C 2 D6C 2 DAC 2 D2D 8 D6D 8 DAD 8 D2E 8 D6E 8 DAE 8 D2F 8 D6F 8 DAF 8 D30 4 D70 4 DBO 4 D31 4 D71 4 DB1 4 D32 4 D72 4 DB2 4 D33 4 D73 4 DB3 4 D34 2 D74 2 DB4 2 D35 8 D75 8 DB5 8 D36 8 D76 8 DB6 8 D37 8 D77 8 DB7 8 D38 2 D78 2 DB8 2 D39 8 D79 8 DB9 8 D3A 8 D7A 8 DBA 8 D3B 8 D7B 8 DBB 8 D3C 2 D7C 2 DBC 2 D3D 8 D7D 8 DBD 8 D3E 8 D7E 8 DBE 8 D3F 8 D7F DBF 8 SUB ITUTE SffiEt FFH LOOKUP TABLE (FUNC: FFMAFH, DATA LENGTH: HALF-WORD) Page 15 of 16 ADDR. OUTPUT ADDR. OUTPUT ADDR. OUTPUT (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) E40 4 E80 4 ECO 4 E41 8 E81 8 EC1 8 E42 8 E82 8 EC2 8 E43 8 E83 8 EC3 8 E44 8 E84 8 EC4 8 E45 8 E85 8 EC5 8 E46 8 E86 8 EC6 8 E47 8 E87 8 EC7 8 E48 8 E88 8 EC8 8 E49 8 E89 8 EC9 8 E4A 8 E8A 8 ECA 8 E4B 8 E8B 8 ECB 8 E4C 8 E8C 8 ECC 8 E4D 8 E8D 8 ECD 8 E4E 8 E8E 8 ECE 8 E4F 8 E8F 8 ECF 8 E50 4 E90 4 EDO 4 E51 8 E91 8 ED1 8 E52 8 E92 8 ED2 8 E53 8 E93 8 ED3 8 E54 8 E94 8 ED4 8 E55 8 E95 8 ED5 8 E56 8 E96 8 ED6 8 E57 8 E97 8 ED7 8 E58 8 E98 8 ED8 8 E59 8 E99 8 ED9 8 E5A 8 E9A 8 EDA 8 E5B 8 E9B 8 EDB 8 E5C 8 E9C 8 EDC 8 E5D 8 E9D 8 EDD 8 E5E 8 E9E 8 EDE 8 E5F 8 E9F 8 EDF 8 E60 4 EAO 4 EEO 4 E61 8 EA1 8 EE1 8 E62 8 EA2 8 EE2 8 E63 8 EA3 8 EE3 8 E64 8 EA4 8 EE4 8 E65 8 EA5 8 EE5 8 E66 8 EA6 8 EE6 8 E67 8 EA7 8 EE7 8 E68 8 EA8 8 EE8 8 E69 8 EA9 8 EE9 8 E6A 8 EAA 8 EEA 8 E6B 8 EAB 8 8 E6C 8 EAC 8 EEC 8 E6D 8 EAD 8 EED 8 E6E 8 EAE . 8 EEE 8 E6F 8 EAF 8 EEF 8 E70 4 EBO 4 EFO 4 E71 8 EB1 8 EF1 8 E72 8 EB2 8 EF2 8 E73 8 EB3 8 EF3 8 E74 8 EB4 8 EF4 8 E75 8 EB5 3 EF5 8 E76 8 EB6 8 EF6 8 E77 8 EB7 8 EF7 8 E78 8 EB8 8 EF8 8 E79 8 EB9 8 EF9 8 E7A 8 EBA 8 EFA 8 E7B 8 EBB 8 EFB 8 E7C 8 EBC 8 EFC 8 E7D 8 EBD 8 EFD 8 E7E 8 EBE 8 EFE 8 E7F 8 EBF 8 EFF 8 Page 16 of 16 FFH LOOKUP TABLE (FUNC: FFMAFH, DATA LENGTH: WORD) ADDR. OUTPUT ADDR. OUTPUT ADDR. OUTPUT ADDR. OUTPUT (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) F80 8 FCO 8 F00 8 F40 8 F81 8 FC1 8 F01 8 F41 8 F42 8 F82 8 FC2 8 F02 8 F83 8 FC3 8 F03 8 F43 8 F84 8 FC4 8 F04 8 F44 8 F85 8 FC5 8 F05 8 F45 8 F86 8 FC6 8 F06 8 F46 8 F87 8 FC7 8 F07 8 F47 8 F88 8 FC8 8 F08 8 F48 8 F89 8 FC9 8 F09 8 F49 8 F8A 8 FCA 8 FOA 8 F4A 8 F8B 8 FCB 8 FOB 8 F4B 8 F8C 8 FCC 8 FOC 8 F4C 8 F8D 8 FCD 8 FOD 8 F4D 8 F8E 8 FCE 8 FOE 8 F4E 8 F8F 8 FCF 8 FOF 8 F4F 8 F90 8 FDO 8 F10 8 F50 8 FD1 8 F91 8 F11 8 F51 8 F92 8 FD2 8 F12 8 F52 8 FD3 8 F93 8 F13 8 F53 8 F94 8 FD4 8 F14 8 F54 8 F95 8 FD5 8 F15 8 F55 8 F96 8 FD6 8 F16 8 F56 8 F97 8 FD7 8 F17 8 F57 8 F98 8 FD8 8 F18 8 F58 8 FD9 8 F99 8 F19 8 F59 8 F9A 8 FDA 8 F1A 8 F5A 8 F9B 8 FDB 8 F1 B 8 F5B 8 F9C 8 FDC 8 F1C 8 F5C 8 8 F9D 8 FDD F1 D 8 F5D 8 F9E 8 FDE 8 F1E 8 F5E 8 FDF 8 8 F9F 8 F1 F 8 F5F FEO 8 F20 8 F60 8 FAO 8 FE1 8 8 FA1 8 F21 8 F61 FE2 8 8 FA2 8 F22 8 F62 FE3 8 F23 8 F63 8 FA3 8 FE4 8 F24 8 F64 8 FA4 8 FE5 8 F25 8 F65 8 FA5 8 FE6 8 F26 8 F66 8 FA6 8 FE7 8 F27 8 F67 8 FA7 8 FE8 8 F28 8 F68 8 FA8 8 FE9 8 F29 8 F69 8 FA9 8 FEA 8 F2A 8 F6A 8 FAA 8 FEB 8 F2B 8 F6B 8 FAB 8 FEC 8 8 FAC 8 F2C 8 F6C FED 8 F2D 8 F6D 8 FAD 8 FEE 8 8 FAE 8 F2E 8 F6E FEF 8 F2F 8 F6F 8 FAF 8 FFO 8 F30 8 F70 8 FBO 8 FF1 8 F31 8 F71 8 FB1 8 FF2 8 F72 8 FB2 8 F32 8 FF3 8 F33 8 F73 8 FB3 8 FF4 8 F34 8 F74 8 FB4 8 FF5 8 F35 8 F75 8 FB5 3 F36 8 F76 8 FB6 8 FF6 8 F77 8 FB7 8 FF7 8 8 FB8 8 FF8 F78 8 8 FB9 8 FF9 F79 8 8 FBA 8 FFA 8 F7A F7B 8 FBB 8 FFB 8 F7C 8 FBC 8 FFC 8 F7D 8 FBD 8 FFD 8 8 FBE 8 FFE 8 F7E F7F 8 FBF 8 FFF 8

Claims: 34 -118- WHAT IS CIAIMED IS: 1. A parallel byte string processor that finds t location of matching bytes in first and second data words each data word having a predetermined number of data bytes said parallel byte processor characterized by: a first circuit (100, 102, 109, 115, 122) th performs an exclusive-OR operation on a byte-by-by basis of said two data words and provides an output b corresponding to each byte of said first data wo having first and second logic levels such that output bit has said first logic level when t corresponding byte in said first data word matches t corresponding byte in said second data word and havi said second logic level when the corresponding byte said first data word does not match the correspondi byte in said second data word; and a second circuit (500, 522, 532, 536} th receives said output bits from said first circuit (10 102, 109, 115, 122), said second circuit (500, 52 532, 536) providing a digital output value th identifies an output bit from said first circuit (10 102, 109, 115, 122) that has a predetermin characteristic, thereby identifying the position of particular byte in said first data word that has sa selected predetermined characteristic. 2. The parallel byte processor as defined in Cla 1, wherein said predetermined characteristic is t location of the most significant bit of said output bi having said first logic level, thus identifying the mo significant byte of said first data word that matches t corresponding byte of said second data word. 3. The parallel byte processor as defined in cla 1, wherein said predetermined characteristic is t location of the most significant bit of said output bi having said second logic level, thus identifying the mo significant byte of said first data word that does not match the corresponding byte of said second data word. 4. The parallel byte processor as defined in Claim 1, wherein said predetermined characteristic is the location of the most significant bit of said output bits having said first logic level that is less significant than a bit of said output bits having said second logic level, thus identifying the most significant byte of said first data word that does not match the corresponding byte of said second data word that is less significant that a byte of said first data word that matches the corresponding byte of said second data word. 5. The parallel byte processor as defined in Claim 1, wherein said predetermined characteristic is the location of the most significant bit of said output bits having said second logic level that is less significant than a bit of said output bits having said first logic level, thus identifying the most significant byte of said first data word that matches the corresponding byte of said second data word that is less significant that a byte of said first data word that does not match the corresponding byte of said second data word. 6. The parallel byte processor as defined in Claim 1, wherein said second circuit is characterized by a programmable read only memory (522). 7. The parallel byte processor as defined in Claim 1, wherein said bit having said characteristic is the first of at least two adjacent bits having said characteristic. 8. The parallel byte processor as defined in Claim 1, wherein said second data word is characterized by a plurality of identical bytes, and wherein said parallel byte processor further includes a replication circuit (550) , said replication circuit (550) receiving a single byte input and generating said predetermined number of bytes as outputs, each of said predetermined number of bytes being identical to said input byte.

Inventors: MCLAGAN ANGUS, MEHTVIN DAVID, UN CHONG SAM, MCLAGAN, ANGUS, MEHTVIN, DAVID, UN, CHONG, SAM
Applicants: DAVIN COMPUTER CORP, DAVIN COMPUTER CORPORATION
Application year: 1989
Main classification: G06F7
IPC codes: G06F7, G06F9