DRIVER CIRCUIT

Abstract: A driver circuit which drives a flat panel display. A constant-voltage element (16) generates a gate bias of an MOS transistor (11) which electrically charges the output terminal (23) to a high level, and a current that flows into the constant-voltage element (16) is controlled by a current control circuit (25). The charging current electrically charges the output terminal (23) via a diode (15). To turn the charging MOS transistor (11) off, an MOS transistor (13) is turned on to discharge the node of gate of the MOS transistor (11). When the output is to be switched, a drive signal generating circuit (30) produces drive signals (S1, S2) that have a period for turning off both the charging MOS transistor (11) and a discharging MOS transistor (12) that discharges the output terminal (23) to a low level.

Description: Technical Field The present invention relates to a driver circuit for converting a CMOS level signal to a high-voltage level and, more particularly, to a driver circuit for driving a flat panel display unit. Background Art A flat panel display unit such as a plasma display is normally driven by a high voltage of about 100 V to 300 V. When such a flat panel display unit is controlled by a CMOS level signal having a logical amplitude of about 5 V, the unit cannot be directly driven by this logic signal. Therefore, a driver circuit for converting the CMOS level signal into a high-voltage level is required. Fig. 7 is a circuit diagram taken from "High Voltage IC for Display Driver, Nikkei Electronics, no. 418, April 6 (1987), p. 115 and showing the arrangement of a driver circuit used for the above purpose. This driver circuit possesses a function for determining the level of an output signal Out on the basis of an input signal In and a control signal Cont, as well as having a function for setting the output state at a high-impedance state. Referring to Fig. 7, reference numerals 51 to 54 denote double diffusion n-channel MOS transistors each having a structure of a high withstand voltage; 55, a CMOS AND gate consisting of enhancement p- and n-channel MOS transistors; 56, an inverter; 57, a current setting resistor; 58, a pnp multicollector transistor; 59, a Zener diode for a bias voltage generating; 60, an output terminal; and 61, a load capacitor corresponding to one segment of the flat panel display unit and connected to the output terminal 60. Reference symbol V DD denotes a power source voltage of, e.g., 5 V of a logical system; V CC , a power source voltage of, e.g., 300 V for a high-voltage system; and GND, a ground voltage of 0 V for the logical and high-voltage systems. The resistor 57 and the transistor 54 constitute a reference voltage generator 62 for generating a predetermined reference voltage Vref from the power source voltage V DD of the logical system. The reference voltage Vref generated by the reference voltage generator 62 is supplied to the AND gate 55 as a power source voltage. The AND gate 55 also receives the input signal In and the control signal Cont. An output from the AND gate 55 is supplied to the gate of the transistor 53. When both the input signal In and the control signal Cont are set at "1" level, an output signal from the AND gate 55 is also set at "1" level, i.e., at the reference voltage Vref. At this time, a drain current determined by the resistance of the resistor 57 and having the same value as that of the transistor 54 flows in the transistor 53. As a result, the multicollector transistor 58 is turned on, and a predetermined Zener voltage appears at the cathode of the Zener diode 59 as a consequence of a current flowing out from one of the collectors of the multicollector transistor 58. If the value of the Zener voltage of the Zener diode 59 is set to the threshold voltage of the transistor 51 or higher, the transistor 51 is turned on. Thus, when both the input signal In and the control signal Cont are set at "1" level, the output signal Out is set at "1" level, i.e., the V CC level, by means of the ON transistor 51. However, when both the input signal In and the control signal Cont are set at "0" level, an output signal from the AND gate 55 is set at "0" level, and the transistor 53 is turned off. In this case, an output signal from the inverter 56 is set at "1" level, and then the transistor 52 is turned on. As a result, the output terminal 60 is discharged through the Zener diode 59 and the ON transistor 52, and the output signal out is set at "0" level, i.e., the GND level. When the input signal In is set at "1" level and the control signal Cont is set at "0" level, the transistors 51 and 52 are both turned off, and the output signal Out is set in a high-impedance state. In the conventional circuit described above, the reference voltage Vref is always generated by the reference voltage generator 62, and a constant current flows there through. For this reason, however, when the output signal Out is to be set to "1" level, current continuoues flowing unnecessarily through the generator 62 after the level of the output signal Out goes to the V CC level, resulting in energy waste. Since, in the conventional circuit, each transistor constituting the AND gate 55 is operated by means of the voltage Vref which is lower than the power source voltage V DD of 5 V for the logical system, the control range of the threshold voltage is very narrow. Because of this, it is very difficult to design an optimum circuit arrangement. In addition, when, in the case of the conventional circuit, the output signal Out is switched from "1" level to "0" level, the transistors 51 and 52 are simultaneously turned on for a given time interval due to a delay in the cut-off operation of the transistor 51. During this time interval, a short-circuiting current flows from the power source voltage Vcc of the high-voltage system to the ground voltage GND. Since the level of the power source voltage Vcc of the high-voltage system is very high, i.e., 300 V, a considerable amount of power is consumed even when the time interval during which the short-circuiting current flows is very short. In the worst case, this short-circuiting current may cause the transistors 51 and 52 to break down. Moreover, the conventional circuit has another disadvantage in that the switching of the output signal Out from "1" level to the high-impedance state takes place at a relatively slow speed. More specifically, when the multicollector transistor 58 is kept on, and the output signal Out is set at "1" level, the predetermined Zener voltage is generated at the cathode of the Zener diode 59. Even if the multicollector transistor 58 is turned off, the cathode potential does not immediately drop, since there is no discharge path to the ground voltage at the cathode of the Zener diode 59. Thus, the timing for switching off the transistor 51 is drawn out, in turn the increasing time required to switch the output signal Out to the high-impedance state. As described above, the conventional driver circuit has a number of disadvantages: current consumption is high, the control range of the threshold voltage of a transistor is very narrow, resulting in difficulties with regard in to circuit design, a short-circuiting current flows between the power sources, and can easily cause transistor breakdown due to a consequent delay in a transistor switching operation, with the result that the time required for switching the output signal from "1" level to the high-impedance state is increased. The present invention has been developed in consideration of the above, and has as its object to provide a driver circuit the design of which can be optimized, the operating speed of which is increased, and its current consumption reduced. Disclosure of Invention A driver circuit according to the present invention comprises a first MOS transistor having a source and a drain, one of which is connected to a first power source voltage, a diode connected between the other of the source and drain of the first MOS transistor and an output terminal, a constant voltage element inserted between a gate of the first MOS transistor and the other of the source and drain of the first MOS transistor, a third MOS transistor, a source and a drain of which are respectively connected to the gate of the first MOS transistor and the ground voltage and a gate of which receives a second drive signal, a bipolar transistor, an emitter circuit of which is connected to the first power source voltage and a collector circuit of which is connected to the gate of the first MOS transistor, current control means for controlling a value of a current supplied to a base circuit of the bipolar transistor in accordance with a plurality of third drive signals, and drive signal generating means for generating a first drive signal, the second drive signal, and the plurality of third drive signals on the basis of an input signal and a control signal, a second MOS transistor, a source and a drain of which are respectively connected to the output terminal and a ground voltage and a gate of which receives a first drive signal, and a gate of which receives the first drive signal, which is only active, when the second drive signal for the third MOS transistor is active, and whose leading edge is delayed with regard to the second drive signal. With the above arrangement, when a signal of "1" level is output from the output terminal, a current having a large value is supplied from the current control means to the base circuit of the bipolar transistor. Therefore, a current flows in the constant voltage element connected to the collector of the bipolar transistor, and a voltage drop across the constant voltage element occurs. This voltage biases the gate of the first MOS transistor to turn on the first MOS transistor. Once the first MOS transistor is turned on, the voltage drop across the constant voltage element can be maintained even if a large current is not supplied to the base circuit of the bipolar transistor. Therefore, after the first MOS transistor is turned on, a current having a small value is supplied from the current control means to the base circuit of the bipolar transistor, thereby reducing current consumption. When a signal of "0" level is output from the output terminal, the second MOS transistor is set in an ON state in response to the first drive signal. When the first MOS transistor is turned off, the third MOS transistor is rendered conductive in response to the second drive signal. A gate potential of the first MOS transistor is discharged through the third MOS transistor. Therefore, the first MOS transistor is immediately turned off. In addition, the drive signal generating means generates the first and second drive signals such that the third MOS transistor is turned off a predetermined period of time before the first MOS transistor is turned on. At the same time, the drive signal generating means generates the first and second drive signals such that the third MOS transistor is turned on a predetermined period of time after the first MOS transistor is turned off. Therefore, both the first and second MOS transistors are not simultaneously turned on when their operating conditions are switched. Therefore, generation of a short-circuiting current between the power sources can be prevented. Brief Description of the Drawings Fig. 1 is a circuit diagram showing an arrangement of a driver circuit according to an embodiment of the present invention, Fig. 2 is a timing chart for explaining an operation of the circuit of the embodiment shown in Fig. 1, Fig. 3 is a circuit diagram showing a detailed arrangement of a drive signal generator used in the circuit of the embodiment shown in Fig. 1, Figs. 4 to 6 are circuit diagrams showing arrangements of other embodiments of the present invention, and Fig. 7 is a circuit diagram showing a conventional driver circuit. Best Mode of Carrying out the Invention The present invention will be described in detail with reference to embodiments in conjunction with the accompanying drawings. Fig. 1 is a circuit diagram showing an arrangement of a driver circuit according to the first embodiment of the present invention. Referring to Fig. 1, reference numerals 11 to 14 denote double diffusion n-channel MOS transistors (to be referred to as DMOSs hereinafter) each having a structure of a high withstand voltage; 15, an output diode; 16, a gate bias Zener diode whose Zener voltage V Z is set to be the threshold voltage of the DMOS 11 or higher; 17, a level shift pnp multicollector transistor having a first collector C1 and a second collector C2; 18, a base current discharge resistor for the multicollector transistor 17; 19 and 20, current value setting resistors; 21 and 22, current switching enhancement n-channel MOS transistors; 23, an output terminal; 24, a load capacitor connected to the output terminal 23; and 30, a drive signal generator for receiving an input signal In and a control signal Cont and for generating drive signals S1 and S2 for driving the DMOSs 12 and 13 and drive signals S3-1 and S3-2 for driving the MOS transistors 21 and 22. The drain of the DMOS 11 is connected to a power source voltage V CC of, e.g., 300 V for a high-voltage system. The source of the DMOS 11 is connected to the output terminal 23 through the anode and cathode of the diode 15. The gate of the DMOS 11 is connected to the cathode of the Zener diode 16. The anode of the Zener diode 16 is connected to the source of the DMOS 11. The drain of the DMOS 12 is connected to the output terminal 23. The source of the DMOS 12 is connected to a ground voltage GND. The drain of the DMOS 13 is connected to the gate of the DMOS 11. The source of the DMOS 13 is connected to the ground voltage GND. The emitter of the multicollector transistor 17 is connected to the power source voltage V CC . The first collector C1 of the multicollector transistor 17 is connected to its base, and the second collector C2 is connected to the gate of the DMOS 11. The resistor 18 is connected between the base of the multicollector transistor 17 and the power source voltage V CC . The first collector C1 of the multicollector transistor 17 is also connected to the drain of the DMOS 14. The source of the DMOS 14 is connected to one terminal of each of the two resistors 19 and 20 having different resistances. The other terminal of each of the resistors 19 and 20 is connected to a corresponding one of the drains of the transistors 21 and 22. The sources of the transistors 21 and 22 are connected to the ground voltage GND. The resistances of the resistors 19 and 20 are set to satisfy condition R1 < R2 when the resistance of the resistor 19 is represented by R1 and the resistance of the resistor 20 is represented by R2. The DMOS 14, the resistors 19 and 20, and the transistors 21 and 22 constitute a current control circuit 25 for controlling a value of a current supplied to the base of the multicollector transistor 17. The drive signal S1 is supplied to the gate of the DMOS 12; the drive signal S2, to the gate of the DMOS 13; the power source voltage V DD of, e.g., 5 V for the logical system, to the gate of the DMOS 14; the drive signal S3-1, to the gate of the transistor 21; and the drive signal S3-2, to the gate of the transistor 22. The drive signal generator 30 for generating the drive signals S1, S2, S3-1, and S3-2 receives the power source voltage V DD of 5 V for the logical system and the ground voltage GND of 0 V as power source voltages. An operation of the circuit having the above arrangement will be described with reference to a timing chart shown in Fig. 2. In the circuit of this embodiment, basically, when the control signal Cont is set at "0" level and the input signal In is set at "0" level, the output signal Out is set at "1" level (V CC level). When the control signal Cont is set at "0" level and the input signal In is set at "1" level, the output signal Out is set at "0" level (GND level). In addition, when the control signal Cont is set at "1" level, the output signal Out is set in the high-impedance state. Referring to Fig. 2, prior to time t1 at which the input signal In is changed from "0" level to "1" level, the drive signal S3-1 is kept at "1" level within a predetermined period of time to turn on the transistor 21. The drive signal S3-2 goes to "1" level in synchronism with the leading edge of the drive signal S3-1. At the same time, the transistor 22 is turned on. A drain current I D defined by the following equation flows in the DMOS 14 which receives the voltage V DD of 5 V when the threshold voltage of the DMOS 14 is given as Vth: When the drain current I D flows through the DMOS 14, the multicollector transistor 17 is turned on. At this time, a predetermined current flows into the Zener diode 16 through the transistor 17. The predetermined Zener voltage V Z is generated by the Zener diode 16. Since the Zener voltage V Z is set to be higher than the threshold voltage of the DMOS 11, the DMOS 11 is turned on. Therefore, the load capacitor 24 is charged with the voltage V CC through the ON DMOS 11. The output signal Out is set at "1" level. Thereafter, the drive signal S3-1 goes to "0" level to turn off the transistor 21. However, as the drive signal S3-2 is kept at "1" level, the transistor 22 is kept on. At this time, a drain current I D given by the following equation is supplied to the DMOS 14: I D = (V DD - Vth)/R2 = I2 (2) In this case, since the resistance R2 of the resistor 20 is larger than the resistance R1 of the resistor 19, the drain current I D of the DMOS 14 has a smaller amplitude. However, the gate potential of the DMOS 11 has already been set to be V Z . This potential is held by a parasitic capacitance (not shown) present at this node. Therefore, a current for compensating for a voltage drop by a current leaking from the parasitic capacitance is supplied to the DMOS 11 by the transistor 22, so that the DMOS 11 is kept on. In this manner, in the circuit of this embodiment, a sufficiently large current is supplied to the DMOS 14 only for a predetermined initial period in which the output signal Out is set at "1" level. Thereafter, a very small current is supplied to the DMOS 14. For this reason, unlike the conventional circuit, a constant current need not always be supplied to generate a reference voltage, thereby reducing current consumption. The input signal In is changed from "0" level to "1" level at time t1. When the input signal In goes to "1" level, the drive signal S3-2 which has been set at "1" goes to "0" level. The transistor 22 is turned off, and the previous current does not flow in the DMOS 14. The drive signal S2 goes to "1" level after the input signal In goes to "1" level. The DMOS 13 is turned on. The node potential of the gate of the DMOS 11 is immediately discharged to the ground voltage through the DMOS 13. For this reason, a signal S4 at the node of the gate of the DMOS 13 goes to "0" level, as shown in Fig. 2, and therefore the DMOS 11 is turned off. The drive signal S1 is kept at "0" level immediately after the input signal In goes to "1" level. The drive signal S1 goes to "1" level at time t2 after a lapse of a predetermined period of time from time t1. Both the DMOS 11 and the DMOS 12 are kept off during a time interval from time t1 to time t2. During this time interval, the output signal Out is set in a high-impedance state, as indicated by a hatched portion in Fig. 2. At time t2, the drive signal S1 goes to "1" level. When the signal S1 is set at "1" level, the DMOS 12 is turned on, and the output signal Out is set at the ground voltage GND, i.e., "0" level. At time t3, the input signal In goes from "1" level to "0" level. When the input signal In goes to "0" level, the drive signal S1 rapidly goes to "0" level, and the DMOS 12 is turned off. At this time, the drive signal S2 is kept at "1" level, so that the DMOS 13 is kept on, and the DMOS 11 is kept off. At time t4 after a lapse of a predetermined period of time from time t3, the drive signal S2 goes to "0" level. During a time interval from time t3 to time t4, both the DMOS 11 and the DMOS 12 are kept off. During this time interval, the output signal Out is kept in a high-impedance state, as indicated by a hatched portion in Fig. 2. At time t4, both the drive signals S3-1 and S3-2 go to "1" level, and both the transistors 21 and 22 are simultaneously turned on. The drain current I D represented by equation 1 above is supplied to the DMOS 14. As a result, the output signal Out is set at "1" level. Thereafter, at time t5, only the drive signal S3-1 goes to "0" level. At this time, the drive signal S3-2 is kept at "1" level. Therefore, after time t5, the drain current I D given by equation 2 above is supplied to the DMOS 14 through the ON transistor 22 to keep the DMOS 11 ON. The output signal Out is kept at "1" level. At time t6, the control signal Cont goes from "0" level to "1" level. When the signal Cont goes to "1" level, the drive signal S3-2 goes to "0" level and at the same time the drive signal S2 goes to "1" level. When the drive signal S3-2 goes to "0" level, the transistor 22 which has been kept ON is turned off, and the previous current is no longer supplied to the DMOS 14. That is, the drain current I D of the DMOS 14 becomes zero, as shown in Fig. 2, and no current is supplied to the Zener diode 16. When the signal S2 goes to "1" level, the DMOS 13 is turned on. The node potential of the gate of the DMOS 11 is rapidly discharged to the ground voltage through the DMOS 13. The signal S4 goes to "0" level, as shown in Fig. 2, thereby turning off the DMOS 11. On the other hand, since the drive signal S1 is kept at "0" level, the DMOS 12 is kept OFF. Therefore, when the control signal Cont is changed to "1" level, the output signal Out is set in a high-impedance state, as indicated by a hatched portion in Fig. 2. In this manner, when the output signal Out is changed from "1" level to the high-impedance state, the DMOS 13 is turned on. The cathode potential of the Zener diode 16 is rapidly discharged to the GND through the DMOS 13. As a result, the DMOS 11 is immediately turned off to advance the timing at which the output signal Out is changed to the high-impedance state. This state continues until time t7 at which the next control signal Cont is changed to "0" level. At time t7, when the control signal Cont is changed from "1" level to "0" level, both the drive signals S3-1 and S3-2 go to "1" level and the output signal Out is set at "1" level in the same manner as at time t4. Thereafter, at time t8, only the drive signal S3-1 goes to "0" level to turn off the transistor 21. At this time, the output signal Out is kept at "1" level. The drive signal generator 30 for receiving the input signal In and the control signal Cont and generating the drive signals S1, S2, S3-1, and S3-2 at timings shown in Fig. 2 can be easily arranged using known logical gate circuits and signal delay circuits. A detailed arrangement of this circuit is shown in Fig. 3. Referring to Fig. 3, the input signal In is input to an OR gate 32 through a delay circuit 31 for delaying the input by a predetermined period of time. The OR gate 32 directly receives the input signal In and the control signal Cont. The OR gate 32 outputs the drive signal S2. The input signal In is supplied to an AND gate 34 through an inverter 33. The AND gate 34 receives the input signal In and an output signal from the delay circuit 31. The AND gate 34 outputs the drive signal S1. The drive signal S2 is supplied to an inverter 35. The inverter 35 outputs the drive signal S3-2. The drive signal S2 is supplied to an AND gate 37 through a delay circuit 36 for delaying an input by a predetermined period of time. The AND gate 37 also receives the drive signal S3-2. The AND gate 37 outputs the drive signal S3-1. The logical gate circuits and signal delay circuits in the drive signal generator 30 having the above arrangement receive V DD and GND as power source voltages. Fig. 4 is a circuit diagram showing an arrangement of a driver circuit according to the second embodiment of the present invention. The circuit of this embodiment uses a pnp transistor 26 having a single collector in place of the multicollector transistor 17 in the circuit of the embodiment shown in Fig. 1. In this case, the collector of the transistor 26 is connected to the gate of the DMOS 11, and the base is connected to the drain of the DMOS 14 of the current control circuit 25. The resistor 18 is connected between the base and the voltage V CC. Fig. 5 is a circuit diagram showing an arrangement of a driver circuit according to the third embodiment of the present invention. In the circuit of this embodiment, a current control circuit 25 includes i (i is an integer of 2 or more) resistors 27₁, 27₂, 27₃,... 27 i having different resistances. These resistors 27₁ to 27 i are controlled by enhancement transistors 28₁, 28₂, 28₃,... 28 i in accordance with drive signals S2-11, S2-12, S2-13,... S3-1i generated by a drive signal generator 40. Drain currents having different values, the number of which is larger than two, are supplied to a DMOS 14. In this case, therefore, the value of a current supplied to a Zener diode 16 can be finely controlled in accordance with a change in state of a load connected to an output terminal 23. Fig. 6 is a circuit diagram showing an arrangement of a driver circuit according to the fourth embodiment of the present invention. The circuit of this embodiment uses a pnp transistor 26 having a single collector in place of the multicollector transistor 17 arranged in the circuit of the embodiment shown in Fig. 5. The drive signal generators 40 used in the circuits of the embodiments of Figs. 5 and 6 to generate the drive signals S1 and S2 and the drive signals S3-1 to S3-i can be easily arranged by using known logical gate circuits and signal delay circuits. Industrial Applicability The driver circuit according to the present invention can be effectively utilized in a driver circuit for driving a flat panel display with a high voltage.

Claims: A driver circuit comprising a first MOS transistor (11) having a source and a drain, one of which is connected to a first power source voltage (V CC ), a diode (15) connected between the other of said source and drain of said first MOS transistor (11) and an output terminal (23), a constant voltage element (16) inserted between a gate of said first MOS transistor (11) and the other of said source and drain of said first MOS transistor (11), a third MOS transistor (13), a source and a drain of which are respectively connected to said gate of said first MOS transistor (11) and the ground voltage (GND) and a gate of which receives a second drive signal (S2), a bipolar transistor (17), an emitter of which is connected to the first power source voltage (V CC ) and a collector (C2) of which is connected to said gate of said first MOS transistor (11), a current control means (25) for controlling a value of a current supplied to the base of said bipolar transistor (17) in accordance with a plurality of third drive signals (S3-1, S3-2; S3-11-S3-1i), and drive signal generating means (30) for generating a first drive signal (S1), the second drive signal (S2), and the plurality of third drive signals (S3-1, S3-2; S3-11-S3-1i) on the basis of an input signal (in) and a control signal (cont), characterized by comprising a second MOS transistor (12), a source and a drain of which are respectively connected to said output terminal (23) and said ground voltage (GND), and a gate of which receives said first drive signal (S1), which is only active, when said second drive signal (S2) for said third MOS transistor (13) is active, and whose leading edge is delayed with regard to said second drive signal (S2). A driver circuit according to claim 1, wherein said first, second, and third MOS transistors (11, 12, 13) are double diffusion n-channel MOS transistors. A driver circuit according to claim 1, wherein said constant voltage element (16) is a Zener diode, an anode of which is connected to the other of said source and drain of said first MOS transistor (11) and a cathode of which is connected to said gate of said first MOS transistor (11). A driver circuit according to claim 1, wherein said current control means (25) comprises a fourth MOS transistor (14) having a source and a drain, one of which is connected to said base of said bipolar transistor (17), and a gate which receives a second power source voltage (V DD ), a plurality of first resistors (19, 20; 27₁-27 i ) each having one terminal connected to the other of said source and drain of said fourth MOS transistor (14), said plurality of first resistors (19, 20; 27₁-27 i ) having different resistances, and a plurality of fifth MOS transistors (21, 22; 28₁-28 i ) each having a source and a drain, one of which is connected to the other terminal of a corresponding one of said plurality of first resistors (19, 20; 27₁-27 i ), the other of which is connected to the ground voltage (GND), and each having a gate which receives a corresponding one of said plurality of third drive signals (S3-1, S3-2; S3-11- S3-1i). A driver circuit according to claim 4, wherein said current control means (25) includes two of said first resistors (19, 20) to supply different three-value currents including a current value of zero to said base of said bipolar transistor (17). A driver circuit according to claim 4, wherein said fourth MOS transistor (14) is a double diffusion n-channel MOS transistor, and said plurality of fifth MOS transistors (21, 22; 2b₁-28₂) are enhancement n-channel MOS transistors. A driver circuit according to claim 1, wherein said drive signal generating means (30) is arranged to generate the second drive signal (S2) so as to turn on said third MOS transistor (13) in synchronism with a timing at which said second MOS transistor (12) is turned off in response to the first drive signal (S1). A driver circuit according to claim 7, wherein said drive signal generating means (30) generates the first and second drive signals (S1, S2) to turn on said third MOS transistor (13) a predetermined period of time before turn-on of said second MOS transistor (12), and generates the first and second drive signals (S1, S2) so as to turn off said third MOS transistor (13) a predetermined period of time after turn-off of said second MOS transistor (12). A driver circuit according to claim 4, wherein said bipolar transistor (17) is a pnp multicollector transistor having first and second collectors (C1, C2), the base of said pnp multicollector transistor being connected to said first collector (C1), said second collector (C2) being connected to said gate of said first MOS transistor (11), a second resistor (18) being connected between said base of said multicollector transistor (17) and the first power source voltage (V CC ). A driver circuit according to claim 4, wherein said bipolar transistor (26) is a pnp transistor having a single collector, said single collector being connected to said gate of said first MOS transistor (11), a second resistor (18) being connected to said base of said pnp transistor (26) and the first power source voltage (V CC ).

Inventors: TAKAHASHI NOBUYUKI, TAKAHASHI, NOBUYUKI
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1989
Main classification: H03K5
IPC codes: H03K5, G06F3, H03K19, H03K17