Diamond transistor and method of manufacture thereof

Abstract: The invention provides a process for manufacturing an electronic device on a semiconducting substrate (10) which is transparent to light of a particular wavelength. The process includes the steps of treating the substrate to form at least one region (S,D) having a different electrical property to the substrate, and defining a conducting contact (18) for the region by selective photolithographic masking and chemical etching. A layer of photoresist material (16) deposited on one side of the substrate is subjected to light transmitted through the substrate from a light source on the other side of the substrate. The process can be used to produce a field effect transistor on a diamond substrate.

Description: BACKGROUND OF THE INVENTION This invention relates to a field effect transistor formed from diamond material. Field effect transistors (FETS) have been manufactured which comprise a generally conventional FET structure formed on a substrate of diamond, instead of a silicon substrate. The physical properties of diamond result in it having superior characteristics to silicon (Si), gallium arsenide (GaAs) or other known semi-conductive materials in this application. In particular, diamond FETs can be expected to have a lower resistance, and a higher gain and maximum frequency than transistors employing conventional materials. JP-A-60246627, which provides the basis for the prior art portion of claim 1, discloses a MISFET structure in which a diamond substrate is ion-implanted to have source and drain regions and a gate is positioned on a diamond film insulating layer between those regions. According to the present invention there is provided a field effect transistor comprising a diamond substrate provided with a gate electrode and spaced apart source and drain regions, respective ohmic or quasi-ohmic source and drain contacts being applied to the source and drain regions with the gate electrode being located between and separated from the source and drain contacts characterized in that said substrate is p type, said source and drain regions are formed by the deposition of p+ semiconductor material on the surface of the substrate and said gate electrode is on or adjacent to said substrate surface. The gate electrode may be separated from the surface of the substrate by an insulating layer of a wide-bandgap material, to provide a MISFET configuration. Alternatively, the gate electrode may be applied directly to the surface of the substrate to provide a MESFET configuration. The source and drain contacts applied to the source and drain regions may be quasi-ohmic contacts formed by the deposition of p⁺ doped amorphous silicon or germanium on the substrate above the source and drain regions, with a metal layer being deposited on the p⁺ doped silicon or germanium. The metal layer may comprise aluminium, molybdenum, molybdenum/tantalum alloy, chrome, titanium, nichrome, titanium/tungsten alloy, palladium, platinum, or an aluminium/silicon alloy. Further according to another aspect of the present invention there is provided a process for manufacturing a field-effect transistor as defined in claim 6. In a first version of the process, a layer of a second metal, different from the first metal, is deposited over the layer of insulating material and then selectively removed from the source and drain regions, so that a MISFET structure is obtained having source and drain contacts of the first metal and a gate contact of the second metal. In a second version of the process, a portion of the layer of insulating material is removed above the gate region to expose the substrate, a layer of a second metal having a low work function is deposited over the source, gate and drain regions, and the layer of the second metal is then selectively removed from the source and drain regions, so that a MESFET structure is obtained having source and drain contacts of the first metal and a gate contact of the second metal. The second metal may be, in the latter case, aluminium, gold or titanium, for example. In both versions of the process, the layer of p⁺ doped amorphous silicon or germanium and the layers of the first and second metals are preferably deposited by chemical vapour deposition (CVD) or physical vapour deposition (PVD). The selective removal of portions of the various layers is preferably done by a photolithographic masking and etching process. The wide-bandgap insulating material preferably comprises an oxide, nitride, oxynitride or carbide, and is preferably deposited by a CVD or PVD process. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1a to 1f illustrate the manufacture of a MISFET by a first version of the process of the invention; and Figures 2a to 2d illustrate the manufacture of a MESFET transistor according to a second version of the process. DESCRIPTION OF EMBODIMENTS OF THE INVENTION Referring to Figure 1a, a p-type diamond substrate 10 is shown schematically. A layer 12 of p⁺ doped amorphous silicon or germanium is applied to the upper surface of the substrate 10 by means of a chemical vapour deposition (CVD) process, or by means of a physical vapour deposition (PVD) process. In Figure 1b, a layer 14 of a first metal is deposited on top of the p⁺ layer 12, again by means of a CVD or PVD process. Examples of metals which are suitable are aluminium, molybdenum, molybdenum/tantalum alloy, chrome, titanium, nichrome, titanium/tungsten alloy, palladium, platinum, or an aluminium/silicon alloy. In Figure 1c, a portion of the layers 14 and 12 has been removed selectively by a photolithographic masking and a chemical etching process, exposing the substrate 10 in a region which defines the gate of the transistor. Regions on either side of the gate (G) area define the source (S) and drain (D) of the transistor. Turning to Figure 1d, a layer 16 of a wide-bandgap insulating material is applied over the structure of Figure 1c, again by means of a CVD or PVD process, covering the source, gate and drain regions. The insulating material is an oxide, nitride, oxynitride, or a carbide. The next step in the process is illustrated by Figure 1e, which shows a further metallic layer 18, of a second metal which is different from the metal of the layer 14, deposited onto the layer 16 of insulating material. Again, a CVD or PVD process is used. The second metal, although different from the first metal of the layer 14, is selected from the group of metals listed above. Finally, as shown in Figure 1f, portions of the layers 18 and 16 are selectively removed by photolithographic masking and chemical etching, to expose the metallic layer 14 above the source and drain regions of the transistor. It can thus be seen that the transistor is provided with metallic contacts of the first metal for the source and drain regions, and a contact of the second metal for the gate region. The transistor has a MISFET structure, with the insulating layer 16 lying between the metal gate contact and the p-type semiconductor substrate of the transistor. Although the illustrated transistor has no p-n junctions, a transistor switching action is, nevertheless, obtained. If a positive voltage is applied to the gate contact, a corresponding negative charge is induced in the insulating layer adjacent the gate contact. This is balanced by a positive charge in the insulating layer adjacent the surface of the substrate, which again induces a negative charge in the substrate adjacent its surface. This effectively forms an n-type channel in the substrate between the source and drain regions. Referring now to Figures 2a to 2d, a process for manufacturing a second version of the transistor will be described. The second version of the process is similar to that described above, up to the point were the layer 16 of insulating material is applied to the structure illustrated in Figure 1d. The structure of Figure 2a therefore corresponds to that of Figure 1d. Referring now to Figure 2b, the insulating layer 16 is selectively etched right down to the surface of the substrate 10, to define a gate (G) region. Then, as shown in Figure 2c, a layer 20 of a second metal, which differs from the metal of the layer 14, is deposited over the structure by a CVD or PVD process. The metallic layer 20 is thus in contact with the surface of the substrate 10 in the gate region. Finally, as shown in Figure 2d, the layers 20 and 16 are selectively removed by photolithographic masking and chemical etching, to expose the metal layer 14 above the source and drain regions of the transistor. A transistor is thus obtained which has source and drain contacts of the first metal and a gate contact of the second metal. In this case, however, the transistor has a MESFET configuration, with the metallic gate contact being directly in contact with the substrate 10 in the gate region of the transistor. The layer 16 of insulating material serves to isolate the gate contact from the source and drain contacts.

Claims: A field effect transistor comprising a diamond substrate (10) provided with a gate electrode (18,20) and spaced apart source and drain regions (S,D), respective ohmic or quasi-ohmic source and drain contacts (14) being applied to the source and drain regions (S,D) with the gate electrode (18,20) being located between and separated from the source and drain contacts characterized in that said substrate is p type, said source and drain regions (S,D) are formed by the deposition of p+ semiconductor material (12) on the surface of the substrate and said gate electrode (18,20) is on or adjacent to said substrate surface. A field effect transistor according to claim 1 characterised in that the gate electrode (18) is separated from the surface of the substrate by an insulating layer (16) of a wide-bandgap material, to provide a MISFET configuration. A field effect transistor according to claim 1 characterised in that the gate electrode (20) is applied directly to the surface of the substrate to provide a MESFET configuration. A field effect transistor according to any one of claims 1 to characterised in that the source and drain contacts (14) applied to the source and drain regions (S, D) are quasi-ohmic contacts formed by the deposition of p⁺ doped amorphous silicon or germanium (12) on the substrate (10) above the source and drain regions, with a metal layer (14) being deposited on the p⁺ doped silicon or germanium. A field effect transistor according to claim 4 characterised in that the metal layer (14) comprises aluminium, molybdenum, molybdenum/tantalum alloy, chrome, titanium, nichrome, titanium/tungsten alloy, palladium, platinum, or an aluminium/silicon alloy. A process for manufacturing a field-effect transistor characterised in that it includes the steps of: providing a p-type diamond substrate (10); depositing a layer (12) of p⁺ doped amorphous silicon or germanium on the surface of the substrate; depositing a layer (14) of a first metal over the p⁺ layer; selectively removing portions of the layer (14) of the first metal and the p⁺ layer (12) to define spaced apart source and drain regions (S, D) of the transistor, with a gate region (G) being defined by an exposed portion of the substrate between the source and drain regions; depositing a layer (16) of a wide-bandgap insulating material over the source, gate and drain regions; selectively removing portions of the layer (16) of insulating material; and providing metallic contacts (14, 18) for the source, gate and drain regions which are separated by the insulating material. A process according to claim 6 characterised in that a layer of a second metal (18), different from the first metal (14), is deposited over the layer of insulating material (16) and then selectively removed from the source and drain regions (S, D), so that a MISFET structure is obtained having source and drain contacts (14) of the first metal and a gate contact (18) of the second metal. A process according to claim 6 characterised in that a portion of the layer (16) of insulating material is removed above the gate region (G) to expose the substrate (10), a layer (18) of a second metal having a low work function is deposited over the source, gate and drain regions (S,G,D), and the layer (18) of the second metal is then selectively removed from the source and drain regions, so that a MESFET structure is obtained having source and drain contacts (14) of the first metal and a gate contact (18) of the second metal. A process according to claim 8 characterised in that the second metal is aluminium, gold or titanium. A process according to any one of claims 7 to 9 characterised in that the layer (12) of p⁺ doped amorphous silicon or germanium and the layers (14, 18) of the first and second metals are deposited by chemical vapour deposition (CVD) or physical vapour deposition (PVD). A process according to any one of claims 6 to 10 characterised in that the selective removal of portions of the various layers is done by a photolithographic masking and etching process. A process according to any one of claims 6 to 11 characterised in that the wide-bandgap insulating material (16) comprises an oxide, nitride, oxynitride or carbide, and is deposited by a CVD or PVD process.

Inventors: JONES BARBARA LYNN, JONES, BARBARA LYNN
Applicants: DE BEERS IND DIAMOND, DE BEERS INDUSTRIAL DIAMOND DIVISION (PROPRIETARY) LIMITED
Application year: 1989
Main classification: H01L29
IPC codes: H01L29