Time variant drive for use in integrated circuits

Abstract: A circuit is provided which modifies a digital drive signal to produce a time variant drive signal for appli­ cation to a gate of a bus driver transistor. The circuit's purpose is to reduce the amplitude of ringing on a bus, due to rapid discharging of current from the bus, in order to prevent unintentional triggering of devices connected to the bus. A P-channel MOS transistor (60) and N-channel MOS transistor (50) are connected so that the digital drive signal (V G ) is simultaneously applied to the source of the P-channel MOS transistor (60) and to the drain of the N-channel MOS transistor (50). The gate of the driver transistor (10) is connected to the drain of the P-channel MOS transistor (60) and the source of the N-channel transistor (50). The width-to-length ratio of the channels of the P-channel (60) and N-channel MOS (50) transistors, and the gate voltages, are chosen so that application of a drive signal to the circuit causes the N-channel MOS transistor (50) to rapidly apply a limited drive signal to the gate of the driver transistor (10) and causes the P-channel MOS transistor (60) to apply a gradually increasing drive signal voltage to the gate of the driver transistor (10). By choosing the proper width-to-length ratios and gate voltages, the time variant drive signal applied to the gate of the driver transistor (10) will not produce objectionable ringing on the bus when the bus is intended to be at a low level.

Description: BACKGROUND OF THE INVENTION This invention relates to drivers used in integrated circuits and more particularly to time variant drives for controlling driver transistors. The high speed drivers which can be improved by the present invention are of the type comprising an N-channel MOS (NMOS) or P-channel (PMOS) driver transistor which is controlled by a digital drive signal to, in the case of an NMOS driver transistor, rapidly shunt to ground the current supplied to a data bus, or, in the case of a PMOS driver transistor, rapidly short the data bus to the positive power supply. Shown in Fig. 1 is a typical NMOS driver transistor 10 connected to data bus 15. When a "high" drive signal V G of voltage V max is applied to gate 10-G of driver transistor 10, driver transistor 10 turns on and becomes saturated, thus effectively shorting to ground bus 15. This shunting corresponds to a logical zero signal on bus 15 since bus 15 is pulled low (i.e., to about zero volts). The absence of shunting (i.e., when driver transistor 10 is open) allows a positive voltage to appear on bus 15, representing a logical one. The rapid switching of driver transistor 10 enables the rapid transfer of digital information from drive signal V G to devices connected to bus 15. The design of high speed-high current bus drivers used in integrated circuits has encountered some limitations that have their bases in the laws of physics. When the data bus is shorted to ground by the driver transistor, the rapid change of current and voltage on the bus (i.e., voltage being driven "low") causes a damped oscillation or ringing, shown in Fig. 2, due to the inherent parasitic self-inductances of the leads connected to the driver transistor combined with the inherently capacitive loads of the devices connected to the bus. The equivalent bus circuit is shown in Fig. 3, where device leads 16, 18 have self-inductances represented by inductors 20, 22 and the capacitive load is represented by capacitor 24. The bus circuit, therefore, effectively forms an LC oscillator circuit, where L equals the combined inductance of leads 16, 18, and C equals the capacitance of the load, with a ringing frequency related to 1/(LC) ½ , although this frequency is altered in actual circuits by additional factors. This damped ringing can cause unintentional triggering of devices connected to bus 15 if the amplitude of an oscillation cycle exceeds the logic threshold level of the devices. This situation is shown in Fig. 2 at time T, where V th is the logic threshold level of the devices. Various approaches have been taken to eliminate the effect of these initial discharge transient currents. These approaches have limited the current through the driver transistor, thereby initially shunting to ground only part of the current supplied to the bus through the driver transistor and, consequently, reducing the amplitude of the ringing. This limited current through the driver transistor is then increased to the full current required to fully shunt to ground all the current supplied to the bus. The amount of current shunted at each stage is calculated to be insufficient to cause objectionable ringing on the bus. One technique, shown in Fig. 4a, used to implement this approach is to use two MOS transistors 26, 28 in parallel as the driver, where transistor 26 only shunts to ground a portion of current supplied to bus 15 upon application of drive signal V G , while transistor 28 shunts to ground the remaining current supplied to bus 15 upon application of slightly delayed drive signal V G ′. Fig. 4b shows the voltage (V out ) applied to the devices connected to bus 15. A problem with this prior art technique is that a fairly complex digital logic network must be designed and incorporated into the integrated circuit to provide delayed drive signal V G ′. Also, parallel drivers 26 and 28 must turn off quickly at the same time to avoid incurring two separate current surges on bus 15, which may, in conjunction, cause unintentional triggering of devices connected to bus 15. Another disadvantage is that the degree of ringing on the bus is a function of the sizes of drivers 26 and 28 (i.e., width-to-length ratio). Therefore, the extent of ringing on the bus is fixed once the drivers have been fabricated. Another technique, shown in Fig. 5a, is used to provide a two-tiered drive signal to driver transistor 10, wherein the first tier is of a voltage V G1 sufficient to cause driver transistor 10 to shunt to ground only a portion of the current supplied to bus 15. The second tier is the addition of a slightly delayed voltage V G2 , where the sum of V G1 and V G2 make driver transistor 10 fully conduct and shunt to ground all current supplied to bus 15. Fig. 5b shows the voltage (V out ) supplied to the devices connected to bus 15. The above described two-tiered drive signal generator is relatively complex due to its requiring two voltage sources, and, as in the circuit of Fig. 4a, requires the two voltage sources turn off simultaneously to avoid two separate current surges on bus 15. Figure 6 illustrates a typical output driver stage used in CMOS circuitry. In the circuit of Figure 6, the positive supply voltage +V is not shorted to ground when current is to be shunted away from bus 15, as in Figs. 1-5, but instead the bus is exclusively coupled to either +V or ground. Shown in Figure 6 are NMOS driver transistor 30 and PMOS driver transistor 32, forming the output driver stage. The gate of NMOS driver transistor 30 is coupled to a pre-driver stage comprising NMOS transistor 34 and PMOS transistor 36, while the gate of PMOS driver transistor 32 is coupled to a pre-driver stage comprising NMOS transistor 38 and PMOS transistor 40. The gates of all transistors forming the pre-driver stage are made common and coupled to an input drive signal V in so that upon application of a sufficiently low V in pre-driver transistors PMOS 36 and PMOS 40 will conduct, causing +V to be applied to the gate of NMOS driver transistor 30 and PMOS driver transistor 32. NMOS driver transistor 30 will now fully conduct and drive bus 15 to approximately ground potential. When a sufficiently positive input drive signal V in is applie4d to the gates of the pre-driver transistors, only pre-driver transistor NMOS 34 and NMOS 38 will conduct, causing PMOS driver transistor 32 to turn on and drive bus 15 to approximately +V. Accordingly the present invention provides a drive circuit for generating a time dependent voltage drive signal in response to a digital input signal, to drive a transistor arrangement, comprising an N-type field effect first transistor and a P-type field effect second transistor, the drain of the first transistor and the source of the second transistor both being connected to receive said digital input signal, the source of the first transistor and the drain of the second transistor both being connected to a node arranged to supply said drive signal, the gate of said first transistor being connected to a first bias potential, and the gate of said second transistor being connected to a second bias potential; characterised in that said first bias potential is lower than the maximum value of said digital input signal; said first transistor has a channel width to length ratio such that a transition to a high value of said digital input signal produces an initial fast rise rate to an intermediate value in said drive signal, while said second transistor has a channel width to length ratio such that said transition of said digital signal produces a slower subsequent rise rate in said drive signal from said intermediate value to the full value of said drive signal. When the digital drive signal is applied to the drain of the N-type transistor, the voltage at the source of the N-type transistor, and consequently at the gate of the driver transistor, rises to equal V bias -V th , where V th is the threshold voltage of the N-type transistor. V bias is selected so that the driver transistor will shunt the maximum current away from the bus without producing ringing which exceeds threshold levels. A gradually increasing voltage imparted to the gate of the driver transistor by the P-type transistor causes the driver transistor to increasingly shunt more current away from the bus until the bus is pulled to a minimum low level. When the externally generated digital drive signal goes low, the N-type transistor quickly discharges the gate of the driver transistor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a typical driver transistor connected to a data bus. Fig. 2 shows the damped ringing effect caused by instantaneous shunting of current through the driver. Fig. 3 is a schematic diagram of a driver transistor and a bus circuit showing inductances and capacitances inherent in the bus circuit. Fig. 4a and 5a are schematic diagrams of prior art time variant bus drivers. Figs. 4a and 5b are graphs showing bus voltage versus time for the circuits of Figs. 4a and 5a, respectively. Fig. 6 is a schematic diagram of a prior art non-time variant bus driver using CMOS circuitry. Fig. 7 is a schematic diagram of a time variant driver circuit constructed in accordance with one embodiment of the invention. Fig. 8 graphs a-e, show graphs illustrating the voltage versus time at various points in the circuit of Fig. 7. Fig. 9 is a schematic diagram of a time variant driver circuit constructed in accordance with another embodiment of the invention. Fig. 10 is a schematic diagram of a time variant driver constructed in accordance with the preferred embodiment of the invention. DETAILED DESCRIPTION The present invention is a circuit which reduces or overcomes the problems of prior art time variant drive circuits discussed previously. Fig. 7 shows a schematic diagram depicting a time variant driver circuit, constructed in accordance with one embodiment of this invention, which provides a time variant drive signal to a driver transistor, such as an N-channel type, in order to eliminate objectionable ringing on a bus. In Fig. 7, N-channel MOS (NMOS) transistor 50 has its drain 50-D connected to receive digital drive signal V G , shown in Fig. 8, graph a, and its source 50-S connected to gate 10-G of driver transistor 10. It is to be noted that since the driver circuit is completely bidirectional (i.e., current flows through NMOS transistor 50 and PMOS transistor 60 in both directions), the designations of terminals as source and drain are arbitrary. Bias voltage V bias is applied to gate 50-G of NMOS transistor 50, where V bias is less than the maximum digital drive signal voltage V max . NMOS transistor 50 has a channel width-to-length ratio (W/L) such that, when V G goes high, NMOS transistor 50 rapidly charges gate 10-G of driver transistor 10, as shown in Fig. 8, graph b, at time T1. The final voltage applied to gate 10-G of driver transistor 10 due to NMOS transistor 50 will be only V bias -V th , where V th is the threshold voltage of NMOS transistor 50, since the voltage at the source of NMOS transistor 50 is unable to go any higher without turning off NMOS transistor 50. Bias voltage V bias must be chosen so that driver transistor 10 initially shunts to ground as much current as possible without producing ringing on bus 15 sufficiently large to exceed logic threshold levels. This current shunted by driver transistor 10 in response to the gate voltage will normally be sufficient to drive bus 15 to a low logic state. P-channel MOS (PMOS) transistor 60 has its source 60-S connected to receive digital drive signal V G and its drain 60-D connected to gate 10-G of driver transistor 10. Gate 60-G of PMOS transistor 60 is grounded so as to make PMOS transistor 60 conduct when a positive voltage is applied to its source. The channel of PMOS transistor 60 has a W/L such that, when digital drive signal V G goes high, PMOS transistor 60 does not instantaneously charge gate 10-G of driver transistor 10 to the maximum digital drive signal voltage V max , but gradually charges gate 10-G of driver transistor 10, as shown in Fig. 8, graph c, to V max . The slope of voltage versus time in Fig. 8, graph c, is chosen so that the additional shunting to ground of current by driver transistor 10 under the control of PMOS transistor 60 will not increase the amplitude of ringing on bus 15 above the logic threshold levels of devices connected to bus 15. The combination of the voltages applied to gate 10-G of driver transistor 10 from NMOS transistor 50 and PMOS transistor 60 is shown in Fig. 8, graph d. This time variant drive signal V G(t) controls driver transistor 10, thus providing time variant shunting to ground of current supplied to bus 15. The resulting voltage V out , as measured on bus 15, is shown in Fig. 8, graph e, and represents a logical zero on bus 15 between the times T2 and T3. As seen, even though ringing is still apparent on bus 15 after digital drive signal V G goes high at time T1, V out does not exceed logic threshold levels. V bias may be adjusted as desired to allow increased ringing or to eliminate ringing altogether. Computer simulations of this time variant drive circuit coupled to the circuits to be switched can be run with various levels of V bias to see the switching response with the various levels of V bias . V bias may be adjusted as desired to allow increased ringing or to eliminate ringing altogether. As seen, the extent of ringing on bus 15 in response to the output of the time variant drive circuit is largely controlled by the magnitude of V bias . Since V bias is adjustable after the time variant driver circuit and load circuit have been fabricated, V bias may later be adjusted to optimize switching response. When digital drive signal V G goes low, the charge on gate 10-G of driver transistor 10 must be rapidly removed in order to allow the full supply voltage +V to once again appear on bus 15. PMOS transistor 60 cannot effectively discharge to ground the charge on gate 10-G of driver 10 when digital drive signal V G goes low due to the relatively small channel W/L of PMOS transistor 60. NMOS transistor 50, however, having a much larger channel W/L than PMOS transistor 60, can easily discharge the charge on gate 10-G of driver transistor 10, resulting in no measurable effect on turn-off delay. The NMOS transistor 50 and PMOS transistor 60 channel W/L dimensions may be made non-critical by using the following criteria. The W/L of NMOS transistor 50 should be made at least as large as transistors in a previous driving stage so as not to add appreciable delay between application of drive signal V G to NMOS transistor 50 and application of the lowered drive signal to the gate of driver transistor 10. At this W/L, NMOS transistor 50 is also large enough to properly discharge the gate of driver transistor 10. The W/L of PMOS transistor 60 must be small enough so that the rise of V G(t) to V max is delayed sufficiently from the NMOS transistor 50 response. This W/L will typically be 1/100 that of the NMOS transistor 50 W/L. In an actual physical embodiment of the device the channel width and length dimensions of PMOS transistor 60 were both made 2 microns. These dimensions are non-critical and are calculated using well known techniques. The desired W/L may be implemented by standard lithographic processes in the formation of the integrated circuit. Fig. 9 shows a time variant drive circuit using CMOS technology. The circuit is similar to the prior art CMOS drive circuit of Fig. 6 except that the circuit is made time variant by the incorporation of transistors 65, 70, 75, and 80. Transistors 30, 32, 34, 36, 38, and 40 perform similarly to the corresponding transistors in the circuit of Fig. 6. The operation of NMOS transistor 65 and PMOS transistor 70, NMOS transistor 65 and PMOS transistor 70 being connected between NMOS driver transistor 30 and its corresponding pre-driver stage, is identical to the operation of NMOS transistor 50 and PMOS transistor 60, shown in Fig. 7, wherein NMOS transistor 65 has a W/L sufficient to quickly charge the gate of NMOS driver transistor 30 to V bias (N), and PMOS transistor 70 has a W/L such as to gradually charge the gate of NMOS driver transistor 30 to the full drive signal voltage level. The operation of NMOS transistor 75 and PMOS transistor 80, NMOS transistor 75 and PMOS transistor 80 being coupled between PMOS driver transistor 32 and its corresponding pre-driver stage, differs slightly from the operation of NMOS transistor 50 and PMOS transistor 60, shown in Fig. 7, in that when a high V in is applied to the gates of pre-driver transistors 38 and 40, producing a low voltage at the source of NMOS transistor 75 and at the drain of PMOS transistor 80, PMOS transistor 80, having a large channel W/L, allows the gate of PMOS driver transistor 32 to be quickly lowered to V bias (P). NMOS transistor 75, having a small channel W/L, slowly discharges the gate of PMOS driver transistor 32 to the low voltage thus completely turning on PMOS driver transistor 32. The channel W/L of PMOS transistor 80 and NMOS transistor 65 are large enough to allow PMOS driver transistor 32 and NMOS driver transistor 30 to turn off quickly. Thus, the operation of transistors 65, 70, 75, and 80 ensures both NMOS driver transistor 30 and PMOS driver transistor 32 have their full turn-on delayed, hence, reducing or eliminating any ringing on bus 15. Fig. 10 shows basically the same circuit as Fig. 9 except that transistors 65, 70, 75, and 80 have been bypassed to allow PMOS driver transistor 32 and NMOS driver transistor 30 to turn off without having to conduct gate current through transistors 65, 70, 75, and 80. Transistors 30, 32, 34, 36, 38, and 40 operate similarly to the corresponding transistors in the circuit of Fig. 9. This preferred embodiment of the time variant driver circuit using CMOS technology offers all of the aforementioned benefits of the time variant gate drive, but offers no deterioration or loss of turn-off speed of the output stages. In Fig. 10, the gate of PMOS driver transistor 32 is directly coupled to the drain of PMOS pre-driver transistor 40 in the pre-driver stage so that when input drive signal V in is low, the gate of PMOS driver transistor 32 will immediately be driven high, turning off PMOS driver transistor 32. When V in is high, the gate of PMOS driver transistor 32 will be discharged through NMOS transistor 75 and PMOS transistor 80 as described in Fig. 9. Similarly, the gate of NMOS driver transistor 30 is directly coupled to the drain of NMOS transistor 34 so that upon application of a high V in to the gate of NMOS transistor 34, the gate of NMOS transistor 30 will immediately discharge, turning off NMOS driver transistor 30. When V in is low, thus signaling for NMOS driver transistor 30 to turn on, the gate of NMOS driver transistor 30 is charged via NMOS transistor 65 and PMOS transistor 70 as described in Fig. 9. As seen, a prior art driver circuit, to be made time variant, requires no redesign of pre-driver stages or the driver transistor stage. In one embodiment, previously described, two transistors, such as NMOS transistor 50 and PMOS transistor 60, shown in Fig. 7, are merely connected between the existing driver transistor gate and a pre-driver output to form a time variant driver circuit. Also, an NMOS transistor can be substituted for PMOS transistor 60 in Fig. 7, wherein the NMOS transistor has a channel W/L so that it conducts gradually and has a bias voltage applied to its gate which is higher than the maximum drive signal amplitude. A single MOS transistor of an N or P-channel type which conducts gradually may also supply a time variant drive signal to a driver transistor if switching speed of the logic state of the bus is not critical (i.e., there is no requirement for the gate of the driver transistor to charge or discharge quickly to V bias ). Also, any bidirectional field effect transistor may be substituted for the MOS transistors used in the various embodiments.

Claims: A drive circuit for generating a time dependent voltage drive signal (V Gt ), in response to a digital input signal (V G ), to drive a transistor arrangement (10;30,32), comprising an N-type field effect first transistor (50) and a P-type field effect second transistor (60), the drain (50D) of the first transistor and the source (60S) of the second transistor both being connected to receive said digital input signal (V G ), the source (50S) of the first transistor and the drain (60D)of the second transistor both being connected to a node arranged to supply said drive signal (V Gt ), the gate of said first transistor being connected to a first bias potential (V bias ), and the gate of said second transistor being connected to a second bias potential; characterised in that said first bias potential (V bias ) is lower than the maximum value of said digital input signal (V G ); said first transistor has a channel width to length ratio such that a transition to a high value of said digital input signal (V G ) produces an initial fast rise rate to an intermediate value (V bias -V th ) in said drive signal (V Gt ), while said second transistor has a channel width to length ratio such that said transition of said digital signal (V G ) produces a slower subsequent rise rate in said drive signal from said intermediate value to the full value (V max ) of said drive signal. A transistor output arrangement comprising a complementary pair of CMOS transistors (30,32), characterised in that each complementary transistor is connected by its gate to a respective drive circuit as claimed in Claim 1. A transistor output arrangement as claimed in Claim 2, characterised in that each said drive circuit receives said digital input signal by way of a respective complementary pair of CMOS transistors (34,36;38,40). A transistor output arrangement comprising a complementary pair of CMOS transistors (30,32) each connected to receive a digital signal at its gate by way of a respective complementary pair of CMOS transistors (34,36;38,40) characterised in that a drive circuit, as claimed in Claim 1, is connected in series between the transistors of each said respective complementary pair (34,36;38,40).

Inventors: KUBINEC JAMES J, KUBINEC, JAMES J.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1989
Main classification: H03K17
IPC codes: G06F3, H03K17, H03K19, H04L25