Logic circuit with a test function

Abstract: A logic circuit having a plurality of macrocells and a testing function for processing test input data and outputting a result of the process. Each of the macrocells is tested independently of each other and includes an input-output circuit (8). The input-output circuit (8) comprises: a first holding device (12) for holding the test input data; a selector circuit (15) for shutting off an input path of normal operation signals to the macrocell in question at the time of testing the macrocell, selecting the test input data held in the first holding device (12), and outputting the selected test input data to a portion to be tested of the macrocell; a second holding device (18) for holding test output data obtained as a result of a test process carried out in the macrocell on the test input data, and outputting the test output data to the outside; and a switching circuit (19) for shutting off, at the time of testing the macrocell, an output path of normal operation signals from the macrocell to other circuit portions of the logic circuit.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a logic circuit, and particularly to a logic circuit employing previously prepared macrocells to enable the logic circuit to be tested easily, and having enhanced test-feasibility. Description of the prior Art In recent years, LSIs based on the macrocell system are used. These LSIs are a kind of custom LSIs. The macrocell system uses macrocells each of which is a circuit block comprising a plurality of elements such as transistors, resistors and capacitors to realize a predetermined function such as a RAM and an ALU. The macrocells are prepared in advance and registered in, for instance, a data base. The macrocells thus prepared are arranged and wired among them manually or with a CAD to design and form an LSI. Compared to other conventional designing method, the macrocell system can greatly reduce a developing period and developing costs of a LSI. And as a reasonable test for a logic circuit such as LSI, a method of supplying test data into the logic circuit and comparing the output from the logic circuit with an expected value is generally being used. An example of this sort of method is an LSSD (Level Sensitive Scan Design) method. How to test an integrated circuit with this method will be explained. In testing the integrated circuit, all flip-flops (FFs) in the integrated circuit are controlled to form one continuous shift register. Input test data from a test data generating unit are passed through the shift register and supplied to a combinational logic circuit of the integrated circuit, and combinational logic circuit is controlled to execute one cycle of operation. An output signal from the combinational logic circuit is latched by the shift register, output from the integrated circuit via a scan signal output terminal, and compared with an expected value to judge whether or not the integrated circuit has achieved a predetermined function. Conventionally, the logic circuit designed and formed according to the macrocell system is tested as a whole by using, for instance, the LSSD method. Since, however, the circuit is tested as a whole, it is difficult to reuse test data already prepared for the respective macrocells, and test data for the logic circuit as a whole should be prepared newly. US-A-3 924 144 shows a method of testing by dividing into isolated functional sub-assemblies Test output patterns from the parts are multiplexed to enable output from a single pin IEEE Design and test of computers vol. 3 no. 6, Dec. 1986, p. 26-32 shows macro testing using test interface elements inserted on signals between macros, for serial testing of macros. To solve the problem of the conventional technique, the object of the present invention is to provide an improved logic circuit. According to the present invention there is provided a logic circuit capable of operation in a test execution mode and in a normal operating mode, said logic circuit comprising: an operational circuit for providing normal operating mode input signals, a plurality of macrocell means for producing normal operating mode output signals, input path means for transferring said normal operating mode input signals to said plurality of macrocell means, and output path means for transferring said normal operating mode output signals to said operational circuit, each of said macrocell means being capable of being independently tested and having a test object portion and input-output circuit means for inputting input test data and for outputting output test data in said test execution mode, said input-output circuit means including: first holding means for holding said input test data, selector circuit means for shutting off said input path means in said test execution mode, for selecting said input test data from said first holding means and for outputting said input test data to said test object portion, said test object portion being responsive to said input test data to perform a test execution and produce said output test data as a result thereof, second holding means for holding said output test data and outputting said output test data externally of said macrocell means, and switching circuit means for shutting off said output path means in said test execution mode. The present invention will be more readily understood by referring, by way of example, to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram for a logic circuit according to an embodiment of the present invention; Fig. 2 is a circuit diagram showing the details of an input-output circuit of the logic circuit shown in Fig. 1; and Fig. 3 is a set of timing charts of clock signals used in the logic circuit shown in Fig. 1. DETAILED DESCRIPTION OF THE EMBODIMENTS Fig. 1 is a block diagram showing a logic circuit 1 according to an embodiment of the present invention. In a testing mode, each macrocell can be tested independently from other circuit portions. The logic circuit 1 of Fig. 1 has the plurality " l " of macrocells 2(1) to 2( l ), an input-output circuit 3 for receiving input-signals for the logic circuit 1 and generating output-signals for the logic circuit 1, a combinational logic circuit 4 which functions as an interface between the input-output circuit 3 and the macrocells 2(1) to 2( l ) and as a signal transmission path among the macrocells, and a decoder 5 for generating, in the test mode, a select signal for selecting any one of the macrocells 2(1) to 2( l ) or the logic circuit 1 as a whole as a circuit to be tested. The input-output circuit 3 receives a signal T/ N that specifies a test mode or a normal operation mode, clock signals  W ,  T ,  E and  R . Further, the input-output circuit 3 receives, in the test mode, test input data IN. The macrocell 2(1) comprises a memory circuit 6 made of many FFs, a combinational logic circuit 7 and an input-output circuit 8. Each of the other macrocells 2(2) to 2 ( l ) has the same constitution as that of the macrocell 2(1). Under normal operation of the logic circuit 1, input signals 101 are given from the outside to the logic circuit 1, and supplied to the input-output circuit 8 in each macrocell. Input signals of normal operation mode supplied to the input-output circuit 8 are supplied to the memory circuit 6 via the combinational logic circuit 7. Output signals of the memory circuit 6 are given to the input-output circuit 8 via the combinational logic circuit 7. Output signals from the input-output circuits 8 are passed through the combinational logic circuit 4 and the input-output circuit 3 and output as output signals 102 of normal operation mode to the outside of the logic circuit 1. Under a test mode where each macrocell 2(1) to 2( l ) is tested, test input data IN are given from the outside of the logic circuit 1 to the input-output circuit 8 of a macrocell to be tested. Then, the test input data IN are given to the memory circuit 6 via the combinational logic circuit 7. An output from the memory circuit 6 is given to the input-output circuit 8 via the combinational logic circuit 7 and output as test output data OUT from the input-output circuit 8 to the outside of the logic circuit 1. Similarly, under a test mode where the logic circuit 1 as a whole is tested, test input data IN are given from the outside of the logic circuit 1 to the input-output circuit 3. Then, the test input data IN are given to the respective macrocells 2(1) to 2( l ) through the combinational logic circuit 4, and the output from macrocells are output as test output data OUT through the combinational logic circuit 4 and the input-output circuit 3 to the outside of the logic circuit 1. The decoder 5 receives a select signal 103 for selecting a circuit portion to be tested, from the outside of the logic circuit 1 and decodes the select signal 103. And the decoder 5 generates one of the decoded signals 104-0 to 104- l to specify a test object circuit among macrocells 2(1) to 2( l ) and the logic circuit 1. When the logic circuit 1 as a whole is designated as a circuit to be tested by the select signal 103, the decoder 5 outputs a decoded signal 104-0 of signal value 1 to the input-output circuit 3. When the macrocell 2(i) (i = 1, 2, ...., l ) is designated as a circuit to be tested by the select signal 103, the decoder 5 outputs a signal 104-i of value 1 to the input-output circuit 8 of the macrocell 2(i) to be tested. Under the test mode, when the logic circuit 1 is designated as a test object circuit and the input-output circuit 3 receives the signal 104-0 of logical value 1, the input-output circuit 3 separates the logic circuit 1 from other circuit portions, receives test input data IN, and outputs the result of process carried out in the logic circuit 1 on the test input data IN as test output data OUT. Similarly, when the macrocell 2(i) is designated as a test object circuit and the input-output circuit 8 of the macrocell 2(i) receives the signal 104-i of logical value 1 under the test mode, the input-output circuit 8 separates this macrocell 2(i) from the other remaining circuits, transmits the test input data IN to the test object portion in the macrocell 2(i) conists of combinational logic circuit 7 and memory circuit 6, and outputs the result of the operation carried out in the macrocell 2(i) on the test input data IN as test output data OUT. The details of the input-output circuits 3 and 8 will be described. Fig. 2 is a view showing the details of the input-output circuit 3 (8). The input-output circuits 3 and 8 are similarly constituted. Flip-flops FF 11(1) to FF 11(m) constitute a shift register 12. The number "m" of stages of the shift register 12 is equal to the number of bits of a first input signal. For the input-output circuit 3, the first input signal is the input signal 101 input from the outside to the logic circuit 1. For the input-output circuit 8, the first input signal is a normal operation mode output signal of the combinational logic circuit 4. Under the test mode the test input data IN are sequentially set to the FFs 11(1) to 11(m), in synchronism with the write clock signal  W shown in Fig. 3. Flip-flops FF 13(1) to FF 13(m) form a shift register 14. Under the test mode each bit value of the test input data IN held in the FF 11(i) is transferred to each FF 13(i) and stored therein in synchronism with the transfer clock signal  T shown in Fig. 3. The test input data IN written in the shift register 14 are sequentially read out thereof in synchronism with the read clock signal  R shown in Fig. 3. Each of the input-output circuits 3 and 8 has "m" pieces of selectors 15(1) to 15(m). Each selector 15(i) receives an "i"th bit of the first input signal as well as an output of the FF 13(i). The selector 15(i) selects and outputs the output of the FF 13(i) when the macrocell 2(i) or the logic circuit 1 is designated as a test object circuit and the decoded signal 104-i of logical value 1 is input to the input-output circuit of macrocell 2(i) or of the logic circuit 1 under the test mode. In other cases, the selector 15(i) selects the "i"th bit of the first input signal. The "i"th bit of the first input signal or the output of the FF 13(i) thus selected is given to a buffer circuit 16(i). The buffer circuits 16(1) to 16(m) output after amplication or block the signals given from the respective selectors, according to a control signal generated in a control signal generating portion (not shown). A plurality "n" of FFs 17(1) to 17(n) constitute a shift register 18. The number "n" of stages of the shift register 18 is equal to the bit width of a second input signal. For the input-output circuit 3, the second input signal is an output signal of the combinational logic circuit 4. For the input-output circuit 8, the second input signal is an output signal of the combinational logic circuit 7. The FF 17(1) in the first stage of the shift register 18 is connected to the FF 13(m) in the last stage of the shift register 14. The second input signal is set in the FFs 17(1) to 17(n) under the test mode in synchonism with the execution clock signal  E shown in Fig. 3. And under the test mode, the shift registers 14 and 18 operates as one continuous shift register , information pieces held in the shift registers 14 and 18 are output as the test output data OUT in synchronism with the read clock signal  R shown in Fig. 3. Each of the input-output circuits 3 and 8 is provided with buffer circuits 19(1) to 19(n). The buffer circuits 19(1) to 19(n) receive the decoded signal, and their internal conditions are controlled by the decoded signal. That is when the decoded signal of logical value 1 is input under the test mode, each buffer circuit is put in a high-impedance state to separate the logic circuit 1 or the macrocell as test object circuit from other circuit portions. In other cases, the buffer circuits of the input-output circuit 3 output the second input signal as the output signal 102 to the outside, and the buffer circuits of the input-output circuit 8 output the second input signal to the combinational logic circuit 4. In the above statements, the input-output circuit 3 of the logic circuit 1 and the input-output circuit 8 of each macrocell have been explained in parallel, and distinction between the two kinds of the input-output circuits was not explicitly pointed out for the convenience of explanation. However, they have incidental differences of course. For example, the bit widths of first input signals thereof generally differ from each other. Operation of the logic circuit of the above-mentioned arrangement will be described. Firstly, the case of testing the logic circuit 1 as a whole will be explained. To put the logic circuit 1 in the test mode, the decoded signal 104-0 of logical value 1 is given to the input-output circuit 3. Hereby, the logic circuit 1 is designated as a circuit to be tested. "m" bits of the test input data IN are set in the shift register 12 of the input-output circuit 3 in order and in synchronism with "m" pulses of the clock  W indicated with "A" on the top timing chart of Fig. 3. Then the test input data IN is transferred to the shift register 14 in synchronism with a pulse of the transfer clock  T as indicated with "A" on the second timing chart of Fig. 3. In this case, the test is entirely for the checking of operation of the input-output circuit 3 and combinational logic circuit 4. Therefore, much smaller number of test input data IN are needed than in the case when a respective macrocell is selected as a test object circuit. The test input data IN transferred to the shift register 14 is given to the combinational logic circuit 4 via the selectors 15(1) to 15(m) and buffer circuits 16(1) to 16(m). The test input data IN given to the combinational logic circuit 4 is given to the input-output circuits 8 of the respective macrocells. And in synchronism with a pulse of the execution clock  E incicated with "A" on the third timing chart of Fig. 3, the logic circuit 1 is operated on the test input data IN for one cycle. Thus, one cycle of the test is executed. After the completion of a cycle of the test, a result of the cycle is set in the shift register 18 at the fall of a pulse of the clock  E indicated with "A" in Fig. 3. The test result set in the shift register 18 is output as test output data OUT together with input data IN set in the shift register 14 to the outside of the logic circuit 1 in synchronism with pulses of the read clock  R indicated with "A" on the fourth timing chart of Fig. 3. While one cycle operation of the logic circuit 1 is being carried out on the test data which was set in the shift register 14 in synchronism with the pulse of the transfer clock signal  T indicated with "A" on the second timing chart of Fig. 3, a test input data IN to be used in the next test cycle is set in the shift register 12 in synchronism with pulses of the write clock  W indicated with "B" on the top timing chart of Fig. 3. As a result, the test can be carried out in real time to shorten a total testing time. Further, by connecting the FFs 17(1) to 17(n) to form a linear feedback shift register (LFSR), GO/NO-GO test to judge whether a product is acceptable or not can be carried out effectively. The case where each macrocell 2(i) is tested independently will now be explained. In this case, a decoded signal 104-i of logical value 1 is given to the macrocell 2(i) to be tested. Then, each selector 15(i) in the input-output circuit 8 of the macrocell 2(i) selects the output of each FF 13(i) as its output, and the buffer circuits 19(1) to 19(n) are put in a high-impedance state. Therefore, the macrocell 2(i) to be tested is separated from the other circuit portions. Under such conditions, the test input data IN is set from the outside of the logic circuit 1 to the shift register 12 of the input-output circuit 8 in synchronism with the write clock signal  W . After that, test is executed for the specified macrocell 2(i), similar to the above stated test for the logic circuit 1 as a whole. In this way, each macrocel can be tested independently of each other. Therefore, a set of test data prepared for the respective macrocells in advance can be used in testing the logic circuit 1, thus eliminating the necessity of newly preparing test data. As a result, developing period for the logic circuit 1 can remarkably be reduced, and development cost is greatly reduced. Further, testing time can greatly be shortened since the test is carried out in real time. The logic circuit 1 itself may be used as a macrocell of a larger scale logic circuit. In this case, a select signal given to the decoder 5 can be set to a predetermined value to specify the logic circuit 1 as a circuit to be tested. Thus, the logic circuit 1 as a macrocell can be tested independently of other circuits. Therefore, with the present invention it becomes possible to offer any scale of a logic circuit with enhanced test feasibility systematically. And by combining a plurality of such logic circuits, a larger scale logic circuit with enhanced test feasibility can be realized easily. For instance, if the number of macrocells of the logic circuit 1 is not large, the decoder may be omitted, and each test object macrocell can be directly designated by a select signal which is given from the outside of the logic circuit 1. And when it is not necessary to read out the test input data IN transferred to and set in the FFs 13(1) to 13(m), the FFs 13(1) to 13(m) may not be needed to be formed into a shift register. Further, when only a final result is needed and intermediate results are not needed, and so there is no need for reading out the contents of FF 17(1) to 17 (l) in each cycle of the execution clock signal  E , in such a case where, for example, test is executed as summation over many data, it suffices for this object to execute test in a sequence where first repeating steps of inputting test input data IN and test execution predetermined number according to the write clock signal  W , transfer clock signal  T , and execution clock signal  E , next reading out the final result according to the read clock signal  R . It is also possible to omit the shift register 14 in the logic circuit 1. In this case, though real time test is no longer possible, still it is possible to separate the test object circuit from other remaining circuits and test it independently. Still further, when it is not needed to set values of the second input signals in FF 17(1) to 17(n)in in the normal operation , it is possible to dispose n switches on the signal paths of the second input signals before respective FF 17(1) to 17(n), and turn-off them in the normal operation. Thus the invention provides a logic circuit which is constructed from plural macrocells, and in which each macrocell can be tested independently. For the test of a logic circuit of the present invention, it is possible to use the test data which are already obtained for each macrocell of the logic circuit. Thus labour for obtaining new test data is no longer needed, and so the time and cost required for the development of a logic circuit is greatly reduced. And the invention present a logic circuit in which while a cycle of test is executed, test input data which is used in the next cycle is input, and test is executed in real time. Thus this logic circuit has the more enhanced test feasibility.

Claims: A logic circuit capable of operation in a test execution mode and in a normal operating mode, said logic circuit comprising: an operational circuit for providing normal operating mode input signals; a plurality of macrocell means (2) for producing normal operating mode output signals; input path means for transferring said normal operating mode input signals to said plurality of macrocell means (2); and output path means for transferring said normal operating mode output signals to said operational circuit, each of said macrocell means (2) being capable of being independently tested and having a test object portion (6,7) and input-output circuit means (8) for inputting input test data and for outputting output test data in said test execution mode, said input-output circuit means (8) including: first holding means (12, 14) for holding said input test data, selector circuit means (15) for shutting off said input path means in said test execution mode, for selecting said input test data from said first holding means (12, 14) and for outputting said input test data to said test object portion (6,7), said test object portion (6,7) being responsive to said input test data to perform a test execution and produce said output test data as a result thereof, second holding means (18) for holding said output test data and outputting said output test data externally of said macrocell means (2), and switching circuit means (19) for shutting off said output path means in said test execution mode. The logic circuit of claim 1, which further comprises: additional input path means for transferring said normal operating mode input signals to said logic circuit; additional output path means for transferring said normal operating mode output signals from said logic circuit; additional input-output circuit means (3) for inputting said input test data and for outputting said output test data in said test execution mode, said additional input-output circuit means (3) including: additional first holding means (12, 14) for holding said input test data; additional selector circuit means (15) for shutting off said additional input path means in said test execution mode, for selecting said input test data from said additional first holding means (12, 14) and for outputting said test input data to an additional test object portion (6, 7) in said logic circuit, said additional test object portion (6, 7) responding to said input test data to perform a test execution and produce said output test data as a result thereof; additional second holding means (18) for holding said output test data and outputting said output test data externally of said logic circuit, and additional switching circuit means (19) for shutting off said additional output path means in said test execution mode, said logic circuit being capable of being independently tested. The logic circuit of claim 1, wherein said first holding means (12, 14) and said second holding means (18) each include a shift register, respectively. The logic circuit of claim 1, which further comprises: decoder means (5) for receiving a select signal for selecting a particular macrocell means (2) to be tested, decoding said select signal, and supplying a decoded select signal to said input-output circuit means (8) of said particular macrocell means (2) to be tested. The logic circuit of claim 1, wherein said first holding means comprises a first holding circuit (12) for holding said input test data and a second holding circuit (14) for holding said input test data transferred from said first holding circuit (12). The logic circuit of claim 5, wherein said first holding means, said second holding means and said third holding means each include a shift register, respectively, and a second shift register constituting said second holding means is connected to a third shift register constituting said third holding means (18) in series to output said output test data as well as said input test data. The logic circuit of claim 5, wherein said first holding means and said third holding means each include a shift register, respectively. The logic circuit of claim 5, which further comprises: decoder means (5) for receiving a select signal for selecting a macrocell means (2) to be tested, decoding said select signal, and supplying a decoded select signal to said input-output circuit means (8) of said macrocell means (2) to be tested.

Inventors: KANUMA AKIRA, KANUMA, AKIRA
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G06F11
IPC codes: H03K19, G01R31