Threshold tracking system

Abstract: A system for decoding signals such as Class IV partial-response signals, wherein threshold levels are used to distinguish between binary ones and zeros in partial-response signals. The threshold levels are adjusted by a feedback system (37, 39, 19) to compensate automatically for effects such as signal dropouts.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to systems for decoding signals such as Class IV partial-response signals and, more particularly, to systems wherein threshold levels that are used to distinguish between binary ones and zeros when decoding partial-response signals are adjusted automatically to compensate for effects such as signal dropouts. In the art of recording information on magnetic media, various techniques have been developed to maximize data packing densities and to improve reproduced signal response in the presence of noise. In particular, a technique known as "Class IV partial-response coding" has proven beneficial to enhance the extraction of digital information from recordings on magnetic tape. Methods for encoding information in the partial-response signals format are disclosed in Kabal and Pasupathy, "Partial-Response Signalling", IEEE Transactions on Communications, Vol. COM-23, No. 9, September 1975. In reproducing digital data that has been recorded on magnetic tape, one advantage of Class IV partial-response coding is that signal-to-noise ratios of off-tape signals are significantly improved. Also, signals encoded by Class IV partial-resonse coding are DC free during tape playback, i.e., the encoded off-tape signals are automatically centered on zero volts. The use of partial-response coding in magnetic recording systems is described in an article by Kobayashi and Tang, "Application of Partial-Response Channel Coding to Magnetic Recording Systems", IBM J. Res. & Devel., July, 1970. Partial-response coding of digital signal information, however, has several drawbacks. One drawback is that encoded partial-response signals are not binary but have three levels. Generally speaking, this problem can be overcome by full-wave rectification of the off-tape partial-response signals. A more significant problem is that changes in the amplitude of off-tape partial-response signals can adversely affect decoding accuracy. In practice, amplitude changes in off-tape signals occur frequently, usually as a result of dropouts, which are common in, for example, magnetic recording tapes having high data packing densities. To decode Class IV partial response signals, it is known to employ comparators having fixed voltages which determine threshold levels. The thresholds are usually fixed mid-way between the center level (i.e., zero volts) and the absolute value of the normal outer envelope level for the partial-response signal. (The outer envelope levels are defined with reference to ternary eye patterns for partial-response signals; the ternary eye patterns are described by Kabal, et al., supra .). With fixed decoding thresholds, however, a dropout that causes a decrease in the peak-to-peak amplitude of a partial-response signal for the duration of some number of data bits can result in a logical "1" being erroneously decoded as a logical "0" during the dropout period even in the absence of noise. With electronic noise present, decoding errors may occur even with lesser signal reductions. U.S. Patent 4,399,474 suggests that threshold voltages employed in decoding Class IV partial-response signals should be automatically adjusted in accordance with changes in amplitude of the partial-response signals. The goal of the automatic adjustment is to change threshold voltages in proportion to scale changes in the levels of the partial-response signals in the absence of noise. In particular, the aforementioned patent discloses a system including first and second sample-and-hold circuits. The first sample-and-hold circuit provides an output which is updated each sampling period to represent the amplitude of the most recent sampled partial-response signal. The second sample-and-hold circuit provides an output that reproduces the output of the first sample-and-hold circuit only when the amplitude of a sampled partial-response signal equals or exceeds a predetermined fraction of the amplitude of the next-previously sampled partial-response signal. According to the aforementioned patent, threshold voltages are adjusted as a function of the output signals from the second sample-and-hold circuit; that is, the threshold voltages follow changes in the amplitude scale of partial-response signals. Although systems according to U.S. Patent 4,399,474 are effective in minimizing decoding errors due to shallow dropouts (i.e., ones in which the partial-response signal drops only a few dB), the system is complex and expensive to implement. In part, the difficulties of implementation arise because decoding requires sampling at high rates such as 100 MHz and, therefore, requires rapid operating cycles for the sample-and-hold circuits. Although such high-speed sample-and-hold circuits can be designed, they are difficult to manufacture. An object of the present invention is to provide a simplified system for decoding signals such as Class IV partial-response signals and, more particularly, to provide a system for automatically adjusting threshold levels when decoding partial-response signals so that decoding errors are minimized. A further object of the present invention is to provide an improved system which automatically compensates for the effects of partial dropouts and signal modulation when decoding partial-response signals. SUMMARY OF THE INVENTION According to one aspect, the invention provides a method for decoding partial-response signals wherein decision threshold levels are automatically adjusted in proportion to variations in the amplitude of a partial-response signal, the decoded level at a specified clock time having one binary state if the amplitude exceeds a positive threshold level and having another binary state if the amplitude is below the threshold level, characterised by: comparing the amplitude of the partial-response signal with the amplitude stored by a charge storage device being fedback; comparing the amplitude of the partial-response signal with a predetermined fraction of the amplitude of the feedback signal and providing an enable signal only when this comparison indicates that amplitude of the partial-response signal exceeds the predetermined fraction of the feedback signal; and, only when an enable signal is present, increasing the amplitude stored by the charge storage device when the amplitude of the partial-response signal exceeds the amplitude of the feedback signal and decreasing the amplitude stored by the charge storage device when the amplitude of the partial-response signal is less than the amplitude of the feedback signal. According to another aspect the invention provides a decoder for a partial-response signal, comprising a clock-controlled comparator for comparing the partial-response signals with a first threshold to provide a binary output, means for comparing the partial-response signal with a second threshold which is a fraction of the first threshold, and threshold adjusting means responsive when the binary output indicates that the partial response signal exceeds the second threshold to cause increase or decrease respectively of the first threshold according as a comparison made by the said comparator denotes that the partial-response signal is greater or less than the first threshold. In a preferred form the invention provides an apparatus for decoding a partial-response signal whose amplitude at specified clock times represents a first binary state if the amplitude exceeds a positive threshold and represents a second binary state if the amplitude is below the threshold level, comprising rectifying means for providing full-wave rectification of the partial-response signal, characterised by first comparator means connected to compare the amplitude of the full-wave rectified signal with the amplitude of a first feedback voltage signal stored by a charge storage device (39); second comparator means connected for comparing the amplitude of the rectified signal with a second feedback signal which is a predetermined fraction of the first feedback signal; enabling means for providing an enable signal only when the comparison provided by the second comparator means indicates that the amplitude of the rectified partial-response signal exceeds the amplitude of the second feedback signal; and charge pump means operative only in the presence of the enable signal for increasing the charge on the charge storage device when the amplitude of the rectified partial-response signal exceeds the first feedback signal and for decreasing the charge on the charge storage device when the amplitude of the rectified partial-response signal is less than the first feedback signal. BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 is a block diagram of a system according to the prior art for decoding Class IV partial-response signals; FIGURE 2 is a block diagram of a system for decoding partial-response signals, which system includes a threshold tracking system according to the present invention; FIGURES 3a through 3e are timing diagrams that illustrate operation of the system of FIGURE 2; and FIGURE 4 is a schematic diagram of a charge pump forming part of the system shown in FIGURE 2. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT FIGURE 1 shows a known system for decoding partial-response signals such as are obtained from a magnetic recording medium via a magnetic read head. This system employs comparators 1 and 2 which receive partial-response signals and threshold reference signals. In particular, a positive fixed threshold level is coupled to the comparator 1 and a negative fixed threshold level is coupled to the comparator 2. The comparators 1 and 2 are gated by clock pulses via a phase ajdusting circuit 4. In operation of the system of FIGURE 1, whenever one of the comparators is actuated a partial-response signal is greater than the positive threshold level or less than the negative threshold level at a clocking instant. When a partial-response signal is neither greater than the positive threshold reference nor less than the negative threshold reference at the clocking instant, neither comparator is actuated. In the system of FIGURE 1, an OR gate 6 provides a binary output whenever either comparator 1 or 2 outputs a signal. That is, the output of OR gate 6 is a binary "1" whenever a partial-response signal is either higher than the positive threshold level or lower than the negative threshold level. For all other levels of the partial-response signal, the output of OR gate 6 constitutes the partial response signal decoded in binary format. FIGURE 2 shows an improved system for decoding partial-response signals. In the system, a rectifier 13 provides full-wave rectification of off-tape partial-response signals. The operation of a suitable rectifier is described in terms of eye pattern diagrams in U.S. Patent No. 4,399,474. By full-wave rectification of the partial-response signals, all the signal amplitudes are converted into their absolute values. As is also shown in FIGURE 2, the rectified partial-response signals are provided to a first comparator 15 and to a second comparator 17. The other signals received by comparators 15 and 17 are feedback signals carried on a line 19. At the inverting input of comparator 17 series resistors 21 and 23 provide voltage division of the feedback signal. Normally, the two resistors have the same value and, therefore, comparator 17 receives a voltage which is one-half the feedback voltage. Comparators 15 and 17 receive analog inputs and provide binary output signals that depend upon the comparison between the inputs. In particular, the comparator 15 provides a logical "1" output if the amplitude of the partial-response signal at its non-inverting input exceeds the amplitude of the feedback signal at its inverting input; otherwise, the comparator provides a logical "0" output. Similarly, the comparator 17 provides a logical "1" output if the amplitude of the partial-response signal at its non-inverting input exceeds the amplitude of the voltage-divided feedback signal at its inverting input; otherwise comparator 17 provides a logical "0" output. As is further shown in FIGURE 2, output signals from the comparator 15 are provided to the data input of the D-type bistable (flip-flop) 31. The bistable 31 is gated to transfer data to its output whenever there is a positive-going transition of a clock pulse. Similarly, output signals from the comparator 17 are provided to the data input of a D-type bistable (flip-flop) 33 which is also gated by the clock pulses. As is also shown in FIGURE 2, the output of the bistable 31 is connected to a charge pump 37. The charge pump 37 is also connected to be selectively enabled, or disabled, by the output of the bistable 33. Finally, as shown by FIGURE 2, the output of charge pump 37 is connected to one node 38 of a capacitor 39 whose other node is grounded. In practice, capacitor 39 is generally linear, which is to say that the voltage across it is linearly proportional to its accumulated charge. In practice, capacitor 39 normally has a value of a few thousand picofarads. In this embodiment, the conductor 19 extends from node 38 to provide voltage feedback to the comparators 15 and 17. Preferably, a unity-gain buffer 41 is interposed in line 19 to prevent discharge of the capacitors by the resistors 21 and 23. The voltage at the output of unity-gain buffer 41 equals the voltage across the capacitor 39 and, in the following, is referred to as the threshold tracking voltage V T . FIGURES 3a to 3e are timing diagrams that illustrate the operation of the system of FIGURE 2. FIGURE 3a shows a periodic train of clock pulses having generally rectangular shape. The arrows indicate the rising edges of the pulses; those edges gate the data transfer devices. Typically, the period of the clock pulses is about ten nanoseconds in applications involving high-density magnetic tape recordings. The sampling times t o , t₁......t n coincide with the rising edges of the clock pulses. Circuits to generate suitable clock pulses are described in U.S. Patent 4,399,474. It may be noted that the rising edges of the clock pulses coincide with the foci or crossing times of the ternary eye patterns for Class IV partial-response signals. In FIGURE 3b, the heavy curve indicates an off-tape partial response signal V I such as may occur upon replay of digitally-encoded information recorded on magnetic tape. It should be noted that the off-tape signal, V I , has been full-wave rectified and, therefore, displays no negative voltage values. The lighter line in FIGURE 3b illustrates the tracking voltage, V T , as a function of time. It may be noted that the initial value of the tracking voltage (i.e., the amplitude of V T at time t o ) is arbitrary. For purposes of understanding the operation of the system of FIGURE 3, changes in the amplitude of the tracking voltage are important; its initial value is not. The dashed line in FIGURE 3b is drawn generally parallel to the tracking voltage V T and has half of its amplitude. In terms of FIGURE 2, the dashed line depicts the "decision" voltage, V d , at the input to second comparator 17. FIGURE 3c shows the output signals from the bistable 33. These output signals are generally rectangular pulses which begin and end at the sampling times. More particularly, the output signals from the bistable 33 have zero amplitude whenever a sampled off-tape partial-response signal V I has an amplitude less than one-half the tracking voltage, V T , and the output signal from the bistable 33 have a positive amplitude (i.e., binary level "1") when a sampled off-tape signal V I has an amplitude greater than one-half the tracking voltage V T . For example, the amplitude of the output of the bistable 33 is logical "0" from sampling times t₁ to t₃ and from sampling times t₅ to t₆. Also, the amplitude of the output from the bistable 33 is a logical "1" from sampling times t o to t₁ and from sampling times t₃ to t₅. It should be noted that the output signals from the bistable 33 are, in fact, decoded partial-response signals where the decoding has been done relative to the decision voltage V d . FIGURE 3d shows the output signals from the bistable 31. Again, the output signals are generally rectangular pulses which begin and end at the sampling times. The output signals from the bistable 31 have zero amplitude when a sampled off-tape partial-response signal V I has an amplitude less than the tracking voltage V T , and have a positive amplitude when a sampled off-tape signal has an amplitude greater than the tracking voltage V T . For example, the amplitude of the output of the bistable 31 is logical "0" from sampling times t₁ to t₃ and from sampling times t₅ to t₈, and is a logical "1" from sampling times t o to t₁ and from sampling times t₉ to t₁₀. FIGURE 3e shows the output current from charge pump 37 at the sampling times. As previously mentioned, output current from the charge pump is provided only when the charge pump is enabled by a positive output from the bistable 33. Thus, in terms of the timing diagrams, the charge pump 37 provides an output only when the amplitude of the off-tape signal V I exceeds one-half the amplitude of tracking voltage V T . During such times, the output current from charge pump 37 is either positive or negative. Positive current is provided by the pump 37 only when the amplitude of the off-tape signal V I exceeds the tracking voltage V T , and negative current is provided only when the amplitude of the off-tape signal V I is less than tracking voltage V T . In practice, the positive and negative currents have values of a few milliamps. Finally with regard to the timing diagrams, it should be understood that the output currents from charge pump 37 cause changes in the tracking voltage V T . This is because current flow to the capacitor 39 of FIGURE 2 changes the voltage across the capacitor and, hence, changes tracking voltage V T . When there is positive current from charge pump 37, as between sampling times t o and t₁ and between sampling times t₃ and t₅, the tracking voltage V T increases. Conversely, when there is negative current from charge pump 37, as between sampling times t₆ and t₉, tracking voltage V T decreases. When there is no positive or negative current from charge pump, as between sampling times t₁ and t₃, the tracking voltage V T remains constant. FIGURE 4 shows one embodiment of charge pump 37. In this embodiment, the charge pump includes current sources 51 and 53 connected to constant voltage sources V cc and -V cc respectively. The charge pump 37 also includes a gating network constituted by AND gates 55 and 57 which are connected to receive the enable signals from the bistable 33 as well as the output signals from the bistable 31 which is inverted at the input to the AND gate 57. The outputs of the AND gates 55 and 57 control transistor switches 61 and 63 respectively. Preferably, the circuit FIGURE 4 is partly implemented with emitter-coupled transistor logic for the sake of operating speed. In the operation of the charge pump shown in FIGURE 4, AND gates 55 and 57 can provide an output only in the presence of binary "1" to enable signals from the bistable 33. The one of the AND gates which is operative in the presence of an enable signal depends upon whether the bistable 31 provides a binary "1" or binary "0" output during such times. Recause of the inversion at the input to AND gate 57, only one of the AND gates 55 or 57 can be operative to produce a binary "1" output during the period of an enable signal from the bistable 33. When AND gate 55 is operative, switch 61 is closed to connect the current source 61 to the capacitor 39, thereby to increase the charge on the capacitor. When AND gate 57 is operative, the switch 63 is closed to connect the current source 63 to capacitor 39, thereby to decrease the charge on the capacitor. Although a preferred embodiment of the present invention has been illustrated and described, various modifications, alternatives and equivalents thereof will become apparent to those skilled in the art. For example, it should be recognized that the comparator 15 and the bistable 31 can be integrated into a single device and that, likewise, the comparator 17 and bistable 33 can be integrated into a single device. As another example of an alternative, it should be noted that charge pump 37 can also be implemented as an integrator with an enable control. Furthermore, although the present invention is usable for reducing errors in decoding playback signals from magnetic recordings, it will be apparent to those skilled in the art that the invention can be applied in connection with other types of partial-response signal decoding systems and to devices other than magnetic recorders.

Claims: A method for decoding partial-response signals, wherein decision threshold levels are automatically adjusted in proportion to variations in the amplitude of a partial-response signal, the decoded level at a specified clock time having one binary state if the amplitude exceeds a positive threshold level and having another binary state if the amplitude is below the threshold level, characterised by: comparing the amplitude of the partial-response signal with the amplitude stored by a charge storage device being fedback; comparing the amplitude of the partial-response signal with a predetermined fraction of the amplitude of the feedback signal and providing an enable signal only when this comparison indicates that the amplitude of the partial-response signal exceeds the predetermined fraction of the feedback signal; and, only when an enable signal is present, increasing the amplitude stored by the charge storage device when the amplitude of the partial-response signal exceeds the amplitude of the feedback signal and decreasing the amplitude stored by the charge storage device when the amplitude of the partial-response signal is less than the amplitude of the feedback signal. A method according to claim 1 wherein a binary signal is provided as a result of the comparison of the partial-response signal with the predetermined fraction of the feedback signal, which binary signal represents a decoded partial-response signal. A method according to claim 1 wherein the predetermined fraction is one-half. An apparatus for decoding a partial-response signal whose amplitude at specified clock times represent a first binary state if the amplitude exceeds a positive threshold and represents a second binary state if the amplitude is below the threshold level, comprising rectifying means (13) for providing full-wave rectification of the partial-response signal; characterised by first comparator means (15) connected to compare the amplitude of the full-wave rectified signal with the amplitude of a first feedback voltage signal stored by a charge storage device (39); second comparator means (17) connected for comparing the amplitude of the rectified signal with a second feedback signal which is a predetermined fraction of the first feedback signal; enabling means (55, 57) for providing an enable signal only when the comparison provided by the second comparator means indicates that the amplitude of the rectified partial-response signal exceeds the amplitude of the second feedback signal; and charge pump means (37) operative only in the presence of the enable signal for increasing the charge on the charge storage device when the amplitude of the rectifed partial-response signal exceeds the first feedback signal and for decreasing the charge on the charge storage device when the amplitude of the rectifed partial-response signal is less than the first feedback signal. A system according to claim 4 wherein the first and second comparator means (15, 17) comprise comparators which provide binary output signals. A system according to claim 4 and including a first binary data transfer means (31) connected to receive the output of the first comparator means and a second binary data transfer means (33) connected to receive the output of the second comparator means. A system according to claim 6 wherein the enabling means comprises a gating network (55, 57) that is connected to the second binary data transfer means (33). A system according to claim 7 wherein the gating network (55, 57) is also connected to receive the output signal from the first binary data transfer means (31). A system according to any of claims 6 to 8, further including a clock means for generating periodic clock pulses which determine sampling times for the partial-response signal, said clock means being connected to the first and second binary data transfer means (31, 33) to control data transfer from their inputs to their outputs. A system according to any of claims 4 to 9 wherein the charge pump means comprises a current source (51) for selectively increasing the charge on the charge storage device and a current drain (53) for selectively decreasing the charge on the charge storage device. A system according to any of claims 4 to 10 wherein the charge storage device (39) is a capacitor. A decoder for a partial-response signal, comprising a clock-controlled comparator (15) for comparing the partial-response signal with a first threshold, means (17) for comparing the partial-response signal with a second threshold which is a fraction of the first threshold to provide a binary output, and threshold adjusting means (33, 37, 39, 41, 19) responsive when the binary output indicates that the partial-response signal exceeds the second threshold to cause increase or decrease respectively of the first threshold if a comparison made by the said comparator (15) denotes that the partial-response signal is greater or less than the first threshold. A decoder according to claim 12 wherein the threshold adjusting means comprises an integrator or accummulator (39) for storing a signal which is incremented or decremented when the partial-response signal is detected at specified clock times to exceed the second threshold. A decoder according to claim 12 or 13, wherein the comparator (15) and the said means (17) for comparing receive rectified partial response signals for comparison thereof with the first threshold and second threshold respectively.

Inventors: SMIDTH PETER, SMIDTH, PETER
Applicants: AMPEX SYSTEMS CORP, AMPEX SYSTEMS CORPORATION
Application year: 1989
Main classification: G11B20
IPC codes: H03K5, H04L25, G11B20