BICMOS positive supply voltage reference

Abstract: The present invention provides a voltage reference level using a bipolar output transistor to provide a reference voltage on a reference output line. A control circuit is used for varying the current to the base of the output transistor in response to the load on the reference output line. In addition, the control circuit provides the reference level to the output transistor. The MOS control circuit and the bipolar output transistor are fabricated on the same chip using a BICMOS process. The voltage reference provided by the control circuit is derived from a voltage level provided by a resistor coupled between the positive voltage supply and a current source.

Description: The present invention relates to BICMOS voltage reference circuits, and in particular to such reference circuits for EPROMs. A typical prior art positive voltage reference is shown in Fig. 1. The voltage reference is provided on a line 10 from a bipolar transistor 12 which is coupled to a positive voltage supply VCC. A current source 14 provides the necessary current. Transistor 12 is biased by a resistor 16 coupled to voltage supply VCC. A second current source 18 provides the appropriate current to the base of transistor 12 to provide the appropriate voltage level at reference line 10. Fig. 2 shows a typical use for such a reference generator circuit 20 for an ECL memory. Reference line 10 is connected through resistors 22 in row decode circuits 24 to row lines 0, 1 and 2, respectively. As can be seen, with a large number of row lines connected, the circuit of Fig. 1 will reach the maximum amount of current of current source 14 and thus pull down the voltage at reference line 10. This phenomena is shown in Fig. 3 during a switching period 26 in which a row line 1 goes high but a row line 0 has not yet discharged, causing the reference line to give a false indication of a high value on row line 2. If the current source 14 in Fig. 1 is split among enough row lines, the amount of current to each row line will decrease, thus lowering the voltage level. Without sufficient current to quickly discharge a deselected row, the speed of the address access is slowed. One solution is to add a discharge circuit to discharge the capacitance of a row line and thus limit the amount of current required from the voltage reference circuit. However, this adds a considerable amount of circuitry since a separate discharge circuit is required for each row line. Such a discharge circuit is shown on page 108-109 of the 1983 IEEE International Solid-State Circuits Conference Digest of Technical Papers. The present invention is defined by claim 1. The combination of features set forth in its preamble are known from EP-A-0,113,865. The present invention provides a voltage reference level using a bipolar output transistor to provide a reference voltage on a reference output line. A control circuit is used for varying the current to the base of the output transistor in response to the load on the reference output line. In addition, the control circuit provides the reference levels to the output transistor. The MOS control circuit and the bipolar output transistor are fabricated on the same chip using a BICMOS process. The voltage reference provided by the control circuit is derived from a voltage level provided by a resistor coupled between the positive voltage supply and a current source. In a preferred embodiment, the control circuit consists of MOS transistors arranged to control the output transistor base current in response to the output current of the reference circuit and to simultaneously hold the reference line output at the reference voltage level. In one embodiment, a PMOS transistor has its source and drain coupled between the reference output and the base of the output transistor. Thus, the base current of the output transistor is coupled to the reference output to provide tracking. A second embodiment uses a current mirror configuration. A capacitor is coupled between the voltage supply and the reference line output to counteract oscillation. A resistor is coupled to the base of the output bipolar transistor to provide biasing. For a further understanding of the objects and advantages of the invention, reference should be made to the ensuing description taken in conjunction with the accompanying drawings. Fig. 1 is a circuit diagram of a prior art voltage reference; Fig. 2 is a block diagram of a prior art ECL memory array using a reference generator circuit; Fig. 3 is a diagram showing the voltage effects of the selection of multiple rows on a voltage reference circuit according to the prior art; Fig. 4 is a diagram of a reference circuit according to the present invention; Fig. 5 is a diagram of first embodiment of the reference circuit of Fig. 4; and Fig. 6 is a diagram of a second embodiment of the reference circuit of Fig. 4. Fig. 4 shows a voltage reference circuit according to the present invention. An output reference line 28 is coupled to the collector of a bipolar output transistor 30. The collector of transistor 30 is coupled through a capacitor 32 to positive voltage supply VCC. The base of transistor 30 is coupled by a resistor 34 to a ground reference level. A control circuit 36 is connected to the collector and base of transistor 30 and connects reference line 28 to a voltage reference level setting circuit which includes a resistor 38 and a current source 40. Control circuit 36 not only supplies the voltage reference from resistor 38 and current source 40 to reference line 28, but also controls the current to the base of transistor 30 in response to the load on line 28. Resistor 34 is used to bias transistor 30 to the proper operating level. Capacitor 32 is added in order to counteract the possibility of oscillation. Fig. 5 shows a first embodiment of the control circuit 36 of Fig. 4. As can be seen, control circuit 36 includes transistors 42 and 44. Resistor 38 generates the required voltage level that is needed and is referenced to the positive supply VCC. A PMOS transistor 44 generates the proper gate voltage for PMOS transistor 42 to ensure that the source of transistor 42 will be equal to the required reference voltage. Transistor 42 also sets the DC operating current and supplies the base current to bipolar transistor 30 during transient mode high current operation. Transistors 44 and 42 form a current mirror to drive the base of transistor 30. Thus, the current I₁ in current source 40 is reflected as current I₂ into the base of transistor 30. The value of resistor 34 is chosen to provide conduction by transistor 30 at the desired level. If the voltage on line 28 rises due to an increased load, more current is supplied through PMOS transistor 42 to the base of transistor 30 which in turn will try to pull the reference voltage on line 28 back down. If the reference voltage on line 28 decreases in voltage, less current flows through PMOS transistor 42, decreasing the base current into transistor 30, which allows the voltage reference level to rise. The DC current flowing through transistor 42 and resistor 34 biases transistor 30 at its proper operation level. The design of Fig. 5 has the advantage of a low DC operating current with a very high transient mode capability. Thus, little current is used in a steady state operation, but a large amount of current can be supplied for switching voltage levels. Fig. 6 shows an alternate version of the circuit of Fig. 4. Again, resistor 38 generates the voltage reference, which is presented to the gate of PMOS transistor 46. Transistor 46 is coupled to another PMOS transistor 48, which has a gate which will try to equal the gate of transistor 46. Current is supplied to transistors 46 and 48 by a transistor 50, which is one leg of a current mirror consisting of transistors 50 and 52. The other leg of the current mirror includes a current source 54. Transistors 46 and 48 form a differential amplifier which drives the base of transistor 30. The differential amplifier combined with the gain of transistor 30 will force the gate of transistor 48 to the reference level. If the reference voltage on line 28 raises, less current will flow through transistor 48, and more current will flow through transistor 46 to the base of transistor 30, which will in turn try to pull the voltage reference level on line 28 down. To equalize the load at the drain of transistors 46 and 48, a diode 56 is added between the drain of transistor 48 and the negative voltage reference to correspond to the diode drop of the base-emitter junction of transistor 30, which is in parallel with resistor 34. A resistor 58 is added in parallel with diode 56 to correspond to resistor 34. Transistors 46 and 48 are long channel length devices in order to give a constant current reference level for a varying drain to source voltage level. This is possible because a long channel length results in the gate to source voltage (Vgs) leveling off to become relatively constant as the drain current increases or the drain to source voltage varies. The embodiment of Fig. 6 has a higher DC operating current than the embodiment of Fig. 5, but the reference voltage is more accurate. As will be evident to those of skill in the art, the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For example, a different circuit could be used to bias transistor 30, bipolar transistor 30 could be an NMOS transistor, or resistor 38 could be replaced with a diode. Accordingly, the disclosure of the preferred embodiments of the invention is to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.

Claims: A reference circuit for producing a first reference voltage level (REF) from a positive voltage supply (V cc ) the reference circuit having: an output transistor (30) which has a control electrode and an output electrode for providing said first reference voltage level at an output (28); voltage level means (38, 40), coupled to said positive voltage supply (V cc ), for establishing a second reference voltage level, characterized in that: said voltage level means (38, 40) includes control circuit means (36), coupled to said output (28) and to the control electrode of said output transistor (30) for providing at said output (28) said first reference voltage level (REF) from said second reference voltage level whereby the current to said control electrode increases in response to an increase in said first reference voltage level (REF) and the current to said control electrode decreases in response to a decrease in said first reference voltage level (REF). The reference circuit of claim 1 wherein said voltage level means comprises: a first resistor (38) coupled to said positive voltage supply; and a first current (40) source coupled to said resistor to produce a first voltage level at a node between said first resistor and said first current source. The reference circuit of claim 1 wherein said output transistor (30) is a bipolar transistor. The circuit of claim 1 further comprising a capacitor (32) coupling said output electrode to said positive voltage supply. The circuit of claim 1 further comprising a biasing resistor (34) coupling the control electrode of said output transistor to a voltage reference negative with respect to said positive voltage supply. The circuit of claims 2 and 3 wherein said control circuit means comprises: a first MOS transistor (44) having a first output electrode coupled to said first resistor (38), a second output electrode coupled to said first current source (40) and a gate coupled to said node; and a second MOS transistor (42) having a first output electrode coupled to said reference circuit output (28), a second output electrode coupled to said base of said bipolar transistor (30) and a gate coupled to said gate of said first MOS transistor. The circuit of claim 6 wherein said MOS transistors are PMOS transistors. The circuit of claim 1 wherein said control circuit means comprises a differential pair of first (46) and second (48) MOS transistors, said first MOS transistor having a gate coupled to said voltage level means and a first output electrode coupled to said base of said bipolar transistor (30), said second MOS transistor having a gate coupled to said reference circuit output (28). The circuit of claim 8 further comprising a current mirror circuit (50, 52) having a first leg coupled to second output electrodes of said first and second MOS transistors and a second leg coupled to a second current source (54).

Inventors: BOWMAN TERRANCE L, SMITH DOUGLAS D, BOWMAN, TERRANCE L., SMITH, DOUGLAS D.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1989
Main classification: G05F3
IPC codes: H01L27, G05F3, H01L21