Digital memory system

Abstract: A digital memory system of the type which includes an amplifier transistor (22,24) connected to provide an amplified bitline signal corresponding to the state of a selected memory cell (12). A bitline pullup transistor (18,20) is positioned to function as a bitline current source and as a load device for the amplifier transistor. The amplifier transistor is connected between the pullup transistor and the bitline and an output node positioned between the pullup and amplifier transistors provides the amplified bitline signal corresponding to the state of a selected memory cell.

Description: The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract No. F33615-85-C-1797 awarded by the Air Force Wright Aeronautical Laboratories. FIELD OF THE INVENTION This invention relates to digital memory systems and, more specifically, to a high speed static random access memory (RAM) system. BACKGROUND In high speed static RAM systems such as, for example, one disclosed in U.S. Patant No. 4,665,508 assigned to the assignee of the present invention, the typical combination of a high bitline capacitance and a relatively low level of bitline charging current necessitates a low bitline voltage swing. Accordingly, conventional static RAM designs have employed relatively complex and power consumptive circuitry to provide sufficient signal magnification. Even so, sense amplifier gain has been a limiting factor in the speed of memory operations, e.g., reading data out of memory cells. That is, for a given level of amplification a minimum bitline swing voltage must be provided in order to develop a signal of sufficient magnitude to permit proper operation of adjoining circuitry. The response time, t, for developing a voltage swing, V, is proportional to the voltage, i.e., V = It/C where I is the bitline charging current and C is the bitline capacitance. The desire in the art is to minimize the response time in order to provide higher speed memory operation. In the process of increasing the density of static RAM devices it is also desirable to minimize power dissipation as well as the area occupied by the circuit components. In EP-A-0 239 021, there is disclosed a semiconductor memory device having memory cells in a plurality of columns connected to pairs of bitlines. Each bitline receives current from a pullup transistor. Each pair of bitlines is connected through a column transfer gate operated by column address signals to a sense amplifier and to a write circuit including a clamp circuit for clamping a driving level. In JP-A-58-179990 there is described a sense amplifying circuit having a pair of cross-connected FET's with transistor current sources as loads across which the amplified output signals are developed. The sources and gates of the cross-connected FET's are connected to the outputs of two other FET amplifiers, to the gates of which two lines receiving complementary signals to be amplified are respectively connected. JP-A-61-208693 discloses a 6-transistor memory cell for a random access memory using MESFET's. Single transistor current sources are respectively connected to two bitlines which are connected to ground through respective diodes, and to which the memory cell is connected through its gate transistors that are controlled by a word line signal. In accordance with a first aspect of the present invention there is provided a digital memory system comprising: at least a first column of memory cells; a plurality of word lines respectively connected to the memory cells to enable electrical signals to be applied to a selected memory cell; a first bitline connected to each memory cell in the column for electrical signals determining the state of the selected cell; a bitline pullup transistor connectable to a source of electrical power and connected to function as a current source for the bitline and sense amplifying means connected to the bitline to provide an output signal corresponding to the state of the corresponding memory cell characterised in that the sense amplifying means comprises a transistor having its controlled current path connected between the bitline and the bitline pull up transistor 18 to provide at its connection to the bitline pullup transistor a signal corresponding to the state of a selected memory cell; and in that the system further comprises biasing means for biasing the gate of the transistor of the sense amplifying means so that the bias applied is low when the potential on the bitline is high and the bias is high when the potential is low. In a general form the system includes a column of memory cells and a plurality of word lines connected for selecting a memory cell. A bitline is connected to each memory cell in the column and a bitline pullup transistor having first, second and third terminals is arranged to form a current source at the second terminal. First and second source/drain electrodes of an amplifier transistor are connected to the second terminal of the pullup transistor and the bitline respectively. The gate electrode of the amplifier transistor is connected to receive a bias voltage. An amplified bitline signal corresponding to the state of a selected memory cell is available at an output node between the pullup and amplifier transistors. The preferred embodiment of the memory system includes first and second bitlines connected to each memory cell in the column. A bitline pullup transistor and an amplifier transistor are associated with each bit line as described above. An output node between the first pullup and amplifier transistors provides an amplified bitline signal corresponding to the state of a selected memory cell while a second output node between the second pullup transistor and the second amplifier transistor provides an amplified bitline signal corresponding to the inverted state of a selected memory cell. According to a second aspect of the present invention there is provided a digital memory system comprising at least a first column of memory cells, a plurality of word lines respectively connected to the memory cells to enable electrical signals to be applied to a selected memory cell in the first column, first and second bitlines conected to each memory cell in the first column for electrical signals determining the state of the selected memory cell, first and second bitline pullup transistors connectable to a source of electrical power and respectively arranged to provide currents for the first and second bitlines, and sense amplifying means connected to the first and second bitlines for providing at least one output signal corresponding to the state of the selected memory cell, characterised in that the sense amplifying means comprises two transistors, the first transistor having its controlled current path connected between the first bit line pullup transistor and the first bit line and its gate connected to the second bit line, the second transistor having its controlled current path connected between the second bit line pullup transistor and the second bit line and its gate connected to the first bit line; and the at least one output signal is provided at at least one of the connections of the transistors of the sense amplifying means to the bitline pullup transistors. In accordance with a third aspect of the present invention there is provided a method for enhancing high speed operation of a static random access memory system including at least a first column of memory cells, a plurality of word lines and bitlines connected for memory cell selection, a bitline pullup transistor and a sense amplifier transistor connected to a bitline, the method comprising the steps of feeding a charging current from the bitline pullup transistor to the bitline (BL₁) through the sense amplifier transistor, biasing the gate of the sense amplifier transistor with a low bias when the potential on the bitline is high and with a high bias when the potential on the bitline is low, and deriving a signal corresponding to the state of the selected memory cell from the connection of the sense amplifier transistor to the bitline pullup transistor so as to isolate the capacitance of the bitline (BL₁) from the associated bitline pullup transistor dependent on the low or high bias. BRIEF DESCRIPTION OF THE DRAWINGS The invention may best be understood by reference to the detailed description when read in conjunction with the following drawing, wherein: Figure 1 provides a partial schematic view of a high speed static RAM device according to the present invention; Figure 2 illustrates a memory device based on a conventional sense amplifier design; Figure 3 displays computer simulation results illustrating performance characteristics of a static RAM device constructed according to the invention; and Figure 4 displays computer simulation results illustrating performance characteristics of a static RAM device based on a conventional sense amplifier design. Similar reference numbers are used in various figures to designate similar features and components. Certain preferred embodiments of the invention are disclosed herein. However, it should be appreciated that the specific materials, component arrangements and memory sizes disclosed herein are merely illustrative. DESCRIPTION OF THE PREFERRED EMBODIMENT If the bitline current could be used to generate a sufficiently large signal, a simpler, lower power, faster system would be available. However, as already noted, the speed requirements of high density memories preclude obtaining the full amplitude signal directly from the bitlines. According to the present invention a merged bitline pullup - sense amplifier circuit provides an impedance transformation, i.e., a current to voltage conversion of the bitline signal. This results in a highly amplified voltage output signal indicative of the state of a selected memory cell. Figure 1 is a partial schematic view of a high speed static RAM device 10 comprising a merged bitline pullup - sense amplifier circuit in conjunction with an exemplary column of 64 memory cells 12. Although the device 10 is presented in simplified form to more clearly describe the invention, it is to be understood that the device includes numerous additional components present in conventional static RAM architecture such as row and column address circuitry, decode logic and output circuitry. See U.S. Patent No. 4,665,508. By way of illustration, the device 10 may be a 4K GaAs MESFET Static RAM containing 4,096 memory cells organized in a 64 row by 64 column array. Decoding may be implemented with a single level of 64 six-input NOR gates. The decoded 6-bit row and column addresses enable the word lines and select a particular column of memory cells. Data are sequentially written into or read out of selected memory cells in accordance with the state of the write enable, data in and chip select signals. The memory cells 12 illustrated in Figure 1 may each be, for example, of a conventional six transistor design including two cross-coupled switching transistors, two load transistors and a pair of pass transistors. A plurality of word lines WL i and bitlines BL i are connected for memory cell selection. As illustrated in Figure 1, bitlines BL₁ and BL₂ are coupled to the memory cells 12 along opposing sides of the column. The bitlines are coupled to a power supply line V DD by bitline pullup - sense amplifier circuitry which includes a pair of dual function pullup/load transistors 18 and 20 as well as a pair of amplifier transistors 22 and 24 each positioned between a bitline and one of the dual function transistors 18 or 20. An amplifier output node 28 or 30 is located between each dual function transistor 18 or 20 and an adjacent amplifier transistor 22 or 24. The amplifier transistors 22 and 24 are positioned to isolate the bitline capacitance from the output nodes 28 and 30. With this isolation each transistor 18 and 20 serves as the load to an adjacent amplifier transistor. The arrangement enables a very fast amplified output to be developed at the output nodes 28 and 30. As a minimum the circuit only requires four devices to perform both bitline charging and amplification of the otherwise low level bitline signals. In the preferred embodiment the gate electrode 40 of each amplifier transistor 22 and 24 is connected to an opposing bitline and all four transistors 18, 20, 22 and 24 are depletion mode MESFETs. The transistors 18 and 20 are each arranged with the drain electrode coupled to V DD and the gate tied to the source electrode thereby providing a current source. To further limit the high level of the bitline swing voltage, a clamping diode 42 may be serially connected between each bitline and a reference potential 44. A computer simulation has been carried out to compare the performance of the device 10 with the memory device 50 of Figure 2, which is based on a conventional sense amplifier design. The device 50 also includes the clamping diodes 42 of the present invention in order to obtain similar voltage swings, this permitting a more objective evaluation of the merged bitline - pullup circuitry of the present invention. The comparison was performed by reading data out of two adjacent memory cells 12 in a column. The adjacent cells were initialized to opposite states in order to require reversal of voltages in bitlines BL₁ and BL₂. That is, simultaneously switching WL₁ and WL₂ reverses the memory cell selection and causes the bitlines to charge to opposite states. The bitlines were assumed to each include 0.3 pF of capacitance. The simulation results based on the designs of devices 10 and 50 are illustrated in Figures 3 and 4, respectively. In each case the voltage changes in the bitlines BL₁ and BL₂ and the word linear WL₁ and WL₂ are plotted along with the amplified Sense Out waveforms SO. The output waveforms of the device 10, designated in Figure 3 as SO(28) and SO (30), exhibit faster and more symmetrical rise and fall times than those of the device 50. For example, lapsed time between the word line and sense out cross points is approximately 0.1 ns shorter for the device 10. The rise time of the device 10 sense out signal, e.g., to 90 percent of the peak to peak value, is also much shorter. Furthermore, in modeling the response time V DD for device 50 was 2.7 volts while V DD for the device 10 was only 2.2 volts. Nevertheless, the output signal of the device 10 was much larger, i.e., approximately 0.5 volts. The combination of faster rise time and higher gain provide a relatively larger output signal for a given response time. Thus the device 10 is capable of providing output signals of acceptable magnitude faster than the device 50. For example, the device 10 provides a sense out signal of 0.5 volts (as measured from the sense out cross points) in approximately 0.1 ns. In comparison, the device 50 requires greater than a 0.5 ns rise time to develop a 0.5 volt output. Thus higher speed memory operation is attainable with the merged bitline - pullup circuitry of the present invention. A corresponding method for enhancing high speed static random access memory operation comprises the step of isolating the capacitance of a bitline from the associated bitline pullup device. In a preferred form the pullup device is positioned to function as the sense amplifier load as well as the bitline current source. The result is faster and simpler memory operation. ADVANTAGES AND MODIFICATIONS A feature of the preferred embodiment circuit 10 is that the gate electrode 40 of each amplifier transistor 22 and 24 is connected to an opposing bitline. Although the gate bias of each amplifier transistor could be provided with a DC voltage, the cross coupled scheme of Figure 1 is advantageous for three reasons. First, the coupling eliminates the need for providing an external voltage bias. Second, the amplified signal response times at the output nodes 28 and 30 are nearly symmetrical in comparison to the bitline response. Third, the amplifier sensitivity is approximately doubled because the gate to source voltage of each amplifier transistor is essentially the difference between the two bitline voltages. In addition to requiring fewer components than conventional memory devices, the designs disclosed herein are more power efficient because the same current that charges the bitlines provides the output signal through a simple impedance transformation. In alternative embodiments of the invention a single bitline, e.g., BL₁, in combination with one pullup/load transistor 18 and one amplifier transistor 22 provide sufficient gain for RAM operation although a longer response time may be required in order to develop a desired sense out voltage response. The advantages of this embodiment are lower power dissipation and fewer components. Certain embodiments of the invention have been described. Various other arrangements and configurations of the disclosed embodiments and components thereof will be apparent. For example, while GaAs components may be preferred for high speed operation, other semiconductor materials such as silicon are applicable. To realize advantages of the design principles disclosed herein semiconductor components are not required. While it is preferred that the transistors 18, 20, 22 and 24 be of equal size, this is not necessary. Nor do the transistors have to be MESFETs. They may, for example, be replaced with MOS, bipolar or other types of devices. All of the devices 18 - 24 could be high electron mobility transistors (HEMTs). Furthermore, designs incorporating enhancement mode devices are within the scope of substitutions, although these may not provide satisfactory performance. Accordingly, the scope of the invention is only to be limited by the claims which follow.

Claims: A digital memory system comprising: at least a first column of memory cells (12); a plurality of word lines (WL) respectively connected to the memory cells to enable electrical signals to be applied to a selected memory cell; a first bitline (BL1) connected to each memory cell in the column for electrical signals determining the state of the selected cell; a bitline pullup transistor (18) connectable to a source of electrical power and connected to function as a current source for the bitline; and sense amplifying means connected to the bitline to provide an output signal corresponding to the state of the corresponding memory cell characterised in that the sense amplifying means comprises a transistor (22) having its controlled current path connected between the bitline and the bitline pull up transistor (18) to provide at its connection to the bitline pullup transistor a signal corresponding to the state of a selected memory cell; and in that the system further comprises biasing means for biasing the gate of the transistor of the sense amplifying means so that the bias applied is low when the potential on the bitline is high and the bias is high when the potential is low. A digital memory system comprising at least a first column of memory cells (12), a plurality of word lines (WL) respectively connected to the memory cells to enable electrical signals to be applied to a selected memory cell (12) in the first column, first and second bitlines (BL1,BL2) connected to each memory cell (12) in the first column for electrical signals determining the state of the selected memory cell (12), first and second bitline pullup transistors (18,20) connectable to a source of electrical power and respectively arranged to provide currents for the first and second bitlines (BL1,BL2), and sense amplifying means (22,24) connected to the first and second bitlines (BL1,BL2) for providing at least one output signal corresponding to the state of the selected memory cell (12), characterised in that the sense amplifying means comprises two transistors (22, 24), the first transistor (22) having its controlled current path connected between the first bit line pullup transistor (18) and the first bit line (BL1) and its gate (40) connected to the second bit line (BL2), the second transistor (24) having its controlled current path connected between the second bit line pullup transistor (20) and the second bit line (BL2) and its gate (40) connected to the first bit line (BL1); and the at least one output signal is provided at least at one of the connections of the transistors of the sense amplifying means to the bitline pullup transistors. A system according to claim 1 or claim 2 characterised in that the or each pullup transistor (18,20) is a field effect transistor with its source or drain electrode connected to its gate electrode. A system according to any one of claims 1, 2 and 3 characterised in that the or each transistor of the sense amplifying means has source and drain terminals connected to the ends of a channel forming its controlled current path and a gate as the control electrode for controlling that current. A system according to any one of the preceding claims characterised in that the or each bitline pullup transistor acts as the load for the corresponding transistor of the sense amplifying means. A system according to any one of the preceding claims, characterised in that the or each bitline (BL₁,BL₂) includes a terminal connectable to a reference potential; there being provided for the or each bitline a diode (42) serially connected between the terminal of the bitline and the reference potential. A system according to any one of the preceding claims, characterised in the pullup transistor (18,20) and the first or second transistor (22,24) are gallium arsenide MESFETs. A system according to any one of the preceding claims, characterised in that the memory cells are static random access memory cells. A method for enhancing high speed operation of a static random access memory system including at least a first column of memory cells (12), a plurality of word lines (WL) and bitlines (BL) connected for memory cell selection, a bitline pullup transistor (18) and a sense amplifier transistor (22) connected to a bitline (BL₁), said method comprising the steps of feeding a charging current from the bitline pullup transistor (18) to the bitline (BL₁) through the sense amplifier transistor (22), biasing the gate of the sense amplifier transistor with a low bias when the potential on the bitline is high and with a high bias when the potential on the bitline is low, and deriving a signal corresponding to the state of the selected memory cell from the connection of the sense amplifier transistor to the bitline pullup transistor so as to isolate the capacitance of the bitline (BL₁) from the associated bitline pullup transistor (18) dependent on the low or high bias. A method according to claim 9, characterised in that in the step of feeding the charging current to the bitline is accomplished by connecting the bitline pullup transistor (18) so as to function as the load of the sense amplifier transistor (22) as well as the bitline current source. A method according to claim 9, wherein the step of feeding the charging current to the bitline is accomplished by connecting the sense amplifier transistor (22) in series between the bitline pullup transistor (18) and the bitline (BL₁). A method according to any of claims 9 to 11, in which the sense amplifier transistor (22) is an FET and the method is applied to the system further having a second bitline (BL₂) associated to the first column of memory cells for memory cell state signals, a second bitline pullup transistor (20) and a second sense amplifier transistor (24), connected between the second bit line pull up transistor and the second bit line, and wherein the gate of the first sense amplifier transistor (22) is connected to the second bitline (BL₂) and the gate of the second sense amplifier transistor (24) is connected to the first bitline (BL₁).

Inventors: TADDIKEN ALBERT HENRY, WHITE WILLIAM ALVIN, TADDIKEN, ALBERT HENRY, WHITE, WILLIAM ALVIN
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1989
Main classification: G11C7
IPC codes: G11C7, G11C11