Method of recording reproducing data of mesh pattern, and apparatus therefor

Abstract: A data reading apparatus reads data of dots from a recording sheet on which data is recorded in the form of a mesh pattern, and decodes the read data into binary data. The data reading apparatus has an image sensor (1) to read black/white levels of dots of the mesh pat­ tern using the image sensor and to binarize the read levels by a hardware component (2) or CPU processing according to software. An image can have a high record­ ing density by minimizing a dot size.

Description: The present invention relates to a method for recording encoded data in the form of an image on a recording medium according to claim 1. A bar code technique is known as a method for reading an encoded image from a recording medium (recording sheet) and for reproducing binary data. For example, this method is disclosed in US-A-4,422,361, US-A-4,437,378, and in US-A-4,464,966. However, the bar code is not suitable for inputting a large volume of data since it is difficult to increase a recording density of bar codes because of their specific format. Published Unexamined Japanese Patent Application JP-A-53-73026 discloses a method wherein an image constituted by some black dots and the remaining white dots of an i × j (e.g., 3 × 3) matrix is read to recognize a black-and-white mesh pattern. The data volume of the matrix encoded image can be increased by increasing the number of dots included in the matrix. However, in this known method, in order to recognize the black-and-white mesh pattern, software is used. For this reason, this method requires a considerable time to recognize a pattern, and a pattern reading apparatus becomes expensive. A data recording method using a similar matrix image is also described in "Dump List Read by Image Scanner" I/O, May 1988, pp. 121 to 125. It is the object of the present invention to provide a recording method which can easily and quickly read and recognize encoded image data having a relatively high recording density. This object is solved by the features of claim 1. It is another aspect of the present invention to provide a data reading apparatus which can eliminate problems caused when encoded image data is sequentially input (e.g., in units of scan lines) using a hand-held image scanner or the like, e.g., a problem of a data recognition error caused by a change in scanning speed, direction, or the like. In the following description of preferred embodiments of the present invention taken reference is made to the accompanying drawings, in which: Fig. 1 schematically shows the overall arrangement when the present invention is applied to an input section of performance data of an electronic musical instrument; Fig. 2 shows an encoded image of a music score recorded on a recording sheet; Figs. 3A to 3C show code systems associated with notes of a music score; Fig. 4 is a block diagram showing the overall arrangement of a data reading apparatus according to a first embodiment of the present invention; Fig. 5 is a view for explaining a line width of a sensor unit and a scan direction; Fig. 6 is a circuit diagram of a control circuit unit shown in Fig. 4; Fig. 7 is an enlarged view of an encoded image for explaining an operation of the control circuit unit; Figs. 8A and 8B show image data to be sampled by the control circuit unit; Fig. 9 is a circuit diagram of a sampling circuit shown in Fig. 6; Fig. 10 is a timing chart of principal signals used in the control circuit unit; Fig. 11 is an enlarged view of a specific pattern in a mesh pattern of an image for explaining another arrangement of the control circuit unit shown in Fig. 4; Fig. 12 is a circuit diagram showing another arrangement of the control circuit unit shown in Fig. 4; Fig. 13 is a circuit diagram of a scanning speed detecting circuit shown in Fig. 12; Fig. 14 is a circuit diagram of a sampling circuit shown in Fig. 12; Figs. 15A to 15E show 1-bit encoded images according to a second embodiment of the present invention; Fig. 16 shows an encoded image recorded on a recording sheet; Fig. 17A is a view for explaining data decoding; Fig. 17B is a flow chart of data decoding executed by a CPU; Fig. 18 is a block diagram of a binary data recording apparatus for recording/reproducing an encoded image according to a third embodiment of the present invention; Fig. 19A is a view for explaining data encoding states executed by a CPU in a recording mode; Fig. 19B is a flow chart of data encoding executed by the CPU; Fig. 19C is a view for explaining a data encoding operation; Fig. 20 is a block diagram showing the overall arrangement of a data reading apparatus according to a fourth embodiment of the present invention; Fig. 21 is a view showing an encoded image recorded on a recording medium; Fig. 22 is a circuit diagram of a threshold determining circuit; Figs. 23A to 23F are timing charts of signals of respective sections of the data reading apparatus shown in Fig. 20; and Fig. 24 is a flow chart showing processing for changing a threshold level on the basis of a binarization result. Some embodiments of the present invention will now be described with reference to the accompanying drawings. (First Embodiment) An embodiment in which the present invention is applied to inputting of performance data of an electronic musical instrument will be described below. Fig. 1 is a schematic view showing the overall electronic musical instrument according to this embodiment. An image EI obtained by encoding performance data (music score data) is printed at a high density on a margin of a music score S. A data reading apparatus DR scans the music score data image EI to read it. The apparatus DR transfers the read data to an electronic musical instrument MI. The musical instrument MI makes a performance according to the received data. Fig. 2 shows an example of the encoded image EI. As shown in Fig. 2, the encoded image EI has a mesh pattern MP having a rectangular shape, and each dot is set to be white ( ) or black ( ). Upper and lower bars A-1 and A-2 are printed along the upper and lower sides of the mesh pattern MP. The pair of bars A-1 and A-2 are utilized to determine sampling points of the mesh pattern MP in the vertical direction of the drawing. Two columns at the "left end" of the mesh pattern MP form a checker pattern, and two rows at each of the "upper end" and "lower end" of the mesh pattern MP also form a checker pattern. These checker patterns indicate ends of the mesh pattern MP. In this embodiment, the number of rows of the mesh pattern MP is 12. Therefore, 8 rows other than the two rows each at the upper and lower ends serve as a data area (area decoded by the data reading apparatus DR). In the data area, one note is expressed by two columns, and black-and-white patterns at odd-numbered columns from the left represent pitch data. Of the black-and-white patterns at the odd-numbered columns, the black-and-white pattern of three dots from the upper end represents an octave code (OC), the black-and-white pattern of the following four dots represents a scale or note code (SC), and an eighth black or white dot represents a parity. Black-and-white patterns at even-numbered columns represent tone durations. Of the black-and-white patterns at the even-numbered columns, the black-and-white pattern of seven dots from the upper end represents a time code TC, and an eighth dot represents a parity code. Figs. 3A to 3C show code systems when a black dot is "1" and a white dot is "0". Fig. 4 shows the overall arrangement of the data reading apparatus. In Fig. 4, a sensor unit 1 reads image data, and sends the read image data to a control circuit unit 2. The control circuit unit 2 converts each dot of the image data into data representing a black/white state of each dot, and writes the converted data into a memory 3. A CPU 4 reads out data stored in the memory 3, converts readout data into corresponding application data (in this case, performance data), and transfers it to an external apparatus (in this case, the electronic musical instrument). The sensor unit 1 includes a proximity type line image sensor. The line image sensor radiates light on an image using an LED array 1-3, receives light reflected by the image by a sensor element array 1-1 through a rod lens array 1-2, and converts it into an electrical signal. The line width of the sensor unit 1 is determined according to an operation condition. In general, when the sensor unit 1 is scanned from the left end toward the right end of the encoded image EI, the line width is determined so that the entire encoded image can be read even if it is scanned while being inclined at a maximum inclination angle, as shown in Fig. 5. In Fig. 5, a portion surrounded by dotted lines is read by the sensor unit 1 as image data. The memory 3 and the CPU 4 in Fig. 5 are conventional ones, and a description thereof will be omitted. The control circuit unit 2 is a main part of the data reading apparatus. The control circuit unit 2 recognizes the black/white dots in the mesh pattern of the encoded image EI. Two arrangements of the control circuit unit 2 will be described below. Example of Control Circuit Unit (1) Fig. 6 shows a first arrangement of the control circuit unit 2. The control circuit unit 2 receives image data from the sensor unit 1 described above. This arrangement is made under the assumption that the sensor unit 1 scans the encoded image EI from the left to the right, as shown in Fig. 5. Fig. 7 is a view for explaining Fig. 6, and shows a case wherein an encoded image EI is obliquely scanned by the sensor unit 1. If actual dimensions of each dot of the mesh pattern are 0.5 mm × 0.5 mm, Fig. 7 is an enlarged view of dots at a magnification of about 16. Therefore, if the sensor unit 1 is assumed to have a resolution of 16 lines per mm, a black/white dot per mm is read in Fig. 7. Lines 7-3 and 7-4 represent input image data for one line of the sensor unit 1. In Fig. 6, a signal SDATA is serial image data supplied from the sensor unit 1. In this embodiment, data corresponding to about 160 bits are output per one scan (one scan line) of the sensor. The data SDATA passes a flip-flop FF1 enabled in synchronism with a clock 1 (Fig. 10), and is then supplied to a 20-bit shift register 2-1. The outputs from the 20-bit shift register 2-1 and the input data SDATA through an inverter INV1 are supplied to a ROM1 constituting a NAND gate. The ROM1 outputs a signal PT (Fig. 10). When the input data SDATA has one white bit following 20 continuous black bits, the signal PT goes to low level, i.e., is set in an active state. These circuit elements detect the edges (points 7-1 and 7-2 in Fig. 7) of the upper and lower bars. Note that in Fig. 6, latches and registers perform a read operation in response to the clock 1 and perform an output operation in response to a clock 2 (Fig. 10) unless otherwise specified. The signal PT is supplied to a gate G1 together with a signal obtained by inverting the clock 1 by an inverter INV2. An output signal from the gate G1 is supplied to a circuit 2-3 including an S-R flip-flop and a D-flip-flop as major components. The circuit 2-3 forms a signal DON (Fig. 10) which goes to high level (active level) from the edge 7-1 to the edge 7-2 of the upper and lower bars. Note that the circuit 2-3 receives, through an inverter INV3, a signal SH (Fig. 10) which is generated every time image data for one scan line is supplied from the sensor unit 1. The circuit 2-3 is reset by an output signal SH from the inverter INV3. The signal DON is supplied to a counter 2-4 which is reset by the signal SH. The counter 2-4 counts the number of clock pulses 1 while the signal DON is at high level, i.e., from detection of the edge 7-1 of the upper bar A-1 to detection of the edge 7-2 of the lower bar A-2. The signal DON is also supplied to a flip-flop FF2. The output signal of the flip-flop FF2 and another output signal TPT (a Q output of the D-flip-flop) of the circuit 2-3 are supplied to a NAND gate G2. The output from the NAND gate G2 becomes a signal which goes to high level when the sensor unit 1 detects the trailing edge 7-2, and is input to an 8-bit latch 2-5 as a load control signal. The count value of the counter 2-4 when the load control signal goes to "high level" represents a distance from the leading edge 7-1 (7-7) to the trailing edge 7-2 (7-8). This count value is latched by the latch 2-5. The output signal from the gate G2 is supplied to a gate G3 together with an inverted signal of the clock 1 from an inverter INV4. The output signal of the gate G3 becomes a signal L (effective line end signal) which goes to high level when the sensor unit 1 detects the trailing edge 7-2 (Fig. 10). A circuit (2-6, 2-7, 2-8, 2-9, INV5, and G4) at the output side of the latch 2-5 almost equally divides a distance from the leading edge 7-1 to the trailing edge 7-2 into 16 sections. Thus, timing signals S (Fig. 10) corresponding to vertical sampling positions of the mesh pattern MP can be obtained. The sampling positions are represented by 7-6 (...) in Fig. 7. The number of equally divided sections is set to be 16 since the width of the bar A-2 corresponds to three dots, 12 rows of dots are present between the upper and lower bars A-1 and A-2, and an interval between the bar A-1 or A-2 and the mesh pattern corresponds to half a dot in the image data of Fig. 7. If timings are obtained by equally dividing an interval between a detection timing of the edge 7-1 and a detection timing of the edge 7-2 into 16 sections, first 12 out of 16 timings represent vertical sampling timings of 12 rows of dots. The circuit (2-6, 2-7, 2-8, 2-9, INV5, and G4) will be described in detail below. Upper four bits of the latch 2-5 are supplied to a half adder (HA) 2-6. The output from the half adder 2-6 serves as load data to a subtractor 2-7. The subtractor 2-7 decrements data by one in response to the clock 1, and loads the data from the half adder 2-6 every time its borrow output is generated. The borrow output of the subtractor 2-7 is supplied to a gate G4 together with an inverted signal of the clock 1 from an inverter INV5. The output signal of the gate G4 serves as a sampling signal S (indicating a sampling timing) in a vertical (main scan) direction. Lower four bits of the output data of the 8-bit latch 2-5 are input to four inputs of a 4-bit full adder (FA) 2-8. The outputs from 4-bit full adder FA are fetched by a latch 2-9 in response to the signal S. The outputs from the latch 2-9 are input to the remaining four inputs of the full adder 2-8. The carry output of the full adder 2-8 serves as an LSB input of the 4-bit half adder 2-6. For example, paying attention to a line 7-4 in Fig. 7, if 130-bit image data are present between edges 7-7 and 7-8, a value "130" (decimal notation) is counted by the counter 2-4, and data "10000010" (binary notation) is latched by the latch 2-5. Upper four bits "1000" of this data cause the gate G4 to output the signal S once per 8 clocks 1. On the other hand, lower four bits "0010" of the latched data of the latch 2-5 cause the full adder 2-8 to output the carry output once every 8 clocks S. The carry output is input to the half adder 2-6. For this reason, the load data of the subtractor 2-7 which calculates the signal S is incremented by 1. In a cycle in which the carry is output, the signal S is output with a delay corresponding to one clock 1. In response to the vertical sampling signal S, a 4-bit shift register 2-10 and a 12-bit shift register 2-11 fetch (sample) image input data from the flip-flop FF1. The outputs of the 12-bit shift register 2-11 are latched by a 12-bit latch 2-12 in response to the timing signal L representing detection of the trailing edge 7-8. Data input to the latch 2-12 are those at vertical sampling positions of the dots of the image data SDATA for the present line. The outputs from the latch 2-12 are supplied to 12-channel sampling circuits 2-13. The sampling circuits 2-13 select image data (data indicating black/white (0/1) levels of dots) at the horizontal sampling positions, and write them into the memory 3. The sampling circuits 2-13 will be described in detail later. Fig. 8A shows sampled data. More specifically, data shown in Fig. 8A represent the contents of the latch 2-12 in units of scan lines. For example, the first row of Fig. 8A represents data of sampling positions when a line 7-3 in Fig. 7 is scanned. Similarly, the seventh row of Fig. 8A represents sampling data when a line 7-4 is scanned, and the lowermost row of Fig. 8A represents sampling data when a line 7-5 is scanned. Fig. 8B shows data actually written in the memory 3, and conversion from the data shown in Fig. 8A to data shown in Fig. 8B is performed by the sampling circuits 2-13. The arrangement of the sampling circuit will be described below with reference to Fig. 9. In Fig. 9, a counter 9-1 counts the number of successive bits "0" or "1" (the number of lines L) for columns of data shown in Fig. 8A. The counter 9-1 is reset by an EX-OR 9-2 when data in the column is changed from "0" to "1" or from "1" to "0". More specifically, when the EX-OR 9-2 detects a noncoincidence between the vertical sampling data of the present line from the 1-bit latch 2-12 (Fig. 6) and vertical sampling data of an immediately preceding line from a flip-flop FF3, it resets the counter 9-1. The output from the counter 9-1 is supplied to a ROM2. The ROM2 generates a horizontal sampling signal ns when the output from the counter 9-1 is 4 or 12 (after the lapse of a time corresponding to 4 or 12 lines from when the output from the latch 2-12 changes to "0" or "1"). A change in output from the latch 2-12 from "0" to "1" or from "1" to "0" corresponds to detection of a switching point (boundary) from a white dot to a black dot or vice versa. In Fig. 9, a circuit 9-3 is provided to each of odd-numbered channel (odd-numbered circuits from the left in Fig. 6) sampling circuits 2-13. In each of even-numbered channels, a circuit 9-4 is used in place of the circuit 9-3. The circuits 9-3 and 9-4 are used to detect start of data. As shown in Fig. 2, in the "left end" mesh pattern, dots in each odd-numbered row (e.g., the uppermost row) are changed from black ("1") to white ("0"), while dots in each even-numbered row are changed from white ("0") to black ("1") along the scanning direction (Fig. 5). The circuit 9-3 in each odd-numbered channel detects a change from a white dot to a black dot in the "left end" pattern. The outputs from the circuits 9-3 and 9-4 set a flip-flop FF4 to cause it to output a signal EN indicating that data is being scanned. The flip-flop FF4 is reset in response to a signal generated when the data reading apparatus starts scanning of an image. The signal ns and the signal EN are supplied to an AND gate G5. An AND gate G6 receives the output signal from the AND gate G6 and a clock W (clock generated in response to the trailing edge of a signal DON). The AND gate G6 generates a write signal WR to the memory 3 after data reading is started. In response to the signal WR, the content (DATA) of the flip-flop FF3 is written in the memory 3. Furthermore, the output signal ns of the gate G5 increments an address counter 9-5 to designate the next address (ADDRESS) of the memory 3. Fig. 10 shows timing charts of principal signals. RON in Fig. 10 is a signal representing that the data reading apparatus scans an image, and SRON in Fig. 10 is a one-shot pulse generated at the beginning of scanning. W in Fig. 10 is a clock generated at the leading edge of the signal DON (upon passing the edge 7-1 of the upper bar A-1). Other signals have already been described with reference to Figs. 6 and 7, and a description thereof will be omitted. The control circuit unit 2 (Figs. 6 and 9) of the first arrangement performs processing in the following procedures. The control circuit unit 2 (1) receives the image data SDATA from the sensor unit 1 which reads an encoded image shown in Fig. 2 line by line while being moved from the left to the right, (2) detects the edges 7-1 and 7-2 of the upper and lower bars A-1 and A-2 included in the 1-line image data, (3) calculates an interval therebetween, and (4) almost equally divides the interval to detect vertical sampling positions of the mesh pattern MP (by 2-1, ROM1, 2-3 to 2-9, and the like). The control circuit unit 2 (5) extracts vertical sampling data from image data for the next line (by 2-10, 2-11, and 2-12). The control circuit unit 2 (6) then detects boundaries between black and white dots from time-serial image data associated with the vertical sampling positions (by FF3 and 9-2), (7) measures a predetermined time from the detection (by 9-1 and ROM2), (8) extracts corresponding vertical sampling data using a timing corresponding to the lapse of the predetermined time as a timing of the horizontal sampling position, and (9) writes the extracted data in the memory 3 (by G5, G6, 9-5, FF3, and the like). Therefore, the control circuit unit 2 of the first arrangement can recognize black and white dots in the mesh pattern MP at high speed. As shown in Fig. 7, when the sensor unit 1 obliquely scans the encoded image EI, the vertical sampling positions can be assured, and no problem occurs in data recognition. However, in the above arrangement, the horizontal sampling timing corresponds to the lapse of the predetermined time from detection of a boundary between horizontally adjacent black and white dots. For this reason, when the sensor unit 1 is manually moved, the horizontal scanning speed of the mesh pattern varies, and the horizontal data sampling position is shifted. As a result, erroneous data recognition may be made. A control circuit unit (second arrangement) which can cope with this problem will be described below. Example of Control Circuit Unit (2) The control circuit unit of the second arrangement includes a circuit for detecting a horizontal scanning speed of the sensor unit 1 from a specific pattern included in the mesh pattern MP. The specific patterns are patterns shown at the "upper end" and "lower end" of the mesh pattern MP shown in Fig. 11. More specifically, a mesh pattern in which black and white dots alternately appear along the horizontal direction is utilized. In Fig. 11, although neither black nor white dots are illustrated in the data area, dots are changed from white to black at least every two dots in the horizontal direction. In order to change dots from white to black at least every two dots, two data dots represent 1 bit. Bit "1" is expressed by or , bit "0" is expressed by or , and the encoded image EI is recorded so that a boundary between black and white dots is formed between a 1-bit dot pair and an adjacent dot on the left or right side thereof. For example, when bit "1" is recorded on the right side of (bit "1"), a pattern is selected; when bit "0" is recorded, a pattern is selected. Other operating conditions (scanning direction, and the like) are the same as those in the first arrangement. Fig. 12 shows a control circuit unit 2M of the second arrangement. The arrangement for detecting vertical sampling positions and the arrangement for sampling image data at the vertical sampling positions are the same as those in the control circuit unit 2 of the first arrangement. A difference between Figs. 6 and 12 is that 2-channel scanning speed detecting circuits 2-14 are arranged, and sampling circuits 2-13M are modified. The 2-channel scanning speed detecting circuits 2-14 have the same arrangement. The circuits 2-14 receive inputs from the 1st and 11th bits each of the 12-bit latch 2-12 to detect the horizontal scanning speed of the sensor unit 1 on the basis of patterns in the 1st and 11th rows in the mesh pattern MP shown in Fig. 11. Fig. 13 shows the arrangement of each scanning speed detecting circuit 2-14. The 1st or 11th bit data of the latch 2-12 is supplied to a flip-flop FF5 and an EX-OR gate 14-1. The output data from the flip-flop FF5 is supplied to the EX-OR gate 14-1. The EX-OR gate 14-1 detects a boundary between black and white dots in the pattern of the 1st or 11th row as the specific pattern shown in Fig. 11. The output signal from the EX-OR 14-1 resets a counter 14-4 through a flip-flop 14-3. The output signal from the EX-OR gate 14-1 is supplied to a gate 14-2 together with the clock 1. The gate 14-2 generates a signal N (latch clock) in synchronism with the clock 1. The counter 14-4 counts the number of successive white (bit "0") or black (bit "1") dots from the boundary, i.e., scan lines in response to the line signals L. A boundary between black and white dots in the specific pattern (1st row or 11th row in Fig. 11) appears every other dots. Therefore, the count value of the counter 14-4 represents a time from detection of a given boundary to detection of the next boundary. This means that the horizontal scanning speed of the sensor unit 1 is detected. The count value of the counter 14-4 is input to full adder (FA) 14-5, and is added to an immediately preceding sum. The sum of the full adder 14-5 is supplied to a 1/2 divider 14-6, and is divided by 2. The output data of the 1/2 divider 14-6 is latched by a latch 14-7 at a timing N representing detection of the boundary of the specific pattern. An output n of the latch 14-7 is sent to the full adder (FA) 14-5 as an immediately preceding sum, and is supplied to a latch 14-9 which is operated in response to the clock N through a 1/2 divider 14-8. The latch 14-9 generates an n/2 signal. The output from the latch 14-7 and the output from the 1/2 divider 14-8 are added to each other by a full adder (FA) 14-10. The output data from the full adder 14-10 is supplied to a latch 14-11 which is operated in response to the clock N. The latch 14-11 generates a 3n/2 signal. The n/2 signal represents a time required for the sensor unit 1 to move by half a dot at its present horizontal scanning speed, and the 3n/2 signal represents a time required for the sensor unit 1 to move by a dot + 1/2 at its present horizontal scanning speed. These two signals n/2 and 3n/2 are utilized in each sampling circuit 2-13M to generate the horizontal sampling position signal. Fig. 14 shows the arrangement of the sampling circuit 2-13M. A difference between the sampling circuit 2-13M in Fig. 14 and the sampling circuit 2-13 (Fig. 9) in the first arrangement is that a coincidence circuit 9M is used in place of the ROM2 (circuit for detecting a coincidence between the output from the counter 9-1 and a fixed value). The coincidence circuit 9M compares the n/2 and 3n/2 signals which change in accordance with the scanning speed with the output from the counter 9-1 to detect a coincidence/noncoincidence. More specifically, the coincidence circuit 9M detects a timing corresponding to the lapse of an n/2 time or 3n/2 time from detection of the boundary between black and white dots in a data row of the mesh pattern MP, and generates a horizontal sampling position signal ns. As described above, the n/2 time corresponds to movement by half a dot, and the 3n/2 time corresponds to movement by one dot + 1/2. Meanwhile, the data row (each of the 3rd to 10th rows in Fig. 11) changes from white to black or vice versa in a cycle of at least two dots. Therefore, the coincidence signal ns of the coincidence circuit 9M designates a substantially central position of each dot of the data row regardless of a variation in scanning speed. Note that although two scanning speed detecting circuits 2-14 are arranged, the outputs (n/2, 3n/2) of the scanning speed detecting circuit 2-14 corresponding to the specific pattern at the upper end (Fig. 11) are input to the sampling circuits 2-13M corresponding to upper half data rows, and the outputs of the scanning speed detecting circuit 2-14 corresponding to the specific pattern at the lower end are input to the sampling circuits 2-13M corresponding to lower half data rows. Alternatively, the outputs from the scanning speed detecting circuit 2-14 which scans the specific pattern first are input to all the sampling circuits 2-13M, and the outputs from the scanning speed detecting circuit 2-14 which scans the specific pattern later may be inhibited from being used. Other operations of the sampling circuits 2-13M in Fig. 14 are the same as those in the sampling circuits 2-13 in Fig. 9, and a description thereof will be omitted. In this manner, the control circuit unit 2M of the second arrangement detects the horizontal scanning speed of the sensor unit 1 on the basis of the specific patterns included in the mesh pattern MP, and then detects horizontal data sampling positions on the basis of boundaries between black and white dots detected in association with the data rows of the mesh pattern MP. For this reason, the horizontal sampling positions can be set at correct positions regardless of a variation in scanning speed of the sensor unit 1, and data of an encoded image from an image sensor which scans at a variable moving speed can be reliably recognized. (Modification) The first embodiment of the present invention has been described. The above embodiment is merely an example, and various changes and modifications may be made. The scanning speed dependent signals n/2 and 3n/2 input to the coincidence circuit 9M shown in Fig. 14 may be generated on the basis of an output (scanning speed signal) of a rotary encoder provided to the sensor unit 1. The control circuit unit 2M of the second arrangement has been described under the assumption that each data row of the mesh pattern MP is changed from white to black or vice versa in a cycle of at least two dots. However, the control circuit unit 2M can be slightly modified to cancel this assumption. For example, a circuit for resetting the counter 9-1 when the output from the counter 9-1 coincides with the signal n (Fig. 13) representing movement by one dot may be added to the arrangement shown in Fig. 14. In this case, the coincidence circuit 9M detects a coincidence between the output from the counter 9-1 and the n/2 signal. In Fig. 11, the specific pattern constituted by two rows is formed at each of the upper and lower ends. Alternatively, a specific pattern (in which black and white dots alternately appear) of one row can be formed as the central row of the mesh pattern to extend in the horizontal direction to be longer than other rows. In this case, the scanning speed detecting circuit 2-14 need only be arranged for one channel. The mesh pattern has a rectangular shape as a whole, but may have a square or parallelogram shape. Image data input to the control circuit unit 2 may be transferred from an image memory storing the encoded image EI. As described above, according to the first embodiment, a recording sheet of an image including a mesh pattern obtained by encoding data by selectively formed black and white dots is used as a recording medium. And the data reading apparatus is constituted by hardware means (vertical data sampling position calculating circuit means, horizontal data sampling position calculating circuit means, and data sampling circuit means) for detecting vertical and horizontal data sampling positions of the mesh pattern to sample image data at these positions in order to recognize black and white dots from the image read by the image sensor means. Therefore, data recognition of a high-density encoded image can be performed at high speed. As a mark for indicating vertical sampling positions of the mesh pattern, a pair of bars are formed along the upper and lower sides of the mesh pattern. The data reading apparatus measures an interval between the pair of bars, and equally divides the measured interval to detect vertical sampling positions. Therefore, even if the image sensor means obliquely reads the encoded image on the recording sheet, vertical data sampling positions can be maintained at correct positions. In this data reading apparatus, a line image sensor for reading an image line by line while being moved from one side portion of the mesh pattern to the other side portion is used as the image sensor means. The horizontal data sampling position calculating circuit means detects a boundary between horizontally adjacent black and white dots included in the mesh pattern, and detects a timing corresponding to the lapse of a predetermined time from this detection as a horizontal data sampling timing. Therefore, the apparatus is a simple arrangement, and as long as the moving (scanning) speed of the image sensor means is constant, a correct horizontal sampling position can be obtained. However, it is not suitable for image sensor means whose moving speed is variable. When the data reading apparatus is constituted using scanning speed detecting circuit means for detecting a horizontal scanning speed of the image sensor means, a correct horizontal data sampling position can be detected for an image from the image sensor means who scanning speed varies, and reliable data recognition can be performed. A row in which black and white dots alternately appear in the horizontal direction is formed as a specific pattern in the mesh pattern, a boundary between black and white dots in this specific pattern is detected, and a time between two adjacent boundaries is detected to detect a scanning speed of the image sensor means. In this case, as compared to a case using an apparatus for detecting a scanning speed of image sensor means independently of an image (e.g., a rotary encoder), an arrangement can be rendered and simple, and its precision can be improved. (Second Embodiment) This embodiment is an improvement of the first embodiment and is characterized in that an operation error upon reading of binary data is prevented. More specifically, in this embodiment, a mesh pattern in which each 1-bit encoded image is constituted by a black-and-white pattern of a predetermined number of dots, and boundaries between two adjacent black and white dots are regularly distributed is recorded on a data recording medium. The data reading apparatus utilizes these features to improve its data recognition rate. An encoded image of this embodiment will be described below. Figs. 15A to 15E show encoded images each representing 1 bit. According to this embodiment, each 1-bit encoded image is expressed by a black-and-white pattern of a plurality of dots. In this embodiment, as shown in Fig. 15A, four dots correspond to 1 bit. Patterns shown in Figs. 15B and 15C represent bit "0", and patterns shown in Figs. 15D and 15E represent bit "1". Assume that a white dot is given by "0", a black dot is given by "1", and a bit pattern is represented by a numerical value in the order of upper left, upper right, lower left, and lower right. The patterns representing bit "0" shown in Figs. 15B and 15C are respectively "1100" and "0011", and the patterns representing bit "1" shown in Figs. 15D and 15E are respectively "0110" and "1001". In either 1-bit encoded image, a horizontal central line of four dots serves as a boundary between black and white dots. When these 1-bit encoded images are arranged in a matrix to form a mesh pattern, these images are coupled so that the right and left sides of each 1-bit image serve as boundaries between black and white dots. For example, if a 1-bit encoded image of "0" is coupled to the right side of the pattern shown in Fig. 15B, the pattern shown in Fig. 15C is selected; when a 1-bit encoded image of "1" is coupled, the pattern shown in Fig. 15D is selected. Fig. 16 shows an example of an image recorded on the data recording medium according to this coupling method. In Fig. 16, reference symbol MP denotes a mesh pattern in which 1-bit encoded images are arrayed according to the above-mentioned coupling method. In this case, two rows at the "upper end", two rows at the "lower end", and two columns at the "left end" include the pattern shown in Fig. 15E, and represent ends of the mesh pattern MP. A portion other than these ends is a data area. In Fig. 16, the data area is constituted by 8 rows of patterns. The horizontal central line and right and left sides of each 1-bit encoded image are used as boundaries between black and white dots, so that the boundaries are almost uniformly distributed in the mesh pattern MP. When the boundaries between the black and white dots are uniformly distributed, a maximum number of dots which have the same lightness and are successively coupled is limited to two, and this stabilizes the operation of an image sensor (to be described later) and facilitates binarization of black and white dots. In Fig. 16, the specific patterns located at the "upper end" and "lower end" are utilized to detect a horizontal moving speed (scanning speed) of an image sensor when image data is read while moving the image sensor from the left end toward the right end of an encoded image. In Fig. 16, upper and lower bars A-1 and A-2 are arranged along the upper and lower sides of the mesh pattern MP. These bars A-1 and A-2 are utilized to detect vertical data sampling positions, i.e., an almost central vertical coordinate of each dot in the mesh pattern MP. In this manner, the encoded image of the second embodiment is the same as that (especially in Fig. 11) of the first embodiment, and only the rule of the mesh pattern is different from that of the first embodiment, as shown in Fig. 15. Therefore, as a data reading apparatus for reading this image and reproducing binary data, one described in the first embodiment can be used without modifications. Therefore, a repetitive description thereof will be avoided herein. For example, if the arrangements shown in Figs. 4, 12, 13, and 14 are employed (of course, the arrangements shown in Figs. 6 and 9 may be employed), sampling data is finally written in the memory 3 (Fig. 4). Data indicating a black/white level of each dot of the mesh pattern stored in the memory 3 is converted to a bit for each 1-bit encoded image. This processing will be described below with reference to Figs. 17A and 17B. Four squares b , c , f , and g represented by solid lines represent black/white levels of dots of a 1-bit encoded image to be decoded. Squares a , e , d , and h represented by dotted lines represent black/white levels of dots adjacent to the 1-bit encoded image. As described above, in the encoded image shown in Fig. 16, a boundary between black and white dots is present at a horizontal central line of each 1-bit pattern constituted by four dots, and the right and left sides of the 1-bit patterns serve as boundaries between black and white dots. This rule is used in the flow chart shown in Fig. 17B. In addition, assume that black/white levels of adjacent dots are correctly recognized. In step 10-1, a CPU 4 compares black/white data b of the upper left dot b of a 1-bit pattern to be decoded with black/white data f of the lower left dot f . According to the boundary rule, the black/white data b and f must not coincide with each other. When the black/white data b and f coincide with each other, this means that a sensor unit 1 and a control circuit unit 2 erroneously recognized dots. The flow then advances to step 10-2 to compare the black/white data b with black/white data a of the left neighboring dot a . If the black/white data a is correct, the black/white data a and b do not coincide with each other according to the boundary condition. Therefore, if a = b is established, it can be considered that the black/white data b is erroneously recognized. Thus, the data b is inverted (step 10-3). If the black/white data a and b do not coincide with each other, the flow advances to step 10-4, and black/white data f of the lower left dot of the 1-bit pattern is compared with black/white data e of the left neighboring dot. In this case, if e = f is established, it can be considered that the black/white data f of the lower left dot f is erroneously recognized, and the data f is corrected (step 10-5). If a ≠ b and e ≠ f are established when b = f , it means that black/white data of two or more dots of these dots a , b , e , and f are erroneously recognized, and error processing is executed. If the black/white data b and f do not coincide with each other, the flow advances to step 10-6, and black/white data c of the upper right dot c of the 1-bit pattern is compared with black/white data g of the lower right dot g . According to the boundary condition, these data must not coincide with each other. Therefore, if the black/white data c and g coincide with each other, the flow advances to step 10-7, and the black/white data c of the upper right dot c of the 1-bit pattern is compared with black/white data d which is identified for the right neighboring dot d . According to the boundary condition, these data must not coincide with each other. In consideration of the result in step 10-6, both c = g and c = d are established only when only c of the black/white data of the three dots is erroneously recognized (a possibility that the data c is correctly recognized and both the data d and g are erroneously recognized is small). Therefore, the black/white data g is inverted in step 10-8 to have a correct value. If c = d is not established, the black/white data g of the lower right dot g of the 1-bit pattern is compared with black/white data h of the right neighboring dot h . If g = b is established, it is determined that the black/white data is erroneously recognized, and the black/white data g is corrected (step 10-10). If neither of c = d and g = h are established when c = g , these four black/white data include two or more errors, and error processing is performed. After the processing in steps 10-3, 10-5, 10-8, and 10-10, the flow returns to step 10-1. With these processing operations, the 1-bit pattern ( b , c , f , g ) is corrected to a correct pattern, and neither of b = f and c = g are established respectively in steps 10-1 and 10-6. In this case, the flow advances to step 10-11, and the black/white data b of the upper left dot in the corrected 1-bit pattern is compared with the black/white data c of the upper right dot c . As can be seen from Figs. 15B to 15E, b = c is established for the "0" pattern, and is not established for the "1" pattern. Therefore, bit "0" and bit "1" are generated respectively in steps 10-12 and 10-19. Similarly, the flow shown in Fig. 17B is sequentially executed for the next 1-bit encoded image, thus reproducing binary data encoded into the mesh pattern MP. In the processing in Fig. 17B, black/white data for a total of eight dots are checked for a 1-bit encoded image, as shown in Fig. 17A, and bits which are likely to be correct are decoded based on the check result. Although similar to the processing in Fig. 17B, the black/white data a , b , c , d , e , f , g , and h may be directly compared with reference patterns "01101001" and "100100110" of bit "0" and reference patterns "10100101" and "01011010" of bit "1", and the number of noncoincidences may be counted. If the number of noncoincidences is 1 or less, the pattern to be checked is estimated as the corresponding reference pattern, thus decoding a bit. (Modification) The present invention is not limited to the above embodiment, and various changes and modifications may be made. For example, in this embodiment, a black/white level of each dot is identified by the control circuit unit 2 as the hardware means. However, the identification operation may be executed by the CPU 4 if a decrease in recognition speed does not pose a problem. In association with this, specific patterns at the ends of the encoded image EI and the upper and lower bars A-1 and A-2 are not always required. These elements are merely marks for allowing easy and quick detection of vertical and horizontal data sampling positions of an encoded image in the control circuit unit 2 which performs hardware processing in real time. In place of the specific patterns, the black/white boundary rule may be utilized to identify the black/white level of each dot by the CPU 4. For example, a frame of encoded image data is scanned in the vertical and horizontal directions to extract a boundary point of black and white pixels, thus recognizing vertical and horizontal lines forming dots of the mesh pattern. The central points of adjacent vertical lines and the central points of the adjacent horizontal lines are calculated to obtain sampling coordinates of each dot. Image data located at the calculated coordinates can be sampled to recognize a black/white level of each dot. In the above embodiment, 1 bit is encoded using four types of black-and-white patterns each of four dots, and each of bit "0" and bit "1" includes two patterns. Alternatively, a single pattern may be assigned to each of bit "0" and bit "1". For example, a pattern shown in Fig. 15D may be used as bit "0", and a pattern shown in Fig. 15E may be used as bit "1". In this case, a maximum number of successive bits having the same lightness is 2 in the mesh pattern. The number of dots representing 1 bit is not limited to 4, and 1 bit may be expressed by a plurality of dots excluding 4. For example, when a 1-bit encoded image is constituted by three dots, a pattern in which the upper left dot is black and the upper right and lower left dots are white or a pattern obtained by rotating this pattern by 180° may be used as bit "1", and a pattern in which the upper left dot is white and the upper right and lower left dots are black or a pattern obtained by rotating this pattern by 180° may be used as bit "0". In this case, a 1-bit encoded image having no upper left dot (three dots, i.e., lower right, upper right, and lower left) can be coupled under a 1-bit encoded image having no lower right dot (three dots, i.e., upper left, upper right, and lower left). A 1-bit encoded image having no lower right dot has black/white boundaries between the upper left and upper right dots and between the upper left and lower left dots. A 1-bit encoded image including no upper left dot has black/white boundaries between the lower right and lower left dots and between the lower right and upper right dots. Therefore, black/white boundaries are regularly present in the mesh pattern. 1-bit encoded images preferably have different black-and-white patterns from each other as much as possible. In such a case, even when many errors are included upon recognition of black/white levels of a plurality dots, bits which are likely to be correct can be decoded. In the data reading apparatus of this embodiment, image sensor means reads an image on the data recording medium, dot state identification means identifies a black/white level of each dot of the mesh pattern, and data decoding means compares a black-and-white pattern identified by the dot state identification means with a predetermined reference pattern, thus decoding data. Black/white boundaries are almost uniformly distributed in the mesh pattern. For this reason, the image sensor means does not successively receive identical black/white data, and a black/white recognition rate of each dot by the dot state identification means can be improved. Furthermore, since each 1-bit encoded image is expressed by a black-and-white pattern of a plurality of dots, even if black/white levels of some dots are erroneously recognized, the data decoding means can estimate a bit which is likely to be correct, thus improving a data recognition rate. (Third Embodiment) A third embodiment of the present invention will now be described. The feature of the third embodiment is to provide a recording apparatus with which a user records a mesh pattern, while the first and second embodiments relate to a reading apparatus for reading data from a recording medium on which a mesh pattern is recorded. For example, as an encoded image recorded on a data recording medium like in the second embodiment, a mesh pattern in which each 1-bit encoded image is constituted by a black-and-white pattern of a predetermined number of dots, and boundaries between black and white dots are regularly distributed is employed. The encoded image is recorded on a data recording medium using a binary data recording apparatus, and binary data is reproduced from the encoded image using a binary data recording/reproducing apparatus. In this case, the reading apparatus DR shown in Fig. 1 is replaced with a binary data recording/reproducing apparatus. The binary data recording/reproducing apparatus DR serves as an I/O device of performance data for an electronic musical instrument MI. When data is input, performance data is transferred from the apparatus DR to the musical instrument MI. When data is output, performance data is transferred from the musical instrument MI to the apparatus DR. Fig. 18 is a block diagram of the binary data recording/reproducing apparatus DR for recording an encoded image on a data recording medium such as a paper sheet (in Fig. 1, a margin of the music score S), and reproducing binary data from the recorded encoded image. In a recording mode, binary data supplied from an external apparatus (in Fig. 1, an electronic musical instrument) is encoded by a CPU 4, and is printed on the data recording medium. In a reproducing mode, image data on the data recording medium is read by a sensor unit 1, black/white levels of dots of a mesh pattern MP are identified by a control circuit unit 2, and the identified data are temporarily stored in a memory 3. The data stored in the memory 3 are decoded into binary data by the CPU 4, and the decoded data are transferred to the external apparatus. Encoding processing executed by the CPU 4 in the recording mode will be described below with reference to Figs. 19A to 19C. In the following description, starting 16 bits of binary data to be encoded are "9E5B" (hexadecimal notation) (X in Fig. 19A). A two-dimensional bit pattern of the binary data "9E5B" is indicated by Y in Fig. 19A. Starting four bits are arranged in the first column of the bit pattern, and following sets of four bits are sequentially arranged in right columns. The bit pattern Y is surrounded by bits "1". This corresponds to a pattern in which two rows at each of the upper and lower ends and two columns at the left end of the mesh pattern MP form specific patterns in the encoded image shown in Fig. 16. The mesh pattern MP (indicated by Z in Fig. 19A) and the bit pattern have the relationship that one bit is expressed by four (2 × 2) black/white dots (1-bit encoded image). Black/white boundaries must be formed at right and left sides of each 1-bit encoded image. An operation for converting a bit pattern into a black-and-white pattern will be described below with reference to the flow chart shown in Fig. 19B. In step 5-1, the CPU 4 writes ( 10 01 ) six times in the vertical direction in a print buffer in a printer 5. This corresponds to the pattern at the left end of the mesh pattern MP in Fig. 16. In step 5-2, the CPU 4 writes ( 10 01 ) corresponding to a 1-bit encoded image at the upper end in the print buffer. Thereafter, the CPU 4 repeats the processing in steps 5-3 to 5-9 four times, thus forming data for 4-bit encoded images in the present column. More specifically, in order to generate data corresponding to a 1-bit encoded image, the CPU 4 extracts data a (Fig. 19C) indicating a black/white level of a right neighboring dot of the upper left dot of this 1-bit encoded image from already converted data, and checks in step 5-3 if the extracted data is "1" (black) or "0" (white). If the data a is "1", the flow advances to step 5-4 to check if one bit of binary data to be presently converted is bit "1" or "0". When an encoded image representing bit "1" is coupled to the left side of the pattern shown in Fig. 15B or 15D, the pattern shown in Fig. 15D must be selected. When an encoded image representing bit "0" is coupled, the pattern shown in Fig. 15C must be selected. Therefore, if one bit of binary data to be converted to an image is "1", the CPU 4 writes ( 01 10 ) in step 5-5; if the bit is "0", it writes ( 00 11 ) in step 5-6. If it is determined in step 5-3 that a = 0, the flow advances to step 5-7 to check a value of a bit to be converted. On the right side of the pattern shown in Fig. 15C or 15E, the pattern shown in Fig. 15E must be recorded for bit "1", or the pattern shown in Fig. 15B must be recorded for bit "0". Therefore, if the bit to be converted is "1", the flow advances to step 5-8 and ( 10 01 ) is written in the print buffer; if it is "0", the flow advances to step 5-9 and ( 11 00 ) is written in the print buffer. If convertion for four bits of binary data corresponding to one column is completed, the flow advances to step 5-10, and ( 10 01 ) corresponding to a 1-bit encoded image at the lower end is written in the print buffer. The flow then advances to step 5-11 to check if conversion for all the binary data is completed. If NO in step 5-11, the flow returns to step 5-2 for data conversion of the next column. If it is determined in step 5-11 that conversion for all the data is completed, encoded data representing black/white levels of dots of the mesh pattern MP are completed on the print buffer. A stored position (address) on the print buffer represents a position of each dot when dots are two-dimensionally recorded on the data recording medium. Thereafter, bits of the encoded data stored in the print buffer can be recorded as dots on the data recording medium by the printer 5. For example, if the bit of the encoded data is "1", a black dot is printed; if it is bit "0", one dot is subjected to space processing (when a mesh pattern is recorded on a data recording medium with a white background color). Every time one dot is recorded, the printer 5 shifts a printing position in accordance with the address of the encoded data, thus printing the two-dimensional mesh pattern MP. Note that the upper and lower bars A-1 and A-2 have not been described. However, since these bars are simple patterns having a predetermined positional relationship with the mesh pattern MP, they can be easily printed. In a reproducing mode, image data on the data recording medium is read by the sensor unit 1, and binary data is reproduced by the control circuit unit 2 and the CPU 4. Conversion process from image data to binary data is constructed two steps. In the first step, black/white levels of dots in the mesh pattern MP are recognized based on image data. In the second step, black/white data of four recognized dots are decoded to bits of binary data. The processing in the first step is performed by the control circuit unit 2, and the processing in the second step is performed by the CPU 4. These processing operations are the same as those already described in the second embodiment, and a description thereof will be omitted. (Modification) The present invention is not limited to the above embodiment, and various changes and modifications may be made. For example, in this apparatus, a recording apparatus and a reproducing apparatus may be constituted as separate units. In the above embodiment, a black/white level of each dot is identified by the control circuit unit 2 as the hardware means. However, the identification operation may be executed by the CPU 4 if a decrease in recognition speed does not pose a problem. In association with this, specific patterns at the ends of the encoded image EI and the upper and lower bars A-1 and A-2 are not always required. These elements are merely marks for allowing easy and quick detection of vertical and horizontal data sampling positions of an encoded image in the control circuit unit 2 which performs hardware processing in real time. In place of the specific patterns, the black/white boundary rule may be utilized to identify the black/white level of each dot by the CPU 4. For example, a frame of encoded image data is scanned in the vertical and horizontal directions to extract a boundary point of black and white pixels, thus recognizing vertical and horizontal lines forming dots of the mesh pattern. The central points of adjacent vertical lines and the central points of the adjacent horizontal lines are calculated to obtain sampling coordinates of each dot. Image data located at the calculated coordinates can be sampled to recognize a black/white level of each dot. In the above embodiment, 1 bit is encoded using four types of black-and-white patterns each of four dots, and each of bit "0" and bit "1" includes two patterns. Alternatively, a single pattern may be assigned to each of bit "0" and bit "1". For example, a pattern shown in Fig. 15D may be used as bit "0", and a pattern shown in Fig. 15E may be used as bit "1". In this case, a maximum number of successive bits having the same lightness is 2 in the mesh pattern. When a single image pattern is assigned to each of bit "0" and bit "1", a pattern can be selected on the basis of only a value of a bit in encoding processing in the recording mode. The number of dots representing 1 bit is not limited to 4, and 1 bit may be expressed by a plurality of dots excluding 4. For example, when a 1-bit encoded image is constituted by three dots, a pattern in which the upper left dot is black and the upper right and lower left dots are white or a pattern obtained by rotating this pattern by 180° may be used as bit "1", and a pattern in which the upper left dot is white and the upper right and lower left dots are black or a pattern obtained by rotating this pattern by 180° may be used as bit "0". In this case, a 1-bit encoded image having no upper left dot (three dots, i.e., lower right, upper right, and lower left) can be coupled under a 1-bit encoded image having no lower right dot (three dots, i.e., upper left, upper right, and lower left). A 1-bit encoded image having no lower right dot has black/white boundaries between the upper left and upper right dots and between the upper left and lower left dots. A 1-bit encoded image including no upper left dot has black/white boundaries between the lower right and lower left dots and between the lower right and upper right dots. Therefore, black/white boundaries are regularly present in the mesh pattern. 1-bit encoded images preferably have different black-and-white patterns from each other as much as possible. In such a case, even when many errors are included upon recognition of black/white levels of a plurality of dots, bits which are likely to be correct can be decoded. In an extreme case, one bit can be expressed and encoded by one dot. In this case, the same technique as in the first embodiment can be employed. According to this embodiment, in reproduction of binary data, when image data is read, input black/white levels of dots can be reliably binarized due to the regularly present boundaries. The black/white levels of dots can be identified at a high recognition rate. Furthermore, since the identified black-and-white pattern is compared with a predetermined pattern, even if the black-and-white pattern includes recognition errors of black/white levels of dots, a bit which is likely to be correct can be decoded, thus improving a reproduction rate. Therefore, a printing precision in the binary data recording apparatus can be low relative to a recording density. As a result, in this embodiment, information having a relatively high density can be recorded on an inexpensive data recording medium such as a paper sheet. According to the binary data recording/reproducing apparatus of this embodiment, a large volume of information can be stocked and exchanged through an inexpensive data recording medium. (Fourth Embodiment) A fourth embodiment of the present invention will be described below. The characteristic feature of the fourth embodiment is an improvement of a circuit arrangement used when an encoded image is read and binarized. According to this embodiment, an average value of analog signals of an image for one scan line from an image sensor is calculated, and analog signals of an image for the next line are binarized using this average value as a threshold level. Therefore, when a density of an image on a recording medium varies, binary data of an image can be read according to the variation. Fig. 20 shows the overall arrangement of a data reading apparatus according to this embodiment. An image sensor 101 converts an encoded image (Fig. 21) on a recording medium into analog electrical signals, and serially supplies them to an amplifier 102 in units of scan lines. The analog electrical signals amplified by the amplifier 102 are sent to a sample-hold circuit 103 to be periodically sampled and held. The analog electrical signals from the sample-hold circuit 103 are supplied to a binarization circuit 104 and a threshold level determination circuit 105. The binarization circuit 104 binarizes the analog electrical signals using a threshold level determined by the threshold level determination circuit 105 in units of lines. The binarized digital signals are written in a RAM 106, and are sent to the threshold level determination circuit 105 so as to determine the threshold level for the next line. Fig. 21 shows an example of an encoded image recorded on a recording medium. The encoded image is constituted by known patterns and a data body. In Fig. 21, the known patterns are constituted by black and white bars 21 extending along a sub-scan direction of an image. Widths w of the white and black bars along the main scan direction are equal to each other. Therefore, a ratio of widths of the white and black bars is 1. More specifically, each bar 21 is constituted by two black bars and a blank portion sandwiched therebetween. The bars 21 are formed at two sides of an area of a data body 22. In the data body 22, black pixels which are to be decoded as "1" and white pixels which are to be decoded as "0" are distributed. Fig. 22 shows the arrangement of the threshold level determination circuit 105. An averaging circuit 51 calculates an average value of analog electrical signals (sensor outputs) supplied from the sample-hold circuit 103. More specifically, the averaging circuit 51 is constituted by a capacitor C1 one end of which is connected to a positive voltage source (12 V); a diode D1 the cathode of which is connected to the output terminal of the sample-hold circuit 103; a capacitor C2 one end of which is grounded; a diode D2 the cathode of which is connected to the other end of the capacitor C2 and the anode of which is connected to the output of the sample-hold circuit 103; and a voltage divider having resistors R1 and R2 (having equal resistances R1 = R2) for equally dividing a voltage V L appearing at the other end of the capacitor C1 and a voltage V H appearing at the other end of the capacitor C2 to generate a voltage V A = (V L + V H )/2. The voltage V L of the capacitor C1 represents a voltage of a minimum level of the outputs of the sensor 101, i.e., a voltage corresponding to a darkest pixel, the voltage V H of the capacitor C2 represents a voltage of a maximum level of the outputs of the sensor 101, i.e., a voltage corresponding to a brightest pixel, and the output voltage V A represents an average value between these voltages. The average value voltage V A is supplied to the binarization circuit through a changing circuit 53 as an initial value of the threshold level. A CPU 52 checks binary data supplied from the binarization circuit 104 in units of scan lines, and counts the number of pixels representing the widths 2w of the two bars, and the number of pixels representing the widths 2w of the two blank portions using a counter 52c to,compare them. As shown in Fig. 21, the width of the black bar is equal to that of the blank portion. Therefore, if it is determined that the width of the black bar is larger, this indicates that the threshold level is too high. If it is determined that the width of the blank portion is larger, this indicates that the threshold level is too low. Therefore, the CPU 52 generates data ±α representing an amount to be changed of the threshold level in accordance with the comparison result of the ratio of widths, and supplies it to the changing circuit 53. The changing circuit 53 adds/subtracts the data α from the CPU 52 to/from the present value of the threshold value to calculate a new threshold level. The new threshold level is used for binarizing analog electrical signals for the next image line in the binarizing circuit 104. Figs. 23A to 23F are timing charts of signals used in the respective sections of Fig. 20. A scan start signal a shown in Fig. 23A is output from a switch of the image sensor 101 upon starting of scanning of an image. An address reset signal b shown in Fig. 23B is a main scan start pulse, and goes to low level at the begining of serial outputting of analog electrical signals for one scan line read in the main scan period. A signal c in Fig. 23C is a clock for defining a data read timing, and is output from the image sensor 101 during the main scan period. Signals d in Fig. 23D are analog electrical signals serially output from the image sensor 101. The signals are sampled by the sample-hold circuit 103 at the trailing edge of the clock c (excluding a low-active period of the address reset signal b ). Signals e shown in Fig. 23E are image analog electrical signals sampled and held by the sample-hold circuit 103. Fig. 23F shows digital signals f obtained by binarizing the signals e . As can be seen from these timing charts, the image analog electrical signals for one main scan line include information of the corresponding portions of the bars 21. Therefore, when these signals are binarized, the widths of the bars 21 can be evaluated by obtaining run lengths of black and white pixels. If the ratio of the evaluated widths does not coincide with the known ratio of the widths of bars, the threshold level can be corrected to obtain a coincidence. Fig. 24 is a flow chart of threshold level changing processing. In step S1, the width of the black bar and the width of the blank portion are detected from the binary data of an image for one main scan line. In step S2, the detected widths are compared with each other. If these widths are equal to each other, since the threshold level is at a proper level, the value is maintained. If the width of the black bar is larger, this is caused by too high a threshold level. Thus, the threshold level is decreased by α (step S3). If the width of the black bar is smaller, this is caused by too low a threshold level. Thus, the threshold level is increased by α (step S4). The threshold level V A changed in this manner is used as a threshold value for binarizing image analog signals for the next main scan line. (Modification) Various changes and modifications of this embodiment may be made. For example, in the above embodiment, the output of the averaging circuit 51 is used as only the initial value of the threshold level. A threshold level for the entire image can be obtained on the basis of only the output of the averaging circuit 51. The averaging circuit 51 detects the voltages V H and V L to follow a sub-scan operation. For this reason, the average value signal V A of the voltages V H and V L is changed to follow a print density which varies depending on positions on the recording medium, thus obtaining a desired threshold level. In this arrangement, the known pattern need not be included in the image data, and data can be read at high speed with a simple arrangement. Contrary to this, the threshold level may be variably controlled so that a ratio of measured values of white and black bars always coincides with an actual ratio by utilizing only bars as the known patterns. An approach for correcting the threshold level to cause it to coincide with the known patterns allows more accurate data reading as compared to an arrangement for changing a threshold level based on an average value. A reference pattern for correcting the threshold level is not limited to patterns having a known width ratio. For example, a single bar whose width is known or marks each having a known size scattered in an image may be used (when an image is scanned in a predetermined direction). According to this embodiment, known reference patterns are distributed in an image to be recorded on a recording medium, and a threshold level for binarization is automatically changed so that the binarized data includes pattern data which coincides with the reference pattern. Therefore, accurate data reading can be performed regardless of recording quality of the recording medium. In this embodiment, an image includes patterns which have a predetermined ratio of widths of black and white bars, and an average value of image analog electrical signals obtained by averaging means is used as an initial value of the threshold level to binarize the image analog electrical signals. Every time signals for one scan line are binarized, the ratio of the widths of the black and white bars included in the binary data is measured, and the threshold level is corrected in accordance with the measurement result. For this reason, even when a scanning direction of an image is varied during an operation, accurate binarization can be performed.

Claims: A method for recording on a recording medium encoded data in the form of an image ( E1 ) which is comprised of a plurality of data cells so as to form a mesh pattern ( MP ) of said data cells, each said data cell consisting of a plurality of dots arranged in a dot pattern, each dot having one of two optical densities ( black/white ), each said data cell representing a binary ( 1-bit ) value, each said binary value being expressed by at least two different dot patterns, where the dot pattern used for each said binary value is chosen such that at the boundary between each cell and an immediately neighbouring cell there is at least one transition from a dot of one optical density in said each cell to a dot of the other optical density in said neighbouring cell. Method according to claim 1, comprising the steps of forming a first mark ( A-1, A-2 ) which indicates a vertical starting region of the data cells of said mesh pattern ( MP ) and of forming a second mark which indicates a boundary position of horizontally adjacent data cells of said mesh pattern ( MP ). Method according to claim 2, wherein said second mark is formed such that it is indicative of a horizontal data sampling position of said mesh pattern ( MP ). Method according to claim 2 or 3, wherein said second mark is constituted by at least one row of data cells in which data cells of different density are alternately arranged. Method according to one of claims 1 through 4, wherein a further mark ( A-1, A-2 ) is formed which is indicative of a vertical starting region of the data cells of said mesh pattern ( MP ). Method according to one of claims 1 through 5, wherein the data cells are formed of bars (21) of different densities having a predetermined ratio of widths. Method according to one of claims 1 through 5, wherein the data cells are formed of square cells comprised of four dots each of which has a predetermined optical density. A data recording medium for storing encoded data in the form of an image ( E1 ) which is comprised of a plurality of data cells so as to form a mesh pattern ( MP ) of said data cells, wherein said image ( E1 ) is recorded according to the method of one of claims 1 through 7. An apparatus for reading an image ( E1 ) which is formed on a data recording medium in compliance with one of claims 2 through 7, comprising: [a] image sensor means ( 1 ) for reading said image ( E1 ) and for generating an image signal; [b] vertical sampling position calculating means ( 2-1 through 2-9, G4) for calculating a vertical sampling position by detecting said first mark (A1, A2) within said image signal; [c] horizontal sampling position calculating means ( FF3, 9- 1, 9-2, ROM2 ) for calculating a horizontal data sampling position of said mesh pattern by detecting said second mark within said image signal; and [d] data sampling means ( 3, 9-5, G6 ) for sampling data within said image signal on the basis of data sampling coordinates defined by said calculated vertical and horizontal sampling positions. An apparatus according to claim 9, comprising data repairing means for repairing an incorrectly identified density of a dot by reversing the incorrectly detected optical density thereof based on a known dot pattern.

Inventors: CHIKAKIYO HIROSHI PAT DEP DEV, MATSUOKA TAKESHI PAT DEP DEV D, MORIKAWA SHIGENORI PAT DEP DEV, CHIKAKIYO, HIROSHI PAT. DEP. DEV. DIV. HAMURA R&D, MATSUOKA, TAKESHI PAT. DEP. DEV. DIV. HAMURA R&D, MORIKAWA, SHIGENORI PAT. DEP. DEV. DIV. HAMURA R&D, Chikakiyo, Hiroshi Pat. Dep. Dev. Div. Hamura R&amp;D, Matsuoka, Takeshi Pat. Dep. Dev. Div. Hamura R&amp;D, Morikawa, Shigenori Pat. Dep. Dev. Div. Hamura R&amp;D
Applicants: CASIO COMPUTER CO LTD, CASIO COMPUTER COMPANY LIMITED
Application year: 1989
Main classification: H04N1
IPC codes: G06K19, G06K7, G10H1