CHARGE COUPLED DEVICE

Abstract: A CCD is fabricated from an intermediate product comprising a body of semiconductor material having a channel region of a first conductivity type bounded by a substrate region of a second, opposite conduct­ ivity type and a surface of the body, and first and second gates overlying the surface and spaced from each other. The method comprises introducing a dopant into the channel region by way of the sur­ face of the body. The first and second gates are opaque with respect to the dopant. The dopant is such that it forms a zone within the channel region, beneath the space between the first and second gates, and the zone is of the first conductivity type and is of a higher doping concentration than other portions of the channel region. A third gate is formed over the surface of the body of semi­ conductor material, the third gate being at least partially disposed across the space between the first and second gates.

Description: The inventions relates to a charge-coupled device (CCD) comprising: a body of semiconductor material having a channel region of a first conductivity type bounded by a substrate region of a second, opposite conductivity type and a surface of the body, the body of semiconductor material having, within the channel region, a zone of said first conductivity type and of a different doping concentration, acting as having a higher doping concentration, than other portions of the channel region, and an electrode structure that overlies said surface and is composed of at least first, second, and third gates, the first and second gates being spaced from each other, and said zone of said first conductivity type being beneath the space between the first and second gates, and the third gate extending at least partially across the space between the first and second gates. A charge-coupled device of the above type is disclosed by C.K. Kim, "Two-Phase Charge Coupled Linear Imaging Devices With Self-Aligned Implanted Barrier", International Electron Device Meeting, 1974. This prior art charge-coupled device disclosed by C.K. Kim is a n-channel two-phase CCD in which alternate pairs of transfer gates are connected to two clock phases respectively. The gates are formed of polysilicon that has been deposited in two stages over a layer of gate oxide, so that each pair of gates comprises a lower level polysilicon gate and an upper level polysilicon gate. The upper level gates each have at least one edge region that partially overlaps an adjacent lower level gate. After the lower level polysilicon has been applied, and before the upper level polysilicon is applied, an implantation of a p-type dopant takes place. During this implantation, the lower level polysilicon serves as an implantation mask. The ions of the p-type dopant partially compensate the effect of the n-type dopant in the channel region. Accordingly, zones of n conductivity but having a lower net concentration of n-type dopant are formed in the channel region beneath the upper level gates, and form potential barriers between the n-type zones beneath the lower level gates. The width of the potential wells between the barriers depends on the width of the lower level gates. A charge-coupled device of the type mentioned in the above introductional paragraph is also disclosed by FR-A-2.227.646 (figure 4). In this prior art device the zone of different doping concentration is obtained by doping said zone with a higher concentration than other portions of the channel region. It is an object of the invention to elaborate the prior art charge-coupled device, as described in the introductional paragraph of this specification, and to provide it with means for diverting a charge beneath an intermediate one of said gates from beneath said gates. Then the charge-coupled device can be used in a serial-parallel-serial (SPS) analog shift register, for example of the type as described in US-A-4,725,748. In particular if the charge-coupled device is to be used in such SPS analog shift register it is a further object to attain a relatively short propogation time for a charge between the first gate and the second gate, and also to match this propogation time to a time to divert such charge from beneath the first gate to a place adjacent the third gate. According to the invention said objects are attained by the charge-coupled device described in claim 1. With the charge-coupled device disclosed by C.K. Kim the dopant that is generally used to form the p-type implant is boron. Under certain processing conditions, boron will diffuse from the implant through the gate oxide under the lower level polysilicon, resulting in threshold shifts which may adversely affect the operation and manufacturability of the device. Further it is known that in fabrication of integrated circuits, design rules for a given photolithographic process generally allow a lower minimum for the width of a space between conductor runs than for the width of conductor run. Therefore, in a preferred embodiment of the invention said zone is doped with a higher concentration than said other portions of the channel region, and the third gate partially overlaps the first and second gates. The invention will be described with reference to the accompanying drawings in which: Fig. 1A is a diagrammatic partial cross-sectional view of an SPS analog shift register based on a conventional two-phase CCD and illustrates the potential profile within the channel region, Fig. 1B shows a plan view of the juncture between the input register of the SPS shift register and one segment of the parallel register of the SPS shift register according to the present invention, Fig. 2A is a diagrammatic partial cross-sectional view of an SPS analog shift register based on an alternative two-phase CCD and illustrates the potential profile within the channel region, and Fig. 2B shows a plan view of the juncture between the input register of the SPS shift register and one segment of the parallel register of the SPS shift register according to the present invention. In the plan views shown in figs. 1B and 2B, the lower level gates are marked in solid lines, the upper level gates with dashed lines, and the buried channel region with dot-dashed lines. As shown in Fig. 1 of the drawings, a two-phase CCD of the kind shown by Kim may be used in an SPS shift register. The direction of charge transfer is indicated by the arrow 12. The juncture between the input serial register 2 and one of the segments 4 of the parallel register is at the location of a potential well 6 of the serial register. In order to allow high speed operation of the register, it is desirable that this well be small, so that the distance travelled by an electron passing through the well is short. The size of the well 6 depends on the size of the lower level polysilicon gate 8 that overlies the well 6 and thus forms a mask with respect to the p-type implantation 10 that froms the barrier between wells. Accordingly, the time taken for an electron entering the well along the path A to pass through the well in the serial direction depends on the distance X and the time taken for such an electron to make a corner turn from the serial direction to the parallel direction and enter the parallel register depends on the distance Y. In case of the CCD shown in fig. 2, the dopant that is implanted into the channel region after formation of the lower level gates is an n-type dopant. THe resulting doping concentration in the zones 20 beneath the upper level gates is higher than the doping concentration in other parts of the channel region. The doping concentration in the zones 20 may be about twice that in other parts of the channel region. Accordingly, a potential well is formed beneath the space between each pair of adjacent lower level gates while potential barriers are formed between adjacent wells. Thus the well 22 at the juncture between the serial register 24 and one of the segments 26 of the parallel register is formed beneath the space that is between the lower level gates 28, 30 of the serial register and is bounded by the first gate 32 of the parallel register. The time taken for an electron entering the well 22 along the path A' to pass through the well in the serial direction depends on the distance X', and the time taken for such an electron to make a corner turn from the serial direction to the parallel direction and enter the parallel register depends on the distance Y'. If the figs. 1 and 2 devices are fabricated using the same set of design rules, the well 22 of the Fig. 2 device can be made physically smaller, in directions parallel to the surface of the die, than the well 6 of the Fig. 1 device, so that the distances X' and Y' are smaller than the distances X and Y respectively, and accordingly the propagation time through the well 22 is shorter than the propogation time through the well 6. The n-type implant can be carried out using phosphorus, which avoids the problem associated with use of a boron implantation. It will be appreciated that the present invention is not restricted to the particular embodiment that has been described, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims For example, the invention is not limited to an SPS register and may be applied to other CCDs where narrow wells are desired, e.g., other high speed analog shift registers and high resolution imaging arrays.

Claims: Charge-coupled device (CCD) comprising: a body of semiconductor material having a channel region of a first conductivity type bounded by a substrate region of a second, opposite conductivity type and a surface of the body, the body of semiconductor material having, within the channel region a zone (20) of said first conductivity type and of a higher doping concentration than other portions of the channel region, and an electrode structure that overlies said surface and is composed of at least first (28), second (30), and third (22) gates, the first and second gates being spaced from each other, and said zone (20) of said first conductivity type being beneath the space between the first and second gates, and the third gate extending at least partially across the space between the first and second gates, the first and second gates being elongate and having a length component parallel to a predetermined direction characterized in that, the first and second gates have an end portion angled with respect to said predetermined direction, the electrode structure further comprising a fourth gate that extends transverse to said predetermined direction and is spaced from the angled end portions of the first and second gates, the third gate having a generally triangular shape defined by the angled end portions of the first and second gates, and the fourth gate. Charge-coupled device according to claim 1, wherein said zone is doped with a higher concentration than said other portions of the channel region, and the third gate partially overlaps the first and second gates. Charge-coupled device according to claim 1 or 2, wherein the first and second gates, comprise series register segments. Charge-coupled device according to any preceding claim, wherein the fourth gate comprises a parallel register segment.

Inventors: HAYES, RAYMOND, HEIDTMANN, DENIS LEE
Applicants: TEKTRONIX INC.
Application year: 1989
Main classification: H01L29
IPC codes: H01L21, H01L29