Reciprocal arithmetic circuit with ROM table

Abstract: A reciprocal arithmetic circuit for deriving the reciprocal of a divisor A includes a ROM table (21) for converting upper-bit data AH supplied as an address to the approximation of the reciprocal 1/AH² of the square thereof and outputting the same, a subtracter circuit (22) for deriving a difference (AH-AL) between the upper-bit data AH and the lower-bit data AL of the divisor A, and a multiplier circuit (23) for receiving an output (1/AH²) of the ROM table (21) and an output AH-AL) of the subtracter circuit and deriving the product 1/AH²·(AH-AL) thereof to make the output (1/AH²) of the ROM table more nearly equal to the reciprocal 1/A of the divisor A.

Description: This invention relates to a reciprocal arithmetic circuit for deriving a reciprocal 1/A of a divisor A, and more particularly to a reciprocal arithmetic circuit used in a divider circuit. In general, a division B/A is calculated by multiplying the reciprocal 1/A of a divisor A by a dividend B. A typical example of a divider circuit of performing the division B/A is shown in Fig. 1. In Fig. 1, 1 denotes a conversion table for converting the divisor A into the reciprocal 1/A and the conversion table is constituted by a read only memory (ROM). In Fig. 1, 2 denotes a multiplier circuit. All the bits of the divisor A are supplied as an address signal to the conversion table 1 and reciprocal table information straged in the conversion table 1 is searched for according to the address signal. However, in the all-bit or full-bit method in which all the bits of the divisor A are used, it is necessary for the ROM constituting the conversion table to have an extremely large memory capacity. For example, when the divisor A is of 16 bits and the reciprocal 1/A is expressed by 16 bits, the memory capacity of the ROM must be 2 16 words or 2 16 × 16 = 1 Mbits. In this way, in the full-bit method in which the reciprocal 1/A is derived by use of all the bits of the divisor A, a large ROM memory capacity is necessary, increasing the cost of a LSI in which the divider circuit is integrated. In general, an approximation arithmetic method using Newton's method is used as an arithmetic method of deriving the reciprocal 1/A with a small ROM memory capacity. In the above approximation arithmetic method, upper-digit bits AH of the divisor A are first input as an address signal to the conversion table and table information of the conversion table is searched for according to the address signal. As a result, the primary approximate reciprocal 1/AH of the divisor A can be derived. Next, the primary approximate reciprocal 1/AH is subjected to the approximation process of Newton's method to derive the secondary approximate reciprocal which is more precise than the primary approximate reciprocal. Now, the approximate calculation according to Newton's method is explained. Fig. 2 is a flowchart showing the approximate calculation according to Newton's method. First, upper m-bit data AH of the divisor A are used as an address signal to search for table information in the ROM, thus deriving the primary approximate reciprocal R0 = 1/AH (steps S1 to S3). Then, the secondary approximate reciprocal R1 is derived by use of the following approximate equation (steps S4 and S5): R1 = R0·(2-A·R0) Further, R1 is used instead of R0 in Eq. (1) to calculate the same. As the calculation process is repeatedly effected, the secondary approximate reciprocal R1 more approaches to the reciprocal 1/A of A. A counter C counts the number of calculations, and the calculation of Eq. (1) is repeatedly effected until the count of the counter C reaches a preset loop number N. Therefore, the secondary approximate reciprocal R1 becomes more nearly equal to the reciprocal 1/A of the divisor A as the loop number N becomes larger. Fig. 3 shows the relation between the bit number m of the upper-bit data AH, the size of the ROM constituting the conversion table and the loop number N in a case where the full-bit number of the divisor A is set to 16 bits. As is clearly understood from Fig. 3, the ROM size becomes smaller as the bit number m of the upper-bit data AH becomes smaller. In contrast, an error in the primary approximate reciprocal R0 becomes larger as the bit number m of the upper-bit data AH becomes smaller, thereby making it necessary to increase the loop number N. The approximate equation by Newton's method shown in Eq. (1) includes two multiplications. Therefore, in the approximate equation by Newton's method, it is necessary to effect multiplications of a number twice the loop number N. Since the multiplication is effected by repeatedly effecting additions, it takes a long time to effect the multiplication. Therefore, in the Newton's method, there occurs a problem that the loop number N becomes larger if the ROM size is reduced, and as a result time required for effecting the approximate calculation becomes larger. EP-A-0 149 248 shows a method and an apparatus for division using interpolation approximation, wherein the divisor and dividend are normalized in a normalization circuit. A plurality of approximate reciprocal divisors and differences between adjacent approximate reciprocal divisors are addressed by the high order bits of the normalized divisor. An approximate reciprocal divisor is changed into an interpolation approximated approximate reciprocal divisor in accordance with a plurality of bits following the high order bits and the difference. A multiplication unit multiplies the interpolation approximated approximate reciprocal divisor by the normalized divident to output a quotient. In GB-A-2 204 433 a method and appartus for deriving instantaneous reciprocals of the homogenous coordinate W is shown, wherein the digital value of W is split into a most significant bit section (MSB) and a least significant bit section (LSB). The MSB is used to address two look up tables to produce digital values of 1/W o and (1/W o ) 2 respectively. The delayed LSB section is multiplied with the (1/W o ) 2 value and the product subtracted from the 1/W o value. This emulates the truncated version of the Taylor series. An object of this invention is to provide a reciprocal arithmetic circuit in which a high-speed and highly precise reciprocal calculation can be effected and the hardware construction can be made simple. The object is achieved by a circuit as specified in independent claims 1 and 4. Further advantageous embodiments can be found in the subclaims. According to this invention, there is provided a reciprocal arithmetic circuit comprising conversion table means storing approximate information items corresponding to the reciprocals [(1/AH) 2 ] of the square of upper-bit data AH of divisors A, for converting the upper-bit data AH supplied as an address into the approximation of the squared reciprocal [(1/AH) 2 ] and outputting the approximation; subtracter means for deriving a difference (AH-AL) between the upper-bit data AH and lower-bit data AL of the divisor A; and multiplier means connected to receive an output [(1/AH) 2 ] of the conversion table means and an output (AH-AL) of the subtracter means, for deriving the product [(1/AH) 2 ·(AH-L)] thereof to make the output [(1/AH) 2 ] of the conversion table means more nearly equal to the reciprocal 1/A of the divisor A. In the reciprocal arithmetic circuit, a precalculation or the subtraction (AH-AL) is effected by the subtracter means using the lower-bit data AL prior to the calculation by multiplier means. Therefore, the approximate calculation for approximating the output [(1/AH) 2 ] of the conversion table means to the reciprocal 1/A of the divisor A can be effected by a simple operation of multiplying the output [(1/AH) 2 ) of the conversion table means by the output (AH-AL) of the subtracter means. Further, since the subtraction (AH-AL) by the subtracter means is effected while the conversion operation is being effected by the conversion table, the operation time is not increased because of the subtracting operation of the subtracter means. In this way, according to the reciprocal arithmetic circuit, the precalculation is effected by use of the lower-bit data AL prior to the approximate calculation and the high-speed reciprocal calculation can be effected by the simple hardware. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram showing the construction of an ordinary divider circuit; Fig. 2 is a flowchart for illustrating the approximate calculation method by using Newton's method; Fig. 3 is a diagram showing the relation between the ROM size and the number of calculations in a case where the approximate calculation method shown in Fig. 2 is effected; Fig. 4 is a block diagram showing a reciprocal arithmetic circuit according to a first embodiment of this invention; Fig. 5 is a flowchart showing the operation of the reciprocal arithmetic circuit shown in Fig. 4; Figs. 6A to 7B are diagrams showing the characteristics of the the approximate calculation effected by the reciprocal arithmetic circuit shown in Fig. 4; Fig. 8 is a block diagram showing a reciprocal arithmetic circuit according to a second embodiment of this invention; Fig. 9 is a block diagram showing the detail construction obtained by applying the principle of a correction process by the reciprocal arithmetic circuit according to the second embodiment of this invention to the reciprocal arithmetic circuit of Fig. 4 according to the first embodiment; Fig. 10 is a flowchart showing the correction process by the reciprocal arithmetic circuit shown in Fig. 9; Figs. 11A to 11C are diagrams showing the characteristics of the correction process effected by the reciprocal arithmetic circuit shown in Fig. 9; Fig. 12 is a block diagram showing a reciprocal arithmetic circuit according to a third embodiment of this invention; Fig. 13 is a flowchart showing the operation of the reciprocal arithmetic circuit shown in Fig. 12; Fig. 14 is a diagram showing the relation between the number of bits of the divisor A and the ROM size in the reciprocal arithmetic circuit shown in Fig. 12; Fig. 15 is a block diagram showing a reciprocal arithmetic circuit according to a fourth embodiment of this invention; Fig. 16 is a flowchart showing the operation of the reciprocal arithmetic circuit shown in Fig. 15; and Fig. 17 is a diagram showing the relation between the number of bits of the divisor A and the ROM size in the reciprocal arithmetic circuit shown in Fig. 15. Fig. 4 shows a reciprocal arithmetic circuit according to a first embodiment of this invention. The reciprocal arithmetic circuit derives an approximation of the reciprocal 1/A of the divisor A. First, the principle of the approximate calculation for deriving the approximation is explained. In order to obtain the approximation of the reciprocal of the divisor A, the divisor A is first divided into upper m-bit data AH and lower (n-m)-bit data AL. That is, the divisor A can be expressed by the following equation: A = AH+AL Assume that A is expressed as follows: A = a1·(1/2)+a2·(1/2) 2 +...+an·(1/2) n Then, the following equations can be obtained: AH = a1·(1/2)+a2·(1/2) 2 +...+am·(1/2) m AL = am+1·(1/2) m+1 +...+an·(1/2) n The approximation is derived as follows: First, the approximation R1 of the reciprocal 1/A can be expressed by the following equation: R1= 1 A = 1 AH+AL = AH-AL AH 2 -AL 2 In this case, assume the following condition: AH 2 >> AL 2 Then, the following approximation can be obtained: R1 ≃ ( 1 AH ) 2 · (AH-AL) Thus, the reciprocal arithmetic circuit of the first embodiment effects the approximate calculation expressed by Eq. (8). A ROM table 21 of Fig. 4 stores approximation information corresponding to the square reciprocals [(1/AH) 2 ] of the upper-bit data AH of divisors A. The ROM table 21 receives the upper m-bit data AH of the divisor A as an address signal, converts the data AH into the reciprocal [(1/AH) 2 ] of the square of the data AH and outputs the converted value. The output [(1/AH) 2 ] consists of n bits. A subtracter circuit 22 derives a difference (AH-AL) between the upper m-bit data AH and lower (n-m)-bit data AL. An output (AH-AL) of the subtracter circuit 22 consists of n bits. The output [(1/AH) 2 ] of the ROM table 21 and the output (AH-AL) of the subtracter circuit 22 are respectively supplied to first and second input terminals of a multiplier circuit 23. The multiplier circuit 23 multiplies the output [(1/AH) 2 ] of the ROM table 21 by the output (AH-AL) of the subtracter circuit 22, and the output R1 of the multiplier circuit 23 becomes (1/AH) 2 ·(AH-AL). The result is equal to Eq. (8) and R1 determined by the approximate calculation is the approximation of the reciprocal 1/A. In the approximate calculation, the approximation R1 can be made most nearly equal to the reciprocal 1/A when the bit number m of the upper-bit data AH is set to be larger than one half the bit number n of the divisor A, that is, m≧n/2. Fig. 5 is a flowchart showing the flow of the approximate calculation process of the reciprocal arithmetic circuit shown in Fig. 4. That is, table information is searched for according to the upper m-bit data AH of the divisor A supplied as an address signal and (1/AH) 2 is detected by the searching operation (steps S21 and S22). Then, (1/AH) 2 is used instead of R0 in the following equation (21). R1 = R0·(AH-AL) After this, Eq. (21) is calculated (step S24). R1 is the reciprocal approximation to be obtained in the first embodiment. Figs. 6A and 6B show the approximate calculation characteristics of the reciprocal arithmetic circuit of Fig. 4. That is, Fig. 6A shows the relation between the divisor A and the reciprocal 1/A in a case where the divisor A is increased in the step of (1/2) m . The line L1 in Fig. 6A shows an ideal relation therebetween and the line L2 shows a relation therebetween obtained by the approximate calculation of the reciprocal arithmetic circuit of the first embodiment. In Fig. 6B, the magnitude of the error in the reciprocal approximation obtained by the reciprocal arithmetic circuit of the first embodiment is shown. Figs. 7A and 7B are enlarged views respectively corresponding to Figs. 6A and 6B and show the approximate calculation characteristics in one step of variation in the divisor A or in that range of the divisor A which lies between (1/2)+(1/2) m and (1/2)+2(1/2) m . As is clearly seen from Fig. 7B, the magnitude of the error becomes smaller than 1 [LSB] when the lower-bit data AL satisfies that 0≦AL<AL1, it changes from 1 to 2 [LSB] inclusive when AL1≦AL<AL2, and it becomes larger than 2 [LSB] when AL2≦AL. Now, the reciprocal arithmetic circuit of the first embodiment is explained by comparing the reciprocal arithmetic circuit based on the Newton's method. In the approximate calculation by the Newton's method, it is necessary to effect two multiplications and one subtraction for each calculation loop as shown in Eq. (1). In contrast, the approximate calculation of the first embodiment can be effected by effecting one multiplication and one subtraction as shown by Eq. (8). Further, the subtraction in the first embodiment is previously effected prior to the multiplication while the conversion process of (1/AH) 2 is being effected by use of the ROM table 21. Therefore, all the necessary calculation time required for the actual approximate calculation is not increased because of the subtracting operation. In this way, the approximate calculation process can be simplified, the hardware for the calculation can be made simple in construction and the operation speed of the approximate calculation process can be enhanced. In a reciprocal arithmetic circuit according to a second embodiment to be described below, the function of detecting an error caused by the approximate calculation made in the first embodiment and correcting the reciprocal approximation R1 is further added. Fig. 8 schematically shows the reciprocal arithmetic circuit according to the second embodiment. As described with reference to Fig. 7B, the magnitude of an error in the reciprocal approximation R depends on the lower-bit data AL. For this reason, in the second embodiment, the range of the lower-bit data AL for the error of 2 [LSB] or more is previously stored into a ROM table 51 and the reciprocal approximation R1 is corrected when the value of the lower-bit data AL of the divisor A lies in the range stored in the ROM table 51. The determination whether or not the value of the lower-bit data AL of the divisor A lies in the error occurrence range stored in the ROM table 51 is made by means of a comparison circuit 53. Further, the correction process for the reciprocal approximation R1 is effected by adding or subtracting a correction value D to or from R1 by use of adder/subtracter circuit 55. Fig. 9 shows the detail construction obtained by applying the second embodiment to the first embodiment shown in Fig. 4. As shown in Fig. 9, an error correction circuit 61 includes a ROM table 59 and a comparison circuit 60. The ROM table 59 stores the error occurrence range of the lower-bit data AL which is determined based on the error characteristics (see Figs. 6B and 7B) of the reciprocal arithmetic circuit of the first embodiment. That is, the ROM table 59 stores that value AL1 of the lower-bit data which causes an error of 2 [LSB] and that value AL2 of the lower-bit data which causes an error of 3 [LSB] together with the corresponding input upper-bit data AH. The comparison circuit.60 compares the each value of the lower-bit data AL1, AL2 output from the ROM table 59 with the value of the lower-bit data AL of the divisor A to detect the error occurrence range to which the lower-bit data AL belongs. For example, when the comparator 60 detects that the lower-bit data AL belongs to the range of 0≦AL<AL1, it generates the correction value D of "0" since the magnitude of the error is less than 1 [LSB]. Further, when it is detected that the lower-bit data AL lies in the range of AL1≦AL<AL2, the comparator 60 generates the correction value D of "-1" since the magnitude of the error lies between 1 [LSB] and 2 [LSB] and it is necessary to make the error less than 1 [LSB]. When it is detected that the lower-bit data AL lies in the range of AL2≦AL, the comparator 60 generates the correction value D of "-2" since the magnitude of the error is more than 2 [LSB]. Next, the operation of the reciprocal arithmetic circuit of Fig. 9 is explained with reference to a flowchart shown in Fig. 10. First, the upper-bit data AH of the divisor A is input as an address signal to the ROM table 21 to read out (1/AH) 2 from the ROM table 21 (steps S51 and S52). Likewise, the upper-bit data AH is input to the ROM table 59 to read out the value AL1, AL2, ---, ALd of the lower-bit data which may cause an error from the ROM table 59 (step S53). In this case, AL1 is the minimum value of the lower-bit data AL which causes an error of 2 [LSB], AL2 is the minimum value of the lower-bit data AL which causes an error of 3 [LSB] and ALd is the minimum value of the lower-bit data AL which causes an error of d+1 [LSB]. The comparator circuit 60 compares the value AL1, AL2, ---, ALd with the lower-bit data AL of the divisor A to determine the error occurrence range (0≦AL<AL1, AL1≦AL<AL2, or ALd≦AL) to which the lower-bit data AL belongs (steps S541 to S54d). Then, in order to make the error of the approximate calculation less than 1 [LSB], the correction value D is determined according to the error occurrence range to which AL belongs (steps S551 to S55d). Next, a calculation of R0·(AH-AL) is made by an operation circuit 23' with the output (1/AH) 2 of the ROM table 21 used as R0 (steps S56 and S57). Figs. 11A to 11C show the characteristics of the approximate calculation operation of the reciprocal arithmetic circuit of Fig. 9. That is, the approximate calculation characteristic prior to the correction process is shown by a line L2 and the ideal characteristic is shown by a line L1 in Fig. 11A. Fig. 11B shows the error characteristic prior to the correction process and Fig. 11C shows the error characteristic after the correction process. As is clearly seen from Fig. 11C, the error after the correction process becomes less than 1 [LSB] and the approximate reciprocal R1 becomes equal to the true reciprocal 1/A obtained in the fraction cutoff mode. R1 = 1/A = 1 AH+AL = 1 AH 3 +AL 3 · (AH 2 -AH·AL+AL 2 ) Assuming that AH 3 >>AL 3 , then the following expression can be obtained: R1 ≃ 1 AH 3 · (AH 2 +AH·AL+AL 2 ) In the third embodiment, the approximate calculation shown in Eq. (19) is effected according to the flowchart shown in Fig. 13 so as to derive an approximation R1. A reciprocal arithmetic circuit of the third embodiment shown in Fig. 12 includes a ROM table 71, selectors 72 to 74, a multiplier circuit 75, an adder/subtracter circuit 76 and an accumulator 77. The ROM table 71 stores approximation information of the cubes (1/AH) 3 of the reciprocals of the upper-bit data AH of divisors A. In the reciprocal arithmetic circuit, the upper-bit data AH is first selected by means of the selectors 72 and 73, a calculation of (AH·AH+0) is made by the multiplier circuit 75 and adder/subtracter circuit 76, and the calculation result is stored as ACC0 into the accumulator 77. Next, the lower-bit data AL is selected by means of the selectors 72 and 73 and an output of the accumulator 77 is selected by means of the selector 74. As a result, an operation of (AL·AL+ACC0) is effected by use of the multiplier circuit 75 and the adder/subtracter circuit 76 and the operation result is stored as ACC0 into the accumulator 77. Then, the upper-bit data AH is selected by means of the selector 72, the lower-bit data AL is selected by means of the selector 73, and an output of the accumulator 77 is selected by means of the selector 74. As a result, an operation of (ACC0-AH·AL) is effected by use of the multiplier circuit 75 and adder/subtracter circuit 76 and (AH 2 +AL 2 -AH·AL) is newly stored as ACC0 into the accumulator 77. Next, an output of (1/AH) 3 of the ROM table 71 is selected by means of the selector 72 and an output of the accumulator 77 is selected by means of the selector 73. Therefore, an operation of ACC0·(1/AH) 3 +0 is effected by means of the multiplier circuit 75 and the adder/subtracter circuit 76 and the operation result is stored as ACC0 into the accumulator 77 again. As a result, the same operation result as that of Eq. (19) can be obtained in the accumulator 77. Fig. 14 shows the relation between the bit number n of the divisor A and the bit number m of the upper-bit data AH, and in the fourth embodiment, m=3 bits when n=8 bits, for example. That is, in the third embodiment, it becomes possible to reduce the number of bits to be input to the ROM table in comparison with the approximation process using the full-bit method and Newton's method mentioned before, thereby making it possible to reduce the memory capacity of the ROM table. Fig. 15 shows a reciprocal arithmetic circuit according to the fourth embodiment of this invention. First, the principle of the calculation of the approximation R1 in the fourth embodiment is explained. R1 = 1/A = 1 AH+AL = 1 AH 4 +AL 4 · (AH-AL)·(AL 2 +AL 2 ) Assuming that AH 4 >>AL 4 , the following expression can be obtained: R1 ≃ (1/AH) 4 ·(AH-AL)·(AH 2 +AL 2 ) In the fourth embodiment, the approximation R1 of the reciprocal 1/A can be derived by effecting the approximate calculation of Eq. (20) according to the flowchart of Fig. 16. The reciprocal arithmetic circuit according to the fourth embodiment shown in Fig. 15 includes a ROM table 81, selectors 82 to 84, a multiplier circuit 85, an adder/subtracter circuit 86, and accumulators 87 and 88. The ROM table 81 stores approximation information of reciprocals (1/AH) 4 of the upper-bit data AH of divisors A to the fourth power. In the reciprocal arithmetic circuit, the upper-bit data AH is first selected by means of the selectors 82 and 83, a calculation of AH 2 is made by the multiplier circuit 85, and AH 2 is stored as ACC0 into the accumulator 87. Next, the lower-bit data AL is selected by means of the selectors 82 and 83, a calculation of AL 2 is made by the multiplier circuit 85, and AL 2 is stored as ACC1 into the accumulator 88. Then, an operation of (ACC0+ACC1) is effected by use of the adder/subtracter circuit 86 and (AH 2 +AL 2 ) is newly stored as ACC0 into the accumulator 87. Next, an operation of (AH-AL) is effected by use of the adder/subtracter circuit 86 and the operation result is stored into the accumulator 88. Next, an output of (1/AH) 4 is read out from the ROM table 81 and then an operation of ACC1·(1/AH) 4 is effected by means of the multiplier circuit 85 and the operation result is newly stored as ACC1 into the accumulator 88 again. Then, a multiplication (ACC1·ACC0) of data in the accumulators 87 and 88 is effected by means of the multiplier circuit 85. As a result, the same operation result as that of Eq. (20) can be obtained in the accumulator 88. Fig. 17 shows the relation between the bit number n of the divisor A and the bit number m of the upper-bit data AH, and in the fourth embodiment, AH=2 bits when n=8 bits, for example. That is, in the fourth embodiment, it becomes possible to reduce the number of bits to be input to the ROM table in comparison with the approximation calculation process using the full-bit method and Newton's method mentioned before, thereby making it possible to reduce the memory capacity of the ROM table. As is clearly understood by comparing Figs. 14 and 17, the memory capacity of the ROM table for generating (1/AH) 4 can be made smaller than that of the ROM table for generating (1/AH) 3 . This is because the converting precision of the approximate calculation shown in Eq. (20) is higher than that of the approximate calculation shown in Eq. (19) (1/AH) 3 . As described above, according to this invention, a reciprocal arithmetic circuit in which the hardware can be made simple and whose operation speed and operation precision are enhanced can be obtained.

Claims: A reciprocal arithmetic circuit comprising: conversion table means (21) for storing approximate information items corresponding to the reciprocals [(1/AH) 2 ] of the squares of m upper-bit data AH of each of a plurality of divisors A and converting the m upper-bit data AH supplied as an address into the approximation of the squared reciprocal [(1/AH) 2 ] and outputting said approximation consisting of n bits; subtracter means (22) for deriving a difference (AH-AL) between the m upper-bit data AH and (n-m) lower-bit data AL of the divisor A; whereby m ≧ n / 2 and creating an output of n bits and multiplier means (23) connected to receive said output [(1/AH) 2 ] of said conversion table means (21) and said output (AH-AL) of said subtracter means (22), for deriving the product thereof to make the output [(1/AH) 2 ] of said conversion table means more nearly equal to the reciprocal 1/A of the divisor A. A reciprocal arithmetic circuit according to claim 1, characterized in that said conversion means (21) includes a ROM. A reciprocal arithmetic circuit according to claim 1, further comprising an error occurrence range storing table (51) for storing error occurrence ranges of the (n-m) lower-bit data AL corresponding to the respective m upper-bit data AH and outputting the error occurrence range of the lower-bit data AL corresponding to the upper-bit data AH when the upper-bit data AH is supplied as an address, an error component which is included in the approximation output from said conversion table means (21) being larger than a predetermined value in each of the error occurrence ranges; and correction means (53) for determining whether or not the lower-bit data AL of the divisor A lies in the error occurrence range of the lower-bit data AL output from said error occurrence range storing table (51) and correcting the output of said multiplier means (23) upon detecting that the lower-bit data AL of the divisor A lies in said error occurrence range. A reciprocal arithmetic circuit comprising: conversion table means (71) for storing approximate information items corresponding to the reciprocals [(1/AH) 3 ] of the cubes of m upper-bit data AH of each of a plurality of divisors A and converting the m upper-bit data AH supplied as an address into the approximation of the cube [(1/AH) 3 ] of the reciprocal thereof and outputting said approximation; pre-processing means (74, 76, 77) for effecting a calculation of (AH 2 -AH·AL+AL 2 ) based on the m upper-bit data AH and (n-m) lower-bit data AL of the divisor A and creating an output thereof; and approximation calculation means (75) for multiplying said output of said conversion table means (71) by said output of said pre-processing means (75, 76, 77) to make the output (1/AH) 3 of said conversion table means more nearly equal to the reciprocal 1/A of the divisor A. A reciprocal arithmetic circuit comprising: conversion table means (81) for storing approximate information items corresponding to the reciprocals [(1/AH) 4 ] of m upper-bit data AH of each of a plurality of divisors A to the fourth power and converting the m upper-bit data AH supplied as an address into the approximation of the reciprocal [(1/AH) 4 ] of AH to the fourth power and outputting said approximation; pre-processing means (85, 86, 87, 88) for effecting a calculation of (AH-AL)·(AH 2 +AL 2 ) based on the m upper-bit data AH and (n-m) lower-bit data AL of the divisor A and creating an output thereof; and approximation calculation means (85) for multiplying said output of said conversion table means (81) by said output of said pre-processing means (85, 86, 87, 88) to make the output (1/AH) 4 of said conversion table means (81) more nearly equal to the reciprocal 1/A of the divisor A.

Inventors: YAMAGUCHI AKIRA, YAMAGUCHI, AKIRA, YAMAGUCHI, AKIRA C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G06F1
IPC codes: G06F1, G06F7