Transfer circuit for signal lines

Abstract: A transfer circuit for signal lines comprises a bipolar transistor (QB₁₁) and two MIS transistors (e.g. QP₄₁ , QN₄₃). A base of the bipolar transistor is connected to a first line(DB₁) of the signal lines, a collector of the bipolar transistor is connected to a power source (V CC ), the two MIS transistors are connected in series, the connected point is connected to an emitter of the bipolar transistor (QB₁₁), and one end of the series-connected MIS transistors is connected to the first line (DB₁) and the other end is con­ nected to a second line (DB) of the signal lines. When data on the first line (DB₁) is transferred to the second line (DB) , the MIS transistor (QP₄₁) connected between the base and emitter of the bipolar transistor (QB₁₁) is made non-conductive and the other MIS transistor (QN₄₃) connected to the second line(DB) is made conductive. The transfer circuit constituted as above can carry out data transfer of the signal lines at a high speed by rapidly charging the second line (DB).

Description: The present invention relates to a transfer circuit for signal lines and utilized, for example, for selectively transferring data on one of a plurality of local data buses to a common data bus. In a static random access memory (SRAM), a memory cell array is divided into a plurality of blocks, to obtain a low power consumption or a high speed processing. In this case, one of a plurality of local buses connected to the memory cell array block must be selected and the data thereon transferred to a common data bus. This selection and transfer are carried out by a transfer gate circuit. In a transfer circuit for signal lines using a transfer gate, since all of the transistors are MIS (metal insulator semiconductor) transistors, the resistance in a conductive state is relatively high, the overdrive voltage is low, and the local data bus has a large electrostatic capacity due to the connection of many memory cells. Therefore, a time constant for a charge in the bus is long, and a problem arises in that it takes a long time to transfer data from the local data bus to the common data bus. It is therefore desirable to provide a high speed operating transfer circuit for signal lines. According to the present invention, there is provided a transfer circuit for controlling a signal transfer between a first signal line and a second signal line in response to a control signal comprising a first MIS transistor including a first electrode connected to the first signal line, a second electrode, and a gate electrode; a second MIS transistor including a first electrode connected to the second electrode of the first MIS transistor, a second electrode connected to the second signal line, and a gate electrode; and a bipolar transistor including a base electrode connected to the first signal line, a first electrode connected to a power supply line, and a second electrode connected to the first electrode of the second MIS transistor; the gate electrodes of the first MIS transistor and the second MIS transistor being controlled in response to the control signal such that the first MIS transistor and the second MIS transistor operate in a complementary manner. Thus, the present invention may provide a high speed transfer circuit for signal lines by using a bipolar transistor and MIS transistors. Reference is made, by way of example, to the accompanying drawings in which:- Figure 1 is a partial circuit diagram of a static random access memory, explaining an application example of a transfer circuit for signal lines; Fig. 2 is a partial circuit diagram of a static random access memory, explaining a prior-proposed transfer circuit for signal lines; Fig. 3 is a partial circuit diagram of a static random access memory, explaining a transfer circuit for signal lines according to a first embodiment of the invention; Fig. 4 is a circuit diagram of a transfer circuit for signal lines according to a second embodiment of the present invention; Fig. 5 is a circuit diagram of a transfer circuit for signal lines according to a third embodiment of the present invention; Fig. 6 is a circuit diagram of a transfer circuit for signal lines according to a fourth embodiment of the present invention; and Fig. 7 is a waveform diagram in the transfer circuit for the signal lines shown in Fig. 3. Prior to an explanation of embodiments of the present invention, a static random access memory (SRAM) wherein transfer circuits for signal lines are applied is explained with reference to Fig. 1. In Fig. 1, blocks BLK₁ and BLK₂ enclosed by broken lines are divided into memory cell array blocks (shown as a partially abbreviated diagram). Each block comprises memory cells (MC's) as memory elements, and in each block, one column is selected by column selection circuits controlled by signals CA₀ to CA n from a decoder, and one word line (WL₀ to WL m ) is selected by the decoder. Then, data is read from an MC arranged at a cross point of the word line and a pair of bit lines (e.g. one pair of BL₀ , BL ₀; to BL n , BL n ) selected by the column selection circuit, and the data is supplied to a common data bus (DB, DB ) through a local data bus (e.g. one pair of DB₁ , DB ₁; DB₂ , DB ₂; etc.). The common data bus is connected to a sense amplifier SA and the data is output as D out through an data output buffer OB. Here, a transfer circuit for signal lines must be provided to selectively connect the plurality of local data buses and the common data bus. In Fig. 1, the transfer circuit for signal lines comprises transistors Q₂₁ , Q₂₂ , Q₃₁ , and Q₃₂ , which are controlled by a signal BS₁ or BS₂. Write data (D in ) for this SRAM is supplied to write amplifiers (WRITE AMP 1 and 2) through a data-in buffer (DATA-IN BUF) and data bus (DBW, DBW ). One memory cell array block is selected by the selection of a write amplifier controlled by a control signal (WS₁ or WS₂) and the data is supplied to the selected MC through the local data bus. A prior-proposed transfer circuit for signal lines is explained with reference to Fig. 2. Figure 2 shows a portion of the SRAM in Fig. 1 in detail. In Fig. 2, the same elements as in Fig. 1 are denoted by the same reference characters. Data from each MC is supplied to local data buses (DB₁ , DB ₁; DB₂ , DB ₂) through a transfer gate circuit TG B , which comprises transistors Q₁₁ and Q₁₂ , and one of the transfer gate circuits (TG₁ , TG₂) is selected by a block selection control signal (BS₁ or BS₂) and is made conductive to the common data bus as a transfer circuit for signal line. The TG₁ comprises MIS transistors Q₂₁ and Q₂₂ , and each transistor is made conductive by the block selection control signal BS₁. MIS transistors Q₂₃ and Q₂₄ are used to apply a voltage, e.g., Vcc (5 volts), through an effective resistance, so that a floating state thereof does not exist when the local bus is at the non-selection state. The transfer gate TG₂ comprises MIS transistors Q₃₁ and Q₃₂ , the power source voltage Vcc is connected to the local data bus (DB₂ , DB ₂) through MIS transistors Q₃₃ and Q₃₄ , and the operation thereof is the same as that of the TG₁. In this type of transfer circuit for signal lines, since the resistance of the MIS transistors Q₂₁ , Q₂₂ , Q₃₁ , and Q₃₂ does not become completely zero in the conductive state thereof, the memory cell having a small power supply capacity cannot charge the common data bus with a large amount of electric current in a short time, and thus the bus transfer time cannot be shortened. A transfer circuit for signal lines according to a first embodiment of the invention is explained with reference to Fig. 3. Note, in Fig. 3, a portion of the SRAM is abbreviated as in Fig. 2. A memory cell is a memory element in the SRAM as shown in Figs. 1 and 2 and is a flip-flop circuit shown at the top of Fig. 3. The memory cell, for example, comprises four MIS transistors and two resistors, and two series-connected resistors and transistors are arranged in parallel between the power source and ground. A drain of one of the transistors is cross-connected to a gate of another transistor, and vice versa. The gate of each transistor is connected to a MIS transistor to be selected by a word line (WL) and to be connected to a respective bit line. A pair of bit lines (BL₀ , BL ₀) is connected to a local data bus (DB₁ , DB ₁) through a transfer gate circuit TG B , which comprises transistors Q₁₁ and Q₁₂ as a column selection circuit. Another pair of bit lines from another memory cell array block is connected to a local data bus (e.g. DB₂ , DB ₂) in the same way. The local data bus (DB₁ , DB ₁) is connected to the common data bus through a transfer gate circuit TG₁₁ , according to the first embodiment of the invention, and a selection signal BS ₁ makes the transfer gate circuit conductive or disconnects same. The local data bus (DB₂ , DB ₂) and the local data bus belonging to other blocks are connected and controlled in the same way. In the following description, the transfer gate circuit TG₁₁ (transfer circuit assembly) is explained. The TG₁₁ comprises a symmetrical circuit for transmitting a complementary pair of signals. Here, only a half of the symmetrical circuit is explained, but the other half thereof is exactly the same. The half circuit comprises a bipolar transistor (QB₁₁ or QB₁₂), an n channel MIS transistor (QN₃₁ or QN₃₂), and a p channel MIS transistor (QP₃₃ or QP₃₄). one of the local data bus signal lines DB₁ is connected to a base of the NPN type bipolar transistor QB₁₁; a collector of the transistor QB₁₁ is connected to the power source Vcc; a source of the transistor QN₃₁ is connected to a source of the transistor QP₃₃; a gate of the transistor QN₃₁ is connected to a gate of the transistor QP₃₃; a drain of the transistor QN₃₁ is connected to the base of the transistor QB₁₁; and, a drain of the transistor QP₃₃ is connected to the common data bus DB. For another signal line DB ₁ of the local data bus, the transistor QB₁₁ is replaced by the transistor QB₁₂ , the transistor QN₃₁ is replaced by the transistor QN₃₂ , the transistor QP₃₃ is replaced by the transistor QP₃₄ , and the drain of the transistor QP₃₄ is connected to the common data bus DB . The remaining circuit constitution of the another signal line of the local data bus is the same as that of one of the local data bus signal lines. Note, the interconnected MIS transistor gates are supplied with the selection signal BS ₁. Also, the above-mentioned circuit constitution is applied to the transfer gate circuit TG₁₂ to which the local data bus (DB₂ , DB ₂) is connected, as for TG₁₁. If the line to be transferred is not complementary to a bus line but is an individual line, a half circuit application in the symmetrical circuit is sufficient. An operation of this circuit of the first embodiment is now explained. When data is transferred from the local data bus to the common data bus, the selection signal BS ₁ is at a "low" level, the n channel MIS transistors QN₃₁ and QN₃₂ are OFF, and the p channel MIS transistors QP₃₃ and QP₃₄ are ON (conductive). The data signal on the local data bus DB₁ is applied to the base of the transistor QB₁₁ , the current is amplified, and the data is transferred to the common data bus DB instantly through the emitter of the transistor QB₁₁ and the transistor QP₃₃. Similarly, a data signal on the local data bus DB ₁ is applied to the base of the transistor QB₁₂ , the current is amplified, and the data is transferred to the common data bus DB instantly through the emitter of the transistor QB₁₂ and the transistor QP₃₄. When the data transfer is inhibited, the selection signal BS ₁ is at a high level, the n channel transistors QN₃₁ and QN₃₂ are ON, and the p channel transistors QP₃₃ and QP₃₄ are OFF. Accordingly, the transistor Q₁₁ and QB₁₂ are made OFF by a short circuit between the base and emitter thereof, and thus the data signals from the local data bus (DB₁ , DB ₁) are completely disconnected. In the above operation, since the transistor QN₃₁ is short circuited during the non-selection time, delay of the conductive operation at the next step is prevented due to the absence of an emitter voltage higher than the base voltage in the transistor QB₁₁. The bipolar transistor QB₁₁ amplifies the signal current from the MC by using an emitter follower, the transistor QP₃₃ supplies the electric current from the transistor QB₁₁ to the common data bus DB when the transfer circuit for signal lines is in a selection state, and the transistor QP₃₃ disconnects the signal from the MC so that the signal from the bus DB₁ does not reach the bus DB when the transfer circuit is in a non-selection state. The common data bus is connected to a sense amplifier SA, and the data is output through an output buffer circuit. A pull-down circuit PD is connected to the common data bus. This circuit PD comprises two MIS transistors Q₁₅ and Q₁₆ , and a drain of the transistor Q₁₅ is connected to the common data bus DB and a drain of the transistor Q₁₆ is connected to the common data bus DB . Sources of the transistors Q₁₅ and Q₁₆ are grounded and bases of the transistors Q₁₅ and Q₁₆ are connected to the power source V₁ or Vcc. The circuit PD lowers the bus voltage when the voltage of the common data bus is changed from high to low. The channel widths of the transistors Q₁₅ and Q₁₆ are made narrower than that of the MIS transistor QP₃₃ or the like. Assuming that the voltage levels of connecting points between the sources of the transistors QN₃₁ and QP₃₃ and between the sources of the transistors QN₃₂ and QP₃₄ are A and B, respectively, as shown in Fig. 3, the voltage levels of the connecting points, of the local data bus (DB₂ , DB ₂) and of the common data bus (DB , DB ) are as shown in Fig. 7. The waveforms in Fig. 7 are generated when a high level of the selection signal is transferred from BS ₂ to BS ₁. In Fig. 7, the axis of the ordinates shows a voltage (volt) and the quadrature axis shows the time (t). When using the above-mentioned circuit, since the current of the data signal through the local data bus is amplified, the common data bus is charged by a large amount of electric current, and thus the transfer time for the data becomes very short and a high speed transfer is possible. A circuit diagram of a transfer circuit for signal lines according to a second embodiment of the invention is shown in Fig. 4. This circuit comprises two NPN type bipolar transistors QB₁₁ and QB₁₂ , two p channel MIS transistors QP₄₁ and QP₄₂ , and two n channel MIS transistor QN₄₃ and QN₄₄. The local data bus DB₁ is connected to the base of the transistor QB₁₁ and a drain of the transistor QP₄₁ , and the collector of the transistor QB₁₁ is connected to the power source Vcc. Sources of the transistors QP₄₁ and QN₄₃ are interconnected and the connecting point is connected to the emitter of the transistor QB₁₁ , and a drain of transistor QN₄₃ is connected to the common data bus DB. Gates of the transistors QP₄₁ and QN₄₃ are interconnected and are applied with a selection signal BS. The local data bus DB ₁ is connected to the base of the transistor QB₁₂ and a drain of the transistor QP₄₂ , the collector of the transistor QB₁₂ is connected to the power source Vcc, sources of the transistors QP₄₂ and QN₄₄ are interconnected and the connecting point is connected to the emitter of the transistor QB₁₂ , and a drain of the transistor QN₄₄ is connected to the common data bus DB . Gates of the transistors QP₄₂ and QN₄₄ are interconnected and are applied with a selection signal BS. In this circuit, during the selection (i.e. the signal BS is high level), the transistors QP₄₁ and QP₄₂ are OFF and the transistors QN₄₃ and QN₄₄ are ON. The operation of this circuit is the same as that of the first embodiment. A circuit diagram of a transfer circuit for signal lines according to a third embodiment of the invention is shown in Fig. 5. This circuit comprises two NPN type bipolar transistors QB₁₁ and QB₁₂ and four n channel MIS transistors QN₅₁ , QN₅₂ , QN₅₃ , and QN₅₄. The local data bus DB₁ is connected to the base of the transistor QB₁₁ and a drain of the transistor QN₅₁ , the collector of the transistor QB₁₁ is connected to the power source Vcc, sources of the transistors QN₅₁ and QN₅₃ are interconnected and the connecting point is connected to the emitter of the transistor QB₁₁ , and a drain of the transistor QN₅₃ is connected to the common data bus DB. A gate of the transistors QN₅₁ is supplied with the signal BS , and a gate of the transistor QN₅₃ is supplied with the signal BS (inverted BS signal). The local data bus DB ₁ is connected to the base of the transistor QB₁₂ and a drain of the transistor QN₅₂ , the collector of the transistor QB₁₂ is connected to the power source Vcc, sources of the transistors QN₅₂ and QN₅₄ are interconnected and the connecting point is connected to the emitter of the transistor QB₁₂ , and a drain of the transistor QN₅₄ is connected to the common data bus DB . A gate of the transistor QN₅₂ is supplied with the selection signal BS and a gate of the transistor QN₅₄ is supplied with the selection signal BS. In this circuit, during the transfer State (i.e. the signal BS is high and the signal BS is low level), the transistors QN₅₁ and QN₅₂ are OFF and the transistors QN₅₃ and QN₅₄ are ON. The operation of this circuit is the same as that of the first embodiment. A circuit diagram of a transfer circuit for signal lines according to a fourth embodiment of the invention is shown in Fig. 6. This circuit comprises two NPN type bipolar transistors QB₁₁ and QB₁₂ and four p channel MIS transistors QP₆₁ , QP₆₂ , QP₆₃ , and QP₆₄. The local data bus DB₁ is connected to the base of the transistor QB₁₁ and a drain of the transistor QP₆₁ , the collector of the transistor QB₁₁ is connected to the power source Vcc, sources of the transistors QP₆₁ and QP₆₃ are interconnected and the connecting point is connected to the emitter of the transistor QB₁₁ , and a drain of the transistor QP₆₃ is connected to the common data bus DB. A gate of the transistor QP₆₁ is supplied with the selection signal BS, and a gate of the transistor QP₆₃ is supplied with the selection signal BS . The local data bus DB ₁ is connected to the base of the transistor QB₁₂ and a drain of the transistor QP₆₂ , the collector of the transistor QB₁₂ is connected to the power source Vcc, sources of the transistors QP₆₂ and QP₆₄ are interconnected and the connecting point is connected to the emitter of the transistor QB₁₂ , and a drain of the transistor QP₆₄ is connected to the common data bus DB . A gate of the transistor QP₆₂ is supplied with the selection signal BS and a gate of the transistor QP₆₄ is supplied with the selection signal BS . In this circuit, during the transfer state the transistors QP₆₁ and QP₆₂ are OFF and the transistors QP₆₃ and QP₆₄ are ON. The operation of this circuit is the same as that of the first embodiment. In the above-mentioned description of the embodiments, a pair of transfer circuits is used with transfer buses supplied with a pair of complementary signals, but this transfer circuit for signal lines can function using only one of the pair of circuits, to transfer data from one signal line to another signal line.

Claims: A transfer circuit for controlling a signal transfer between a first signal line (DB1, DB1 ) and a second signal line (DB, DB ) in response to a control signal (BS, BS ), comprising: a first MIS transistor (QN31, QP41, QN51, QP61) including a first electrode connected to the first signal line, a second electrode, and a gate electrode; a second MIS transistor (QP33, QN43, QN53, QP63) including a first electrode connected to the second electrode of the first MIS transistor, a second electrode connected to the second signal line, and a gate electrode; and a bipolar transistor (QB11) including a base electrode connected to the first signal line, a first electrode connected to a power supply line, and a second electrode connected to the first electrode of the second MIS transistor; the gate electrodes of the first MIS transistor and the second MIS transistor being controlled in response to the control signal such that the first MIS transistor and the second MIS transistor operate in a complementary manner. A transfer circuit as set forth in claim 1, wherein the bipolar transistor is an NPN type transistor. A transfer circuit as set forth in claim 1 or 2, wherein the first MIS transistor is an n channel type transistor and the second MIS transistor is a p channel type transistor. A transfer circuit as set forth in claim 1 or 2, wherein the first MIS transistor is a p channel type transistor and the second MIS transistor is an n channel type transistor. A transfer circuit as set forth in claim 1 or 2, wherein the first MIS transistor and the second MIS transistor are n channel type transistors. A transfer circuit as set forth in claim 1 or 2, wherein the first MIS transistor and the second MIS transistor are p channel type transistors. A transfer circuit as set forth in any preceding claim , further comprising a pull-down circuit connected to the second signal line. A transfer circuit as set forth in claim 7, wherein the pull-down circuit comprises an MIS transistor having a drain connected to the second line a source connected to a ground line or second power supply line, and a gate to which is supplied a voltage at a level such that the MIS transistor has a higher resistance value than that of the second MIS transistor in the conductive state. A transfer circuit as set forth in any preceding claim , further comprising: a third MIS transistor including a first electrode connected to a third signal line, a second electrode, and a gate electrode connected to the gate electrode of the first MIS transistor; a fourth MIS transistor including a first electrode connected to the second electrode of the third MIS transistor, a second electrode connected to a fourth signal line, and a gate electrode connected to the gate electrode of the second MIS transistor; and another bipolar transistor including a base electrode connected to the third signal line, a first electrode connected to the power supply line, and a second electrode connected to the first electrode of the fourth MIS transistor; whereby, complementary signals are transferred between the first and second signal lines and the third and fourth signal lines.

Inventors: KOSHIZUKA ATUO, KOSHIZUKA, ATUO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: G11C7
IPC codes: H03K17, G11C11, G11C7