Direct memory access controller

Abstract: A direct memory access controller adaptable to control a direct memory access transfer in a data processing system which includes at least a central processing unit (13, 50) and a system bus (20), comprises a register (11, 18) coupled to the system bus for outputting a transfer terminate request signal which instructs a normal termination when the central processing unit is operating and a write operation is carried out with respect to the register from the central processing unit, and a transfer termination part (12) coupled to the register for stopping to accept a new transfer request signal or stopping to generate a transfer request signal responsive to the transfer termination request signal so as to make an instructed channel inactive.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to direct memory access controllers, and more particularly to a direct memory access controller which controls a direct memory access between an input/output control unit and a memory or between two memories. FIG.1 shows a data processing system which includes an example of a conventional direct memory access controller (hereinafter simply referred to as a DMAC). The data processing system has a DMAC 1, a central processing unit (CPU) 2, an input/output control unit 3, and memories 4 and 5 which are coupled via a system bus 6 which includes an address bus, a data bus and a control bus. When making a desired data processing on this data processing system, a data transfer is made between the input/output control unit 3 and the memory 4 or 5 or between the memories 4 and 5. In order to improve a data transfer rate of the data transfer, a direct memory access (DMA) transfer is made between the input/output control unit 3 and the memory 4 or 5 or between the memories 4 and 5 by hardware and not through the CPU 2. This DMA transfer is controlled by the DMAC 1 so that the DMA transfer takes place during a time when the CPU 2 does not make access to the system bus 6 or by stopping the operation of the CPU 2. When making the DMA transfer, it is desirable that the DMA transfer can be terminated with an arbitrary timing. When controlling the data transfer between the input/output control unit 3 and the memory 4 or 5 by the conventional DMAC 1, the data transfer is started responsive to a transfer request signal REQ from the input/output control unit 3 and the data transfer is terminated in a normal termination at an intermediate stage of the data transfer responsive to an interrupt request signal DONE from the input/output control unit 3. The data transfer between the memories 4 and 5 can be started responsive to a trigger signal which is continuously generated within the DMAC 1. However, the memories 4 and 5 do not have the function of generating the interrupt request signal DONE. For this reason, once the DMAC 1 starts the DMA transfer, there is a problem in that it is impossible to terminate the DMA transfer at an intermediate stage of the data transfer in a normal termination unless an abnormality such as a bus error occurs. On the other hand, a Japanese Laid-Open Patent Application No.61-133460 discloses a method of interrupting the DMA transfer at an intermediate stage of the data transfer by a terminate signal which is supplied directly from the input/output control unit to the DMAC via a signal line which is provided exclusively for the terminate signal. In this case, the DMAC stops operating responsive to the terminate signal which is supplied directly to the DMAC and not through the CPU which carries out the main control of the data processing system. For this reason, the CPU may not be aware that the DMAC has stopped operating. As a result, this method introduces problems when it is necessary to make some kind of a decision or discrimination in the CPU before stopping the operation of the DMAC. EP-A-0 108 415 discloses a direct memory access controller according to the preamble of accompanying claim 1. According to the present invention, there is provided a direct memory access controller adaptable to control a direct memory access transfer in a data processing system which includes at least one central processing unit, at least one system bus, and a register means coupled to the system bus, characterized in that: said register means is arranged for outputting a transfer terminate request signal which instructs a normal termination when the central processing unit is operating and a write operation is carried out with respect to said register means from the central processing unit; and in that said direct memory access controller further comprises: transfer termination means coupled to said register means for stopping to accept a new transfer request signal or stopping to generate a transfer request signal responsive to said transfer terminate request signal so as to make an instructed direct memory access transfer inactive. An embodiment of the present invention may provide a novel and useful DMAC in which the above-mentioned problems of the prior art are reduced or eliminated. Reference is made, by way of example, to the accompanying drawings in which: Fig. 1 is a system block diagram showing a data processing system including an example of a conventional DMAC; Fig. 2 is a system block diagram showing an essential part of a data processing system including a DMAC according to the present invention for explaining an operating principle thereof; FIG.3 is a system block diagram showing an embodiment of the DMAC according to the present invention; FIG.4 is a system block diagram showing an embodiment of a request handler of the DMAC shown in FIG.3; FIG.5 is a flow chart for explaining the operation of the DMAC shown in FIG.3; and FIGS.6A and 6B are system block diagrams respectively showing data processing systems to which the DMAC according to the present invention may be applied. DETAILED DESCRIPTION First, a description will be given of an operating principle of a DMAC according to the present invention by referring to FIG.2. In FIG.2, a DMAC 10 is coupled to a CPU 13, and this DMAC 10 includes a register 11 and a transfer termination means 12. The register 11 outputs a transfer terminate request signal which instructs a normal termination of a data transfer when the CPU 13 writes an information requesting a termination of the data transfer in the register 11. The transfer termination means 12 stops accepting a new transfer request signal or stops generating a transfer request signal responsive to the transfer terminate request signal, and makes an instructed DMA channel inactive. Even when a DMA transfer is started, the transfer termination means 12 stops accepting a new transfer request signal or stops generating a transfer request signal when the CPU 13 writes the above described information in the register 11. For this reason, it is possible to terminate the DMA transfer in a normal termination at an intermediate stage of the data transfer regardless of whether or not the DMA transfer involves a memory or the like having no function of generating a normal termination request signal. FIG.3 shows an embodiment of the DMAC 10. The DMAC 10 has a request handler 15, a microsequencer 16, and a data handler 17. A system bus 20 has a data bus 20a, an address bus 20b, and a control bus 20c. The DMAC 10 may be applied to a data processing system shown in FIG.6A, for example. In FIG.6A, the data processing system includes a CPU 50, memories 51 and 52, an input/output control unit 53 and the DMAC 10 which are coupled via the system bus 20. The request handler 15 receives transfer request signals REQ0 through REQ3 of channels "0" through "3" from the input/output control unit 53, and outputs a process request signal OPE and an operation channel number CH depending on a predetermined priority. In addition, the request handler 15 receives an interrupt request signal DONE from the input/output control unit 53 if needed, and outputs a process request signal OPE indicative of the interrupt request. Furthermore, as will be described later, the request handler 15 also outputs a process request signal OPE which instructs a normal termination responsive to a terminate request signal CLS received from the data handler 17. The microsequencer 16 stores microprograms and and renews an address, byte number and the like required for the DMA transfer depending on the process request signal OPE and the operation channel number CH received from the request handler 15. The microsequencer 16 also outputs a control signal CTRL which is supplied to the data handler 17. The data handler 17 has an internal register 18 which corresponds to the register 11 shown in FIG.2. The data handler 17 makes access to the data bus 20a and the address bus 20b depending on the operation channel number CH and the control signal CTRL. At the same time, the data handler 17 outputs control signals such as a read/write signal, and these control signals are outputted on the control bus 20c. When an access is made to an internal register such as the register 18 of the data handler 17 by a chip select signal CS which is received from the CPU 50 through the control bus 20c, the data handler 17 makes a data write operation or a data read operation with respect to a selected internal register of the data handler 17. A data from the data bus 20a is written into the selected internal register of the data handler 17 by the data write operation, and a stored data is read out from the selected internal register of the data handler 17 by the data read operation. The request handler 15 generates the process request signal OPE for terminating the DMA transfer, and FIG.4 shows an embodiment of the request handler 15. The request handler 15 includes a register part 23, a sample and hold circuit 24, a sampling control circuit 25, an operation priority determination part 26, a process request signal output part 27, a channel priority determination part 28, a channel output part 29, and a clear control circuit 30. For example, the register part 23 stores a cycle steal mode, a burst mode and a request generation information, and a sampling mode of the sample and hold circuit 24 is set depending on such information stored in the register part 23. The cycle steal mode refers to a mode where a DMA transfer is made using a time interval in which the CPU 50 does not make an access to the system bus 20. The burst mode refers to a mode where a data transfer is made by stopping the CPU 50. In this burst mode, a discrimination is made every time to determine whether or not a next request for DMA transfer exists, and the DMA transfer is made continuously when the next request for DMA transfer exists. Further, the request generation information refers to an information which indicates whether an external transfer request is to be received or a transfer request is to be self- generated within the DMAC 10. The sample and hold circuit 24 samples and holds one of the terminate request signal CLS, the transfer request signal REQ (REQ0 through REQ3) and the interrupt request signal DONE responsive to a sample instruction signal from the sampling control circuit 25, and supplies the sampled and held signal to the operation priority determination part 26. When signals are received at the same time, the operation priority determination part 26 determines the priorities of the signals according to a predetermined sequence and supplies the priorities to the process request signal output part 27 and the channel priority determination part 28. The priorities are also supplied to the channel output part 29 through the channel priority determination part 28 and is supplied to the microsequencer 16 and the data handler 17 as the operation channel number CH. The process request signal output part 27 supplies process request signals OREQ and OCODE to the microsequencer 16. These request signals OREQ and OCODE correspond to the process request signal OPE. The following Table shows the relationship of the value of the process request signal OCODE and the content of the process request. Value of OCODE Content of Process Request 00 START 01 ABORT 10 CLOSE 11 IRA In the Table, "START" indicates an instruction to start a DMA transfer, "ABORT" indicates an abnormal termination instruction based on an external request which is entered via a signal line other than the system bus 20, "CLOSE" indicates a normal termination instruction at an intermediate stage of the DMA transfer, and "IRA" indicates an instruction when an illegal register access is made. The illegal register access occurs when a write operation is made with respect to an internal register of the DMAC 10 in a state where the DMAC 10 is operating and no rewriting of the internal register should be made. In FIG.4, OACK and ACTCLR respectively denote process terminate signals received from the microsequencer 16. The process terminate signal OACK is supplied to the sampling control circuit 25 and the clear control circuit 30, while the process terminate signal ACTCLR is supplied to the clear control circuit 30. The process terminate signals OACK and ACTCLR are respectively entered when terminating the process. But although the process terminate signal OACK is entered every time each of a plurality of processes terminate during a time in which the channel is active, the process terminate signal ACTCLR is only entered at a time when the processes as a whole terminates. The register part 23 is cleared by an output signal of the clear control circuit 30 when the processes as a whole terminates. Next, a description will be given of the operation of the embodiment shown in FIG.3 by referring to a flow chart shown in FIG.5 and the block system shown in FIG.4. For the sake of convenience, it is assumed that a DMA transfer is made directly between the two memories 51 and 52 and not via the CPU 50. In this state where the DMA transfer is made, the CPU 50 outputs the chip select signal CS responsive to an external interrupt request. In a step S1, the CPU 50 discriminates whether or not a write operation is made with respect to the register 18 within the data handler 17 for instructing an interrupt request responsive to the chip select signal CS. When the discrimination result in the step S1 becomes YES, the data handler 17 in a step S2 supplies the terminate request signal CLS to the request handler 15 as described before in conjunction with FIG.3. Accordingly, in a step S3, the request handler 15 stops accepting the transfer request signal REQ and outputs the process request signal OPE for making a normal termination (interruption) of the process. In other words, the request handler 15 stops the operation of sampling and holding a new transfer request signal REQ in the sample and hold circuit 24 shown in FIG.4 after the terminate request signal CLS is received, and the process request signal output part 27 outputs the normal termination instruction signal indicated as "CLOSE" in the Table described before responsive to the terminate request signal CLS. In a step S4, the microsequencer 16 makes the instructed channel inactive. The processes of the steps S3 and S4 are realized by the transfer termination means 12 shown in FIG.2. Therefore, even when the data processing system has such a system structure that the memory cannot generate the interrupt request signal during the DMA transfer between two memories, it is possible to make a normal interruption of the DMA transfer as if the interrupt request signal DONE is generated, by making a write operation with respect to the register 18 from the CPU 50. In the described embodiment, the register 18 is an internal register of the data handler 17. However, it is of course possible to provide the register 18 within the request handler 15, for example. In addition, instead of stopping the acceptance of the new transfer request signal REQ as described above, it is also possible to stop the generation of the transfer request signal REQ within the DMAC 10. On the other hand, the DMAC 10 is also applicable to a data processing system having two mutually independent system buses as shown in FIG.6B. In FIG.6B, those parts which are basically the same as those corresponding parts in FIG.6A are designated by the same reference numerals, and a description thereof will be omitted. In FIG.6B, the CPU 50 is coupled to a system bus 20 1 , and the DMAC 10 is coupled to both system buses 20 1 and 20 2 . The memories 51 and 52 and the input/output control unit 53 are coupled to the system bus 20 2 .

Claims: A direct memory access controller adaptable to control a direct memory access transfer in a data processing system which includes at least a central processing unit (13, 50), at least one system bus (20, 20 1 , 20 2 ), and a register means (11) coupled to the system bus, characterized in that: said register means (11) is arranged for outputting a transfer terminate request signal which instructs a normal termination when the central processing unit is operating and a write operation is carried out with respect to said register means from the central processing unit; and in that said direct memory access controller further comprises: transfer termination means (12) coupled to said register means for stopping to accept a new transfer request signal or stopping to generate a transfer request signal responsive to said transfer terminate request signal so as to make an instructed direct memory access transfer inactive. The direct memory access controller as claimed in claim 1, wherein said data processing system includes mutually independent system buses (20 1 , 20 2 ), and said central processing unit (50) is coupled to one of the mutually independent system buses, and said register means (11) is coupled to both of the mutually independent system buses. The direct memory access controller as claimed in claim 1 or 2, wherein said register means (11) outputs the transfer terminate request signal at an intermediate stage of a direct memory access. The direct memory access controller as claimed in any of claims 1 to 3, which further comprises: a request handler (15) outputting a process request signal and an operation channel number in response to a transfer request signal and outputting a process request signal instructing a normal termination in response to an interrupt request signal; a microsequencer (16) storing microprograms for updating an address and a byte number required for a direct memory access and generating a control signal based on the process request signal and the operation channel number received from said request handler; a data handler (17) making access to the system bus in response to the operation channel number received from said request handler and the control signal received from said microsequencer and generating a read/write signal; and a register (11, 18), included in said register means (11), which is accessible by the central processing unit through the system bus, said register outputting a transfer terminate request signal which instructs a normal termination when the central processing unit is operating and a predetermined information is written in said register from the central processing unit. The direct memory access controller as claimed in claim 4, wherein said request handler (15) includes said transfer termination means (12). The direct memory access controller as claimed in claim 4 or 5, wherein an access is made to said register (11, 18) from the central processing unit (13, 50) when said data handler (17) receives a chip select signal from the central processing unit. The direct memory access controller as claimed in claim 4, 5 or 6, wherein said data handler (17) generates a termination request signal when the predetermined information is written in said register (11, 18), said termination request signal being supplied to said request handler (15) to stop accepting a new transfer request signal. The direct memory access controller as claimed in any of claims 4 to 7, wherein said microsequencer (16) makes an instructed channel inactive in response to the process request signal and the operation channel number outputted from said request handler (15) responsive to said transfer terminate request signal. The direct memory access controller as claimed in any of claims 4 to 8, wherein said register means (11) is provided within said data handler (17).

Inventors: FUJIHIRA ATSUSHI, OGAWA HARUNOBU, TANIAI TAKAYOSHI, FUJIHIRA, ATSUSHI, OGAWA, HARUNOBU, TANIAI, TAKAYOSHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: G06F13
IPC codes: G06F13