Apparatus for providing distance protection and distance measurement for a high voltage transmission line

Abstract: A protective relay for detecting faults in electrical power distribution system generates a signal Δi(t) which is substantially equal to the magnitude of the power distribution system current i measured at a first time subtracted from the magnitude of the power distribution system current i measured at a second time, the second time occurring later than the first time. The signal Δi(t) is utilized to generate measurement of the distance of a fault to the relay and is also utilized to generate operate signals if the fault occurs within the zone protected by the relay.

Description: BACKGROUND OF THE INVENTION The present invention relates to protective systems for use in AC electrical power distribution systems and more particularly to distance relays for AC electrical power transmission line protection. Distance relays are well known in the art of protective relaying. For example, reference may be had to "The Art and Science of Protective Relaying", Mason, published by John Wiley and Son, Inc. (1956), particularly to Chapter 14. Exemplary types of distance relays are disclosed in U.S. Patent No. 4,034,269, issued to S. B. Wilkinson, on July 5, 1977; U.S. Patent No. 4,420,788, issued to S. B. Wilkinson and G. E. Alexander on December 13, 1983; and U.S. Patent No. 4,405,966, issued to Leonardo Cavero, the inventor of the present invention, on September 20, 1983. Distance relays are utilized in protective systems for AC power transmission lines to detect faults within protected zones or portions of the transmission lines. If such a fault is detected within the relay's zone or reach, the distance relay will enable operation of a circuit breaker in order to trip the faulted phase or phases. Phase distance relays are utilized to detect phase to phase faults within a protected zone or portion of a transmission line. If such a fault is detected within the zone or reach of this type of distance relay, the phase distance relay will initiate a signal which will be used to cause the operation of a three pole circuit breaker to trip all three phases of the transmission line. This is to be contrasted with a ground distance relay which detects faults between a phase and ground, again within a designated zone or reach; and, upon detection of such a fault, generates a signal which enables the operation of a circuit breaker to trip the faulted phase only. As indicated above, each particular distance relay should only detect faults within its protected zone or reach. The parameters of a distance relay are commonly selected to correspond to the parameters of the transmission line. For example, the parameters are selected to provide a forward reach that may correspond to the forward distance of the protected zone of a transmission line under protection of the particular relay. It is desired that the distance relay operate within its selected forward reach thereby confining the protection of a particular distance relay to the selected zone within a protected system. The desired operation of the distance relay may be hindered by the inability to distinguish between internal and external faults. Internal faults are those which occur within the protected zone or reach of the relay, whereas external faults are those which occur outside the zone or relay reach. For example, errors in measuring fault resistance can cause the fault to appear further away from or closer to the distance relay location than it actually is; situations which, in the worse case, could prevent the operation of the distance relay on a fault occurring within its zone or reach, or could cause the relay to misoperate for a fault external to the protected zone or reach. Although distance relays have, in the past, been used to detect faults within a predetermined protected zone or reach of the relay, such relays have not been able to provide a determination of the actual location of the fault; that is, the distance from the relay at which the fault occurred. The ability to determine the location of the fault in terms of distance from the relay enhances the utility of a distance relay. FR-A-2538122 discloses a protective relay for detecting faults in an electrical power distribution system, said relay comprising the features (a) to (d) specified in the pre-characterising portion of claim 1. Nevertheless, improvements are desirable to improve discrimination between internal and external faults and to increase the reliability of operation and security of the protection system. The present invention provides a protective relay for detecting faults in an electrical power distribution system, said relay comprising: (a) means for receiving signals from an electrical power distribution system, which signals relate to at least one system voltage v and at least one system current i; (b) means for generating a signal di dt which is substantially equal to a first derivative with respect to time of said system current; (c) means for generating a signal v r which is substantially equal to the sum of a line resistance R of said power distribution system multiplied by said system current i and a line inductance L multiplied by said di dt signal; (d) means for generating a signal Δi which is substantially equal to the magnitude of the system current i measured at a first time subtracted from the magnitude of the system current i measured at a second time, said second time occurring later than said first time; characterised by (e) means for generating a signal d Δ i dt which is substantially equal to a first derivative with respect to time of said Δi signal; (f) means for generating a signal i f which is substantially equal to the sum of the signal Δi plus the signal d Δ i dt multiplied by a scaling function having a predetermined magnitude; (g) means for generating signals v(t₁), v r (t₁) and i f (t₁) which are substantially equal to the magnitude of the signals v, v r and i f respectively occurring at a first time t₁; (h) means for generating signals v(t₂), v r (t₂) and i f (t₂) which are substantially equal to the magnitude of the signals v, v r and i f respectively occurring at a second time t₂, which second time occurs later than said first time; (i) means for generating a signal S₁ which is substantially equal to the signal v r (t₁) multiplied by the signal i f (t₂) minus the signal v r (t₂) multiplied by the signal i f (t i ); (j) means for generating a signal S₂ which is substantially equal to the signal v(t₁) multiplied by the signal i f (t₂) minus the signal v(t₂) multiplied by the signal i f (t₁); (k) means for providing a signal n set having a predetermined magnitude; and (l) means for generating an output signal O₁ when the magnitude of the signal n set multiplied by the signal S₁ is greater than the magnitude of the signal S₂. Embodiments of the invention seek to provide one or more of the following features: a distance relay with improved discrimination between internal and external faults thereby increasing the reliability of the relay operation and the security of the protection system; a distance relay for detecting faults in a protected zone of an AC electrical power transmission line, which relay determines the distance to the fault; a distance relay with a capability for improved fault resistance determination; a distance relay which substantially eliminates the adverse effects on fault distance determination due to fault current components from multiple sources connected to the AC power transmission line; a distance relay which eliminates adverse effects of prefault load current on fault distance determination. The invention, both as to its organization and operation, may be better understood by reference to the following illustrative description in conjunction with the accompanying drawing figures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a one line, block diagram of a current and voltage processing portion of a preferred embodiment of the present invention. Figure 2 is a block diagram of a first operate signal generation portion of the preferred embodiment of the present invention, utilizing voltage and current signals generated by that portion depicted in Figure 1. Figure 3 is a block diagram of a distance measurement portion of the preferred embodiment of the present invention, utilizing voltage and current signals generated by the portion depicted in Figure 1. Figure 4 is a block diagram of a second operate signal generation portion of the preferred embodiment of the present invention, utilizing voltage and current signals generated by that portion depicted in Figure 1. Figure 5 is a block diagram of a trip signal generation portion of the preferred embodiment of the present invention, utilizing the first and second operate signals generated by that portion depicted in Figures 2 and 4 respectively. Figure 6 depicts the characteristic of the preferred embodiment of the relay of the present invention plotted on an L-R diagram. Figure 7 is a block diagram of a third operate signal generation portion of the preferred embodiment of the present invention, utilizing a delta current signal generated by that portion depicted in Figure 1 and signals generated by the second operate signal generation portion depicted in Figure 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Figure 1, there is shown an alternating current electric power transmission line, generally designated 10. Although such alternating current electrical power transmission lines normally comprise three phases and ground, for purposes of simplicity and clarity, the following detailed description will be described with respect to the A phase (A) and ground (G). It should be understood that the following description also applies with respect to the B and the C phase, as well as relays connected between phases. Associated with A phase is means 12 for sensing current in that phase as well as means 14 for sensing voltage on that phase. As is well known to those skilled in the protective relaying and power transmission art, current sensing means 12 may be a current transformer and voltage sensing means 14 may be a step down potential transformer. Also, a current sensing means may be associated with each phase as well as a separate voltage sensing means associated with each phase. However, it is to be understood that although a specific type of current and voltage sensing scheme is depicted in Figure 1, other schemes known in the art may be substituted for that depicted; the purpose being to obtain signals which are related to each phase voltage and each phase current. The output from the current sensing means 12, which is a signal i A (t) proportional to the current flowing in the A phase, is coupled to the input of a first low pass filter 16. The output of the voltage sensing means 14, which is a signal v A (t) proportional to the phase A to ground voltage, is coupled to the input of a second low pass filter 18. In the preferred embodiment, the first 16 and second 18 low pass filters each preferably have a frequency cut off of approximately 500Hz in order to filter out transients and other spurious signals having frequencies which exceed 1KHz, while passing, substantially unchanged, signals at the system frequency which is typically 50Hz or 60Hz. Consequently, the output signal i A (t) from the first filter 16 is the filtered input signal i A (t), and the output signal v A (t) from the second filter 18 is the filtered input signal v A (t). The output v A (t) of the second low pass filter 18 is coupled to the input of a first analog to digital (A/D) converter 20. In the preferred embodiment, the first A/D converter 20 samples the magnitude of the input signal at a predetermined rate which in the preferred embodiment, is twenty samples per cycle in 50Hz systems and sixteen samples per cycle in 60 Hz systems. The magnitude of each sample is converted into a digital signal having a value corresponding to such magnitude. Consequently, the output v A (t) of the first A/D converter 20 is a digitized version of the analog input signal. The output of the first low pass filter 16 is coupled to a second A/D converter 22 which is of the same type and performs the same function as that previously described with respect to the first A/D converter 20. The output i A (t) of the second A/D converter 22, which is a digitized version of the input signal, is coupled to the input of a buffer 24, a positive input of a first digital subtraction circuit 26, the input of a first differentiator 28, and the input of a first scaler 30. In the preferred embodiment, the buffer 24 comprises a memory for storing the digitized input signal i A (t) for a time k/f where k is a predetermined constant and f is the system frequency, typically 50 Hz or 60 Hz. Accordingly, the output of the buffer 24 is the signal i A (t-k/f). When k=1, the output of the buffer 24 is equal to the magnitude of i A at a point one cycle prior to the input i A (t). In the preferred embodiment, the output i A (t-k/f) of buffer 24 is the input signal i A (t) which has been delayed five cycles at the fundamental system frequency; that is, 100 milliseconds in a 50Hz system and 83.333 milliseconds in a 60Hz system. The output i A (t-k/f) of the buffer 24 is coupled to a negative input of the first digital subtraction circuit 26. In the preferred embodiment, the first digital subtraction circuit 26 is a circuit whose output is a digital signal Δ i A (t) having a digital value equal to the magnitude of the digital value of the input signal applied to the positive input minus the value of the signal applied to the negative input. Since the signal i A (t) is applied to the positive input and the signal i A (t-k/f) is applied to the negative input, the output signal, Δi A (t) is equal to i A (t)-i A (t-k/f). The output Δi A (t) of the digital subtraction circuit 26 is coupled to the input of a second differentiator 32 and one input of a first two-input adder 34. In the preferred embodiment, the first 28 and second 32 differentiators each measures and stores the magnitude of the input signal at a first time t₁ and again at a second time t₃, then subtracts the magnitude measured at t₁ from the magnitude measured at t₃ and divides the result by the magnitude of time t₃ minus time t₁. Consequently, the output of the second digital differentiator 32 is a signal d Δ i A (t) dt at a time t₂, having a value substantially equal to the differential, with respect to time, of the input signal Δi A (t). The output of the second digital differentiator 32 is coupled to the input of a second scaler 36. The second scaler 36 is a circuit whose output is a digital signal having a magnitude equal to the input signal d Δ i A (t) dt multiplied by a predetermined scaler function which, in the preferred embodiment is tan α 2 π f , where f is the fundamental system frequency, typically 50Hz or 60Hz, and tan α is a quantity which is a function of the particular power system in which the distance relay of the present invention is used. Consequently the output of the second scaler 36 is d Δi A (t). dt tan α . 2 π f The output of the second scaler 36 is coupled to the second input of the first two-input adder 34. The first two-input adder 34 is a circuit whose output is a digital signal i f (t) having a magnitude which is equal to the digital sum of the input signals which are Δi A (t) and d Δ i A (t) . dt tan α. 2 π f Consequently, the output i f (f) of the first two-input adder 34 is equal to Δi A (t)+d Δ i A (t) dt · tan α. 2 π f The output of the first differentiator 28 is a digital signal di A (t) dt whose magnitude is the differential respect to time of the input signal i A (t). The output di A (t) dt of the first differentiator 28 is coupled to the input of a third scaler 38. The third scaler 38 is of the same type as that previously described with respect to the first 30 and second 36 scalers, having a digital output signal whose magnitude is equal to the input di A (t) dt multiplied by a predetermined scaling function which, in the preferred embodiment, is L. Consequently, the output of the third scaler 38 is L di A (t) dt . The magnitude of L is selected to be substantially equal to the line inductance per mile of the particular power system in which the relay of the present invention is used. The output L di A (t) dt of the third scaler 38 is coupled to one input of a second two input adder 40. The output of the first scaler 30 is a digital signal whose magnitude is equal to the input signal i A (t) multiplied by a predetermined scaling function which, in the preferred embodiment, is R. Consequently, the output of the first scaler 30 is Ri A (t). The magnitude of R is selected to be substantially equal to the line resistance per mile of the particular power system in which the relay of the present invention is used. The output Ri A (t) of the first scaler 30 is coupled to the second input of the second two input adder 40. The second two input adder 40 is the same type as that previously described with respect to the first two input adder 34, having an output signal whose magnitude is equal to the sum of the inputs Ri A (t) and L di A (t). dt Accordingly, v r (t) is equal to Ri A (t)+L di A (t). dt Referring now to Fig. 2, the output signal i f (t) from the first two-input adder 34 (see Fig. 1) is coupled to the input of a first sampler/buffer circuit 42. The output v r (t) from the second two-input adder 40 (see Fig. 1) is coupled to the input of a second sampler/buffer circuit 44. The output v A (t) of the first A/D converter 20 (see Fig. 1) is coupled to the input of a third sampler/buffer circuit 46. In the preferred embodiment, the first 42, second 44 and third 46 sampler/buffer circuits each have two outputs, the first of which is equal to the magnitude of the input signal sampled at a first time t₁, and the second of which is equal to the magnitude of the input signal sampled at a second time t₂. Consequently, the outputs of the first sampler/buffer circuit 42 is a first signal i f (t₁) which is the input signal i f (t) sampled at time t₁; and the second output is a signal i f (t₂) which is equal to the input signal i f (t) sampled at time t₂. Similarly, the outputs of the second sampler/buffer circuit 44 comprise a first signal v r (t₁) which is equal to the input signal v r (t) sampled at the first time t₁; and a second signal v r (t₂) which is equal to the input signal v r (t) sampled at the second time t₂. The outputs of the third sampler/buffer circuit 46 comprise a first signal v A (t₁) which is equal to the input signal v A (t) sampled at the first time t₁; and a second signal v A (t₂) which is equal to the input signal v A (t) sampled at the second time t₂. The output signal i f (t₁) from the first sampler/buffer circuit 42 is coupled to one input of a first two-input multiplier 48 and one input of a second two-input multiplier 50. The output signal i f (t₂) from the first sampler/buffer circuit 42 is coupled to one input of a third two-input multiplier 52 and one input of a fourth two-input multiplier 54. The output signal v r (t₁) from the second sampler/buffer circuit 44 is coupled to the second input of the third two-input multiplier 52. The output signal v r (t₂) from the second sampler/buffer circuit 44 is coupled to the second input of the first two-input multiplier 48. The output signal v A (t₁) from the third sampler/buffer circuit 46 is coupled to the second input of the fourth two-input multiplier 54. The output signal v A (t₂) from the third sampler/buffer circuit 46 is coupled to the second input of the second two-input multiplier 50. In the preferred embodiment, the first 48, second 50, third 52 and fourth 54 two-input multipliers are each digital multipliers producing a digital output signal having a magnitude which is equal to the magnitude of the first input signal multiplied by the magnitude of the second input signal. Consequently, the output of the first multiplier 48 is the signal v r (t₂)i f (t₁); the output of the second multiplier circuit 50 is the signal v A (t₂)i f (t₁); the output of the third multiplier 52 is the signal v r (t₁)i f (t₂); and the output of the fourth multiplier 54 is the signal v A (t₁)i f (t₂). The output of the first multiplier circuit 48 is coupled to a negative input of a second digital subtraction circuit 60. The output of the second multiplier circuit 50 is coupled to a negative input of a third digital subtraction circuit 62. The output of the third multiplier circuit 52 is coupled to a positive input of the second digital subtraction circuit 60. The output of the fourth multiplier circuit 54 is coupled to a positive input of the third digital subtraction circuit 62. In the preferred embodiment the second 60 and third 62 digital subtraction circuits are of the same type as the previously described first digital subtraction circuit 26, each producing a digital output signal whose magnitude is equal to the magnitude of the signal applied to the positive input minus the magnitude of the signal applied to the negative input. Consequently, the output of the second digital subtraction circuit 60 is the signal S₁ which is is equal to v r (t₁)i f (t₂)-v r (t₂)i f (t₁); and the output of the third digital subtraction circuit 62 is the signal S₂ which is equal to v A (t₁)i f (t₂)-v A (t₂)i f (t₁). The output signal S₁ from the second digital subtraction circuit 60 is coupled to the input of a fourth scaler circuit 64. The fourth scaler circuit 64 is preferably of the same type as that previously described with respect to the first 30, second 36 and third 38 scaler circuits, having an output which is equal to the input multiplied by a predetermined scaling function. In the preferred embodiment, the scaling function of the fourth scaler circuit 64 is the quantity n set which is a constant determined by the desired relay reach. Consequently, the output of the fourth scaler circuit 64 is the signal n set {v r (t₁)i f (t₂)-v r (t₂)i f (t₁)} or n set S₁. The output of the fourth scaler circuit 64 is coupled to a first input of a first two-input comparator circuit 66. The output of the third digital subtraction circuit 62 is coupled to a second input of the first two-input comparator circuit 66. The first two-input comparator circuit 66 is a digital comparator which generates an output signal when the magnitude of the signal applied to the first input exceeds the magnitude of the signal applied to the second input. Consequently, the first two-input comparator circuit 66 generates an output signal when the magnitude of the signal n set {v r (t₁)i f (t₂)-v r (t₂)i f (t₁)} exceeds the magnitude of the signal {v A (t₁)i f (t₂)-v A (t₂)i f (t₁)} or n set S₁>S₂. The output of the first two-input comparator circuit 66 is coupled to the input of a first counter 68. In the preferred embodiment, the first counter 68 provides a count signal upon receipt of a signal from the first two-input comparator circuit 66. The count signal is incremented by one count if the signal from the circuit 66 is present during the next succeeding sampling interval; otherwise, the count signal is reset to zero. The count signal is incremented by one count upon receipt of a signal from circuit 66 during each succeeding sampling interval. The count signal is reset to zero following any sampling interval during which a signal is not received from circuit 66. The count signal from the first counter 68 is coupled to the input of a first comparator circuit 70. The first comparator circuit 70 generates an output signal O₁, which is a first operate signal in the preferred embodiment described herein, when the magnitude of the input signal exceeds a predetermined value. Consequently, the first comparator circuit 70 will generate the first operate signal O₁ when the magnitude of the count signal from the counter 68 exceeds a predetermined value, for example three in the preferred embodiment. This means that in the preferred embodiment, the first operate signal O₁ will be generated upon detection of a signal from the first two-input comparator circuit 66 during at least three consecutive sampling intervals. Referring now to Figure 3, the output signal Δi A (t) from the first digital subtraction circuit 26 (see Figure 1) is coupled to the input of a fourth sampler/buffer circuit 202. The output V r (t) from the second two input adder 40 (see Figure 1) is coupled to the input of a fifth sampler/buffer circuit 204. The output v A (t) of the first A/D converter 20 (see Figure 1) is coupled to the input of a sixth sampler/buffer circuit 206. In the preferred embodiment, the fourth 202, fifth 204 and sixth 206 sampler/buffer circuits are of the same type as the first 42, second 44 and third 46 sampler/buffer circuits previously described. Each has two outputs, the first of which is equal to the magnitude of the input signal sampled at the first time t₁, and the second of which is equal to the magnitude of the input signal sampled at the second time t₂. Consequently, the outputs of the fourth sampler/buffer circuit 202 is a first signal Δi A (t₁) which is the input signal Δi A (t) sampled at the first time t₁; and the second output is a signal Δi A (t₂) which is equal to the input signal Δi A (t) sampled at the second time t₂. Similarly, the outputs of the fifth sampler/buffer circuit 204 comprise a first signal V r (t₁) which is equal to the input signal V r (t) sampled at the first time t₁; and a second signal V r (t₂) which is equal to the input signal V r (t) sampled at the second time t₂. The outputs of the sixth sampler/buffer circuit 206 comprise a first signal v A (t₁) which is equal to the input signal v A (t) sampled at the first time t₁; and a second signal v A (t₂) which is equal to the input signal v A (t) sampled at the second time t₂. The signal Δi A (t₁) output from the fourth sampler/buffer circuit 202 is coupled to one input of a fifth two-input multiplier 208 and one input of a sixth two-input multiplier 210. The signal Δi A (t₂) output from the fourth sampler/buffer circuit 202 is coupled to one input of a seventh two-input multiplier 212 and one input of an eighth two-input multiplier 214. The V r (t₁) signal output from the fifth sampler/buffer circuit 204 is coupled to the second input of the seventh two-input multiplier 212. The signal V r (t₂) output from the fifth sampler/buffer circuit 204 is coupled to the second input of the fifth two-input multiplier 208. The signal v A (t₁) output from the sixth sampler/buffer circuit 206 is coupled to the second input of the eighth two-input multiplier 214 The signal v A (t₂) output from the sixth sampler/buffer circuit 206 is coupled to the second input of the sixth two-input multiplier 210. In the preferred embodiment, the fifth 208, sixth 210, seventh 212 and eighth 214 two-input multipliers are the same type as the first 48, second 50, third 52 and fourth 54 two-input multipliers previously described. Each two-input multiplier produces a digital output signal having a magnitude which is equal to the magnitude of the first input signal multiplied by the magnitude of the second input signal. Consequently, the output of the fifth multiplier 208 is the signal V r (t₂)Δi A (t₁); the output of the sixth multiplier circuit 210 is the signal v A (t₂)Δi A (t₁); the output of the seventh multiplier 212 is the signal V r (t₁)Δi A (t₂); and the output of the eighth multiplier 214 is the signal v A (t₁)Δi A (t₂). The output of the fifth multiplier circuit 208 is connected to a negative input of a fourth digital subtraction circuit 216. The output of the sixth multiplier circuit 210 is coupled to a negative input of a fifth digital subtraction circuit 218. The output of the seventh multiplier circuit 212 is coupled to a positive input of the fourth digital subtraction circuit 216. The output of the eighth multiplier circuit 214 is coupled to a positive input of the fifth digital subtraction circuit 218. In the preferred embodiment, the fourth 216 and fifth 218 digital subtraction circuits are of the same type as the previously described first 26, second 60 and third 62 digital subtraction circuits, with each producing a digital output signal whose magnitude is equal to the magnitude of the signal applied to the positive input minus the magnitude of the signal applied to the negative input. Consequently, the output signal S₃ of the fourth digital subtraction circuit 216 is equal to V r (t₁)Δi A (t₂)-V r (t₂)Δi A (t₁); and the output signal S₄ of the fifth digital subtraction circuit 218 is equal to V A (t₁)Δi A (t₂)-V A (t₂)Δi A (t₁). The output signal S₃ of the fourth digital subtraction circuit 216 is coupled to the divisor input of a digital divider circuit 220. The output signal S₄ of the fifth digital subtraction circuit 218 is coupled to a dividend input of the digital divider 220. The output n from the divider circuit 220 is a digital signal whose magnitude is equal to the quotient of the digital signal S₄ applied to the dividend input divided by the digital signal S₃ applied to the divisor input. The magnitude of the signal n is a function of the distance from the relay to the fault and is equal to V A (t₁)Δi A (t₂)-V A (t₂)Δi A (t₁) V r (t₁)Δi A (t₂)-V r (t₂)Δi A (t₁) or S₄ S₃ . Referring now to Figure 4, the output signal Δi A (t) from the first digital subtraction circuit 26 (see Figure 1) is coupled to the input of a seventh sampler/buffer circuit 402. The output V r (t) from the second two-input adder 40 (see Figure 1) is coupled to the input of an eighth sampler/buffer circuit 404. The output v A (t) of the first A/D converter 20 (see Figure 1) is coupled to the input of a ninth sampler buffer circuit 406. In the preferred embodiment, the seventh 402, eighth 404 and ninth 406 sampler/buffer circuits are of the same type as the first 42, second 44, third 46, fourth 202, fifth 204 and sixth 206 sampler/buffer circuits previously described. Each has two outputs, the first of which is equal to the magnitude of the input signal sampled at the first time t₁, and the second of which is equal to the magnitude of the input signal sampled at the second time t₂. Consequently, the outputs of the seventh sampler/buffer circuit 402 is a first signal Δi A (t₁) which is the input signal Δi A (t) sampled at the first time t₁; and the second output is a signal Δi A (t₂) which is equal to the input signal Δi A (t) sampled at the second time t₂. Similarly, the outputs of the eighth sampler/buffer circuit 404 comprises a first signal V r (t₁) which is equal to the input signal V r (t) sampled at the first time t₁; and a second signal V r (t₂) which is equal to the input signal V r (t) sampled at the second time t₂. The outputs of the ninth sampler/buffer circuit 406 comprises a first signal v A (t₁) which is equal to the input signal v A (t) sampled at the first time t₁; and a second signal v A (t₂) which is equal to the input signal v A (t) sampled at the second time t₂. The signal Δi A (t₁) output from the seventh sampler/buffer circuit 402 is coupled to one input of a two-input multiplier 408. The signal Δi A (t₂) output from the seventh sampler/buffer circuit 402 is coupled to one input of a tenth two-input multiplier 410. The V r (t₁) signal output from the eighth sampler/buffer circuit 404 is coupled to the second input of the tenth two-input multiplier 410 and to one input of an eleventh two-input multiplier 412. The V r (t₂) signal output from the eighth sampler/buffer circuit 404 is coupled to a second input of the ninth two-input multiplier 408 and one input of a twelfth two-input multiplier 414. The v A (t₁) signal output from the ninth sampler/buffer circuit 406 is coupled to a second input of the twelfth two-input multiplier 414. The v A (t₂) signal output from the ninth sampler/buffer circuit 406 is coupled to a second input of the eleventh two-input multiplier 412. In the preferred embodiment, the ninth 408, tenth 410, eleventh 412 and twelfth 414 two-input multipliers are the same type as the first 48 through eighth 214 two-input multipliers previously described. Each two-input multiplier produces a digital output signal having a magnitude which is equal to the magnitude of the first input signal multiplied by the magnitude of the second input signal. Consequently, the output of the ninth multiplier 408 is the signal v r (t₂) Δ i A (t₁); the output of the tenth multiplier 410 is the signal v r (t₁) Δi A (t₂); the output of the eleventh multiplier 412 is the signal v A (t₂)v r (t₁); and the output of the twelfth multiplier 414 is the signal v A (t₁)v r (t₂). The output of the ninth multiplier circuit 408 is connected to a positive input of a sixth digital subtraction circuit 416. The output of the tenth multiplier circuit 410 is coupled to a negative input of the sixth digital subtraction circuit 416. The output of the eleventh multiplier circuit 412 is coupled to a negative input of a seventh digital subtraction circuit 418. The output of the twelfth multiplier circuit 414 is coupled to the positive input of the seventh digital subtraction circuit 418. In the preferred embodiment, the sixth 416 and seventh 418 digital subtraction circuits are of the same type as the previously described first 26, second 60, third 62, fourth 216 and fifth 218 digital subtraction circuits, with each providing a digital output signal whose magnitude is equal to the magnitude of the signal applied to the positive input minus the magnitude of the signal applied to the negative input. Consequently, the output signal S₅ of the sixth digital subtraction circuit 416 is equal to v r (t₂)Δi A (t₁)-v r (t₁) Δi A (t₂); and the output signal S₆ of the seventh digital subtraction circuit 418 is equal to v A (t₁)V r (t₂)-v A (t₂)V r (t₁). The output signal S₅ of the sixth digital subtraction circuit 416 is coupled to the divisor input of a second digital divider circuit 420. The output signal S₆ of the seventh digital subtraction circuit 418 is coupled to a dividend input of the second digital divider 420. In the preferred embodiment, the second digital divider 420 is the same type as the previously described first digital divider circuit 220; having an output signal which is a digital signal whose magnitude is equal to the quotient of the digital signal S₆ applied to the dividend input divided by the digital signal S₅ applied to the divisor input. Consequently, the output R fA from the second divider circuit 420 is equal to V A (t₁)V r (t₂)- V A (t₂)V r (t₁) Δi A (t₁)V r (t₂)-Δi A (t₂)V r (t₁) or S₆ S₅ . The signal R fA is a function of the fault resistance; that is, the magnitude of R fA is proportional to the magnitude of the fault resistance measured at the relay location and the angle of the signal R fA is substantially equal to the fault resistance angle. The output signal S₅ of the sixth digital subtraction circuit 416 is also coupled to the input of a fifth scaler circuit 422. The fifth scaler circuit 422 is preferably of the same type as that previously described with respect to the first 30, second 36, third 38 and fourth 64 scaler circuits, having an output which is equal to the input multiplied by a predetermined scaling function. In the preferred embodiment, the scaling function of the fifth scaler circuit 422 is the quantity R SET which is a constant determined by the desired relay reach. Consequently, the output of the fifth scaler circuit 222 is the signal R SET [ Δ i A (t₁)v r (t₂)- Δi A (t₂)V r (t₁)] or R SET S₅. The output of the fifth scaler circuit 422 is coupled to a first input of a second two-input comparator circuit 424. The output signal S₆ of the seventh digital subtraction circuit 418 is coupled to a second input of the second two-input comparator circuit 424. The second two-input comparator circuit 424 is preferably of the same type as that previously described with respect to the first two-input comparator circuit 66 which generates an output signal when the magnitude of the signal applied to the first input exceeds the magnitude of the signal applied to the second input. Consequently, the second two-input comparator circuit 424 generates an output signal when the magnitude of the signal R SET [ Δ i A (t₁)V r (t₂)- Δi A (t₂)V r (t₁)] exceeds the magnitude of the signal [V A (t₁)V r (t₂)-v A (t₂)V r (t₁) ] or R SET S₅>S₆. The output of the second two-input comparator circuit 424 is coupled to the input of a second counter 426. In the preferred embodiment, the second counter 426 is of the same type as that previously described with respect to the first counter 68 which provides a count signal upon receipt of a signal from the second two-input comparator circuit 424. The count signal is incremented by one count if the signal from the second two-input comparator circuit 424 is present during the next succeeding sampling interval; otherwise, the count signal is reset to zero. The count signal is incremented by one count upon receipt of a signal from the second two-input comparator circuit 424 during each succeeding sampling interval. The count signal is reset to zero following any sampling interval during which a signal is not received from the circuit 424. The count signal from the second counter 426 is coupled to the input of a second comparator circuit 428. The second comparator circuit 428 is preferably of the same type as that previously described with respect to the first comparator circuit 70 which generates an output signal O₂, which is a second operate signal in the preferred embodiment, when the magnitude of the input signal exceeds a predetermined value. Consequently, the second comparator circuit 428 will generate the second operate signal O₂ when the magnitude of the count signal exceeds a predetermined value, for example 3 in the preferred embodiment. This means that in the preferred embodiment, the second operate signal O₂ will be generated upon detection of a signal from the second two-input comparator circuit 424 during at least three consecutive sampling intervals. Referring now to Fig. 5, the first operate signal O₁ is coupled to the first input of a two-input AND gate 250 and the second operate signal O₂ is coupled to the second input of the two-input AND gate 250. The output of the two-input AND gate 250 is a trip signal which is generated upon coincidence of the first operate signal O₁ and the second operate signal O₂. The trip signal is preferably utilized to enable the operation of a circuit breaker or other transmission line interruption means. The preferred embodiment of the apparatus for providing distance protection and distance measurement for a high voltage transmission line, as depicted in Figures 1, 2, 3, 4 and 5, operates as follows. When there is no fault on the line, and the load remains substantially constant, the signal i A (t- k f ) is equal to the signal i A (t). Consequently, the output Δ i A (t) from the first subtract circuit 26 is equal to 0. As a result, the signal i f (t) output from the first two-input adder 34 is also equal to 0. Accordingly, the output signal i f (t₁) and i f (t₂) from the first sampler/buffer circuit 42 are also 0. Therefore, the output signals from the first 48, second 50, third 52 and fourth 54 multipliers are 0 which means that the input signals to the first comparator 66 are 0 as well. Since both input signals are 0, the first comparator 66 will not produce an output signal which thus precludes the generation of the first operate signal O₁ from the output of the first comparator 70. Since the output Δi A (t) from the first subtract circuit 26 is equal to 0, the output signals Δi A (t₁) and Δi A (t₂) from the seventh sampler/buffer circuit 402 are also 0. Therefore, the output signals from the ninth 408 and tenth 410 multipliers are 0 which means that the output signal S₅ from the sixth subtract circuit 416 is 0 as well. Since S₅ is 0, the output R SET ·S₅ from the fifth scaler circuit 422 is also 0. As indicated previously, the second two-input comparator circuit 424 will generate an output when R SET S₅>S₆. Since R SET S₅ is 0, the second two-input comparator 424 will not produce an output signal which thus precludes the generation of the second operate signal 0₂ from the output of the second comparator circuit 428. Since the generation of the first output signal 0₁ and the second output signal 0₂ is precluded, the AND gate 250 will not produce a trip signal. Assuming now a fault on phase A, the output Δi A (t) from the first subtract circuit 26 will now be equal to the fault current since the output of subtract circuit 26 is the total postfault current (i.e. load current plus fault current) minus the prefault current (load current) occurring at h/f second prior to the occurrence of the fault. Since Δi A (t) is no longer zero, the comparator 66 will generate an output signal when n set [V r (t₁)i f (t₂)-V r (t₂)i f (t₁)]> [V A (t₁)i f (t₂)-V A (t₂)i f (t₁)] or n set S₁>S₂. This means that the A phase fault of this example has occurred within the relay reach as set by the value of the constant n SET as previously described. Similarly, the second two-input comparator 424 will generate an output signal when R SET S₅>S₆. This means that the A phase fault of this example has occurred within the resistance reach of the relay as set by the value of the constant R SET as previously described. Since a A phase fault has been assumed, the output signal from the first two-input comparator 66 and the output signal from the second two-input comparator 424 will each remain during the three consecutive sampling intervals; consequently, the first 70 and second 428 comparators will generate operate signals O₁ and O₂ respectively. The requirement that the two-input comparator output signals remain during consecutive sampling intervals is to ensure that an operate signal is generated only for actual faults and is not based on transient or spurious signals. Since a phase A fault has been assumed in this example, the output signals O₁ and O₂ from the first 70 and second 428 comparators will be generated concurrently. Consequently, the AND gate 250 depicted in Figure 5, will generate a trip signal which is utilized by the protection system to trip circuit breakers thereby isolating the faulted phase. Also, since Δ i A (t) is no longer zero, the divider circuit 220 (see Figure 3) will generate a signal n which is a function of the distance from the relay to the fault and which is equal to S₄ S₃ or v A (t₁)Δi A (t₂)-v A (t₂)Δi A (t₁) v r (t₁)Δi A (t₂)-v r (t₂)Δi A (t₁) . Similarly, since Δi A (t) is no longer 0, the second divider circuit 420 (see Figure 4) will generate a signal R fA which is a function of the fault resistance and which is equal to S₆ S₅ or v A (t₁)V r (t₂)-v A (t₂)V r (t₁) Δ i A (t₁)V r (t₂)- Δi A (t₂)V r (t₁) . When there is no fault on the line, but the load current changes, the signal Δi A (t) will be equal to the magnitude of the change in load current since the output of the subtract circuit 26 is proportional to the post-load change current minus the pre-load change current. However, the n SET and R SET constants have been selected to ensure that there will be no output from the first 66 and second 424 two-input comparators for changes in load currents which are not due to faults within the reach of the relay. This can best be explained by reference to Figure 6 which depicts the relay characteristic plotted on an L-R diagram. As can be seen, when n SET [v r (t₁)i f (t₂)-v r (t₂)i f (t₁)]< [v A (t₁)i f (t₂)-v A (t₂)i f (t₁)] or R SET [v r (t₂)Δi A (t₁)-v r (t₁) Δ i A (t₂)]< [v A (t₁)Δi A (t₂)-v A (t₂)Δi A (t₁)] the relay will not operate since that load characteristic falls outside the zone of operation as shown in Figure 6. When n SET [v r (t₁)i f (t₂)-v r (t₂)i f (t₁)]> [V A (t₁)i f (t₂)-v A (t₂)i f (t₁)] and R SET [v r (t₂)Δi A (t₁)-v r (t₁)Δi A (t₂)]> v A (t₁)V r (t₂)-v A (t₂)V r (t₁)] the relay will operate since the load characteristic falls within the zone of operation shown in Figure 6. As can be seen from the diagram of Figure 6, the n SET line can be tilted (see dotted line) in order to provide a slope to the relay reach. This tilt angle α is adjustable as provided by the differentiator 32 and scaler 36 of Figure 1 where the scale function of the scaler 36 is tan α 2 π f . Referring now to Figure 7, there is shown a block diagram of a variable resistance reach portion of the apparatus of the present invention. The output signal Δi A (t) from the first digital subtraction circuit 26 (see Figure 1) is coupled to the input of a tenth sampler/buffer circuit 302. The tenth sampler/buffer circuit 302 is of the same type as the previously described first 42 through ninth 406 sampler/buffer circuits. Accordingly, the tenth sampler/buffer circuit 302 has two outputs, the first of which is equal to the magnitude of the input signal sampled at the first time t₁, and the second of which is equal to the magnitude of the input signal sampled at the second time t₂. Consequently, the outputs of the tenth sampler/buffer circuit 302 is a first signal Δi A (t₁) which is the input signal Δi A (t) sampled at the first time t₁; and the second output is a signal Δi A (t₂) which is equal to the input signal Δi A (t) sampled at the second time t₂. The output signal Δi A (t₁) from the tenth sampler/buffer circuit 302 is coupled to one input of a maximum computation circuit 304 and one input of a minimum computation circuit 306. The output signal Δi A (t₂) from the tenth sampler/buffer circuit 302 is coupled to a second input of the maximum computation circuit 304 and a second input of the minimum computation circuit 306. The maximum computation circuit 304 is a circuit which compares the magnitudes of the two input signals and provides an output signal which is equal to the maximum value of the two compared input signals. Consequently, the output signal from the maximum computation circuit 304 is the signal Δi A (t)MAX. The minimum computation circuit 306 is a circuit which compares the magnitudes of the two input signals and provides an output which is equal to the minimum of the input signals. Consequently, the output of the minimum computation circuit 306 is the signal Δi A (t)MIN. The output signal Δi A (t)MAX from the maximum computation circuit 304 is coupled to one input of a third two-input adder 308. The output signal Δi A (t)MIN is coupled to the second input of the third two-input adder 308. The third two-input adder 308 is preferably the same type as the previously described first 34 and second 42 two-input adders. Accordingly, the output of the third two-input adder 308 is a signal having a magnitude which is substantially equal to the sum of the magnitudes of the two input signals. Consequently, the output of the third two-input adder 308 is the signal 2ΔI A pk. The output signal 2 Δ I A pk from the third two-input adder 308 is coupled to the input of a sixth scaler circuit 310. The sixth scaler circuit 310 is the same type as the previously described first 30, second 36, third 38, fourth 64 and fifth 422 scaler circuits. Accordingly, the sixth scaler circuit 310 has an output which is equal to the input multiplied by a predetermined scaling function. In the preferred embodiment, the scaling function of the sixth scaler circuit 310 is the quantity 0.5; consequently, the output of the sixth scaler circuit 310 is the signal ΔI A pk, which is coupled to one input of a thirteenth two-input multiplier 312. The thirteenth two-input multiplier 312 is preferably the same type as the first 48 through twelfth 414 two-input multipliers previously described. Accordingly, the thirteenth two-input multiplier 312 produces a digital output signal having a magnitude which is equal to the magnitude of the first input signal multiplied by the magnitude of the second input signal. The output signal S₄ from the fifth digital subtraction circuit 218 (see Figure 3) is coupled to the second input of the thirteenth two-input multiplier 312. Consequently, the output signal from the thirteenth two-input multiplier 312 is the signal ΔI A pkS₄. The output signal ΔI A pkS₄ from the thirteenth multiplier 312 is coupled to one input of a third two-input comparator circuit 314. The output signal S₃ from the fourth digital subtraction circuit 216 (see Figure 3) is coupled to the input of a seventh scaler circuit 316. The seventh scaler circuit 316 is preferably the same type as that previously described with respect to the first 30, second 36, third 38, fourth 64, fifth 222 and sixth 310 scaler circuits, having an output which is equal to the input multiplied by a predetermined scaling function. In the preferred embodiment, the scaling function of the seventh scaler circuit 316 is the quantity V SET which is a constant determined by the desired relay reach. Consequently, the output of the seventh scaler circuit 316 is the signal V SET S₃, which is coupled to the second input of the third two-input comparator circuit 314. The third two-input comparator circuit 314 is preferably the same type as that previously described with respect to the first 66 and second 424 two-input comparator circuits, each of which generates an output signal when the magnitude of the signal applied to the first input exceeds the magnitude of the signal applied to the second input. Consequently, the third two-input comparator circuit 314 generates an output signal when the magnitude of the signal V SET S₃ > ΔI A pkS₄. Since signal S₃ is equal to [v r (t₁) Δi A (t₂)-v r (t₂) Δ i A (t₁)] and signal S₄ is equal to [v A (t₁) Δ i A (t₂)-v A (t₂) Δi A (t₁)], the third comparator 314 will generate an output signal when V SET [v r (t₁) Δ i A (t₂)-v r (t₂) Δ i A (t₁)] > ΔI A pk[v A (t₁) Δ i A (t₂)-v A (t₂) Δ i A (t₁)]. The output signal from the third two-input comparator circuit 314 is coupled to the input of a third counter 318. In the preferred embodiment, the third counter 318 is the same type as that previously described with respect to the first 68 and second 426 counters each of which provides a count signal upon receipt of a signal from their respect two-input comparator circuits. Accordingly, the output count signal is incremented by one count if the signal from the third two-input comparator circuit 314 is present during the next succeeding sampling interval; otherwise, the output count signal is reset to 0. The output count signal is incremented by one count upon receipt of a signal from the third two-input comparator circuit 314 during each succeeding sampling interval. The count signal is reset to 0 following any sampling interval during which the signal is not received from the comparator circuit 314. The output count signal from the third counter 318 is coupled to the input of third comparator circuit 320. The third comparator circuit 320 is preferably the same type as that previously described with respect to the first 70 and second 428 comparator circuits each of which generates an output signal when the magnitude of the input signal exceeds a predetermined value. Accordingly, the third comparator 320 will generate an output signal 0₃, which is a third operate signal in the preferred embodiment, when the magnitude of the input signal exceeds a predetermined value, for example 3, in the preferred embodiment. This means that in the preferred embodiment, the third operate signal 0₃ will be generated upon detection of a signal from the third two-input comparator circuit 314 during at least three consecutive sampling intervals. The third operate signal 0₃, since it is generated when ΔI A pkS₄<V SET · S₃ (relay setting), where ΔI A pk is the peak value of ΔI A , gives the relay a variable reach characteristic along the resistive axis similar to that obtained with a variable MHO characteristic. Consequently, the optimum relay tripping characteristic is preferably a combination of the following criteria: This is implemented by coupling the third operate signal 0₃ to one input of an AND gate and coupling 0₂ MAX (the second operate signal 0₂ adjusted for maximum R F reach) to the other input of the two-input AND gate. The output of the two-input AND gate is coupled to one input of a two-input OR gate. The signal 0₂ MIN (R SET set for minimum R F reach) is coupled to the other input of the two-onput OR gate. The output of the two-input or gate is coupled to the second input of the two-input AND gate 250 depicted in Figure 5 with the first operate signal )₁ being coupled to the first input of AND gate 250 as shown in Figure 5. While the present invention has been described with reference to a specific embodiment thereof, it will be obvious to those skilled in the art that various changes and modifications may be made within the scope of the appended claims.

Claims: A protective relay for detecting faults in an electrical power distribution system (10), said relay comprising: (a) means (18,20) for receiving signals from an electrical power distribution system (10), which signals relate to at least one system voltage v and at least one system current i; (b) means (28) for generating a signal di dt which is substantially equal to a first derivative with respect to time of said system current; (c) means (40) for generating a signal v r which is substantially equal to the sum of a line resistance R of said power distribution system multiplied by said system current i and a line inductance L multiplied by said di dt signal; (d) means (26) for generating a signal Δi which is substantially equal to the magnitude of the system current i measured at a first time subtracted from the magnitude of the system current i measured at a second time, said second time occurring later than said first time; characterised by (e) means (32) for generating a signal d Δ i dt which is substantially equal to a first derivative with respect to time of said Δi signal; (f) means (34) for generating a signal i f which is substantially equal to the sum of the signal Δ i plus the signal d Δ i dt multiplied by a scaling function having a predetermined magnitude; (g) means (46,44,42) for generating signals v(t₁), v r (t₁) and i f (t₁) which are substantially equal to the magnitude of the signals v, v r and i f respectively occurring at first time t₁; (h) means (46,44,42) for generating signals v(t₂), v r (t₂) and i f (t₂) which are substantially equal to the magnitude of the signals v, v r and i f respectively occurring at a second time t₂, which second time occurs later than said first time; (i) means (48,52,60) for generating a signal S₁ which is substantially equal to the signal V r (t₁) multiplied by the signal i f (t₂) minus the signal v r (t₂) multiplied by the signal i f (t₁); (j) means (50,54,62) for generating a signal S₂ which is substantially equal to the signal v(t₁) multiplied by the signal i f (t₂) minus the signal v(t₂) multiplied by the signal i f (t₁); (k) means (64) for providing a signal n set having a predetermined magnitude; and (l) means (66,68,70) for generating an output signal O₁ when the magnitude of the signal n set multiplied by the signal S₁ is greater than the magnitude of the signal S₂. A protective relay in accordance with claim 1 additionally comprising: (a) means (202) for generating a signal Δi(t₁) which is substantially equal to the magnitude of the signal Δi occurring at said first time t₁; (b) means (202) for generating a signal Δi(t₂) which is substantially equal to the magnitude of the signal Δi occurring at said second time t₂; (c) means (216) for generating a signal S₃ which is substantially equal to the signal v r (t₁) multiplied by the signal Δi(t₂) minus the signal v r (t₂) multiplied by the signal Δ i(t₁); (d) means (218) for generating a signal S₄ which is substantially equal to the signal v(t₁) multiplied by the signal Δi(t₂) minus the signal v(t₂) multiplied by the signal Δi(t₁); and (e) means (220) for providing an output signal n which is substantially equal to the magnitude of the signal S₄ divided by the magnitude of the signal S₃. The protective relay in accordance with claim 2 additionally comprising: (a) means (408,410,416) for generating a signal S₅ which is substantially equal to the signal v r (t₂) multiplied by the signal Δi(t₁) minus the signal v r (t₁) multiplied by the signal Δi(t₂); (b) means (412,414,418) for generating a signal S₆ which is substantially equal to the signal v(t₁) multiplied by the signal v r (t₂) minus the signal v(t₂) multiplied by the signal v r (t₁); (c) means (422) for providing a signal R set having a predetermined magnitude; and (d) means (424) for generating an output signal O₂ when the magnitude of the signal R set multiplied by the signal S₅ is greater than the magnitude of the signal S₆. The protective relay in accordance with claim 3 additionally comprising: (a) means (310) for generating a signal Δ I pk which is substantially equal to a peak magnitude of the signal ΔI; (b) means (316) for providing a signal V set having a predetermined magnitude; and (c) means (314,318,320) for generating an output signal when the magnitude of the signal V set multiplied by the signal S₃ is greater than the magnitude of the signal ΔI pk multiplied by the signal S₄.

Inventors: CAVERO LEONARDO PEREZ, CAVERO, LEONARDO PEREZ
Applicants: GEN ELECTRIC, GENERAL ELECTRIC COMPANY
Application year: 1989
Main classification: H02H7
IPC codes: H02H3