Amplifying circuit

Abstract: An amplifying circuit has a plurality of first signal input circuits for multi-channel input, a signal output circuit receptive commonly of outputs of these signal input circuits, and a switching circuit for selecting one of the first signal input circuits. A second signal input circuit (1) has an input terminal held at a fixed potential (V Z ) and an output terminal connected to the signal output circuit and is operative during a selecting transient period of the plurality of first signal input circuits.

Description: BACKGROUND OF THE INVENTION The present invention relates to structure of an amplifying circuit, and more specifically relates to a particular amplifying circuit of multi-channel input and single-output type. Conventionally, this type of the amplifying circuit is constructed in view of the multi-channel input and single-output type such that when selecting a particular channel, only the selected channel is biased and the other nonselected channels are not biased. The drawings are referred to for detailed description of the prior art, in which Fig. 1 shows a schematic structure of the prior art, Fig. 2 shows a circuit of the Fig. 1 prior art and Fig. 3 is a timing chart of switching operation in the Fig. 2 circuit. Referring to Fig. 2, for instance, A channel is initially selected and next, is switched to B channel. In such case, as shown in Fig. 3, a base potential V A of transistor Tr5 and another base potential V B of transistor Tr6 are falling and rising, respectively, in illustrated timings. At this time, a collector potential of transistor Tr9 is lowered during a period Td shown in Fig. 3, in which none of the channels is operated, and therefore a collector current of transistor Tr9 is reduced so that a flowing current is reduced through load resistors R₃ and R₄ within an output circuit, thereby causing transient noise. The above described conventional amplifying circuit of the multi-channel input and single-output type is constructed such that when selecting a particular channel only the selected channel is biased and the remaining channels are not biased. Therefore, during the switching of channels, one channel which has been selected before the switching is firstly made non-operative and then another newly selected channel is made operative, thereby causing a time delay in which none of the channels momentarily operates. As a result, a transient noise may be generated at an output terminal to thereby impart bad influence to a circuit subsequently connected to the amplifying circuit. A prior art amplifier of the foregoing type is disclosed in US-A-3.617.916. SUMMARY OF THE INVENTION An object of the invention is to, therefore, eliminate transient noise at the output terminal of the amplifying circuit. The present invention, utilises a dummy channel having an input at a fixed potential and designed to be selected when all of the other channels are made non-operative during the switching of channels. According to the invention there is provided an amplifying circuit having a plurality of first signal input circuits for multi-channel input, a signal output circuit receptive commonly of outputs of these signal input circuits, and selecting means for selecting one of said first signal input circuits, characterised by a second signal input circuit having an input terminal held at a fixed potential and an output terminal connected to said signal output circuit, the second signal input circuit being operative during a transient selecting period of said plurality of first signal input circuits. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural diagram of the prior art; Fig. 2 is a circuit diagram of the prior art; Fig. 3 is a timing chart of channel switching in the Fig. 2 circuit; Fig. 4 is a block diagram showing one embodiment of the present invention; Fig. 5 is a circuit diagram of the Fig. 4 embodiment; and Fig. 6 is a timing chart of channel switching in the Fig. 5 circuit. DETAILED DESCRIPTION OF EMBODIMENT Next, the present invention is described with reference to the drawings. Fig. 4 is a block diagram of one embodiment according to the present invention and Fig. 5 is a circuit diagram thereof. In Figs. 4 and 5, a dummy channel 1 is provided according to the present invention and is indicated as a portion enclosed by dot and chain line. In Fig. 5, a portion enclosed by dashed lines has a structure identical to that of the conventional circuit, including A channel input circuit, B channel input circuit, C channel input circuit, D channel input circuit and switching circuit. The current switch transistors Tr5, Tr6, Tr7 and Tr8 of the respective channel input circuits are fed at their bases with base bias voltages V A , V B , V C and V D , respectively, during their active states. These bias voltages V A through V D are generated from corresponding bias circuits which have the same structure, hence these bias voltages are set to the identical value with each other. Instead, these may be set to different values optimum to the respective channels. Further, in the dummy channel 1, the current switch transistor Tr4 is fed with a base bias voltage V Z which is set to a value lower than any of the bias voltages V A , V B , V C and V D . The switching circuit is provided with a switching control circuit. The switching control circuit makes one of the control signal lines CA - CD active level, responding to a selection data, so that the corresponding current switch transistor is made conductive. A channel input circuit has two transistors Tr13 and Tr14 connected with each other in a differential circuit, and a current switch transistor Tr5 through which the above two transistors Tr13 and Tr14 are connected to the current source and whose base is connected to a bias voltage V A of the switching circuit. B, C, and D channel input circuits have the same structure as A channel input circuit, respectively. When the bias voltage V A is fed to base of the transistor Tr5, a current from the current source 10 is fed as an operating current through the transistor Tr5 to the two transistors Tr13 and Tr14, in which when input signal is fed to input terminal A, the voltage of the input signal is amplified and the voltage amplified is generated between output terminals. A dummy channel has two transistors Tr11 and Tr12 each of whose collectors is connected to a load circuit, a power 2 for dummy channel connected to bases of the above two transistors Tr11 and Tr12, another transistor Tr4 through which emitters of the above two transistors Tr11 and Tr12 are connected to a current source, and a voltage V Z which is connected to base of the another transistor Tr4. Said voltage V Z renders said the transistor Tr4 conductive in a transient period in which the content of said selection data changes, that is when switching is effected from one channel to another channel, by which variation of the collector current of the transistor Tr9 of the bias current source 10 is removed. Accordingly, as shown by switching timing of Fig. 6, when switching is effected from A channel to B channel, the transistor Tr4 starts to operate during the course of falling of V A and stops operating when V B rises. As a result, the lowering of the collector voltage can be effectively suppressed in the transistor Tr9 of the bias current source 10 to thereby remove variation of the collector current of the transistor Tr9. Consequently, the flowing current is not changed through the load resistors R1 and R2 of the output circuit to thereby reduce the generation of transient noise. As described above, according to the present invention, the amplifying circuit of the multi-channel input and single-output type is provided with the dummy channel effective to reduce transient noise which would be generated at the time of the channel switching.

Claims: An amplifying circuit having a plurality of first signal input circuits (A,B,C,D) for multi-channel input, a signal output circuit (R₁,R₂,output) receptive commonly of outputs of these signal input circuits, and selecting means (C A ,C B ,C C ,C D ) for selecting one of said first signal input circuits, characterised by a second signal input circuit (1) having an input terminal held at a fixed potential (2) and an output terminal connected to said signal output circuit, the second signal input circuit being operative during a transient selecting period of said plurality of first signal input circuits. An amplifying circuit according to Claim 1, wherein the first signal input circuits have respectively differential amplifier circuits (Tr13,Tr14), and connect respectively with the selecting means feeding selectively bases of current switch transistors (Tr5,Tr6,Tr7,Tr8) with base bias voltages, whereby these bias voltages are generated from corresponding bias circuits during their active states. An amplifying circuit according to Claim 2, wherein the second signal input circuit comprises a current switch transistor (Tr4) and connects with a power supply circuit (Vz) feeding the base of the current switch transistor with base bias voltage, which is set to a value lower than any of the bias voltages of the first signal input circuits, reducing the generation of noise. An amplifying circuit as claimed in Claim 1 wherein the output circuit comprises a load circuit (R₁,R₂) commonly connected to outputs of the signal input circuits, and an output terminal connected to said load circuit, the amplifying circuit further comprising a current source (Tr9,Tr10), the selecting means connecting said current source selectively to said plurality of signal input circuits and in response to a selection data, the second signal input circuit (Tr4,Tr11,Tr12) feeding said load circuit with said current from the current source without passing through said plurality of signal input circuits during the selecting transient period. An amplifying circuit as claimed in Claim 1, wherein each signal input circuit has a first and a second transistor (Tr13,Tr14) connected with each other to form differential type circuit, the amplifying circuit further comprising means (input terminal A-D) each of which applies a respective input signal to bases of the first and the second transistors, a load circuit (R₁,R₂), means which commonly connect said signal input circuits with said load circuit, a current source (Tr9,Tr10), a plurality of third transistors (Tr5-Tr8) through each of which said current source is connected to a common emitter point of said first and second transistors, said selecting means being arranged to make conductive one of the third transistors specified in response to selection data, the second signal input circuit comprising fourth and fifth transistors (Tr11,Tr12) whose collectors are connected respectively to said load circuit and to whose bases bias current is fed, a sixth transistor (Tr4) through which the emitters of said fourth and fifth transistors are connected to said current source and means (Vz) which renders said sixth transistor conductive in said selecting period.

Inventors: NOZAWA SHINJI, SUGAWARE MITSUTOSHI, NOZAWA, SHINJI, SUGAWARE, MITSUTOSHI, NOZAWA, SHINJI C/O NEC IC, SUGAWARE, MITSUTOSHI C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: H03F3
IPC codes: H03F3, H03G3