COMPUTER SYSTEM WITH DISTRIBUTED ASSOCIATIVE MEMORY

Abstract: An apparatus and method for transmitting data from a plurality of senders (32, 38, 42) to a receiver (52) over a single communication channel (50) is described incorporating an associative memory module (12, 13, 14) for each respective sender (32, 38, 42) wherein the associative memory module (12, 13, 14) includes a memory (68) and a control unit (67) and wherein the memory (68) may be a random access memory (68) or an associative memory (68'). The invention overcomes the problem of transmitting on the communication channel (50) one data word from each sender (32, 38, 42) only prior to any of the senders transmitting a second word on the communication channel.

Description: "CCMPUIER SYSTEM WITH DISTRIBUTED ASSOCIATIVE METORy" Background of the Invention Field of the Invention; This invention relates to multi-processor computer systems and more particularly to a parallel processing system employing a distributed associative memory consisting of separate modules accessible by a common communication channel. Description of the Prior Art In the prior art, a single communication channel may be interconnected to several input/output controllers, to input/output ports of a general or special purpose processors or to other ports capable of transferring data in accordance with the protocol of the communication channel. The data transferred on the bus is normally determined by the input/output port given access to the bus. Normally, one word or a sequence of words or a sequence of bits of a word may be transferred serially on the bus. In U. S. Patent 4, 493,074, which issued on January 8, 1985 to C. J. Walter et al. , a communication channel was described incorporating a content induced transaction overlap (CITO) protocol. In 4,493,074, the senders simultaneously transmit the highest order bits of their data word, one bit at a time in serial fashion and monitor the state of the communication channel. Transmission of data bits is terminated by all senders which detect a difference between the state of their transmitted data bit and the state of the communication channel. Bit competition performed at the end of each transmitted data word determines among those senders still having data bits remaining to be transmitted which sender has lexicographically the next smallest word and activates the sender to transmit its remaining dat bits. This procedure continues until all of the sender have completed the sending of their data word. In U. S. Patent 4,493,074, the sender having th smallest word numerically is transmitted first on th communication channel. All senders are given a opportunity to transmit their respective word prior t any sender sending a second word unless an interrup procedure is used. In U. S. Patent 4,493,074, some data compressio takes place because words having bits of the same valu nay be transmitted simultaneously and words o increasing numerical value are sent successively. It i understood that reconstruction of a complete word i performed by the receiver by supplying higher order bit to the lower order bits subsequently sent in time. Summary of the Invention In accordance with the present invention, a apparatus and method is provided for transmitting dat from a. plurality of senders to a receiver over communication channel comprising the- s raps of storing i a memory coupled to each sender, respectively, plurality of data words with each bit position "0 through n of the plurality of data words correspondin to a respective column "0" through n in the respectiv memory, storing in a word boundary register in eac sender the miner of bit positions of the plurality o data words, storing in a bit position register in eac sender the number of bit positions of the plurality o data words, first determining if a binary "0" is store in column n of each memory, respectively, if a binar "0" is stored in column n, storing a binary "0" in data register in the sender indicative of the binary "0 in the column n of the respective memory, disabling i the respective memory each word having a binary "1" in the column n from further readout and storing in a respective second memory, the column position n with the word address of each word having the binary "1" stored in column n, if a binary "0" is not stored in column n, storing a binary "1" in the data register in the sender indicative of the binary "1" in the column n, each sender transmitting the highest order data bit in the data register corresponding to the data bit from column n to the communication channel, detecting the state of the communication channel by each sender to determine when the state of the communication channel is the same as the state of the transmitted data bit, second determining if a binary "0" is stored in column n -1 of each memory, respectively, if a binary "0" is stored in column n -1, storing a binary "0" in the data register in the sender indicative of the binary "0" in the column n -1 of the respective memory, disabling in the respective memory each word not previously disabled having a binary "1" in the column n -1 from further readout and storying in the respective second memory, the column position n -1 with the word address of each word having the binary "1" stored in column n -I, if a binary "0" is not stored in column n -1, storing ' a binary "1" in the data register in the sender indicative of the binary "1" in the column n -1, each sender transmitting the next highest order of data bits when the state of the channel is the same as the state of the transmitted data bits, repeating the second determining step for columns n -2 through "0" of each memory, respectively, at which time each data register of each sender will contain a data word and whereby the column position and word address of each disabled word will be stored in the respective second memory, successively transmitting the next highest data bit from each sender when the state of the channel is the same as the state of the transmitted data bit, successively decrementin the word boundary register and bit position register fo each transmitted data bit whose state was the same a the state of the communication channel, and terminatin the transmission of the remaining data bits by eac sender whose transmitted data bit is different from th state of the communication channel whereby a data wor from at least one sender is transmitted over th communication channel. It is an object of the invention to interconnect plurality of associative memory modules through plurality of respective senders to a singl communication channel which utilizes a content induce transaction overlap (CITO) protocol. It is a further object of the invention for eac sender to access data in the associative memory modul connected thereto by accessing data words according t their content similar to the content induced transactio overlap (CITO) protocol. It is a further object of the invention to acces data words in a plurality of distributed memory module according to the content of the data word and withou regard to the distributed memory module holding the dat word. It is a further object of the invention to acces data from a memory containing a plurality of data word by utilizing a variation of the content induce transaction overlap (CITO) protocol. It is a further object of the invention to acces data from a memory containing a plurality of data word by searching a column in the memory associated with th highest order bit of the. word for a binary "0" an disabling words containing a binary "1" at times binary "0" is found. It is a further object of the invention t successively search each column of a memory for binar -5- values and to store those words having the opposite value in a word filter memory. It is a further object of the invention to access a complete data word in a memory containing a plurality of data words according to the content of each bit and to disable the word from further access. Brief Description of the Drawing Fig. 1 is a block diagram of one embodiment of the invention. Fig. 2 is a block diagram of a sender. Fig. 3 is a block diagram of one embodiment of an associative memory unit. Fig. 4 is a flow diagram for the operation of sender 32 and associative memory module 12. Fig. 5 is one embodiment of control unit 67 where memory 68 may be a random access memory. Fig. 6 is a block diagram of an alternate embodiment of associative memory module 12. Fig. 7 is a detail block diagram of an associative memory cell. Description of the Preferred Embodiment Referring to Fig. 1, a block diagram of a multi-processor computer system 10 is shown. Multi-processor computer system 10 has a plurality of associative memory modules 12-14. Each associative nenory module 12-14 is coupled over a respective bidirectional bus 16-18 to a respective arithmetic logic unit 20-22. The associative memory module 12, bidirectional bus 16 and arithmetic logic unit 20 function as a processor 24 in multi-processor computer system 10. Associative memory module 13, bidirectional bus 17 and arithmetic logic unit 21 function as processor 25 in multi-processor computer system 10. Likewise, associative memory module 14, bidirectiona bus 18 and arithmetic logic unit 22 function a processor 26 in multi-processor computer system 10. Processor 24 is coupled over bidirectional bus 30 t sender 32. Processor 25 is coupled over bidirectional bus 36 to sender 38. Processor 26 is coupled ove bidirectional bus 40 to sender 42. Each sender 32, 3 and has a respective bidirectional port 44, 46 and 4 which is coupled in common to communication channel 50. Receiver 52 has a bidirectional port 54 which is couple to communication channel 50 and coupled in common t senders 32, 38 and 42. Senders 32, 38 and 42 transmi binary data to one another and to receiver 52 ove communication channel 50 in accordance with the conten induced transaction overlap (CITO) communicatio protocol which is more fully described in U. S. Paten 4, 493,074 which issued January 8, 1985 which i incorporated herein by reference. Each sender 32, 28 and 42 and receiver 52 may hav additional circuitry not shown in Fig. 2 to enabl itself to reconstruct and receive each data wor transmitted on communication channel - 50 using the CIT communication protocol. Fig. 2 shows a schematic block diagram of sende 32. Sender 32 has a word boundary register 56 fo storing the number of bit positions of the data words t be transmitted over communication channel 50. Sender 3 has a bit position register 58 for storing the number o bit positions of a data word remaining to b transmitted. Sender 32 has a channel status registe for comparing the binary level of the data registe corresponding to a particular bit position in the dat word with the binary level of the communication channe 50. Sender 32 has a port 44 for coupling communicatio channel 50 to word boundary register 56, bit positio register 58, channel status register 60 and data register 62 over lead 64. The operation and function of sender 32 is the same as described for sender 10 in U. S. Patent 4,493,074, which issued on January 8, 1985 and is incorporated by reference to describe the operation and function of sender 32, communication bus 50 and receiver 52. As shown in Fig. 2, bidirectional bus 30 is coupled to an input of data register 62 which functions to store a data word or a portion thereof at a time to be transmitted on communication channel 50. Referring to Fig. 1, associative memory modules 12, 13 and 14 may each contain a plurality of words having n bits each to be transmitted over communication channel 50. In the present invention, the order of transmission of words over communication channel 50 is independent of its location in associative memory modules 12, 13 and 14. The order of transmission of words is selected based on the information content in the word or in selected bit positions of the word. Each associative memory module 12, 13 and 14 function to search through its respective memory to locate words having a predetermined information content. For example, the words having the lowest binary value may be transmitted first over communication channel 50 using the content induced transaction overlap (CITO) communication protocol. Each associative memory module 12, 13 and 14 may transfer over its respective bidirectional bus 30, 36 and 40 a word from its associative memory module either one bit at a time or the entire word to its respective sender 32, 38 and 42. After a sender has transmitted a word over communication channel 50, the sender receives an additional word from its respective associative memory module representative of the next word, for example the word having the next lowest binary value from the associative memory module, to be transmitted by the sender over communication bus 50 using the CITO communication protocol. Referring to Fig. 3, a block diagram of one embodiment of associative memory module 12 is shown. In Fig. 3, a control unit 67 is shown which functions to store and access data from memory 68 and to control the flow of data on bidirectional bus 30 and bidirectional bus. Memory 68 may be organized, for example, 128 words by 32 bits. Control unit 67 is coupled to memory 74 by way of bidirectional bus 76. Control unit 67 is also coupled to bidirectional bus 16 to transfer data to and from memory 68. Fig. 4 shows a flow diagram for the operation of sender 32 and associative memory module 12. As shown in block 70, word boundary register 56 is initialized with the value r which is the number of bits in the word. Bit position register 58 is initialized with the value r. Index register 63 is also initialized with the value r. The index register 63 is a pointer which points to one of the data bits in data register 62 to be transmitted. The index regsiter 63 also is a pointer pointing to the corresponding column in memory 68 for accessing a data bit value of one of the words in memory 68. The access word will be loaded into data register 62 on a bit by bit basis. First decision block 72, inquires if the index "i" is less than one indicating that there are no more bits remaining to be transmitted. If "i" is "0", then one word from memory 68 has been transmitted by way of data register 62 shown in Figs. 2 and 3. Decision block 73 inquires if more words to be sent, by sender 32, are in memory 68. If the answer is no, then the procedure or operation ends as indicated by termination block 74. If the answer is yes, then the operation recycles .by returning to block 70 wherein the word boundary register 56, bit position register 58 and index register 63 are initialized with the value r. In decision block 72, if "i" is not less than "1", the program proceeds to block 75. The procedure in block 75 is to sense column i in memory 68 for "0"s. Memory 68 may be a random access memory or may be an associative memory. A custom associative memory may be implemented to provide overlap sensing of bits in a column. The program proceeds to decision block 77 wherein if all "0"s are sensed in column i of memory 68 of words to be searched and excluding the words disabled or excluded, then the program proceeds to procedure block 79. In procedure block 79, the i bit of data register 62 is set equal to "0". If the outcome of the decision block 77 is no, then the program proceeds to decision block 81. If all "l"s are in column i of memory 68 while exluding words in memory 68 which have previously been disabled from further access, and the outcome is yes, then the program proceeds to procedure block 83 wherein the i bit of data register 62 is set to equal "1". If the outcome of decision block 81 is no, then there is a mixture of "l"s and "0"s and the program proceeds to procedure block 85. In procedure block 85, the addresses of the words having a "1" in column i and the value i are stored in a filter memory. The words corresponding to the addresses stored in the filter memory are disabled from further access from memory 68. The program then proceeds to procedure block 79 wherein the i bit of data register 62 is set equal to "0". The program from procedure block 79 proceeds to procedure block 78 where sender 32 transmits a logic "0" on communication channel 50. The program proceeds from procedure block 78 to procedure block 80 wherein the bit position register 58 and the word boundary register 56 and index register 63 are decremented and the program proceeds to decision box 72. The program may then repeat itself where i equals i -1 or the next highest bit in data register 62 and the next highest column in memory 68. If the data bit is a logical "1" as provided b procedure block 83, the program proceeds to procedur block 82 wherein sender 32 keeps silent on communicatio channel 50 and does not transmit the logical "1" dat bit, since the transmission of a "1" bit is to liste only on communication channel 50. The program proceed to decision block 84 which checks the Channel Statu (CS) register 60 by noting the value of channel status register 60 to determine if another sender, for example, sender 38, transmitted a "0" bit. If another sender ha transmitted a "0" bit, the procedure calls the "wait for end of word", procedure block 86. The program then goe to procedure block 88 which performs bit competition. Procedure blocks 86 and 88 may be, for example, subroutines. If sender 32 wins the bit competitio indicated by block 88, the program proceeds to block 8 wherein bit position register 58, word boundary registe 56 and index register 63 are decremented. The progra then proceeds to decision block 72. Reference is mad to U. S. Patent 4,493,074 which issued on January 8, 1985 to C. J. Walter et al. which in Fig. 7 shows a flo diagram containing blocks 70, 72, 74, 78, 80, 82, 84, 8 and 88 which perform like functions corresponding to th same numbered blocks in Fig. 4 herein and which i incorporated herein by reference. Fig. 5 is one embodiment of control unit 67 shown i Fig. 3 where memory 68 may be a random access memory An address counter 94 upon receiving a start signal ove lead 95 cycles through all the addresses contained i memory 68 which may be organized 128 words by 32 bits. The word address from address counter 94 is coupled ove lead 96 to an input of multiplexer 97. The output o multiplexer 97 is coupled over bidirectional bus 69 t memory 68. The address from address counter 94 is als coupled over lead 96 to the address input of word filte memory 98 and the word status memory 99. Word filte memory 98 may be organized 128 words by 32 bits and may initially be written to all "l"s. At the time the program performs procedure block 85 as shown in Fig. 4, word filter memory may be written a "0" in the appropriate word and in the i column and all columns less than the i column. Word status memory 99 may be organized, for example, 128 words by one bit. At the time a particular word in memory 68 is transmitted completely, a "0" may be written for that word in the word status memory 99. The output of word status memory 99 is coupled over lead 100 to an input of NAND gate 101 having an output coupled over lead 102 to an input of NAND gate 103. The output of word filter memory 98 which may be, for example, a word is coupled to a decoder which selects the i bit in accordance with the signal on lead 30'. The i bit is coupled over lead 105 to a second input of NAND gate 101. The output of NAND gate 103 is coupled over lead 106 to an input of NAND gate 107. Memory 68 has an output over lead 16' which is coupled through decoder 108 which selects one bit of the data word on lead 16'. Decoder 108 has a control input coupled over lead 30' to provide selection of the i bit which is coupled through decoder 108 over lead 109 through NAND gate 110 to an input of NAND gate 107. The output of NAND gate 107 is coupled over bidirectional bus 30 to sender 32 as shown in Fig. 1. In operation of control unit 67, the i value from index register 63 is coupled over lead 30' to kU L~ decoders 104 and 108 to select the i column or i bit of the words read out of word filter memory 98 and memory 68. A start signal to address counter 94 addresses all the words in memory 68 one at a time and the corresponding word in word filter memory 98 and word status memory 99. The outputs of word filter memory 98 and word status memory 99 are OR'd together to provide an inhibit signal if a "0" is on lead 105 or 100. The inhibit signal is on lead 106. The output of memory 68, and in particular, the i bit of each word read out of memory 68 is inverted by NAND gate 110. NAND gate 107 will provide a "0" on bidirectional bus 30 if the i bit of the word read out of memory 68 is a "0" and the inhibit signal on lead 102 is a "0". Word filter memory 98 functions to disable or exclude words in memory 68. Word status memory 99 functions to disable or exclude words from memory 68 which have been transmitted or which are desired not to be transmitted on communication channel 50. Fig. 6 is a block diagram of an alternate embodiment of associative memory module 12. Control unit 67' contains a memory 114 for storing bit positions or columns where words were disabled in memory 68 due to the presence of "l"s in addition to the presence of "0"s. Memory 114 may be a push down stack where bit positions or columns are stored and read out according to last in first out, which is well known in the art. A register 115 stores the sequence of data bits read out of memory 68* . Memory 68' comprises word decoder 116, content-addressable storage 117 and sensing block 118. Word decoder 116 receives an address over bus 119. Word decoder 116 functions to select a word in content-addressable storage 117 during write operation when data is loaded into content-addressable 117. Data is written into a selected word by activating control line 120 through 123 while the data to be written is presented on leads 124-127. Leads 128-131 couple word decoder 116 to respective words within content-addressable storage 117. Fig. 7 is a detail block * diagram of an associative memory cell 134 which may be identical to each memory cell in content-addressable storage 117. In Fig. 1 , memory cell 134 has a memory bit 135 which includes logic to write data into memory bit 135 dependent upon the data on lead 124 and control signal 120 and word line 131. Further, memory bit 135 contains logic to perform comparison with the data stored in memory bit 135 when control lead 124 is pulsed in a first manner to indicate that each memory cell should compare its contents with "0" or pulsed in a second manner to indicate each memory cell in the column should compare its data with a "1". At times the contents of memory bit 135 compares with a "0" or "1" as determined by the signal on control lead 124, a signal indicative of a match is coupled out on lead 136 to sensing block 118. Each memory cell also has a flip-flop 137 for storing the activation status of memory cell 135 at times an activation signal on lead 138 goes high. For example, if the output of memory bit 135 indicates a match on lead 136, lead 138 may go high to store a "1" in flip-flop 137. For example, if memory bit 135 contains a "1", then a "1" may be stored in flip-flop 137 which in turn will generate an inhibit signal to render succeeding lower bits of the word dormant or inhibited from further readout. Thus, words containing a "1" in a particular column may be removed from subsequent readout from content-addressable storage 117. At a later time, flip-flop 137 may be reset by a separate control line or by a different activation signal on lead 138 to cause flip-flop 137 to reset. Sensing block 118 may store the match outputs of the memory cells in biphase such as "01" or "10" and may contain logic to determine if any match signals were obtained indicative of a "0". Further, sensing block 118 may contain logic to determine if match signals were obtained indicative of all "l"s stored in a column. Sensing block 118 may also contain logic to determine if a mixture of "0"s and "l"s were stored in a particular column. Also, sensing block 118 may contain logic to determine if all sensing lines were dormant during a comparison search for "0"s and "l"s. In operation of control unit 67' and memory 68*, data to . be transmitted on communication channel 50 may be loaded into content-addressable storage 117 on a word by word basis by appropriate signals to word decoder 116 and appropriate signals on control leads 124-127 indicative of data to be stored and control leads 120-123. The column representitive of the highest order bit may be searched for "0"s. If a mixture of "0"s and **l"s are found, the words containing "1" may have their flip-flop 137 set to a "1" by an appropriate control signal on lead 138 while memory bit 135 indicates a match indicative of a "1" stored in memory bit 135. The storing of a "1" in flip-flop 137 will result in a signal to succeeding bits in the same word which will render the word dormant from further readout. The bit position will also be stored in memory 114. After one word has been completely read out of content-addressable storage 117, the last bit position to be stored in memory 114 will be read out and functions as a pointer to the column for read out of the next word from content-addressable storage 117. The column indicated by memory 114 will have its flip-flops 137 reset so that words previously dormant will be reactivated. It is understood that the column that memory 114 will point to will contain a "1" and thus, a "1" may automatically be indicated for that column. A comparison for "0 M s may then be conducted on the next column having a lower bit position. A method and apparatus for transmitting data from a plurality of senders to a receiver over a single communication channel 50 has been described characterized by the steps of storing in a memory 68 a plurality of data words with each bit position "0" through n of the plurality of data words corresponding to a respective column "0" through n in the respective memory, storing in a word boundary register in a respective sender the number of bit positions of the plurality of data words, storing in a bit position register in each respective sender, the number of bit positions of the plurality of data words, first determining if a "0" is stored in column n of each respective memory, if a "0" is stored in column n, storing a "0" in a data register in the sender indicative of the "0" in the column n of the respective memory, disabling in the respective memory each word having a "1" in the column n from further readout and storing in a respective second memory, the column position n with the word address of each word having the "1" stored in column n, if a "0" is not stored in column n, storing a "1" in the data register in the sender indicative of the "1" in the column n, each sender transmitting the highest order data bit in the data register to the communication channel 50, detecting the state of the communication channel by each sender to determine when the state of the communication channel is the same as the state of the transmitted data bit; second determining if a "0" is stored in column n -1 of each memory, respectively, if a "0" is stored in column n -1, storing a "0" in the data register in the sender indicative of "0" in the column n -1 of the respective memory, disabling in the respective memory each word not previously disabled having a "1" in the column n -1 from further readout and storing in the respective second memory, the column position n -1 with the word address of each word having the "1" stored in the column n -1, if a "0" is not stored in column n -1, storing a "1" in the data register in the sender indicative of all n l n s in column n -1, each sender transmitting the next highest order data bit when the state of the channel is the same as the state of the transmitted data bit, repeating the second determining step for columns n -2 through "0" of each memory, respectively, at which time each data register of each sender will contain a data word and whereby the column position and word address of each disabled word will be stored in the respective second memory, successively transmitting the next highest data bit from each sender when the state of the channel is the same as the state of the transmitted data bit. The invention claimed is:

Claims: 1. A method for accessing data from a memory (68) having a plurality of words stored therein with each bit position "0" through n of said plurality of words corresponding to a respective column "0" through n in said memory (68) comprising the steps of: first determining if a "0" is stored in column n of said memory (68) , if a "0" is stored in column n, storing a "0" in a data register (62) indicative of said "0" in said column n and disabling each word having a "1" in said column n from further readout and storing the column position n with said word address of each word having said "1" stored in column n, if a "0" is not stored in column n, storing a "1" in said data register (62) indicative of said "1" in said column n, second determining if a "O" is stored in column n -1 of said memory (68) of words not previously disabled, if a "0" is stored in column n -1 of words not previously disabled, storing a "0" in a data register (62) indicative of said "0" in said column n -1 and disabling each word having a "1" in said column n -1 from further readout and storing the column position n -1 with said word address of each word having said "1" stored in column n -1, if a "0" is not stored in column n -1 of words not previously disabled, storing a "1" in said data register (62) indicative of said "1" in said column n -1, repeating said second determining step for columns n -2 through "0" at which time said data register (62) will contain a first word and whereby the column position and word address of each disabled word will be stored. 2. The method of Claim 1 wherein a second word is retrieved from said memory (68) comprising the steps of: disabling said word addresses of said first word, third determining the smallest value c of the column 5 positions stored, enabling each word address associated with said column position c to further readout, storing a "1 H in said data register (62) indicative of said "l" in said column c, lø fourth determining if a "O" is stored in column c -1 of said memory (68), if a "O" is stored in column c -1 of words not previously disabled, storing a n 0 n in said d^ta register (62) indicative of said "O" in said column c -1 and j L5 disabling each word having a "1" from further readout and storing the column position c -1 with said word address of each word having said "1" stored in column c -1, repeating said third determining step for columns c -2 through "O", whereby said data register (62) will contain 2 Q at least a partial word and whereby the column position and word address of each disabled word will be stored. 3. A method for transmitting data from a plurality of senders (32, 38, 42) to a receiver (52) over a single communication channel (50) characterized by the steps of: 25 storing in a memory (68) coupled to each sender (32, 38, 42) respectively a plurality of data words with each bit position "O" through n of said plurality of data words corresponding to a respective column "O- 1 through n in said respective memory (68), 30 storing in a word boundary register { 56 ' ) in each sender (32, 38, 42) the number of bit positions of said plurality of data words, storing in a bit position register (58) in each sender (32, 38, 42) the number of bit positions of said plurality 5 of data words, first determining if a "O" is stored in column n of each said memory (68), respectively, if a "0" is stored in column n, storing a "0" in a data register (62) in said sender (32, 38, 42) indicative of said "0" in said column n of said respective memory (68), disabling in said respective memory (68) each word having a "1" in said column n from further readout and storing in a respective second memory (98), the column position n with said word address of each word having said "l" stored in column n, if a ■, 0 M is not stored in column n, storing a "l" in said data register (62) in said sender (32, 38, 42) indicative of said "l" in said column n, each sender (32, 38, 42) transmitting the highest order data bit in said data register (62) to said communication channel (50), detecting the state of the communication channel by each sender to determine when the state of the communication channel is the same as the state of the transmitted data bit; second determining if a w 0" is stored in column n -1 of each said memory (68), respectively, if a "0 W is stored in column n -1, storing a "O" in said data register (62) in said sender (32, 38, 42) indicative of said "0" in said column n -1 of said respective memory, disabling in said respective memory (68) each word not previously disabled having a "l" in said column n -1 from further readout and storing in said respective second memory (98), the column position n -1 with said word address of each word having said w l" stored in column n -1, if a "0" is not stored in column n -1, storing a "1" in said data register (62) in said sender (32, 38, 42) indicative of said "1" in said column n -1, each sender (32, 38, 42) transmitting the next highest order data bit when the state of the communication channel (50) is the same as the state of the transmitted data bit, repeating said second determining step for columns n -2 through "0" of each said memory (68), respecti ely, at which time each said data register (62) of each sender (32, 38, 42) will contain a data word and whereby the column position and word address of each disabled word will be stored in said respective second memory (98), successively transmitting the next highest data bit from each sender (32, 38, 42) when the state of the communication channel (50) is the same as the state of the transmitted data bit, successively decrementing said word boundary register (56) and bit position register (58) for each transmitted data bit whose state was the same as the state of communication channel (50); terminating the transmission of the remaining data 10 bits by each sender (32, 28, 42) whose transmitted data bit is different from the state of the communication channel (50); waiting by each sender (32, 38, 42) which has terminated the transmission of its remaining data bits , 5 until the transmission of the data word currently being transmitted is completed; for each sender (32, 38, 42) that has successfully transmitted a data word from its data register (62) performing the steps of: accessing from its second memory 20 (98) the lowest column position Q stored in said second memory (98) and storing said lowest column position Q in the bit position register (58) of said respective sender (32, 38, 42), enabling each word in each respective memory (68) 2 5 previously disabled and stored in said second memory (98) with bit position Q, third determining if a "O" is stored in column Q of each said memory (68), respectively, if a "O" is stored in column Q, storing a "0" in said data register (62) in said 3 Q sender (32, 38, 42) indicative of said "0" in said column Q of said respective memory (68), disabling in said respective memory (68) each word having a "l n in said column Q from further readout and storing in said respective second memory (98), the column 35 position Q with said word address of each word having said "1" stored in column Q, if a "O" is not stored in column Q, storing a "1" in said data register (62) in said sender (32, 38, 42) indicative of said "1" in said column Q, repeating said third determining step for columns Q -1 through "O" of each said memory (68), respectively at which time each said data register (62) of each sender (32, 38, 42) will contain a data word and whereby the column position and word address of each disabled word will be stored in said respective second memory (98), perform bit competition in response to the end of the transmitted data word to determine if the content of the senders (32, 38, 42) bit position register (58) is lexicographically indicative of the next smallest data word. 4. A memory (68 67 1 ) for accessing selected bits stored therein based upon its contents, one column at a time comprising: an array (117) of memory (134) for storing binary bits of information cells arranged in a plurality of rows and a plurality of columns, means (116, 67') for writing information into said array (117) of memory cells (34), means for presenting a selected data bit to each memory cell (134) in a selected one of said plurality of columns, each said memory cell (134) including means (67', 139) for comparing said selected data bit with the binary bit (135) of information stored in said memory cell (134) in said selected column and means (139) for providing a first signal on a lead (136) coupled to each memory cell (134) in said row indicative of a match at times said selected data bit (67') is the same as said binary bit (135) of information stored in said memory cell (134), each said memory cell (134) further including a register (137) associated therewith for storing the status of said memory cell (134) in said selected column in response to said first signal (136) and means (137) for generating a second signal on a lead (140) coupled to each me ory cell (134) in said row in columns of lesser number each said memory cell (134) including means responsive to said second signal to disable said memory cell (134) from comparing selected data bits presented in a subsequent 5 selected column, and means (67 » ) for resetting said register (137) associated with each memory cell (134) in a selected column. 5. A memory (68', 67') for accessing selected bits 10 stored therein based upon its contents, one column at a time comprising: an array (117) of memory (134) for storing binary bits of information cells arranged in a plurality of rows and a plurality of columns, j L5 means (116, 67') for writing information into said array (117) of memory cells (134), means for presenting a selected data bit to each memory cell (134) in a selected one of said plurality of columns, 20 each said memory cell (134) including means (67', 139) for comparing said selected data bit with the binary bit (135) of information stored in said memory cell (134) in said selected column and means (134) for providing a first signal on a lead (136) coupled to each memory cell (134) 25 in said row indicative of a match at times said selected data bit (67') is the same as said binary bit (135) of information stored in said memory cell (134), each said memory cell (134) further including a register (137) associated therewith for storing the status 30 of said memory cell (134) in said selected column in response to said first signal (136) and means (137) for generating a second signal (140) coupled to an adjacent memory cell (134) in a column of lesser number in said row, each said memory cell (134) including means (137) 5 responsive to said second signal to disable said memory cells (134) from comparing selected data bits presented, and means (67') for resetting said register (137) associated with each memory cell (134) in a selected column.

Inventors: BERKOVICH SEMYON, BERKOVICH, SEMYON
Applicants: ALLIED SIGNAL INC, ALLIED-SIGNAL INC.
Application year: 1989
Main classification: G06F12
IPC codes: G06F13, G11C15