Write-read/write-pass memory subsystem cycle

Abstract: Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently writes the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently writes the portion of the transferred data that is most current in the SCU memory and reads the written data that is most current in the SCU memory and reads the written data for transfer to the requesting CPU.

Description: Field Of The Invention The present invention relates to digital computer memory control systems, and more particularly to methods and apparatus for initiating multiple operation commands for central processor unit (CPU) to central processor unit (CPU) data transfers in a digital computer system including a system control unit (SCU) and multiple CPU's. Background Of The Invention In a digital computer system which includes an SCU with an associated main memory and multiple independent CPU's, each CPU with its own associated writeback cache, data stored in the SCU main memory may be invalid because more current data has been entered into one of the CPU's and stored into its associated CPU cache. A CPU in the system which requests selected data must find out if the version of the requested data stored in the SCU main memory is the most current version, or if not, the location of the CPU cache in which the most current version is stored. To this end, the SCU may contain a data storage location directory which includes a cache consistency unit (CCU) which indicates if the requested data stored in the SCU main memory has been invalidated, and the CPU cache location for the refreshed version of the requested data. To provide the requesting CPU with data which is stored in the cache of another CPU, it has been necessary to read the data of the CPU cache in which the most current version of the requested data is located, transfer the read data back to the SCU, and then write the received data into the SCU main memory so that the received data replaces the less current version of the requested data already stored in the SCU main memory. After the refreshed data received from the located CPU is written into the SCU main memory, the SCU main memory is read se that the refreshed data can be transferred to the requesting CPU. However, the above described procedure involves significant memory read latency because the SCU must first initiate a write cycle with a "WRITE" command to enter the refreshed data transferred to it into memory, and then, when the write cycle is complete, initiate a read cycle for the same data address with a "READ" command to transfer the most current version of requested data written in the SCU main memory to the requesting CPU. Thus, two complete SCU main memory cycles are necessary every time requested data is transferred to a requesting CPU from a cache of another CPU through the SCU. An article by Tang entitled "Cache System Design in the Tightly-Coupled Multiprocessor System" (Proceedings of the National Computer Conference, New York, 7-10 June 1976, vol.45, pages 749-753, AFIPS, Montvale, US), shows a multiprocessor system like that described above. Tang teaches that data blocks found to reside in another cache are first transferred to the main memory, written to memory in their entirety, read from memory in their entirety, and finally sent on to the requesting CPU. US Patent No. 3,984,818 to Gnadeberg et al. teaches a memory arrangement wherein a buffer store is placed between a processor and a main store. In the embodiment of Figure 2, a word portion is written to the buffer store in the event of a buffer store hit, and then the entire word block containing that word portion is read out of the buffer store and written to a main store. In the even of a buffer store miss during a write, the word block is read from the main store, the retrieved word block is combined in a buffer store register with the word portion to be written, and the word block so modified is then written back to the main store. Gnadeberg et al. does not teach any method for cache coherency in a multi-processor system, nor any scheme for reducing memory latency in such a system in the event of a cache miss. EP-A-0095598 teaches a multi-processing systems having a scheme whereby caches are cross-interrogated on a cache miss, and the data found in an interrogated cache is sent directly to the requesting cache bypassing main memory. In that system the main memory is not involved in cache-to-cache transfers at all. Summary Of The Invention The present invention minimizes memory read latency when requested data is transferred from the cache of a located CPU through the SCU to a requesting CPU by using new cycles which combine two operations at once with a single command. These new cycles may be termed a "WRITE-READ" cycle and a "WRITE-PASS" cycle. The "WRITE-READ" cycle permits the SCU to perform a write cycle and a read cycle to the same address concurrently. The "WRITE-PASS" cycle allows the SCU to concurrently write data received from a CPU and pass the same data onto another CPU in one cycle. The "WRITE-READ" and "WRITE-PASS" cycles are initiated with single commands. Description Of The Drawings Figure 1 is a block diagram of a typical digital computer system with a SCU and associated independent CPU's suitable for incorporating the present invention. Figure 2 is a basic flow chart of logic steps for the preferred embodiment of the invention adapted for use with the system shown Figure 1. Figure 3 is a typical block diagram of the preferred embodiment of the invention for use with the digital computer system shown in Figure 1. Detailed Description Of The Preferred Embodiment Referring to the drawings, wherein like reference characters designate like or corresponding parts throughout the views, Figure 1 shows a typical digital computer system 2 suitable for incorporating the present invention. The system 2 includes a system control unit (SCU) 4 with an associated SCU main memory 6 and SCU data storage location directory 8. The directory 8 includes a cache consistency unit (CCU) 10 which indicates, for any requested data address from the SCU main memory 6, if the SCU main memory 6 data is superceded by a more current version of the requested data elsewhere in the system 2 with implementation well known in the art. The SCU 4 is typically interconnected to a plurality of independent central processing units (CPU's) 12 via individual associated data bus links 14. Each one of the CPU's 12 has a writeback cache 16, a control unit 18 and an input/output (I/O) unit 20. As well known in the art, the CPU's 12 may individually accept and store data in their associated caches 16. This data may not be in the SCU main memory 6 or may include a refreshed (more current) version of data that is stored in the SCU main memory 6. Also in accordance with the prior art, the addresses of data written into the individual CPU's 12 are transferred to the SCU 4 for storage in the SCU data storage location directory 8, and the CCU 10 indicates which SCU main memory 6 data has been superceded by more current versions in one of the CPU caches 16. As part of the data transfer process from one of the CPU's 12 through the SCU 4 and to a requesting one of the CPU's 12, it is highly desirable to not only transfer the most current version of the data requested to the requesting one of the CPU's 12 from another one of the CPU's 12, but also to update the SCU main memory 6 at the same time, while also registering in the SCU directory 8 that the SCU main memory now has the most current version of the requested data. In this way, additional requests for the same data may be read from the SCU main memory 6, until one of the CPU's 12 refreshes the requested data still further. However, the above described process of refreshing the SCU main memory 6 with the transferred data according to the prior art generally involves at least the execution of two distinct commands, a "WRITE" command to write the transferred data received by the SCU 4 at a selected address, followed by a "READ" command at the same address. The use of two such distinct commands then requires the execution of two complete data transfer timing cycles for the SCU main memory 6, thereby at least doubling memory read latency relative to a single cycle data transfer operation. The present invention eliminates memory read latency caused by the need for two distinct commands and two complete data transfer timing cycles for the SCU main memory 6 by using combined operation cycles for the process of transferring the requested data between the CPU's 12 and concurrently storing the transferred data into the SCU main memory 6. When the transferred data has been validated as the most current version by the SCU directory 8, a "WRITE-PASS" cycle is used. This cycle allows the validated data to be passed through the SCU 4 to the requesting CPU 12 as the validated data is written into the SCU main memory 6. When the transferred data has not been validated by the SCU directory 8, a "WRITE-READ" cycle is used. This cycle allows only validated portions of the transferred data to be written into the SCU main memory 6, and in the same cycle, for the SCU main memory 6 to be read for transfer of data requested by the requesting one of the CPU's 12. Thus, for the "WRITE-READ" cycle, only the validated portion of the data transferred to the SCU 4 in response to the data request from the requesting one of the CPU's 12 is written into the SCU main memory 6, whereas all of the data requested by the requesting one of the CPU's 12 is read from the SCU main memory 6. The read data contains the validated portion of the data received by the SCU 4 which was written into the SCU main memory 6. The data transferred to the SCU 4 from the located one of the CPU's 12 is transferred into an SCU memory subsystem 22. The memory subsystem 22 includes a data write buffer 24, a data bypass multiplexer 26 and a data read buffer 28. The memory subsystem 22 serves to sequence and transfer the data transferred to the SCU 4 so that the data flow through the SCU 4 is controlled with the "WRITE-PASS" and "WRITE-READ" operations described above. The SCU 8, the SCU main memory 6, the CCU 10, the SCU memory subsystem 22, the write buffer 24, the bypass multiplexer 26 and the read buffer 28 are all components well known in the art. They may be interconnected in a variety of well known configurations, and are shown in block form in Figure 1 for purposes of representation only, since they do not in themselves constitute part of the present invention. Likewise, each CPU 12, the CPU cache 16, the control unit 18 and the I/O unit 20 shown as part of each of the CPU's 12 are well known components which may be interconnected in a variety of well known configurations and are shown in block form for purposes of representation only, since they do not in themselves constitute part of the present invention. The methodology of the present invention is shown in the system flow chart of Figure 2. The SCU directory 8 determines that the most current version of data requested by a requesting one of the CPU's 12 is not in the SCU main memory 6, but rather in another one of the CPU's 12 located by the SCU directory 8 according to methodology well known in the art. The data transferred from the located one of the CPU's 12 with the most current version of the requested data is transferred to the memory subsystem 22 of the SCU 4. The SCU 4 command information is processed by the memory subsystem 22 to decode the proper address for selection of the requested data from the SCU main memory 6. The selected address is then passed from the memory subsystem 22 to the SCU main memory 6. The timing cycle for the SCU main memory 6 is then indicated. Before data retrieved from the located one of the CPU's 12 is passed to the SCU main memory, its validity as the most current version of the requested data is checked in the memory subsystem 22. If the checked data is validated, it is loaded into the write buffer 24 and the write buffer 24 then concurrently transfers the loaded data into both the SCU main memory 6 and the bypass multiplexer 26. If the checked data is not validated by the memory subsystem 22, the data is also loaded into the write buffer 24, but then only the valid portions of the loaded data are written into the SCU main memory 6 at the selected address. As the write cycle for the selected address is completed, the memory subsystem 22 indicates a read cycle of the SCU main memory 6 at the selected address. The data read from the SCU main memory 6 at the selected address is then a mixture of new validated data transferred from the located one of the CPU's 12 and the old data already stored in the SCU main memory 6. The read data is then passed to the bypass multiplexer 26. The bypass multiplexer 26 provides a common transfer point for the validated data passed to it directly from the write buffer 24 and the read data at the selected address from the SCU main memory 6. The bypass multiplexer 26 transfers either the validated data received from the write buffer 24 or the read data from the selected address of the SCU main memory 6 into the read buffer 28. The read buffer 28 then transfers the buffered data to the requesting one of the CPU's 12. Thus, when the most current version of data requested by a requesting one of the CPU's 12 is only available from the cache 16 of another one of the CPU's 12, the requested data is retrieved from the located one of the CPU's 12 and then transferred through the SCU 4 to the requesting one of the CPU's 12 with one of two possible dual operation program cycles which both update the SCU main memory 6 as the requested data is transferred through the SCU 4. When the data retrieved from the located one of the CPU's 12 is confirmed valid (most current) by the memory subsystem 22, the data is written into the SCU main memory 6 while being transferred through the memory subsystem 22 to the requesting one of the CPU's 12 without any subsequent read cycle of the SCU main memory 6. When the retrieved data cannot be confirmed valid by the memory subsystem 22, the portions of the retrieved data that can be determined valid are written at the selected address for the requested data in the SCU main memory 6. The SCU main memory 6 is then read in its entirety at the same selected address in the same operation, providing read data corresponding to the requested data. The read data is a mixture of the valid portions of the data retrieved from the located one of the CPU's 12 along with portions of stored data in the SCU main memory 6 which correspond to the other portions of the requested data. The read data forms a complete data transfer of the requested data for the requesting one of the CPU's 12. A preferred embodiment of the SCU memory subsystem 22 is shown in Figure 3. The SCU memory subsystem 22 receives command information from the SCU 4 in an address decoder 30 on a command line 32. The address decoder 30 decodes the selected address for storage of the retrieved data in the SCU main memory 6 from the command information. The decoded address from the address decoder 30 is fed to a main memory controller 34 via an address line 36. The memory controller 34 transmits the selected address into the SCU main memory 6 via a select line 38. The memory controller 34 then begins a timing cycle for the SCU main memory 6, with reference clock signals fed to the main memory 6 via a clock line 40 and memory array strobe signals fed to the main memory 6 via a memory array strobe line 42 to lock in the selected address. The memory subsystem 22 also includes a validity checker 44 to check the validity of the data retrieved from the located one of the CPU's 12 fed to the validity checker 44 via a validity input line 46. The retrieved data is also fed to the write buffer 24 via a write buffer input line 48. The write buffer 24 may typically include latching circuitry to latch and store the retrieved data until released by a write data latch signal supplied by the main memory controller 34 and fed to the write buffer 24 via a write buffer latch line 50. The validity checker 44 feeds a validity signal to the main memory controller 34 via a validity signal line 52. If the validity signal on the line 52 indicates a valid condition, the main memory controller 34 unlatches the data stored in the write buffer 24 with the write buffer latch signal on the line 50 to feed the unlatched data to the SCU main memory 6 via a write buffer output line 54 at the selected address transmitted to the SCU main memory 6 on the line 38. Concurrently, the main memory controller 34 feeds a multiplexer latch signal to the bypass multiplexer 26 via a multiplexer latch line 56 allowing the data unlatched by the write buffer 24 to pass through the bypass multiplexer 26 via a bypass line 58 into the read buffer 28 via a read buffer input line 60. The data fed into the read buffer 28 is latched with a read buffer latch signal on a read buffer latch line 62, and then the latched data is released from the read buffer 28 by the main memory controller 34 at the end of the operation cycle with the read buffer latch signal. The data released by the read buffer 28 is then transmitted to the requesting one of the CPU's 12 via a read buffer output line 64. If the validity signal on the line 52 does not indicate a valid condition, the main memory controller still unlatches the data stored in the write buffer 24 with the write buffer signal on the line 50, but the main memory controller 34 does not feed the bypass multiplexer 26 with the multiplexer signal on the line 56, so that the released data is only fed to the SCU main memory 6 on the line 54. As is well known, the main memory controller 34 only unlatches those portions of the received data confirmed valid by the validity checker 44. After all the validified data is written, the main memory controller 34 commands the SCU main memory 6 to read the data stored at the selected address with a select signal on the line 38. The read data from the output of the SCU main memory 6 is fed to the bypass multiplexer 26 via a memory output line 66. The bypass multiplexer 26 passes the data read by the SCU main memory 6 to the read buffer 28 via the line 60. The data fed into the read buffer 28 is latched with the read buffer latch signal on the line 62, and then the latched data is released from the read buffer 28 by the main memory controller 34 for transmission to the requesting one of the CPU's 12 via the read buffer output line 64. The address decoder 30, the memory controller 34 and the validity checker 44 shown in Figure 3 are all well known components which may be interconnected in a variety of well known configurations, and are shown in block form in Figure 3 for purposes of representation only, since they do not in themselves constitute part of the present invention. Thus, there has been described above memory subsystem cycles for an SCU with a main memory which minimizes memory read latency when data is transferred from the writeback cache of a selected CPU through the SCU to a requesting CPU and the transferred data also updates the main memory. The cycles include one dual operation mode, a "WRITE-BYPASS" cycle, which with transferred data confirmed valid concurrently writes the transferred data into a selected address of the SCU main memory and transfers the data on to the requesting CPU without any intervening read cycle, and another dual operation mode, a "WRITE-READ" cycle, which with transferred data not confirmed valid writes portions of the unconfirmed data which is determined to be valid in the SCU main memory, and then reads the same selected address in the SCU main memory in the same operation, and transmits the read data to the requesting CPU. It will be understood that various changes in the details, arrangements and configurations of the parts and assemblies which has been described and illustrated above in order to explain the nature of the present invention may be made by those skilled in the art within the scope of the present invention as expressed in the appended claims.

Claims: For a digital computer system having a system control unit SCU (4) with a main memory (6) and a plurality of central processing units (CPU's) (12), each CPU with its own associated writeback cache (16), a method of transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and updating said SCU main memory, comprising the steps of: establishing (8) in said SCU that said requested data is valid as the most current version not in the main memory (6) but in the cache of said selected CPU; transmitting said requested data from said cache of said selected CPU to said SCU; checking said transmitted data to establish that said transmitted data is all valid data or only partially valid data; if said transmitted data is established as all valid data then (a) transmitting said all valid data to said requesting CPU; and (b) concurrently writing said all valid data in said SCU main memory at a selected address; or, if said transmitted data is established as only partially valid data then (a) determining the valid portions of said transmitted data; (b) writing only said valid portions of said data in said SCU main memory at a selected address while in the same operation reading from said SCU main memory at said selected address data being a mixture of the valid portions of said transmitted data with portions of data stored in the main memory which correspond to the other portions of the requested data; and (c) transmitting said read data to said requesting CPU. The method of transferring as set forth in claim 1 further comprising the steps of: receiving (32) command information from said SCU; decoding (30) a memory address in said main memory for said requested data from said command information; transmitting (36,34,40,42) said decoded addresses (38) to said main memory; and latching said decoded address in said main memory. In a digital computer system having a system control unit SCU (4) with a main memory (16) and a plurality of central processing units (CPU's) (12), each CPU with its own associated writeback cache (16), apparatus for transferring requested data to a requesting one of the CPU's from the cache of a selected one of said other CPU's through said SCU and updating said SCU main memory, comprising: means (16,18,48) means (8) for establishing that said requested data is valid as the most current version not in the main memory (6) but in the cache of said selected CPU; for transmitting said requested data from said cache of said selected CPU to said SCU; means (44) for checking said transmitted data to establish that said transmitted data is all valid data or only partially valid data; means (34,26,28) for transmitting said all valid data to said requesting CPU; means (34,26) for initiating the writing of said all valid data in said SCU main memory at a selected address concurrently with transmitting said all valid data to said requesting CPU; means (44) for determining the valid portions of said only partially valid data; means (34,26) for initiating the writing of only said valid portions of said only partially valid data in said SCU main memory at said selected address while in the same operation initiating the reading from said SCU main memory at said selected address of data being a mixture of the valid portions of said transmitted data with portions of data stored in the main memory which correspond to the other portions of the requested data; and means (34,28) for transmitting said read data to said requesting CPU. The apparatus for transferring as set forth in claim 3 further comprising means for receiving command information from said SCU; means (30) for decoding a memory address in said main memory for said requested data from said command information; means (34) for transmitting said decoded address to said main memory; and means for latching said decoded address in said main memory.

Inventors: CHINNASWAMY KUMAR, GAGLIARDO MICHAEL, LYNCH JOHN J, TESSARI JAMES E, CHINNASWAMY, KUMAR, GAGLIARDO, MICHAEL, LYNCH, JOHN J., TESSARI, JAMES E.
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1989
Main classification: G06F12
IPC codes: G06F15, G06F12