Integrated circuit package structure

Abstract: An integrated circuit, for example a hybrid integrated circuit, including a circuit substrate (2) on which active and/or passive elements (6, 7, 7′) are formed, a lead frame (9) having a support plate (8) which has an opening (80a) therein and supports the circuit substrate (2) thereon, and a mold (4) of resin for packaging the circuit substrate (2), support plate (8), and inner leads (31) of the lead frame. A bottom surface of the circuit substrate (2) is exposed and made free to contact the mold resin through the opening (8a). The integrated circuit has a ratio of exposed bottom surface to total bottom surface greater than 50%, and preferably has a ratio of surface area of the circuit substrate (2) to principal surface area of the mold (4) greater than 60%. This structure relieves mechanical stress caused in the mold package and eliminates or reduces occurrences of crack defects in the mold. Further, an integrated circuit package structure for avoiding or reducing deformation thereof is provided in accordance with the invention in which mold thicknesses above (x₁) and below (x₂) the circuit substrate (2) are selectively chosen (Fig. 15(b)). Further, an integrated circuit package structure is provided in accordance with the invention in which elements can be mounted on both main surfaces of a base member (5) (Figs. 11).

Description: The present invention relates to integrated circuits and more particularly to package structures for integrated circuits, including hybrid integrated circuits in which active and passive elements are incorporated. For package structures for semiconductor integrated circuits or hybrid integrated circuits, epoxy resin is very popular and widely used as a molding material, and an insert-mold method is utilised which lends itself to mass production. A circuit substrate and a lead frame are incorporated in molding material during the mold process. Figs. 1(a) and 1(b) show respectively a schematic cross-sectional view of a conventional hybrid integrated circuit and a plan view of a lead frame used therein. The lead frame 60 has a square support plate 61 centrally arranged, which plate is sometimes called a stage or tab. On the support plate 61 a circuit substrate 62 is mounted and is selectively connected to leads 63 by a wire bonding method. The above structure is finally molded as a package 64 of epoxy resin material. The circuit substrate 62 comprises a base member 66, for example of alumina ceramic, epoxy glass or silicon, and active and passive elements 67 disposed on the base member 66. In the package structure such as disclosed above, differences in expansion coefficients, adhesion characteristics, etc., between the various constituent parts comprised therein can cause a problem of cracking of the mold package. Usually, the expansion coefficient of the base member 66 is smaller than that of the molding material, and adhesive strength between the mold material and the support plate 61 (e.g. a metal plate) is less than that between the mold material and the base member 66. When the device (hybrid integrated circuits or integrated circuits are sometimes called devices, for brevity, in the present application) is put into operation and is subjected to repeated heat cycles of expansion and contraction, the lower portion of the mold package 64 may not withstand the stress induced, which is concentrated along a periphery of the support plate 61, and finally the mold package 64 of the device may manifest a crack 65 along a side or along two neighbouring sides of the square periphery of the support plate, as shown in Fig. 1(a). In order to relieve stress at the support plate, arising due to its different expansion characteristics as compared with the mold material, an idea of forming a lead frame which has an opening or a void portion in the support plate was disclosed in the Japanese Unexamined Patent Publication JP-52-95173 dated 10th August 1977 by S. Kobayashi. The patent discloses that the support plate of the lead frame is composed of a surrounding peripheral frame portion with either a single or a plurality of openings formed therein. Another idea was disclosed in Japanese Unexamined Patent Publication JP-63-81966 dated 12th April 1988 by H. Tsutani, et al. The patent discloses that the device comprises a lead frame, a support plate thereof having a plurality of cuts extending from its periphery towards the centre of the support plate. The two disclosures mentioned above are concerned each with a semiconductor integrated circuit which comprises a single monolithic semiconductor chip mounted on the support plate. Generally, the semiconductor chip size (surface area) is comparatively small compared with the outline dimensions of the mold package. Patent Abstracts of Japan 8(099),(E-243) (Publication NO. 59-016357) discloses a lead frame with holes. The holes are filed with mold resin when the lead frame, with a pellet mounted thereon, is resin sealed. This constitution is said to provide a package which is strong with regard to thermal stress and moisture, etc.. With the trend towards higher integration, a hybrid integrated circuit, which comprises a circuit substrate and a plurality of active and passive elements mounted thereon, has come to be larger in size, so that the circuit substrate occupies a substantial part of the molding size. In these circumstances, the stress generated in the mold package during operation becomes a serious problem. According to the present invention there is provided an integrated circuit, comprising:- a circuit substrate, comprising a base member and at least one semiconductor element, an active element or a passive element, disposed on the base member, a lead frame comprising at least a plurality of leads and a support plate, respectively provided at outward and inward portions of the lead frame, and each lead having an inner lead portion and an outer lead portion, the circuit substrate being disposed on the support plate and selectively electrically, connected with inner ends of inner lead portions, a mold of resin material packaging the circuit substrate, support plate and inner lead portions, the ratio of the surface area of the base member to the principal surface area of the mold package being greater than 60%, and the support plate having an opening for exposing the bottom surface of the base member to the mold, the ratio of the exposed bottom surface area to the entire bottom surface area thereof being greater than 50%, and wherein the support plate comprises four stages arranged at respective corners of either an imaginary square shape or an imaginary rectangular shape, the stages being spaced apart and supporting the base member, and the bottom surface area of the base member being not larger than that of the imaginary square or rectangular shape. An embodiment of the present invention can provide a hybrid integrated circuit which is more resistant to the effects of repeated heat cycles of expansion and contraction. An embodiment of the present invention can provide a package structure of a hybrid integrated circuit, which affords excellent durability even when hybrid integrated circuit is constructed with a notably large scale of integration. An embodiment of the present invention can provide a hybrid integrated circuit which can be fabricated by methods similar to those conventionally used. An embodiment of the invention can provide a package structure of a hybrid integrated circuit such that reduced or minimum deformation of the mold package occurs between premolding and postmolding states. Embodiments of the present invention can provide hybrid integrated circuits which are more resistant to the effects of repeated cycles of thermal expansion and contraction. By applying the above structure of a hybrid integrated circuit, the molding material of epoxy resin contacts the bottom surface of the circuit substrate with a stronger adhesive force than in a case in which mold material contacts the support plate directly, as in the prior art mentioned above. Further, because the support plate area is reduced as compared with the case in which no opening is provided, stress due to thermal expansion of the support plate is also reduced and is further distributed over the entire surface thereof. These factors combine in effect to provide for the avoidance of or the reduction of rate of occurrence of package crack defects. In an embodiment of the present invention, in order to minimise or reduce change of characteristics of active or passive elements comprised in a hybrid or non-hybrid integrated circuit between premolding and postmolding states, the relationship between mold thickness above and below the circuit substrate may be selectively chosen, in dependence upon the relationship between expansion coefficients of the circuit substrate and the support plate. Normally, during a molding process for forming a package, a preassembled hybrid, for example, integrated circuit is heated up to about 175°C which causes a deformation thereof. The deformation remains after the molding process, which is the cause of the characteristic change. The deformation can be reduced or eliminated with a package structure in accordance with an embodiment of the present invention. According to an embodiment of the present invention it is provided that:- mold thickness above the base member is smaller than that below the base member when the thermal expansion coefficient of the circuit substrate is smaller than that of the support plate, or mold thickness above the base member is larger than that below the base member when the thermal expansion coefficient of the circuit substrate is larger than that of the support plate. Reference is made, by way of example, to the accompanying drawings, in which:- Fig. 1(a) is a schematic cross-sectional view of a conventional hybrid integrated circuit, and Fig. 1(b) is a plan view of a lead frame used in the device shown in Fig. 1(a), a support plate thereof having no opening, Fig. 2 is a schematic cross-sectional view of a hybrid integrated circuit for assistance in explaining the present invention, Fig. 3 is a plan view of a lead frame used in Fig. 2, the lead frame having an opening in a support plate, Fig. 4(a) is a graph illustrating relationship between percentage occupancy and tendency for crack occurrence, where percentage occupancy is given by a ratio of the surface area (S₀) of a circuit substrate to that (S₁) of a mold package, and Fig. 4(b) is a schematic top view of a device with a package, partly cut away, in which S₀ and S₁ are indicated, Fig. 5 is a graph of test result data for several embodiments of the present invention, illustrating relationship between crack occurrence percentage and number of heat cycles, for various surface area ratio percentages, Figs. 6(a) to 6(i) are respective top or plan views illustrating various configurations of support plate comprised in lead frames in embodiments of the present invention, the support plate having a variety of opening shapes therein, and Figs. 6(f′) to 6(i′) are respective cross-sectional views of lead frames, some including circuit substrates, of Figs. 6(f) to 6(i) respectively, Fig. 7 is a schematic cross-sectional view of a device in accordance with an embodiment of the present invention, with a mold package, when the lead frame of Fig. 6(f′) is used, Fig. 8 is a graph illustrating a relationship between a bending amount and width ratio between a connecting bar and a support plate stage when a lead frame as seen in Fig. 6(c) is utilised, Fig. 9 is a diagram illustrating a relationship between a bending amount and configuration or shape of connecting bar when lead frames of Figs. 6(c) and 6(f)/6(f′) types are utilised, Fig. 10 is a graph of test results illustrating relationships between crack occurrence percentage and number of heat cycles for various configurations of support plate, Figs. 11(a) and 11(b) are respective schematic cross-sectional views of hybrid devices in accordance with embodiments of the present invention molded in packages using lead frames of Figs. 6(f)/6(f′) and 6(h)/6(h′) types, Fig. 12 is a cross-sectional view of a clipping or pinching structure of support plate for embodiments of the present invention, where a circuit substrate is clipped or pinched by a pair of clippers or pincers, Fig. 13 is a schematic cross-sectional view of a device illustrating deformation caused by a difference in expansion characteristics between circuit substrate and support plate, Figs. 14(a) and 14(b) illustrate schematically two sequential steps in which the mold package is deformed when x₁ and x₂ are almost equal, Figs. 15(a) and 15(b) are a top view, partly cut away, and a cross-sectional view, of the device according to the present invention for explaining a device structure by which deformation of the mold package is eliminated or reduced, Figs. 16(a) and 16(b) are illustrations similar to those at Figs. 14(a) and 14(b) when a structure in accordance with the present invention is applied in order to eliminate deformation, and Figs. 17 and 18 are graphs, each illustrating a relationship between a resistance change, for upper and lower resistors respectively, and a thickness ratio x₁/x₂, which indicate an optimum value of x₁/x₂ for which deformation is eliminated or minimised, wherein upper and lower resistors are formed respectively on front (upper) and bottom (lower) surfaces of a circuit substrate, and x₁ and x₂ denote thicknesses of a mold package above and below the circuit substrate respectively. Throughout the drawings, the same reference signs designate the same or similar parts. A hybrid integrated circuit for assistance in explaining the present invention is shown in cross-section in Fig. 2, and Fig. 3 is a top view of a lead frame 9 used in Fig. 2. The lead frame 9 is made of any of copper alloy, iron nickel alloy, etc. A circuit substrate 2 comprises a base member 5 and chip parts (6, 7) mounted and fixed thereon. The base member 5 is of insulating material such as alumina ceramic, epoxy glass, glass coated metal, oxide covered silicon, sapphire, etc. The chip parts may include any active and/or passive elements, such as a semiconductor active element 6 forming an integrated circuit, a capacitor chip 7, etc. These chip parts are bonded on the base member 5 by conductive bonding resin and terminals thereof are selectively connected to bonding pads on the base member 5 and/or are mutually interconnected. The circuit substrate 2 is mounted on a support plate 8 and is fixed thereon by heat resistive adhesive. A plurality of leads 3 of the lead frame 9 are arranged on each side of the circuit substrate 2, and a lead 3 is composed of an inner lead 31 and outer lead 32. An inside end of an inner lead 31 is connected selectively to a bonding pad on the base member 5. The whole structure, except for substantial portions of the leads 3, is molded in a mold package 4 of epoxy resin, forming a completed hybrid integrated circuit 1. Chip parts 6, 7 are mentioned as illustrations of possible active and passive elements. However, such elements used in embodiments of the invention are not restricted to chip parts. For instance, they may be thick or thin film parts (not shown in Fig. 2), forming capacitors or resistors, which are directly formed on the base member 5 by screen printing or sputtering methods. The leads 3 and support plate 8 are integral parts of the lead frame 9, and the support plate 8 has an outline of a square shape having a square opening 80a therein. Therefore, the support plate 8 has four side strips forming a square outline, and is connected to the remainder of the lead frame by support bars 10. The opening 80a is formed with a predetermined size such that the remaining four side strips of the support plate 8 are of sufficient size to support the base member 5, it being preferable that the base member 5 does not extend beyond the outermost outline edges of the support plate. Dimensions of the base member 5 are indicated by broken lines 2 in Fig. 3. The support plate 8 is centrally located in the lead frame 9, and inside ends of inner leads 31 are disposed close to the support plate 8 for easy connection, by a wire bonding process, to bonding pads on the circuit substrate 2. An outside frame portion 11 and an interconnection bar 12 between leads 3 are removed after the molding process. The opening 80a functions to make or allow resin material flow freely to the bottom surface of the circuit substrate 2 (base member 5) and adhere thereto during a molding process of the mold package 4, utilising a transfer-mold method. Adhesive strengths against shearing force of bonds between epoxy resin of the mold package 4 and other parts such as base member 5 and support plate 8 comprised therein are shown in TABLE 1. The functions of the opening 80a formed in the support plate 8 will next be explained. When the device 1 is heated up, the mold package 4, circuit substrate 2, support plate 8, etc., suffer different amounts of expansion. The mold material of package 4 directly contacts the base member 5 through the opening 80a (of predetermined size) and therefore, in this case (as seen from TABLE 1) the adhesive strength of the adhesion of the mold package 4 to the base member 5 is much greater than the adhesive strength achieved in a case in which a support plate without an opening is used, as in previous proposals. The lower portion of the package 4 under the base member 5 is fixed more rigidly thereto, and cannot easily move apart from the bottom surface of the base member 5. Further, because the effective area of the support plate 8 is remarkably reduced, stress due to expansion of the support plate is also reduced and further distributed to the overall fringe portions thereof, resulting in avoidance of stress concentration at the outer fringe portion only. The above two factors contribute to eliminate or reduce the chances of the package 4 cracking. Crack occurrence probability increases significantly as package size becomes larger when a support plate without an opening is utilised. Fig. 4(a) is a graph illustrating data indicating the relationships between percentage occupancy X of the circuit substrate 2 and tendency to crack occurrence for different package sizes (for support plates without openings). Percentage occupancy is indicated along the abscissa and is defined by the ratio of surface area S₀ of the circuit substrate 2 (base member 5) to principal surface area S₁ of the mold package. Tendency to crack occurrence is indicated along the ordinate and is defined by the number of heat cycles needed until a 10% rate of occurrence of crack defects is observed among test pieces. The percentage occupancy X is, therefore, expressed by a ratio S₀/S₁, S₀ defining the surface area of circuit substrate 2 and S₁ defining the principal surface area of mold package as shown in Fig. 4(b). In order to perform the above tests, a large number of circuit substrates having a square shape and a thickness of 0.5 mm but having different percentage occupancies were prepared in each of five groups having respective different mold package sizes. Further, a large number of lead frames, having different sizes of support plate of a square shape without an opening, were prepared corresponding to each of the five package size groups. The percentage occupancy becomes 80% when the surface areas of the support plate and circuit substrate are equal. To fabricate the test pieces, each of the circuit substrates was mounted on the square support plate of a lead frame and fixed thereto by adhesive. Each test piece, having a 4 mm thickness of the mold package 4 and as shown in Fig. 4(b), is obtained after molding in epoxy resin by a transfer-mold method. Different package outline dimensions were fabricated by changing the dimensions of the molding die. In this way, test pieces in five different package size groups were provided, each group including different percentage occupancies. Test piece were subjected to a heat cycle test which included the steps of dipping in a solution at -55°C for five minutes and dipping in a solution at 125°C for five minutes. The number of heat cycles needed to reach a state in which 10% of test pieces manifested a package crack was measured for each package size and occupancy percentage. The results are shown in Fig. 4(a). In Fig. 4(a), X denotes the ratio of surface area S₀ of the circuit substrate to principal surface area S₁ of the package. It can be seen from the Figure that, when either the package size becomes larger or the percentage occupancy X becomes larger, the package is more liable to be cracked. Liability to cracking is more seriously pronounced as package size grows larger. When X is larger than 60%, a package of the smallest size, 10 x 10 mm², cannot withstand 1000 heat cycles, which is the criteria used for judging whether or not a package can be employed in practice. This is a serious problem for hybrid integrated circuits having circuit substrates of large size and a high occupancy percentage X. Generally, a semiconductor integrated circuit including a single semiconductor chip has at most a surface area of about 15 x 15 mm², and the occupancy percentage X (ratio of area of the semiconductor chip to the package outline) is less than 50%, mostly less than 30%. Under these conditions the semiconductor chip is completely covered by epoxy resin and buried in the package, and there is very little chance of a package crack occurring. Therefore, package cracking has almost been left out of consideration. When the occupancy percentage X is increased over 60%, the thickness of the package becomes comparatively small and the mold package becomes very susceptible to cracks. When the package size is further increased above 20 x 20 mm², resistance to cracking is further decreased, and finally it becomes almost impossible to obtain usable devices by using the square support plate without opening. A hybrid integrated circuit in accordance with an embodiment of the present invention enables the application of an occupancy percentage X of the circuit substrate in a range greater than 60% without significant package cracking, with the result that package size can be made smaller and integration density increased. According to the present invention, a support plate having an opening is utilised. For assistance in explanation, reference is made to Figs. 2 and 3 where opening 80a, allowing resin material to flow to the bottom surface of the circuit substrate 2 is formed in the support plate 8. Fig. 5 is a graph illustrating heat cycling test results when the tests were carried out on hybrid integrated circuits provided with openings 80a in their support plates. The circuits were subjected to alternate dipping steps into solutions at -55°C and 125°C for five minutes each. For the hybrid integrated circuits used for the tests, lead frames of copper alloy were employed, and the circuit substrates had a surface area of 28 x 28 mm² and the percentage occupancy X thereof to the mold package was about 67%. An area ratio Y in percent is defined by the following equation, Y = Opening area of support plate Bottom surface area of circuit substrate x 100(%). If the outside peripheral shape, in the case of Fig. 5 a square, of the support plate having the opening is not the same as that of the circuit substrate, the numerator of the above equation is preferably modified to a more precise expression such as "the exposed bottom area of the circuit substrate, directly contacting the mold package". When both outside dimensions of the support plate and substrate circuit are the same or become large, the two definitions are the same or indicate almost the same area. The test results are illustrated in Fig. 5 and the curves therein indicate the probability of a mold package being cracked versus the number of heat cycles applied thereto. As the area ratio Y becomes larger, the curve moves toward the right and lower region in Fig. 5, which means the crack occurrence probability decreases. Each curve pertaining to a specific value of Y was obtained using 50 test pieces. The test results make clear that crack occurrence can be controlled by providing the opening 80a in the support plate 8. Even when Y is made greater than 50%, the mold package can withstand over 1000 heat cycles, and there is therefore no problem in conventional practical use. Further, when area ratio Y is made larger than 80%, preferably 90%, hybrid integrated circuits can be obtained exhibiting virtually no package cracking problems. In Figs. 2 and 3, an opening of a square shape is formed in the support plate. However, the shape of the opening need not be restricted to a square shape. A rectangular shape may be used, for instance when the circuit substrate is rectangular. The shape may be changed depending on the design of the circuit substrate. Fig. 6(a) illustrates a first embodiment of the present invention. The Figure shows only a partial plan view of a lead frame omitting outer lead and frame portions thereof, because the omitted portions of the lead frame are substantially the same as those in Fig. 3. Four square stages 100 form the support plate, the stages being provided at respective corners of an assumed square shape having a side length 84. Each stage 100 is supported and connected to the remainder of the lead frame by a single support bar 10 extending in an outward diagonal direction. Chain lines 80e denote schematically the opening of the support plate 8, which is substantially the same as the exposed bottom surface area of the circuit substrate 2. Similar chain lines and similar reference numerals to 80e are used in following Figures. A stage 100 need not be restricted to square shape, but may be rectangular or circular in shape. Further, the number of stages may be increased depending on a size of the circuit substrate 2. Figs. 6(b) and 6(c) illustrate second and third embodiments of the present invention. In Fig. 6(b), pairs of stages 100 are connected by connecting bars 101, and in Fig. 6(c), all four stages are connected by four connecting bars 101. In both Figures, connecting bars 101 have a width W₁ less than that W₀ of a stage 100. In support plates with these structures effective stabilisation of stage positions one to the other, when the circuit substrate 2 becomes large, is afforded. Figs. 6(d) and 6(e) illustrate fourth and fifth embodiments of the present invention, which are further modifications of the embodiment of Fig. 6(a). In Fig. 6(d), each stage 100 is supported by two support bars 10′ and 10″. In Fig. 6(e), each stage 100 is supported by three support bars 10, 10′ and 10″. when the support bar structure for a stage is composed of a single support bar, such as is shown in Fig. 6(a), mechanical strength is sometimes insufficient. For example, when the circuit substrate 2 is bonded on stage 100, the stage is easily subjected to deformation or a position shift, resulting in inferior quality in wire-bonding and in other respects. On the other hand, the structures shown in Figs. 6(d) or 6(e) increase the support strength of stages 100 by increasing the number of support bars to two or three. TABLE 2 shows measured displacements of a stage 100 after bonding a circuit substrate 2 thereon, for two different support bar structures as shown in Figs. 6(a) and 6(d) respectively. The displacements were measured in each of X-, Y- and Z-directions. Test pieces for these measurements had structures such that stages 100 were located substantially on each corner of a square 24 x 24 mm², i.e. the side length 84 of Fig. 6(a) was about 24 mm, and a stage 100 formed a square of 3 x 3 mm². The width of support bars 10, 10′ and 10″ of Fig. 6(d) was about 0.65 mm, and the length of support bars 10 of Fig. 6(a) was about 12 mm and the length of support bars 10′, 10″ to a connecting bar 13 in Fig. 6(d) was about 8.5 mm. The base members forming the circuit substrates had a size of 23 x 23 mm² and were made of alumina ceramic having a 0.5 mm thickness, and bonded on the stages by heat resistive silicon resin. TABLE 2 shows average data for 50 test pieces for both types, measured by a dial gauge and a microscope. As seen in TABLE 2, the displacement decreases by a factor of about ten by changing the number of support bars from one to two. In Fig. 6(d), two support bars 10′ and 10″ are used for a stage, the directions thereof forming a right angle and being parallel to sides of the stage. By increasing the number of support bars to three as shown in Fig. 6(e), further improvement can be expected for molding a larger size of circuit substrate. In Fig. 6(e), two support bars 10′ and 10″ form a right angle, each direction being parallel to a side of a square shape, and the remaining support bar 10 is arranged in an outward diagonal direction. Figs. 6(f) and 6(f′) illustrate a sixth embodiment of the present invention, in which Fig. 6(f) shows a partial plan view of a lead frame and Fig. 6(f′) shows a cross-section along the line A-A′ in Fig. 6(f). The plan view is very similar to that of Fig. 6(c), but, as shown in Fig. 6(f′), a stage 100 is displaced to a lower position from an original frame level. On the other hand, the inside ends of inner leads 31 are bent upwardly to an upper position in order to bring bonding positions of inner leads and the circuit substrate to the same level even when a thick circuit substrate is utilised. In Fig. 6(f′), a connecting bar 101 has two further sloped portions and a horizontal portion, which contribute to relieve stress. Fig. 7 shows a schematic cross-section of a hybrid integrated circuit when a circuit substrate is mounted on this type of the lead frame (of Fig. 6(f)) having upwardly deformed inner leads and lowered stages and is molded in a package. Figs. 6(g) and 6(g′) illustrate a seventh embodiment of the present invention, in which Fig. 6(g) is a plan view of the support plate and Fig. 6(g′) is a cross-sectional view thereof. A connecting bar 101 has an undulation in the same plane as the stages 100. The undulation makes the support plate more flexible and has an effect of relieving stress between the circuit substrate 2 and the support plate. Figs. 6(h) and 6(h′) illustrate an eighth embodiment of the present invention which is a modification of that of Fig. 6(d). The top or plan view of Fig. 6(h) is quite similar to that of Fig. 6(d). However, as seen from Fig. 6(h′), which is a cross-sectional view taken along line A-A′ of Fig. 6(h), stages 100 are lowered and inner leads 31 are bent upwardly, with the result that the inside ends of the inner leads 31 are maintained at the same level as the surface of circuit substrate 2. Figs. 6(i) and 6(i′) illustrate a ninth embodiment of the present invention, which is a modification of the embodiments of Fig. 6(c) or Fig. 6(d). Stages 100 are mutually interconnected by connecting bars 101 and have each two support bars 10′ and 10″. Stages 100 are lowered and the inside ends of inner leads 31 are bent upwardly as shown in Fig. 6(i′) which is similar in this respect to Figs. 6(f′) and 6(h′). Fig. 8 is a graph illustrating a relationship between a bending amount t and a width ratio W₁, W₀ between a connecting bar and a stage. These notations (t, W₁, W₀) are indicated in the illustrations inserted in Fig. 8. The shape of lead frame used for obtaining test data for the graph was of the type disclosed by Fig. 6(c). The reference character L denotes the side dimension of a square outline of the support plate, which was chosen to be a length of 24 mm. The dimension W₀ was chosen to be 3 mm. The bending amount t was measured when the assembly of circuit substrate and lead frame was heated up to 175°C, which is a package molding temperature. Fig. 8 shows that the smaller the width of connecting bar is, the less the bending amount is. Fig. 9 is a diagram illustrating a relationship between a bending amount t and the shape of connecting bar. Similar tests were performed at 175°C using lead frames having support plate structures as shown in Fig. 6(c) and Figs. 6(f), 6(f′). The former group has a larger bending amount t than the latter group in which the support bar is (deliberately) bent and the stage is lowered. Fig. 10 is a graph illustrating probability of package cracking versus number of heat cycles. The tests for obtaining the graph data were performed using test pieces having an area ratio Y of about 60% and a side dimension L of 23 mm in Fig. 8. In Fig. 10, the curve indicated by an encircled 1 is a reproduction of the curve for Y = 0% in Fig. 5; the curve indicated by encircled 2 illustrates crack probability data for the support plate structure of Fig. 6(c) where W₁/W₀ is 0.2; the curve indicated by encircled 3 shows data for Fig. 6(b); the curve indicated by encircled 4 shows data for Fig. 6(f) where W₁/W₀ is given as 0.2; and the curve indicated by encircled 5 shows data for both the structure of Fig. 6(a) and the structure modified from Fig. 6(b) in which a connecting bar has an undulation. Fig. 10 shows that the crack occurrence probability (as against number of heat cycles) can be significantly reduced by providing the opening in the support plate, even when the hybrid integrated circuit has a high percentage occupancy (ratio of circuit substrate area to package size). When the continuing trend towards higher integration densities, integrated circuits, for example hybrid integrated circuits, are required in which semiconductor active elements (and passive elements such as capacitors and resistors) are mounted on both surfaces of a base member 5 forming a circuit substrate 2. Fig. 11(a) is a schematic cross-sectional view of an example of such a (hybrid) device. Chip capacitors 7 are mounted on both sides of the base member 5 and a semiconductor chip 6 and a resistor 7′ are mounted on the upper surface thereof. The assembled circuit substrate 5 is bonded on a stage 100 of a support plate and is molded in a package 4. The lead frame used is of a type similar to that shown in Figs. 6(f) and 6(f′), but the inner leads 31 are not bent upwardly. Fig. 11(b) is a cross-sectional view of an embodiment of the present invention, having elements mounted on both surfaces of a base member, in this case a hybrid device. A lead frame such as is illustrated in Fig. 6(h) is used in this embodiment. In the Figure, two semiconductor integrated circuit chips 6 are mounted on a front surface of the circuit substrate 2, and passive chip elements 7 such as resistor, capacitor, etc., are soldered on both surfaces of the circuit substrate 2. When both surfaces of the base member are utilised for chip (or other element), a lead frame having a support plate without an opening cannot be used. Thus, integrated circuits (e.g. hybrid circuits) according to embodiments of the present invention can have particular merits when both surfaces of a chip substrate are used for mounting chip parts or elements. In order to fix a circuit substrate 2 on to a stage 100 of a lead frame, a bonding method using adhesive is generally employed. However, another method can be used in which the circuit substrate 2 is clipped or pinched by or between a pair of clippers or pincer portions of the stage. Fig. 12 is a schematic cross-sectional view of a device in which tip portions of a stage 85 are separated into upper and lower portions 85a and 85b. Portions 85a and 85b clip or pinch a fringe or edge of a circuit substrate 2. As explained with reference to Figs. 8 and 9, an assembled lead frame and circuit substrate 2 warp downwardly when heated up to 170°C to 180°C during a molding process. The bending amount t is relieved by providing the opening in the support plate 8, but the bend or warp still remains after molding. This is illustrated in the cross-sectional view of Fig. 13, in which x₁ and x₂ denote thicknesses of upper and lower portions of a mold package 4 with regard to the base member 5, which forms the circuit substrate 2 with chip parts (not shown). In the Figures, x₂ represents a dimension (thickness) below the support plate 8, which is substantially equal to that below the base member 5. Generally, x₁ and x₂ are chosen to be almost equal, as shown in Fig. 13, and the packaged device shows, as a whole, a downward bend. States occurring during a transfer molding process are shown schematically and somewhat exaggeratedly in Figs. 14(a) and 14(b). In Fig. 14(a), the assembled parts are inserted in a molding cavity 20 and heated up to about 175°C, and the circuit substrate 2 and support plate 8 show a downward convex bend. After an injection of epoxy resin material, the mold package is cooled down to room temperature. In this process, the shrinkage forces in the upper and lower portions of the mold package with regard to the circuit substrate 2 are almost equal; therefore, the resin mold hardens without recovery from the bent shape. Another embodiment of the present invention utilises a package structure as illustrated in Figs. 15(a) and 15(b) to solve the above problem. Fig. 15(a) is a plan view of the embodiment, in which an upper portion of the mold material is partially removed, and Fig. 15(b) is a cross-sectional view thereof. The parts used therein are similar to those used in the previous embodiments. The device may be a hybrid or non-hybrid device, with elements mounted on one or both sides of a circuit substrate. In the illustrated embodiment, a circuit substrate 2 has a square size of 23 x 23 mm² and a 0.6 mm thickness. To detect device deformation, thick film resistors of 10 kilo-ohms were formed on both surfaces of a base member 5 by a printing method (instead of forming the circuit substrate 2 with chip parts). A film resistor is a sensitive passive element which can be used easily to detect deformation of the substrate on which the resistor is formed. Symbols x₁ and x₂ (see Fig. 16(b)) denote thickness of upper and lower portions of the mold package respectively. Several kinds of test pieces were fabricated to enable measurement of deformation, which depends on a relationship between x₁ and x₂, and the best conditions sought. The total thickness of x₁ and x₂ was changed over a range between 3 mm and 5 mm, and the ratio x₁/x₂ was changed over a range between 0.3 and 1.5. When the best condition is found, the device shapes in the molding process as shown in Figs. 16(a) and 16(b), which are illustrations of a kind similar to Figs. 14(a) and 14(b). When the assembled parts are heated up to about 175°C, a downward convex bend is seen in Fig. 16(a) as in Fig. 14(a). However, when the test piece has a ratio x₁/x₂ of the selectively predetermined value in fabrication, in this case x₁<x₂, the packaged device recovers its original flat surface after being cooled down as shown in Fig. 16(b). Test results for mold packages with film resistors are shown in the graphs of Figs. 17 and 18. The ordinates of the graphs in both Figures indicate resistance change in percent and the abscissae indicate the ratio x₁/x₂ of upper mold thickness to lower mold thickness. Fig. 17 shows data for resistors formed on the front surfaces of the base members 5 and Fig. 18 shows data for resistors formed on the bottom surfaces thereof. Generally, resistance value of a film resistor increases when the base member 5 on which the film resistor is formed is subjected to an upward convex deformation and, on the other hand, resistance value decreases when the substrate is subjected to an upward concave deformation. Test pieces were fabricated utilising alumina ceramic for the base member 5, having an expansion coefficient of about 7.2 x 10⁻⁶/°C, and copper alloy for the support plate, having an expansion coefficient of about 16.9 x 10⁻⁶/°C. The expansion of the former is much less than that of the latter, a little less than a half of the latter. As shown in Figs. 17 and 18, the resistance change is almost null (zero) when x₁/x₂ is about 0.7. If a resistance change within 0.2% is allowable, the thickness ratio x₁/x₂ is preferably selected to be in a range between 0.6 and 0.8. In the above example pieces, the expansion of the circuit substrate 2 (base member 5) is smaller than that of the support plate 8, and therefore the upper thickness x₁ of the mold package above the base member 5 is selected to be smaller than the lower thickness x₂ thereunder. On the other hand, when the expansion of the base member 5 is larger than that of the support plate 8, for example when an iron-nickel alloy such as the so-called "41 alloy" is used therefor, the circuit substrate and the support plate show upward convex deformation when heated up. Therefore, the upper thickness x₁ of the mold package above the circuit substrate is selected to be larger than the lower thickness x₂ under the circuit substrate. The test pieces had thick film resistors on the base member, being elements which are susceptible to deformation. Other elements such as capacitors and semiconductor chips are also apt to change characteristics due to deformation. Therefore, in embodiments of the present invention having a package structure in which the thickness ratio x₁/x₂ is selectively chosen has features of less dispersion in characteristics and a high quality. An integrated circuit, for example a hybrid integrated circuit, in accordance with an embodiment of the present invention includes a circuit substrate on which at least one of an active and passive elements are formed, a lead frame having a support plate which has an opening therein and supports the circuit substrate thereon, and a mold of resin for packaging the circuit substrate, support plate and inner leads of the lead frame. A bottom surface of the circuit substrate is exposed and made free to contact the mold resin through the opening. The support plate has four stages, at the corners of an imaginary square or rectangle shape, spaced apart and supporting the substrate. The bottom surface area of the circuit substrate is not larger than the imaginary square or rectangle shape. The hybrid integrated circuit has a ratio of exposed bottom surface to total bottom surface greater than 50%, and has a ratio of surface area of the circuit substrate to principal surface area of the mold greater than 60%. This structure relieves mechanical stress caused in the mold package and eliminates or reduces occurrences of crack defects in the mold. Further, an integrated circuit package structure for avoiding or reducing deformation thereof is provided in accordance with the invention in which mold thicknesses above and below the circuit substrate are selectively chosen. Further, an integrated circuit package structure is provided in accordance with the invention in which elements can be mounted on both main surfaces of a base member.

Claims: An integrated circuit, comprising:- a circuit substrate (2), comprising a base member (5) and at least one semiconductor element (6, 7, 7′), an active element or a passive element, disposed on the base member (5), a lead frame (9) comprising at least a plurality of leads (3) and a support plate (8), respectively provided at outward and inward portions of the lead frame (9), and each lead (3) having an inner lead portion (31) and an outer lead portion (32), the circuit substrate (2) being disposed on the support plate (8) and selectively electrically connected with inner ends of inner lead portions (31), a mold (4) of resin material packaging the circuit substrate (2), support plate (8) and inner lead portions (31), the ratio of the surface area of the base member (5) to the principal surface area of the mold package being greater than 60%, and the support plate (8) having an opening (80) for exposing the bottom surface of the base member (5) to the mold (4), the ratio of the exposed bottom surface area to the entire bottom surface area thereof being greater than 50%, and wherein the support plate (8) comprises four stages (100; 85) arranged at respective corners of either an imaginary square shape or an imaginary rectangular shape, the stages (100; 85) being spaced apart and supporting the base member (5), and the bottom surface area of the base member (5) being not larger than that of the imaginary square or rectangular shape. An integrated circuit as claimed in claim 1, wherein said ratio of the exposed bottom surface area to the entire bottom surface area is greater than 90%. An integrated circuit as claimed in claim 1 or 2, wherein the base member (5) is of insulating material. An integrated circuit as claimed in claim 3, wherein the insulating material is alumina ceramic, epoxy glass, glass coated metal, oxide covered silicon, or sapphire. An integrated circuit as claimed in claim 1, 2, 3 or 4, wherein the lead frame (9) is of copper alloy or iron nickel alloy. An integrated circuit as claimed in any preceding claim, wherein each stage (100; 85) is provided with a single support bar (10) connecting it to the remainder of the lead frame (9) and arranged in an outward diagonal direction. An integrated circuit as claimed in any preceding claim, wherein each stage (100; 85) is provided with two support bars (10′, 10″) connecting it to the remainder of the lead frame (9), the directions of the support bars forming a right angle, each direction being parallel to a side of the square or rectangular shape. An integrated circuit as claimed in any preceding claim, wherein each stage (100; 85) is provided with three support bars (10, 10′, 10″) connecting it to the remainder of the lead frame (9), the directions of two of those support bars forming a right angle, each direction being parallel to a side of the square or rectangular shape, and the remaining support bar being arranged in an outward diagonal direction. An integrated circuit as claimed in any preceding claim, wherein the four stages (100; 85) are formed in two pairs, each of two adjacent stages (100; 85), the two stages (100; 85) of each pair being mutually connected by a connecting bar (101) therebetween, the connecting bar (101) having a width less than a side dimension of a stage (100; 85). An integrated circuit as claimed in any of claims 1 to 8, wherein the support plate (8) further comprises four connecting bars (101), each connecting bar (101) connecting two adjacent stages (100; 85) with each other and having a width less than a side dimension of a stage (100; 85). An integrated circuit as claimed in claim 6, 7 or 8, or claim 9 or 10 when read as appended to claim 6, 7 or 8, wherein each support bar (10, 10′, 10″) is bent, resulting in a lowering of the level of the four stages (100; 85) from the principal level of the lead frame (9), whereby the level difference between the upper surface of the circuit substrate (2) and the inner lead portions (31) is reduced. An integrated circuit as claimed in claim 11, wherein inner lead portions (31) are further bent upwardly to raise the inside ends thereof higher than the principal level, whereby said level difference is further reduced. An integrated circuit as claimed in claim 11 or 12 when read as appended to claim 9 or 10, wherein the or each connecting bar (101) has two downwardly sloped portions and a horizontal portion therebetween. An integrated circuit as claimed in claim 11 or 12 when read as appended to claim 9 or 10, or as claimed in claim 13, wherein each connecting bar (101) lies in the same plane as the stages and has an undulation. An integrated circuit as claimed in any preceding claim, wherein each stage (85) is formed in a shape providing a pair of upper and lower clipper or pincer portions (85a, 85b), a fringe of the base member (5) being clipped or pinched therebetween. An integrated circuit as claimed in any preceding claim, having semiconductor elements (6, 7, 7′) on both upper and lower surfaces of the base member (5). An integrated circuit as claimed in any preceding claim, being a hybrid integrated circuit with at least one active (6) and one passive element (7, 7′). An integrated circuit as claimed in any preceding claim, wherein the mold (4) thickness above the base member (5) is smaller than that below the base member (5) when the thermal expansion coefficient of the circuit substrate (2) is smaller than that of the support plate (8), or mold (4) thickness above the base member (5) is larger than that below the base member (5) when the thermal expansion coefficient of the circuit substrate (2) is larger than that of the support plate (8). An integrated circuit as claimed in claim 18, wherein a mold (4) thickness above the base member (5) is smaller than that below the base member (5) when the base member (5) is of alumina ceramic and the support plate (8) is of copper alloy. An integrated circuit as claimed in claim 18, wherein a mold (4) thickness above the base member (5) is larger than that below the base member (5) when the base member (5) is of alumina ceramic and the support plate (8) is of a nickel-iron alloy. An integrated circuit as claimed in claim 20, wherein the nickel-iron alloy is 42 alloy. An integrated circuit as claimed in any preceding claim, being a hybrid integrated circuit.

Inventors: MATSUZAKI TOSHIO C O FUJITSU L, TOSHIMA HIROAKI C O FUJITSU LI, MATSUZAKI, TOSHIO C/O FUJITSU LIMITED, TOSHIMA, HIROAKI C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: H01L23
IPC codes: H05K3, H01L23