METHOD OF AND APPARATUS FOR TESTING MULTI-WIRE CABLE

Abstract: Disclosed herein is an automatic tester for multi-wire cable having a remote unit (6) to connect to one end of a cable to directly loop together wires to form paired forward and return wires (01-11, 02-12...09-19, 10-20) and a local unit connected to the other end of the cable, which unit sequentially transmits a test signal on each forward wire and has an open-circuit detector (TEST 1) connected to all the forward wires (01-10) and all the return wires (11-20) and arranged to output a signal when the test signal is detected on the forward wire but is not detected on the return wire of a given pair of wires, a short-circuit detector (TEST 2) connected to all the forward wires and all the return wires and arranged to output a signal when the test signal is detected on the forward wire and on any wire other than the return wire of a given pair of wires, control means (3) connected to the detectors and arranged to output a control signal to stop test signal sequencing when a signal is output by either detector means; and display means (DISP 1, DISP 2) separately connected to each wire to identify the or each faulty wire and indicator means (LED 1, LED 2, LED 3) respectively connected to the open-circuit detector, the short-circuit detector and the control means, to indicate the type of fault (a crossed wire showing as both an open-circuit and short-circuit fault).

Description: METHOD OF AND APPARATUS FOR TESTING MULTI-WIRE CABLE The present invention relates to a method of and apparatus for testing multi-wire cable; preferably, but not exclusively, IDC ten pair cable. There is a requirement to test multi-wire cable for open-, short- and crossed-circuits with apparatus having a remote unit to be connected to one end of the cable to be tested and active unit to be connected to the other end of the cable; all testing being controlled and operated from the active unit. Two such multi-wire cable testers are disclosed in United Kingdom Patent Specification No. 1298350 (Stanley) and United States Patent Specification No. 3986106 (Shuck). The active units described in these specifications may be regarded as generally comprising:- (a) generator means to generate a test signal; (b) switching means connected to the wiring to continuously, sequentially switch the test signal to each wire in turn; (c) detector means connected to detect the test signal; (d) display means provided to display which wires are being tested; (e) control means connected to the detector means and arranged to output a control signal to stop the switching means when the test signal is not detected by the detector means; and (f) indicator means connected to the output of the control - * means to indicate detection of a * wiring: fault, by ■ response to said control signal. The disadvantage of the above described :tesrters is. that; neither tester identifies each and every wire that may- be at. fault and indicates the type of fault; be it open-circuit, short-circuit or crossed wires. It is an object of the present invention to provide a multi-wire cable tester that overcomes the above-stated disadvantages. According to the present invention a method of automatically testing multi-wire cable comprises the steps of:- at one, remote, end of the cable, i) directly looping together wires to form paired forward and return wires; and, at the other, local, end of the cable, ii) sequentially transmitting a test signal on each forward wire; iii) continuously monitoring all the wires for the test signal; iv) identifying the forward wire on which the test signal is being transmitted; v) identifying the wire or wires, if any, on which the test signal is being received; vi) comparing the identification of steps iv) and v) to detect wiring faults; and, vii) stopping test signal sequencing upon detection of a fault, whereby the or each faulty wire and the type of wiring fault may be identified. In apparatus according to the present invention, . i) the passive unit includes means to directly loop together wires to form paired forward wires and return wires; and, ii) the local unit has:- (a) the switching means connected to all the forward wires; (b) the detector means connected to all the forward wires and to all the return wires; and, (c) the control means arranged to output said control signal when the test signal is not detected solely in the pair of forward and return wires under test, whereby scan testing of paired forward and return wires will be stopped at a particular pair of wires if a wiring fault is detected in either the forward or return wire of said pair, the or each faulty wire is identified and the type of fault indicated. In a preferred embodiment of the present invention, the detector means comprise open-circuit detector means, connected to all the forward wires and all the return wires and arranged to output a signal when the test signal is detected on the forward wire but is not detected on the return wire of a given pair of wires, and short-circuit detector means connected to all the forward wires and all the return wires and arranged to output a * signal, when the: test signal is detected on the forward wire:and on any -wire■• other than the return wire of a given pair of wires * ; the- control means are arranged to output said control"signal in. response to either or both the short-circuit or the- open- circuit output signal; and, further indicator means- are respectively connected to the open-circuit and the short- circuit detector means. Both open-circuit and short-circuit detector means may • comprise a series of paired NAND gates, the open-circuit . detector means having one input of one gate of each NAND pair connected to the forward wire of a respective wire pair, the other input of said one gate of each NAND pair and one input of the other gate of said NAND gate pair connected to the return wire of said wire pair and the output of said one gate of each NAND gate pair connected to the other input of said other gate of said NAND gate pair; the outputs of all said other gates of said NAND gate pairs being connected to said open-circuit indicator means and to the control means. The short-circuit detector means has one input of one gate of each NAND gate pair connected to the return wire of a respective wire pair, the other input of said one gate of each NAND gate pair and one input of the other gate of said NAND gate pair connected to the forward wire of said wire pair and the output of said one gate of each NAND gate pair connected to the other input of said other gate of said NAND gate pair; the outputs of all said other gates of said NAND gate pairs being connected to said short-circuit indicator means and to the control means. A crossed-wire is detected as a fault by both the open- circuit detector means and short-circuit detector means. The generator means may be an oscillator, said switching means a counter/divider and said control means an enable/disable circuit connected between the oscillator and the counter/divider and operatively connected to be controlled by all the open-circuit gate pairs and all the short-circuit gate pairs. The display means may comprise an individual display device separately connected to each wire; whereby the presence of the test signal on any wire may be displayed. The above and other features of the present invention are illustrated, by way of example, in the drawings wherein:- Fig. 1 is a circuit diagram of a circuit test control apparatus in accordance with the present invention; Fig. la is a circuit diagram, to a larger scale of part of the control device of Fig. 1; Fig. 2 is a circuit diagram of an open-circuit detector; Fig. 3 is a circuit diagram of a short-circuit detector; Fig. 4 is a schematic of the front panel of the control apparatus of Fig. 1; and, Fig. 5 is a circuit diagram of a remote or looping unit of the control apparatus. The cable tester shown in the drawings -and .described hereafter has been developed to test IDC ten pair cable*. Clearly, the same principle can be applied to testing cable having any number of wires. The apparatus consists of two basic units, one being a* control or scanner and the other being a remote or looping * unit. Only one unit is active, the control or scanner. As shown, the scanner comprises an oscillator or clock 1 using a pair of NAND gates on integrated circuit IC l (CMOS type 4011); with capacitors Cl and C2 and resistors Rl and R2 setting the clock rate. The clock output on line 2 passes to an enable/disable circuit 3, using a further gate circuit on IC 1, and thence to the input of a decade counter/divider 4 on integrated circuit IC 2 (CMOS type 4017), which presents a continuous signal pattern sequentially on outputs 0 to 9. The counter output is connected to the first ten wires, hereinafter designated forward wires 1 to 1, of the ten pair IDC cable (not shown) ; by an interface 5 (Fig. 4) in the form of a 25- way C type panel socket or plug. A 10-way LED bar display DISP 1 is also connected across the counter outputs -0 to - 9. * ' A remote unit 6 (Fig. 5), in the form of a 25-way, C- type free socket or plug, is connected to the other end of the cable under test and loops wire 01 to wire 11, 02 to 12, 9 to 19 and wire 10 to wire 20. Test connections for the thus-formed loops of forward and return wires are completed at the control section of the apparatus through interface 5. A further 10-way LED bar display DISP 2 is connected across the return wires 11 to 2. One section of an open-circuit detector, TEST 1, is shown by Fig. 2 to consist of a pair of NAND gates Gl and G2. There is one section for each pair of wires and sections are grouped in twos on IC's 3 to 7 and are shown to have inputs of each unit connected via matrix networks to a respective pair of the looped forward and return wires 01 - 11 10 - 20. In each section, the transmitted signal feeds to one input of NAND gate Gl and the received signal feeds to the other input of NAND gate Gl and to one input of NAND gate G2; the output of NAND gate Gl feeding to the other input of NAND gate G2. The output of NAND gate G2, i.e. the output from TEST 1, and of all the other TEST 1 sections are co moned via diodes and feed to a red 'open' circuit indicator light LED 2 and to the ' enable/disable circuit 3. One section of a short-circuit detector TEST 2 is shown by Fig. 3 to consist of a pair of NAND gates G3 and G4. There is one section for each pair of wires and sections are grouped in twos on IC's 8 to 12 and are shown to have the inputs of each unit connected via matrix networks to a respective pair of the looped forward and return wires. In each section, the transmitted signal feeds to one input of NAND gate G3 and to one input of NAND gate G4 and the received signal feeds to the .-other input * of .NAND7 gate - G3; the output of NAND gate G3 feeding to the other-" input of NAND gate G4. The output of NAND gate G4, .i.e. the output from TEST 2 and of all the other TEST 2 sections are commoned via diodes and feed to a red short-circuit indicator light LED 1 and to the enable/disable circuit , 3. There is an additional indicator LED-3 (green/flashing red) , LED-3 is green when no fault is detected on the testing cable and it trips to flashing red when a fault is detected. The green part of LED-3 is connected to the outputs of Test-1 and Test-2 circuits via transistor TR1. When the outputs of Test-1 and Test-2 are Logic 1, LED-3 indicates green:ok. The flashing red part of LED-3 is also connected to the outputs of Test-1 and Test-2 but via a NAND gate in enable/disable circuit 3, so when the outputs of Test-1 and Test-2 go Logic 0, the output of the NAND gate trips to Logic l, so LED-3 will show flashing red, indicating a fault. See Fig. la. The apparatus is capable of carrying out tests for short-circuit, open-circuit and crossed wires. TEST 1 - Open-circuit If a wire is broken anywhere within the tested 10 pairs, the transmitted signal will be displayed on DISP l but there will be no received signal on the corresponding wire. The circuit shown on Fig. 2 will detect this status. This circuit consists of two NAND gates interconnected in sucn a manner that, if the transmitted signal is present but there is no received signal, the output of the circuit will be logic O. Ten of these circuits will test 10 pairs in the IDC block wiring. If an open-circuit is detected, the logic 0 output from TEST 1 will trip enable/disable circuit 3 and the scanning will stop. DISP 1 will indicate on which wire the control section is transmitting the signal, DISP 2 will show nothing, because of the absence of the received signal, and LED 1 (Figs, la and 4) will light, showing that there is an open-circuit. LED-3 will show flashing red, indicating a fault. The fault is now located and can be rectified. TEST 2 - Short-circuit If there is a short-circuit with the 10 pairs tested, the transmitted and received signals will be displayed on DISP 1 and DISP 2, but in addition to these signals there will be another signal, not generated by the control section. This signal will also be displayed on one or more of the LED bars, either DISP.1 or DISP 2; depending on where the short-circuit is. The circuit shown in Fig. 3 will detect this condition. If there is no transmitted signal on the input of this circuit, but it can detect a received signal, the output will change to logic 0. Ten of these circuits will test 10 pairs in the IDC block wiring. If a short-circuit is detected, the logic 0 signal output from TEST 2 will trip enable/disable circuit 3 and the scanning will stop; LED 2 will light, showing ■ the condition of short circuit. LED-3 will show flashing.-red, indicating a fault. TEST 3 - Crossed pair In the case of a crossed pair, the transmitted and received signals will be displayed, but the received signal will not be on the correct wire. TEST 1 and TEST 2 circuits will simultaneously detect this condition and output logic 0 signals, trip enable/disable circuit 3 and stop the scanning. LED 1 and LED 2 will light simultaneously indicating a crossed pair. LED-3 will show flashing red, indicating a fault. If there are no faults on the tested 10 pairs, the scanning will be continuous, logic 1 signals from TEST l and TEST 2 will be applied to the base of a transistor switch TRl and a green 'OK' lamp LED 3 will light, to show that the block is fault-free. CMOS components are used in the scanner to enable it to be battery-powered.

Claims: CLAIMS : - 1. A method of automatically testing multi-wire cable comprising the steps of:- at one, remote, end of the cable, i) directly looping together wires to form paired forward and return wires; and, at the other, local, end of the cable, ii) sequentially transmitting a test signal on each forward wire; iii) continuously monitoring all the wires for the test signal; iv) identifying the forward wire on which the test signal is being transmitted; v) identifying the wire or wires, if any, on which the test signal is being received; vi) comparing the identification of steps iv) and v) to detect wiring faults; and, vii) stopping test signal sequencing upon detection of a fault, whereby the or each faulty wire and the type of wiring fault may be identified. 2. Apparatus for automatically testing multi-wire cable comprising:- i) a passive, remote, unit (6) to be connected to one end of the cable; and, ii) an active, local, unit to be connected to the other end of the cable and including:- (a) generator means (1, 2) to generate a test signal; (b) switching means (4) connected to the wires (01-20) to continuously, sequentially switch the test signal to each wire in turn; (c) detector means (TEST 1, TEST 2) connected to detect the test signal; (d) display means (DISP 1, DISP 2) provided to display which wires are being tested; (e) control means (3) connected to the detector means and arranged to output a control signal to stop the switching means when the test signal is not detected by the detector means; and, (f) indicator means (LED 3) connected to the output of the control means to indicate detection of a wiring fault by response to said control signal CHARACTERISED IN THAT:- i) the passive unit (6) includes means to directly loop together wires to form paired forward wires and return wires (01-11,02-12...09-19,10-20); and, ii) the local unit has:- (a) the switching means (4) connected to all the forward wires (01-10); (b) the detector means (TEST 1, TEST 2) connected to all the forward wires (01-10) and all the return wires (11- 20) ; and, (c) the control means (3) arranged to output said control signal when the test signal is not detected solely in the pair of forward and return wires under test, whereby scan testing of paired forward and return wires will be stopped at a particular pair of wires if a wiring fault is detected in either the forward or return wire of said pair, the or each faulty wire is identified and the type of fault indicated. 3. Apparatus as claimed in claim 2 AND FURTHER CHARACTERISED IN THAT the detector means comprise open- circuit detector means (TEST 1), connected to all the forward wires (01-10) and all the return wires (11-20) and arranged to output a signal when the test signal is detected on the forward wire but is not detected on the return wire of a given pair of wires (01-11,02-12...09-19,10-20) , and short-circuit detector means (TEST 2), connected to all the forward wires and all the return wires and arranged to output a signal when the test signal is detected on the forward wire and on any wire other than the return wire of a given pair of wires; the control means (3) are arranged to output said control signal in response to either or both the short-circuit or the open-circuit output signal; and, further indicator means (LED 1, LED 2) are respectively connected to the open-circuit and the short-circuit detector means. 4. Apparatus as claimed, in claim 3. AND. FURTHER CHARACTERISED IN THAT the open-circuit detector means (TEST 1) comprise a series of paired NAND gates (Gl, G2), one input of one gate (Gl) of each NAND gate pair being- connected to the forward wire of a respective wire pair (01- 11,01-12...09-19,10-20) , the other input of said one gate of each NAND gate pair and one input of the other gate (G2) of said NAND gate pair being connected to the return wire of said wire pair and the output of said one gate of each NAND gate pair being connected to the other input of said other gate of said NAND gate pair; the outputs of all of said other gates of said NAND gate pairs being connected to said open-circuit indicator means (LED 1) and to the control means (3) . 5. Apparatus as claimed in claim 3 AND FURTHER CHARACTERISED IN THAT the short-circuit detector means (TEST 2) comprise a series of paired NAND gates (G3, G4), one input of one gate (G3) of each NAND gate pair being connected to the return wire of a respective wire pair (01- 11,01-12...09-19,10-20) , the other input of said one gate of each NAND gate pair and one input of the other gate (G4) of said NAND gate pair being connected to the forward wire of said wire pair and the output of said one gate of each NAND gate pair being connected to the other input of said other gate of said NAND gate pair; the outputs of all of said other gates of said NAND gate pairs being connected to said short-circuit indicator means (LED 2) and to the control means 3. 6. Apparatus as claimed in claim 4 and claim 5 AND FURTHER CHARACTERISED IN THAT said generator means is an oscillator (1), said switching means is a counter/divider (4) and said control means is an enable/disable circuit (3) connected between the oscillator and the counter/divider and operatively connected to be controlled by all the open- circuit NAND gate pairs (Gl, G2) and all the short-circuit NAND gate pairs (G3, G4) . 7. Apparatus as claimed in any of claims 2 to 6 AND FURTHER CHARACTERISED IN THAT said display means (DISP 1, DISP 2) comprise an individual display device separately connected to each wire (01 ,02...19,20) ; whereby the presence of the test signal on any wire may be displayed.

Inventors: TODOR LOUIS, TODOR, LOUIS
Applicants: NETWORK SYSTEMS BUILDERS LIMIT, NETWORK SYSTEMS BUILDERS LIMITED
Application year: 1989
Main classification: G01R31
IPC codes: G01R31