Semiconductor memory device which can suppress operation error due to power supply noise

Abstract: A row address signal (Ai) is supplied to a row address input buffer (13), and a column address signal (Aj) is supplied to a column address input buffer (14). The row address signal (Ai) supplied to the row address input buffer (13) is then supplied to a row main decoder (19), through a row address predecoder (15), the column address signal (Aj) supplied to the column address input buffer (14) being supplied to a column address predecoder (17). An output from the column address predecoder (17) is supplied to a filter or delay circuit (20), and an output signal from the filter or delay circuit (20) is supplied to a column main decoder (21). One memory cell (MC) in a memory cell array is selected in response to decode outputs from the row main decoder (19) and the column main decoder (21), and readout data of the selected memory cell (MC) is amplified by a sense amplifier (24). An output from the sense amplifier (24) is output through a data output circuit (25) and a data output buffer (26). An erroneous detected signal of the column address buffer (14), arising from power supply noise generated when an output from the data output buffer (26) is inverted, is eliminated or reduced by the filter or delay circuit (20).

Description: The present invention relates to a semiconductor memory device which can suppress an operation error arising from power supply noise and, more particularly, to a semiconductor memory device which incorporates an address transition detector (ATD) and hence realizes a high-speed operation. An ATD is incorporated in a memory device in order to realize high-speed reading of memory data of a semiconductor memory device. The ATD detects a change in address signal and generates a clock pulse. The clock pulse generated from the ATD is used for equalizing control of bit and sense amplifier lines, and the like, so that a high-speed reading operation can be realized. More specifically, before an address is selected in accordance with the change in address signal, the potentials of a pair of bit lines and a pair of sense amplifier lines arranged at an output terminal of a sense amplifier are equalized on the basis of the control, in response to a clock pulse generated from the ATD. Therefore, the influence of a data output during a prior cycle is erased in a short period of time. The ATD is described in, for example, 1987 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 264, 265 and 420 "A 25ns 1Mb CMOS SRAM" T.Ohtani et. al., 1985 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 64, 65 and 306 "A 17ns 64K CMOS RAM with a Schmitt Trigger Sense Amplifier" Kiyofumi Ochii et. al., 1984 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 216, 217 and 341 "A 30ns 64K CMOS RAM" Kim Hardee et. al., and the like. In a memory device having a memory designed for high-speed operation, in particular, a memory device having a large number of data bits, i.e., one having an output configuration of 8-bits or more, power supply noise is generated due to a large peak current when a data output buffer is driven, and internal circuits are erroneously operated. The operation error is exemplified by a detection error of an input signal level caused by power supply noise. When a power supply potential is varied due to a large driving current during an operation of the output buffer, the detection error is caused. The change in power supply potential is conducted to an address input buffer by distributed parasitic inductance and distributed parasitic resistance in a power supply line. Therefore, the detection level of the address input buffer is changed, and hence an erroneous address input signal is supplied to a decoder. For this reason, the memory cell at an erroneous address is selected, and memory data of the memory cell is output. If the power supply noise is significantly increased and the above phenomena are repeated, a chip mounting the memory devices is often set in the oscillation state. Prior art document GB-A-2 078 405 which forms the basis of the preamble of claim 1 discloses a semiconductor memory device which includes first and second decoder circuits. The first decoder circuit receives partial address signals from address signals of a plurality of bits supplied from an address buffer circuit and provides decoded signals of the partial address signals as intermediate signals. The second decoder circuit receives the intermediate signals in order to provide signals for selecting from among a plurality of memory circuits contained within memory cell arrays a memory circuit determined by the address signals of the plurality of bits. The semiconductor memory circuit device is designed to operate at high speed as a result of the particular arrangements of the first and second decoder circuits. A semiconductor substrate on which the semiconductor memory circuit device is formed can be made comparatively small in view of the arrangements of the first and second decoder circuits. Further, prior art document EP-A-0 167 275 describes a semiconductor memory device which includes an address change detection circuit and a pulse width control circuit. The pulse width control circuit inhibits the passage of write enable signals having a short pulse width for a predetermined time period after a change of address has occurred. After the predetermined period has elapsed the operation of the pulse width control circuit is overridden and thus the write cycle time is reduced. It is an object of the present invention to provide a semiconductor memory device which can suppress an operation error arising from power supply noise, without an increase in the read access time. To solve this object the present invention provides a semiconductor memory device as specified in claim 1. With this arrangement, even if the second address input circuit erroneously detects an address signal due to power supply noise, an operation error by the second decoder is controlled, since noise components included in a column address signal output from the address input circuit. Since the operation speed required for determination of the column address is lower than that for the row address, therefore when the time, by which the column address signal has been delayed by the filter or delay circuit, is set within a time period until the row address is determined, after the column address has been determined, the operation speed is unaffected. As a result, there is herewith provided a semiconductor memory device which can suppress an operation error arising from power supply noise, without an increase in the read access time. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram showing an arrangement of a semiconductor memory device according to a first embodiment of the present invention; Fig. 2 is a timing chart showing signal waveforms of parts included in the circuit shown in Fig. 1; Fig. 3 is a circuit diagram showing an arrangement of a filter included in the circuit shown in Fig. 1; Fig. 4 is a timing chart showing signal waveforms of parts included in the filter shown in Fig. 3; Fig. 5 is a circuit diagram showing another arrangement of the filter included in the circuit shown in Fig. 1; Fig. 6 is a timing chart showing signal waveforms of parts included in the filter shown in Fig. 5; Fig. 7 is a circuit diagram showing an arrangement of a delay circuit included in the circuit shown in Fig. 1; Fig. 8 is a timing chart showing signal waveforms of parts included in the delay circuit shown in Fig. 7; Fig. 9 is a circuit diagram showing another arrangement of the delay circuit included in the circuit shown in Fig. 1; Fig. 10 is a timing chart showing signal waveforms of parts included in the delay circuit shown in Fig. 9; and Fig. 11 is a block diagram showing an arrangement of a semiconductor memory device according to a second embodiment of the present invention. Fig. 1 shows a semiconductor memory device according to a first embodiment of the present invention. Row address signal Ai is supplied to address input terminal 11, and column address signal Aj is supplied to address input terminal 12. The input terminals of address input buffers 13 and 14 are connected to address input terminals 11 and 12, respectively. The input terminals of address predecoder 15 and address transition detector (ATD) 16 are connected to the output terminal of address input buffer 13, and the input terminals of address predecoder 17 and ATD 18 are connected to the output terminal of address input buffer 14. The input terminal of row main decoder 19 is connected to the output terminal of address predecoder 15, the input terminal of filter or delay circuit 20 is connected to the output terminal of address predecoder 17, and the input terminal of column main decoder 21 is connected to the output terminal of filter or delay circuit 20. The delay time of a column address signal delayed by filter or delay circuit 20 is set within a delay time from the input of a row address signal to the determination of a row address of memory cell MC in response to an output of row main decoder 19. The input terminals of clock generator 22 are connected to the output terminals of ATDs 16 and 18, and one end of each word line WL is connected to a corresponding output terminal of row main decoder 19. Each gate of a pair of column selection MOS transistors CSa and CSb is connected to a corresponding decode signal CD output terminal of column main decoder 21. One end of each of the current paths of each pair of column selection MOS transistors CSa and CSb are connected to sense amplifier 24, and the other ends thereof are respectively connected to one ends of the corresponding pair of bit lines BL and BL . Word lines WL and bit lines BL and BL intersect with each other and memory cells MC are arranged at each intersection position in a matrix form. Bit line loads LDa and LDb are connected between the other ends of corresponding bit lines BL and BL and power supply V DD , respectively. Bit line equalizers 23 are arranged between bit lines BL and BL and bit line loads LDa and LDb, respectively, each bit line equalizer 23 consisting of, for example, a MOS transistor in which a current path is connected between bit lines BL and BL . The output terminal of clock generator 22 is connected to the gates of the MOS transistors, the input terminals of data output circuit 25 are connected to the output terminals of sense amplifier 24, the input terminals of data output buffer 26 are connected to the output terminals of data output circuit 25, and output terminal 27 is connected to the output terminal of data output buffer 26. A normal reading operation performed by the device having the above arrangement will now be described. Row and column address signals Ai and Aj are supplied to address input buffers 13 and 14 through address input terminals 11 and 12. When row and column address signals Ai and Aj are supplied to address input buffers 13 and 14, the change in address signals is detected by ATDs 16 and 18, as a result of which, clock pulse  EQ for equalizing each pair of bit lines BL and BL is output from clock generator 22. Since bit line equalizer 23 is rendered active only during a predetermined period of time in which clock pulse  EQ is at level "H", therefore short-circuiting occurs between bit lines BL and BL , and the output level of the prior cycle is equalized, causing the potentials of bit lines BL and BL to become equal. When clock pulse  EQ goes to level "L", bit line equalizer 23 is disabled and the pair of bit lines BL and BL is precharged by bit line loads LDa and LDb. Row address signal Ai, supplied to address input buffer 13, is subsequently supplied to row main decoder 19 through address predecoder 15, in parallel with the above equalizing operation, while column address signal Aj, supplied to address input buffer 14, is subsequently supplied to column main decoder 21 through address predecoder 17 and filter or delay circuit 20. When member 20 denotes a filter (member 20 can be either a filter or a delay circuit), signal noise arising from the detection error of column address signal Aj, caused by power supply noise included in column address signal Aj output from address predecoder 17 (caused during the prior reading cycle), is absorbed or reduced. On the other hand, when member 20 is constituted by a delay circuit, the leading or trailing edge of the signal noise is delayed, so that the signal level is gradually changed. In this way, an erroneously detected signal arising from power supply noise is not supplied to column main decoder 21. In a standard semiconductor memory device, the operation speed of column selection is higher than that of row selection, and this also applies to the memory device shown in Fig. 1. Therefore, by arranging filter or delay circuit 20, if column address signal Aj is delayed until a row address is determined, the access time is not delayed. Then, the row of memory cells connected to one word line WL selected by row main decoder 19 is selected, in addition to the pair of bit lines BL and BL in one column selected by column decode signal CD output from column main decoder 21. At this time, bit line equalizer 23 is already disabled. Therefore, one memory cell MC positioned at the intersecting point between selected row word line WL and bit lines BL and BL is selected. The memory data of selected memory cell MC is supplied to sense amplifier 24 and then amplified. An output from sense amplifier 24 is supplied to data output buffer 26 through data output circuit 25, and is output from output terminal 27 as output data Vout. An operation when power supply noise is generated will be described in detail hereinafter, with reference to the timing chart shown in Fig. 2. Fig. 2 shows the case wherein row address signal Ai changes from level "L" (V IL ) to level "H" (V IH ), and column address signal Aj is kept at level "H". Assume that an output during the prior cycle of data output buffer 26 is inverted (from level "H" to level "L") when the address is changed. At this time, the potential of power supply V SS is increased due to power supply noise. Therefore, when address input buffer 14 is erroneously operated, column address signal Ajb to be at level "H" output from buffer 14 is set at level "L" for a short period of time. However, since output Ajp from address predecoder 17 becomes signal Ajf in which noise is eliminated or the trailing edge is delayed, the influence of the power supply noise is not conducted to column main decoder 21. Note that address input buffer 13 is affected by the power supply noise in the same manner as in address input buffer 14. However, since an operation speed of row address selection is lower than that of column address selection, an operation error when the row is selected by row main decoder 19 is negligible. When row and column address signals Ai and Aj are respectively supplied to address input buffers 13 and 14, the changes in address signals are detected by ATDs 16 and 18. The detection signals are supplied to clock generator 22, and clock pulse  EQ for equalizing each pair of bit lines BL and BL is output from clock generator 22 for a predetermined period. Therefore, bit line equalizer 23 is enabled and bit lines BL and BL are short-circuited, thus equalizing the level of the prior cycle. Thereafter, one memory cell MC is selected in response to outputs from row and column main decoders 19 and 21. Memory data of selected memory cell MC is output through sense amplifier 24, data output circuit 25, data output buffer 26, and output terminal 27. When this data is output, the level of power supply V SS is increased by a driving current flowing in data output buffer 26. Therefore, address input buffers 13 and 14 may be affected by power supply noise. However, since the above-mentioned operation are repeated, the operation error due to the power supply noise is suppressed. With the above arrangement, an output error when address input buffer 14 is erroneously operated by filter or delay circuit 20 can be eliminated or reduced. In addition, since a signal delay time of filter or delay circuit 20 is set shorter than a time period required until a row address is determined after row address signal Ai is changed, access time is not reduced. Therefore, a detection error of the level of column address signal Aj due to a large peak current generated when data output buffer 26 is driven can be reduced without loss of read access time. Fig. 3 shows an arrangement of filter 20 in the circuit shown in Fig. 1. This filter 20 consists of three inverters 28 to 30 and one NAND gate 31. Output signal Ajp from address predecoder 17 is supplied to one input terminal of NAND gate 31 and the input terminal of inverter 28. An output from inverter 28 is supplied to inverter 29. Output Ajd from inverter 29 is supplied to the other input terminal of NAND gate 31. An output from NAND gate 31 is supplied to inverter 30. Output Ajf from inverter 30 is supplied to column main decoder 21 as an output from filter 20. Fig. 4 is a waveform chart of the signals of filter 20 shown in Fig. 3. When output signal Ajp from address predecoder 17 goes to level "H" (time t1), output Ajd from inverter 29 is set at level "H" after delay time ΔT by inverters 28 and 29.has elapsed (time t2). Therefore, an output from NAND gate 31 is set at level "L", and output Ajf from inverter 30 is set at "H". At this time, column main decoder 21 performs a selecting operation. Therefore, even if power supply noise is superposed on column address signal Aj during period ΔT between times t1 and t2, this noise is not conducted to column main decoder 21. Therefore, the influence of the power supply noise is eliminated. When output Ajp from address predecoder 17 is set at level "L" (non-selection state) (time t3), signal Ajf is also set at level "L". Note that although two inverters 28 and 29 are arranged at the other input terminal of NAND gate 31 in the circuit shown in Fig. 3, four or more even-numbered inverters may be arranged so as to obtain a required delay time. Fig. 5 shows another arrangement of filter 20. This filter 20 consists of three inverters 32 to 34 and one NOR gate 35. Output signal Ajp from address predecoder 17 is supplied to the input terminal of inverter 32. An output from inverter 32 is supplied to one input terminal of NOR gate 35 and the input terminal of inverter 33. Output from inverter 33 is supplied to inverter 34. Output Ajd from inverter 34 is supplied to the other input terminal of NOR gate 35. Output Ajf from NOR gate 35 is supplied to column main decoder 21 as an output from filter 20. Fig. 6 is a waveform chart of the signals of filter 20 shown in Fig. 5. When output signal Ajp from address predecoder 17 is set at level "H" (time t1), this signal is inverted by inverter 32, and supplied to NOR gate 35 and inverter 33. When delay time ΔT by inverters 32 to 34 has elapsed after signal Ajp is inverted (time t2), an output from NOR gate 35 is set at level "H". At this time, column main decoder 21 is in a selection state. Therefore, even if power supply noise is superposed on column address signal Aj during period ΔT between times t1 and t2, this noise is not conducted to column main decoder 21. Therefore, the influence of the power supply noise is eliminated. When output Ajp from address predecoder 17 is set at level "L" (non-selection state) (time t3), signal Ajf is also set at level "L". Note that although two inverters 33 and 34 are arranged at the other input terminal of NOR gate 35 in the circuit shown in Fig. 5, four or more even-numbered inverters may be arranged so as to obtain a required delay time, as in the circuit shown in Fig. 3. Fig. 7 shows an arrangement of delay circuit 20 in the circuit shown in Fig. 1. This delay circuit 20 consists of two cascade-connected CMOS inverters 36 and 37. Output signal Ajp from address predecoder 17 is supplied to CMOS inverter 36. Output signal Ajin from inverter 36 is supplied to the input terminal of CMOS inverter 37, and output signal Ajf from inverter 37 is supplied to column main decoder 21. The W/L of p-channel type load MOS transistor 38 constituting CMOS inverter 36 is set larger than that of n-channel type driving MOS transistor 39. Therefore, inverter 36 has characteristics wherein its output signal level rises quickly and falls slowly. On the other hand, the W/L of n-channel type driving MOS transistor 40 constituting CMOS inverter 37 is set larger than that of p-channel type load MOS transistor 41. Therefore, inverter 37 has characteristics wherein its output signal level falls quickly and rises slowly. Fig. 8 is a waveform chart of the signals in delay circuit 20 shown in Fig. 7. When an output signal from address predecoder 17 is set at level "H" (time t1), and delay time ΔT1 by inverter 36 has elapsed (time t2), an output from inverter 36 is slowly set at level "L". Then, at time t3 after delay time ΔT2 by inverter 37 has elapsed, an output from inverter 37 is slowly set at level "H". At this time t3, column main decoder 21 is in a selection state. Therefore, even if power supply noise is superposed on column address signal Aj, since the signal level can be controlled by delay circuit 20 so as to slowly change, almost no influence of the power supply noise is conducted to column main decoder 21. When output Ajp from address predecoder 17 is set at level "L" (non-selection state) (time t4), signals Ajin and Ajf are set at level "L" at relatively high speed. Fig. 9 shows another arrangement of delay circuit 20 in the circuit shown in Fig. 1. This delay circuit 20 consists of two CMOS inverters 42 and 43, and two resistors 44 and 45 respectively arranged at output nodes of the inverters. Output signal Ajp from address predecoder 17 is supplied to CMOS inverter 42. The fall rate of the output level of inverter 42 is reduced by resistor 44. Therefore, inverter 42 has characteristics wherein its output level rises quickly and falls slowly. Output Ajin from inverter 42 is supplied to inverter 43. The rise rate of the output level of inverter 43 is reduced by resistor 45. Therefore, inverter 43 has characteristics wherein its output signal level falls quickly and rises slowly. Output signal Ajf from inverter 45 is supplied to column main decoder 17. Fig. 10 is a waveform chart of the signals in delay circuit 20 shown in Fig. 9. As shown in Fig. 10, in the delay circuit having the arrangement shown in Fig. 9, the same delay operation as in the circuit shown in Fig. 7 is performed. Therefore, with this arrangement, the influence of power supply noise is not conducted to column main decoder 21. Note that delay circuits 20 shown in Figs. 7 and 9 consist of two inverters, respectively. However, four or more even-numbered cascade-connected inverters may constitute the delay circuit depending upon the required delay time or reduction characteristics of noise. Fig. 11 shows a semiconductor memory device according to a second embodiment of the present invention. The same reference numerals in Fig. 11 denote the same parts as in the circuit shown in Fig. 1, and the description thereof is omitted. More specifically, in Fig. 11, equalizer 46 is arranged on output lines of sense amplifier 24 in the circuit shown in Fig. 1. Equalizer 46 is controlled in response to equalizing signal  EQ2 output from clock generator 22. Equalizer 46 equalizes pair of output lines SOa and SOb of sense amplifier 24. Equalizing signal  EQ2 serves as a pulse-type signal having a change timing delayed with respect to equalizing signal  EQ1 . Equalizing signal  EQ1 is generated by delaying, e.g., signal  EQ2 . With the above arrangement, the same operation is basically performed and the same effect can be obtained as in the circuit shown in Fig. 1. As has been described above, according to the present invention, there is provided a semiconductor memory device which can suppress an operation error due to power supply noise without loss of read access time.

Claims: A semiconductor memory device comprising a memory cell array in which memory cells (MC) are arranged in a matrix form, first address input means (11 and 13) for receiving a row address signal (Ai), second address input means (12 and 14) for receiving a column address signal (Aj), first decoder means (15 and 19) for decoding an output signal from said first address input means (11 and 13) to select a row of said memory cell array, second decoder means (17 and 21) for decoding an output signal from said second address input means (12 and 14) to select a column of said memory cell array, sense amplifier means (24) for amplifying readout data from a memory cell (MC) selected in response to an output from said first and second decoder means (15, 19 and 17, 21), and output means (25, 26 and 27) for outputting a signal from said sense amplifier means (24), characterized by further comprising delay means (20) for delaying an output signal from said second address input means (12 and 14) within a period of time after the row and column address signals (Ai and Aj) are input until a row address of a memory cell (MC) in said memory cell array is determined in response to an output from said first decoder means (15 and 19), wherein said delay means (20) comprises a first inverter (36 or 42) an input terminal of which receives an output signal from said second address input means (12 and 14), and a second inverter (37 or 43) an input terminal of which receives an output (Ajin) from said first inverter (36 or 42), said first inverter (36 or 42) having characteristics wherein the level of the output signal rises quickly and falls slowly, and said second inverter (37 or 43) having characteristics wherein the level of the output signal rises slowly and falls quickly. A device according to claim 1, characterized in that said first inverter (36) comprises a load MOS transistor (38) and a driving MOS transistor (39), said load MOS transistor (38) having a driving capacity larger than that of said driving MOS transistor (39), and said second inverter (37) comprises a load MOS transistor (41) and a driving MOS transistor (40), said driving MOS transistor (40) having a driving capacity larger than that of said load MOS transistor (41). A device according to claim 1, characterized in that said first inverter (42) comprises a first load MOS transistor one end of a current path of which is connected to a first potential supply source (V DD ), and a gate of which is connected to an output terminal of said second address input means (12 and 14), a first load element (44) one end of which is connected to the other end of the current path of said first load MOS transistor, and a first driving MOS transistor a current path of which is connected between the other end of said first load element (44) and a second potential supply source, and a gate of which is connected to said output terminal of said second address input means (12 and 14), and said second inverter (43) comprises a second load MOS transistor one end of a current path of which is connected to said first potential supply source (V DD ), and a gate of which is connected to the other end of the current path of said first load MOS transistor, a second load element (45) one end of which is connected to the other end of the current path of said second load MOS transistor, and a second driving MOS transistor a current path of which is connected between the other end of said second load element (45) and said second potential supply source, and a gate of which is connected to the other end of the current path of said second load MOS transistor. A device according to claim 1, characterized in that said first decoder means comprises a first address predecoder (15) and a row main decoder (19), and said second decoder means comprises a second address predecoder (17) and a column main decoder (21), said delay means (20) being arranged between said second address predecoder (17) and said column main decoder (21). A device according to claim 1, characterized by further comprising address transition detector means (16, 18, 22), respectively connected to output terminals of said first and second address input means (11, 13 and 12, 14), for detecting a change in address signal (Ai and Aj), and bit line pair equalizer means (23) for operating for a predetermined period of time in response to an output ( EQ ) from said address transition detector means (16, 18, 22), and equalizing bit line pairs (BL, BL ) of said memory cell array. A device according to claim 5, characterized in that said address transition detector means comprises first and second address transition detectors (16 and 18) an input terminal of each of which is connected to an output terminal of said address input means (13 and 14), and a clock generator (22) for receiving outputs from said first and second address transition detectors (16 and 18), and outputting an equalizing signal ( EQ ). A device according to claim 1, characterized by further comprising address transition detector means (16, 18, 22), respectively connected to output terminals of said first and second address input means (13 and 14), for detecting a change in address signal (Ai and Aj), and bit line pair equalizer means (23) for operating for a predetermined period of time in response to a first output signal ( EQ1 ) from said address transition detector means (16, 18, and 22), and equalizing bit line pairs (BL, BL ) of said memory cell array, and sense amplifier line pair equalizer means (46) for operating for a predetermined period of time in response to a second output signal ( EQ2 ) from said address transition detector means (16, 18, 22), and equalizing a pair of output lines (SOa, SOb) of said sense amplifier means (24). A device according to claim 7, characterized in that said address transition detector means comprises first and second address transition detectors (16 and 18) input terminals of which are respectively connected to output terminals of said first and second address input means (11, 13 and 12, 14), and a clock generator (22) for receiving outputs from said first and second address transition detectors (16 and 18), and outputting first and second equalizing signals ( EQ1 ,  EQ2 ).

Inventors: MATSUI MASATAKA, OOTANI TAKAYUKI, MATSUI, MASATAKA, OOTANI, TAKAYUKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1989
Main classification: G11C5
IPC codes: H01L27, G11C5, G11C11, G11C8