Parallel computer system using a SIMD method

Abstract: A parallel computer system using a SIMD method, which in one aspect is constituted by a controller (10) and a plurality of processor elements (14), each of the processor elements has a storage unit to store data to be processed, the controller controls operation of the processor elements, and the parallel computer system performs processing of the data based on a calculation control signal transmitted from the controller (10). The parallel computer system further comprises: a data collection unit (13) connected between the processor elements and the controller (10) for receiving output data from the processor elements (14), performing a predetermined calculation, and outputting calculated data to the controller; and a calculation control unit (15) connected between the data collection unit (13) and the controller (10) for transmitting the calculation control signal from the controller to the data collection unit (13) to make it possible to perform the predetermined calculation in the data collection circuit. In another aspect (Fig. 10), the parallel computer system comprises: a controller (10), a plurality of control groups (G1...G4), each of the control groups being constituted by a number of processor elements divided from a plurality of the processor elements (14), for use as an address control unit; a plurality of scheduling circuits (110), each of the scheduling circuits provided for one of the control groups (G1...G4) and operatively connected to the controller (10), and for receiving and managing an event signal designating an address signal for data to be processed and transmitted from an adjacent control group; and a plurality of real address generation circuits (120), each of the real address generation circuits provided for one of the control groups (G1...G4) and connected between the controller (10), the scheduling circuit (110), and the control group, for generating an address signal for data to be processed by the processor element (14) belonging to the control group based on a base address determined by the event signal to be managed by the scheduling circuit (110), and an address signal applied from the controller (10).

Description: The present invention relates to a parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements connected to each other in a lattice configuration. Parallel computer systems are widely used, particularly, in the field of CAD (Computer Aided Design) which necessitates high speed calculation for a LSI (large scale integrated) circuit design. Accordingly, it is necessary to improve techniques to make these processor elements operate more efficiently in accordance with requirements of high density and high speed LSI. There are two types of parallel computers based on the connection configuration between the processor elements and the controller. One method is called an MIMD (multiple instruction stream multiple data stream) method which is constituted by a plurality of processor elements and controllers. In this method, each of the processor elements is connected to a corresponding controller, respectively. Accordingly, it is necessary to provide the same number of controllers as there are processors. However, it is difficult to constitute a large scale parallel computer system using this method because a large number of controllers are necessary in accordance with the number of processors, which can be from several tens to several hundreds of processors. The other method is called an SIMD (single instruction stream multiple data stream) method which is constituted by a plurality of processor elements and one controller. In this method, the controller is connected in parallel to all processor elements. Accordingly, it is possible to constitute a large scale parallel computer which has a large number of processor elements, for example, several tens of thousands of processors. In the latter method, a "Connection Machine" made by Thinking Machines Corporation uses the SIMD method. This system is constituted by several tens of thousands of processor elements. However, there are some problems in the SIMD type of parallel computer. A first problem occurs in the synchronization of all the processor elements. In general, two countermeasures are taken for solving this problem. In one method, data for obtaining synchronization is exchanged between processor elements through a transmission line. However, it is necessary for all the processor elements to be entirely connected to effectively apply this method. In the other method, a particular signal for obtaining synchronization is output from each processor element. Then, a "wired-OR" logic is performed on all of the synchronization signals and the resultant data of the wired-OR is returned to all of the processor elements. However, the number of processor elements is limited in the wired-OR logic approach because a large delay occurs in the wired-OR logic operation. A second problem occurs in the order of priority use of the bus line. When the number of processor elements reaches from several thousand to several tens of thousands, it is necessary to determine the priority order of use of the bus line. A third problem occurs in the extraction of essential data from essential processor elements. The essential data is, for example, maximum data or minimum data. A parallel computer system according to the present invention is provided in view of the above problems. Embodiments of the present invention may provide a parallel computer system using a SIMD method enabling high efficiency data processing and high load distribution capability. According to the invention, there is provided a parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of the processor elements having a storage unit to store data to be processed, the controller controlling the operation of the processor elements, and the parallel computer system processing data based on a calculation control signal transmitted from the controller, characterised in that the parallel computer system comprises: a data collection unit connected between the processor elements and the controller for receiving data output from the processor elements, performing a predetermined calculation, and outputting calculated data to the controller; and a calculation control unit connected between the data collection unit and the controller for transmitting the calculation control signal from the controller to the data collection unit to make it possible to perform the predetermined calculation in the data collection unit. Reference is made, by way of example, to the accompanying drawings in which:- Fig. 1 is a basic block diagram of a type of parallel computer system embodying the invention; Fig. 2 is one embodiment of a parallel computer system shown in Fig. 1; Fig. 3 is a schematic block of a processor element shown in Figs. 1 and 2; Fig. 4 is a schematic block diagram of a gathering logic unit GLU shown in Fig. 1; Fig. 5 is a table for explaining various control signals shown in Fig. 4; Fig. 6 shows one example of a gathering logic unit shown in Fig. 1; Fig. 7 is a signal timing chart for explaining the operation of the circuit shown in Fig. 6; Fig. 8 is a detailed block diagram of a gathering logic unit shown in Fig. 4; and Fig. 9 is detailed block diagram of the MAX/MIN/ADD calculation circuit shown in Fig. 4. Figure 1 is a basic block diagram of one type of parallel computer system embodying the invention. In Fig. 1, reference number 10 denotes a controller, 11 a control memory for storing a micro-code including output control signals, and 12 a global data register for performing an input/output operation of the data processed or to be processed. The control memory 11 and the global data register 12 are provided in the controller 10. Reference number 13 denotes a data collection circuit for collecting output data from processor elements (PE) 14. 15A to 15D denote control registers CR constituting a calculation control circuit and connected to each other using a pipe-line method for applying various calculation control signals to the collection circuit 13. 16A to 16D denote gathering logic units (GLU) constituting the collection circuit 13 and each constituted by a tree configuration. Reference number 17 denotes a signal line for the calculation control signal to the GLU, 18 a signal line for controlling processor elements, and 19 a data line for broadcasting global data. Each of the processor elements comprises a data register for storing the data to be processed and an arithmetic logic unit ALU as shown in Fig. 3. The arithmetic logic unit ALU calculates the data stored in the register in response to the order transmitted from the controller 10 through the signal line 18. Each gathering logic unit GLU 16A to 16D collects the output data transmitted from the processor elements. The gathering logic units 16A to 16D are connected in the form of a tree configuration having several stages. That is, in Fig. 1, the units 16A are the first stage, the units 16B are the second stage, and the unit 16D is the final stage. The outputs of the processor elements 14 are input to the gathering logic units 16A. The resultant calculation data obtained in the GLU's 16A are output to the GLU's 16B. Similarly, the resultant data obtained in the GLU's 16B are output to the next stage. The final stage 16D gathers all resultant data obtained in the previous stages and the data calculated in the final stage 16D is output to the global data register 12 in the controller 10. Each of the calculation control registers CR 15A to 15D are connected in series with each other using the pipe-line method. The number of registers is equal to the number of stages in the gathering logic unit GLU. In this case, the calculation in each stage is performed in response to the calculation control signals, for example, an "ADD" calculation signal, transmitted through the signal line 17. That is, when the calculation signal "ADD" is input to the first stage 16A, the calculation suggested by the calculation signal is performed in the first stage 16A regarding the data output from the processor elements. This calculation signal is transmitted to the next stage in response to the clock signal from the controller 10 and the same calculation suggested by the calculation signal is performed in the second stage 16B. The above calculation is performed using the pipe-line method. That is, when the first calculation signal "ADD" is input to the first stage, the next calculation signal, for example, "MAX" is input to the first stage. The synchronization of all processor elements is performed in accordance with a synchronization signal from the controller 10. The controller 10 sends the synchronization signal to all processor elements through the control line 18 to output the value "1" when each processor element completes the predetermined processing. At the same time, the signal "AND" is transmitted to the control register 15A through the control line 17. When the calculation signal "AND" is set in the register 15A, the GLU 16A of the first stage performs an "AND" calculation regarding all output from the processor element in response to the first clock. The same "AND" calculation is performed in the GLU 16B of the next stage in response to the next clock. When the same "AND" calculation is performed in the GLU 16D of the final stage in response to the clock and the resultant data is the value "1", the controller 10 can recognize that all processor elements output the value "1". The essential processor element having the essential data is extracted as follows. A proper processor number is previously attached to each processor element. First, the controller 10 commands the essential processor element to output the proper number. Second, the controller 10 commands another processor element to output a suitable signal, for example, the value "11---1" or "00---0". The controller 10 then sends the control signal "MAX" or "MIN" to the control register 15A. Accordingly, the essential processor element can be selected in response to "MAX" or "MIN" of the number in the collection circuit 13. In this case, a next essential processor element can be selected from the remaining processor elements excluding the first essential processor element in the same manner as the above. Accordingly, it is possible to use this circuit to select the priority order of use of a bus line. Figure 2 illustrates one particular embodiment of the system shown in Fig. 1. The same reference numbers as used above indicate the same components. In Fig. 2, reference number 20 denotes a processor array the elements of which are connected to each other in a lattice configuration. As explained above, the processor array and the collection circuit are controlled by the control signals from the controller 10. The control memory 11 in the controller 10 comprises a plurality of control formats 1 to n. The controller 10 further comprises a sequencer 21 which determines the sequence for reading out the control information from the control memory 11. The global data register 12 is a register for holding the data transmitted in common to all processor elements and to receive the output data from the collection circuit 13. Figure 3 is a schematic block of a processor element. In Fig. 3, reference number 30 denotes a data register for holding the data to be processed. 31 denotes an arithmetic logic unit ALU for calculating the data stored in the register 30. The processor element 14 is controlled by the same control signal transmitted from the controller 10. This control signal includes an address of the data register 30 and an operation code for the arithmetic logic unit 31. The processor element 14 further comprises four ports, i.e., east port (E), west port (W), north port (N) and south port (S) for communicating between adjacent processor elements. The processor element 14 further comprises an input terminal GT for inputting the data from the global data register 12, and a collection terminal CT for outputting the data. The processor element 14 is a one-bit type and the input/output operation to the data register 30 is basically performed for each bit. Data larger than one bit is processed from the most significant bit (MSB) or the least significant bit (LSB) for each bit. Figure 4 is a schematic block diagram of a gathering logic unit GLU. Each of the gathering logic units GLU 16A to 16D comprises an OR calculation circuit 40, an AND calculation circuit 41, a MAX/MIN/ADD calculation circuit 42 and a selector circuit SEL 43. The signal GLI is data input to the GLU 16 and constituted by 32 bits. This means that one GLU 16 can handle a maximum of 32 bits in the input side. The signal GLO is resultant data and is constituted by one bit. Kinds of calculation control signals input to the GLU 16 from the control registers 15A to 15D are as follows. These control signals are shown in a table in Fig. 5. XGOPS (2 bits) This is an operation code for the GLU 16. When this signal is the value "00", the AND calculation is performed, when it is "01", the OR calculation is performed, when it is "10", the "MIN" or "MAX" calculation is performed, and when it is "11", the "ADD"calculation is performed. XGCR (1 bit) This is a carry control signal for a carry clear operation in the "ADD" calculation. GLSTS (2 bits) This is a switching signal for switching the number of bits of the input signal to the GLU. That is the number of bits of the input signal, for example, 32 bits, 16 bits, 8 bits, or 4 bits can be selected by this switching signal. GMAXS (1 bit) This is an instruction signal to select either a "MIN" or "MAX" calculation when the operation order XGOPS is the value "10". GNOPS (1 bit) This is an instruction signal to force the input signal to "0". When this bit is "0", the input data GLI becomes invalid. Figure 6 shows one example of a gathering logic unit GLU. As is obvious from the drawing, the first stage is constituted by four GLU's 16-1 to 16-4, and the second stage (final stage) is constituted by one GLU 16-5. Since each GLU can handle 32 bits in the input side, this circuit can handle up to 128 bits in the input side. The operation code XGOPS and the carry control signal XGCR are used in the registers 15-1 and 15-2 to simplify the explanation Accordingly, the GLU performs the calculation under the above operation code and the carry control signal. Further, reference numbers 50 to 58 denote registers for the pipe-line control. OP-1 denotes a signal set in the register 15-1, and OP-2 a signal set in the register 15-2. Further, D1 denotes data set in the registers 50 to 53, D2 data set in the registers 54 to 57, and D3 data set in the register 58. Figure 7 is a signal timing chart for explaining the operation of the circuit shown in Fig. 6. In Fig. 7, B0 to B3 denote four-bit data to be processed, B0 is a least significant bit (LSB) and B3 is a most significant bit (MSB). In the "ADD" operation, these bits are sequentially input to the registers 50 to 53 from the LSB to the MSB, bit by bit, in response to a clock signal CLK. Synchronizing with the data, the operation code "ADD" for addition is set in the register 15-1. The carry control signal XGCR is input to the GLU so as to indicate the carry clear with the value "0" in the first clock, and so as to indicate the normal calculation with the value "1" in the next clock. The first stage GLU 16-1 to 16-4 performs an addition calculation for 32 bits regarding the bit B0 (LSB) under the order OP-1 in response to the first clock. The first stage 16-1 to 16-4 next performs an addition calculation of 32 bits regarding the bit B1 in response to the next clock. In this addition calculation, the carry operation is taken into consideration for the resultant data of the bit B0. These calculations are continued until the bit B3. The resultant data obtained by the GLU 16-1 to 16-4 is set in the register 54 to 57. In this case, the order OP-1 is moved to the OP-2 at every clock. The final stage GLU 16-5 performs the addition calculation for four input signals in response to the order OP-2. The resultant data is output to the register 58. Since the collection circuit is constituted by two stages, the GLU 16-5 performs the same operation as that of the GLU 16-1 to 16-4 after a delay of one clock. As explained above, the calculation is performed using the pipe-line method. Regarding the calculation of "MAX" and "MIN", the same calculation as mentioned above can be performed with an optional bit length. In this case, the bits are input from the MSB to the LSB. Figure 8 is a detailed block diagram of a gathering logic unit shown in Fig. 4. In Fig. 8, A1 denotes an AND circuit, N1 to N5 denote NOR circuits, NA-1 to NA-5 denote NAND circuits, S1 to S5 denote selectors, and MA00 to NA40 denote MAX/MIN/ADD calculation circuits. The AND circuit Al sets the input data GLI to all zeroes when the control signal GNOPS is the value "0". The NOR circuits N1 to N4 and the NAND circuit perform the OR calculation in accordance with the number of input stages regarding the input data GLI. The NAND circuits NA2 to NA5 and the NOR circuit N5 perform the AND calculation regarding the input data GLI. The MAX/MIN/ADD calculation circuits MA00 to MA40 perform the maximum/minimum/addition calculation. The selectors S1 to S4 select the output in accordance with the operation code XGOPS. The selector S5 performs the selection in accordance with the number of the input stage. Figure 9 is detailed block diagram of the MAX/MIN/ADD calculation circuit. In Fig. 9, A10 to A16 denote AND circuits, N10 to N12 NOR circuits, NT0 to NT6 NOT circuits, 01 to 02 OR circuits, R0 to R1 registers, S10 to S11 selectors, and 90 a full adder having three inputs. This circuit performs a maximum/minimum calculation for 2 inputs. DM0 and DM1 are the input signals each having one bit to obtain a maximum/minimum value. DA0 and DA1 are the input signals each having one bit for addition. XM is resultant data for a maximum/minimum calculation and XA is resultant data for addition. In the first stage MA00 to MA15, the DM0 is equal to the DA0, and the DM1 is equal to the DA1, respectively. The operation of the addition "ADD" is explained in detail below. The addition data is input to the DA0 and DA1 from the LSB bit at every bit. In the first bit, since the signal XGCR is the value "0", the carry is cleared so that the carry CARRY-0 becomes "0". The adder 90 performs the addition regarding the DA0 and DA1, and the resultant data XA is output therefrom. When no carry is performed in the addition, the output signal CARRYOUT becomes "0". When a carry is performed, the output signal CARRYOUT becomes "1". The signal CARRYOUT is held in the register R0 for use in the addition at the next clock through the selector S10. In the next bit from the LSB, the content of the register R0 is used as the carry CARRY-0, and is added to the DA0 and DA1. The operation for obtaining the maximum value is explained in detail below. When obtaining the maximum value, the signal GMAXS is the value "0", the input data is input to the DM0 and DM1 at every bit from the MSB bit. In the first bit, the signal XGCR is "0", and the outputs of the AND circuit A10 and A11 are "0" so that the output of the NOR circuit N12 becomes "1" and the outputs of the AND circuits A14, A15 and the OR circuit 01 become "0". Accordingly, the selection signal in the selector S11 becomes "10" so that, as the maximum output XM, the output of the OR circuit 02 is selected in the OR logic operation between the DM0 and DM1. In the registers R0 and R1, when one of the DM0 and DM1 previously becomes "1", the value "1" is set to the corresponding side. That is, when the DM0 is "1" and the DM1 is "0", the value "1" is set to the register R0. On the contrary, when the DM0 is "0" and the DM1 is "1", the value "1" is set to the register R1. When the value "1" is input to one of the registers R0 and R1, the output of the NOR circuit N12 becomes "0" from the next clock. Further, the output of the OR circuit 01 becomes "1" when the register R0 is "1" and becomes "0" when the register R1 is "1". Accordingly, after the above selection, the selector 11 outputs the value of either the DM0 or the DM1 in which the value "1" was previously detected. The operation for obtaining the minimum value is explained in detail below. When obtaining the minimum value, the signal GMAXS is the value "1". The operation is the same as that for the maximum. When the output of the NOR circuit N12 is the value "1", the selection signal to the selector S11 is "11" and the output of the AND circuit A16 is selected. When one of the DM0 and DM1 becomes "1", one of the registers R0 and R1 becomes "1" and the selection signal to the selector S11 becomes "00" or "01". After the above selection, the minimum value in either DM0 or DM1 is selected.

Claims: A parallel computer system using a SIMD method constituted by a controller (10) and a plurality of processor elements (14), each of said processor elements having a storage means to store data to be processed, said controller controlling operation of said processor elements, and said parallel computer system performing processing of said data based on a calculation control signal (17) transmitted from said controller, characterised in that said parallel computer system comprises: a data collection means (13) connected between said processor elements (14) and said controller (10) for receiving output data from said processor elements, performing a predetermined calculation, and outputting calculated data to said controller, and a calculation control means (15) connected between said data collection means (13) and said controller (10) for transmitting said calculation control signal (17) from said controller to said data collection means to make it possible to perform said predetermined calculation in said data collection means. A parallel computer system as claimed in claim 1, wherein said data collection means (13) comprises a plurality of gathering logic units (16) coupled in a tree configuration having a plurality of stages (16A-16D), a first stage (16A) of said gathering logic units receiving said output data from each of said processor elements (14), a second stage (16B) of said gathering logic units receiving calculation data obtained from said first stage, calculation data obtained from said second stage (16B) being output to a next stage (16C), and final calculation data obtained from a final stage (16D) being output to said controller (10). A parallel computer system as claimed in claim 2, wherein said calculation control means (15) comprises a plurality of control registers (15A-15D) corresponding to the number of said stages (16A-16D), each of the control registers being connected by a pipe-line method, and each of the control registers sequentially outputting said calculation control signal to each of said stages (16A-16D). A parallel computer system as claimed in claim 1 or 3, wherein said calculation control signal comprises an AND calculation signal, an OR calculation signal, a MAX/MIN calculation signal, and an ADD calculation signal. A parallel computer system as claimed in claim 1, 2, or 4, wherein each gathering logic unit (16) comprises an OR calculation circuit (40) for performing a logic OR calculation of data output from each of said processor elements (14), an AND calculation circuit (41) for performing a logic AND calculation of data output from each of said processor elements, a MAX/MIN/ADD calculation circuit (42) for obtaining a maximum value, minimum value, or added value of data output from each of said processor elements, and a selector (43) for selecting said OR calculation circuit, AND calculation circuit, and MAX/MIN/ADD calculation circuit, these calculations being performed in response to said calculation control signal.

Inventors: KAWAMURA KAORU, MIWATARI HIDEKI, SHIBUYA TOSHIYUKI, SHINDO TATSUYA, UMEDA MASANOBU, KAWAMURA, KAORU, MIWATARI, HIDEKI, SHIBUYA, TOSHIYUKI, SHINDO, TATSUYA, UMEDA, MASANOBU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1989
Main classification: G06F15
IPC codes: G06F15