Semiconductor driver for producing switching and offset signals

Abstract: A semiconductor intergrated circuit device for applying to an external load connectable between an output terminal (7) and a power supply terminal (1), a switching signal and an offset signal in superposed relation to each other. An offset signal supplying circuit for supplying an offset signal to the output terminal (7) is comprised of a first field effect transistor (Q19) having a drain electrode connected to the output terminal, and a second field effect transistor (Q18) having the substantially same characteristics as the first field effect transistor (Q19). The second field effect transistor (Q18) has a drain electrode connected to a source electrode of the first field effect transistor (Q19), a gate electrode connected to a control terminal (6) receptive of a control signal effective to control the offset signal, and a source electrode connected to a negative power supply terminal. A constant-voltage generating circuit (28) for generating and applying a constant voltage to a gate electrode of the first field effect transistor (Q19) is comprised of a resistor (R11) connected between a positive power supply terminal (1) and the gate electrode of first field effect transistor (Q19), and a plurality of diodes (D13-16) having the substantially same characteristics and being forwardly series-connected to each other such that an anode of the first stage diode is connected to the gate electrode of the first field effect transistor (Q19) and a cathode of the last stage diode is connected to the negative power supply terminal (2) so that a voltage between the series-connected diodes is set to half of a power supply voltage applied between the positive and negative power supply terminals, each of the diodes having an internal resistance smaller than a specific resistance of the resistor.

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device for driving an external load such as a laser diode, and more specifically relates to a semiconductor integrated circuit device of the GaAs digital IC type having a GaAs substrate formed thereon with a plurality of Shottky junction type field effect transistors. With the development of high speed digital signal processing technology including optical communication technology, the GaAs digital IC becomes more important for use as a semiconductor laser driver (hereinafter, referred to as "laser driver") for driving directly a semiconductor laser at an ultra high speed (c.f. Japanese Electrocommunication Society, technology research report SSD-85-140), and The Technical Digest of the IEEE GaAs IC Symposium 1985 pages 103-106 which discloses a GaAs laser-driver operating at up to 2 Gbits/s data rate. Hereinafter, the conventional laser driver will be explained in conjunction with the attached drawings. Fig. 1 shows a driver described in the above-mentioned document, constructed of field effect transistors (FETs) and diodes which are composed of Shottky junction type field effect transistors and diodes. These FETs and diodes are formed on a GaAs substrate together with other components. Referring to Fig. 1, the laser driver is provided with an earth terminal 31 and a power supply terminal 32. Normally, a power supply voltage of -5.2V is applied to the power supply terminal 32 with respect to the earth terminal 31. An input signal is inputted from an input terminal 33 through a level shifting circuit comprised of FET Q₄₁, level shifting diode D₄₁ and current supplying FET Q₄₃ into a gate electrode of FET Q₄₆ which constitutes a part of output differentially operating circuit. Further, the laser driver is provided with a reference terminal 34 receptive of a reference signal such as an opposite phase signal or a reference voltage of -1.3V. The reference signal received at the reference terminal 34 is inputted through another level shifting circuit composed of FET Q₄₂, level shifting diode D₄₂ and current supplying FET Q₄₄ into a gate electrode of FET Q₄₅ which is contained in the output differentially operating circuit. The output differentially operating circuit is comprised of the FET Q₄₅, the FET Q₄₆ and current supplying FET Q₄₇, and carries out switching of an output current at ultra high speed. The gate electrode of FET Q₄₇ is connected.to a switching current control terminal 35, and the drain terminal of FET Q₄₆ is connected to an output terminal 37. Further, an FET Q₄₈ has a function of supplying an offset current, and the gate electrode thereof is connected to an offset current control terminal 36 and the drain terminal thereof is connected to the output terminal 37. In the prior art laser driver having the above-described structure, the drain current flowing through the FET Q₄₈ is applied to a load in the form of a laser diode 38 as an offset current I o , and the drain current flowing through the FET Q₄₇ included in the output differentially operating circuit is also applied to the load as a switching current I s . The offset current I o can be controlled by applying externally a control voltage to the offset current control terminal 36, and the switching current I s can be controlled by applying externally another control voltage to the switching current control terminal 35. In general, a needed maximum value of the switching current I s is about 50mA, and a needed variable range of the offset current I o is from 0mA to 100mA. The set value of offset current I o is determined according to a threshold current of the laser diode 38. Fig. 2 shows the relation between the above-described offset current I o and switching current I s . In Fig. 2, a waveform a represents a time-responsive waveform of the output current where the magnitude of offset current I o is indicated by b , and the amplitude of switching current I s is indicated by c . However, the above-described prior art laser driver has the following drawbacks. As appearant from Fig. 2, when the set value of offset current I o (indicated by b ) is zero, the minimum magnitude of the output current becomes zero. In such case, as appearant from Fig. 1, a voltage V DS between the drain and source electrodes of FET Q₄₈ which has the function of supplying the offset current is held about 5.2V. Further, in similar manner, when the offset current I o is set to zero value, a voltage V GS between the gate and source electrodes of FET Q₄₈ must satisfy the following relation (1) such that the value of V GS exceeds the threshold value V th of the FET Q₄₈. V GS < V th Normally, the threshold value V th is set within the range from about -1.0V to about -0.5V for the high speed operation. On the other hand, a high performance FET is utilized as FET Q₄₈ in the laser driver so as to obtain the high speed operation characteristic. Such a high performance FET has a reverse withstanding voltage of about -6V to -5V between the gate and drain electrodes. In this connection, the voltage V GD applied between the gate and drain electrodes of FET Q₄₈ used in the prior art shown in Fig. 3 is represented according to the following relation (2) by using the relation (1). V GD = V GS - V DS < V th - V DS As described above, since the value of V th is set to -1.0V to -0.5V and the maximum value of V DS is 5.2V, the value of V GD is represented by: V GD < -6.7V to -5.7V Consequently, the maximum value of V GD can be very close to -6.7V through -5.7V and therefore is comparable to the reverse withstanding voltage of -6V through -5V in the offset current supplying FET Q₄₈ used in the prior art laser driver of Fig. 1. For this reason, when carrying out the high speed operation, the FET Q₄₈ is actually operated under the state close to the limit capacity, thereby causing reliability problem such as deterioration of FET Q₄₈. In order to eliminate the drawbacks of the first prior art laser driver, the inventor devised a laser driver such as shown in Fig. 3. In the figure, the same components are designated by the same reference numerals as in Fig. 1, and therefore the detailed description thereof is omitted. Referring to Fig. 3, an offset current supplying FET Q₄₉ and voltage dividing FET Q₅₀ are connected between the power supply terminal 32 and output terminal 37. Namely, the source electrode of FET Q₄₉ is connected to the power supply terminal 32, the drain electrode of FET Q₄₉ is connected to the source terminal of FET Q₅₀, and the drain electrode of FET Q₅₀ is connected to the output terminal 37. Further, the gate electrode of FET Q₄₉ is connected to the offset current control terminal 36. A pair of voltage dividing resisters R₄₁ and R₄₂ are series connected between the earth terminal 31 and power supply terminal 32, and the junction point therebetween is connected to the gate electrode of FET Q₅₀. In this devised structure, the FETs Q₄₉ and Q₅₀ are formed to have the same structure and parameters such as pattern dimensions of parts and threshold voltage. Further, the voltage dividing resistors R₄₁ and R₄₂ are formed to have the same resistance. For this reason, a potential at the gate electrode of FET Q₅₀ is set to -2.6V which is a half of the power supply voltage -5.2V applied between the earth terminal 31 and power supply terminal 32. In addition, the resistance of the resistors R₄₁ and R₄₂ is set to about 1kΩ, respectively, so as to avoid the increase of current consumption. In this case, the total power consumption of about 13.5mW is consumed by the resistors R₄₁ and R₄₂, and such value can be negligible in actual use. As described above, in Fig. 3, the FETs Q₄₉ and Q₅₀ have the identical structure and the gate potential of FET Q₅₀ is fixed to -2.6V. For this reason, when both of the offset current I o and switching current I s becomes zero, a voltage V DS between the drain and source electrodes of FET Q₄₉ is held 2.6V+V th , and another voltage V DS between the drain and source electrodes of FET Q₅₀ is held 2.6V-V th where V th (V) is a threshold voltage of FET Q₄₉. Further, a voltage V GD between the gate and drain electrodes of FET Q₅₀ is held -2.6V and another V GD between the gate and drain electrodes of FET Q₄₉ is held about 2V th -2.6V. In this case, the value of V GD of FET Q₄₉ is held in the range from -4.6V to -3.5V when the value of V th is set to the range between -1V and -0.5V. Accordingly, Fig. 3, since a load voltage exceeding the reverse withstanding voltage from -6V to -5V between the gate and drain electrodes cannot be applied to the respective FETs Q₄₉ and Q₅₀, a laser driver having high reliability can be obtained. However, in the laser driver of Fig. 3, the additional function to vary the offset current I o within the range from 0mA to 100mA is needed in accordance with the threshold current value of laser diode 38 to be driven as described above. On the other hand, with the need for higher speed processing in a general digital IC including GaAs digital IC, a new problem relating to the interface emerges, and therefore the additional function is needed to vary the offset voltage of output signal. In this regard, when providing the function to change the offset current (or offset voltage) over a wide range in Fig. 3, there is caused a problem that a waveform of high frequency modulation is deteriorated. Hereinafter, this problem will be explained. As described already, the variable range from about O to 100mA is needed for the offset current I o in the laser driver. In this case, the respective gate electrode of FETs Q₄₉ and Q₅₀ must have the gate width of about 400µm through 600µm in order to flow a relatively large current through the FETs Q₄₉ and Q₅₀. In addition, when controlling the offset current I o by applying an external control voltage to the offset current control terminal 36, the respective voltage V GS between the gate and source electrodes of FETs Q₄₉ and Q₅₀ is set to 0.4V through 0.5V. In this case, a parasitic capacitor C gd between the gate and drain electrodes of FET Q₅₀ has a capacitance more or less exceeding 0.3pF through 0.5pF due to the great width of gate electrode and the forward biasing of 0.4V through 0.5V between the gate and source electrodes. Further, by the combination of capacitance of capacitor C gd of FET Q₅₀ and resistances of voltage dividing resistors R₄₁ and R₄₂, the transition characteristic of output current outputted from the output terminal should have long time-dependant component. Since the resistors R₄₁ and R₄₂ have the resistance of 1kΩ, respectively, and the capacitor C gd has the capacitance of 0.3pF through 0.5pF, a time constant defined as the product of the parallel composite resistance of resistors R₄₁ and R₄₂ and the capacitance of capacitor C gd is caluculated to 150psec through 250psec. Such order of time constant cannot be neglected in ultra high speed modulation characteristic on the order of Gb/sec. Such situation will be explained with reference to Fig. 4. Referring to Fig. 4, the level of offset current I o is indicated by d when I o =0, the amplitude of switching current I s is indicated by e when I o =0, and the waveform of switching current I s is indicated by f when I o =0. In case of I o =0, the respective voltage V GS of FETs Q₄₉ and Q₅₀ is reverse biased as V GS < V th so that the above described deterioration of high frequency modulating signal waveform due to the capacitor C gd is not remarkable. On the other hand, the DC level of offset current I o is indicated by g when the respective FETs Q₄₉ and Q₅₀ are forward biased at 0.4V through 0.5V between the gate and source electrodes thereof. The level of offset current I o is set to a great value of 80mA through 100mA, and the amplitude of switching current I s is indicated by h and the output waveform of switching current I s is indicated by i . In this case, due to the affect of time constant defined by the product of the parallel composite resistance of resistors R₄₁ and R₄₂ and the capacitance of capacitor C gd , the peak level of output current waveform i cannot reach the level of offset current I o indicated by g . Accordingly, the high level of envelope of output current waveform is different from the DC level of offset current I o . Such deterioration of high frequency modulating signal waveform becomes remarkable when the modulating or switching speed exceeds about 1Gb/sec, thereby causing practically difficult problem. In this case, it is apparent that the maximum operating speed is affected. By reducing the resistances of voltage dividing resistors R₄₁ and R₄₂, the above-mentioned time constant could be reduced as desired. For example, if the resistances of resistors R₄₁ and R₄₂ were set to 100Ω, respectively, the above-mentioned time constant could be 15psec through 25psec and the problem of waveform deterioration could be avoided. However, in such case, the total electric power consumed in the resistors R₄₁ and R₄₂ could reach 140mW through 150Mw to cause practical problem. SUMMARY OF THE INVENTION In order to solve the above-described problems of the prior art structure and the inventor's devised structure, an object of the present invention is to, therefore, provide a semiconductor integrated circuit device in which wasted power is not consumed, and the deterioration of FETs due to the application of voltage close to the reverse withstanding voltage thereof between the gate and drain electrodes thereof and deterioration of high frequency modulating signal waveform can be eliminated. According to the present invention, a semiconductor integrated circuit device for applying to an external load connectable between an output terminal and a first power supply terminal, a switching signal and an offset signal in superposed relation to each other, the device comprising supplying means for supplying an offset signal to said output terminal, and characterised by said supplying means comprising a first field effect transistor having a drain electrode connected to said output terminal, and a second field effect transistor having the substantially same characteristics as said first field effect transistor, said second field effect transistor having a drain electrode connected to a source electrode of said first field effect transistor, a gate electrode connected to a control terminal receptive of a control signal effective to control said offset signal, and a source electrode connected to a second power supply terminal; and constant-voltage generating means for generating and applying a constant voltage to a gate electrode of said first field effect transistor, said constant-voltage generating means comprising a resistor connected between said first power supply terminal and said gate electrode of the first field effect transistor, and a plurality of diodes having the substantially same characteristics and being forwardly series-connected to each other such that an anode of said first stage diode is connected to said gate electrode of said first field effect transistor and a cathode of said last stage diode is connected to said second power supply terminal so that a voltage between said series-connected diodes is set to half of a power supply voltage applied between said first and second power supply terminals, each of said diodes having an internal resistance smaller than the resistance of said resistor. According to the present invention as constructed above, the series-connected resistor and the plurality of diodes actually function as a constant voltage generating circuit. Namely, since the anode of first stage diode in the plural diodes is held at the potential which is half of the voltage applied between the power supply terminals, the gate electrode of first FET is always held at half of the power supply voltage. For this reason, when the power supply voltage is set to, for example, -5.2V, and the threshold voltage of first FET (or second FET) is set to V th , the voltages V DS between the drain and source electrodes of first and second FETs are held at 2.6v+V th and 2.6V-V th , respectively. Further, the voltages V GS between the gate and drain electrodes of first and second FETs are held at about -2.6V and 2V th -2.6V, respectively. Normaldy, since the value of V th is selected between about -1V and -0.5V, the voltage V GD of second FET is held at about -4.6V through -3.5V. Accordingly, in view of the fact that the reverse withstanding voltages between the gate and drain electrodes of first and second FETs have a value of about -6V through -5V, an excessive voltage close to the reverse withstanding voltage is not applied between the gate and drain electrodes of first or second FET, thereby preventing the deterioration of FETs. Moreover, since each of the plural diodes has an internal resistance much smaller than that of the resister in the above-described constant voltage generating circuit, the value of current flowing through this circuit is supressed small substantially according to the resistance of resistor, and therefore the power consumption is sufficiently reduced in the constant voltage generating circuit. Further, since the parallel composite resistance of the resistor and the plural diodes is substantially equal to combined internal resistance of the plurality of series-connected diodes, the time constant defined by the product of parastic capacity between the gate and drain region of first FET and the parallel composite resistance is sufficiently reduced. For this reason, the deterioration of high frequency modulating signal waveform can be sufficiently supressed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an equivalent circuit diagram of the prior art laser driver; Fig. 2 is a waveform diagram showing the output current waveform of the prior art laser driver shown in Fig. 1 and the relation between offset and switching currents; Fig. 3 is an equivalent circuit diagram of the laser driver prior-devised by the inventor; Fig. 4 is a waveform diagram showing the relation among the offset current, the amplitude of switching current and the waveform of output current in the prior-devised structure shown in Fig. 3; Fig. 5 is an equivalent circuit diagram of a first embodiment of the laser driver according to the present invention; and Fig. 6 is an equivalent circuit diagram of a second embodiment of the laser driver according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of semiconductor laser driver according to the present invention will be explained in conjunction with the attached drawings. First, referring to Fig. 5, the first embodiment is explained. Various types of field effect transistors used in the embodiment is composed of Schottky junction type field effect transistor and various types of diodes used in the embodiment is composed of Schottky junction type diodes. Further, these field effect transistors and diodes are formed on a semiconductor substrate composed of GaAs together with other components. As shown in Fig. 5, the semiconductor laser driver is provided with an earth or positive power terminal 1 and a negative power supply terminal 2. Normally, a voltage of -5.2V is applied between the earth terminal 1 and power supply terminal 2 to power the semiconductor laser driver. Further, a pair of first and second level-shifting circuits 25 and 26 are connected in parallel to each other between the earth terminal 1 and power supply terminal 2. The first level-shifting circuit 25 is comprised of a field effect transistor (hereinafter, referred to as "FET") Q₁₁, level-shifting diode D₁₁ and current-supplying FET Q₁₃ connected in series to each other. A gate electrode of the FET Q₁₁ is connected to an input terminal 3 and receives an input signal such that the first level-shifting circuit 25 shifts or regulates the voltage level of input signal according to a given standard. The second level-shifting circuit 26 is comprised of a FET Q₁₂, level-shifting diode D₁₂ and current-supplying FET Q₁₄ connected in series to each other. A gate electrode of the FET Q₁₂ is connected to a reference terminal 4 and receives a reference signal such as, for example, a signal having a phase opposite to that of the input signal so that the second level-shifting circuit 26 shifts or regulates the voltage level of reference signal according to the given standard. An output differentially-operating circuit 27 is connected subsequently to the first and second level-shifting circuits 25 and 26 to differentially operate or process the level-shifted input and reference signals with each other to thereby produce an output signal in the form of a switching current I s effective to drive an external laser diode 8. Namely, the differentially-operating circuit 27 is comprised of a pair of FETs Q₁₅ and Q₁₆ connected in parallel to each other and a current supplying FET Q₁₇ connected in series to the pair of FETs Q₁₅ and Q₁₆. More specifically, a gate electrode of the FET Q₁₅ is branch-connected to a cathode of the level-shifting diode D₁₂ and a drain electrode of the FET Q₁₅ is connected to the earth terminal 1. Further, a gate electrode of the FET Q₁₆ is branch-connected to a cathode of the level-shifting diode D₁₁ and a drain electrode of the FET Q₁₆ is connected to an output terminal 7 which is connectable to the external laser diode 8. The current supplying FET Q₁₇ has a source electrode connected to the power supply terminal 2, a drain electrode connected to the source electrodes of FETs Q₁₅ and Q₁₆, and a gate electrode connected to a switching current control terminal 5 receptive of a first control signal effective to control or regulate the switching current I s . An offset current supplying circuit is connected subsequently to the differentially-operating circuit 27 to supply an offset or bias current I o to the external laser diode 8 in superposed relation to the switching current I s . The offset current supplying circuit is comprised of an offset current supplying FET Q₁₈ for supplying the offset current I o and a voltage-dividing FET Q₁₉ connected in series to the FET Q₁₈ for dividing a voltage between the power supply terminal 2 and the output terminal 7. Namely, the offset current supplying FET Q₁₈ has a source electrode connected to the power supply terminal 2, a drain electrode connected to a source electrode of the FET Q₁₉ and a gate electrode connected to an offset current control terminal 6 receptive of a second control signal effective to control or regulate the offset current I o . The voltage-dividing FET Q₁₉ has a drain electrode connected to the output terminal 7. The FETs Q₁₈ and Q₁₉ have electrically and thermally identical characteristics. Stated otherwise, the FETs Q₁₈ and Q₁₉ have substantially the same structure and parameter with respect to, for example, the pattern dimension of portions thereof and threshold voltage. Further, a constant voltage generating circuit 28 is connected subsequently to the series-connected FETs Q₁₈ and Q₁₉. The constant voltage generating circuit 28 is comprised of a resistor R₁₁ and group of diodes D₁₃-D₁₆ series-connected to each other between the earth terminal 1 and power supply terminal 2. The constant voltage generating circuit 28 is connected at its junction between the resistor R₁₁ and anode of the diode D₁₃ to a gate electrode of the FET Q₁₉ to apply thereto a constant voltage so as to control the voltage-dividing FET Q₁₉. In this case, the resistor R₁₁ has a resistance of 1kΩ, and each of the diodes D₁₃-D₁₆ has an internal resistance r i of less than 10Ω and a forward drop voltage V f of 0.65V between the cathode and anode thereof. Lastly, as mentioned before, the external laser diode 8 is connected between the earth terminal and the output terminal 7 as a load. Next, the operation of embodiment of the semiconductor laser driver as constructed above will be explained hereinbelow. An input signal is inputted from the input terminal 3 into the gate electrode of FET Q₁₆ included in the differentially-operating circuit 27 through the first level-shifting circuit 25. Also, a reference signal in the form of a reference voltage of -1.3V or a signal having a phase opposite to that of the input signal is inputted from the reference terminal 4 into the gate electrode of FET Q₁₅ included in the differentially-operating circuit 27 through the second level-shifting circuit 26. The output differentially-operating circuit 27 operates when receiving the input and reference signals to effect intermittent switching or modulation of a drain current flowing through the current supplying FET Q₁₇ at ultra high speed in response to the voltage difference between the input and reference signals to thereby produce a switching current I s . The switching current I s can be controlled or regulated according to the application of a first external control voltage to the switching current control terminal 5. Another drain current flowing through the FET Q₁₉ and supplied from the FET Q₁₈ is applied as an offset or bias current I o to the laser diode 8 in superposed relation to the switching current I s to thereby intermittently drive the laser diode 8. The offset current I o can be controlled or regulated according to the application of a second external control voltage to the offset current control terminal 6. With regard to the constant voltage generating circuit 28, as described above, each of the series-connected diodes D₁₃-D₁₆ has a forward drop voltage V f =0.65V between the anode and cathode thereof. Accordingly, the anode voltage at the anode of diode D₁₃ is fixed to a constant value of -5.2V+4x0.65V=-2.6V where the voltage value of -5.2V represents the power supply voltage at the power supply terminal 2 with respect to the earth terminal 2. A voltage of |-2.6|V is applied across the resistor R₁₁ which has a resistance of 1kΩ so that the current of 2.6V/1kΩ=2.6mA flows through the resister R₁₁. Consequently, the total power consumption of 2.6mAx1-5.21V= about 13mW is consumed in the resistor R₁₁ and the group of diodes D₁₃-D₁₆, and such value is practically negligible. Further, since the anode potential of diode D₁₃ is fixed to -2.6V, the gate potential at the gate electrode of FET Q₁₉ is always set to the value of -2.6V. Accordingly, the operation of FETs Q₁₈ and Q₁₉ is substantially identical to those used in the second prior work (art) shown in Fig. 4. Namely, when both of the offset current I o and output switching current I s are zero, a drain-source voltage V DS between the drain and source electrodes of FET Q₁₉ equals to 2.6+V th (V), and another drain-source voltage V DS between the drain and source electrodes of FET Q₁₈ equals to 2.6-V th (V) where V th is the threshold voltage of FET Q₁₉. A gate-drain voltage V GD between the gate and drain electrodes of FET Q₁₉ equals to -2.6V, and another gate-drain voltage V GD between the gate and drain electrodes of FET Q₁₈ equals to 2V th -2.6V. In this case, when the value of V th ranges from -1V to -0.5V, the value of V GD of FET Q₁₈ is set to range from -4.6V to -3.5V. Consequently, in this embodiment, no excessive load voltage is applied between the gate and drain electrodes of FETS Q₁₈ and Q₁₉, respectively, not exceeding reverse-withstanding voltage of -6V to -5V thereof, thereby avoiding the deterioration thereof due to application of excessive load voltage thereto. Moreover, since each of the diodes D₁₃-D₁₆ has an internal resistance r i of less than 10Ω, the time constant defined by the product of the parallel composite resistance of resistor R₁₁ and group of diodes D₁₃-D₁₆, and the parastic capacity C gd (0.3pF to 0.5pF) formed between the gate and drain electrodes of FET Q₁₉ equals to the order of C gd x40Ω, i.e., 12psec to 15psec which is smaller by one order than that in the second prior work (art) structure. If the time constant has such value, the wave form of high frequency switching or modulated signal cannot be deteriorated even if the switching or modulation speed exceeds 1Gb/sec, thereby achieving an excellent ultra high frequency modulation characteristic. Referring to Fig. 6, the second embodiment according to the present invention is explained hereinbelow. The same elements are designated by the same reference numerals as in Fig. 1 and therefore the detailed description thereof is omitted. As shown in Fig. 2, an additional resistor R₁₂ is connected between the source electrode of offset current supplying FET Q₁₈ and the power supply terminal 2 for monitoring the offset current I o . The resistance of resistor R₁₂ is set to about 10Ω. An offset current monitoring terminal 9 is branch-connected to the source electrode of FET Q₁₈. As appearant from the circuit construction shown in Fig. 6, the additional resistor R₁₂ does not deteriorate the waveform of switching or high-frequency-modulating signal effective to intermittently switching the laser diode. According to this embodiment as constructed above, the potential difference between the monitoring terminal 9 and the power supply terminal 2 is measured so as to easily monitor the offset current I o . Such monitoring is considerably effective for automatic stabilization of output of the laser diode 8, and prevention of the laser diode destruction. As explained above, the first and second embodiments are used as a current modulating element for driving the laser diode; however, the present invention is not limited to such application. Namely, the present invention can be widely applied to a general semiconductor integrated circuit device having controlling function for offset current or voltage. As described above, the present invention has following advantages: 1. The electric power consumption is sufficiently reduced in the constant voltage generating circuit which applies a constant voltage to the gate electrode of voltage-dividing FET. 2. The FETs can be driven with a voltage sufficiently smaller than the reverse withstanding voltage between the gate and drain electrodes of the FETs so that the deterioration of the FETs can be easily prevented. 3. In case that the offset current is set to a relatively great amount of 30mA to 100mA or the offset voltage is set to a relatively great amount in a similar manner, the deterioration of high frequency output switching signal which is caused by the time constant defined by the product of parastic capacity between the gate and drain electrodes of the voltage-dividing FET and the parallel composite resistance of constant voltage generating circuit, and which would cause drawbacks in the conventional structure can be easily prevented. 4. Means for monitoring the offset current (or offset voltage) can be added so as to effectively carry out the automatic stabilization of output in the load such as laser diode and the prevention of destruction of the load.

Claims: A semiconductor integrated circuit device for applying to an external load (8) connectable between an output terminal (7) and a first power supply terminal (1), a switching signal and an offset signal in superposed relation to each other, the device comprising supplying means (Q 18,19 ) for supplying the offset signal to said output terminal, and characterised by said supplying means comprising a first field effect transistor (Q₁₉) having a drain electrode connected to said output terminal (7), and a second field effect transistor (Q₁₈) having the substantially same characteristics as said first field effect transistor, said second field effect transistor having a drain electrode connected to a source electrode of said first field effect transistor, a gate electrode connected to a control terminal (6) receptive of a control signal effective to control said offset signal, and a source electrode connected to a second power supply terminal (2); and constant-voltage generating means (R₁₁,D₁₃₋₁₆) for generating and applying a constant voltage to a gate electrode of said first field effect transistor (Q₁₉), said constant-voltage generating means comprising a resistor (R₁₁) connected between said first power supply terminal and said gate electrode of the first field effect transistor, and a plurality of diodes (D₁₃₋₁₆) having the substantially same characteristics and being forwardly series-connected to each other such that an anode of said first stage diode (D₁₃) is connected to said gate electrode of said first field effect transistor and a cathode of said last stage diode (D₁₆) is connected to said second power supply terminal (2) so that the voltage drop across said series-connected diodes is set to half of a power supply voltage applied between said first and second power supply terminals (1,2), each of said diodes having an internal resistance smaller than the resistance of said resistor (R₁₁). A semiconductor integrated circuit device as claimed in Claim 1; characterised in that each of said diodes (D₁₃₋₁₆) has a forward drop voltage between said anode and cathode thereof equal to: half of the power supply voltage number of the diodes A semiconductor integrated circuit device as claimed in Claim 1, characterised in that said series-connected diodes (D₁₃₋₁₆) have a total internal resistance smaller than said resistance of said resistor (R₁₁). A semiconductor integrated circuit device as claimed in Claim 1, characterised by an additional resistor (R₁₂) connected between said source electrode of said second field effect transistor (Q₁₈) and said second power supply terminal (2) for monitoring said offset signal. A semiconductor integrated circuit device as claimed in Claim 1, characterised by a semiconductor substrate composed of GaAs and integrating thereon shottky type field effect transistors (Q₁₁₋₁₉), said resistor (R₁₁) and shottky type diodes (D₁₁₋₁₆). A semiconductor integrated circuit device as claimed in any preceding claim, wherein the switching signal is produced in response to an input frequency signal, said device comprising two switching transistors (Q₁₅,Q₁₆) connected in series between said output terminal (7) and said first power supply terminal (1) and switchable alternately to each other in response to said input frequency signal, and a current supply transistor (Q₁₇) connected between the junction point of the switching transistors (Q₁₅,Q₁₆) and the second power supply terminal (2) to supply a current such that said current is modulated by said switching transistors (Q₁₅,Q₁₆) to output said switching signal at said output terminal (7).

Inventors: HIRAYAMA HIROMITSU, HIRAYAMA, HIROMITSU
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1989
Main classification: H03K17
IPC codes: G05F3, H03K17, H01S5