An integrated circuit self-protected against reversal of the supply battery polarity

Abstract: An integrated circuit (1) self-protected agianst reversal of the supply battery (2) polarity comprises a first DMOS power transistor (T1) connected with its source electrode (S1) side to an electric load (R1) to be driven toward ground, and a second, protective DMOS transistor (T2) which is connected with its source electrode (S2) side to a positive pole (Vc) of the battery (2) and with its drain electrode (D2) side to the drain electrode (D1) of the first transistor (T1). The first T1) and second (T2) transistors have in common the drain region formed on a single pod (9) in the semiconductor substrate (4).

Description: This invention relates to an integrated circuit which is self-protected against reversal of the polarity of a supply battery. As is well known, on car assembly lines, the storage battery for the car electric system is customarily installed in each car at the end of the assembly and installation steps of the electric system and utilities connected thereto. The electric loads represented by lights, actuators, and the like items, are usually driven between a positive supply pole and ground, through an electronic control circuit. Since it may happen that the power supply cables to such electronic circuits in the system are inverted accidentally, there exists a need to install the battery without danger of damaging said integrated circuits even when the polarity is reversed. This demand also arises from the possibility of a wrong battery connection, and is intensified especially where the electric system includes power actuators for which no resistive components can be connected in the supply because such components would bring down the supply voltage on account of the voltage drop thereacross. To meet this demand, the prior art has proposed that a one-way component, specifically a diode, be connected externally between the electronic control circuit and the positive supply pole to protect said integrated circuit in the event of the battery polarity being reversed. While being advantageous cost-wise, this prior approach has drawbacks in that the voltage drop Vd across the diode brings down the voltage available to the electric load to be driven; in addition, the system efficiency deteriorates because the dissipated power is increased by an amount equal to the voltage Vd on the diode multiplied by the current I1 that flows through the load. EP-A-0349836 discloses an integrated circuit which is self-protected against reversal of the polarity of a supply battery, comprising a first MOS transistor to be connected with its source electrode side to an electric load to be driven towards ground, and a second, protective MOS transistor to be connected with its source electrode side to a pole of the battery and with its drain electrode side to the drain electrode of said first transistor. EP-A-0349836 has a priority date of 05/07/88 thus falling under the terms of Art. 54(3) of the European Patent Convention. In practical implementation of the circuit disclosed in EP-A-0349836, it is important to provide a low resistance unidirectional path to the load current, while at the same time minimizing the surface area required for integration of the circuit. This problem is solved by an integrated circuit comprising: a first DMOS power transistor to be connected with its source electrode side to an electric load to be driven toward ground; and a second, protective DMOS transistor to be connected with its source electrode side to a positive pole of the battery, and with its drain electrode side to the drain electrode of said first transistor; said first and second transistors having the drain region in common. The features and advantages of a circuit according to the invention will become more clearly apparent from the following detailed description of an emdobiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 is a wiring diagram of the integrated circuit according to the invention; Figure 2 is a side elevation cross-sectional view showing schematically the structure of the integrated circuit according to the invention; and Figures 3 and 4 are respective side elevation cross-sectional views showing schematically modified embodiments of the circuit of Figures 1 and 2. With reference to the drawing views, generally and schematically shown at 1 is a circuit which is self-protected against reversal of the polarity of a storage battery 2. The circuit 1 is expediently in the form of an integrated circuit. The circuit 1 comprises a first power transistor T1 of the DMOS type which is connected with its source electrode side to an electric load RL to drive said load toward ground. More specifically, the transistor T1 has its source S1 connected to one end of said load RL which has the other end connected to ground. The circuit 1 further comprises a second, protective transistor T2, also of the DMOS type, which is connected between a positive pole VC of the battery 2 and the first transistor T1. The source S2 of that transistor T2 is connected to said pole Vc, whereas the gate electrodes G1, G2 of the transistors T1, T2 are respectively connected to corresponding outputs of a circuit portion 3 driving the circuit 1. Advantageously, the respective drain regions D1 and D2 of the transistors T1 and T2 are shared in common and formed on a single polarity pod N (in the instance of an N-channel DMOS) in the semiconductor substrate with P polarity of that integrated structure. Each transistor includes, moreover, a corresponding intrinsic diode DT1 and DT2 which is connected in each transistor between the drain and the source and forward biased to the source. Furthermore, between the common drain D1, D2 of said transistors and the substrate there is provided a parasitic diode D forward biased to the substrate. More specifically, there is shown in the example according to Figure 2 the structure of the transistors T1 and T2 which are, in a preferred embodiment, a vertical high voltage (VDMOS) DMOS transistor and a lateral low voltage (LDMOS) DMOS transistor, interlaid with each other. It may be appreciated from Figure 2 that in a semiconductor substrate 4 slightly doped with P-type impurities, there is formed a buried layer 9 doped oppositely from the substrate, being in particular of the N+ type, which constitutes the low resistivity portion of said drain region D1-D2 shared by both of said transistors T1 and T2. Over the epitaxially grown, buried layer 9, there are formed the transistor common drain D1, D2 regions 6 and 7 being doped N- alike but with a lower dopant concentration than the buried layer 9, in which conventional zones 8 and 8a, also referred to as source cells, are formed. Thus, the circuit of this invention is formed by alternating so-called source cells 8 of a vertical DMOS transistor T1 with source cells 8a of a lateral DMOS transistor T2, the latter having a lower specific series resistance than the former. High-doped N+ regions 5, also referred to as fingers, are provided which, by connecting the N+ buried layer 9 of the vertical DMOS to the surface in the proximities of the lateral DMOS fingers, form a low resistivity path for the flow of electrons which is picked up by the LDMOS from the VDMOS. Whenever the supply voltage Vc is applied, the second transistor T2 will be in conduction and protect the integrated circuit 1 in which the power actuator T1 is connected in all those cases where the polarity of the storage battery 2 has been reversed. With the device driver in operation, a current I1 flows through the load RL, which current is supplied from the first transistor T1 via the second, protection transistor T2. If the battery polarity is reversed, the second transistor will break and protect, therefore, both the driver and the load RL. Advantageously, the voltage drop V across the second transistor can be made as small as desired by appropriate driving of the gate electrode, since that voltage is the product of the inherent resistance of the transistor T2 by the load current I1 flowing therethrough. In view of the value of that resistance being inversely proportional to the silicon surface area occupied by the second transistor in the integrated circuit 1, the resistance can be made quite small by increasing the surface area occupied by the transistor and correspondingly reducing the voltage drop thereacross as well as the dissipation of electric power. Furthermore, the combination of a vertical DMOS transistor with a lateral DMOS transistor, respectively for a high and low voltage, enables the circuit to adequately withstand both reversals of the battery polarity, which would in all cases have a low voltage value in the 12-24 Volts range, and any dumping operational conditions apt to induce voltage peaks as high as 60 Volts. A further benefit is that the circuit of this invention can maximize the performance of the transistors incorporated thereto, especially in terms of the overall resistive drop, whereby the silicon surface area required for integration can be minimized. The drain regions are formed in the same pod, and accordingly, the two transistors do not require to be isolated on separate pods and take up useful area. With specific reference to the example shown in Figure 3, a modified embodiment of the inventive circuit will now be described in which cooperating items and parts which are structured and operate similarly to the preceding embodiment are designated by the same reference numerals. This variant is particularly useful where the circuit 1 is not required to withstand dumping operational conditions. In this variant, the circuit 1 comprises a pair of interlaid low voltage lateral transistors T10 and T11 of the DMOS type. More specifically, in a semiconductor substrate 4 which is P-doped slightly, there is provided a buried layer 9 doped N+ oppositely from the substrate, which bounds, in cooperation with opposing lateral regions 12 and 13 having a higher concentration of the same P-type dopant as the substrate, a pod 14 doped N- which is adapted to form the drain region shared by both transistors T10 and T11 in common. Formed on said pod 14 are also conventional source regions 15 alternating with gates 16 as is typical of the structure of lateral DMOS transistors. IN a further modified embodiment, as shown in Figure 4, the circuit 1 may be constructed by associating a pair of lateral DMOS transistors having gate regions with several extensions which serve substantially field plate functions. Using the planos technique, in fact, the gate electrode made of polycrystalline silicon can be extended and spread over the field oxide to provide a lateral DMOS transistor adapted to withstand high voltages. Conversely, by reducing the spread of the gate electrode over the field oxide, a lateral DMOS transistor can be obtained for low voltages. Furthermore, to reduce the resistive path between adjacent sources, using the locos technique to provide the field oxide, a high-doped zone 17 of the N+ type is introduced by ion implantation which is self-aligned to the field oxide on the side of the low voltage LDMOS transistor. The circuit of the above-discussed variants operates in the same manner as the embodiment described first, to substantially bring about the same advantages.

Claims: An integrated circuit (1) which is self-protected against reversal of the polarity of a supply battery (2), characterized in that it comprises a first DMOS power transistor (T1) to be connected with its source electrode side to an electric load (RL) to be driven toward ground, and a second, protective DMOS transistor (T2) to be connected with its source electrode side to a positive pole (Vc) of the battery (2) and with its drain electrode (D2) side to the drain electrode (D1) of said first transistor (T1), said first (T1) and second (T2) transistors having the drain region (D1,D2) in common. A circuit according to Claim 1, characterized in that said first transistor (T1) is a DMOS transistor of the vertical type. A circuit according to Claim 1, characterized in that said first transistor (T1) is a high voltage lateral DMOS transistor. A circuit according to Claim 2, characterized in that said second transistor (T2) is a lateral DMOS transistor. A circuit according to Claim 4, characterized in that it comprises at least one region (17) of N+ polarity fingers between said vertical DMOS transistor (T1) and said second lateral DMOS transistor (T2) in the common drain region (14) to lower the circuit specific series resistance. A circuit according to Claim 4, characterized in that it comprises at least one N+ doped region (17) self-aligned to the field oxide on the side of said second lateral DMOS transistor (T2) to lower the circuit specific series resistance.

Inventors: CONTIERO CLAUDIO, MURARI BRUNO, CONTIERO, CLAUDIO, MURARI, BRUNO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1989
Main classification: H02H11
IPC codes: H01L27, H01L29, H01L23, H02H11, H01L21