Logarithmic amplification circuit for obtaining output voltage corresponding to difference between logarithmically amplified values of two input currents

Abstract: A logarithmic amplification circuit is provided with a first transistor 10 having its collector supplied with a first input current, a second transistor 11 having its collector supplied with a second input current and being differentially connected to the first transistor, a comparing circuit 13 for receiving the first and second input currents to supply a signal corresponding to a difference between the two input currents to a base of the second transistor, and first and second constant current circuits 21 and 25 for supplying respective collectors of the first and the second transistors with equivalent compensating current. An output voltage corresponding to a difference between a logarithmically amplified values of the first input current and a logarithmically amplified value of the second input current can be obtained.

Description: Logarithmic Amplification Circuit for Obtaining Output Voltage Corresponding to Difference between Logarithmically Amplified Values of Two Input Currents BACKGROUND OF THE INVENTION The present invention relates to a logarithmic amplifications circuit according to the preamble part of claim 1. From GB-A-21 33 597 such a logarithmic circuit is known which compensates for temperature variations by means of a pair of opposed P/N junctions. This circuit is not able to prevent generation of undesired outputs when the input current is very small or the leak current is increased. From "Elektronik", volume 35, no.18, September 1986, pages 73, 74, 76 to 78, a logarithmic amplification circuit is known the dynamic range of which is extended by means of additional amplifiers. However, also this circuit can not compensate for the problem of very small currents or increased leak currents. Fig. 2 is a circuit diagram showing one example of a conventional logarithmic amplification circuit, and is, for example, described in a Japanese publication "Practical Technique of Operational Amplifier", pp. 150, issued October 10, 1980. In the circuit of Fig. 2, an input terminal 3 is connected to a negative input end of a comparing circuit 1 through a resistor 2, and a positive input end of the comparing circuit 1 is grounded. An emitter-collector path of a transistor 5 having its base grounded is connected between the negative input end of the comparing circuit 1 and an output terminal 4. Now, if an input voltage of ei is applied to the input terminal 3, an output voltage e₀ obtained at the output terminal 4 will be as follows: wherein: q: electric charge of electron, k: Boltzmann's constant T: absolute temperature, R: resistance value of the resistor 2, I S : saturation current of P/N junction Accordingly, the circuit of Fig. 2 is able to logarithmically amplify the input voltage ei. However, the logarithmic amplification circuit of Fig. 2 had a problem in that it could not obtain an output corresponding to a difference between logarithmically amplified values of two input signals. Although a logarithmic amplification circuit for two input signals may be employed as being provided with a differential amplification circuit of two inputs-one output at a prior stage to the logarithmic amplification circuit shown in Fig. 2, such a circuit has a problem in that it leads to increase of the number of elements and deterioration of characteristics. SUMMARY OF THE INVENTION It is the object of the present invention to provide a logarythmic amplification circuit of the known kind. The dynamic range of which is extended and in which no fluctuations of the output voltage is caused even when the input current is small or the leak current is increased. This object is solved by the features of claim 1. The subclaims show preferred embodiments of the logarithmyc amplification circuit according to the invention. A main advantage of the present invention is that since compensating currents are supplied to the collectors of the first and the second transistors from the first and the second constant current circuits, even if input current becomes small or 0, or undesired current such as leak current is increased, fluctuation of an output voltage can be prevented to maintain a stable operation. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing a logarithmic amplification circuit of one embodiment of the present invention. Fig. 2 is a circuit diagram showing a conventional logarithmic amplification circuit. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a circuit diagram showing a logarithmic amplification circuit of one embodiment of the present invention. In Fig. 1, first and second input signals are respectively applied to first and second input terminals 6 and 7. The first and the second input signals are respectively converted into first and second input currents by means of first and second resistors 8 and 9. Then, the first input current is supplied to a collector of a first transistor 10, and the second input current is supplied to a collector of a second transistor 11. A collector of a constant current transistor 12 is connected to emitters of the first and the second transistors 10 and 11 connected in common. In addition, a comparing circuit 13 having its negative input end connected to the collector of the first transistor 10, its positive input end connected to the collector of the second transistor 11, and its output end connected to an output terminal 14 is provided. An output voltage obtained at the output terminal 14 is divided by means of voltage dividing resistors 15 and 16, to be applied to a base of the second transistor 11. Positive and negative input ends of the comparing circuit 13 are connected in common by means of third and fourth resistors 17 and 18, and a common node of the third and the fourth resistors 17 and 18 is connected to a gate of an FET19. The FET19 has its drain connected to a reference power supply 20, and its source connected to an emitter of the constant current transistor 12. A first constant current source 21 comprises a third transistor 22 of diode-connected type having its emitter connected to a power supply + V CC , a constant current source 23 connected to a collector of the third transistor 22, and a fourth transistor 24 connected to the third transistor 22 to form current mirror relation, and a second constant current circuit 25 comprises the third transistor 22, the constant current source 23, and a fifth transistor 26 connected to the third transistor 22 to form current mirror relation. Now, operation of a logarithmic amplification circuit of one embodiment of the present invention shown in Fig. 1 will be described. In the circuit of Fig. 1, if first and second input voltages applied to the first and the second input terminals 6 and 7 are respectively represented as V₁ and V₂, first and second input currents I₁ and I₂ will be represented as the following equations. I₁ = V₁/R₁, I₂ = V₂/R₂ wherein: R₁ and R₂ are resistance values of the first and the second resistors 8 and 9, respectively. If both output currents of the first and the second constant current circuits 21 and 25 are equivalent to each other and represented as I a , base-emitter voltages V BE1 and V BE2 of the first and the second transistors 10 and 11 will be represented as the following equations. Therefore, an output voltage V₀ obtained at the output terminal 14 will be represented as the following equations. wherein R₃ and R₄ are resistance values of voltage dividing resistors 15 and 16, respectively. Now, in the above equation (5), when both of the first and the second input currents I₁ and I₂ become 0, V₀ also becomes 0. More specifically, it can be appreciated that in the absence of input current, no output voltage is generated. In addition, in the circuit of Fig. 1, if I₂ = 0, while I₁ = I b due to existence of current caused by offset of an input voltage or leak current, the output voltage V₀ will be represented as the following equation from the above equation (5) V₀ = R₃ + R₄ R₃ · kT q ℓn I a I b + I a In this case, as long as the output current I a of the first and the second constant current circuits 21 and 25 is set so as to be I b < I a , even if inconvenient current such as leak current and the like exists, the output voltage can be held approximately 0 in the absence of an input signal. More specifically, if there are not the first and the second constant current circuits 21 and 25, as apparent from the above equation (6), the undesired current I b is increased and an undesired output voltage is generated at a higher level in the absence of an input signal. Although the value of leak current is changed depending on processing technique for integration of circuits, it is usually of approximately several hundreds pA. Accordingly, if the value of the output constant current I a of the first and the second constant current circuits 21 and 25 is set at approximately 100nA, the above bad effect of leak current is negligible. In case of the logarithmic amplification circuit of Fig. 1, the value of the output constant current I a of the first and the second constant current circuits 21 and 25 is needed to be smaller in order to maintain a enough dynamic range. Accordingly, it is necessary to set the value of the output constant current I a at an appropriate value in consideration both of a dynamic range and prevention of occurrence of undesired output voltage. The third and the fourth resistors 17 and 18 for connecting the positive and negative input ends of the comparing circuit 13 in common, and the FET19 having its gate connected to the common node of the third and the fourth resistors 17 and 18, are arranged in order to extend the dynamic range with respect to an in-phase input. More specifically, source current of the FET19 is reduced and collector current of the constant current transistor 12 is increased when the in-phase input becomes large, so that the dynamic range can be extended. As the above, according to one embodiment of the present invention, an output voltage corresponding to a difference between logarithmically amplified values of two input currents can be obtained. In addition, since compensating currents are supplied from the first and the second constant current circuits to respective collectors of the first and the second transistors, bad effects such as output fluctuation due to undesired current such as leak current and the like can be prevented. In particular, if the above value of the constant current is set at a predetermined value large enough as compared with the leak current and the like while small enough as compared with minimum operation current of the signal current, extension of the dynamic range as well as stabilization of circuits and prevention of fluctuation of output voltage becomes possible. In addition, operation current of a differential amplification circuit comprising first and second transistors is changed according to an in-phase input, the dynamic range can be further extended. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the present invention being limited only by the appended claims.

Claims: A Logarithmic amplification circuit comprising, means (6, 8) for supplying a first input current, means (7, 9) for supplying a second input current, a first transistor (10) having a collector supplied with said first input current, an emitter and a base, a second transistor (11) having a collector supplied with said second input current, an emitter and a base, said second transistor being differentially connected to said first transistor, charaterized by comparing circuit means (13) having input ends connected to respective collectors of said first and second transistors, and an output end for supplying a signal corresponding to a difference between said first and second input currents, said output end being connected to said base of said second transistor, and first and second constant current circuit means (21, 25) for supplying compensating currents equivalent to each other to said respective collectors of said first and second transistors, whereby output voltage corresponding to a difference between a logarithmically amplified value of said first input current and a logarithmically amplified value of said second input current can be obtained from said output end (14) of the comparing circuit means (13). A logarithmic amplification circuit according to claim 1, wherein said first constant current circuit means (21) comprises, a power supply (+V CC ), a third transistor (22) having an emitter connected to said power supply, a collector and a base, said collector and said base being connected in common, a constant current source (23) for supplying said third transistor with constant current, a fourth transistor (24) connected to said third transistor to form current mirror relation, and said second constant current circuit means (25) comprises, said power supply (+V CC ), said third transistor (22), said constant current source (23), a first transistor (26) connected to said third transistor to form current mirror relation. A logarithmic amplification circuit according to claim 1, wherein values of said compensating currents supplied from said first and second constant current circuit means (21, 25) are set at values larger than that of leak current, and smaller than that of minimim operation current of said first and second input currents. A logarithmic amplification circuit according to claim 1, further comprising, first and second resistors (8, 9) having resistance values (R₁, R₂) equivalent to each other, wherein said first and second resistors (8, 9) are connected to a common node through said first and second transistors (10, 11) are changed corresponding to current flowing through said common node.

Inventors: TANNO MASAYA, TANNO, MASAYA
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1989
Main classification: G06G7
IPC codes: H03G11, H03G7, G06G7